2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
43 #include <linux/sched.h>
44 #include <linux/delay.h>
45 #include <rdma/ib_user_verbs.h>
46 #include <rdma/ib_addr.h>
47 #include <rdma/ib_cache.h>
48 #include <linux/mlx5/port.h>
49 #include <linux/mlx5/vport.h>
50 #include <linux/list.h>
51 #include <rdma/ib_smi.h>
52 #include <rdma/ib_umem.h>
54 #include <linux/etherdevice.h>
55 #include <linux/mlx5/fs.h>
58 #define DRIVER_NAME "mlx5_ib"
59 #define DRIVER_VERSION "2.2-1"
60 #define DRIVER_RELDATE "Feb 2014"
62 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
63 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
64 MODULE_LICENSE("Dual BSD/GPL");
65 MODULE_VERSION(DRIVER_VERSION
);
67 static int deprecated_prof_sel
= 2;
68 module_param_named(prof_sel
, deprecated_prof_sel
, int, 0444);
69 MODULE_PARM_DESC(prof_sel
, "profile selector. Deprecated here. Moved to module mlx5_core");
71 static char mlx5_version
[] =
72 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
73 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
76 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
79 static enum rdma_link_layer
80 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
82 switch (port_type_cap
) {
83 case MLX5_CAP_PORT_TYPE_IB
:
84 return IB_LINK_LAYER_INFINIBAND
;
85 case MLX5_CAP_PORT_TYPE_ETH
:
86 return IB_LINK_LAYER_ETHERNET
;
88 return IB_LINK_LAYER_UNSPECIFIED
;
92 static enum rdma_link_layer
93 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
95 struct mlx5_ib_dev
*dev
= to_mdev(device
);
96 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
98 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
101 static int mlx5_netdev_event(struct notifier_block
*this,
102 unsigned long event
, void *ptr
)
104 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
105 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
109 case NETDEV_REGISTER
:
110 case NETDEV_UNREGISTER
:
111 write_lock(&ibdev
->roce
.netdev_lock
);
112 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
113 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ?
115 write_unlock(&ibdev
->roce
.netdev_lock
);
120 struct net_device
*lag_ndev
= mlx5_lag_get_roce_netdev(ibdev
->mdev
);
121 struct net_device
*upper
= NULL
;
124 upper
= netdev_master_upper_dev_get(lag_ndev
);
128 if ((upper
== ndev
|| (!upper
&& ndev
== ibdev
->roce
.netdev
))
129 && ibdev
->ib_active
) {
130 struct ib_event ibev
= { };
132 ibev
.device
= &ibdev
->ib_dev
;
133 ibev
.event
= (event
== NETDEV_UP
) ?
134 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
135 ibev
.element
.port_num
= 1;
136 ib_dispatch_event(&ibev
);
148 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
151 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
152 struct net_device
*ndev
;
154 ndev
= mlx5_lag_get_roce_netdev(ibdev
->mdev
);
158 /* Ensure ndev does not disappear before we invoke dev_hold()
160 read_lock(&ibdev
->roce
.netdev_lock
);
161 ndev
= ibdev
->roce
.netdev
;
164 read_unlock(&ibdev
->roce
.netdev_lock
);
169 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
170 struct ib_port_attr
*props
)
172 struct mlx5_ib_dev
*dev
= to_mdev(device
);
173 struct net_device
*ndev
, *upper
;
174 enum ib_mtu ndev_ib_mtu
;
177 memset(props
, 0, sizeof(*props
));
179 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
180 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
182 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
183 roce_address_table_size
);
184 props
->max_mtu
= IB_MTU_4096
;
185 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
186 props
->pkey_tbl_len
= 1;
187 props
->state
= IB_PORT_DOWN
;
188 props
->phys_state
= 3;
190 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
191 props
->qkey_viol_cntr
= qkey_viol_cntr
;
193 ndev
= mlx5_ib_get_netdev(device
, port_num
);
197 if (mlx5_lag_is_active(dev
->mdev
)) {
199 upper
= netdev_master_upper_dev_get_rcu(ndev
);
208 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
209 props
->state
= IB_PORT_ACTIVE
;
210 props
->phys_state
= 5;
213 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
217 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
219 props
->active_width
= IB_WIDTH_4X
; /* TODO */
220 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
225 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
226 const struct ib_gid_attr
*attr
,
229 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
230 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
232 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
238 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
240 if (is_vlan_dev(attr
->ndev
)) {
241 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
242 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
245 switch (attr
->gid_type
) {
247 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
249 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
250 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
257 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
258 if (ipv6_addr_v4mapped((void *)gid
))
259 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
260 MLX5_ROCE_L3_TYPE_IPV4
);
262 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
263 MLX5_ROCE_L3_TYPE_IPV6
);
266 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
267 !ipv6_addr_v4mapped((void *)gid
))
268 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
270 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
273 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
275 const union ib_gid
*gid
,
276 const struct ib_gid_attr
*attr
)
278 struct mlx5_ib_dev
*dev
= to_mdev(device
);
279 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)] = {0};
280 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)] = {0};
281 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
282 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
284 if (ll
!= IB_LINK_LAYER_ETHERNET
)
287 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
289 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
290 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
291 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
294 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
295 unsigned int index
, const union ib_gid
*gid
,
296 const struct ib_gid_attr
*attr
,
297 __always_unused
void **context
)
299 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
302 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
303 unsigned int index
, __always_unused
void **context
)
305 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
308 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
311 struct ib_gid_attr attr
;
314 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
322 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
325 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
328 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
330 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_IB
)
331 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
336 MLX5_VPORT_ACCESS_METHOD_MAD
,
337 MLX5_VPORT_ACCESS_METHOD_HCA
,
338 MLX5_VPORT_ACCESS_METHOD_NIC
,
341 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
343 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
344 return MLX5_VPORT_ACCESS_METHOD_MAD
;
346 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
347 IB_LINK_LAYER_ETHERNET
)
348 return MLX5_VPORT_ACCESS_METHOD_NIC
;
350 return MLX5_VPORT_ACCESS_METHOD_HCA
;
353 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
354 struct ib_device_attr
*props
)
357 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
358 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
359 u8 atomic_req_8B_endianness_mode
=
360 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
362 /* Check if HW supports 8 bytes standard atomic operations and capable
363 * of host endianness respond
365 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
366 if (((atomic_operations
& tmp
) == tmp
) &&
367 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
368 (atomic_req_8B_endianness_mode
)) {
369 props
->atomic_cap
= IB_ATOMIC_HCA
;
371 props
->atomic_cap
= IB_ATOMIC_NONE
;
375 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
376 __be64
*sys_image_guid
)
378 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
379 struct mlx5_core_dev
*mdev
= dev
->mdev
;
383 switch (mlx5_get_vport_access_method(ibdev
)) {
384 case MLX5_VPORT_ACCESS_METHOD_MAD
:
385 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
388 case MLX5_VPORT_ACCESS_METHOD_HCA
:
389 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
392 case MLX5_VPORT_ACCESS_METHOD_NIC
:
393 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
401 *sys_image_guid
= cpu_to_be64(tmp
);
407 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
410 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
411 struct mlx5_core_dev
*mdev
= dev
->mdev
;
413 switch (mlx5_get_vport_access_method(ibdev
)) {
414 case MLX5_VPORT_ACCESS_METHOD_MAD
:
415 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
417 case MLX5_VPORT_ACCESS_METHOD_HCA
:
418 case MLX5_VPORT_ACCESS_METHOD_NIC
:
419 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
428 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
431 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
433 switch (mlx5_get_vport_access_method(ibdev
)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD
:
435 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
437 case MLX5_VPORT_ACCESS_METHOD_HCA
:
438 case MLX5_VPORT_ACCESS_METHOD_NIC
:
439 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
446 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
452 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
453 case MLX5_VPORT_ACCESS_METHOD_MAD
:
454 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
456 case MLX5_VPORT_ACCESS_METHOD_HCA
:
457 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
460 case MLX5_VPORT_ACCESS_METHOD_NIC
:
461 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
469 *node_guid
= cpu_to_be64(tmp
);
474 struct mlx5_reg_node_desc
{
475 u8 desc
[IB_DEVICE_NODE_DESC_MAX
];
478 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
480 struct mlx5_reg_node_desc in
;
482 if (mlx5_use_mad_ifc(dev
))
483 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
485 memset(&in
, 0, sizeof(in
));
487 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
488 sizeof(struct mlx5_reg_node_desc
),
489 MLX5_REG_NODE_DESC
, 0, 0);
492 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
493 struct ib_device_attr
*props
,
494 struct ib_udata
*uhw
)
496 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
497 struct mlx5_core_dev
*mdev
= dev
->mdev
;
502 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
503 struct mlx5_ib_query_device_resp resp
= {};
507 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
508 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
511 resp
.response_length
= resp_len
;
513 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
516 memset(props
, 0, sizeof(*props
));
517 err
= mlx5_query_system_image_guid(ibdev
,
518 &props
->sys_image_guid
);
522 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
526 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
530 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
531 (fw_rev_min(dev
->mdev
) << 16) |
532 fw_rev_sub(dev
->mdev
);
533 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
534 IB_DEVICE_PORT_ACTIVE_EVENT
|
535 IB_DEVICE_SYS_IMAGE_GUID
|
536 IB_DEVICE_RC_RNR_NAK_GEN
;
538 if (MLX5_CAP_GEN(mdev
, pkv
))
539 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
540 if (MLX5_CAP_GEN(mdev
, qkv
))
541 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
542 if (MLX5_CAP_GEN(mdev
, apm
))
543 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
544 if (MLX5_CAP_GEN(mdev
, xrc
))
545 props
->device_cap_flags
|= IB_DEVICE_XRC
;
546 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
547 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
548 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
549 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
550 /* We support 'Gappy' memory registration too */
551 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
553 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
554 if (MLX5_CAP_GEN(mdev
, sho
)) {
555 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
556 /* At this stage no support for signature handover */
557 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
558 IB_PROT_T10DIF_TYPE_2
|
559 IB_PROT_T10DIF_TYPE_3
;
560 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
561 IB_GUARD_T10DIF_CSUM
;
563 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
564 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
566 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
)) {
567 if (MLX5_CAP_ETH(mdev
, csum_cap
))
568 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
570 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
571 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
573 resp
.tso_caps
.max_tso
= 1 << max_tso
;
574 resp
.tso_caps
.supported_qpts
|=
575 1 << IB_QPT_RAW_PACKET
;
576 resp
.response_length
+= sizeof(resp
.tso_caps
);
580 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
)) {
581 resp
.rss_caps
.rx_hash_function
=
582 MLX5_RX_HASH_FUNC_TOEPLITZ
;
583 resp
.rss_caps
.rx_hash_fields_mask
=
584 MLX5_RX_HASH_SRC_IPV4
|
585 MLX5_RX_HASH_DST_IPV4
|
586 MLX5_RX_HASH_SRC_IPV6
|
587 MLX5_RX_HASH_DST_IPV6
|
588 MLX5_RX_HASH_SRC_PORT_TCP
|
589 MLX5_RX_HASH_DST_PORT_TCP
|
590 MLX5_RX_HASH_SRC_PORT_UDP
|
591 MLX5_RX_HASH_DST_PORT_UDP
;
592 resp
.response_length
+= sizeof(resp
.rss_caps
);
595 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
))
596 resp
.response_length
+= sizeof(resp
.tso_caps
);
597 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
))
598 resp
.response_length
+= sizeof(resp
.rss_caps
);
601 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
602 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
603 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
606 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
607 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
))
608 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
610 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
611 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
613 props
->vendor_part_id
= mdev
->pdev
->device
;
614 props
->hw_ver
= mdev
->pdev
->revision
;
616 props
->max_mr_size
= ~0ull;
617 props
->page_size_cap
= ~(min_page_size
- 1);
618 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
619 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
620 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
621 sizeof(struct mlx5_wqe_data_seg
);
622 max_sq_desc
= min_t(int, MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
), 512);
623 max_sq_sg
= (max_sq_desc
- sizeof(struct mlx5_wqe_ctrl_seg
) -
624 sizeof(struct mlx5_wqe_raddr_seg
)) /
625 sizeof(struct mlx5_wqe_data_seg
);
626 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
627 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
628 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
629 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
630 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
631 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
632 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
633 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
634 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
635 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
636 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
637 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
638 props
->max_srq_sge
= max_rq_sg
- 1;
639 props
->max_fast_reg_page_list_len
=
640 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
641 get_atomic_caps(dev
, props
);
642 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
643 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
644 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
645 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
646 props
->max_mcast_grp
;
647 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
648 props
->max_ah
= INT_MAX
;
649 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
650 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
652 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
653 if (MLX5_CAP_GEN(mdev
, pg
))
654 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
655 props
->odp_caps
= dev
->odp_caps
;
658 if (MLX5_CAP_GEN(mdev
, cd
))
659 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
661 if (!mlx5_core_is_pf(mdev
))
662 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
664 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
665 IB_LINK_LAYER_ETHERNET
) {
666 props
->rss_caps
.max_rwq_indirection_tables
=
667 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt
);
668 props
->rss_caps
.max_rwq_indirection_table_size
=
669 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
);
670 props
->rss_caps
.supported_qpts
= 1 << IB_QPT_RAW_PACKET
;
671 props
->max_wq_type_rq
=
672 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rq
);
675 if (field_avail(typeof(resp
), cqe_comp_caps
, uhw
->outlen
)) {
676 resp
.cqe_comp_caps
.max_num
=
677 MLX5_CAP_GEN(dev
->mdev
, cqe_compression
) ?
678 MLX5_CAP_GEN(dev
->mdev
, cqe_compression_max_num
) : 0;
679 resp
.cqe_comp_caps
.supported_format
=
680 MLX5_IB_CQE_RES_FORMAT_HASH
|
681 MLX5_IB_CQE_RES_FORMAT_CSUM
;
682 resp
.response_length
+= sizeof(resp
.cqe_comp_caps
);
685 if (field_avail(typeof(resp
), packet_pacing_caps
, uhw
->outlen
)) {
686 if (MLX5_CAP_QOS(mdev
, packet_pacing
) &&
687 MLX5_CAP_GEN(mdev
, qos
)) {
688 resp
.packet_pacing_caps
.qp_rate_limit_max
=
689 MLX5_CAP_QOS(mdev
, packet_pacing_max_rate
);
690 resp
.packet_pacing_caps
.qp_rate_limit_min
=
691 MLX5_CAP_QOS(mdev
, packet_pacing_min_rate
);
692 resp
.packet_pacing_caps
.supported_qpts
|=
693 1 << IB_QPT_RAW_PACKET
;
695 resp
.response_length
+= sizeof(resp
.packet_pacing_caps
);
698 if (field_avail(typeof(resp
), mlx5_ib_support_multi_pkt_send_wqes
,
700 resp
.mlx5_ib_support_multi_pkt_send_wqes
=
701 MLX5_CAP_ETH(mdev
, multi_pkt_send_wqe
);
702 resp
.response_length
+=
703 sizeof(resp
.mlx5_ib_support_multi_pkt_send_wqes
);
706 if (field_avail(typeof(resp
), reserved
, uhw
->outlen
))
707 resp
.response_length
+= sizeof(resp
.reserved
);
710 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
720 MLX5_IB_WIDTH_1X
= 1 << 0,
721 MLX5_IB_WIDTH_2X
= 1 << 1,
722 MLX5_IB_WIDTH_4X
= 1 << 2,
723 MLX5_IB_WIDTH_8X
= 1 << 3,
724 MLX5_IB_WIDTH_12X
= 1 << 4
727 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
730 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
733 if (active_width
& MLX5_IB_WIDTH_1X
) {
734 *ib_width
= IB_WIDTH_1X
;
735 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
736 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
739 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
740 *ib_width
= IB_WIDTH_4X
;
741 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
742 *ib_width
= IB_WIDTH_8X
;
743 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
744 *ib_width
= IB_WIDTH_12X
;
746 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
754 static int mlx5_mtu_to_ib_mtu(int mtu
)
763 pr_warn("invalid mtu\n");
773 __IB_MAX_VL_0_14
= 5,
776 enum mlx5_vl_hw_cap
{
788 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
793 *max_vl_num
= __IB_MAX_VL_0
;
796 *max_vl_num
= __IB_MAX_VL_0_1
;
799 *max_vl_num
= __IB_MAX_VL_0_3
;
802 *max_vl_num
= __IB_MAX_VL_0_7
;
804 case MLX5_VL_HW_0_14
:
805 *max_vl_num
= __IB_MAX_VL_0_14
;
815 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
816 struct ib_port_attr
*props
)
818 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
819 struct mlx5_core_dev
*mdev
= dev
->mdev
;
820 struct mlx5_hca_vport_context
*rep
;
824 u8 ib_link_width_oper
;
827 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
833 memset(props
, 0, sizeof(*props
));
835 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
839 props
->lid
= rep
->lid
;
840 props
->lmc
= rep
->lmc
;
841 props
->sm_lid
= rep
->sm_lid
;
842 props
->sm_sl
= rep
->sm_sl
;
843 props
->state
= rep
->vport_state
;
844 props
->phys_state
= rep
->port_physical_state
;
845 props
->port_cap_flags
= rep
->cap_mask1
;
846 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
847 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
848 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
849 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
850 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
851 props
->subnet_timeout
= rep
->subnet_timeout
;
852 props
->init_type_reply
= rep
->init_type_reply
;
853 props
->grh_required
= rep
->grh_required
;
855 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
859 err
= translate_active_width(ibdev
, ib_link_width_oper
,
860 &props
->active_width
);
863 err
= mlx5_query_port_ib_proto_oper(mdev
, &props
->active_speed
, port
);
867 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
869 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
871 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
873 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
875 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
879 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
886 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
887 struct ib_port_attr
*props
)
889 switch (mlx5_get_vport_access_method(ibdev
)) {
890 case MLX5_VPORT_ACCESS_METHOD_MAD
:
891 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
893 case MLX5_VPORT_ACCESS_METHOD_HCA
:
894 return mlx5_query_hca_port(ibdev
, port
, props
);
896 case MLX5_VPORT_ACCESS_METHOD_NIC
:
897 return mlx5_query_port_roce(ibdev
, port
, props
);
904 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
907 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
908 struct mlx5_core_dev
*mdev
= dev
->mdev
;
910 switch (mlx5_get_vport_access_method(ibdev
)) {
911 case MLX5_VPORT_ACCESS_METHOD_MAD
:
912 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
914 case MLX5_VPORT_ACCESS_METHOD_HCA
:
915 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
923 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
926 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
927 struct mlx5_core_dev
*mdev
= dev
->mdev
;
929 switch (mlx5_get_vport_access_method(ibdev
)) {
930 case MLX5_VPORT_ACCESS_METHOD_MAD
:
931 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
933 case MLX5_VPORT_ACCESS_METHOD_HCA
:
934 case MLX5_VPORT_ACCESS_METHOD_NIC
:
935 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
942 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
943 struct ib_device_modify
*props
)
945 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
946 struct mlx5_reg_node_desc in
;
947 struct mlx5_reg_node_desc out
;
950 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
953 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
957 * If possible, pass node desc to FW, so it can generate
958 * a 144 trap. If cmd fails, just ignore.
960 memcpy(&in
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
961 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
962 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
966 memcpy(ibdev
->node_desc
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
971 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
972 struct ib_port_modify
*props
)
974 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
975 struct ib_port_attr attr
;
979 mutex_lock(&dev
->cap_mask_mutex
);
981 err
= mlx5_ib_query_port(ibdev
, port
, &attr
);
985 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
986 ~props
->clr_port_cap_mask
;
988 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
991 mutex_unlock(&dev
->cap_mask_mutex
);
995 static void print_lib_caps(struct mlx5_ib_dev
*dev
, u64 caps
)
997 mlx5_ib_dbg(dev
, "MLX5_LIB_CAP_4K_UAR = %s\n",
998 caps
& MLX5_LIB_CAP_4K_UAR
? "y" : "n");
1001 static int calc_total_bfregs(struct mlx5_ib_dev
*dev
, bool lib_uar_4k
,
1002 struct mlx5_ib_alloc_ucontext_req_v2
*req
,
1005 int uars_per_sys_page
;
1006 int bfregs_per_sys_page
;
1007 int ref_bfregs
= req
->total_num_bfregs
;
1009 if (req
->total_num_bfregs
== 0)
1012 BUILD_BUG_ON(MLX5_MAX_BFREGS
% MLX5_NON_FP_BFREGS_IN_PAGE
);
1013 BUILD_BUG_ON(MLX5_MAX_BFREGS
< MLX5_NON_FP_BFREGS_IN_PAGE
);
1015 if (req
->total_num_bfregs
> MLX5_MAX_BFREGS
)
1018 uars_per_sys_page
= get_uars_per_sys_page(dev
, lib_uar_4k
);
1019 bfregs_per_sys_page
= uars_per_sys_page
* MLX5_NON_FP_BFREGS_PER_UAR
;
1020 req
->total_num_bfregs
= ALIGN(req
->total_num_bfregs
, bfregs_per_sys_page
);
1021 *num_sys_pages
= req
->total_num_bfregs
/ bfregs_per_sys_page
;
1023 if (req
->num_low_latency_bfregs
> req
->total_num_bfregs
- 1)
1026 mlx5_ib_dbg(dev
, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1027 MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? "yes" : "no",
1028 lib_uar_4k
? "yes" : "no", ref_bfregs
,
1029 req
->total_num_bfregs
, *num_sys_pages
);
1034 static int allocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1036 struct mlx5_bfreg_info
*bfregi
;
1040 bfregi
= &context
->bfregi
;
1041 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++) {
1042 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &bfregi
->sys_pages
[i
]);
1046 mlx5_ib_dbg(dev
, "allocated uar %d\n", bfregi
->sys_pages
[i
]);
1051 for (--i
; i
>= 0; i
--)
1052 if (mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]))
1053 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1058 static int deallocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1060 struct mlx5_bfreg_info
*bfregi
;
1064 bfregi
= &context
->bfregi
;
1065 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++) {
1066 err
= mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]);
1068 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1075 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
1076 struct ib_udata
*udata
)
1078 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1079 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
1080 struct mlx5_ib_alloc_ucontext_resp resp
= {};
1081 struct mlx5_ib_ucontext
*context
;
1082 struct mlx5_bfreg_info
*bfregi
;
1086 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
1090 if (!dev
->ib_active
)
1091 return ERR_PTR(-EAGAIN
);
1093 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
1094 return ERR_PTR(-EINVAL
);
1096 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
1097 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
1099 else if (reqlen
>= min_req_v2
)
1102 return ERR_PTR(-EINVAL
);
1104 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
1106 return ERR_PTR(err
);
1109 return ERR_PTR(-EINVAL
);
1111 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
1112 return ERR_PTR(-EOPNOTSUPP
);
1114 req
.total_num_bfregs
= ALIGN(req
.total_num_bfregs
,
1115 MLX5_NON_FP_BFREGS_PER_UAR
);
1116 if (req
.num_low_latency_bfregs
> req
.total_num_bfregs
- 1)
1117 return ERR_PTR(-EINVAL
);
1119 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
1120 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
1121 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
1122 resp
.cache_line_size
= cache_line_size();
1123 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
1124 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
1125 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1126 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1127 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
1128 resp
.cqe_version
= min_t(__u8
,
1129 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
1130 req
.max_cqe_version
);
1131 resp
.log_uar_size
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1132 MLX5_ADAPTER_PAGE_SHIFT
: PAGE_SHIFT
;
1133 resp
.num_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1134 MLX5_CAP_GEN(dev
->mdev
, num_of_uars_per_page
) : 1;
1135 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
1136 sizeof(resp
.response_length
), udata
->outlen
);
1138 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
1140 return ERR_PTR(-ENOMEM
);
1142 lib_uar_4k
= req
.lib_caps
& MLX5_LIB_CAP_4K_UAR
;
1143 bfregi
= &context
->bfregi
;
1145 /* updates req->total_num_bfregs */
1146 err
= calc_total_bfregs(dev
, lib_uar_4k
, &req
, &bfregi
->num_sys_pages
);
1150 mutex_init(&bfregi
->lock
);
1151 bfregi
->lib_uar_4k
= lib_uar_4k
;
1152 bfregi
->count
= kcalloc(req
.total_num_bfregs
, sizeof(*bfregi
->count
),
1154 if (!bfregi
->count
) {
1159 bfregi
->sys_pages
= kcalloc(bfregi
->num_sys_pages
,
1160 sizeof(*bfregi
->sys_pages
),
1162 if (!bfregi
->sys_pages
) {
1167 err
= allocate_uars(dev
, context
);
1171 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1172 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
1175 context
->upd_xlt_page
= __get_free_page(GFP_KERNEL
);
1176 if (!context
->upd_xlt_page
) {
1180 mutex_init(&context
->upd_xlt_page_mutex
);
1182 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
1183 err
= mlx5_core_alloc_transport_domain(dev
->mdev
,
1189 INIT_LIST_HEAD(&context
->vma_private_list
);
1190 INIT_LIST_HEAD(&context
->db_page_list
);
1191 mutex_init(&context
->db_page_mutex
);
1193 resp
.tot_bfregs
= req
.total_num_bfregs
;
1194 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
1196 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1197 resp
.response_length
+= sizeof(resp
.cqe_version
);
1199 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1200 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
|
1201 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH
;
1202 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1206 * We don't want to expose information from the PCI bar that is located
1207 * after 4096 bytes, so if the arch only supports larger pages, let's
1208 * pretend we don't support reading the HCA's core clock. This is also
1209 * forced by mmap function.
1211 if (field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1212 if (PAGE_SIZE
<= 4096) {
1214 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1215 resp
.hca_core_clock_offset
=
1216 offsetof(struct mlx5_init_seg
, internal_timer_h
) % PAGE_SIZE
;
1218 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
1219 sizeof(resp
.reserved2
);
1222 if (field_avail(typeof(resp
), log_uar_size
, udata
->outlen
))
1223 resp
.response_length
+= sizeof(resp
.log_uar_size
);
1225 if (field_avail(typeof(resp
), num_uars_per_page
, udata
->outlen
))
1226 resp
.response_length
+= sizeof(resp
.num_uars_per_page
);
1228 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1233 bfregi
->num_low_latency_bfregs
= req
.num_low_latency_bfregs
;
1234 context
->cqe_version
= resp
.cqe_version
;
1235 context
->lib_caps
= req
.lib_caps
;
1236 print_lib_caps(dev
, context
->lib_caps
);
1238 return &context
->ibucontext
;
1241 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1242 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1245 free_page(context
->upd_xlt_page
);
1248 deallocate_uars(dev
, context
);
1251 kfree(bfregi
->sys_pages
);
1254 kfree(bfregi
->count
);
1259 return ERR_PTR(err
);
1262 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1264 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1265 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1266 struct mlx5_bfreg_info
*bfregi
;
1268 bfregi
= &context
->bfregi
;
1269 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1270 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1272 free_page(context
->upd_xlt_page
);
1273 deallocate_uars(dev
, context
);
1274 kfree(bfregi
->sys_pages
);
1275 kfree(bfregi
->count
);
1281 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
,
1282 struct mlx5_bfreg_info
*bfregi
,
1285 int fw_uars_per_page
;
1287 fw_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? MLX5_UARS_IN_PAGE
: 1;
1289 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) +
1290 bfregi
->sys_pages
[idx
] / fw_uars_per_page
;
1293 static int get_command(unsigned long offset
)
1295 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1298 static int get_arg(unsigned long offset
)
1300 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1303 static int get_index(unsigned long offset
)
1305 return get_arg(offset
);
1308 static void mlx5_ib_vma_open(struct vm_area_struct
*area
)
1310 /* vma_open is called when a new VMA is created on top of our VMA. This
1311 * is done through either mremap flow or split_vma (usually due to
1312 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1313 * as this VMA is strongly hardware related. Therefore we set the
1314 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1315 * calling us again and trying to do incorrect actions. We assume that
1316 * the original VMA size is exactly a single page, and therefore all
1317 * "splitting" operation will not happen to it.
1319 area
->vm_ops
= NULL
;
1322 static void mlx5_ib_vma_close(struct vm_area_struct
*area
)
1324 struct mlx5_ib_vma_private_data
*mlx5_ib_vma_priv_data
;
1326 /* It's guaranteed that all VMAs opened on a FD are closed before the
1327 * file itself is closed, therefore no sync is needed with the regular
1328 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1329 * However need a sync with accessing the vma as part of
1330 * mlx5_ib_disassociate_ucontext.
1331 * The close operation is usually called under mm->mmap_sem except when
1332 * process is exiting.
1333 * The exiting case is handled explicitly as part of
1334 * mlx5_ib_disassociate_ucontext.
1336 mlx5_ib_vma_priv_data
= (struct mlx5_ib_vma_private_data
*)area
->vm_private_data
;
1338 /* setting the vma context pointer to null in the mlx5_ib driver's
1339 * private data, to protect a race condition in
1340 * mlx5_ib_disassociate_ucontext().
1342 mlx5_ib_vma_priv_data
->vma
= NULL
;
1343 list_del(&mlx5_ib_vma_priv_data
->list
);
1344 kfree(mlx5_ib_vma_priv_data
);
1347 static const struct vm_operations_struct mlx5_ib_vm_ops
= {
1348 .open
= mlx5_ib_vma_open
,
1349 .close
= mlx5_ib_vma_close
1352 static int mlx5_ib_set_vma_data(struct vm_area_struct
*vma
,
1353 struct mlx5_ib_ucontext
*ctx
)
1355 struct mlx5_ib_vma_private_data
*vma_prv
;
1356 struct list_head
*vma_head
= &ctx
->vma_private_list
;
1358 vma_prv
= kzalloc(sizeof(*vma_prv
), GFP_KERNEL
);
1363 vma
->vm_private_data
= vma_prv
;
1364 vma
->vm_ops
= &mlx5_ib_vm_ops
;
1366 list_add(&vma_prv
->list
, vma_head
);
1371 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
1374 struct vm_area_struct
*vma
;
1375 struct mlx5_ib_vma_private_data
*vma_private
, *n
;
1376 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1377 struct task_struct
*owning_process
= NULL
;
1378 struct mm_struct
*owning_mm
= NULL
;
1380 owning_process
= get_pid_task(ibcontext
->tgid
, PIDTYPE_PID
);
1381 if (!owning_process
)
1384 owning_mm
= get_task_mm(owning_process
);
1386 pr_info("no mm, disassociate ucontext is pending task termination\n");
1388 put_task_struct(owning_process
);
1389 usleep_range(1000, 2000);
1390 owning_process
= get_pid_task(ibcontext
->tgid
,
1392 if (!owning_process
||
1393 owning_process
->state
== TASK_DEAD
) {
1394 pr_info("disassociate ucontext done, task was terminated\n");
1395 /* in case task was dead need to release the
1399 put_task_struct(owning_process
);
1405 /* need to protect from a race on closing the vma as part of
1406 * mlx5_ib_vma_close.
1408 down_read(&owning_mm
->mmap_sem
);
1409 list_for_each_entry_safe(vma_private
, n
, &context
->vma_private_list
,
1411 vma
= vma_private
->vma
;
1412 ret
= zap_vma_ptes(vma
, vma
->vm_start
,
1414 WARN_ONCE(ret
, "%s: zap_vma_ptes failed", __func__
);
1415 /* context going to be destroyed, should
1416 * not access ops any more.
1419 list_del(&vma_private
->list
);
1422 up_read(&owning_mm
->mmap_sem
);
1424 put_task_struct(owning_process
);
1427 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1430 case MLX5_IB_MMAP_WC_PAGE
:
1432 case MLX5_IB_MMAP_REGULAR_PAGE
:
1433 return "best effort WC";
1434 case MLX5_IB_MMAP_NC_PAGE
:
1441 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
1442 struct vm_area_struct
*vma
,
1443 struct mlx5_ib_ucontext
*context
)
1445 struct mlx5_bfreg_info
*bfregi
= &context
->bfregi
;
1448 phys_addr_t pfn
, pa
;
1452 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1455 uars_per_page
= get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
);
1456 idx
= get_index(vma
->vm_pgoff
);
1457 if (idx
% uars_per_page
||
1458 idx
* uars_per_page
>= bfregi
->num_sys_pages
) {
1459 mlx5_ib_warn(dev
, "invalid uar index %lu\n", idx
);
1464 case MLX5_IB_MMAP_WC_PAGE
:
1465 /* Some architectures don't support WC memory */
1466 #if defined(CONFIG_X86)
1469 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1473 case MLX5_IB_MMAP_REGULAR_PAGE
:
1474 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1475 prot
= pgprot_writecombine(vma
->vm_page_prot
);
1477 case MLX5_IB_MMAP_NC_PAGE
:
1478 prot
= pgprot_noncached(vma
->vm_page_prot
);
1484 pfn
= uar_index2pfn(dev
, bfregi
, idx
);
1485 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
1487 vma
->vm_page_prot
= prot
;
1488 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1489 PAGE_SIZE
, vma
->vm_page_prot
);
1491 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1492 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
1496 pa
= pfn
<< PAGE_SHIFT
;
1497 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
1498 vma
->vm_start
, &pa
);
1500 return mlx5_ib_set_vma_data(vma
, context
);
1503 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1505 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1506 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1507 unsigned long command
;
1510 command
= get_command(vma
->vm_pgoff
);
1512 case MLX5_IB_MMAP_WC_PAGE
:
1513 case MLX5_IB_MMAP_NC_PAGE
:
1514 case MLX5_IB_MMAP_REGULAR_PAGE
:
1515 return uar_mmap(dev
, command
, vma
, context
);
1517 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1520 case MLX5_IB_MMAP_CORE_CLOCK
:
1521 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1524 if (vma
->vm_flags
& VM_WRITE
)
1527 /* Don't expose to user-space information it shouldn't have */
1528 if (PAGE_SIZE
> 4096)
1531 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1532 pfn
= (dev
->mdev
->iseg_base
+
1533 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1535 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1536 PAGE_SIZE
, vma
->vm_page_prot
))
1539 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1541 (unsigned long long)pfn
<< PAGE_SHIFT
);
1551 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1552 struct ib_ucontext
*context
,
1553 struct ib_udata
*udata
)
1555 struct mlx5_ib_alloc_pd_resp resp
;
1556 struct mlx5_ib_pd
*pd
;
1559 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1561 return ERR_PTR(-ENOMEM
);
1563 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1566 return ERR_PTR(err
);
1571 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1572 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1574 return ERR_PTR(-EFAULT
);
1581 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1583 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1584 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1586 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1593 MATCH_CRITERIA_ENABLE_OUTER_BIT
,
1594 MATCH_CRITERIA_ENABLE_MISC_BIT
,
1595 MATCH_CRITERIA_ENABLE_INNER_BIT
1598 #define HEADER_IS_ZERO(match_criteria, headers) \
1599 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1600 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1602 static u8 get_match_criteria_enable(u32 *match_criteria)
1604 u8 match_criteria_enable
;
1606 match_criteria_enable
=
1607 (!HEADER_IS_ZERO(match_criteria
, outer_headers
)) <<
1608 MATCH_CRITERIA_ENABLE_OUTER_BIT
;
1609 match_criteria_enable
|=
1610 (!HEADER_IS_ZERO(match_criteria
, misc_parameters
)) <<
1611 MATCH_CRITERIA_ENABLE_MISC_BIT
;
1612 match_criteria_enable
|=
1613 (!HEADER_IS_ZERO(match_criteria
, inner_headers
)) <<
1614 MATCH_CRITERIA_ENABLE_INNER_BIT
;
1616 return match_criteria_enable
;
1619 static void set_proto(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
1621 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_protocol
, mask
);
1622 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_protocol
, val
);
1625 static void set_flow_label(void *misc_c
, void *misc_v
, u8 mask
, u8 val
,
1629 MLX5_SET(fte_match_set_misc
,
1630 misc_c
, inner_ipv6_flow_label
, mask
);
1631 MLX5_SET(fte_match_set_misc
,
1632 misc_v
, inner_ipv6_flow_label
, val
);
1634 MLX5_SET(fte_match_set_misc
,
1635 misc_c
, outer_ipv6_flow_label
, mask
);
1636 MLX5_SET(fte_match_set_misc
,
1637 misc_v
, outer_ipv6_flow_label
, val
);
1641 static void set_tos(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
1643 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_ecn
, mask
);
1644 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_ecn
, val
);
1645 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_dscp
, mask
>> 2);
1646 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_dscp
, val
>> 2);
1649 #define LAST_ETH_FIELD vlan_tag
1650 #define LAST_IB_FIELD sl
1651 #define LAST_IPV4_FIELD tos
1652 #define LAST_IPV6_FIELD traffic_class
1653 #define LAST_TCP_UDP_FIELD src_port
1654 #define LAST_TUNNEL_FIELD tunnel_id
1656 /* Field is the last supported field */
1657 #define FIELDS_NOT_SUPPORTED(filter, field)\
1658 memchr_inv((void *)&filter.field +\
1659 sizeof(filter.field), 0,\
1661 offsetof(typeof(filter), field) -\
1662 sizeof(filter.field))
1664 static int parse_flow_attr(u32
*match_c
, u32
*match_v
,
1665 const union ib_flow_spec
*ib_spec
)
1667 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1669 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1674 if (ib_spec
->type
& IB_FLOW_SPEC_INNER
) {
1675 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1677 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1680 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1682 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1686 switch (ib_spec
->type
& ~IB_FLOW_SPEC_INNER
) {
1687 case IB_FLOW_SPEC_ETH
:
1688 if (FIELDS_NOT_SUPPORTED(ib_spec
->eth
.mask
, LAST_ETH_FIELD
))
1691 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1693 ib_spec
->eth
.mask
.dst_mac
);
1694 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1696 ib_spec
->eth
.val
.dst_mac
);
1698 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1700 ib_spec
->eth
.mask
.src_mac
);
1701 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1703 ib_spec
->eth
.val
.src_mac
);
1705 if (ib_spec
->eth
.mask
.vlan_tag
) {
1706 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1708 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1711 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1712 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
1713 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1714 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
1716 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1718 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
1719 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1721 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
1723 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1725 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
1726 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1728 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
1730 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1731 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
1732 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1733 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
1735 case IB_FLOW_SPEC_IPV4
:
1736 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv4
.mask
, LAST_IPV4_FIELD
))
1739 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1741 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1742 ethertype
, ETH_P_IP
);
1744 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1745 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1746 &ib_spec
->ipv4
.mask
.src_ip
,
1747 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
1748 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1749 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1750 &ib_spec
->ipv4
.val
.src_ip
,
1751 sizeof(ib_spec
->ipv4
.val
.src_ip
));
1752 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1753 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1754 &ib_spec
->ipv4
.mask
.dst_ip
,
1755 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
1756 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1757 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1758 &ib_spec
->ipv4
.val
.dst_ip
,
1759 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
1761 set_tos(headers_c
, headers_v
,
1762 ib_spec
->ipv4
.mask
.tos
, ib_spec
->ipv4
.val
.tos
);
1764 set_proto(headers_c
, headers_v
,
1765 ib_spec
->ipv4
.mask
.proto
, ib_spec
->ipv4
.val
.proto
);
1767 case IB_FLOW_SPEC_IPV6
:
1768 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv6
.mask
, LAST_IPV6_FIELD
))
1771 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1773 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1774 ethertype
, ETH_P_IPV6
);
1776 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1777 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1778 &ib_spec
->ipv6
.mask
.src_ip
,
1779 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
1780 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1781 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1782 &ib_spec
->ipv6
.val
.src_ip
,
1783 sizeof(ib_spec
->ipv6
.val
.src_ip
));
1784 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1785 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1786 &ib_spec
->ipv6
.mask
.dst_ip
,
1787 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
1788 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1789 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1790 &ib_spec
->ipv6
.val
.dst_ip
,
1791 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
1793 set_tos(headers_c
, headers_v
,
1794 ib_spec
->ipv6
.mask
.traffic_class
,
1795 ib_spec
->ipv6
.val
.traffic_class
);
1797 set_proto(headers_c
, headers_v
,
1798 ib_spec
->ipv6
.mask
.next_hdr
,
1799 ib_spec
->ipv6
.val
.next_hdr
);
1801 set_flow_label(misc_params_c
, misc_params_v
,
1802 ntohl(ib_spec
->ipv6
.mask
.flow_label
),
1803 ntohl(ib_spec
->ipv6
.val
.flow_label
),
1804 ib_spec
->type
& IB_FLOW_SPEC_INNER
);
1807 case IB_FLOW_SPEC_TCP
:
1808 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
1809 LAST_TCP_UDP_FIELD
))
1812 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
1814 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
1817 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_sport
,
1818 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1819 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_sport
,
1820 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1822 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_dport
,
1823 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1824 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_dport
,
1825 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1827 case IB_FLOW_SPEC_UDP
:
1828 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
1829 LAST_TCP_UDP_FIELD
))
1832 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
1834 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
1837 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_sport
,
1838 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1839 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_sport
,
1840 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1842 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_dport
,
1843 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1844 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_dport
,
1845 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1847 case IB_FLOW_SPEC_VXLAN_TUNNEL
:
1848 if (FIELDS_NOT_SUPPORTED(ib_spec
->tunnel
.mask
,
1852 MLX5_SET(fte_match_set_misc
, misc_params_c
, vxlan_vni
,
1853 ntohl(ib_spec
->tunnel
.mask
.tunnel_id
));
1854 MLX5_SET(fte_match_set_misc
, misc_params_v
, vxlan_vni
,
1855 ntohl(ib_spec
->tunnel
.val
.tunnel_id
));
1864 /* If a flow could catch both multicast and unicast packets,
1865 * it won't fall into the multicast flow steering table and this rule
1866 * could steal other multicast packets.
1868 static bool flow_is_multicast_only(struct ib_flow_attr
*ib_attr
)
1870 struct ib_flow_spec_eth
*eth_spec
;
1872 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
1873 ib_attr
->size
< sizeof(struct ib_flow_attr
) +
1874 sizeof(struct ib_flow_spec_eth
) ||
1875 ib_attr
->num_of_specs
< 1)
1878 eth_spec
= (struct ib_flow_spec_eth
*)(ib_attr
+ 1);
1879 if (eth_spec
->type
!= IB_FLOW_SPEC_ETH
||
1880 eth_spec
->size
!= sizeof(*eth_spec
))
1883 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
1884 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
1887 static bool is_valid_attr(const struct ib_flow_attr
*flow_attr
)
1889 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
1890 bool has_ipv4_spec
= false;
1891 bool eth_type_ipv4
= true;
1892 unsigned int spec_index
;
1894 /* Validate that ethertype is correct */
1895 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1896 if (ib_spec
->type
== IB_FLOW_SPEC_ETH
&&
1897 ib_spec
->eth
.mask
.ether_type
) {
1898 if (!((ib_spec
->eth
.mask
.ether_type
== htons(0xffff)) &&
1899 ib_spec
->eth
.val
.ether_type
== htons(ETH_P_IP
)))
1900 eth_type_ipv4
= false;
1901 } else if (ib_spec
->type
== IB_FLOW_SPEC_IPV4
) {
1902 has_ipv4_spec
= true;
1904 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
1906 return !has_ipv4_spec
|| eth_type_ipv4
;
1909 static void put_flow_table(struct mlx5_ib_dev
*dev
,
1910 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
1912 prio
->refcount
-= !!ft_added
;
1913 if (!prio
->refcount
) {
1914 mlx5_destroy_flow_table(prio
->flow_table
);
1915 prio
->flow_table
= NULL
;
1919 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
1921 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
1922 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
1923 struct mlx5_ib_flow_handler
,
1925 struct mlx5_ib_flow_handler
*iter
, *tmp
;
1927 mutex_lock(&dev
->flow_db
.lock
);
1929 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
1930 mlx5_del_flow_rules(iter
->rule
);
1931 put_flow_table(dev
, iter
->prio
, true);
1932 list_del(&iter
->list
);
1936 mlx5_del_flow_rules(handler
->rule
);
1937 put_flow_table(dev
, handler
->prio
, true);
1938 mutex_unlock(&dev
->flow_db
.lock
);
1945 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
1953 enum flow_table_type
{
1958 #define MLX5_FS_MAX_TYPES 10
1959 #define MLX5_FS_MAX_ENTRIES 32000UL
1960 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
1961 struct ib_flow_attr
*flow_attr
,
1962 enum flow_table_type ft_type
)
1964 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
1965 struct mlx5_flow_namespace
*ns
= NULL
;
1966 struct mlx5_ib_flow_prio
*prio
;
1967 struct mlx5_flow_table
*ft
;
1973 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
1974 if (flow_is_multicast_only(flow_attr
) &&
1976 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
1978 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
1980 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1981 MLX5_FLOW_NAMESPACE_BYPASS
);
1982 num_entries
= MLX5_FS_MAX_ENTRIES
;
1983 num_groups
= MLX5_FS_MAX_TYPES
;
1984 prio
= &dev
->flow_db
.prios
[priority
];
1985 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
1986 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
1987 ns
= mlx5_get_flow_namespace(dev
->mdev
,
1988 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
1989 build_leftovers_ft_param(&priority
,
1992 prio
= &dev
->flow_db
.prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
1993 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
1994 if (!MLX5_CAP_FLOWTABLE(dev
->mdev
,
1995 allow_sniffer_and_nic_rx_shared_tir
))
1996 return ERR_PTR(-ENOTSUPP
);
1998 ns
= mlx5_get_flow_namespace(dev
->mdev
, ft_type
== MLX5_IB_FT_RX
?
1999 MLX5_FLOW_NAMESPACE_SNIFFER_RX
:
2000 MLX5_FLOW_NAMESPACE_SNIFFER_TX
);
2002 prio
= &dev
->flow_db
.sniffer
[ft_type
];
2009 return ERR_PTR(-ENOTSUPP
);
2011 ft
= prio
->flow_table
;
2013 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
2020 prio
->flow_table
= ft
;
2026 return err
? ERR_PTR(err
) : prio
;
2029 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
2030 struct mlx5_ib_flow_prio
*ft_prio
,
2031 const struct ib_flow_attr
*flow_attr
,
2032 struct mlx5_flow_destination
*dst
)
2034 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
2035 struct mlx5_ib_flow_handler
*handler
;
2036 struct mlx5_flow_act flow_act
= {0};
2037 struct mlx5_flow_spec
*spec
;
2038 const void *ib_flow
= (const void *)flow_attr
+ sizeof(*flow_attr
);
2039 unsigned int spec_index
;
2042 if (!is_valid_attr(flow_attr
))
2043 return ERR_PTR(-EINVAL
);
2045 spec
= mlx5_vzalloc(sizeof(*spec
));
2046 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
2047 if (!handler
|| !spec
) {
2052 INIT_LIST_HEAD(&handler
->list
);
2054 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
2055 err
= parse_flow_attr(spec
->match_criteria
,
2056 spec
->match_value
, ib_flow
);
2060 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
2063 spec
->match_criteria_enable
= get_match_criteria_enable(spec
->match_criteria
);
2064 flow_act
.action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
2065 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
2066 flow_act
.flow_tag
= MLX5_FS_DEFAULT_FLOW_TAG
;
2067 handler
->rule
= mlx5_add_flow_rules(ft
, spec
,
2071 if (IS_ERR(handler
->rule
)) {
2072 err
= PTR_ERR(handler
->rule
);
2076 ft_prio
->refcount
++;
2077 handler
->prio
= ft_prio
;
2079 ft_prio
->flow_table
= ft
;
2084 return err
? ERR_PTR(err
) : handler
;
2087 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
2088 struct mlx5_ib_flow_prio
*ft_prio
,
2089 struct ib_flow_attr
*flow_attr
,
2090 struct mlx5_flow_destination
*dst
)
2092 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
2093 struct mlx5_ib_flow_handler
*handler
= NULL
;
2095 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
2096 if (!IS_ERR(handler
)) {
2097 handler_dst
= create_flow_rule(dev
, ft_prio
,
2099 if (IS_ERR(handler_dst
)) {
2100 mlx5_del_flow_rules(handler
->rule
);
2101 ft_prio
->refcount
--;
2103 handler
= handler_dst
;
2105 list_add(&handler_dst
->list
, &handler
->list
);
2116 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
2117 struct mlx5_ib_flow_prio
*ft_prio
,
2118 struct ib_flow_attr
*flow_attr
,
2119 struct mlx5_flow_destination
*dst
)
2121 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
2122 struct mlx5_ib_flow_handler
*handler
= NULL
;
2125 struct ib_flow_attr flow_attr
;
2126 struct ib_flow_spec_eth eth_flow
;
2127 } leftovers_specs
[] = {
2131 .size
= sizeof(leftovers_specs
[0])
2134 .type
= IB_FLOW_SPEC_ETH
,
2135 .size
= sizeof(struct ib_flow_spec_eth
),
2136 .mask
= {.dst_mac
= {0x1} },
2137 .val
= {.dst_mac
= {0x1} }
2143 .size
= sizeof(leftovers_specs
[0])
2146 .type
= IB_FLOW_SPEC_ETH
,
2147 .size
= sizeof(struct ib_flow_spec_eth
),
2148 .mask
= {.dst_mac
= {0x1} },
2149 .val
= {.dst_mac
= {} }
2154 handler
= create_flow_rule(dev
, ft_prio
,
2155 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
2157 if (!IS_ERR(handler
) &&
2158 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
2159 handler_ucast
= create_flow_rule(dev
, ft_prio
,
2160 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
2162 if (IS_ERR(handler_ucast
)) {
2163 mlx5_del_flow_rules(handler
->rule
);
2164 ft_prio
->refcount
--;
2166 handler
= handler_ucast
;
2168 list_add(&handler_ucast
->list
, &handler
->list
);
2175 static struct mlx5_ib_flow_handler
*create_sniffer_rule(struct mlx5_ib_dev
*dev
,
2176 struct mlx5_ib_flow_prio
*ft_rx
,
2177 struct mlx5_ib_flow_prio
*ft_tx
,
2178 struct mlx5_flow_destination
*dst
)
2180 struct mlx5_ib_flow_handler
*handler_rx
;
2181 struct mlx5_ib_flow_handler
*handler_tx
;
2183 static const struct ib_flow_attr flow_attr
= {
2185 .size
= sizeof(flow_attr
)
2188 handler_rx
= create_flow_rule(dev
, ft_rx
, &flow_attr
, dst
);
2189 if (IS_ERR(handler_rx
)) {
2190 err
= PTR_ERR(handler_rx
);
2194 handler_tx
= create_flow_rule(dev
, ft_tx
, &flow_attr
, dst
);
2195 if (IS_ERR(handler_tx
)) {
2196 err
= PTR_ERR(handler_tx
);
2200 list_add(&handler_tx
->list
, &handler_rx
->list
);
2205 mlx5_del_flow_rules(handler_rx
->rule
);
2209 return ERR_PTR(err
);
2212 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
2213 struct ib_flow_attr
*flow_attr
,
2216 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
2217 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
2218 struct mlx5_ib_flow_handler
*handler
= NULL
;
2219 struct mlx5_flow_destination
*dst
= NULL
;
2220 struct mlx5_ib_flow_prio
*ft_prio_tx
= NULL
;
2221 struct mlx5_ib_flow_prio
*ft_prio
;
2224 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
2225 return ERR_PTR(-ENOSPC
);
2227 if (domain
!= IB_FLOW_DOMAIN_USER
||
2228 flow_attr
->port
> MLX5_CAP_GEN(dev
->mdev
, num_ports
) ||
2229 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
2230 return ERR_PTR(-EINVAL
);
2232 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
2234 return ERR_PTR(-ENOMEM
);
2236 mutex_lock(&dev
->flow_db
.lock
);
2238 ft_prio
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_RX
);
2239 if (IS_ERR(ft_prio
)) {
2240 err
= PTR_ERR(ft_prio
);
2243 if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2244 ft_prio_tx
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_TX
);
2245 if (IS_ERR(ft_prio_tx
)) {
2246 err
= PTR_ERR(ft_prio_tx
);
2252 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
2253 if (mqp
->flags
& MLX5_IB_QP_RSS
)
2254 dst
->tir_num
= mqp
->rss_qp
.tirn
;
2256 dst
->tir_num
= mqp
->raw_packet_qp
.rq
.tirn
;
2258 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
2259 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
2260 handler
= create_dont_trap_rule(dev
, ft_prio
,
2263 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
,
2266 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2267 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
2268 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
2270 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2271 handler
= create_sniffer_rule(dev
, ft_prio
, ft_prio_tx
, dst
);
2277 if (IS_ERR(handler
)) {
2278 err
= PTR_ERR(handler
);
2283 mutex_unlock(&dev
->flow_db
.lock
);
2286 return &handler
->ibflow
;
2289 put_flow_table(dev
, ft_prio
, false);
2291 put_flow_table(dev
, ft_prio_tx
, false);
2293 mutex_unlock(&dev
->flow_db
.lock
);
2296 return ERR_PTR(err
);
2299 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
2301 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2304 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
2306 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
2307 ibqp
->qp_num
, gid
->raw
);
2312 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
2314 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2317 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
2319 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
2320 ibqp
->qp_num
, gid
->raw
);
2325 static int init_node_data(struct mlx5_ib_dev
*dev
)
2329 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
2333 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
2335 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
2338 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
2341 struct mlx5_ib_dev
*dev
=
2342 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2344 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
2347 static ssize_t
show_reg_pages(struct device
*device
,
2348 struct device_attribute
*attr
, char *buf
)
2350 struct mlx5_ib_dev
*dev
=
2351 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2353 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
2356 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
2359 struct mlx5_ib_dev
*dev
=
2360 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2361 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
2364 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
2367 struct mlx5_ib_dev
*dev
=
2368 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2369 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
2372 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
2375 struct mlx5_ib_dev
*dev
=
2376 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2377 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
2378 dev
->mdev
->board_id
);
2381 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
2382 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
2383 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
2384 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
2385 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
2387 static struct device_attribute
*mlx5_class_attributes
[] = {
2392 &dev_attr_reg_pages
,
2395 static void pkey_change_handler(struct work_struct
*work
)
2397 struct mlx5_ib_port_resources
*ports
=
2398 container_of(work
, struct mlx5_ib_port_resources
,
2401 mutex_lock(&ports
->devr
->mutex
);
2402 mlx5_ib_gsi_pkey_change(ports
->gsi
);
2403 mutex_unlock(&ports
->devr
->mutex
);
2406 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
2408 struct mlx5_ib_qp
*mqp
;
2409 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
2410 struct mlx5_core_cq
*mcq
;
2411 struct list_head cq_armed_list
;
2412 unsigned long flags_qp
;
2413 unsigned long flags_cq
;
2414 unsigned long flags
;
2416 INIT_LIST_HEAD(&cq_armed_list
);
2418 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2419 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
2420 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
2421 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
2422 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
2423 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
2424 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
2425 if (send_mcq
->mcq
.comp
&&
2426 mqp
->ibqp
.send_cq
->comp_handler
) {
2427 if (!send_mcq
->mcq
.reset_notify_added
) {
2428 send_mcq
->mcq
.reset_notify_added
= 1;
2429 list_add_tail(&send_mcq
->mcq
.reset_notify
,
2433 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
2435 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
2436 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
2437 /* no handling is needed for SRQ */
2438 if (!mqp
->ibqp
.srq
) {
2439 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
2440 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
2441 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
2442 if (recv_mcq
->mcq
.comp
&&
2443 mqp
->ibqp
.recv_cq
->comp_handler
) {
2444 if (!recv_mcq
->mcq
.reset_notify_added
) {
2445 recv_mcq
->mcq
.reset_notify_added
= 1;
2446 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
2450 spin_unlock_irqrestore(&recv_mcq
->lock
,
2454 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
2456 /*At that point all inflight post send were put to be executed as of we
2457 * lock/unlock above locks Now need to arm all involved CQs.
2459 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
2462 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
2465 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
2466 enum mlx5_dev_event event
, unsigned long param
)
2468 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
2469 struct ib_event ibev
;
2474 case MLX5_DEV_EVENT_SYS_ERROR
:
2475 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
2476 mlx5_ib_handle_internal_error(ibdev
);
2480 case MLX5_DEV_EVENT_PORT_UP
:
2481 case MLX5_DEV_EVENT_PORT_DOWN
:
2482 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
2485 /* In RoCE, port up/down events are handled in
2486 * mlx5_netdev_event().
2488 if (mlx5_ib_port_link_layer(&ibdev
->ib_dev
, port
) ==
2489 IB_LINK_LAYER_ETHERNET
)
2492 ibev
.event
= (event
== MLX5_DEV_EVENT_PORT_UP
) ?
2493 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
2496 case MLX5_DEV_EVENT_LID_CHANGE
:
2497 ibev
.event
= IB_EVENT_LID_CHANGE
;
2501 case MLX5_DEV_EVENT_PKEY_CHANGE
:
2502 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
2505 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
2508 case MLX5_DEV_EVENT_GUID_CHANGE
:
2509 ibev
.event
= IB_EVENT_GID_CHANGE
;
2513 case MLX5_DEV_EVENT_CLIENT_REREG
:
2514 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
2521 ibev
.device
= &ibdev
->ib_dev
;
2522 ibev
.element
.port_num
= port
;
2524 if (port
< 1 || port
> ibdev
->num_ports
) {
2525 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
2529 if (ibdev
->ib_active
)
2530 ib_dispatch_event(&ibev
);
2533 ibdev
->ib_active
= false;
2536 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
2540 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
2541 mlx5_query_ext_port_caps(dev
, port
);
2544 static int get_port_caps(struct mlx5_ib_dev
*dev
)
2546 struct ib_device_attr
*dprops
= NULL
;
2547 struct ib_port_attr
*pprops
= NULL
;
2550 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
2552 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
2556 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
2560 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
2562 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
2566 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
2567 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
2569 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
2573 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
2575 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
2576 pprops
->gid_tbl_len
;
2577 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
2578 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
2588 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
2592 err
= mlx5_mr_cache_cleanup(dev
);
2594 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
2596 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
2597 ib_free_cq(dev
->umrc
.cq
);
2598 ib_dealloc_pd(dev
->umrc
.pd
);
2605 static int create_umr_res(struct mlx5_ib_dev
*dev
)
2607 struct ib_qp_init_attr
*init_attr
= NULL
;
2608 struct ib_qp_attr
*attr
= NULL
;
2614 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
2615 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
2616 if (!attr
|| !init_attr
) {
2621 pd
= ib_alloc_pd(&dev
->ib_dev
, 0);
2623 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
2628 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
2630 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
2635 init_attr
->send_cq
= cq
;
2636 init_attr
->recv_cq
= cq
;
2637 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
2638 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
2639 init_attr
->cap
.max_send_sge
= 1;
2640 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2641 init_attr
->port_num
= 1;
2642 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
2644 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
2648 qp
->device
= &dev
->ib_dev
;
2651 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2653 attr
->qp_state
= IB_QPS_INIT
;
2655 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
2658 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
2662 memset(attr
, 0, sizeof(*attr
));
2663 attr
->qp_state
= IB_QPS_RTR
;
2664 attr
->path_mtu
= IB_MTU_256
;
2666 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2668 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
2672 memset(attr
, 0, sizeof(*attr
));
2673 attr
->qp_state
= IB_QPS_RTS
;
2674 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2676 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
2684 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
2685 ret
= mlx5_mr_cache_init(dev
);
2687 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
2697 mlx5_ib_destroy_qp(qp
);
2711 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
2713 struct ib_srq_init_attr attr
;
2714 struct mlx5_ib_dev
*dev
;
2715 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
2719 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
2721 mutex_init(&devr
->mutex
);
2723 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
2724 if (IS_ERR(devr
->p0
)) {
2725 ret
= PTR_ERR(devr
->p0
);
2728 devr
->p0
->device
= &dev
->ib_dev
;
2729 devr
->p0
->uobject
= NULL
;
2730 atomic_set(&devr
->p0
->usecnt
, 0);
2732 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
2733 if (IS_ERR(devr
->c0
)) {
2734 ret
= PTR_ERR(devr
->c0
);
2737 devr
->c0
->device
= &dev
->ib_dev
;
2738 devr
->c0
->uobject
= NULL
;
2739 devr
->c0
->comp_handler
= NULL
;
2740 devr
->c0
->event_handler
= NULL
;
2741 devr
->c0
->cq_context
= NULL
;
2742 atomic_set(&devr
->c0
->usecnt
, 0);
2744 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2745 if (IS_ERR(devr
->x0
)) {
2746 ret
= PTR_ERR(devr
->x0
);
2749 devr
->x0
->device
= &dev
->ib_dev
;
2750 devr
->x0
->inode
= NULL
;
2751 atomic_set(&devr
->x0
->usecnt
, 0);
2752 mutex_init(&devr
->x0
->tgt_qp_mutex
);
2753 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
2755 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2756 if (IS_ERR(devr
->x1
)) {
2757 ret
= PTR_ERR(devr
->x1
);
2760 devr
->x1
->device
= &dev
->ib_dev
;
2761 devr
->x1
->inode
= NULL
;
2762 atomic_set(&devr
->x1
->usecnt
, 0);
2763 mutex_init(&devr
->x1
->tgt_qp_mutex
);
2764 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
2766 memset(&attr
, 0, sizeof(attr
));
2767 attr
.attr
.max_sge
= 1;
2768 attr
.attr
.max_wr
= 1;
2769 attr
.srq_type
= IB_SRQT_XRC
;
2770 attr
.ext
.xrc
.cq
= devr
->c0
;
2771 attr
.ext
.xrc
.xrcd
= devr
->x0
;
2773 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2774 if (IS_ERR(devr
->s0
)) {
2775 ret
= PTR_ERR(devr
->s0
);
2778 devr
->s0
->device
= &dev
->ib_dev
;
2779 devr
->s0
->pd
= devr
->p0
;
2780 devr
->s0
->uobject
= NULL
;
2781 devr
->s0
->event_handler
= NULL
;
2782 devr
->s0
->srq_context
= NULL
;
2783 devr
->s0
->srq_type
= IB_SRQT_XRC
;
2784 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
2785 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
2786 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
2787 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
2788 atomic_inc(&devr
->p0
->usecnt
);
2789 atomic_set(&devr
->s0
->usecnt
, 0);
2791 memset(&attr
, 0, sizeof(attr
));
2792 attr
.attr
.max_sge
= 1;
2793 attr
.attr
.max_wr
= 1;
2794 attr
.srq_type
= IB_SRQT_BASIC
;
2795 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2796 if (IS_ERR(devr
->s1
)) {
2797 ret
= PTR_ERR(devr
->s1
);
2800 devr
->s1
->device
= &dev
->ib_dev
;
2801 devr
->s1
->pd
= devr
->p0
;
2802 devr
->s1
->uobject
= NULL
;
2803 devr
->s1
->event_handler
= NULL
;
2804 devr
->s1
->srq_context
= NULL
;
2805 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
2806 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
2807 atomic_inc(&devr
->p0
->usecnt
);
2808 atomic_set(&devr
->s0
->usecnt
, 0);
2810 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
2811 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
2812 pkey_change_handler
);
2813 devr
->ports
[port
].devr
= devr
;
2819 mlx5_ib_destroy_srq(devr
->s0
);
2821 mlx5_ib_dealloc_xrcd(devr
->x1
);
2823 mlx5_ib_dealloc_xrcd(devr
->x0
);
2825 mlx5_ib_destroy_cq(devr
->c0
);
2827 mlx5_ib_dealloc_pd(devr
->p0
);
2832 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
2834 struct mlx5_ib_dev
*dev
=
2835 container_of(devr
, struct mlx5_ib_dev
, devr
);
2838 mlx5_ib_destroy_srq(devr
->s1
);
2839 mlx5_ib_destroy_srq(devr
->s0
);
2840 mlx5_ib_dealloc_xrcd(devr
->x0
);
2841 mlx5_ib_dealloc_xrcd(devr
->x1
);
2842 mlx5_ib_destroy_cq(devr
->c0
);
2843 mlx5_ib_dealloc_pd(devr
->p0
);
2845 /* Make sure no change P_Key work items are still executing */
2846 for (port
= 0; port
< dev
->num_ports
; ++port
)
2847 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
2850 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
2852 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2853 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
2854 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
2855 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
2858 if (ll
== IB_LINK_LAYER_INFINIBAND
)
2859 return RDMA_CORE_PORT_IBA_IB
;
2861 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
2864 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
2867 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
2868 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
2870 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
2871 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
2876 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
2877 struct ib_port_immutable
*immutable
)
2879 struct ib_port_attr attr
;
2880 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
2881 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, port_num
);
2884 err
= mlx5_ib_query_port(ibdev
, port_num
, &attr
);
2888 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
2889 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
2890 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
2891 if ((ll
== IB_LINK_LAYER_INFINIBAND
) || MLX5_CAP_GEN(dev
->mdev
, roce
))
2892 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
2897 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
,
2900 struct mlx5_ib_dev
*dev
=
2901 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
2902 snprintf(str
, str_len
, "%d.%d.%04d", fw_rev_maj(dev
->mdev
),
2903 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
2906 static int mlx5_eth_lag_init(struct mlx5_ib_dev
*dev
)
2908 struct mlx5_core_dev
*mdev
= dev
->mdev
;
2909 struct mlx5_flow_namespace
*ns
= mlx5_get_flow_namespace(mdev
,
2910 MLX5_FLOW_NAMESPACE_LAG
);
2911 struct mlx5_flow_table
*ft
;
2914 if (!ns
|| !mlx5_lag_is_active(mdev
))
2917 err
= mlx5_cmd_create_vport_lag(mdev
);
2921 ft
= mlx5_create_lag_demux_flow_table(ns
, 0, 0);
2924 goto err_destroy_vport_lag
;
2927 dev
->flow_db
.lag_demux_ft
= ft
;
2930 err_destroy_vport_lag
:
2931 mlx5_cmd_destroy_vport_lag(mdev
);
2935 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev
*dev
)
2937 struct mlx5_core_dev
*mdev
= dev
->mdev
;
2939 if (dev
->flow_db
.lag_demux_ft
) {
2940 mlx5_destroy_flow_table(dev
->flow_db
.lag_demux_ft
);
2941 dev
->flow_db
.lag_demux_ft
= NULL
;
2943 mlx5_cmd_destroy_vport_lag(mdev
);
2947 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev
*dev
)
2951 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
2952 err
= register_netdevice_notifier(&dev
->roce
.nb
);
2954 dev
->roce
.nb
.notifier_call
= NULL
;
2961 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev
*dev
)
2963 if (dev
->roce
.nb
.notifier_call
) {
2964 unregister_netdevice_notifier(&dev
->roce
.nb
);
2965 dev
->roce
.nb
.notifier_call
= NULL
;
2969 static int mlx5_enable_eth(struct mlx5_ib_dev
*dev
)
2973 err
= mlx5_add_netdev_notifier(dev
);
2977 if (MLX5_CAP_GEN(dev
->mdev
, roce
)) {
2978 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
2980 goto err_unregister_netdevice_notifier
;
2983 err
= mlx5_eth_lag_init(dev
);
2985 goto err_disable_roce
;
2990 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
2991 mlx5_nic_vport_disable_roce(dev
->mdev
);
2993 err_unregister_netdevice_notifier
:
2994 mlx5_remove_netdev_notifier(dev
);
2998 static void mlx5_disable_eth(struct mlx5_ib_dev
*dev
)
3000 mlx5_eth_lag_cleanup(dev
);
3001 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
3002 mlx5_nic_vport_disable_roce(dev
->mdev
);
3005 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev
*dev
)
3009 for (i
= 0; i
< dev
->num_ports
; i
++)
3010 mlx5_core_dealloc_q_counter(dev
->mdev
,
3011 dev
->port
[i
].q_cnt_id
);
3014 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev
*dev
)
3019 for (i
= 0; i
< dev
->num_ports
; i
++) {
3020 ret
= mlx5_core_alloc_q_counter(dev
->mdev
,
3021 &dev
->port
[i
].q_cnt_id
);
3024 "couldn't allocate queue counter for port %d, err %d\n",
3026 goto dealloc_counters
;
3034 mlx5_core_dealloc_q_counter(dev
->mdev
,
3035 dev
->port
[i
].q_cnt_id
);
3040 static const char * const names
[] = {
3041 "rx_write_requests",
3043 "rx_atomic_requests",
3046 "duplicate_request",
3047 "rnr_nak_retry_err",
3049 "implied_nak_seq_err",
3050 "local_ack_timeout_err",
3053 static const size_t stats_offsets
[] = {
3054 MLX5_BYTE_OFF(query_q_counter_out
, rx_write_requests
),
3055 MLX5_BYTE_OFF(query_q_counter_out
, rx_read_requests
),
3056 MLX5_BYTE_OFF(query_q_counter_out
, rx_atomic_requests
),
3057 MLX5_BYTE_OFF(query_q_counter_out
, out_of_buffer
),
3058 MLX5_BYTE_OFF(query_q_counter_out
, out_of_sequence
),
3059 MLX5_BYTE_OFF(query_q_counter_out
, duplicate_request
),
3060 MLX5_BYTE_OFF(query_q_counter_out
, rnr_nak_retry_err
),
3061 MLX5_BYTE_OFF(query_q_counter_out
, packet_seq_err
),
3062 MLX5_BYTE_OFF(query_q_counter_out
, implied_nak_seq_err
),
3063 MLX5_BYTE_OFF(query_q_counter_out
, local_ack_timeout_err
),
3066 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
3069 BUILD_BUG_ON(ARRAY_SIZE(names
) != ARRAY_SIZE(stats_offsets
));
3071 /* We support only per port stats */
3075 return rdma_alloc_hw_stats_struct(names
, ARRAY_SIZE(names
),
3076 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
3079 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
3080 struct rdma_hw_stats
*stats
,
3083 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3084 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
3090 if (!port
|| !stats
)
3093 out
= mlx5_vzalloc(outlen
);
3097 ret
= mlx5_core_query_q_counter(dev
->mdev
,
3098 dev
->port
[port
- 1].q_cnt_id
, 0,
3103 for (i
= 0; i
< ARRAY_SIZE(names
); i
++) {
3104 val
= *(__be32
*)(out
+ stats_offsets
[i
]);
3105 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
3109 return ARRAY_SIZE(names
);
3112 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
3114 struct mlx5_ib_dev
*dev
;
3115 enum rdma_link_layer ll
;
3121 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
3122 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
3124 printk_once(KERN_INFO
"%s", mlx5_version
);
3126 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
3132 dev
->port
= kcalloc(MLX5_CAP_GEN(mdev
, num_ports
), sizeof(*dev
->port
),
3137 rwlock_init(&dev
->roce
.netdev_lock
);
3138 err
= get_port_caps(dev
);
3142 if (mlx5_use_mad_ifc(dev
))
3143 get_ext_port_caps(dev
);
3145 if (!mlx5_lag_is_active(mdev
))
3148 name
= "mlx5_bond_%d";
3150 strlcpy(dev
->ib_dev
.name
, name
, IB_DEVICE_NAME_MAX
);
3151 dev
->ib_dev
.owner
= THIS_MODULE
;
3152 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
3153 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
3154 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
3155 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
3156 dev
->ib_dev
.num_comp_vectors
=
3157 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
3158 dev
->ib_dev
.dma_device
= &mdev
->pdev
->dev
;
3160 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
3161 dev
->ib_dev
.uverbs_cmd_mask
=
3162 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
3163 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
3164 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
3165 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
3166 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
3167 (1ull << IB_USER_VERBS_CMD_CREATE_AH
) |
3168 (1ull << IB_USER_VERBS_CMD_DESTROY_AH
) |
3169 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
3170 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
3171 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
3172 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
3173 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
3174 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
3175 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
3176 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
3177 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
3178 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
3179 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
3180 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
3181 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
3182 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
3183 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
3184 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
3185 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
3186 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
3187 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
3188 dev
->ib_dev
.uverbs_ex_cmd_mask
=
3189 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
3190 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
3191 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
) |
3192 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP
);
3194 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
3195 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
3196 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
3197 if (ll
== IB_LINK_LAYER_ETHERNET
)
3198 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
3199 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
3200 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
3201 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
3202 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
3203 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
3204 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
3205 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
3206 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
3207 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
3208 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
3209 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
3210 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
3211 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
3212 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
3213 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
3214 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
3215 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
3216 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
3217 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
3218 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
3219 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
3220 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
3221 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
3222 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
3223 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
3224 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
3225 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
3226 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
3227 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
3228 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
3229 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
3230 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
3231 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
3232 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
3233 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
3234 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
3235 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
3236 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
3237 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
3238 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
3239 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
3240 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
3241 dev
->ib_dev
.get_dev_fw_str
= get_dev_fw_str
;
3242 if (mlx5_core_is_pf(mdev
)) {
3243 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
3244 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
3245 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
3246 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
3249 dev
->ib_dev
.disassociate_ucontext
= mlx5_ib_disassociate_ucontext
;
3251 mlx5_ib_internal_fill_odp_caps(dev
);
3253 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
3254 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
3255 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
3256 dev
->ib_dev
.uverbs_cmd_mask
|=
3257 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
3258 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
3261 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
) &&
3262 MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
3263 dev
->ib_dev
.get_hw_stats
= mlx5_ib_get_hw_stats
;
3264 dev
->ib_dev
.alloc_hw_stats
= mlx5_ib_alloc_hw_stats
;
3267 if (MLX5_CAP_GEN(mdev
, xrc
)) {
3268 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
3269 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
3270 dev
->ib_dev
.uverbs_cmd_mask
|=
3271 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
3272 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
3275 if (mlx5_ib_port_link_layer(&dev
->ib_dev
, 1) ==
3276 IB_LINK_LAYER_ETHERNET
) {
3277 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
3278 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
3279 dev
->ib_dev
.create_wq
= mlx5_ib_create_wq
;
3280 dev
->ib_dev
.modify_wq
= mlx5_ib_modify_wq
;
3281 dev
->ib_dev
.destroy_wq
= mlx5_ib_destroy_wq
;
3282 dev
->ib_dev
.create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
;
3283 dev
->ib_dev
.destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
;
3284 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
3285 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
3286 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
) |
3287 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
3288 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
3289 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
3290 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
3291 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
3293 err
= init_node_data(dev
);
3297 mutex_init(&dev
->flow_db
.lock
);
3298 mutex_init(&dev
->cap_mask_mutex
);
3299 INIT_LIST_HEAD(&dev
->qp_list
);
3300 spin_lock_init(&dev
->reset_flow_resource_lock
);
3302 if (ll
== IB_LINK_LAYER_ETHERNET
) {
3303 err
= mlx5_enable_eth(dev
);
3308 err
= create_dev_resources(&dev
->devr
);
3310 goto err_disable_eth
;
3312 err
= mlx5_ib_odp_init_one(dev
);
3316 err
= mlx5_ib_alloc_q_counters(dev
);
3320 dev
->mdev
->priv
.uar
= mlx5_get_uars_page(dev
->mdev
);
3321 if (!dev
->mdev
->priv
.uar
)
3324 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->bfreg
, false, false);
3328 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->fp_bfreg
, false, true);
3332 err
= ib_register_device(&dev
->ib_dev
, NULL
);
3336 err
= create_umr_res(dev
);
3340 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
3341 err
= device_create_file(&dev
->ib_dev
.dev
,
3342 mlx5_class_attributes
[i
]);
3347 dev
->ib_active
= true;
3352 destroy_umrc_res(dev
);
3355 ib_unregister_device(&dev
->ib_dev
);
3358 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
3361 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
3364 mlx5_put_uars_page(dev
->mdev
, dev
->mdev
->priv
.uar
);
3367 mlx5_ib_dealloc_q_counters(dev
);
3370 mlx5_ib_odp_remove_one(dev
);
3373 destroy_dev_resources(&dev
->devr
);
3376 if (ll
== IB_LINK_LAYER_ETHERNET
) {
3377 mlx5_disable_eth(dev
);
3378 mlx5_remove_netdev_notifier(dev
);
3385 ib_dealloc_device((struct ib_device
*)dev
);
3390 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
3392 struct mlx5_ib_dev
*dev
= context
;
3393 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
3395 mlx5_remove_netdev_notifier(dev
);
3396 ib_unregister_device(&dev
->ib_dev
);
3397 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
3398 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
3399 mlx5_put_uars_page(dev
->mdev
, mdev
->priv
.uar
);
3400 mlx5_ib_dealloc_q_counters(dev
);
3401 destroy_umrc_res(dev
);
3402 mlx5_ib_odp_remove_one(dev
);
3403 destroy_dev_resources(&dev
->devr
);
3404 if (ll
== IB_LINK_LAYER_ETHERNET
)
3405 mlx5_disable_eth(dev
);
3407 ib_dealloc_device(&dev
->ib_dev
);
3410 static struct mlx5_interface mlx5_ib_interface
= {
3412 .remove
= mlx5_ib_remove
,
3413 .event
= mlx5_ib_event
,
3414 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3415 .pfault
= mlx5_ib_pfault
,
3417 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
3420 static int __init
mlx5_ib_init(void)
3424 if (deprecated_prof_sel
!= 2)
3425 pr_warn("prof_sel is deprecated for mlx5_ib, set it for mlx5_core\n");
3427 err
= mlx5_register_interface(&mlx5_ib_interface
);
3432 static void __exit
mlx5_ib_cleanup(void)
3434 mlx5_unregister_interface(&mlx5_ib_interface
);
3437 module_init(mlx5_ib_init
);
3438 module_exit(mlx5_ib_cleanup
);