2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #if defined(CONFIG_X86)
44 #include <linux/sched.h>
45 #include <linux/sched/mm.h>
46 #include <linux/sched/task.h>
47 #include <linux/delay.h>
48 #include <rdma/ib_user_verbs.h>
49 #include <rdma/ib_addr.h>
50 #include <rdma/ib_cache.h>
51 #include <linux/mlx5/port.h>
52 #include <linux/mlx5/vport.h>
53 #include <linux/mlx5/fs.h>
54 #include <linux/list.h>
55 #include <rdma/ib_smi.h>
56 #include <rdma/ib_umem.h>
58 #include <linux/etherdevice.h>
62 #include <linux/mlx5/fs_helpers.h>
64 #define DRIVER_NAME "mlx5_ib"
65 #define DRIVER_VERSION "5.0-0"
67 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
68 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
69 MODULE_LICENSE("Dual BSD/GPL");
71 static char mlx5_version
[] =
72 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
75 struct mlx5_ib_event_work
{
76 struct work_struct work
;
77 struct mlx5_core_dev
*dev
;
79 enum mlx5_dev_event event
;
84 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
87 static struct workqueue_struct
*mlx5_ib_event_wq
;
88 static LIST_HEAD(mlx5_ib_unaffiliated_port_list
);
89 static LIST_HEAD(mlx5_ib_dev_list
);
91 * This mutex should be held when accessing either of the above lists
93 static DEFINE_MUTEX(mlx5_ib_multiport_mutex
);
95 struct mlx5_ib_dev
*mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info
*mpi
)
97 struct mlx5_ib_dev
*dev
;
99 mutex_lock(&mlx5_ib_multiport_mutex
);
101 mutex_unlock(&mlx5_ib_multiport_mutex
);
105 static enum rdma_link_layer
106 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
108 switch (port_type_cap
) {
109 case MLX5_CAP_PORT_TYPE_IB
:
110 return IB_LINK_LAYER_INFINIBAND
;
111 case MLX5_CAP_PORT_TYPE_ETH
:
112 return IB_LINK_LAYER_ETHERNET
;
114 return IB_LINK_LAYER_UNSPECIFIED
;
118 static enum rdma_link_layer
119 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
121 struct mlx5_ib_dev
*dev
= to_mdev(device
);
122 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
124 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
127 static int get_port_state(struct ib_device
*ibdev
,
129 enum ib_port_state
*state
)
131 struct ib_port_attr attr
;
134 memset(&attr
, 0, sizeof(attr
));
135 ret
= ibdev
->query_port(ibdev
, port_num
, &attr
);
141 static int mlx5_netdev_event(struct notifier_block
*this,
142 unsigned long event
, void *ptr
)
144 struct mlx5_roce
*roce
= container_of(this, struct mlx5_roce
, nb
);
145 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
146 u8 port_num
= roce
->native_port_num
;
147 struct mlx5_core_dev
*mdev
;
148 struct mlx5_ib_dev
*ibdev
;
151 mdev
= mlx5_ib_get_native_port_mdev(ibdev
, port_num
, NULL
);
156 case NETDEV_REGISTER
:
157 case NETDEV_UNREGISTER
:
158 write_lock(&roce
->netdev_lock
);
160 struct mlx5_eswitch
*esw
= ibdev
->mdev
->priv
.eswitch
;
161 struct net_device
*rep_ndev
;
163 rep_ndev
= mlx5_ib_get_rep_netdev(esw
,
165 if (rep_ndev
== ndev
)
166 roce
->netdev
= (event
== NETDEV_UNREGISTER
) ?
168 } else if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
) {
169 roce
->netdev
= (event
== NETDEV_UNREGISTER
) ?
172 write_unlock(&roce
->netdev_lock
);
178 struct net_device
*lag_ndev
= mlx5_lag_get_roce_netdev(mdev
);
179 struct net_device
*upper
= NULL
;
182 upper
= netdev_master_upper_dev_get(lag_ndev
);
186 if ((upper
== ndev
|| (!upper
&& ndev
== roce
->netdev
))
187 && ibdev
->ib_active
) {
188 struct ib_event ibev
= { };
189 enum ib_port_state port_state
;
191 if (get_port_state(&ibdev
->ib_dev
, port_num
,
195 if (roce
->last_port_state
== port_state
)
198 roce
->last_port_state
= port_state
;
199 ibev
.device
= &ibdev
->ib_dev
;
200 if (port_state
== IB_PORT_DOWN
)
201 ibev
.event
= IB_EVENT_PORT_ERR
;
202 else if (port_state
== IB_PORT_ACTIVE
)
203 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
207 ibev
.element
.port_num
= port_num
;
208 ib_dispatch_event(&ibev
);
217 mlx5_ib_put_native_port_mdev(ibdev
, port_num
);
221 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
224 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
225 struct net_device
*ndev
;
226 struct mlx5_core_dev
*mdev
;
228 mdev
= mlx5_ib_get_native_port_mdev(ibdev
, port_num
, NULL
);
232 ndev
= mlx5_lag_get_roce_netdev(mdev
);
236 /* Ensure ndev does not disappear before we invoke dev_hold()
238 read_lock(&ibdev
->roce
[port_num
- 1].netdev_lock
);
239 ndev
= ibdev
->roce
[port_num
- 1].netdev
;
242 read_unlock(&ibdev
->roce
[port_num
- 1].netdev_lock
);
245 mlx5_ib_put_native_port_mdev(ibdev
, port_num
);
249 struct mlx5_core_dev
*mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev
*ibdev
,
253 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&ibdev
->ib_dev
,
255 struct mlx5_core_dev
*mdev
= NULL
;
256 struct mlx5_ib_multiport_info
*mpi
;
257 struct mlx5_ib_port
*port
;
260 *native_port_num
= 1;
262 if (!mlx5_core_mp_enabled(ibdev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
265 port
= &ibdev
->port
[ib_port_num
- 1];
269 spin_lock(&port
->mp
.mpi_lock
);
270 mpi
= ibdev
->port
[ib_port_num
- 1].mp
.mpi
;
271 if (mpi
&& !mpi
->unaffiliate
) {
273 /* If it's the master no need to refcount, it'll exist
274 * as long as the ib_dev exists.
279 spin_unlock(&port
->mp
.mpi_lock
);
284 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev
*ibdev
, u8 port_num
)
286 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&ibdev
->ib_dev
,
288 struct mlx5_ib_multiport_info
*mpi
;
289 struct mlx5_ib_port
*port
;
291 if (!mlx5_core_mp_enabled(ibdev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
294 port
= &ibdev
->port
[port_num
- 1];
296 spin_lock(&port
->mp
.mpi_lock
);
297 mpi
= ibdev
->port
[port_num
- 1].mp
.mpi
;
302 if (mpi
->unaffiliate
)
303 complete(&mpi
->unref_comp
);
305 spin_unlock(&port
->mp
.mpi_lock
);
308 static int translate_eth_proto_oper(u32 eth_proto_oper
, u8
*active_speed
,
311 switch (eth_proto_oper
) {
312 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII
):
313 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX
):
314 case MLX5E_PROT_MASK(MLX5E_100BASE_TX
):
315 case MLX5E_PROT_MASK(MLX5E_1000BASE_T
):
316 *active_width
= IB_WIDTH_1X
;
317 *active_speed
= IB_SPEED_SDR
;
319 case MLX5E_PROT_MASK(MLX5E_10GBASE_T
):
320 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4
):
321 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4
):
322 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR
):
323 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR
):
324 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR
):
325 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER
):
326 *active_width
= IB_WIDTH_1X
;
327 *active_speed
= IB_SPEED_QDR
;
329 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR
):
330 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR
):
331 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR
):
332 *active_width
= IB_WIDTH_1X
;
333 *active_speed
= IB_SPEED_EDR
;
335 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4
):
336 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4
):
337 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4
):
338 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4
):
339 *active_width
= IB_WIDTH_4X
;
340 *active_speed
= IB_SPEED_QDR
;
342 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2
):
343 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2
):
344 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2
):
345 *active_width
= IB_WIDTH_1X
;
346 *active_speed
= IB_SPEED_HDR
;
348 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4
):
349 *active_width
= IB_WIDTH_4X
;
350 *active_speed
= IB_SPEED_FDR
;
352 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4
):
353 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4
):
354 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4
):
355 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4
):
356 *active_width
= IB_WIDTH_4X
;
357 *active_speed
= IB_SPEED_EDR
;
366 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
367 struct ib_port_attr
*props
)
369 struct mlx5_ib_dev
*dev
= to_mdev(device
);
370 struct mlx5_core_dev
*mdev
;
371 struct net_device
*ndev
, *upper
;
372 enum ib_mtu ndev_ib_mtu
;
373 bool put_mdev
= true;
379 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
, &mdev_port_num
);
381 /* This means the port isn't affiliated yet. Get the
382 * info for the master port instead.
390 /* Possible bad flows are checked before filling out props so in case
391 * of an error it will still be zeroed out.
393 err
= mlx5_query_port_eth_proto_oper(mdev
, ð_prot_oper
,
398 translate_eth_proto_oper(eth_prot_oper
, &props
->active_speed
,
399 &props
->active_width
);
401 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
402 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
404 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
405 roce_address_table_size
);
406 props
->max_mtu
= IB_MTU_4096
;
407 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
408 props
->pkey_tbl_len
= 1;
409 props
->state
= IB_PORT_DOWN
;
410 props
->phys_state
= 3;
412 mlx5_query_nic_vport_qkey_viol_cntr(mdev
, &qkey_viol_cntr
);
413 props
->qkey_viol_cntr
= qkey_viol_cntr
;
415 /* If this is a stub query for an unaffiliated port stop here */
419 ndev
= mlx5_ib_get_netdev(device
, port_num
);
423 if (mlx5_lag_is_active(dev
->mdev
)) {
425 upper
= netdev_master_upper_dev_get_rcu(ndev
);
434 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
435 props
->state
= IB_PORT_ACTIVE
;
436 props
->phys_state
= 5;
439 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
443 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
446 mlx5_ib_put_native_port_mdev(dev
, port_num
);
450 static int set_roce_addr(struct mlx5_ib_dev
*dev
, u8 port_num
,
451 unsigned int index
, const union ib_gid
*gid
,
452 const struct ib_gid_attr
*attr
)
454 enum ib_gid_type gid_type
= IB_GID_TYPE_IB
;
462 gid_type
= attr
->gid_type
;
463 ether_addr_copy(mac
, attr
->ndev
->dev_addr
);
465 if (is_vlan_dev(attr
->ndev
)) {
467 vlan_id
= vlan_dev_vlan_id(attr
->ndev
);
473 roce_version
= MLX5_ROCE_VERSION_1
;
475 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
476 roce_version
= MLX5_ROCE_VERSION_2
;
477 if (ipv6_addr_v4mapped((void *)gid
))
478 roce_l3_type
= MLX5_ROCE_L3_TYPE_IPV4
;
480 roce_l3_type
= MLX5_ROCE_L3_TYPE_IPV6
;
484 mlx5_ib_warn(dev
, "Unexpected GID type %u\n", gid_type
);
487 return mlx5_core_roce_gid_set(dev
->mdev
, index
, roce_version
,
488 roce_l3_type
, gid
->raw
, mac
, vlan
,
492 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
493 unsigned int index
, const union ib_gid
*gid
,
494 const struct ib_gid_attr
*attr
,
495 __always_unused
void **context
)
497 return set_roce_addr(to_mdev(device
), port_num
, index
, gid
, attr
);
500 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
501 unsigned int index
, __always_unused
void **context
)
503 return set_roce_addr(to_mdev(device
), port_num
, index
, NULL
, NULL
);
506 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
509 struct ib_gid_attr attr
;
512 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
520 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
523 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
526 int mlx5_get_roce_gid_type(struct mlx5_ib_dev
*dev
, u8 port_num
,
527 int index
, enum ib_gid_type
*gid_type
)
529 struct ib_gid_attr attr
;
533 ret
= ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
);
542 *gid_type
= attr
.gid_type
;
547 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
549 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_IB
)
550 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
555 MLX5_VPORT_ACCESS_METHOD_MAD
,
556 MLX5_VPORT_ACCESS_METHOD_HCA
,
557 MLX5_VPORT_ACCESS_METHOD_NIC
,
560 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
562 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
563 return MLX5_VPORT_ACCESS_METHOD_MAD
;
565 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
566 IB_LINK_LAYER_ETHERNET
)
567 return MLX5_VPORT_ACCESS_METHOD_NIC
;
569 return MLX5_VPORT_ACCESS_METHOD_HCA
;
572 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
574 struct ib_device_attr
*props
)
577 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
578 u8 atomic_req_8B_endianness_mode
=
579 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianness_mode
);
581 /* Check if HW supports 8 bytes standard atomic operations and capable
582 * of host endianness respond
584 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
585 if (((atomic_operations
& tmp
) == tmp
) &&
586 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
587 (atomic_req_8B_endianness_mode
)) {
588 props
->atomic_cap
= IB_ATOMIC_HCA
;
590 props
->atomic_cap
= IB_ATOMIC_NONE
;
594 static void get_atomic_caps_qp(struct mlx5_ib_dev
*dev
,
595 struct ib_device_attr
*props
)
597 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
599 get_atomic_caps(dev
, atomic_size_qp
, props
);
602 static void get_atomic_caps_dc(struct mlx5_ib_dev
*dev
,
603 struct ib_device_attr
*props
)
605 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_dc
);
607 get_atomic_caps(dev
, atomic_size_qp
, props
);
610 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev
*dev
)
612 struct ib_device_attr props
= {};
614 get_atomic_caps_dc(dev
, &props
);
615 return (props
.atomic_cap
== IB_ATOMIC_HCA
) ? true : false;
617 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
618 __be64
*sys_image_guid
)
620 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
621 struct mlx5_core_dev
*mdev
= dev
->mdev
;
625 switch (mlx5_get_vport_access_method(ibdev
)) {
626 case MLX5_VPORT_ACCESS_METHOD_MAD
:
627 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
630 case MLX5_VPORT_ACCESS_METHOD_HCA
:
631 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
634 case MLX5_VPORT_ACCESS_METHOD_NIC
:
635 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
643 *sys_image_guid
= cpu_to_be64(tmp
);
649 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
652 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
653 struct mlx5_core_dev
*mdev
= dev
->mdev
;
655 switch (mlx5_get_vport_access_method(ibdev
)) {
656 case MLX5_VPORT_ACCESS_METHOD_MAD
:
657 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
659 case MLX5_VPORT_ACCESS_METHOD_HCA
:
660 case MLX5_VPORT_ACCESS_METHOD_NIC
:
661 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
670 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
673 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
675 switch (mlx5_get_vport_access_method(ibdev
)) {
676 case MLX5_VPORT_ACCESS_METHOD_MAD
:
677 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
679 case MLX5_VPORT_ACCESS_METHOD_HCA
:
680 case MLX5_VPORT_ACCESS_METHOD_NIC
:
681 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
688 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
694 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
695 case MLX5_VPORT_ACCESS_METHOD_MAD
:
696 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
698 case MLX5_VPORT_ACCESS_METHOD_HCA
:
699 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
702 case MLX5_VPORT_ACCESS_METHOD_NIC
:
703 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
711 *node_guid
= cpu_to_be64(tmp
);
716 struct mlx5_reg_node_desc
{
717 u8 desc
[IB_DEVICE_NODE_DESC_MAX
];
720 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
722 struct mlx5_reg_node_desc in
;
724 if (mlx5_use_mad_ifc(dev
))
725 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
727 memset(&in
, 0, sizeof(in
));
729 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
730 sizeof(struct mlx5_reg_node_desc
),
731 MLX5_REG_NODE_DESC
, 0, 0);
734 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
735 struct ib_device_attr
*props
,
736 struct ib_udata
*uhw
)
738 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
739 struct mlx5_core_dev
*mdev
= dev
->mdev
;
744 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
745 bool raw_support
= !mlx5_core_mp_enabled(mdev
);
746 struct mlx5_ib_query_device_resp resp
= {};
750 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
751 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
754 resp
.response_length
= resp_len
;
756 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
759 memset(props
, 0, sizeof(*props
));
760 err
= mlx5_query_system_image_guid(ibdev
,
761 &props
->sys_image_guid
);
765 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
769 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
773 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
774 (fw_rev_min(dev
->mdev
) << 16) |
775 fw_rev_sub(dev
->mdev
);
776 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
777 IB_DEVICE_PORT_ACTIVE_EVENT
|
778 IB_DEVICE_SYS_IMAGE_GUID
|
779 IB_DEVICE_RC_RNR_NAK_GEN
;
781 if (MLX5_CAP_GEN(mdev
, pkv
))
782 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
783 if (MLX5_CAP_GEN(mdev
, qkv
))
784 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
785 if (MLX5_CAP_GEN(mdev
, apm
))
786 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
787 if (MLX5_CAP_GEN(mdev
, xrc
))
788 props
->device_cap_flags
|= IB_DEVICE_XRC
;
789 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
790 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
791 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
792 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
793 /* We support 'Gappy' memory registration too */
794 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
796 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
797 if (MLX5_CAP_GEN(mdev
, sho
)) {
798 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
799 /* At this stage no support for signature handover */
800 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
801 IB_PROT_T10DIF_TYPE_2
|
802 IB_PROT_T10DIF_TYPE_3
;
803 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
804 IB_GUARD_T10DIF_CSUM
;
806 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
807 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
809 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) && raw_support
) {
810 if (MLX5_CAP_ETH(mdev
, csum_cap
)) {
811 /* Legacy bit to support old userspace libraries */
812 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
813 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_IP_CSUM
;
816 if (MLX5_CAP_ETH(dev
->mdev
, vlan_cap
))
817 props
->raw_packet_caps
|=
818 IB_RAW_PACKET_CAP_CVLAN_STRIPPING
;
820 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
821 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
823 resp
.tso_caps
.max_tso
= 1 << max_tso
;
824 resp
.tso_caps
.supported_qpts
|=
825 1 << IB_QPT_RAW_PACKET
;
826 resp
.response_length
+= sizeof(resp
.tso_caps
);
830 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
)) {
831 resp
.rss_caps
.rx_hash_function
=
832 MLX5_RX_HASH_FUNC_TOEPLITZ
;
833 resp
.rss_caps
.rx_hash_fields_mask
=
834 MLX5_RX_HASH_SRC_IPV4
|
835 MLX5_RX_HASH_DST_IPV4
|
836 MLX5_RX_HASH_SRC_IPV6
|
837 MLX5_RX_HASH_DST_IPV6
|
838 MLX5_RX_HASH_SRC_PORT_TCP
|
839 MLX5_RX_HASH_DST_PORT_TCP
|
840 MLX5_RX_HASH_SRC_PORT_UDP
|
841 MLX5_RX_HASH_DST_PORT_UDP
|
843 resp
.response_length
+= sizeof(resp
.rss_caps
);
846 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
))
847 resp
.response_length
+= sizeof(resp
.tso_caps
);
848 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
))
849 resp
.response_length
+= sizeof(resp
.rss_caps
);
852 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
853 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
854 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
857 if (MLX5_CAP_GEN(dev
->mdev
, rq_delay_drop
) &&
858 MLX5_CAP_GEN(dev
->mdev
, general_notification_event
) &&
860 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_DELAY_DROP
;
862 if (MLX5_CAP_GEN(mdev
, ipoib_enhanced_offloads
) &&
863 MLX5_CAP_IPOIB_ENHANCED(mdev
, csum_cap
))
864 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
866 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
867 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
) &&
869 /* Legacy bit to support old userspace libraries */
870 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
871 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_SCATTER_FCS
;
874 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
875 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
877 if (MLX5_CAP_GEN(mdev
, end_pad
))
878 props
->device_cap_flags
|= IB_DEVICE_PCI_WRITE_END_PADDING
;
880 props
->vendor_part_id
= mdev
->pdev
->device
;
881 props
->hw_ver
= mdev
->pdev
->revision
;
883 props
->max_mr_size
= ~0ull;
884 props
->page_size_cap
= ~(min_page_size
- 1);
885 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
886 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
887 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
888 sizeof(struct mlx5_wqe_data_seg
);
889 max_sq_desc
= min_t(int, MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
), 512);
890 max_sq_sg
= (max_sq_desc
- sizeof(struct mlx5_wqe_ctrl_seg
) -
891 sizeof(struct mlx5_wqe_raddr_seg
)) /
892 sizeof(struct mlx5_wqe_data_seg
);
893 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
894 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
895 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
896 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
897 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
898 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
899 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
900 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
901 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
902 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
903 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
904 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
905 props
->max_srq_sge
= max_rq_sg
- 1;
906 props
->max_fast_reg_page_list_len
=
907 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
908 get_atomic_caps_qp(dev
, props
);
909 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
910 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
911 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
912 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
913 props
->max_mcast_grp
;
914 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
915 props
->max_ah
= INT_MAX
;
916 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
917 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
919 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
920 if (MLX5_CAP_GEN(mdev
, pg
))
921 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
922 props
->odp_caps
= dev
->odp_caps
;
925 if (MLX5_CAP_GEN(mdev
, cd
))
926 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
928 if (!mlx5_core_is_pf(mdev
))
929 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
931 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
932 IB_LINK_LAYER_ETHERNET
&& raw_support
) {
933 props
->rss_caps
.max_rwq_indirection_tables
=
934 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt
);
935 props
->rss_caps
.max_rwq_indirection_table_size
=
936 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
);
937 props
->rss_caps
.supported_qpts
= 1 << IB_QPT_RAW_PACKET
;
938 props
->max_wq_type_rq
=
939 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rq
);
942 if (MLX5_CAP_GEN(mdev
, tag_matching
)) {
943 props
->tm_caps
.max_rndv_hdr_size
= MLX5_TM_MAX_RNDV_MSG_SIZE
;
944 props
->tm_caps
.max_num_tags
=
945 (1 << MLX5_CAP_GEN(mdev
, log_tag_matching_list_sz
)) - 1;
946 props
->tm_caps
.flags
= IB_TM_CAP_RC
;
947 props
->tm_caps
.max_ops
=
948 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
949 props
->tm_caps
.max_sge
= MLX5_TM_MAX_SGE
;
952 if (MLX5_CAP_GEN(dev
->mdev
, cq_moderation
)) {
953 props
->cq_caps
.max_cq_moderation_count
=
955 props
->cq_caps
.max_cq_moderation_period
=
959 if (field_avail(typeof(resp
), cqe_comp_caps
, uhw
->outlen
)) {
960 resp
.cqe_comp_caps
.max_num
=
961 MLX5_CAP_GEN(dev
->mdev
, cqe_compression
) ?
962 MLX5_CAP_GEN(dev
->mdev
, cqe_compression_max_num
) : 0;
963 resp
.cqe_comp_caps
.supported_format
=
964 MLX5_IB_CQE_RES_FORMAT_HASH
|
965 MLX5_IB_CQE_RES_FORMAT_CSUM
;
966 resp
.response_length
+= sizeof(resp
.cqe_comp_caps
);
969 if (field_avail(typeof(resp
), packet_pacing_caps
, uhw
->outlen
) &&
971 if (MLX5_CAP_QOS(mdev
, packet_pacing
) &&
972 MLX5_CAP_GEN(mdev
, qos
)) {
973 resp
.packet_pacing_caps
.qp_rate_limit_max
=
974 MLX5_CAP_QOS(mdev
, packet_pacing_max_rate
);
975 resp
.packet_pacing_caps
.qp_rate_limit_min
=
976 MLX5_CAP_QOS(mdev
, packet_pacing_min_rate
);
977 resp
.packet_pacing_caps
.supported_qpts
|=
978 1 << IB_QPT_RAW_PACKET
;
980 resp
.response_length
+= sizeof(resp
.packet_pacing_caps
);
983 if (field_avail(typeof(resp
), mlx5_ib_support_multi_pkt_send_wqes
,
985 if (MLX5_CAP_ETH(mdev
, multi_pkt_send_wqe
))
986 resp
.mlx5_ib_support_multi_pkt_send_wqes
=
989 if (MLX5_CAP_ETH(mdev
, enhanced_multi_pkt_send_wqe
))
990 resp
.mlx5_ib_support_multi_pkt_send_wqes
|=
991 MLX5_IB_SUPPORT_EMPW
;
993 resp
.response_length
+=
994 sizeof(resp
.mlx5_ib_support_multi_pkt_send_wqes
);
997 if (field_avail(typeof(resp
), flags
, uhw
->outlen
)) {
998 resp
.response_length
+= sizeof(resp
.flags
);
1000 if (MLX5_CAP_GEN(mdev
, cqe_compression_128
))
1002 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP
;
1004 if (MLX5_CAP_GEN(mdev
, cqe_128_always
))
1005 resp
.flags
|= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD
;
1008 if (field_avail(typeof(resp
), sw_parsing_caps
,
1010 resp
.response_length
+= sizeof(resp
.sw_parsing_caps
);
1011 if (MLX5_CAP_ETH(mdev
, swp
)) {
1012 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1015 if (MLX5_CAP_ETH(mdev
, swp_csum
))
1016 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1017 MLX5_IB_SW_PARSING_CSUM
;
1019 if (MLX5_CAP_ETH(mdev
, swp_lso
))
1020 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1021 MLX5_IB_SW_PARSING_LSO
;
1023 if (resp
.sw_parsing_caps
.sw_parsing_offloads
)
1024 resp
.sw_parsing_caps
.supported_qpts
=
1025 BIT(IB_QPT_RAW_PACKET
);
1029 if (field_avail(typeof(resp
), striding_rq_caps
, uhw
->outlen
) &&
1031 resp
.response_length
+= sizeof(resp
.striding_rq_caps
);
1032 if (MLX5_CAP_GEN(mdev
, striding_rq
)) {
1033 resp
.striding_rq_caps
.min_single_stride_log_num_of_bytes
=
1034 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES
;
1035 resp
.striding_rq_caps
.max_single_stride_log_num_of_bytes
=
1036 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES
;
1037 resp
.striding_rq_caps
.min_single_wqe_log_num_of_strides
=
1038 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES
;
1039 resp
.striding_rq_caps
.max_single_wqe_log_num_of_strides
=
1040 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES
;
1041 resp
.striding_rq_caps
.supported_qpts
=
1042 BIT(IB_QPT_RAW_PACKET
);
1046 if (field_avail(typeof(resp
), tunnel_offloads_caps
,
1048 resp
.response_length
+= sizeof(resp
.tunnel_offloads_caps
);
1049 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_vxlan
))
1050 resp
.tunnel_offloads_caps
|=
1051 MLX5_IB_TUNNELED_OFFLOADS_VXLAN
;
1052 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_geneve_rx
))
1053 resp
.tunnel_offloads_caps
|=
1054 MLX5_IB_TUNNELED_OFFLOADS_GENEVE
;
1055 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
))
1056 resp
.tunnel_offloads_caps
|=
1057 MLX5_IB_TUNNELED_OFFLOADS_GRE
;
1061 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
1070 enum mlx5_ib_width
{
1071 MLX5_IB_WIDTH_1X
= 1 << 0,
1072 MLX5_IB_WIDTH_2X
= 1 << 1,
1073 MLX5_IB_WIDTH_4X
= 1 << 2,
1074 MLX5_IB_WIDTH_8X
= 1 << 3,
1075 MLX5_IB_WIDTH_12X
= 1 << 4
1078 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
1081 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1084 if (active_width
& MLX5_IB_WIDTH_1X
) {
1085 *ib_width
= IB_WIDTH_1X
;
1086 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
1087 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
1090 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
1091 *ib_width
= IB_WIDTH_4X
;
1092 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
1093 *ib_width
= IB_WIDTH_8X
;
1094 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
1095 *ib_width
= IB_WIDTH_12X
;
1097 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
1105 static int mlx5_mtu_to_ib_mtu(int mtu
)
1110 case 1024: return 3;
1111 case 2048: return 4;
1112 case 4096: return 5;
1114 pr_warn("invalid mtu\n");
1119 enum ib_max_vl_num
{
1121 __IB_MAX_VL_0_1
= 2,
1122 __IB_MAX_VL_0_3
= 3,
1123 __IB_MAX_VL_0_7
= 4,
1124 __IB_MAX_VL_0_14
= 5,
1127 enum mlx5_vl_hw_cap
{
1136 MLX5_VL_HW_0_14
= 15
1139 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
1142 switch (vl_hw_cap
) {
1144 *max_vl_num
= __IB_MAX_VL_0
;
1146 case MLX5_VL_HW_0_1
:
1147 *max_vl_num
= __IB_MAX_VL_0_1
;
1149 case MLX5_VL_HW_0_3
:
1150 *max_vl_num
= __IB_MAX_VL_0_3
;
1152 case MLX5_VL_HW_0_7
:
1153 *max_vl_num
= __IB_MAX_VL_0_7
;
1155 case MLX5_VL_HW_0_14
:
1156 *max_vl_num
= __IB_MAX_VL_0_14
;
1166 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
1167 struct ib_port_attr
*props
)
1169 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1170 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1171 struct mlx5_hca_vport_context
*rep
;
1175 u8 ib_link_width_oper
;
1178 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
1184 /* props being zeroed by the caller, avoid zeroing it here */
1186 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
1190 props
->lid
= rep
->lid
;
1191 props
->lmc
= rep
->lmc
;
1192 props
->sm_lid
= rep
->sm_lid
;
1193 props
->sm_sl
= rep
->sm_sl
;
1194 props
->state
= rep
->vport_state
;
1195 props
->phys_state
= rep
->port_physical_state
;
1196 props
->port_cap_flags
= rep
->cap_mask1
;
1197 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
1198 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
1199 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
1200 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
1201 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
1202 props
->subnet_timeout
= rep
->subnet_timeout
;
1203 props
->init_type_reply
= rep
->init_type_reply
;
1204 props
->grh_required
= rep
->grh_required
;
1206 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
1210 err
= translate_active_width(ibdev
, ib_link_width_oper
,
1211 &props
->active_width
);
1214 err
= mlx5_query_port_ib_proto_oper(mdev
, &props
->active_speed
, port
);
1218 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
1220 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
1222 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
1224 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
1226 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
1230 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
1231 &props
->max_vl_num
);
1237 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
1238 struct ib_port_attr
*props
)
1243 switch (mlx5_get_vport_access_method(ibdev
)) {
1244 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1245 ret
= mlx5_query_mad_ifc_port(ibdev
, port
, props
);
1248 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1249 ret
= mlx5_query_hca_port(ibdev
, port
, props
);
1252 case MLX5_VPORT_ACCESS_METHOD_NIC
:
1253 ret
= mlx5_query_port_roce(ibdev
, port
, props
);
1260 if (!ret
&& props
) {
1261 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1262 struct mlx5_core_dev
*mdev
;
1263 bool put_mdev
= true;
1265 mdev
= mlx5_ib_get_native_port_mdev(dev
, port
, NULL
);
1267 /* If the port isn't affiliated yet query the master.
1268 * The master and slave will have the same values.
1274 count
= mlx5_core_reserved_gids_count(mdev
);
1276 mlx5_ib_put_native_port_mdev(dev
, port
);
1277 props
->gid_tbl_len
-= count
;
1282 static int mlx5_ib_rep_query_port(struct ib_device
*ibdev
, u8 port
,
1283 struct ib_port_attr
*props
)
1287 /* Only link layer == ethernet is valid for representors */
1288 ret
= mlx5_query_port_roce(ibdev
, port
, props
);
1292 /* We don't support GIDS */
1293 props
->gid_tbl_len
= 0;
1298 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
1301 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1302 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1304 switch (mlx5_get_vport_access_method(ibdev
)) {
1305 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1306 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
1308 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1309 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
1317 static int mlx5_query_hca_nic_pkey(struct ib_device
*ibdev
, u8 port
,
1318 u16 index
, u16
*pkey
)
1320 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1321 struct mlx5_core_dev
*mdev
;
1322 bool put_mdev
= true;
1326 mdev
= mlx5_ib_get_native_port_mdev(dev
, port
, &mdev_port_num
);
1328 /* The port isn't affiliated yet, get the PKey from the master
1329 * port. For RoCE the PKey tables will be the same.
1336 err
= mlx5_query_hca_vport_pkey(mdev
, 0, mdev_port_num
, 0,
1339 mlx5_ib_put_native_port_mdev(dev
, port
);
1344 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
1347 switch (mlx5_get_vport_access_method(ibdev
)) {
1348 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1349 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
1351 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1352 case MLX5_VPORT_ACCESS_METHOD_NIC
:
1353 return mlx5_query_hca_nic_pkey(ibdev
, port
, index
, pkey
);
1359 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
1360 struct ib_device_modify
*props
)
1362 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1363 struct mlx5_reg_node_desc in
;
1364 struct mlx5_reg_node_desc out
;
1367 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
1370 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
1374 * If possible, pass node desc to FW, so it can generate
1375 * a 144 trap. If cmd fails, just ignore.
1377 memcpy(&in
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
1378 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
1379 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
1383 memcpy(ibdev
->node_desc
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
1388 static int set_port_caps_atomic(struct mlx5_ib_dev
*dev
, u8 port_num
, u32 mask
,
1391 struct mlx5_hca_vport_context ctx
= {};
1392 struct mlx5_core_dev
*mdev
;
1396 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
, &mdev_port_num
);
1400 err
= mlx5_query_hca_vport_context(mdev
, 0, mdev_port_num
, 0, &ctx
);
1404 if (~ctx
.cap_mask1_perm
& mask
) {
1405 mlx5_ib_warn(dev
, "trying to change bitmask 0x%X but change supported 0x%X\n",
1406 mask
, ctx
.cap_mask1_perm
);
1411 ctx
.cap_mask1
= value
;
1412 ctx
.cap_mask1_perm
= mask
;
1413 err
= mlx5_core_modify_hca_vport_context(mdev
, 0, mdev_port_num
,
1417 mlx5_ib_put_native_port_mdev(dev
, port_num
);
1422 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
1423 struct ib_port_modify
*props
)
1425 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1426 struct ib_port_attr attr
;
1431 bool is_ib
= (mlx5_ib_port_link_layer(ibdev
, port
) ==
1432 IB_LINK_LAYER_INFINIBAND
);
1434 /* CM layer calls ib_modify_port() regardless of the link layer. For
1435 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1440 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
) && is_ib
) {
1441 change_mask
= props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1442 value
= ~props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1443 return set_port_caps_atomic(dev
, port
, change_mask
, value
);
1446 mutex_lock(&dev
->cap_mask_mutex
);
1448 err
= ib_query_port(ibdev
, port
, &attr
);
1452 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
1453 ~props
->clr_port_cap_mask
;
1455 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
1458 mutex_unlock(&dev
->cap_mask_mutex
);
1462 static void print_lib_caps(struct mlx5_ib_dev
*dev
, u64 caps
)
1464 mlx5_ib_dbg(dev
, "MLX5_LIB_CAP_4K_UAR = %s\n",
1465 caps
& MLX5_LIB_CAP_4K_UAR
? "y" : "n");
1468 static u16
calc_dynamic_bfregs(int uars_per_sys_page
)
1470 /* Large page with non 4k uar support might limit the dynamic size */
1471 if (uars_per_sys_page
== 1 && PAGE_SIZE
> 4096)
1472 return MLX5_MIN_DYN_BFREGS
;
1474 return MLX5_MAX_DYN_BFREGS
;
1477 static int calc_total_bfregs(struct mlx5_ib_dev
*dev
, bool lib_uar_4k
,
1478 struct mlx5_ib_alloc_ucontext_req_v2
*req
,
1479 struct mlx5_bfreg_info
*bfregi
)
1481 int uars_per_sys_page
;
1482 int bfregs_per_sys_page
;
1483 int ref_bfregs
= req
->total_num_bfregs
;
1485 if (req
->total_num_bfregs
== 0)
1488 BUILD_BUG_ON(MLX5_MAX_BFREGS
% MLX5_NON_FP_BFREGS_IN_PAGE
);
1489 BUILD_BUG_ON(MLX5_MAX_BFREGS
< MLX5_NON_FP_BFREGS_IN_PAGE
);
1491 if (req
->total_num_bfregs
> MLX5_MAX_BFREGS
)
1494 uars_per_sys_page
= get_uars_per_sys_page(dev
, lib_uar_4k
);
1495 bfregs_per_sys_page
= uars_per_sys_page
* MLX5_NON_FP_BFREGS_PER_UAR
;
1496 /* This holds the required static allocation asked by the user */
1497 req
->total_num_bfregs
= ALIGN(req
->total_num_bfregs
, bfregs_per_sys_page
);
1498 if (req
->num_low_latency_bfregs
> req
->total_num_bfregs
- 1)
1501 bfregi
->num_static_sys_pages
= req
->total_num_bfregs
/ bfregs_per_sys_page
;
1502 bfregi
->num_dyn_bfregs
= ALIGN(calc_dynamic_bfregs(uars_per_sys_page
), bfregs_per_sys_page
);
1503 bfregi
->total_num_bfregs
= req
->total_num_bfregs
+ bfregi
->num_dyn_bfregs
;
1504 bfregi
->num_sys_pages
= bfregi
->total_num_bfregs
/ bfregs_per_sys_page
;
1506 mlx5_ib_dbg(dev
, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1507 MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? "yes" : "no",
1508 lib_uar_4k
? "yes" : "no", ref_bfregs
,
1509 req
->total_num_bfregs
, bfregi
->total_num_bfregs
,
1510 bfregi
->num_sys_pages
);
1515 static int allocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1517 struct mlx5_bfreg_info
*bfregi
;
1521 bfregi
= &context
->bfregi
;
1522 for (i
= 0; i
< bfregi
->num_static_sys_pages
; i
++) {
1523 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &bfregi
->sys_pages
[i
]);
1527 mlx5_ib_dbg(dev
, "allocated uar %d\n", bfregi
->sys_pages
[i
]);
1530 for (i
= bfregi
->num_static_sys_pages
; i
< bfregi
->num_sys_pages
; i
++)
1531 bfregi
->sys_pages
[i
] = MLX5_IB_INVALID_UAR_INDEX
;
1536 for (--i
; i
>= 0; i
--)
1537 if (mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]))
1538 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1543 static int deallocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1545 struct mlx5_bfreg_info
*bfregi
;
1549 bfregi
= &context
->bfregi
;
1550 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++) {
1551 if (i
< bfregi
->num_static_sys_pages
||
1552 bfregi
->sys_pages
[i
] != MLX5_IB_INVALID_UAR_INDEX
) {
1553 err
= mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]);
1555 mlx5_ib_warn(dev
, "failed to free uar %d, err=%d\n", i
, err
);
1564 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev
*dev
, u32
*tdn
)
1568 err
= mlx5_core_alloc_transport_domain(dev
->mdev
, tdn
);
1572 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
) ||
1573 (!MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) &&
1574 !MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
1577 mutex_lock(&dev
->lb_mutex
);
1580 if (dev
->user_td
== 2)
1581 err
= mlx5_nic_vport_update_local_lb(dev
->mdev
, true);
1583 mutex_unlock(&dev
->lb_mutex
);
1587 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev
*dev
, u32 tdn
)
1589 mlx5_core_dealloc_transport_domain(dev
->mdev
, tdn
);
1591 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
) ||
1592 (!MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) &&
1593 !MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
1596 mutex_lock(&dev
->lb_mutex
);
1599 if (dev
->user_td
< 2)
1600 mlx5_nic_vport_update_local_lb(dev
->mdev
, false);
1602 mutex_unlock(&dev
->lb_mutex
);
1605 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
1606 struct ib_udata
*udata
)
1608 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1609 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
1610 struct mlx5_ib_alloc_ucontext_resp resp
= {};
1611 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1612 struct mlx5_ib_ucontext
*context
;
1613 struct mlx5_bfreg_info
*bfregi
;
1616 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
1620 if (!dev
->ib_active
)
1621 return ERR_PTR(-EAGAIN
);
1623 if (udata
->inlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
1625 else if (udata
->inlen
>= min_req_v2
)
1628 return ERR_PTR(-EINVAL
);
1630 err
= ib_copy_from_udata(&req
, udata
, min(udata
->inlen
, sizeof(req
)));
1632 return ERR_PTR(err
);
1635 return ERR_PTR(-EINVAL
);
1637 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
1638 return ERR_PTR(-EOPNOTSUPP
);
1640 req
.total_num_bfregs
= ALIGN(req
.total_num_bfregs
,
1641 MLX5_NON_FP_BFREGS_PER_UAR
);
1642 if (req
.num_low_latency_bfregs
> req
.total_num_bfregs
- 1)
1643 return ERR_PTR(-EINVAL
);
1645 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
1646 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
1647 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
1648 resp
.cache_line_size
= cache_line_size();
1649 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
1650 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
1651 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1652 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1653 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
1654 resp
.cqe_version
= min_t(__u8
,
1655 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
1656 req
.max_cqe_version
);
1657 resp
.log_uar_size
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1658 MLX5_ADAPTER_PAGE_SHIFT
: PAGE_SHIFT
;
1659 resp
.num_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1660 MLX5_CAP_GEN(dev
->mdev
, num_of_uars_per_page
) : 1;
1661 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
1662 sizeof(resp
.response_length
), udata
->outlen
);
1664 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
1666 return ERR_PTR(-ENOMEM
);
1668 lib_uar_4k
= req
.lib_caps
& MLX5_LIB_CAP_4K_UAR
;
1669 bfregi
= &context
->bfregi
;
1671 /* updates req->total_num_bfregs */
1672 err
= calc_total_bfregs(dev
, lib_uar_4k
, &req
, bfregi
);
1676 mutex_init(&bfregi
->lock
);
1677 bfregi
->lib_uar_4k
= lib_uar_4k
;
1678 bfregi
->count
= kcalloc(bfregi
->total_num_bfregs
, sizeof(*bfregi
->count
),
1680 if (!bfregi
->count
) {
1685 bfregi
->sys_pages
= kcalloc(bfregi
->num_sys_pages
,
1686 sizeof(*bfregi
->sys_pages
),
1688 if (!bfregi
->sys_pages
) {
1693 err
= allocate_uars(dev
, context
);
1697 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1698 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
1701 context
->upd_xlt_page
= __get_free_page(GFP_KERNEL
);
1702 if (!context
->upd_xlt_page
) {
1706 mutex_init(&context
->upd_xlt_page_mutex
);
1708 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
1709 err
= mlx5_ib_alloc_transport_domain(dev
, &context
->tdn
);
1714 INIT_LIST_HEAD(&context
->vma_private_list
);
1715 mutex_init(&context
->vma_private_list_mutex
);
1716 INIT_LIST_HEAD(&context
->db_page_list
);
1717 mutex_init(&context
->db_page_mutex
);
1719 resp
.tot_bfregs
= req
.total_num_bfregs
;
1720 resp
.num_ports
= dev
->num_ports
;
1722 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1723 resp
.response_length
+= sizeof(resp
.cqe_version
);
1725 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1726 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
|
1727 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH
;
1728 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1731 if (field_avail(typeof(resp
), eth_min_inline
, udata
->outlen
)) {
1732 if (mlx5_ib_port_link_layer(ibdev
, 1) == IB_LINK_LAYER_ETHERNET
) {
1733 mlx5_query_min_inline(dev
->mdev
, &resp
.eth_min_inline
);
1734 resp
.eth_min_inline
++;
1736 resp
.response_length
+= sizeof(resp
.eth_min_inline
);
1739 if (field_avail(typeof(resp
), clock_info_versions
, udata
->outlen
)) {
1740 if (mdev
->clock_info
)
1741 resp
.clock_info_versions
= BIT(MLX5_IB_CLOCK_INFO_V1
);
1742 resp
.response_length
+= sizeof(resp
.clock_info_versions
);
1746 * We don't want to expose information from the PCI bar that is located
1747 * after 4096 bytes, so if the arch only supports larger pages, let's
1748 * pretend we don't support reading the HCA's core clock. This is also
1749 * forced by mmap function.
1751 if (field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1752 if (PAGE_SIZE
<= 4096) {
1754 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1755 resp
.hca_core_clock_offset
=
1756 offsetof(struct mlx5_init_seg
, internal_timer_h
) % PAGE_SIZE
;
1758 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
);
1761 if (field_avail(typeof(resp
), log_uar_size
, udata
->outlen
))
1762 resp
.response_length
+= sizeof(resp
.log_uar_size
);
1764 if (field_avail(typeof(resp
), num_uars_per_page
, udata
->outlen
))
1765 resp
.response_length
+= sizeof(resp
.num_uars_per_page
);
1767 if (field_avail(typeof(resp
), num_dyn_bfregs
, udata
->outlen
)) {
1768 resp
.num_dyn_bfregs
= bfregi
->num_dyn_bfregs
;
1769 resp
.response_length
+= sizeof(resp
.num_dyn_bfregs
);
1772 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1777 bfregi
->num_low_latency_bfregs
= req
.num_low_latency_bfregs
;
1778 context
->cqe_version
= resp
.cqe_version
;
1779 context
->lib_caps
= req
.lib_caps
;
1780 print_lib_caps(dev
, context
->lib_caps
);
1782 return &context
->ibucontext
;
1785 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1786 mlx5_ib_dealloc_transport_domain(dev
, context
->tdn
);
1789 free_page(context
->upd_xlt_page
);
1792 deallocate_uars(dev
, context
);
1795 kfree(bfregi
->sys_pages
);
1798 kfree(bfregi
->count
);
1803 return ERR_PTR(err
);
1806 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1808 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1809 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1810 struct mlx5_bfreg_info
*bfregi
;
1812 bfregi
= &context
->bfregi
;
1813 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1814 mlx5_ib_dealloc_transport_domain(dev
, context
->tdn
);
1816 free_page(context
->upd_xlt_page
);
1817 deallocate_uars(dev
, context
);
1818 kfree(bfregi
->sys_pages
);
1819 kfree(bfregi
->count
);
1825 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
,
1828 int fw_uars_per_page
;
1830 fw_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? MLX5_UARS_IN_PAGE
: 1;
1832 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) + uar_idx
/ fw_uars_per_page
;
1835 static int get_command(unsigned long offset
)
1837 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1840 static int get_arg(unsigned long offset
)
1842 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1845 static int get_index(unsigned long offset
)
1847 return get_arg(offset
);
1850 /* Index resides in an extra byte to enable larger values than 255 */
1851 static int get_extended_index(unsigned long offset
)
1853 return get_arg(offset
) | ((offset
>> 16) & 0xff) << 8;
1856 static void mlx5_ib_vma_open(struct vm_area_struct
*area
)
1858 /* vma_open is called when a new VMA is created on top of our VMA. This
1859 * is done through either mremap flow or split_vma (usually due to
1860 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1861 * as this VMA is strongly hardware related. Therefore we set the
1862 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1863 * calling us again and trying to do incorrect actions. We assume that
1864 * the original VMA size is exactly a single page, and therefore all
1865 * "splitting" operation will not happen to it.
1867 area
->vm_ops
= NULL
;
1870 static void mlx5_ib_vma_close(struct vm_area_struct
*area
)
1872 struct mlx5_ib_vma_private_data
*mlx5_ib_vma_priv_data
;
1874 /* It's guaranteed that all VMAs opened on a FD are closed before the
1875 * file itself is closed, therefore no sync is needed with the regular
1876 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1877 * However need a sync with accessing the vma as part of
1878 * mlx5_ib_disassociate_ucontext.
1879 * The close operation is usually called under mm->mmap_sem except when
1880 * process is exiting.
1881 * The exiting case is handled explicitly as part of
1882 * mlx5_ib_disassociate_ucontext.
1884 mlx5_ib_vma_priv_data
= (struct mlx5_ib_vma_private_data
*)area
->vm_private_data
;
1886 /* setting the vma context pointer to null in the mlx5_ib driver's
1887 * private data, to protect a race condition in
1888 * mlx5_ib_disassociate_ucontext().
1890 mlx5_ib_vma_priv_data
->vma
= NULL
;
1891 mutex_lock(mlx5_ib_vma_priv_data
->vma_private_list_mutex
);
1892 list_del(&mlx5_ib_vma_priv_data
->list
);
1893 mutex_unlock(mlx5_ib_vma_priv_data
->vma_private_list_mutex
);
1894 kfree(mlx5_ib_vma_priv_data
);
1897 static const struct vm_operations_struct mlx5_ib_vm_ops
= {
1898 .open
= mlx5_ib_vma_open
,
1899 .close
= mlx5_ib_vma_close
1902 static int mlx5_ib_set_vma_data(struct vm_area_struct
*vma
,
1903 struct mlx5_ib_ucontext
*ctx
)
1905 struct mlx5_ib_vma_private_data
*vma_prv
;
1906 struct list_head
*vma_head
= &ctx
->vma_private_list
;
1908 vma_prv
= kzalloc(sizeof(*vma_prv
), GFP_KERNEL
);
1913 vma_prv
->vma_private_list_mutex
= &ctx
->vma_private_list_mutex
;
1914 vma
->vm_private_data
= vma_prv
;
1915 vma
->vm_ops
= &mlx5_ib_vm_ops
;
1917 mutex_lock(&ctx
->vma_private_list_mutex
);
1918 list_add(&vma_prv
->list
, vma_head
);
1919 mutex_unlock(&ctx
->vma_private_list_mutex
);
1924 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
1927 struct vm_area_struct
*vma
;
1928 struct mlx5_ib_vma_private_data
*vma_private
, *n
;
1929 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1930 struct task_struct
*owning_process
= NULL
;
1931 struct mm_struct
*owning_mm
= NULL
;
1933 owning_process
= get_pid_task(ibcontext
->tgid
, PIDTYPE_PID
);
1934 if (!owning_process
)
1937 owning_mm
= get_task_mm(owning_process
);
1939 pr_info("no mm, disassociate ucontext is pending task termination\n");
1941 put_task_struct(owning_process
);
1942 usleep_range(1000, 2000);
1943 owning_process
= get_pid_task(ibcontext
->tgid
,
1945 if (!owning_process
||
1946 owning_process
->state
== TASK_DEAD
) {
1947 pr_info("disassociate ucontext done, task was terminated\n");
1948 /* in case task was dead need to release the
1952 put_task_struct(owning_process
);
1958 /* need to protect from a race on closing the vma as part of
1959 * mlx5_ib_vma_close.
1961 down_write(&owning_mm
->mmap_sem
);
1962 mutex_lock(&context
->vma_private_list_mutex
);
1963 list_for_each_entry_safe(vma_private
, n
, &context
->vma_private_list
,
1965 vma
= vma_private
->vma
;
1966 ret
= zap_vma_ptes(vma
, vma
->vm_start
,
1968 WARN_ONCE(ret
, "%s: zap_vma_ptes failed", __func__
);
1969 /* context going to be destroyed, should
1970 * not access ops any more.
1972 vma
->vm_flags
&= ~(VM_SHARED
| VM_MAYSHARE
);
1974 list_del(&vma_private
->list
);
1977 mutex_unlock(&context
->vma_private_list_mutex
);
1978 up_write(&owning_mm
->mmap_sem
);
1980 put_task_struct(owning_process
);
1983 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1986 case MLX5_IB_MMAP_WC_PAGE
:
1988 case MLX5_IB_MMAP_REGULAR_PAGE
:
1989 return "best effort WC";
1990 case MLX5_IB_MMAP_NC_PAGE
:
1997 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev
*dev
,
1998 struct vm_area_struct
*vma
,
1999 struct mlx5_ib_ucontext
*context
)
2004 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2007 if (get_index(vma
->vm_pgoff
) != MLX5_IB_CLOCK_INFO_V1
)
2010 if (vma
->vm_flags
& VM_WRITE
)
2013 if (!dev
->mdev
->clock_info_page
)
2016 pfn
= page_to_pfn(dev
->mdev
->clock_info_page
);
2017 err
= remap_pfn_range(vma
, vma
->vm_start
, pfn
, PAGE_SIZE
,
2022 mlx5_ib_dbg(dev
, "mapped clock info at 0x%lx, PA 0x%llx\n",
2024 (unsigned long long)pfn
<< PAGE_SHIFT
);
2026 return mlx5_ib_set_vma_data(vma
, context
);
2029 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
2030 struct vm_area_struct
*vma
,
2031 struct mlx5_ib_ucontext
*context
)
2033 struct mlx5_bfreg_info
*bfregi
= &context
->bfregi
;
2036 phys_addr_t pfn
, pa
;
2038 u32 bfreg_dyn_idx
= 0;
2040 int dyn_uar
= (cmd
== MLX5_IB_MMAP_ALLOC_WC
);
2041 int max_valid_idx
= dyn_uar
? bfregi
->num_sys_pages
:
2042 bfregi
->num_static_sys_pages
;
2044 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2048 idx
= get_extended_index(vma
->vm_pgoff
) + bfregi
->num_static_sys_pages
;
2050 idx
= get_index(vma
->vm_pgoff
);
2052 if (idx
>= max_valid_idx
) {
2053 mlx5_ib_warn(dev
, "invalid uar index %lu, max=%d\n",
2054 idx
, max_valid_idx
);
2059 case MLX5_IB_MMAP_WC_PAGE
:
2060 case MLX5_IB_MMAP_ALLOC_WC
:
2061 /* Some architectures don't support WC memory */
2062 #if defined(CONFIG_X86)
2065 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2069 case MLX5_IB_MMAP_REGULAR_PAGE
:
2070 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2071 prot
= pgprot_writecombine(vma
->vm_page_prot
);
2073 case MLX5_IB_MMAP_NC_PAGE
:
2074 prot
= pgprot_noncached(vma
->vm_page_prot
);
2083 uars_per_page
= get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
);
2084 bfreg_dyn_idx
= idx
* (uars_per_page
* MLX5_NON_FP_BFREGS_PER_UAR
);
2085 if (bfreg_dyn_idx
>= bfregi
->total_num_bfregs
) {
2086 mlx5_ib_warn(dev
, "invalid bfreg_dyn_idx %u, max=%u\n",
2087 bfreg_dyn_idx
, bfregi
->total_num_bfregs
);
2091 mutex_lock(&bfregi
->lock
);
2092 /* Fail if uar already allocated, first bfreg index of each
2093 * page holds its count.
2095 if (bfregi
->count
[bfreg_dyn_idx
]) {
2096 mlx5_ib_warn(dev
, "wrong offset, idx %lu is busy, bfregn=%u\n", idx
, bfreg_dyn_idx
);
2097 mutex_unlock(&bfregi
->lock
);
2101 bfregi
->count
[bfreg_dyn_idx
]++;
2102 mutex_unlock(&bfregi
->lock
);
2104 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uar_index
);
2106 mlx5_ib_warn(dev
, "UAR alloc failed\n");
2110 uar_index
= bfregi
->sys_pages
[idx
];
2113 pfn
= uar_index2pfn(dev
, uar_index
);
2114 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
2116 vma
->vm_page_prot
= prot
;
2117 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
2118 PAGE_SIZE
, vma
->vm_page_prot
);
2120 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
2121 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
2126 pa
= pfn
<< PAGE_SHIFT
;
2127 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
2128 vma
->vm_start
, &pa
);
2130 err
= mlx5_ib_set_vma_data(vma
, context
);
2135 bfregi
->sys_pages
[idx
] = uar_index
;
2142 mlx5_cmd_free_uar(dev
->mdev
, idx
);
2145 mlx5_ib_free_bfreg(dev
, bfregi
, bfreg_dyn_idx
);
2150 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
2152 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
2153 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
2154 unsigned long command
;
2157 command
= get_command(vma
->vm_pgoff
);
2159 case MLX5_IB_MMAP_WC_PAGE
:
2160 case MLX5_IB_MMAP_NC_PAGE
:
2161 case MLX5_IB_MMAP_REGULAR_PAGE
:
2162 case MLX5_IB_MMAP_ALLOC_WC
:
2163 return uar_mmap(dev
, command
, vma
, context
);
2165 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
2168 case MLX5_IB_MMAP_CORE_CLOCK
:
2169 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2172 if (vma
->vm_flags
& VM_WRITE
)
2175 /* Don't expose to user-space information it shouldn't have */
2176 if (PAGE_SIZE
> 4096)
2179 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
2180 pfn
= (dev
->mdev
->iseg_base
+
2181 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
2183 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
2184 PAGE_SIZE
, vma
->vm_page_prot
))
2187 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
2189 (unsigned long long)pfn
<< PAGE_SHIFT
);
2191 case MLX5_IB_MMAP_CLOCK_INFO
:
2192 return mlx5_ib_mmap_clock_info_page(dev
, vma
, context
);
2201 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
2202 struct ib_ucontext
*context
,
2203 struct ib_udata
*udata
)
2205 struct mlx5_ib_alloc_pd_resp resp
;
2206 struct mlx5_ib_pd
*pd
;
2209 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
2211 return ERR_PTR(-ENOMEM
);
2213 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
2216 return ERR_PTR(err
);
2221 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
2222 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
2224 return ERR_PTR(-EFAULT
);
2231 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
2233 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
2234 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
2236 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
2243 MATCH_CRITERIA_ENABLE_OUTER_BIT
,
2244 MATCH_CRITERIA_ENABLE_MISC_BIT
,
2245 MATCH_CRITERIA_ENABLE_INNER_BIT
2248 #define HEADER_IS_ZERO(match_criteria, headers) \
2249 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2250 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2252 static u8 get_match_criteria_enable(u32 *match_criteria)
2254 u8 match_criteria_enable
;
2256 match_criteria_enable
=
2257 (!HEADER_IS_ZERO(match_criteria
, outer_headers
)) <<
2258 MATCH_CRITERIA_ENABLE_OUTER_BIT
;
2259 match_criteria_enable
|=
2260 (!HEADER_IS_ZERO(match_criteria
, misc_parameters
)) <<
2261 MATCH_CRITERIA_ENABLE_MISC_BIT
;
2262 match_criteria_enable
|=
2263 (!HEADER_IS_ZERO(match_criteria
, inner_headers
)) <<
2264 MATCH_CRITERIA_ENABLE_INNER_BIT
;
2266 return match_criteria_enable
;
2269 static void set_proto(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
2271 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_protocol
, mask
);
2272 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_protocol
, val
);
2275 static void set_flow_label(void *misc_c
, void *misc_v
, u8 mask
, u8 val
,
2279 MLX5_SET(fte_match_set_misc
,
2280 misc_c
, inner_ipv6_flow_label
, mask
);
2281 MLX5_SET(fte_match_set_misc
,
2282 misc_v
, inner_ipv6_flow_label
, val
);
2284 MLX5_SET(fte_match_set_misc
,
2285 misc_c
, outer_ipv6_flow_label
, mask
);
2286 MLX5_SET(fte_match_set_misc
,
2287 misc_v
, outer_ipv6_flow_label
, val
);
2291 static void set_tos(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
2293 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_ecn
, mask
);
2294 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_ecn
, val
);
2295 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_dscp
, mask
>> 2);
2296 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_dscp
, val
>> 2);
2299 #define LAST_ETH_FIELD vlan_tag
2300 #define LAST_IB_FIELD sl
2301 #define LAST_IPV4_FIELD tos
2302 #define LAST_IPV6_FIELD traffic_class
2303 #define LAST_TCP_UDP_FIELD src_port
2304 #define LAST_TUNNEL_FIELD tunnel_id
2305 #define LAST_FLOW_TAG_FIELD tag_id
2306 #define LAST_DROP_FIELD size
2308 /* Field is the last supported field */
2309 #define FIELDS_NOT_SUPPORTED(filter, field)\
2310 memchr_inv((void *)&filter.field +\
2311 sizeof(filter.field), 0,\
2313 offsetof(typeof(filter), field) -\
2314 sizeof(filter.field))
2316 static int parse_flow_attr(struct mlx5_core_dev
*mdev
, u32
*match_c
,
2317 u32
*match_v
, const union ib_flow_spec
*ib_spec
,
2318 struct mlx5_flow_act
*action
)
2320 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2322 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2328 if (ib_spec
->type
& IB_FLOW_SPEC_INNER
) {
2329 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2331 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2333 match_ipv
= MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2334 ft_field_support
.inner_ip_version
);
2336 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2338 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2340 match_ipv
= MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2341 ft_field_support
.outer_ip_version
);
2344 switch (ib_spec
->type
& ~IB_FLOW_SPEC_INNER
) {
2345 case IB_FLOW_SPEC_ETH
:
2346 if (FIELDS_NOT_SUPPORTED(ib_spec
->eth
.mask
, LAST_ETH_FIELD
))
2349 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2351 ib_spec
->eth
.mask
.dst_mac
);
2352 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2354 ib_spec
->eth
.val
.dst_mac
);
2356 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2358 ib_spec
->eth
.mask
.src_mac
);
2359 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2361 ib_spec
->eth
.val
.src_mac
);
2363 if (ib_spec
->eth
.mask
.vlan_tag
) {
2364 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2366 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2369 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2370 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
2371 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2372 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
2374 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2376 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
2377 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2379 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
2381 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2383 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
2384 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2386 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
2388 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2389 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
2390 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2391 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
2393 case IB_FLOW_SPEC_IPV4
:
2394 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv4
.mask
, LAST_IPV4_FIELD
))
2398 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2400 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2401 ip_version
, MLX5_FS_IPV4_VERSION
);
2403 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2405 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2406 ethertype
, ETH_P_IP
);
2409 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2410 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
2411 &ib_spec
->ipv4
.mask
.src_ip
,
2412 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
2413 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2414 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
2415 &ib_spec
->ipv4
.val
.src_ip
,
2416 sizeof(ib_spec
->ipv4
.val
.src_ip
));
2417 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2418 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
2419 &ib_spec
->ipv4
.mask
.dst_ip
,
2420 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
2421 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2422 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
2423 &ib_spec
->ipv4
.val
.dst_ip
,
2424 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
2426 set_tos(headers_c
, headers_v
,
2427 ib_spec
->ipv4
.mask
.tos
, ib_spec
->ipv4
.val
.tos
);
2429 set_proto(headers_c
, headers_v
,
2430 ib_spec
->ipv4
.mask
.proto
, ib_spec
->ipv4
.val
.proto
);
2432 case IB_FLOW_SPEC_IPV6
:
2433 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv6
.mask
, LAST_IPV6_FIELD
))
2437 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2439 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2440 ip_version
, MLX5_FS_IPV6_VERSION
);
2442 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2444 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2445 ethertype
, ETH_P_IPV6
);
2448 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2449 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
2450 &ib_spec
->ipv6
.mask
.src_ip
,
2451 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
2452 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2453 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
2454 &ib_spec
->ipv6
.val
.src_ip
,
2455 sizeof(ib_spec
->ipv6
.val
.src_ip
));
2456 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2457 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
2458 &ib_spec
->ipv6
.mask
.dst_ip
,
2459 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
2460 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2461 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
2462 &ib_spec
->ipv6
.val
.dst_ip
,
2463 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
2465 set_tos(headers_c
, headers_v
,
2466 ib_spec
->ipv6
.mask
.traffic_class
,
2467 ib_spec
->ipv6
.val
.traffic_class
);
2469 set_proto(headers_c
, headers_v
,
2470 ib_spec
->ipv6
.mask
.next_hdr
,
2471 ib_spec
->ipv6
.val
.next_hdr
);
2473 set_flow_label(misc_params_c
, misc_params_v
,
2474 ntohl(ib_spec
->ipv6
.mask
.flow_label
),
2475 ntohl(ib_spec
->ipv6
.val
.flow_label
),
2476 ib_spec
->type
& IB_FLOW_SPEC_INNER
);
2479 case IB_FLOW_SPEC_TCP
:
2480 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
2481 LAST_TCP_UDP_FIELD
))
2484 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
2486 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
2489 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_sport
,
2490 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
2491 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_sport
,
2492 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
2494 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_dport
,
2495 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
2496 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_dport
,
2497 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
2499 case IB_FLOW_SPEC_UDP
:
2500 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
2501 LAST_TCP_UDP_FIELD
))
2504 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
2506 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
2509 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_sport
,
2510 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
2511 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_sport
,
2512 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
2514 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_dport
,
2515 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
2516 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_dport
,
2517 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
2519 case IB_FLOW_SPEC_VXLAN_TUNNEL
:
2520 if (FIELDS_NOT_SUPPORTED(ib_spec
->tunnel
.mask
,
2524 MLX5_SET(fte_match_set_misc
, misc_params_c
, vxlan_vni
,
2525 ntohl(ib_spec
->tunnel
.mask
.tunnel_id
));
2526 MLX5_SET(fte_match_set_misc
, misc_params_v
, vxlan_vni
,
2527 ntohl(ib_spec
->tunnel
.val
.tunnel_id
));
2529 case IB_FLOW_SPEC_ACTION_TAG
:
2530 if (FIELDS_NOT_SUPPORTED(ib_spec
->flow_tag
,
2531 LAST_FLOW_TAG_FIELD
))
2533 if (ib_spec
->flow_tag
.tag_id
>= BIT(24))
2536 action
->flow_tag
= ib_spec
->flow_tag
.tag_id
;
2537 action
->has_flow_tag
= true;
2539 case IB_FLOW_SPEC_ACTION_DROP
:
2540 if (FIELDS_NOT_SUPPORTED(ib_spec
->drop
,
2543 action
->action
|= MLX5_FLOW_CONTEXT_ACTION_DROP
;
2552 /* If a flow could catch both multicast and unicast packets,
2553 * it won't fall into the multicast flow steering table and this rule
2554 * could steal other multicast packets.
2556 static bool flow_is_multicast_only(const struct ib_flow_attr
*ib_attr
)
2558 union ib_flow_spec
*flow_spec
;
2560 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
2561 ib_attr
->num_of_specs
< 1)
2564 flow_spec
= (union ib_flow_spec
*)(ib_attr
+ 1);
2565 if (flow_spec
->type
== IB_FLOW_SPEC_IPV4
) {
2566 struct ib_flow_spec_ipv4
*ipv4_spec
;
2568 ipv4_spec
= (struct ib_flow_spec_ipv4
*)flow_spec
;
2569 if (ipv4_is_multicast(ipv4_spec
->val
.dst_ip
))
2575 if (flow_spec
->type
== IB_FLOW_SPEC_ETH
) {
2576 struct ib_flow_spec_eth
*eth_spec
;
2578 eth_spec
= (struct ib_flow_spec_eth
*)flow_spec
;
2579 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
2580 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
2586 static bool is_valid_ethertype(struct mlx5_core_dev
*mdev
,
2587 const struct ib_flow_attr
*flow_attr
,
2590 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
2591 int match_ipv
= check_inner
?
2592 MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2593 ft_field_support
.inner_ip_version
) :
2594 MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2595 ft_field_support
.outer_ip_version
);
2596 int inner_bit
= check_inner
? IB_FLOW_SPEC_INNER
: 0;
2597 bool ipv4_spec_valid
, ipv6_spec_valid
;
2598 unsigned int ip_spec_type
= 0;
2599 bool has_ethertype
= false;
2600 unsigned int spec_index
;
2601 bool mask_valid
= true;
2605 /* Validate that ethertype is correct */
2606 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
2607 if ((ib_spec
->type
== (IB_FLOW_SPEC_ETH
| inner_bit
)) &&
2608 ib_spec
->eth
.mask
.ether_type
) {
2609 mask_valid
= (ib_spec
->eth
.mask
.ether_type
==
2611 has_ethertype
= true;
2612 eth_type
= ntohs(ib_spec
->eth
.val
.ether_type
);
2613 } else if ((ib_spec
->type
== (IB_FLOW_SPEC_IPV4
| inner_bit
)) ||
2614 (ib_spec
->type
== (IB_FLOW_SPEC_IPV6
| inner_bit
))) {
2615 ip_spec_type
= ib_spec
->type
;
2617 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
2620 type_valid
= (!has_ethertype
) || (!ip_spec_type
);
2621 if (!type_valid
&& mask_valid
) {
2622 ipv4_spec_valid
= (eth_type
== ETH_P_IP
) &&
2623 (ip_spec_type
== (IB_FLOW_SPEC_IPV4
| inner_bit
));
2624 ipv6_spec_valid
= (eth_type
== ETH_P_IPV6
) &&
2625 (ip_spec_type
== (IB_FLOW_SPEC_IPV6
| inner_bit
));
2627 type_valid
= (ipv4_spec_valid
) || (ipv6_spec_valid
) ||
2628 (((eth_type
== ETH_P_MPLS_UC
) ||
2629 (eth_type
== ETH_P_MPLS_MC
)) && match_ipv
);
2635 static bool is_valid_attr(struct mlx5_core_dev
*mdev
,
2636 const struct ib_flow_attr
*flow_attr
)
2638 return is_valid_ethertype(mdev
, flow_attr
, false) &&
2639 is_valid_ethertype(mdev
, flow_attr
, true);
2642 static void put_flow_table(struct mlx5_ib_dev
*dev
,
2643 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
2645 prio
->refcount
-= !!ft_added
;
2646 if (!prio
->refcount
) {
2647 mlx5_destroy_flow_table(prio
->flow_table
);
2648 prio
->flow_table
= NULL
;
2652 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
2654 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
2655 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
2656 struct mlx5_ib_flow_handler
,
2658 struct mlx5_ib_flow_handler
*iter
, *tmp
;
2660 mutex_lock(&dev
->flow_db
->lock
);
2662 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
2663 mlx5_del_flow_rules(iter
->rule
);
2664 put_flow_table(dev
, iter
->prio
, true);
2665 list_del(&iter
->list
);
2669 mlx5_del_flow_rules(handler
->rule
);
2670 put_flow_table(dev
, handler
->prio
, true);
2671 mutex_unlock(&dev
->flow_db
->lock
);
2678 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
2686 enum flow_table_type
{
2691 #define MLX5_FS_MAX_TYPES 6
2692 #define MLX5_FS_MAX_ENTRIES BIT(16)
2693 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
2694 struct ib_flow_attr
*flow_attr
,
2695 enum flow_table_type ft_type
)
2697 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
2698 struct mlx5_flow_namespace
*ns
= NULL
;
2699 struct mlx5_ib_flow_prio
*prio
;
2700 struct mlx5_flow_table
*ft
;
2707 max_table_size
= BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
2709 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
2710 if (flow_is_multicast_only(flow_attr
) &&
2712 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
2714 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
2716 ns
= mlx5_get_flow_namespace(dev
->mdev
,
2717 MLX5_FLOW_NAMESPACE_BYPASS
);
2718 num_entries
= MLX5_FS_MAX_ENTRIES
;
2719 num_groups
= MLX5_FS_MAX_TYPES
;
2720 prio
= &dev
->flow_db
->prios
[priority
];
2721 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2722 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
2723 ns
= mlx5_get_flow_namespace(dev
->mdev
,
2724 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
2725 build_leftovers_ft_param(&priority
,
2728 prio
= &dev
->flow_db
->prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
2729 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2730 if (!MLX5_CAP_FLOWTABLE(dev
->mdev
,
2731 allow_sniffer_and_nic_rx_shared_tir
))
2732 return ERR_PTR(-ENOTSUPP
);
2734 ns
= mlx5_get_flow_namespace(dev
->mdev
, ft_type
== MLX5_IB_FT_RX
?
2735 MLX5_FLOW_NAMESPACE_SNIFFER_RX
:
2736 MLX5_FLOW_NAMESPACE_SNIFFER_TX
);
2738 prio
= &dev
->flow_db
->sniffer
[ft_type
];
2745 return ERR_PTR(-ENOTSUPP
);
2747 if (num_entries
> max_table_size
)
2748 return ERR_PTR(-ENOMEM
);
2750 ft
= prio
->flow_table
;
2752 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
2759 prio
->flow_table
= ft
;
2765 return err
? ERR_PTR(err
) : prio
;
2768 static void set_underlay_qp(struct mlx5_ib_dev
*dev
,
2769 struct mlx5_flow_spec
*spec
,
2772 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
,
2773 spec
->match_criteria
,
2775 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, spec
->match_value
,
2779 MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
2780 ft_field_support
.bth_dst_qp
)) {
2781 MLX5_SET(fte_match_set_misc
,
2782 misc_params_v
, bth_dst_qp
, underlay_qpn
);
2783 MLX5_SET(fte_match_set_misc
,
2784 misc_params_c
, bth_dst_qp
, 0xffffff);
2788 static struct mlx5_ib_flow_handler
*_create_flow_rule(struct mlx5_ib_dev
*dev
,
2789 struct mlx5_ib_flow_prio
*ft_prio
,
2790 const struct ib_flow_attr
*flow_attr
,
2791 struct mlx5_flow_destination
*dst
,
2794 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
2795 struct mlx5_ib_flow_handler
*handler
;
2796 struct mlx5_flow_act flow_act
= {.flow_tag
= MLX5_FS_DEFAULT_FLOW_TAG
};
2797 struct mlx5_flow_spec
*spec
;
2798 struct mlx5_flow_destination
*rule_dst
= dst
;
2799 const void *ib_flow
= (const void *)flow_attr
+ sizeof(*flow_attr
);
2800 unsigned int spec_index
;
2804 if (!is_valid_attr(dev
->mdev
, flow_attr
))
2805 return ERR_PTR(-EINVAL
);
2807 spec
= kvzalloc(sizeof(*spec
), GFP_KERNEL
);
2808 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
2809 if (!handler
|| !spec
) {
2814 INIT_LIST_HEAD(&handler
->list
);
2816 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
2817 err
= parse_flow_attr(dev
->mdev
, spec
->match_criteria
,
2819 ib_flow
, &flow_act
);
2823 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
2826 if (!flow_is_multicast_only(flow_attr
))
2827 set_underlay_qp(dev
, spec
, underlay_qpn
);
2832 misc
= MLX5_ADDR_OF(fte_match_param
, spec
->match_value
,
2834 MLX5_SET(fte_match_set_misc
, misc
, source_port
,
2836 misc
= MLX5_ADDR_OF(fte_match_param
, spec
->match_criteria
,
2838 MLX5_SET_TO_ONES(fte_match_set_misc
, misc
, source_port
);
2841 spec
->match_criteria_enable
= get_match_criteria_enable(spec
->match_criteria
);
2842 if (flow_act
.action
& MLX5_FLOW_CONTEXT_ACTION_DROP
) {
2846 flow_act
.action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
2847 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
2850 if (flow_act
.has_flow_tag
&&
2851 (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2852 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
)) {
2853 mlx5_ib_warn(dev
, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2854 flow_act
.flow_tag
, flow_attr
->type
);
2858 handler
->rule
= mlx5_add_flow_rules(ft
, spec
,
2860 rule_dst
, dest_num
);
2862 if (IS_ERR(handler
->rule
)) {
2863 err
= PTR_ERR(handler
->rule
);
2867 ft_prio
->refcount
++;
2868 handler
->prio
= ft_prio
;
2870 ft_prio
->flow_table
= ft
;
2875 return err
? ERR_PTR(err
) : handler
;
2878 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
2879 struct mlx5_ib_flow_prio
*ft_prio
,
2880 const struct ib_flow_attr
*flow_attr
,
2881 struct mlx5_flow_destination
*dst
)
2883 return _create_flow_rule(dev
, ft_prio
, flow_attr
, dst
, 0);
2886 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
2887 struct mlx5_ib_flow_prio
*ft_prio
,
2888 struct ib_flow_attr
*flow_attr
,
2889 struct mlx5_flow_destination
*dst
)
2891 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
2892 struct mlx5_ib_flow_handler
*handler
= NULL
;
2894 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
2895 if (!IS_ERR(handler
)) {
2896 handler_dst
= create_flow_rule(dev
, ft_prio
,
2898 if (IS_ERR(handler_dst
)) {
2899 mlx5_del_flow_rules(handler
->rule
);
2900 ft_prio
->refcount
--;
2902 handler
= handler_dst
;
2904 list_add(&handler_dst
->list
, &handler
->list
);
2915 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
2916 struct mlx5_ib_flow_prio
*ft_prio
,
2917 struct ib_flow_attr
*flow_attr
,
2918 struct mlx5_flow_destination
*dst
)
2920 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
2921 struct mlx5_ib_flow_handler
*handler
= NULL
;
2924 struct ib_flow_attr flow_attr
;
2925 struct ib_flow_spec_eth eth_flow
;
2926 } leftovers_specs
[] = {
2930 .size
= sizeof(leftovers_specs
[0])
2933 .type
= IB_FLOW_SPEC_ETH
,
2934 .size
= sizeof(struct ib_flow_spec_eth
),
2935 .mask
= {.dst_mac
= {0x1} },
2936 .val
= {.dst_mac
= {0x1} }
2942 .size
= sizeof(leftovers_specs
[0])
2945 .type
= IB_FLOW_SPEC_ETH
,
2946 .size
= sizeof(struct ib_flow_spec_eth
),
2947 .mask
= {.dst_mac
= {0x1} },
2948 .val
= {.dst_mac
= {} }
2953 handler
= create_flow_rule(dev
, ft_prio
,
2954 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
2956 if (!IS_ERR(handler
) &&
2957 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
2958 handler_ucast
= create_flow_rule(dev
, ft_prio
,
2959 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
2961 if (IS_ERR(handler_ucast
)) {
2962 mlx5_del_flow_rules(handler
->rule
);
2963 ft_prio
->refcount
--;
2965 handler
= handler_ucast
;
2967 list_add(&handler_ucast
->list
, &handler
->list
);
2974 static struct mlx5_ib_flow_handler
*create_sniffer_rule(struct mlx5_ib_dev
*dev
,
2975 struct mlx5_ib_flow_prio
*ft_rx
,
2976 struct mlx5_ib_flow_prio
*ft_tx
,
2977 struct mlx5_flow_destination
*dst
)
2979 struct mlx5_ib_flow_handler
*handler_rx
;
2980 struct mlx5_ib_flow_handler
*handler_tx
;
2982 static const struct ib_flow_attr flow_attr
= {
2984 .size
= sizeof(flow_attr
)
2987 handler_rx
= create_flow_rule(dev
, ft_rx
, &flow_attr
, dst
);
2988 if (IS_ERR(handler_rx
)) {
2989 err
= PTR_ERR(handler_rx
);
2993 handler_tx
= create_flow_rule(dev
, ft_tx
, &flow_attr
, dst
);
2994 if (IS_ERR(handler_tx
)) {
2995 err
= PTR_ERR(handler_tx
);
2999 list_add(&handler_tx
->list
, &handler_rx
->list
);
3004 mlx5_del_flow_rules(handler_rx
->rule
);
3008 return ERR_PTR(err
);
3011 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
3012 struct ib_flow_attr
*flow_attr
,
3015 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
3016 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
3017 struct mlx5_ib_flow_handler
*handler
= NULL
;
3018 struct mlx5_flow_destination
*dst
= NULL
;
3019 struct mlx5_ib_flow_prio
*ft_prio_tx
= NULL
;
3020 struct mlx5_ib_flow_prio
*ft_prio
;
3024 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
3025 return ERR_PTR(-ENOMEM
);
3027 if (domain
!= IB_FLOW_DOMAIN_USER
||
3028 flow_attr
->port
> dev
->num_ports
||
3029 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
3030 return ERR_PTR(-EINVAL
);
3032 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
3034 return ERR_PTR(-ENOMEM
);
3036 mutex_lock(&dev
->flow_db
->lock
);
3038 ft_prio
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_RX
);
3039 if (IS_ERR(ft_prio
)) {
3040 err
= PTR_ERR(ft_prio
);
3043 if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
3044 ft_prio_tx
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_TX
);
3045 if (IS_ERR(ft_prio_tx
)) {
3046 err
= PTR_ERR(ft_prio_tx
);
3052 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
3053 if (mqp
->flags
& MLX5_IB_QP_RSS
)
3054 dst
->tir_num
= mqp
->rss_qp
.tirn
;
3056 dst
->tir_num
= mqp
->raw_packet_qp
.rq
.tirn
;
3058 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
3059 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
3060 handler
= create_dont_trap_rule(dev
, ft_prio
,
3063 underlay_qpn
= (mqp
->flags
& MLX5_IB_QP_UNDERLAY
) ?
3064 mqp
->underlay_qpn
: 0;
3065 handler
= _create_flow_rule(dev
, ft_prio
, flow_attr
,
3068 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
3069 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
3070 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
3072 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
3073 handler
= create_sniffer_rule(dev
, ft_prio
, ft_prio_tx
, dst
);
3079 if (IS_ERR(handler
)) {
3080 err
= PTR_ERR(handler
);
3085 mutex_unlock(&dev
->flow_db
->lock
);
3088 return &handler
->ibflow
;
3091 put_flow_table(dev
, ft_prio
, false);
3093 put_flow_table(dev
, ft_prio_tx
, false);
3095 mutex_unlock(&dev
->flow_db
->lock
);
3098 return ERR_PTR(err
);
3101 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
3103 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3104 struct mlx5_ib_qp
*mqp
= to_mqp(ibqp
);
3107 if (mqp
->flags
& MLX5_IB_QP_UNDERLAY
) {
3108 mlx5_ib_dbg(dev
, "Attaching a multi cast group to underlay QP is not supported\n");
3112 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
3114 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
3115 ibqp
->qp_num
, gid
->raw
);
3120 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
3122 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3125 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
3127 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
3128 ibqp
->qp_num
, gid
->raw
);
3133 static int init_node_data(struct mlx5_ib_dev
*dev
)
3137 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
3141 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
3143 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
3146 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
3149 struct mlx5_ib_dev
*dev
=
3150 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
3152 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
3155 static ssize_t
show_reg_pages(struct device
*device
,
3156 struct device_attribute
*attr
, char *buf
)
3158 struct mlx5_ib_dev
*dev
=
3159 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
3161 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
3164 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
3167 struct mlx5_ib_dev
*dev
=
3168 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
3169 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
3172 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
3175 struct mlx5_ib_dev
*dev
=
3176 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
3177 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
3180 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
3183 struct mlx5_ib_dev
*dev
=
3184 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
3185 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
3186 dev
->mdev
->board_id
);
3189 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
3190 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
3191 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
3192 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
3193 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
3195 static struct device_attribute
*mlx5_class_attributes
[] = {
3200 &dev_attr_reg_pages
,
3203 static void pkey_change_handler(struct work_struct
*work
)
3205 struct mlx5_ib_port_resources
*ports
=
3206 container_of(work
, struct mlx5_ib_port_resources
,
3209 mutex_lock(&ports
->devr
->mutex
);
3210 mlx5_ib_gsi_pkey_change(ports
->gsi
);
3211 mutex_unlock(&ports
->devr
->mutex
);
3214 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
3216 struct mlx5_ib_qp
*mqp
;
3217 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
3218 struct mlx5_core_cq
*mcq
;
3219 struct list_head cq_armed_list
;
3220 unsigned long flags_qp
;
3221 unsigned long flags_cq
;
3222 unsigned long flags
;
3224 INIT_LIST_HEAD(&cq_armed_list
);
3226 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
3227 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
3228 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
3229 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
3230 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
3231 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
3232 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
3233 if (send_mcq
->mcq
.comp
&&
3234 mqp
->ibqp
.send_cq
->comp_handler
) {
3235 if (!send_mcq
->mcq
.reset_notify_added
) {
3236 send_mcq
->mcq
.reset_notify_added
= 1;
3237 list_add_tail(&send_mcq
->mcq
.reset_notify
,
3241 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
3243 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
3244 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
3245 /* no handling is needed for SRQ */
3246 if (!mqp
->ibqp
.srq
) {
3247 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
3248 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
3249 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
3250 if (recv_mcq
->mcq
.comp
&&
3251 mqp
->ibqp
.recv_cq
->comp_handler
) {
3252 if (!recv_mcq
->mcq
.reset_notify_added
) {
3253 recv_mcq
->mcq
.reset_notify_added
= 1;
3254 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
3258 spin_unlock_irqrestore(&recv_mcq
->lock
,
3262 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
3264 /*At that point all inflight post send were put to be executed as of we
3265 * lock/unlock above locks Now need to arm all involved CQs.
3267 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
3270 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
3273 static void delay_drop_handler(struct work_struct
*work
)
3276 struct mlx5_ib_delay_drop
*delay_drop
=
3277 container_of(work
, struct mlx5_ib_delay_drop
,
3280 atomic_inc(&delay_drop
->events_cnt
);
3282 mutex_lock(&delay_drop
->lock
);
3283 err
= mlx5_core_set_delay_drop(delay_drop
->dev
->mdev
,
3284 delay_drop
->timeout
);
3286 mlx5_ib_warn(delay_drop
->dev
, "Failed to set delay drop, timeout=%u\n",
3287 delay_drop
->timeout
);
3288 delay_drop
->activate
= false;
3290 mutex_unlock(&delay_drop
->lock
);
3293 static void mlx5_ib_handle_event(struct work_struct
*_work
)
3295 struct mlx5_ib_event_work
*work
=
3296 container_of(_work
, struct mlx5_ib_event_work
, work
);
3297 struct mlx5_ib_dev
*ibdev
;
3298 struct ib_event ibev
;
3302 if (mlx5_core_is_mp_slave(work
->dev
)) {
3303 ibdev
= mlx5_ib_get_ibdev_from_mpi(work
->context
);
3307 ibdev
= work
->context
;
3310 switch (work
->event
) {
3311 case MLX5_DEV_EVENT_SYS_ERROR
:
3312 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
3313 mlx5_ib_handle_internal_error(ibdev
);
3317 case MLX5_DEV_EVENT_PORT_UP
:
3318 case MLX5_DEV_EVENT_PORT_DOWN
:
3319 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
3320 port
= (u8
)work
->param
;
3322 /* In RoCE, port up/down events are handled in
3323 * mlx5_netdev_event().
3325 if (mlx5_ib_port_link_layer(&ibdev
->ib_dev
, port
) ==
3326 IB_LINK_LAYER_ETHERNET
)
3329 ibev
.event
= (work
->event
== MLX5_DEV_EVENT_PORT_UP
) ?
3330 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
3333 case MLX5_DEV_EVENT_LID_CHANGE
:
3334 ibev
.event
= IB_EVENT_LID_CHANGE
;
3335 port
= (u8
)work
->param
;
3338 case MLX5_DEV_EVENT_PKEY_CHANGE
:
3339 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
3340 port
= (u8
)work
->param
;
3342 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
3345 case MLX5_DEV_EVENT_GUID_CHANGE
:
3346 ibev
.event
= IB_EVENT_GID_CHANGE
;
3347 port
= (u8
)work
->param
;
3350 case MLX5_DEV_EVENT_CLIENT_REREG
:
3351 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
3352 port
= (u8
)work
->param
;
3354 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT
:
3355 schedule_work(&ibdev
->delay_drop
.delay_drop_work
);
3361 ibev
.device
= &ibdev
->ib_dev
;
3362 ibev
.element
.port_num
= port
;
3364 if (port
< 1 || port
> ibdev
->num_ports
) {
3365 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
3369 if (ibdev
->ib_active
)
3370 ib_dispatch_event(&ibev
);
3373 ibdev
->ib_active
= false;
3378 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
3379 enum mlx5_dev_event event
, unsigned long param
)
3381 struct mlx5_ib_event_work
*work
;
3383 work
= kmalloc(sizeof(*work
), GFP_ATOMIC
);
3387 INIT_WORK(&work
->work
, mlx5_ib_handle_event
);
3389 work
->param
= param
;
3390 work
->context
= context
;
3391 work
->event
= event
;
3393 queue_work(mlx5_ib_event_wq
, &work
->work
);
3396 static int set_has_smi_cap(struct mlx5_ib_dev
*dev
)
3398 struct mlx5_hca_vport_context vport_ctx
;
3402 for (port
= 1; port
<= dev
->num_ports
; port
++) {
3403 dev
->mdev
->port_caps
[port
- 1].has_smi
= false;
3404 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) ==
3405 MLX5_CAP_PORT_TYPE_IB
) {
3406 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
)) {
3407 err
= mlx5_query_hca_vport_context(dev
->mdev
, 0,
3411 mlx5_ib_err(dev
, "query_hca_vport_context for port=%d failed %d\n",
3415 dev
->mdev
->port_caps
[port
- 1].has_smi
=
3418 dev
->mdev
->port_caps
[port
- 1].has_smi
= true;
3425 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
3429 for (port
= 1; port
<= dev
->num_ports
; port
++)
3430 mlx5_query_ext_port_caps(dev
, port
);
3433 static int get_port_caps(struct mlx5_ib_dev
*dev
, u8 port
)
3435 struct ib_device_attr
*dprops
= NULL
;
3436 struct ib_port_attr
*pprops
= NULL
;
3438 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
3440 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
3444 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
3448 err
= set_has_smi_cap(dev
);
3452 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
3454 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
3458 memset(pprops
, 0, sizeof(*pprops
));
3459 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
3461 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
3466 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
3468 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
3469 pprops
->gid_tbl_len
;
3470 mlx5_ib_dbg(dev
, "port %d: pkey_table_len %d, gid_table_len %d\n",
3471 port
, dprops
->max_pkeys
, pprops
->gid_tbl_len
);
3480 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
3484 err
= mlx5_mr_cache_cleanup(dev
);
3486 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
3488 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
3489 ib_free_cq(dev
->umrc
.cq
);
3490 ib_dealloc_pd(dev
->umrc
.pd
);
3497 static int create_umr_res(struct mlx5_ib_dev
*dev
)
3499 struct ib_qp_init_attr
*init_attr
= NULL
;
3500 struct ib_qp_attr
*attr
= NULL
;
3506 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
3507 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
3508 if (!attr
|| !init_attr
) {
3513 pd
= ib_alloc_pd(&dev
->ib_dev
, 0);
3515 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
3520 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
3522 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
3527 init_attr
->send_cq
= cq
;
3528 init_attr
->recv_cq
= cq
;
3529 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
3530 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
3531 init_attr
->cap
.max_send_sge
= 1;
3532 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
3533 init_attr
->port_num
= 1;
3534 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
3536 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
3540 qp
->device
= &dev
->ib_dev
;
3543 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
3544 qp
->send_cq
= init_attr
->send_cq
;
3545 qp
->recv_cq
= init_attr
->recv_cq
;
3547 attr
->qp_state
= IB_QPS_INIT
;
3549 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
3552 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
3556 memset(attr
, 0, sizeof(*attr
));
3557 attr
->qp_state
= IB_QPS_RTR
;
3558 attr
->path_mtu
= IB_MTU_256
;
3560 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
3562 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
3566 memset(attr
, 0, sizeof(*attr
));
3567 attr
->qp_state
= IB_QPS_RTS
;
3568 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
3570 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
3578 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
3579 ret
= mlx5_mr_cache_init(dev
);
3581 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
3591 mlx5_ib_destroy_qp(qp
);
3605 static u8
mlx5_get_umr_fence(u8 umr_fence_cap
)
3607 switch (umr_fence_cap
) {
3608 case MLX5_CAP_UMR_FENCE_NONE
:
3609 return MLX5_FENCE_MODE_NONE
;
3610 case MLX5_CAP_UMR_FENCE_SMALL
:
3611 return MLX5_FENCE_MODE_INITIATOR_SMALL
;
3613 return MLX5_FENCE_MODE_STRONG_ORDERING
;
3617 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
3619 struct ib_srq_init_attr attr
;
3620 struct mlx5_ib_dev
*dev
;
3621 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
3625 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
3627 mutex_init(&devr
->mutex
);
3629 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
3630 if (IS_ERR(devr
->p0
)) {
3631 ret
= PTR_ERR(devr
->p0
);
3634 devr
->p0
->device
= &dev
->ib_dev
;
3635 devr
->p0
->uobject
= NULL
;
3636 atomic_set(&devr
->p0
->usecnt
, 0);
3638 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
3639 if (IS_ERR(devr
->c0
)) {
3640 ret
= PTR_ERR(devr
->c0
);
3643 devr
->c0
->device
= &dev
->ib_dev
;
3644 devr
->c0
->uobject
= NULL
;
3645 devr
->c0
->comp_handler
= NULL
;
3646 devr
->c0
->event_handler
= NULL
;
3647 devr
->c0
->cq_context
= NULL
;
3648 atomic_set(&devr
->c0
->usecnt
, 0);
3650 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
3651 if (IS_ERR(devr
->x0
)) {
3652 ret
= PTR_ERR(devr
->x0
);
3655 devr
->x0
->device
= &dev
->ib_dev
;
3656 devr
->x0
->inode
= NULL
;
3657 atomic_set(&devr
->x0
->usecnt
, 0);
3658 mutex_init(&devr
->x0
->tgt_qp_mutex
);
3659 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
3661 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
3662 if (IS_ERR(devr
->x1
)) {
3663 ret
= PTR_ERR(devr
->x1
);
3666 devr
->x1
->device
= &dev
->ib_dev
;
3667 devr
->x1
->inode
= NULL
;
3668 atomic_set(&devr
->x1
->usecnt
, 0);
3669 mutex_init(&devr
->x1
->tgt_qp_mutex
);
3670 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
3672 memset(&attr
, 0, sizeof(attr
));
3673 attr
.attr
.max_sge
= 1;
3674 attr
.attr
.max_wr
= 1;
3675 attr
.srq_type
= IB_SRQT_XRC
;
3676 attr
.ext
.cq
= devr
->c0
;
3677 attr
.ext
.xrc
.xrcd
= devr
->x0
;
3679 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
3680 if (IS_ERR(devr
->s0
)) {
3681 ret
= PTR_ERR(devr
->s0
);
3684 devr
->s0
->device
= &dev
->ib_dev
;
3685 devr
->s0
->pd
= devr
->p0
;
3686 devr
->s0
->uobject
= NULL
;
3687 devr
->s0
->event_handler
= NULL
;
3688 devr
->s0
->srq_context
= NULL
;
3689 devr
->s0
->srq_type
= IB_SRQT_XRC
;
3690 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
3691 devr
->s0
->ext
.cq
= devr
->c0
;
3692 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
3693 atomic_inc(&devr
->s0
->ext
.cq
->usecnt
);
3694 atomic_inc(&devr
->p0
->usecnt
);
3695 atomic_set(&devr
->s0
->usecnt
, 0);
3697 memset(&attr
, 0, sizeof(attr
));
3698 attr
.attr
.max_sge
= 1;
3699 attr
.attr
.max_wr
= 1;
3700 attr
.srq_type
= IB_SRQT_BASIC
;
3701 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
3702 if (IS_ERR(devr
->s1
)) {
3703 ret
= PTR_ERR(devr
->s1
);
3706 devr
->s1
->device
= &dev
->ib_dev
;
3707 devr
->s1
->pd
= devr
->p0
;
3708 devr
->s1
->uobject
= NULL
;
3709 devr
->s1
->event_handler
= NULL
;
3710 devr
->s1
->srq_context
= NULL
;
3711 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
3712 devr
->s1
->ext
.cq
= devr
->c0
;
3713 atomic_inc(&devr
->p0
->usecnt
);
3714 atomic_set(&devr
->s1
->usecnt
, 0);
3716 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
3717 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
3718 pkey_change_handler
);
3719 devr
->ports
[port
].devr
= devr
;
3725 mlx5_ib_destroy_srq(devr
->s0
);
3727 mlx5_ib_dealloc_xrcd(devr
->x1
);
3729 mlx5_ib_dealloc_xrcd(devr
->x0
);
3731 mlx5_ib_destroy_cq(devr
->c0
);
3733 mlx5_ib_dealloc_pd(devr
->p0
);
3738 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
3740 struct mlx5_ib_dev
*dev
=
3741 container_of(devr
, struct mlx5_ib_dev
, devr
);
3744 mlx5_ib_destroy_srq(devr
->s1
);
3745 mlx5_ib_destroy_srq(devr
->s0
);
3746 mlx5_ib_dealloc_xrcd(devr
->x0
);
3747 mlx5_ib_dealloc_xrcd(devr
->x1
);
3748 mlx5_ib_destroy_cq(devr
->c0
);
3749 mlx5_ib_dealloc_pd(devr
->p0
);
3751 /* Make sure no change P_Key work items are still executing */
3752 for (port
= 0; port
< dev
->num_ports
; ++port
)
3753 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
3756 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
3758 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3759 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
3760 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
3761 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
3762 bool raw_support
= !mlx5_core_mp_enabled(dev
->mdev
);
3765 if (ll
== IB_LINK_LAYER_INFINIBAND
)
3766 return RDMA_CORE_PORT_IBA_IB
;
3769 ret
= RDMA_CORE_PORT_RAW_PACKET
;
3771 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
3774 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
3777 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
3778 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
3780 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
3781 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
3786 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
3787 struct ib_port_immutable
*immutable
)
3789 struct ib_port_attr attr
;
3790 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3791 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, port_num
);
3794 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
3796 err
= ib_query_port(ibdev
, port_num
, &attr
);
3800 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
3801 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
3802 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
3803 if ((ll
== IB_LINK_LAYER_INFINIBAND
) || MLX5_CAP_GEN(dev
->mdev
, roce
))
3804 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
3809 static int mlx5_port_rep_immutable(struct ib_device
*ibdev
, u8 port_num
,
3810 struct ib_port_immutable
*immutable
)
3812 struct ib_port_attr attr
;
3815 immutable
->core_cap_flags
= RDMA_CORE_PORT_RAW_PACKET
;
3817 err
= ib_query_port(ibdev
, port_num
, &attr
);
3821 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
3822 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
3823 immutable
->core_cap_flags
= RDMA_CORE_PORT_RAW_PACKET
;
3828 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
)
3830 struct mlx5_ib_dev
*dev
=
3831 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
3832 snprintf(str
, IB_FW_VERSION_NAME_MAX
, "%d.%d.%04d",
3833 fw_rev_maj(dev
->mdev
), fw_rev_min(dev
->mdev
),
3834 fw_rev_sub(dev
->mdev
));
3837 static int mlx5_eth_lag_init(struct mlx5_ib_dev
*dev
)
3839 struct mlx5_core_dev
*mdev
= dev
->mdev
;
3840 struct mlx5_flow_namespace
*ns
= mlx5_get_flow_namespace(mdev
,
3841 MLX5_FLOW_NAMESPACE_LAG
);
3842 struct mlx5_flow_table
*ft
;
3845 if (!ns
|| !mlx5_lag_is_active(mdev
))
3848 err
= mlx5_cmd_create_vport_lag(mdev
);
3852 ft
= mlx5_create_lag_demux_flow_table(ns
, 0, 0);
3855 goto err_destroy_vport_lag
;
3858 dev
->flow_db
->lag_demux_ft
= ft
;
3861 err_destroy_vport_lag
:
3862 mlx5_cmd_destroy_vport_lag(mdev
);
3866 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev
*dev
)
3868 struct mlx5_core_dev
*mdev
= dev
->mdev
;
3870 if (dev
->flow_db
->lag_demux_ft
) {
3871 mlx5_destroy_flow_table(dev
->flow_db
->lag_demux_ft
);
3872 dev
->flow_db
->lag_demux_ft
= NULL
;
3874 mlx5_cmd_destroy_vport_lag(mdev
);
3878 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev
*dev
, u8 port_num
)
3882 dev
->roce
[port_num
].nb
.notifier_call
= mlx5_netdev_event
;
3883 err
= register_netdevice_notifier(&dev
->roce
[port_num
].nb
);
3885 dev
->roce
[port_num
].nb
.notifier_call
= NULL
;
3892 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev
*dev
, u8 port_num
)
3894 if (dev
->roce
[port_num
].nb
.notifier_call
) {
3895 unregister_netdevice_notifier(&dev
->roce
[port_num
].nb
);
3896 dev
->roce
[port_num
].nb
.notifier_call
= NULL
;
3900 static int mlx5_enable_eth(struct mlx5_ib_dev
*dev
, u8 port_num
)
3904 if (MLX5_CAP_GEN(dev
->mdev
, roce
)) {
3905 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
3910 err
= mlx5_eth_lag_init(dev
);
3912 goto err_disable_roce
;
3917 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
3918 mlx5_nic_vport_disable_roce(dev
->mdev
);
3923 static void mlx5_disable_eth(struct mlx5_ib_dev
*dev
)
3925 mlx5_eth_lag_cleanup(dev
);
3926 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
3927 mlx5_nic_vport_disable_roce(dev
->mdev
);
3930 struct mlx5_ib_counter
{
3935 #define INIT_Q_COUNTER(_name) \
3936 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3938 static const struct mlx5_ib_counter basic_q_cnts
[] = {
3939 INIT_Q_COUNTER(rx_write_requests
),
3940 INIT_Q_COUNTER(rx_read_requests
),
3941 INIT_Q_COUNTER(rx_atomic_requests
),
3942 INIT_Q_COUNTER(out_of_buffer
),
3945 static const struct mlx5_ib_counter out_of_seq_q_cnts
[] = {
3946 INIT_Q_COUNTER(out_of_sequence
),
3949 static const struct mlx5_ib_counter retrans_q_cnts
[] = {
3950 INIT_Q_COUNTER(duplicate_request
),
3951 INIT_Q_COUNTER(rnr_nak_retry_err
),
3952 INIT_Q_COUNTER(packet_seq_err
),
3953 INIT_Q_COUNTER(implied_nak_seq_err
),
3954 INIT_Q_COUNTER(local_ack_timeout_err
),
3957 #define INIT_CONG_COUNTER(_name) \
3958 { .name = #_name, .offset = \
3959 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3961 static const struct mlx5_ib_counter cong_cnts
[] = {
3962 INIT_CONG_COUNTER(rp_cnp_ignored
),
3963 INIT_CONG_COUNTER(rp_cnp_handled
),
3964 INIT_CONG_COUNTER(np_ecn_marked_roce_packets
),
3965 INIT_CONG_COUNTER(np_cnp_sent
),
3968 static const struct mlx5_ib_counter extended_err_cnts
[] = {
3969 INIT_Q_COUNTER(resp_local_length_error
),
3970 INIT_Q_COUNTER(resp_cqe_error
),
3971 INIT_Q_COUNTER(req_cqe_error
),
3972 INIT_Q_COUNTER(req_remote_invalid_request
),
3973 INIT_Q_COUNTER(req_remote_access_errors
),
3974 INIT_Q_COUNTER(resp_remote_access_errors
),
3975 INIT_Q_COUNTER(resp_cqe_flush_error
),
3976 INIT_Q_COUNTER(req_cqe_flush_error
),
3979 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev
*dev
)
3983 for (i
= 0; i
< dev
->num_ports
; i
++) {
3984 if (dev
->port
[i
].cnts
.set_id
)
3985 mlx5_core_dealloc_q_counter(dev
->mdev
,
3986 dev
->port
[i
].cnts
.set_id
);
3987 kfree(dev
->port
[i
].cnts
.names
);
3988 kfree(dev
->port
[i
].cnts
.offsets
);
3992 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev
*dev
,
3993 struct mlx5_ib_counters
*cnts
)
3997 num_counters
= ARRAY_SIZE(basic_q_cnts
);
3999 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
))
4000 num_counters
+= ARRAY_SIZE(out_of_seq_q_cnts
);
4002 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
))
4003 num_counters
+= ARRAY_SIZE(retrans_q_cnts
);
4005 if (MLX5_CAP_GEN(dev
->mdev
, enhanced_error_q_counters
))
4006 num_counters
+= ARRAY_SIZE(extended_err_cnts
);
4008 cnts
->num_q_counters
= num_counters
;
4010 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
4011 cnts
->num_cong_counters
= ARRAY_SIZE(cong_cnts
);
4012 num_counters
+= ARRAY_SIZE(cong_cnts
);
4015 cnts
->names
= kcalloc(num_counters
, sizeof(cnts
->names
), GFP_KERNEL
);
4019 cnts
->offsets
= kcalloc(num_counters
,
4020 sizeof(cnts
->offsets
), GFP_KERNEL
);
4032 static void mlx5_ib_fill_counters(struct mlx5_ib_dev
*dev
,
4039 for (i
= 0; i
< ARRAY_SIZE(basic_q_cnts
); i
++, j
++) {
4040 names
[j
] = basic_q_cnts
[i
].name
;
4041 offsets
[j
] = basic_q_cnts
[i
].offset
;
4044 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
)) {
4045 for (i
= 0; i
< ARRAY_SIZE(out_of_seq_q_cnts
); i
++, j
++) {
4046 names
[j
] = out_of_seq_q_cnts
[i
].name
;
4047 offsets
[j
] = out_of_seq_q_cnts
[i
].offset
;
4051 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
4052 for (i
= 0; i
< ARRAY_SIZE(retrans_q_cnts
); i
++, j
++) {
4053 names
[j
] = retrans_q_cnts
[i
].name
;
4054 offsets
[j
] = retrans_q_cnts
[i
].offset
;
4058 if (MLX5_CAP_GEN(dev
->mdev
, enhanced_error_q_counters
)) {
4059 for (i
= 0; i
< ARRAY_SIZE(extended_err_cnts
); i
++, j
++) {
4060 names
[j
] = extended_err_cnts
[i
].name
;
4061 offsets
[j
] = extended_err_cnts
[i
].offset
;
4065 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
4066 for (i
= 0; i
< ARRAY_SIZE(cong_cnts
); i
++, j
++) {
4067 names
[j
] = cong_cnts
[i
].name
;
4068 offsets
[j
] = cong_cnts
[i
].offset
;
4073 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev
*dev
)
4078 for (i
= 0; i
< dev
->num_ports
; i
++) {
4079 err
= __mlx5_ib_alloc_counters(dev
, &dev
->port
[i
].cnts
);
4083 mlx5_ib_fill_counters(dev
, dev
->port
[i
].cnts
.names
,
4084 dev
->port
[i
].cnts
.offsets
);
4086 err
= mlx5_core_alloc_q_counter(dev
->mdev
,
4087 &dev
->port
[i
].cnts
.set_id
);
4090 "couldn't allocate queue counter for port %d, err %d\n",
4094 dev
->port
[i
].cnts
.set_id_valid
= true;
4100 mlx5_ib_dealloc_counters(dev
);
4104 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
4107 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4108 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
4110 /* We support only per port stats */
4114 return rdma_alloc_hw_stats_struct(port
->cnts
.names
,
4115 port
->cnts
.num_q_counters
+
4116 port
->cnts
.num_cong_counters
,
4117 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
4120 static int mlx5_ib_query_q_counters(struct mlx5_core_dev
*mdev
,
4121 struct mlx5_ib_port
*port
,
4122 struct rdma_hw_stats
*stats
)
4124 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
4129 out
= kvzalloc(outlen
, GFP_KERNEL
);
4133 ret
= mlx5_core_query_q_counter(mdev
,
4134 port
->cnts
.set_id
, 0,
4139 for (i
= 0; i
< port
->cnts
.num_q_counters
; i
++) {
4140 val
= *(__be32
*)(out
+ port
->cnts
.offsets
[i
]);
4141 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
4149 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
4150 struct rdma_hw_stats
*stats
,
4151 u8 port_num
, int index
)
4153 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4154 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
4155 struct mlx5_core_dev
*mdev
;
4156 int ret
, num_counters
;
4162 num_counters
= port
->cnts
.num_q_counters
+ port
->cnts
.num_cong_counters
;
4164 /* q_counters are per IB device, query the master mdev */
4165 ret
= mlx5_ib_query_q_counters(dev
->mdev
, port
, stats
);
4169 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
4170 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
,
4173 /* If port is not affiliated yet, its in down state
4174 * which doesn't have any counters yet, so it would be
4175 * zero. So no need to read from the HCA.
4179 ret
= mlx5_lag_query_cong_counters(dev
->mdev
,
4181 port
->cnts
.num_q_counters
,
4182 port
->cnts
.num_cong_counters
,
4183 port
->cnts
.offsets
+
4184 port
->cnts
.num_q_counters
);
4186 mlx5_ib_put_native_port_mdev(dev
, port_num
);
4192 return num_counters
;
4195 static void mlx5_ib_free_rdma_netdev(struct net_device
*netdev
)
4197 return mlx5_rdma_netdev_free(netdev
);
4200 static struct net_device
*
4201 mlx5_ib_alloc_rdma_netdev(struct ib_device
*hca
,
4203 enum rdma_netdev_t type
,
4205 unsigned char name_assign_type
,
4206 void (*setup
)(struct net_device
*))
4208 struct net_device
*netdev
;
4209 struct rdma_netdev
*rn
;
4211 if (type
!= RDMA_NETDEV_IPOIB
)
4212 return ERR_PTR(-EOPNOTSUPP
);
4214 netdev
= mlx5_rdma_netdev_alloc(to_mdev(hca
)->mdev
, hca
,
4216 if (likely(!IS_ERR_OR_NULL(netdev
))) {
4217 rn
= netdev_priv(netdev
);
4218 rn
->free_rdma_netdev
= mlx5_ib_free_rdma_netdev
;
4223 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev
*dev
)
4225 if (!dev
->delay_drop
.dbg
)
4227 debugfs_remove_recursive(dev
->delay_drop
.dbg
->dir_debugfs
);
4228 kfree(dev
->delay_drop
.dbg
);
4229 dev
->delay_drop
.dbg
= NULL
;
4232 static void cancel_delay_drop(struct mlx5_ib_dev
*dev
)
4234 if (!(dev
->ib_dev
.attrs
.raw_packet_caps
& IB_RAW_PACKET_CAP_DELAY_DROP
))
4237 cancel_work_sync(&dev
->delay_drop
.delay_drop_work
);
4238 delay_drop_debugfs_cleanup(dev
);
4241 static ssize_t
delay_drop_timeout_read(struct file
*filp
, char __user
*buf
,
4242 size_t count
, loff_t
*pos
)
4244 struct mlx5_ib_delay_drop
*delay_drop
= filp
->private_data
;
4248 len
= snprintf(lbuf
, sizeof(lbuf
), "%u\n", delay_drop
->timeout
);
4249 return simple_read_from_buffer(buf
, count
, pos
, lbuf
, len
);
4252 static ssize_t
delay_drop_timeout_write(struct file
*filp
, const char __user
*buf
,
4253 size_t count
, loff_t
*pos
)
4255 struct mlx5_ib_delay_drop
*delay_drop
= filp
->private_data
;
4259 if (kstrtouint_from_user(buf
, count
, 0, &var
))
4262 timeout
= min_t(u32
, roundup(var
, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS
*
4265 mlx5_ib_dbg(delay_drop
->dev
, "Round delay drop timeout to %u usec\n",
4268 delay_drop
->timeout
= timeout
;
4273 static const struct file_operations fops_delay_drop_timeout
= {
4274 .owner
= THIS_MODULE
,
4275 .open
= simple_open
,
4276 .write
= delay_drop_timeout_write
,
4277 .read
= delay_drop_timeout_read
,
4280 static int delay_drop_debugfs_init(struct mlx5_ib_dev
*dev
)
4282 struct mlx5_ib_dbg_delay_drop
*dbg
;
4284 if (!mlx5_debugfs_root
)
4287 dbg
= kzalloc(sizeof(*dbg
), GFP_KERNEL
);
4291 dev
->delay_drop
.dbg
= dbg
;
4294 debugfs_create_dir("delay_drop",
4295 dev
->mdev
->priv
.dbg_root
);
4296 if (!dbg
->dir_debugfs
)
4299 dbg
->events_cnt_debugfs
=
4300 debugfs_create_atomic_t("num_timeout_events", 0400,
4302 &dev
->delay_drop
.events_cnt
);
4303 if (!dbg
->events_cnt_debugfs
)
4306 dbg
->rqs_cnt_debugfs
=
4307 debugfs_create_atomic_t("num_rqs", 0400,
4309 &dev
->delay_drop
.rqs_cnt
);
4310 if (!dbg
->rqs_cnt_debugfs
)
4313 dbg
->timeout_debugfs
=
4314 debugfs_create_file("timeout", 0600,
4317 &fops_delay_drop_timeout
);
4318 if (!dbg
->timeout_debugfs
)
4324 delay_drop_debugfs_cleanup(dev
);
4328 static void init_delay_drop(struct mlx5_ib_dev
*dev
)
4330 if (!(dev
->ib_dev
.attrs
.raw_packet_caps
& IB_RAW_PACKET_CAP_DELAY_DROP
))
4333 mutex_init(&dev
->delay_drop
.lock
);
4334 dev
->delay_drop
.dev
= dev
;
4335 dev
->delay_drop
.activate
= false;
4336 dev
->delay_drop
.timeout
= MLX5_MAX_DELAY_DROP_TIMEOUT_MS
* 1000;
4337 INIT_WORK(&dev
->delay_drop
.delay_drop_work
, delay_drop_handler
);
4338 atomic_set(&dev
->delay_drop
.rqs_cnt
, 0);
4339 atomic_set(&dev
->delay_drop
.events_cnt
, 0);
4341 if (delay_drop_debugfs_init(dev
))
4342 mlx5_ib_warn(dev
, "Failed to init delay drop debugfs\n");
4345 static const struct cpumask
*
4346 mlx5_ib_get_vector_affinity(struct ib_device
*ibdev
, int comp_vector
)
4348 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4350 return mlx5_get_vector_affinity(dev
->mdev
, comp_vector
);
4353 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4354 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev
*ibdev
,
4355 struct mlx5_ib_multiport_info
*mpi
)
4357 u8 port_num
= mlx5_core_native_port_num(mpi
->mdev
) - 1;
4358 struct mlx5_ib_port
*port
= &ibdev
->port
[port_num
];
4363 mlx5_ib_cleanup_cong_debugfs(ibdev
, port_num
);
4365 spin_lock(&port
->mp
.mpi_lock
);
4367 spin_unlock(&port
->mp
.mpi_lock
);
4372 spin_unlock(&port
->mp
.mpi_lock
);
4373 mlx5_remove_netdev_notifier(ibdev
, port_num
);
4374 spin_lock(&port
->mp
.mpi_lock
);
4376 comps
= mpi
->mdev_refcnt
;
4378 mpi
->unaffiliate
= true;
4379 init_completion(&mpi
->unref_comp
);
4380 spin_unlock(&port
->mp
.mpi_lock
);
4382 for (i
= 0; i
< comps
; i
++)
4383 wait_for_completion(&mpi
->unref_comp
);
4385 spin_lock(&port
->mp
.mpi_lock
);
4386 mpi
->unaffiliate
= false;
4389 port
->mp
.mpi
= NULL
;
4391 list_add_tail(&mpi
->list
, &mlx5_ib_unaffiliated_port_list
);
4393 spin_unlock(&port
->mp
.mpi_lock
);
4395 err
= mlx5_nic_vport_unaffiliate_multiport(mpi
->mdev
);
4397 mlx5_ib_dbg(ibdev
, "unaffiliated port %d\n", port_num
+ 1);
4398 /* Log an error, still needed to cleanup the pointers and add
4399 * it back to the list.
4402 mlx5_ib_err(ibdev
, "Failed to unaffiliate port %u\n",
4405 ibdev
->roce
[port_num
].last_port_state
= IB_PORT_DOWN
;
4408 /* The mlx5_ib_multiport_mutex should be held when calling this function */
4409 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev
*ibdev
,
4410 struct mlx5_ib_multiport_info
*mpi
)
4412 u8 port_num
= mlx5_core_native_port_num(mpi
->mdev
) - 1;
4415 spin_lock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
4416 if (ibdev
->port
[port_num
].mp
.mpi
) {
4417 mlx5_ib_warn(ibdev
, "port %d already affiliated.\n",
4419 spin_unlock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
4423 ibdev
->port
[port_num
].mp
.mpi
= mpi
;
4425 spin_unlock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
4427 err
= mlx5_nic_vport_affiliate_multiport(ibdev
->mdev
, mpi
->mdev
);
4431 err
= get_port_caps(ibdev
, mlx5_core_native_port_num(mpi
->mdev
));
4435 err
= mlx5_add_netdev_notifier(ibdev
, port_num
);
4437 mlx5_ib_err(ibdev
, "failed adding netdev notifier for port %u\n",
4442 err
= mlx5_ib_init_cong_debugfs(ibdev
, port_num
);
4449 mlx5_ib_unbind_slave_port(ibdev
, mpi
);
4453 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev
*dev
)
4455 int port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4456 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
,
4458 struct mlx5_ib_multiport_info
*mpi
;
4462 if (!mlx5_core_is_mp_master(dev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
4465 err
= mlx5_query_nic_vport_system_image_guid(dev
->mdev
,
4466 &dev
->sys_image_guid
);
4470 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
4474 mutex_lock(&mlx5_ib_multiport_mutex
);
4475 for (i
= 0; i
< dev
->num_ports
; i
++) {
4478 /* build a stub multiport info struct for the native port. */
4479 if (i
== port_num
) {
4480 mpi
= kzalloc(sizeof(*mpi
), GFP_KERNEL
);
4482 mutex_unlock(&mlx5_ib_multiport_mutex
);
4483 mlx5_nic_vport_disable_roce(dev
->mdev
);
4487 mpi
->is_master
= true;
4488 mpi
->mdev
= dev
->mdev
;
4489 mpi
->sys_image_guid
= dev
->sys_image_guid
;
4490 dev
->port
[i
].mp
.mpi
= mpi
;
4496 list_for_each_entry(mpi
, &mlx5_ib_unaffiliated_port_list
,
4498 if (dev
->sys_image_guid
== mpi
->sys_image_guid
&&
4499 (mlx5_core_native_port_num(mpi
->mdev
) - 1) == i
) {
4500 bound
= mlx5_ib_bind_slave_port(dev
, mpi
);
4504 dev_dbg(&mpi
->mdev
->pdev
->dev
, "removing port from unaffiliated list.\n");
4505 mlx5_ib_dbg(dev
, "port %d bound\n", i
+ 1);
4506 list_del(&mpi
->list
);
4511 get_port_caps(dev
, i
+ 1);
4512 mlx5_ib_dbg(dev
, "no free port found for port %d\n",
4517 list_add_tail(&dev
->ib_dev_list
, &mlx5_ib_dev_list
);
4518 mutex_unlock(&mlx5_ib_multiport_mutex
);
4522 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev
*dev
)
4524 int port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4525 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
,
4529 if (!mlx5_core_is_mp_master(dev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
4532 mutex_lock(&mlx5_ib_multiport_mutex
);
4533 for (i
= 0; i
< dev
->num_ports
; i
++) {
4534 if (dev
->port
[i
].mp
.mpi
) {
4535 /* Destroy the native port stub */
4536 if (i
== port_num
) {
4537 kfree(dev
->port
[i
].mp
.mpi
);
4538 dev
->port
[i
].mp
.mpi
= NULL
;
4540 mlx5_ib_dbg(dev
, "unbinding port_num: %d\n", i
+ 1);
4541 mlx5_ib_unbind_slave_port(dev
, dev
->port
[i
].mp
.mpi
);
4546 mlx5_ib_dbg(dev
, "removing from devlist\n");
4547 list_del(&dev
->ib_dev_list
);
4548 mutex_unlock(&mlx5_ib_multiport_mutex
);
4550 mlx5_nic_vport_disable_roce(dev
->mdev
);
4553 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev
*dev
)
4555 mlx5_ib_cleanup_multiport_master(dev
);
4556 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4557 cleanup_srcu_struct(&dev
->mr_srcu
);
4562 int mlx5_ib_stage_init_init(struct mlx5_ib_dev
*dev
)
4564 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4569 dev
->port
= kcalloc(dev
->num_ports
, sizeof(*dev
->port
),
4574 for (i
= 0; i
< dev
->num_ports
; i
++) {
4575 spin_lock_init(&dev
->port
[i
].mp
.mpi_lock
);
4576 rwlock_init(&dev
->roce
[i
].netdev_lock
);
4579 err
= mlx5_ib_init_multiport_master(dev
);
4583 if (!mlx5_core_mp_enabled(mdev
)) {
4584 for (i
= 1; i
<= dev
->num_ports
; i
++) {
4585 err
= get_port_caps(dev
, i
);
4590 err
= get_port_caps(dev
, mlx5_core_native_port_num(mdev
));
4595 if (mlx5_use_mad_ifc(dev
))
4596 get_ext_port_caps(dev
);
4598 if (!mlx5_lag_is_active(mdev
))
4601 name
= "mlx5_bond_%d";
4603 strlcpy(dev
->ib_dev
.name
, name
, IB_DEVICE_NAME_MAX
);
4604 dev
->ib_dev
.owner
= THIS_MODULE
;
4605 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
4606 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
4607 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
4608 dev
->ib_dev
.num_comp_vectors
=
4609 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
4610 dev
->ib_dev
.dev
.parent
= &mdev
->pdev
->dev
;
4612 mutex_init(&dev
->cap_mask_mutex
);
4613 INIT_LIST_HEAD(&dev
->qp_list
);
4614 spin_lock_init(&dev
->reset_flow_resource_lock
);
4616 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4617 err
= init_srcu_struct(&dev
->mr_srcu
);
4624 mlx5_ib_cleanup_multiport_master(dev
);
4632 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev
*dev
)
4634 dev
->flow_db
= kzalloc(sizeof(*dev
->flow_db
), GFP_KERNEL
);
4639 mutex_init(&dev
->flow_db
->lock
);
4644 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev
*dev
)
4646 struct mlx5_ib_dev
*nic_dev
;
4648 nic_dev
= mlx5_ib_get_uplink_ibdev(dev
->mdev
->priv
.eswitch
);
4653 dev
->flow_db
= nic_dev
->flow_db
;
4658 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev
*dev
)
4660 kfree(dev
->flow_db
);
4663 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev
*dev
)
4665 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4668 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
4669 dev
->ib_dev
.uverbs_cmd_mask
=
4670 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
4671 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
4672 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
4673 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
4674 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
4675 (1ull << IB_USER_VERBS_CMD_CREATE_AH
) |
4676 (1ull << IB_USER_VERBS_CMD_DESTROY_AH
) |
4677 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
4678 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
4679 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
4680 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
4681 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
4682 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
4683 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
4684 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
4685 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
4686 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
4687 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
4688 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
4689 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
4690 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
4691 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
4692 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
4693 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
4694 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
4695 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
4696 dev
->ib_dev
.uverbs_ex_cmd_mask
=
4697 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
4698 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
4699 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
) |
4700 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP
) |
4701 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ
);
4703 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
4704 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
4705 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
4706 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
4707 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
4708 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
4709 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
4710 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
4711 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
4712 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
4713 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
4714 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
4715 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
4716 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
4717 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
4718 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
4719 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
4720 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
4721 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
4722 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
4723 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
4724 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
4725 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
4726 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
4727 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
4728 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
4729 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
4730 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
4731 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
4732 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
4733 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
4734 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
4735 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
4736 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
4737 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
4738 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
4739 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
4740 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
4741 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
4742 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
4743 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
4744 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
4745 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
4746 dev
->ib_dev
.get_dev_fw_str
= get_dev_fw_str
;
4747 dev
->ib_dev
.get_vector_affinity
= mlx5_ib_get_vector_affinity
;
4748 if (MLX5_CAP_GEN(mdev
, ipoib_enhanced_offloads
))
4749 dev
->ib_dev
.alloc_rdma_netdev
= mlx5_ib_alloc_rdma_netdev
;
4751 if (mlx5_core_is_pf(mdev
)) {
4752 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
4753 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
4754 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
4755 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
4758 dev
->ib_dev
.disassociate_ucontext
= mlx5_ib_disassociate_ucontext
;
4760 dev
->umr_fence
= mlx5_get_umr_fence(MLX5_CAP_GEN(mdev
, umr_fence
));
4762 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
4763 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
4764 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
4765 dev
->ib_dev
.uverbs_cmd_mask
|=
4766 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
4767 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
4770 if (MLX5_CAP_GEN(mdev
, xrc
)) {
4771 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
4772 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
4773 dev
->ib_dev
.uverbs_cmd_mask
|=
4774 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
4775 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
4778 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
4779 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
4780 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
4781 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
4782 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
);
4784 err
= init_node_data(dev
);
4788 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_ETH
) &&
4789 (MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) ||
4790 MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
4791 mutex_init(&dev
->lb_mutex
);
4796 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev
*dev
)
4798 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
4799 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
4804 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev
*dev
)
4806 dev
->ib_dev
.get_port_immutable
= mlx5_port_rep_immutable
;
4807 dev
->ib_dev
.query_port
= mlx5_ib_rep_query_port
;
4812 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev
*dev
,
4817 for (i
= 0; i
< dev
->num_ports
; i
++) {
4818 dev
->roce
[i
].dev
= dev
;
4819 dev
->roce
[i
].native_port_num
= i
+ 1;
4820 dev
->roce
[i
].last_port_state
= IB_PORT_DOWN
;
4823 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
4824 dev
->ib_dev
.create_wq
= mlx5_ib_create_wq
;
4825 dev
->ib_dev
.modify_wq
= mlx5_ib_modify_wq
;
4826 dev
->ib_dev
.destroy_wq
= mlx5_ib_destroy_wq
;
4827 dev
->ib_dev
.create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
;
4828 dev
->ib_dev
.destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
;
4830 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
4831 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
4832 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
4833 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
4834 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
4835 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
4837 return mlx5_add_netdev_notifier(dev
, port_num
);
4840 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev
*dev
)
4842 u8 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4844 mlx5_remove_netdev_notifier(dev
, port_num
);
4847 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev
*dev
)
4849 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4850 enum rdma_link_layer ll
;
4855 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4856 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
4857 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
4859 if (ll
== IB_LINK_LAYER_ETHERNET
)
4860 err
= mlx5_ib_stage_common_roce_init(dev
, port_num
);
4865 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev
*dev
)
4867 mlx5_ib_stage_common_roce_cleanup(dev
);
4870 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev
*dev
)
4872 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4873 enum rdma_link_layer ll
;
4878 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4879 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
4880 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
4882 if (ll
== IB_LINK_LAYER_ETHERNET
) {
4883 err
= mlx5_ib_stage_common_roce_init(dev
, port_num
);
4887 err
= mlx5_enable_eth(dev
, port_num
);
4894 mlx5_ib_stage_common_roce_cleanup(dev
);
4899 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev
*dev
)
4901 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4902 enum rdma_link_layer ll
;
4906 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
4907 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
4908 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
4910 if (ll
== IB_LINK_LAYER_ETHERNET
) {
4911 mlx5_disable_eth(dev
);
4912 mlx5_ib_stage_common_roce_cleanup(dev
);
4916 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev
*dev
)
4918 return create_dev_resources(&dev
->devr
);
4921 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev
*dev
)
4923 destroy_dev_resources(&dev
->devr
);
4926 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev
*dev
)
4928 mlx5_ib_internal_fill_odp_caps(dev
);
4930 return mlx5_ib_odp_init_one(dev
);
4933 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev
*dev
)
4935 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
)) {
4936 dev
->ib_dev
.get_hw_stats
= mlx5_ib_get_hw_stats
;
4937 dev
->ib_dev
.alloc_hw_stats
= mlx5_ib_alloc_hw_stats
;
4939 return mlx5_ib_alloc_counters(dev
);
4945 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev
*dev
)
4947 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
))
4948 mlx5_ib_dealloc_counters(dev
);
4951 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev
*dev
)
4953 return mlx5_ib_init_cong_debugfs(dev
,
4954 mlx5_core_native_port_num(dev
->mdev
) - 1);
4957 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev
*dev
)
4959 mlx5_ib_cleanup_cong_debugfs(dev
,
4960 mlx5_core_native_port_num(dev
->mdev
) - 1);
4963 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev
*dev
)
4965 dev
->mdev
->priv
.uar
= mlx5_get_uars_page(dev
->mdev
);
4966 if (!dev
->mdev
->priv
.uar
)
4971 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev
*dev
)
4973 mlx5_put_uars_page(dev
->mdev
, dev
->mdev
->priv
.uar
);
4976 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev
*dev
)
4980 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->bfreg
, false, false);
4984 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->fp_bfreg
, false, true);
4986 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
4991 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev
*dev
)
4993 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
4994 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
4997 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev
*dev
)
4999 return ib_register_device(&dev
->ib_dev
, NULL
);
5002 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev
*dev
)
5004 ib_unregister_device(&dev
->ib_dev
);
5007 int mlx5_ib_stage_umr_res_init(struct mlx5_ib_dev
*dev
)
5009 return create_umr_res(dev
);
5012 void mlx5_ib_stage_umr_res_cleanup(struct mlx5_ib_dev
*dev
)
5014 destroy_umrc_res(dev
);
5017 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev
*dev
)
5019 init_delay_drop(dev
);
5024 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev
*dev
)
5026 cancel_delay_drop(dev
);
5029 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev
*dev
)
5034 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
5035 err
= device_create_file(&dev
->ib_dev
.dev
,
5036 mlx5_class_attributes
[i
]);
5044 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev
*dev
)
5046 mlx5_ib_register_vport_reps(dev
);
5051 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev
*dev
)
5053 mlx5_ib_unregister_vport_reps(dev
);
5056 void __mlx5_ib_remove(struct mlx5_ib_dev
*dev
,
5057 const struct mlx5_ib_profile
*profile
,
5060 /* Number of stages to cleanup */
5063 if (profile
->stage
[stage
].cleanup
)
5064 profile
->stage
[stage
].cleanup(dev
);
5067 ib_dealloc_device((struct ib_device
*)dev
);
5070 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev
*mdev
, u8 port_num
);
5072 void *__mlx5_ib_add(struct mlx5_ib_dev
*dev
,
5073 const struct mlx5_ib_profile
*profile
)
5078 printk_once(KERN_INFO
"%s", mlx5_version
);
5080 for (i
= 0; i
< MLX5_IB_STAGE_MAX
; i
++) {
5081 if (profile
->stage
[i
].init
) {
5082 err
= profile
->stage
[i
].init(dev
);
5088 dev
->profile
= profile
;
5089 dev
->ib_active
= true;
5094 __mlx5_ib_remove(dev
, profile
, i
);
5099 static const struct mlx5_ib_profile pf_profile
= {
5100 STAGE_CREATE(MLX5_IB_STAGE_INIT
,
5101 mlx5_ib_stage_init_init
,
5102 mlx5_ib_stage_init_cleanup
),
5103 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB
,
5104 mlx5_ib_stage_flow_db_init
,
5105 mlx5_ib_stage_flow_db_cleanup
),
5106 STAGE_CREATE(MLX5_IB_STAGE_CAPS
,
5107 mlx5_ib_stage_caps_init
,
5109 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB
,
5110 mlx5_ib_stage_non_default_cb
,
5112 STAGE_CREATE(MLX5_IB_STAGE_ROCE
,
5113 mlx5_ib_stage_roce_init
,
5114 mlx5_ib_stage_roce_cleanup
),
5115 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES
,
5116 mlx5_ib_stage_dev_res_init
,
5117 mlx5_ib_stage_dev_res_cleanup
),
5118 STAGE_CREATE(MLX5_IB_STAGE_ODP
,
5119 mlx5_ib_stage_odp_init
,
5121 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS
,
5122 mlx5_ib_stage_counters_init
,
5123 mlx5_ib_stage_counters_cleanup
),
5124 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS
,
5125 mlx5_ib_stage_cong_debugfs_init
,
5126 mlx5_ib_stage_cong_debugfs_cleanup
),
5127 STAGE_CREATE(MLX5_IB_STAGE_UAR
,
5128 mlx5_ib_stage_uar_init
,
5129 mlx5_ib_stage_uar_cleanup
),
5130 STAGE_CREATE(MLX5_IB_STAGE_BFREG
,
5131 mlx5_ib_stage_bfrag_init
,
5132 mlx5_ib_stage_bfrag_cleanup
),
5133 STAGE_CREATE(MLX5_IB_STAGE_IB_REG
,
5134 mlx5_ib_stage_ib_reg_init
,
5135 mlx5_ib_stage_ib_reg_cleanup
),
5136 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES
,
5137 mlx5_ib_stage_umr_res_init
,
5138 mlx5_ib_stage_umr_res_cleanup
),
5139 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP
,
5140 mlx5_ib_stage_delay_drop_init
,
5141 mlx5_ib_stage_delay_drop_cleanup
),
5142 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR
,
5143 mlx5_ib_stage_class_attr_init
,
5147 static const struct mlx5_ib_profile nic_rep_profile
= {
5148 STAGE_CREATE(MLX5_IB_STAGE_INIT
,
5149 mlx5_ib_stage_init_init
,
5150 mlx5_ib_stage_init_cleanup
),
5151 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB
,
5152 mlx5_ib_stage_flow_db_init
,
5153 mlx5_ib_stage_flow_db_cleanup
),
5154 STAGE_CREATE(MLX5_IB_STAGE_CAPS
,
5155 mlx5_ib_stage_caps_init
,
5157 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB
,
5158 mlx5_ib_stage_rep_non_default_cb
,
5160 STAGE_CREATE(MLX5_IB_STAGE_ROCE
,
5161 mlx5_ib_stage_rep_roce_init
,
5162 mlx5_ib_stage_rep_roce_cleanup
),
5163 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES
,
5164 mlx5_ib_stage_dev_res_init
,
5165 mlx5_ib_stage_dev_res_cleanup
),
5166 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS
,
5167 mlx5_ib_stage_counters_init
,
5168 mlx5_ib_stage_counters_cleanup
),
5169 STAGE_CREATE(MLX5_IB_STAGE_UAR
,
5170 mlx5_ib_stage_uar_init
,
5171 mlx5_ib_stage_uar_cleanup
),
5172 STAGE_CREATE(MLX5_IB_STAGE_BFREG
,
5173 mlx5_ib_stage_bfrag_init
,
5174 mlx5_ib_stage_bfrag_cleanup
),
5175 STAGE_CREATE(MLX5_IB_STAGE_IB_REG
,
5176 mlx5_ib_stage_ib_reg_init
,
5177 mlx5_ib_stage_ib_reg_cleanup
),
5178 STAGE_CREATE(MLX5_IB_STAGE_UMR_RESOURCES
,
5179 mlx5_ib_stage_umr_res_init
,
5180 mlx5_ib_stage_umr_res_cleanup
),
5181 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR
,
5182 mlx5_ib_stage_class_attr_init
,
5184 STAGE_CREATE(MLX5_IB_STAGE_REP_REG
,
5185 mlx5_ib_stage_rep_reg_init
,
5186 mlx5_ib_stage_rep_reg_cleanup
),
5189 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev
*mdev
, u8 port_num
)
5191 struct mlx5_ib_multiport_info
*mpi
;
5192 struct mlx5_ib_dev
*dev
;
5196 mpi
= kzalloc(sizeof(*mpi
), GFP_KERNEL
);
5202 err
= mlx5_query_nic_vport_system_image_guid(mdev
,
5203 &mpi
->sys_image_guid
);
5209 mutex_lock(&mlx5_ib_multiport_mutex
);
5210 list_for_each_entry(dev
, &mlx5_ib_dev_list
, ib_dev_list
) {
5211 if (dev
->sys_image_guid
== mpi
->sys_image_guid
)
5212 bound
= mlx5_ib_bind_slave_port(dev
, mpi
);
5215 rdma_roce_rescan_device(&dev
->ib_dev
);
5221 list_add_tail(&mpi
->list
, &mlx5_ib_unaffiliated_port_list
);
5222 dev_dbg(&mdev
->pdev
->dev
, "no suitable IB device found to bind to, added to unaffiliated list.\n");
5224 mlx5_ib_dbg(dev
, "bound port %u\n", port_num
+ 1);
5226 mutex_unlock(&mlx5_ib_multiport_mutex
);
5231 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
5233 enum rdma_link_layer ll
;
5234 struct mlx5_ib_dev
*dev
;
5237 printk_once(KERN_INFO
"%s", mlx5_version
);
5239 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
5240 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
5242 if (mlx5_core_is_mp_slave(mdev
) && ll
== IB_LINK_LAYER_ETHERNET
) {
5243 u8 port_num
= mlx5_core_native_port_num(mdev
) - 1;
5245 return mlx5_ib_add_slave_port(mdev
, port_num
);
5248 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
5253 dev
->num_ports
= max(MLX5_CAP_GEN(mdev
, num_ports
),
5254 MLX5_CAP_GEN(mdev
, num_vhca_ports
));
5256 if (MLX5_VPORT_MANAGER(mdev
) &&
5257 mlx5_ib_eswitch_mode(mdev
->priv
.eswitch
) == SRIOV_OFFLOADS
) {
5258 dev
->rep
= mlx5_ib_vport_rep(mdev
->priv
.eswitch
, 0);
5260 return __mlx5_ib_add(dev
, &nic_rep_profile
);
5263 return __mlx5_ib_add(dev
, &pf_profile
);
5266 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
5268 struct mlx5_ib_multiport_info
*mpi
;
5269 struct mlx5_ib_dev
*dev
;
5271 if (mlx5_core_is_mp_slave(mdev
)) {
5273 mutex_lock(&mlx5_ib_multiport_mutex
);
5275 mlx5_ib_unbind_slave_port(mpi
->ibdev
, mpi
);
5276 list_del(&mpi
->list
);
5277 mutex_unlock(&mlx5_ib_multiport_mutex
);
5282 __mlx5_ib_remove(dev
, dev
->profile
, MLX5_IB_STAGE_MAX
);
5285 static struct mlx5_interface mlx5_ib_interface
= {
5287 .remove
= mlx5_ib_remove
,
5288 .event
= mlx5_ib_event
,
5289 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5290 .pfault
= mlx5_ib_pfault
,
5292 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
5295 static int __init
mlx5_ib_init(void)
5299 mlx5_ib_event_wq
= alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
5300 if (!mlx5_ib_event_wq
)
5305 err
= mlx5_register_interface(&mlx5_ib_interface
);
5310 static void __exit
mlx5_ib_cleanup(void)
5312 mlx5_unregister_interface(&mlx5_ib_interface
);
5313 destroy_workqueue(mlx5_ib_event_wq
);
5316 module_init(mlx5_ib_init
);
5317 module_exit(mlx5_ib_cleanup
);