2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/list.h>
56 #include <rdma/ib_smi.h>
57 #include <rdma/ib_umem.h>
59 #include <linux/etherdevice.h>
64 #include <linux/mlx5/fs_helpers.h>
65 #include <linux/mlx5/accel.h>
66 #include <rdma/uverbs_std_types.h>
67 #include <rdma/mlx5_user_ioctl_verbs.h>
68 #include <rdma/mlx5_user_ioctl_cmds.h>
70 #define UVERBS_MODULE_NAME mlx5_ib
71 #include <rdma/uverbs_named_ioctl.h>
73 #define DRIVER_NAME "mlx5_ib"
74 #define DRIVER_VERSION "5.0-0"
76 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
77 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
78 MODULE_LICENSE("Dual BSD/GPL");
80 static char mlx5_version
[] =
81 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
84 struct mlx5_ib_event_work
{
85 struct work_struct work
;
87 struct mlx5_ib_dev
*dev
;
88 struct mlx5_ib_multiport_info
*mpi
;
96 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
99 static struct workqueue_struct
*mlx5_ib_event_wq
;
100 static LIST_HEAD(mlx5_ib_unaffiliated_port_list
);
101 static LIST_HEAD(mlx5_ib_dev_list
);
103 * This mutex should be held when accessing either of the above lists
105 static DEFINE_MUTEX(mlx5_ib_multiport_mutex
);
107 /* We can't use an array for xlt_emergency_page because dma_map_single
108 * doesn't work on kernel modules memory
110 static unsigned long xlt_emergency_page
;
111 static struct mutex xlt_emergency_page_mutex
;
113 struct mlx5_ib_dev
*mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info
*mpi
)
115 struct mlx5_ib_dev
*dev
;
117 mutex_lock(&mlx5_ib_multiport_mutex
);
119 mutex_unlock(&mlx5_ib_multiport_mutex
);
123 static enum rdma_link_layer
124 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
126 switch (port_type_cap
) {
127 case MLX5_CAP_PORT_TYPE_IB
:
128 return IB_LINK_LAYER_INFINIBAND
;
129 case MLX5_CAP_PORT_TYPE_ETH
:
130 return IB_LINK_LAYER_ETHERNET
;
132 return IB_LINK_LAYER_UNSPECIFIED
;
136 static enum rdma_link_layer
137 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
139 struct mlx5_ib_dev
*dev
= to_mdev(device
);
140 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
142 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
145 static int get_port_state(struct ib_device
*ibdev
,
147 enum ib_port_state
*state
)
149 struct ib_port_attr attr
;
152 memset(&attr
, 0, sizeof(attr
));
153 ret
= ibdev
->ops
.query_port(ibdev
, port_num
, &attr
);
159 static int mlx5_netdev_event(struct notifier_block
*this,
160 unsigned long event
, void *ptr
)
162 struct mlx5_roce
*roce
= container_of(this, struct mlx5_roce
, nb
);
163 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
164 u8 port_num
= roce
->native_port_num
;
165 struct mlx5_core_dev
*mdev
;
166 struct mlx5_ib_dev
*ibdev
;
169 mdev
= mlx5_ib_get_native_port_mdev(ibdev
, port_num
, NULL
);
174 case NETDEV_REGISTER
:
175 write_lock(&roce
->netdev_lock
);
177 struct mlx5_eswitch
*esw
= ibdev
->mdev
->priv
.eswitch
;
178 struct net_device
*rep_ndev
;
180 rep_ndev
= mlx5_ib_get_rep_netdev(esw
,
182 if (rep_ndev
== ndev
)
184 } else if (ndev
->dev
.parent
== &mdev
->pdev
->dev
) {
187 write_unlock(&roce
->netdev_lock
);
190 case NETDEV_UNREGISTER
:
191 write_lock(&roce
->netdev_lock
);
192 if (roce
->netdev
== ndev
)
194 write_unlock(&roce
->netdev_lock
);
200 struct net_device
*lag_ndev
= mlx5_lag_get_roce_netdev(mdev
);
201 struct net_device
*upper
= NULL
;
204 upper
= netdev_master_upper_dev_get(lag_ndev
);
208 if ((upper
== ndev
|| (!upper
&& ndev
== roce
->netdev
))
209 && ibdev
->ib_active
) {
210 struct ib_event ibev
= { };
211 enum ib_port_state port_state
;
213 if (get_port_state(&ibdev
->ib_dev
, port_num
,
217 if (roce
->last_port_state
== port_state
)
220 roce
->last_port_state
= port_state
;
221 ibev
.device
= &ibdev
->ib_dev
;
222 if (port_state
== IB_PORT_DOWN
)
223 ibev
.event
= IB_EVENT_PORT_ERR
;
224 else if (port_state
== IB_PORT_ACTIVE
)
225 ibev
.event
= IB_EVENT_PORT_ACTIVE
;
229 ibev
.element
.port_num
= port_num
;
230 ib_dispatch_event(&ibev
);
239 mlx5_ib_put_native_port_mdev(ibdev
, port_num
);
243 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
246 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
247 struct net_device
*ndev
;
248 struct mlx5_core_dev
*mdev
;
250 mdev
= mlx5_ib_get_native_port_mdev(ibdev
, port_num
, NULL
);
254 ndev
= mlx5_lag_get_roce_netdev(mdev
);
258 /* Ensure ndev does not disappear before we invoke dev_hold()
260 read_lock(&ibdev
->roce
[port_num
- 1].netdev_lock
);
261 ndev
= ibdev
->roce
[port_num
- 1].netdev
;
264 read_unlock(&ibdev
->roce
[port_num
- 1].netdev_lock
);
267 mlx5_ib_put_native_port_mdev(ibdev
, port_num
);
271 struct mlx5_core_dev
*mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev
*ibdev
,
275 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&ibdev
->ib_dev
,
277 struct mlx5_core_dev
*mdev
= NULL
;
278 struct mlx5_ib_multiport_info
*mpi
;
279 struct mlx5_ib_port
*port
;
281 if (!mlx5_core_mp_enabled(ibdev
->mdev
) ||
282 ll
!= IB_LINK_LAYER_ETHERNET
) {
284 *native_port_num
= ib_port_num
;
289 *native_port_num
= 1;
291 port
= &ibdev
->port
[ib_port_num
- 1];
295 spin_lock(&port
->mp
.mpi_lock
);
296 mpi
= ibdev
->port
[ib_port_num
- 1].mp
.mpi
;
297 if (mpi
&& !mpi
->unaffiliate
) {
299 /* If it's the master no need to refcount, it'll exist
300 * as long as the ib_dev exists.
305 spin_unlock(&port
->mp
.mpi_lock
);
310 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev
*ibdev
, u8 port_num
)
312 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&ibdev
->ib_dev
,
314 struct mlx5_ib_multiport_info
*mpi
;
315 struct mlx5_ib_port
*port
;
317 if (!mlx5_core_mp_enabled(ibdev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
320 port
= &ibdev
->port
[port_num
- 1];
322 spin_lock(&port
->mp
.mpi_lock
);
323 mpi
= ibdev
->port
[port_num
- 1].mp
.mpi
;
328 if (mpi
->unaffiliate
)
329 complete(&mpi
->unref_comp
);
331 spin_unlock(&port
->mp
.mpi_lock
);
334 static int translate_eth_legacy_proto_oper(u32 eth_proto_oper
, u8
*active_speed
,
337 switch (eth_proto_oper
) {
338 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII
):
339 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX
):
340 case MLX5E_PROT_MASK(MLX5E_100BASE_TX
):
341 case MLX5E_PROT_MASK(MLX5E_1000BASE_T
):
342 *active_width
= IB_WIDTH_1X
;
343 *active_speed
= IB_SPEED_SDR
;
345 case MLX5E_PROT_MASK(MLX5E_10GBASE_T
):
346 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4
):
347 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4
):
348 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR
):
349 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR
):
350 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR
):
351 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER
):
352 *active_width
= IB_WIDTH_1X
;
353 *active_speed
= IB_SPEED_QDR
;
355 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR
):
356 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR
):
357 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR
):
358 *active_width
= IB_WIDTH_1X
;
359 *active_speed
= IB_SPEED_EDR
;
361 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4
):
362 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4
):
363 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4
):
364 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4
):
365 *active_width
= IB_WIDTH_4X
;
366 *active_speed
= IB_SPEED_QDR
;
368 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2
):
369 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2
):
370 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2
):
371 *active_width
= IB_WIDTH_1X
;
372 *active_speed
= IB_SPEED_HDR
;
374 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4
):
375 *active_width
= IB_WIDTH_4X
;
376 *active_speed
= IB_SPEED_FDR
;
378 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4
):
379 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4
):
380 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4
):
381 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4
):
382 *active_width
= IB_WIDTH_4X
;
383 *active_speed
= IB_SPEED_EDR
;
392 static int translate_eth_ext_proto_oper(u32 eth_proto_oper
, u8
*active_speed
,
395 switch (eth_proto_oper
) {
396 case MLX5E_PROT_MASK(MLX5E_SGMII_100M
):
397 case MLX5E_PROT_MASK(MLX5E_1000BASE_X_SGMII
):
398 *active_width
= IB_WIDTH_1X
;
399 *active_speed
= IB_SPEED_SDR
;
401 case MLX5E_PROT_MASK(MLX5E_5GBASE_R
):
402 *active_width
= IB_WIDTH_1X
;
403 *active_speed
= IB_SPEED_DDR
;
405 case MLX5E_PROT_MASK(MLX5E_10GBASE_XFI_XAUI_1
):
406 *active_width
= IB_WIDTH_1X
;
407 *active_speed
= IB_SPEED_QDR
;
409 case MLX5E_PROT_MASK(MLX5E_40GBASE_XLAUI_4_XLPPI_4
):
410 *active_width
= IB_WIDTH_4X
;
411 *active_speed
= IB_SPEED_QDR
;
413 case MLX5E_PROT_MASK(MLX5E_25GAUI_1_25GBASE_CR_KR
):
414 *active_width
= IB_WIDTH_1X
;
415 *active_speed
= IB_SPEED_EDR
;
417 case MLX5E_PROT_MASK(MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2
):
418 *active_width
= IB_WIDTH_2X
;
419 *active_speed
= IB_SPEED_EDR
;
421 case MLX5E_PROT_MASK(MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR
):
422 *active_width
= IB_WIDTH_1X
;
423 *active_speed
= IB_SPEED_HDR
;
425 case MLX5E_PROT_MASK(MLX5E_CAUI_4_100GBASE_CR4_KR4
):
426 *active_width
= IB_WIDTH_4X
;
427 *active_speed
= IB_SPEED_EDR
;
429 case MLX5E_PROT_MASK(MLX5E_100GAUI_2_100GBASE_CR2_KR2
):
430 *active_width
= IB_WIDTH_2X
;
431 *active_speed
= IB_SPEED_HDR
;
433 case MLX5E_PROT_MASK(MLX5E_200GAUI_4_200GBASE_CR4_KR4
):
434 *active_width
= IB_WIDTH_4X
;
435 *active_speed
= IB_SPEED_HDR
;
444 static int translate_eth_proto_oper(u32 eth_proto_oper
, u8
*active_speed
,
445 u8
*active_width
, bool ext
)
448 translate_eth_ext_proto_oper(eth_proto_oper
, active_speed
,
450 translate_eth_legacy_proto_oper(eth_proto_oper
, active_speed
,
454 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
455 struct ib_port_attr
*props
)
457 struct mlx5_ib_dev
*dev
= to_mdev(device
);
458 u32 out
[MLX5_ST_SZ_DW(ptys_reg
)] = {0};
459 struct mlx5_core_dev
*mdev
;
460 struct net_device
*ndev
, *upper
;
461 enum ib_mtu ndev_ib_mtu
;
462 bool put_mdev
= true;
469 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
, &mdev_port_num
);
471 /* This means the port isn't affiliated yet. Get the
472 * info for the master port instead.
480 /* Possible bad flows are checked before filling out props so in case
481 * of an error it will still be zeroed out.
483 err
= mlx5_query_port_ptys(mdev
, out
, sizeof(out
), MLX5_PTYS_EN
,
487 ext
= MLX5_CAP_PCAM_FEATURE(dev
->mdev
, ptys_extended_ethernet
);
488 eth_prot_oper
= MLX5_GET_ETH_PROTO(ptys_reg
, out
, ext
, eth_proto_oper
);
490 props
->active_width
= IB_WIDTH_4X
;
491 props
->active_speed
= IB_SPEED_QDR
;
493 translate_eth_proto_oper(eth_prot_oper
, &props
->active_speed
,
494 &props
->active_width
, ext
);
496 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
497 props
->ip_gids
= true;
499 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
500 roce_address_table_size
);
501 props
->max_mtu
= IB_MTU_4096
;
502 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
503 props
->pkey_tbl_len
= 1;
504 props
->state
= IB_PORT_DOWN
;
505 props
->phys_state
= 3;
507 mlx5_query_nic_vport_qkey_viol_cntr(mdev
, &qkey_viol_cntr
);
508 props
->qkey_viol_cntr
= qkey_viol_cntr
;
510 /* If this is a stub query for an unaffiliated port stop here */
514 ndev
= mlx5_ib_get_netdev(device
, port_num
);
518 if (dev
->lag_active
) {
520 upper
= netdev_master_upper_dev_get_rcu(ndev
);
529 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
530 props
->state
= IB_PORT_ACTIVE
;
531 props
->phys_state
= 5;
534 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
538 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
541 mlx5_ib_put_native_port_mdev(dev
, port_num
);
545 struct mlx5_ib_vlan_info
{
550 static int get_lower_dev_vlan(struct net_device
*lower_dev
, void *data
)
552 struct mlx5_ib_vlan_info
*vlan_info
= data
;
554 if (is_vlan_dev(lower_dev
)) {
555 vlan_info
->vlan
= true;
556 vlan_info
->vlan_id
= vlan_dev_vlan_id(lower_dev
);
558 /* We are interested only in first level vlan device, so
559 * always return 1 to stop iterating over next level devices.
564 static int set_roce_addr(struct mlx5_ib_dev
*dev
, u8 port_num
,
565 unsigned int index
, const union ib_gid
*gid
,
566 const struct ib_gid_attr
*attr
)
568 enum ib_gid_type gid_type
= IB_GID_TYPE_IB
;
569 struct mlx5_ib_vlan_info vlan_info
= { };
575 gid_type
= attr
->gid_type
;
576 ether_addr_copy(mac
, attr
->ndev
->dev_addr
);
578 if (is_vlan_dev(attr
->ndev
)) {
579 vlan_info
.vlan
= true;
580 vlan_info
.vlan_id
= vlan_dev_vlan_id(attr
->ndev
);
582 /* If the netdev is upper device and if it's lower
583 * lower device is vlan device, consider vlan id of
584 * the lower vlan device for this gid entry.
587 netdev_walk_all_lower_dev_rcu(attr
->ndev
,
588 get_lower_dev_vlan
, &vlan_info
);
595 roce_version
= MLX5_ROCE_VERSION_1
;
597 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
598 roce_version
= MLX5_ROCE_VERSION_2
;
599 if (ipv6_addr_v4mapped((void *)gid
))
600 roce_l3_type
= MLX5_ROCE_L3_TYPE_IPV4
;
602 roce_l3_type
= MLX5_ROCE_L3_TYPE_IPV6
;
606 mlx5_ib_warn(dev
, "Unexpected GID type %u\n", gid_type
);
609 return mlx5_core_roce_gid_set(dev
->mdev
, index
, roce_version
,
610 roce_l3_type
, gid
->raw
, mac
,
611 vlan_info
.vlan
, vlan_info
.vlan_id
,
615 static int mlx5_ib_add_gid(const struct ib_gid_attr
*attr
,
616 __always_unused
void **context
)
618 return set_roce_addr(to_mdev(attr
->device
), attr
->port_num
,
619 attr
->index
, &attr
->gid
, attr
);
622 static int mlx5_ib_del_gid(const struct ib_gid_attr
*attr
,
623 __always_unused
void **context
)
625 return set_roce_addr(to_mdev(attr
->device
), attr
->port_num
,
626 attr
->index
, NULL
, NULL
);
629 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
,
630 const struct ib_gid_attr
*attr
)
632 if (attr
->gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
635 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
638 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
640 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_IB
)
641 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
646 MLX5_VPORT_ACCESS_METHOD_MAD
,
647 MLX5_VPORT_ACCESS_METHOD_HCA
,
648 MLX5_VPORT_ACCESS_METHOD_NIC
,
651 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
653 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
654 return MLX5_VPORT_ACCESS_METHOD_MAD
;
656 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
657 IB_LINK_LAYER_ETHERNET
)
658 return MLX5_VPORT_ACCESS_METHOD_NIC
;
660 return MLX5_VPORT_ACCESS_METHOD_HCA
;
663 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
665 struct ib_device_attr
*props
)
668 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
669 u8 atomic_req_8B_endianness_mode
=
670 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianness_mode
);
672 /* Check if HW supports 8 bytes standard atomic operations and capable
673 * of host endianness respond
675 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
676 if (((atomic_operations
& tmp
) == tmp
) &&
677 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
678 (atomic_req_8B_endianness_mode
)) {
679 props
->atomic_cap
= IB_ATOMIC_HCA
;
681 props
->atomic_cap
= IB_ATOMIC_NONE
;
685 static void get_atomic_caps_qp(struct mlx5_ib_dev
*dev
,
686 struct ib_device_attr
*props
)
688 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
690 get_atomic_caps(dev
, atomic_size_qp
, props
);
693 static void get_atomic_caps_dc(struct mlx5_ib_dev
*dev
,
694 struct ib_device_attr
*props
)
696 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_dc
);
698 get_atomic_caps(dev
, atomic_size_qp
, props
);
701 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev
*dev
)
703 struct ib_device_attr props
= {};
705 get_atomic_caps_dc(dev
, &props
);
706 return (props
.atomic_cap
== IB_ATOMIC_HCA
) ? true : false;
708 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
709 __be64
*sys_image_guid
)
711 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
712 struct mlx5_core_dev
*mdev
= dev
->mdev
;
716 switch (mlx5_get_vport_access_method(ibdev
)) {
717 case MLX5_VPORT_ACCESS_METHOD_MAD
:
718 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
721 case MLX5_VPORT_ACCESS_METHOD_HCA
:
722 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
725 case MLX5_VPORT_ACCESS_METHOD_NIC
:
726 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
734 *sys_image_guid
= cpu_to_be64(tmp
);
740 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
743 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
744 struct mlx5_core_dev
*mdev
= dev
->mdev
;
746 switch (mlx5_get_vport_access_method(ibdev
)) {
747 case MLX5_VPORT_ACCESS_METHOD_MAD
:
748 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
750 case MLX5_VPORT_ACCESS_METHOD_HCA
:
751 case MLX5_VPORT_ACCESS_METHOD_NIC
:
752 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
761 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
764 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
766 switch (mlx5_get_vport_access_method(ibdev
)) {
767 case MLX5_VPORT_ACCESS_METHOD_MAD
:
768 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
770 case MLX5_VPORT_ACCESS_METHOD_HCA
:
771 case MLX5_VPORT_ACCESS_METHOD_NIC
:
772 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
779 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
785 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
786 case MLX5_VPORT_ACCESS_METHOD_MAD
:
787 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
789 case MLX5_VPORT_ACCESS_METHOD_HCA
:
790 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
793 case MLX5_VPORT_ACCESS_METHOD_NIC
:
794 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
802 *node_guid
= cpu_to_be64(tmp
);
807 struct mlx5_reg_node_desc
{
808 u8 desc
[IB_DEVICE_NODE_DESC_MAX
];
811 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
813 struct mlx5_reg_node_desc in
;
815 if (mlx5_use_mad_ifc(dev
))
816 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
818 memset(&in
, 0, sizeof(in
));
820 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
821 sizeof(struct mlx5_reg_node_desc
),
822 MLX5_REG_NODE_DESC
, 0, 0);
825 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
826 struct ib_device_attr
*props
,
827 struct ib_udata
*uhw
)
829 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
830 struct mlx5_core_dev
*mdev
= dev
->mdev
;
835 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
836 bool raw_support
= !mlx5_core_mp_enabled(mdev
);
837 struct mlx5_ib_query_device_resp resp
= {};
841 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
842 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
845 resp
.response_length
= resp_len
;
847 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
850 memset(props
, 0, sizeof(*props
));
851 err
= mlx5_query_system_image_guid(ibdev
,
852 &props
->sys_image_guid
);
856 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
860 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
864 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
865 (fw_rev_min(dev
->mdev
) << 16) |
866 fw_rev_sub(dev
->mdev
);
867 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
868 IB_DEVICE_PORT_ACTIVE_EVENT
|
869 IB_DEVICE_SYS_IMAGE_GUID
|
870 IB_DEVICE_RC_RNR_NAK_GEN
;
872 if (MLX5_CAP_GEN(mdev
, pkv
))
873 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
874 if (MLX5_CAP_GEN(mdev
, qkv
))
875 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
876 if (MLX5_CAP_GEN(mdev
, apm
))
877 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
878 if (MLX5_CAP_GEN(mdev
, xrc
))
879 props
->device_cap_flags
|= IB_DEVICE_XRC
;
880 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
881 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
882 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
883 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
884 /* We support 'Gappy' memory registration too */
885 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
887 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
888 if (MLX5_CAP_GEN(mdev
, sho
)) {
889 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
890 /* At this stage no support for signature handover */
891 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
892 IB_PROT_T10DIF_TYPE_2
|
893 IB_PROT_T10DIF_TYPE_3
;
894 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
895 IB_GUARD_T10DIF_CSUM
;
897 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
898 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
900 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) && raw_support
) {
901 if (MLX5_CAP_ETH(mdev
, csum_cap
)) {
902 /* Legacy bit to support old userspace libraries */
903 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
904 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_IP_CSUM
;
907 if (MLX5_CAP_ETH(dev
->mdev
, vlan_cap
))
908 props
->raw_packet_caps
|=
909 IB_RAW_PACKET_CAP_CVLAN_STRIPPING
;
911 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
912 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
914 resp
.tso_caps
.max_tso
= 1 << max_tso
;
915 resp
.tso_caps
.supported_qpts
|=
916 1 << IB_QPT_RAW_PACKET
;
917 resp
.response_length
+= sizeof(resp
.tso_caps
);
921 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
)) {
922 resp
.rss_caps
.rx_hash_function
=
923 MLX5_RX_HASH_FUNC_TOEPLITZ
;
924 resp
.rss_caps
.rx_hash_fields_mask
=
925 MLX5_RX_HASH_SRC_IPV4
|
926 MLX5_RX_HASH_DST_IPV4
|
927 MLX5_RX_HASH_SRC_IPV6
|
928 MLX5_RX_HASH_DST_IPV6
|
929 MLX5_RX_HASH_SRC_PORT_TCP
|
930 MLX5_RX_HASH_DST_PORT_TCP
|
931 MLX5_RX_HASH_SRC_PORT_UDP
|
932 MLX5_RX_HASH_DST_PORT_UDP
|
934 if (mlx5_accel_ipsec_device_caps(dev
->mdev
) &
935 MLX5_ACCEL_IPSEC_CAP_DEVICE
)
936 resp
.rss_caps
.rx_hash_fields_mask
|=
937 MLX5_RX_HASH_IPSEC_SPI
;
938 resp
.response_length
+= sizeof(resp
.rss_caps
);
941 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
))
942 resp
.response_length
+= sizeof(resp
.tso_caps
);
943 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
))
944 resp
.response_length
+= sizeof(resp
.rss_caps
);
947 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
948 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
949 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
952 if (MLX5_CAP_GEN(dev
->mdev
, rq_delay_drop
) &&
953 MLX5_CAP_GEN(dev
->mdev
, general_notification_event
) &&
955 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_DELAY_DROP
;
957 if (MLX5_CAP_GEN(mdev
, ipoib_enhanced_offloads
) &&
958 MLX5_CAP_IPOIB_ENHANCED(mdev
, csum_cap
))
959 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
961 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
962 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
) &&
964 /* Legacy bit to support old userspace libraries */
965 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
966 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_SCATTER_FCS
;
969 if (MLX5_CAP_DEV_MEM(mdev
, memic
)) {
971 MLX5_CAP_DEV_MEM(mdev
, max_memic_size
);
974 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
975 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
977 if (MLX5_CAP_GEN(mdev
, end_pad
))
978 props
->device_cap_flags
|= IB_DEVICE_PCI_WRITE_END_PADDING
;
980 props
->vendor_part_id
= mdev
->pdev
->device
;
981 props
->hw_ver
= mdev
->pdev
->revision
;
983 props
->max_mr_size
= ~0ull;
984 props
->page_size_cap
= ~(min_page_size
- 1);
985 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
986 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
987 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
988 sizeof(struct mlx5_wqe_data_seg
);
989 max_sq_desc
= min_t(int, MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
), 512);
990 max_sq_sg
= (max_sq_desc
- sizeof(struct mlx5_wqe_ctrl_seg
) -
991 sizeof(struct mlx5_wqe_raddr_seg
)) /
992 sizeof(struct mlx5_wqe_data_seg
);
993 props
->max_send_sge
= max_sq_sg
;
994 props
->max_recv_sge
= max_rq_sg
;
995 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
996 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
997 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
998 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
999 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
1000 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
1001 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
1002 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
1003 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
1004 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
1005 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
1006 props
->max_srq_sge
= max_rq_sg
- 1;
1007 props
->max_fast_reg_page_list_len
=
1008 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
1009 get_atomic_caps_qp(dev
, props
);
1010 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
1011 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
1012 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
1013 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
1014 props
->max_mcast_grp
;
1015 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
1016 props
->max_ah
= INT_MAX
;
1017 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
1018 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
1020 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
)) {
1021 if (MLX5_CAP_GEN(mdev
, pg
))
1022 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
1023 props
->odp_caps
= dev
->odp_caps
;
1026 if (MLX5_CAP_GEN(mdev
, cd
))
1027 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
1029 if (!mlx5_core_is_pf(mdev
))
1030 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
1032 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
1033 IB_LINK_LAYER_ETHERNET
&& raw_support
) {
1034 props
->rss_caps
.max_rwq_indirection_tables
=
1035 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt
);
1036 props
->rss_caps
.max_rwq_indirection_table_size
=
1037 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
);
1038 props
->rss_caps
.supported_qpts
= 1 << IB_QPT_RAW_PACKET
;
1039 props
->max_wq_type_rq
=
1040 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rq
);
1043 if (MLX5_CAP_GEN(mdev
, tag_matching
)) {
1044 props
->tm_caps
.max_rndv_hdr_size
= MLX5_TM_MAX_RNDV_MSG_SIZE
;
1045 props
->tm_caps
.max_num_tags
=
1046 (1 << MLX5_CAP_GEN(mdev
, log_tag_matching_list_sz
)) - 1;
1047 props
->tm_caps
.flags
= IB_TM_CAP_RC
;
1048 props
->tm_caps
.max_ops
=
1049 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
1050 props
->tm_caps
.max_sge
= MLX5_TM_MAX_SGE
;
1053 if (MLX5_CAP_GEN(dev
->mdev
, cq_moderation
)) {
1054 props
->cq_caps
.max_cq_moderation_count
=
1056 props
->cq_caps
.max_cq_moderation_period
=
1060 if (field_avail(typeof(resp
), cqe_comp_caps
, uhw
->outlen
)) {
1061 resp
.response_length
+= sizeof(resp
.cqe_comp_caps
);
1063 if (MLX5_CAP_GEN(dev
->mdev
, cqe_compression
)) {
1064 resp
.cqe_comp_caps
.max_num
=
1065 MLX5_CAP_GEN(dev
->mdev
,
1066 cqe_compression_max_num
);
1068 resp
.cqe_comp_caps
.supported_format
=
1069 MLX5_IB_CQE_RES_FORMAT_HASH
|
1070 MLX5_IB_CQE_RES_FORMAT_CSUM
;
1072 if (MLX5_CAP_GEN(dev
->mdev
, mini_cqe_resp_stride_index
))
1073 resp
.cqe_comp_caps
.supported_format
|=
1074 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX
;
1078 if (field_avail(typeof(resp
), packet_pacing_caps
, uhw
->outlen
) &&
1080 if (MLX5_CAP_QOS(mdev
, packet_pacing
) &&
1081 MLX5_CAP_GEN(mdev
, qos
)) {
1082 resp
.packet_pacing_caps
.qp_rate_limit_max
=
1083 MLX5_CAP_QOS(mdev
, packet_pacing_max_rate
);
1084 resp
.packet_pacing_caps
.qp_rate_limit_min
=
1085 MLX5_CAP_QOS(mdev
, packet_pacing_min_rate
);
1086 resp
.packet_pacing_caps
.supported_qpts
|=
1087 1 << IB_QPT_RAW_PACKET
;
1088 if (MLX5_CAP_QOS(mdev
, packet_pacing_burst_bound
) &&
1089 MLX5_CAP_QOS(mdev
, packet_pacing_typical_size
))
1090 resp
.packet_pacing_caps
.cap_flags
|=
1091 MLX5_IB_PP_SUPPORT_BURST
;
1093 resp
.response_length
+= sizeof(resp
.packet_pacing_caps
);
1096 if (field_avail(typeof(resp
), mlx5_ib_support_multi_pkt_send_wqes
,
1098 if (MLX5_CAP_ETH(mdev
, multi_pkt_send_wqe
))
1099 resp
.mlx5_ib_support_multi_pkt_send_wqes
=
1102 if (MLX5_CAP_ETH(mdev
, enhanced_multi_pkt_send_wqe
))
1103 resp
.mlx5_ib_support_multi_pkt_send_wqes
|=
1104 MLX5_IB_SUPPORT_EMPW
;
1106 resp
.response_length
+=
1107 sizeof(resp
.mlx5_ib_support_multi_pkt_send_wqes
);
1110 if (field_avail(typeof(resp
), flags
, uhw
->outlen
)) {
1111 resp
.response_length
+= sizeof(resp
.flags
);
1113 if (MLX5_CAP_GEN(mdev
, cqe_compression_128
))
1115 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP
;
1117 if (MLX5_CAP_GEN(mdev
, cqe_128_always
))
1118 resp
.flags
|= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD
;
1119 if (MLX5_CAP_GEN(mdev
, qp_packet_based
))
1121 MLX5_IB_QUERY_DEV_RESP_PACKET_BASED_CREDIT_MODE
;
1124 if (field_avail(typeof(resp
), sw_parsing_caps
,
1126 resp
.response_length
+= sizeof(resp
.sw_parsing_caps
);
1127 if (MLX5_CAP_ETH(mdev
, swp
)) {
1128 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1131 if (MLX5_CAP_ETH(mdev
, swp_csum
))
1132 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1133 MLX5_IB_SW_PARSING_CSUM
;
1135 if (MLX5_CAP_ETH(mdev
, swp_lso
))
1136 resp
.sw_parsing_caps
.sw_parsing_offloads
|=
1137 MLX5_IB_SW_PARSING_LSO
;
1139 if (resp
.sw_parsing_caps
.sw_parsing_offloads
)
1140 resp
.sw_parsing_caps
.supported_qpts
=
1141 BIT(IB_QPT_RAW_PACKET
);
1145 if (field_avail(typeof(resp
), striding_rq_caps
, uhw
->outlen
) &&
1147 resp
.response_length
+= sizeof(resp
.striding_rq_caps
);
1148 if (MLX5_CAP_GEN(mdev
, striding_rq
)) {
1149 resp
.striding_rq_caps
.min_single_stride_log_num_of_bytes
=
1150 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES
;
1151 resp
.striding_rq_caps
.max_single_stride_log_num_of_bytes
=
1152 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES
;
1153 resp
.striding_rq_caps
.min_single_wqe_log_num_of_strides
=
1154 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES
;
1155 resp
.striding_rq_caps
.max_single_wqe_log_num_of_strides
=
1156 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES
;
1157 resp
.striding_rq_caps
.supported_qpts
=
1158 BIT(IB_QPT_RAW_PACKET
);
1162 if (field_avail(typeof(resp
), tunnel_offloads_caps
,
1164 resp
.response_length
+= sizeof(resp
.tunnel_offloads_caps
);
1165 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_vxlan
))
1166 resp
.tunnel_offloads_caps
|=
1167 MLX5_IB_TUNNELED_OFFLOADS_VXLAN
;
1168 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_geneve_rx
))
1169 resp
.tunnel_offloads_caps
|=
1170 MLX5_IB_TUNNELED_OFFLOADS_GENEVE
;
1171 if (MLX5_CAP_ETH(mdev
, tunnel_stateless_gre
))
1172 resp
.tunnel_offloads_caps
|=
1173 MLX5_IB_TUNNELED_OFFLOADS_GRE
;
1174 if (MLX5_CAP_GEN(mdev
, flex_parser_protocols
) &
1175 MLX5_FLEX_PROTO_CW_MPLS_GRE
)
1176 resp
.tunnel_offloads_caps
|=
1177 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE
;
1178 if (MLX5_CAP_GEN(mdev
, flex_parser_protocols
) &
1179 MLX5_FLEX_PROTO_CW_MPLS_UDP
)
1180 resp
.tunnel_offloads_caps
|=
1181 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP
;
1185 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
1194 enum mlx5_ib_width
{
1195 MLX5_IB_WIDTH_1X
= 1 << 0,
1196 MLX5_IB_WIDTH_2X
= 1 << 1,
1197 MLX5_IB_WIDTH_4X
= 1 << 2,
1198 MLX5_IB_WIDTH_8X
= 1 << 3,
1199 MLX5_IB_WIDTH_12X
= 1 << 4
1202 static void translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
1205 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1207 if (active_width
& MLX5_IB_WIDTH_1X
)
1208 *ib_width
= IB_WIDTH_1X
;
1209 else if (active_width
& MLX5_IB_WIDTH_2X
)
1210 *ib_width
= IB_WIDTH_2X
;
1211 else if (active_width
& MLX5_IB_WIDTH_4X
)
1212 *ib_width
= IB_WIDTH_4X
;
1213 else if (active_width
& MLX5_IB_WIDTH_8X
)
1214 *ib_width
= IB_WIDTH_8X
;
1215 else if (active_width
& MLX5_IB_WIDTH_12X
)
1216 *ib_width
= IB_WIDTH_12X
;
1218 mlx5_ib_dbg(dev
, "Invalid active_width %d, setting width to default value: 4x\n",
1220 *ib_width
= IB_WIDTH_4X
;
1226 static int mlx5_mtu_to_ib_mtu(int mtu
)
1231 case 1024: return 3;
1232 case 2048: return 4;
1233 case 4096: return 5;
1235 pr_warn("invalid mtu\n");
1240 enum ib_max_vl_num
{
1242 __IB_MAX_VL_0_1
= 2,
1243 __IB_MAX_VL_0_3
= 3,
1244 __IB_MAX_VL_0_7
= 4,
1245 __IB_MAX_VL_0_14
= 5,
1248 enum mlx5_vl_hw_cap
{
1257 MLX5_VL_HW_0_14
= 15
1260 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
1263 switch (vl_hw_cap
) {
1265 *max_vl_num
= __IB_MAX_VL_0
;
1267 case MLX5_VL_HW_0_1
:
1268 *max_vl_num
= __IB_MAX_VL_0_1
;
1270 case MLX5_VL_HW_0_3
:
1271 *max_vl_num
= __IB_MAX_VL_0_3
;
1273 case MLX5_VL_HW_0_7
:
1274 *max_vl_num
= __IB_MAX_VL_0_7
;
1276 case MLX5_VL_HW_0_14
:
1277 *max_vl_num
= __IB_MAX_VL_0_14
;
1287 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
1288 struct ib_port_attr
*props
)
1290 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1291 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1292 struct mlx5_hca_vport_context
*rep
;
1296 u8 ib_link_width_oper
;
1299 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
1305 /* props being zeroed by the caller, avoid zeroing it here */
1307 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
1311 props
->lid
= rep
->lid
;
1312 props
->lmc
= rep
->lmc
;
1313 props
->sm_lid
= rep
->sm_lid
;
1314 props
->sm_sl
= rep
->sm_sl
;
1315 props
->state
= rep
->vport_state
;
1316 props
->phys_state
= rep
->port_physical_state
;
1317 props
->port_cap_flags
= rep
->cap_mask1
;
1318 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
1319 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
1320 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
1321 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
1322 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
1323 props
->subnet_timeout
= rep
->subnet_timeout
;
1324 props
->init_type_reply
= rep
->init_type_reply
;
1326 if (props
->port_cap_flags
& IB_PORT_CAP_MASK2_SUP
)
1327 props
->port_cap_flags2
= rep
->cap_mask2
;
1329 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
1333 translate_active_width(ibdev
, ib_link_width_oper
, &props
->active_width
);
1335 err
= mlx5_query_port_ib_proto_oper(mdev
, &props
->active_speed
, port
);
1339 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
1341 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
1343 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
1345 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
1347 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
1351 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
1352 &props
->max_vl_num
);
1358 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
1359 struct ib_port_attr
*props
)
1364 switch (mlx5_get_vport_access_method(ibdev
)) {
1365 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1366 ret
= mlx5_query_mad_ifc_port(ibdev
, port
, props
);
1369 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1370 ret
= mlx5_query_hca_port(ibdev
, port
, props
);
1373 case MLX5_VPORT_ACCESS_METHOD_NIC
:
1374 ret
= mlx5_query_port_roce(ibdev
, port
, props
);
1381 if (!ret
&& props
) {
1382 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1383 struct mlx5_core_dev
*mdev
;
1384 bool put_mdev
= true;
1386 mdev
= mlx5_ib_get_native_port_mdev(dev
, port
, NULL
);
1388 /* If the port isn't affiliated yet query the master.
1389 * The master and slave will have the same values.
1395 count
= mlx5_core_reserved_gids_count(mdev
);
1397 mlx5_ib_put_native_port_mdev(dev
, port
);
1398 props
->gid_tbl_len
-= count
;
1403 static int mlx5_ib_rep_query_port(struct ib_device
*ibdev
, u8 port
,
1404 struct ib_port_attr
*props
)
1408 /* Only link layer == ethernet is valid for representors */
1409 ret
= mlx5_query_port_roce(ibdev
, port
, props
);
1413 /* We don't support GIDS */
1414 props
->gid_tbl_len
= 0;
1419 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
1422 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1423 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1425 switch (mlx5_get_vport_access_method(ibdev
)) {
1426 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1427 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
1429 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1430 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
1438 static int mlx5_query_hca_nic_pkey(struct ib_device
*ibdev
, u8 port
,
1439 u16 index
, u16
*pkey
)
1441 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1442 struct mlx5_core_dev
*mdev
;
1443 bool put_mdev
= true;
1447 mdev
= mlx5_ib_get_native_port_mdev(dev
, port
, &mdev_port_num
);
1449 /* The port isn't affiliated yet, get the PKey from the master
1450 * port. For RoCE the PKey tables will be the same.
1457 err
= mlx5_query_hca_vport_pkey(mdev
, 0, mdev_port_num
, 0,
1460 mlx5_ib_put_native_port_mdev(dev
, port
);
1465 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
1468 switch (mlx5_get_vport_access_method(ibdev
)) {
1469 case MLX5_VPORT_ACCESS_METHOD_MAD
:
1470 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
1472 case MLX5_VPORT_ACCESS_METHOD_HCA
:
1473 case MLX5_VPORT_ACCESS_METHOD_NIC
:
1474 return mlx5_query_hca_nic_pkey(ibdev
, port
, index
, pkey
);
1480 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
1481 struct ib_device_modify
*props
)
1483 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1484 struct mlx5_reg_node_desc in
;
1485 struct mlx5_reg_node_desc out
;
1488 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
1491 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
1495 * If possible, pass node desc to FW, so it can generate
1496 * a 144 trap. If cmd fails, just ignore.
1498 memcpy(&in
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
1499 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
1500 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
1504 memcpy(ibdev
->node_desc
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
1509 static int set_port_caps_atomic(struct mlx5_ib_dev
*dev
, u8 port_num
, u32 mask
,
1512 struct mlx5_hca_vport_context ctx
= {};
1513 struct mlx5_core_dev
*mdev
;
1517 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
, &mdev_port_num
);
1521 err
= mlx5_query_hca_vport_context(mdev
, 0, mdev_port_num
, 0, &ctx
);
1525 if (~ctx
.cap_mask1_perm
& mask
) {
1526 mlx5_ib_warn(dev
, "trying to change bitmask 0x%X but change supported 0x%X\n",
1527 mask
, ctx
.cap_mask1_perm
);
1532 ctx
.cap_mask1
= value
;
1533 ctx
.cap_mask1_perm
= mask
;
1534 err
= mlx5_core_modify_hca_vport_context(mdev
, 0, mdev_port_num
,
1538 mlx5_ib_put_native_port_mdev(dev
, port_num
);
1543 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
1544 struct ib_port_modify
*props
)
1546 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1547 struct ib_port_attr attr
;
1552 bool is_ib
= (mlx5_ib_port_link_layer(ibdev
, port
) ==
1553 IB_LINK_LAYER_INFINIBAND
);
1555 /* CM layer calls ib_modify_port() regardless of the link layer. For
1556 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1561 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
) && is_ib
) {
1562 change_mask
= props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1563 value
= ~props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1564 return set_port_caps_atomic(dev
, port
, change_mask
, value
);
1567 mutex_lock(&dev
->cap_mask_mutex
);
1569 err
= ib_query_port(ibdev
, port
, &attr
);
1573 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
1574 ~props
->clr_port_cap_mask
;
1576 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
1579 mutex_unlock(&dev
->cap_mask_mutex
);
1583 static void print_lib_caps(struct mlx5_ib_dev
*dev
, u64 caps
)
1585 mlx5_ib_dbg(dev
, "MLX5_LIB_CAP_4K_UAR = %s\n",
1586 caps
& MLX5_LIB_CAP_4K_UAR
? "y" : "n");
1589 static u16
calc_dynamic_bfregs(int uars_per_sys_page
)
1591 /* Large page with non 4k uar support might limit the dynamic size */
1592 if (uars_per_sys_page
== 1 && PAGE_SIZE
> 4096)
1593 return MLX5_MIN_DYN_BFREGS
;
1595 return MLX5_MAX_DYN_BFREGS
;
1598 static int calc_total_bfregs(struct mlx5_ib_dev
*dev
, bool lib_uar_4k
,
1599 struct mlx5_ib_alloc_ucontext_req_v2
*req
,
1600 struct mlx5_bfreg_info
*bfregi
)
1602 int uars_per_sys_page
;
1603 int bfregs_per_sys_page
;
1604 int ref_bfregs
= req
->total_num_bfregs
;
1606 if (req
->total_num_bfregs
== 0)
1609 BUILD_BUG_ON(MLX5_MAX_BFREGS
% MLX5_NON_FP_BFREGS_IN_PAGE
);
1610 BUILD_BUG_ON(MLX5_MAX_BFREGS
< MLX5_NON_FP_BFREGS_IN_PAGE
);
1612 if (req
->total_num_bfregs
> MLX5_MAX_BFREGS
)
1615 uars_per_sys_page
= get_uars_per_sys_page(dev
, lib_uar_4k
);
1616 bfregs_per_sys_page
= uars_per_sys_page
* MLX5_NON_FP_BFREGS_PER_UAR
;
1617 /* This holds the required static allocation asked by the user */
1618 req
->total_num_bfregs
= ALIGN(req
->total_num_bfregs
, bfregs_per_sys_page
);
1619 if (req
->num_low_latency_bfregs
> req
->total_num_bfregs
- 1)
1622 bfregi
->num_static_sys_pages
= req
->total_num_bfregs
/ bfregs_per_sys_page
;
1623 bfregi
->num_dyn_bfregs
= ALIGN(calc_dynamic_bfregs(uars_per_sys_page
), bfregs_per_sys_page
);
1624 bfregi
->total_num_bfregs
= req
->total_num_bfregs
+ bfregi
->num_dyn_bfregs
;
1625 bfregi
->num_sys_pages
= bfregi
->total_num_bfregs
/ bfregs_per_sys_page
;
1627 mlx5_ib_dbg(dev
, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1628 MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? "yes" : "no",
1629 lib_uar_4k
? "yes" : "no", ref_bfregs
,
1630 req
->total_num_bfregs
, bfregi
->total_num_bfregs
,
1631 bfregi
->num_sys_pages
);
1636 static int allocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1638 struct mlx5_bfreg_info
*bfregi
;
1642 bfregi
= &context
->bfregi
;
1643 for (i
= 0; i
< bfregi
->num_static_sys_pages
; i
++) {
1644 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &bfregi
->sys_pages
[i
]);
1648 mlx5_ib_dbg(dev
, "allocated uar %d\n", bfregi
->sys_pages
[i
]);
1651 for (i
= bfregi
->num_static_sys_pages
; i
< bfregi
->num_sys_pages
; i
++)
1652 bfregi
->sys_pages
[i
] = MLX5_IB_INVALID_UAR_INDEX
;
1657 for (--i
; i
>= 0; i
--)
1658 if (mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]))
1659 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1664 static void deallocate_uars(struct mlx5_ib_dev
*dev
,
1665 struct mlx5_ib_ucontext
*context
)
1667 struct mlx5_bfreg_info
*bfregi
;
1670 bfregi
= &context
->bfregi
;
1671 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++)
1672 if (i
< bfregi
->num_static_sys_pages
||
1673 bfregi
->sys_pages
[i
] != MLX5_IB_INVALID_UAR_INDEX
)
1674 mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]);
1677 int mlx5_ib_enable_lb(struct mlx5_ib_dev
*dev
, bool td
, bool qp
)
1681 mutex_lock(&dev
->lb
.mutex
);
1687 if (dev
->lb
.user_td
== 2 ||
1689 if (!dev
->lb
.enabled
) {
1690 err
= mlx5_nic_vport_update_local_lb(dev
->mdev
, true);
1691 dev
->lb
.enabled
= true;
1695 mutex_unlock(&dev
->lb
.mutex
);
1700 void mlx5_ib_disable_lb(struct mlx5_ib_dev
*dev
, bool td
, bool qp
)
1702 mutex_lock(&dev
->lb
.mutex
);
1708 if (dev
->lb
.user_td
== 1 &&
1710 if (dev
->lb
.enabled
) {
1711 mlx5_nic_vport_update_local_lb(dev
->mdev
, false);
1712 dev
->lb
.enabled
= false;
1716 mutex_unlock(&dev
->lb
.mutex
);
1719 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev
*dev
, u32
*tdn
,
1724 if (!MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1727 err
= mlx5_cmd_alloc_transport_domain(dev
->mdev
, tdn
, uid
);
1731 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
) ||
1732 (!MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) &&
1733 !MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
1736 return mlx5_ib_enable_lb(dev
, true, false);
1739 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev
*dev
, u32 tdn
,
1742 if (!MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1745 mlx5_cmd_dealloc_transport_domain(dev
->mdev
, tdn
, uid
);
1747 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) != MLX5_CAP_PORT_TYPE_ETH
) ||
1748 (!MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) &&
1749 !MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
1752 mlx5_ib_disable_lb(dev
, true, false);
1755 static int mlx5_ib_alloc_ucontext(struct ib_ucontext
*uctx
,
1756 struct ib_udata
*udata
)
1758 struct ib_device
*ibdev
= uctx
->device
;
1759 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1760 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
1761 struct mlx5_ib_alloc_ucontext_resp resp
= {};
1762 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1763 struct mlx5_ib_ucontext
*context
= to_mucontext(uctx
);
1764 struct mlx5_bfreg_info
*bfregi
;
1767 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
1772 if (!dev
->ib_active
)
1775 if (udata
->inlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
1777 else if (udata
->inlen
>= min_req_v2
)
1782 err
= ib_copy_from_udata(&req
, udata
, min(udata
->inlen
, sizeof(req
)));
1786 if (req
.flags
& ~MLX5_IB_ALLOC_UCTX_DEVX
)
1789 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
1792 req
.total_num_bfregs
= ALIGN(req
.total_num_bfregs
,
1793 MLX5_NON_FP_BFREGS_PER_UAR
);
1794 if (req
.num_low_latency_bfregs
> req
.total_num_bfregs
- 1)
1797 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
1798 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
1799 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
1800 resp
.cache_line_size
= cache_line_size();
1801 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
1802 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
1803 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1804 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1805 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
1806 resp
.cqe_version
= min_t(__u8
,
1807 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
1808 req
.max_cqe_version
);
1809 resp
.log_uar_size
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1810 MLX5_ADAPTER_PAGE_SHIFT
: PAGE_SHIFT
;
1811 resp
.num_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1812 MLX5_CAP_GEN(dev
->mdev
, num_of_uars_per_page
) : 1;
1813 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
1814 sizeof(resp
.response_length
), udata
->outlen
);
1816 if (mlx5_accel_ipsec_device_caps(dev
->mdev
) & MLX5_ACCEL_IPSEC_CAP_DEVICE
) {
1817 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_EGRESS
))
1818 resp
.flow_action_flags
|= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM
;
1819 if (mlx5_accel_ipsec_device_caps(dev
->mdev
) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA
)
1820 resp
.flow_action_flags
|= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA
;
1821 if (MLX5_CAP_FLOWTABLE(dev
->mdev
, flow_table_properties_nic_receive
.ft_field_support
.outer_esp_spi
))
1822 resp
.flow_action_flags
|= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING
;
1823 if (mlx5_accel_ipsec_device_caps(dev
->mdev
) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN
)
1824 resp
.flow_action_flags
|= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN
;
1825 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1828 lib_uar_4k
= req
.lib_caps
& MLX5_LIB_CAP_4K_UAR
;
1829 bfregi
= &context
->bfregi
;
1831 /* updates req->total_num_bfregs */
1832 err
= calc_total_bfregs(dev
, lib_uar_4k
, &req
, bfregi
);
1836 mutex_init(&bfregi
->lock
);
1837 bfregi
->lib_uar_4k
= lib_uar_4k
;
1838 bfregi
->count
= kcalloc(bfregi
->total_num_bfregs
, sizeof(*bfregi
->count
),
1840 if (!bfregi
->count
) {
1845 bfregi
->sys_pages
= kcalloc(bfregi
->num_sys_pages
,
1846 sizeof(*bfregi
->sys_pages
),
1848 if (!bfregi
->sys_pages
) {
1853 err
= allocate_uars(dev
, context
);
1857 if (ibdev
->attrs
.device_cap_flags
& IB_DEVICE_ON_DEMAND_PAGING
)
1858 context
->ibucontext
.invalidate_range
=
1859 &mlx5_ib_invalidate_range
;
1861 if (req
.flags
& MLX5_IB_ALLOC_UCTX_DEVX
) {
1862 err
= mlx5_ib_devx_create(dev
, true);
1865 context
->devx_uid
= err
;
1868 err
= mlx5_ib_alloc_transport_domain(dev
, &context
->tdn
,
1873 if (MLX5_CAP_GEN(dev
->mdev
, dump_fill_mkey
)) {
1874 err
= mlx5_cmd_dump_fill_mkey(dev
->mdev
, &dump_fill_mkey
);
1879 INIT_LIST_HEAD(&context
->db_page_list
);
1880 mutex_init(&context
->db_page_mutex
);
1882 resp
.tot_bfregs
= req
.total_num_bfregs
;
1883 resp
.num_ports
= dev
->num_ports
;
1885 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1886 resp
.response_length
+= sizeof(resp
.cqe_version
);
1888 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1889 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
|
1890 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH
;
1891 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1894 if (field_avail(typeof(resp
), eth_min_inline
, udata
->outlen
)) {
1895 if (mlx5_ib_port_link_layer(ibdev
, 1) == IB_LINK_LAYER_ETHERNET
) {
1896 mlx5_query_min_inline(dev
->mdev
, &resp
.eth_min_inline
);
1897 resp
.eth_min_inline
++;
1899 resp
.response_length
+= sizeof(resp
.eth_min_inline
);
1902 if (field_avail(typeof(resp
), clock_info_versions
, udata
->outlen
)) {
1903 if (mdev
->clock_info
)
1904 resp
.clock_info_versions
= BIT(MLX5_IB_CLOCK_INFO_V1
);
1905 resp
.response_length
+= sizeof(resp
.clock_info_versions
);
1909 * We don't want to expose information from the PCI bar that is located
1910 * after 4096 bytes, so if the arch only supports larger pages, let's
1911 * pretend we don't support reading the HCA's core clock. This is also
1912 * forced by mmap function.
1914 if (field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1915 if (PAGE_SIZE
<= 4096) {
1917 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1918 resp
.hca_core_clock_offset
=
1919 offsetof(struct mlx5_init_seg
, internal_timer_h
) % PAGE_SIZE
;
1921 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
);
1924 if (field_avail(typeof(resp
), log_uar_size
, udata
->outlen
))
1925 resp
.response_length
+= sizeof(resp
.log_uar_size
);
1927 if (field_avail(typeof(resp
), num_uars_per_page
, udata
->outlen
))
1928 resp
.response_length
+= sizeof(resp
.num_uars_per_page
);
1930 if (field_avail(typeof(resp
), num_dyn_bfregs
, udata
->outlen
)) {
1931 resp
.num_dyn_bfregs
= bfregi
->num_dyn_bfregs
;
1932 resp
.response_length
+= sizeof(resp
.num_dyn_bfregs
);
1935 if (field_avail(typeof(resp
), dump_fill_mkey
, udata
->outlen
)) {
1936 if (MLX5_CAP_GEN(dev
->mdev
, dump_fill_mkey
)) {
1937 resp
.dump_fill_mkey
= dump_fill_mkey
;
1939 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY
;
1941 resp
.response_length
+= sizeof(resp
.dump_fill_mkey
);
1944 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1949 bfregi
->num_low_latency_bfregs
= req
.num_low_latency_bfregs
;
1950 context
->cqe_version
= resp
.cqe_version
;
1951 context
->lib_caps
= req
.lib_caps
;
1952 print_lib_caps(dev
, context
->lib_caps
);
1954 if (dev
->lag_active
) {
1955 u8 port
= mlx5_core_native_port_num(dev
->mdev
);
1957 atomic_set(&context
->tx_port_affinity
,
1959 1, &dev
->roce
[port
].tx_port_affinity
));
1965 mlx5_ib_dealloc_transport_domain(dev
, context
->tdn
, context
->devx_uid
);
1967 if (req
.flags
& MLX5_IB_ALLOC_UCTX_DEVX
)
1968 mlx5_ib_devx_destroy(dev
, context
->devx_uid
);
1971 deallocate_uars(dev
, context
);
1974 kfree(bfregi
->sys_pages
);
1977 kfree(bfregi
->count
);
1983 static void mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1985 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1986 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1987 struct mlx5_bfreg_info
*bfregi
;
1989 /* All umem's must be destroyed before destroying the ucontext. */
1990 mutex_lock(&ibcontext
->per_mm_list_lock
);
1991 WARN_ON(!list_empty(&ibcontext
->per_mm_list
));
1992 mutex_unlock(&ibcontext
->per_mm_list_lock
);
1994 bfregi
= &context
->bfregi
;
1995 mlx5_ib_dealloc_transport_domain(dev
, context
->tdn
, context
->devx_uid
);
1997 if (context
->devx_uid
)
1998 mlx5_ib_devx_destroy(dev
, context
->devx_uid
);
2000 deallocate_uars(dev
, context
);
2001 kfree(bfregi
->sys_pages
);
2002 kfree(bfregi
->count
);
2005 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
,
2008 int fw_uars_per_page
;
2010 fw_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? MLX5_UARS_IN_PAGE
: 1;
2012 return (dev
->mdev
->bar_addr
>> PAGE_SHIFT
) + uar_idx
/ fw_uars_per_page
;
2015 static int get_command(unsigned long offset
)
2017 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
2020 static int get_arg(unsigned long offset
)
2022 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
2025 static int get_index(unsigned long offset
)
2027 return get_arg(offset
);
2030 /* Index resides in an extra byte to enable larger values than 255 */
2031 static int get_extended_index(unsigned long offset
)
2033 return get_arg(offset
) | ((offset
>> 16) & 0xff) << 8;
2037 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
2041 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
2044 case MLX5_IB_MMAP_WC_PAGE
:
2046 case MLX5_IB_MMAP_REGULAR_PAGE
:
2047 return "best effort WC";
2048 case MLX5_IB_MMAP_NC_PAGE
:
2050 case MLX5_IB_MMAP_DEVICE_MEM
:
2051 return "Device Memory";
2057 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev
*dev
,
2058 struct vm_area_struct
*vma
,
2059 struct mlx5_ib_ucontext
*context
)
2061 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2064 if (get_index(vma
->vm_pgoff
) != MLX5_IB_CLOCK_INFO_V1
)
2067 if (vma
->vm_flags
& VM_WRITE
)
2070 if (!dev
->mdev
->clock_info_page
)
2073 return rdma_user_mmap_page(&context
->ibucontext
, vma
,
2074 dev
->mdev
->clock_info_page
, PAGE_SIZE
);
2077 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
2078 struct vm_area_struct
*vma
,
2079 struct mlx5_ib_ucontext
*context
)
2081 struct mlx5_bfreg_info
*bfregi
= &context
->bfregi
;
2086 u32 bfreg_dyn_idx
= 0;
2088 int dyn_uar
= (cmd
== MLX5_IB_MMAP_ALLOC_WC
);
2089 int max_valid_idx
= dyn_uar
? bfregi
->num_sys_pages
:
2090 bfregi
->num_static_sys_pages
;
2092 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2096 idx
= get_extended_index(vma
->vm_pgoff
) + bfregi
->num_static_sys_pages
;
2098 idx
= get_index(vma
->vm_pgoff
);
2100 if (idx
>= max_valid_idx
) {
2101 mlx5_ib_warn(dev
, "invalid uar index %lu, max=%d\n",
2102 idx
, max_valid_idx
);
2107 case MLX5_IB_MMAP_WC_PAGE
:
2108 case MLX5_IB_MMAP_ALLOC_WC
:
2109 /* Some architectures don't support WC memory */
2110 #if defined(CONFIG_X86)
2113 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2117 case MLX5_IB_MMAP_REGULAR_PAGE
:
2118 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2119 prot
= pgprot_writecombine(vma
->vm_page_prot
);
2121 case MLX5_IB_MMAP_NC_PAGE
:
2122 prot
= pgprot_noncached(vma
->vm_page_prot
);
2131 uars_per_page
= get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
);
2132 bfreg_dyn_idx
= idx
* (uars_per_page
* MLX5_NON_FP_BFREGS_PER_UAR
);
2133 if (bfreg_dyn_idx
>= bfregi
->total_num_bfregs
) {
2134 mlx5_ib_warn(dev
, "invalid bfreg_dyn_idx %u, max=%u\n",
2135 bfreg_dyn_idx
, bfregi
->total_num_bfregs
);
2139 mutex_lock(&bfregi
->lock
);
2140 /* Fail if uar already allocated, first bfreg index of each
2141 * page holds its count.
2143 if (bfregi
->count
[bfreg_dyn_idx
]) {
2144 mlx5_ib_warn(dev
, "wrong offset, idx %lu is busy, bfregn=%u\n", idx
, bfreg_dyn_idx
);
2145 mutex_unlock(&bfregi
->lock
);
2149 bfregi
->count
[bfreg_dyn_idx
]++;
2150 mutex_unlock(&bfregi
->lock
);
2152 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &uar_index
);
2154 mlx5_ib_warn(dev
, "UAR alloc failed\n");
2158 uar_index
= bfregi
->sys_pages
[idx
];
2161 pfn
= uar_index2pfn(dev
, uar_index
);
2162 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
2164 err
= rdma_user_mmap_io(&context
->ibucontext
, vma
, pfn
, PAGE_SIZE
,
2168 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2169 err
, mmap_cmd2str(cmd
));
2174 bfregi
->sys_pages
[idx
] = uar_index
;
2181 mlx5_cmd_free_uar(dev
->mdev
, idx
);
2184 mlx5_ib_free_bfreg(dev
, bfregi
, bfreg_dyn_idx
);
2189 static int dm_mmap(struct ib_ucontext
*context
, struct vm_area_struct
*vma
)
2191 struct mlx5_ib_ucontext
*mctx
= to_mucontext(context
);
2192 struct mlx5_ib_dev
*dev
= to_mdev(context
->device
);
2193 u16 page_idx
= get_extended_index(vma
->vm_pgoff
);
2194 size_t map_size
= vma
->vm_end
- vma
->vm_start
;
2195 u32 npages
= map_size
>> PAGE_SHIFT
;
2198 if (find_next_zero_bit(mctx
->dm_pages
, page_idx
+ npages
, page_idx
) !=
2202 pfn
= ((dev
->mdev
->bar_addr
+
2203 MLX5_CAP64_DEV_MEM(dev
->mdev
, memic_bar_start_addr
)) >>
2206 return rdma_user_mmap_io(context
, vma
, pfn
, map_size
,
2207 pgprot_writecombine(vma
->vm_page_prot
));
2210 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
2212 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
2213 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
2214 unsigned long command
;
2217 command
= get_command(vma
->vm_pgoff
);
2219 case MLX5_IB_MMAP_WC_PAGE
:
2220 case MLX5_IB_MMAP_NC_PAGE
:
2221 case MLX5_IB_MMAP_REGULAR_PAGE
:
2222 case MLX5_IB_MMAP_ALLOC_WC
:
2223 return uar_mmap(dev
, command
, vma
, context
);
2225 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
2228 case MLX5_IB_MMAP_CORE_CLOCK
:
2229 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
2232 if (vma
->vm_flags
& VM_WRITE
)
2235 /* Don't expose to user-space information it shouldn't have */
2236 if (PAGE_SIZE
> 4096)
2239 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
2240 pfn
= (dev
->mdev
->iseg_base
+
2241 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
2243 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
2244 PAGE_SIZE
, vma
->vm_page_prot
))
2247 case MLX5_IB_MMAP_CLOCK_INFO
:
2248 return mlx5_ib_mmap_clock_info_page(dev
, vma
, context
);
2250 case MLX5_IB_MMAP_DEVICE_MEM
:
2251 return dm_mmap(ibcontext
, vma
);
2260 struct ib_dm
*mlx5_ib_alloc_dm(struct ib_device
*ibdev
,
2261 struct ib_ucontext
*context
,
2262 struct ib_dm_alloc_attr
*attr
,
2263 struct uverbs_attr_bundle
*attrs
)
2265 u64 act_size
= roundup(attr
->length
, MLX5_MEMIC_BASE_SIZE
);
2266 struct mlx5_memic
*memic
= &to_mdev(ibdev
)->memic
;
2267 phys_addr_t memic_addr
;
2268 struct mlx5_ib_dm
*dm
;
2273 dm
= kzalloc(sizeof(*dm
), GFP_KERNEL
);
2275 return ERR_PTR(-ENOMEM
);
2277 mlx5_ib_dbg(to_mdev(ibdev
), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2278 attr
->length
, act_size
, attr
->alignment
);
2280 err
= mlx5_cmd_alloc_memic(memic
, &memic_addr
,
2281 act_size
, attr
->alignment
);
2285 start_offset
= memic_addr
& ~PAGE_MASK
;
2286 page_idx
= (memic_addr
- memic
->dev
->bar_addr
-
2287 MLX5_CAP64_DEV_MEM(memic
->dev
, memic_bar_start_addr
)) >>
2290 err
= uverbs_copy_to(attrs
,
2291 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET
,
2292 &start_offset
, sizeof(start_offset
));
2296 err
= uverbs_copy_to(attrs
,
2297 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX
,
2298 &page_idx
, sizeof(page_idx
));
2302 bitmap_set(to_mucontext(context
)->dm_pages
, page_idx
,
2303 DIV_ROUND_UP(act_size
, PAGE_SIZE
));
2305 dm
->dev_addr
= memic_addr
;
2310 mlx5_cmd_dealloc_memic(memic
, memic_addr
,
2314 return ERR_PTR(err
);
2317 int mlx5_ib_dealloc_dm(struct ib_dm
*ibdm
, struct uverbs_attr_bundle
*attrs
)
2319 struct mlx5_memic
*memic
= &to_mdev(ibdm
->device
)->memic
;
2320 struct mlx5_ib_dm
*dm
= to_mdm(ibdm
);
2321 u64 act_size
= roundup(dm
->ibdm
.length
, MLX5_MEMIC_BASE_SIZE
);
2325 ret
= mlx5_cmd_dealloc_memic(memic
, dm
->dev_addr
, act_size
);
2329 page_idx
= (dm
->dev_addr
- memic
->dev
->bar_addr
-
2330 MLX5_CAP64_DEV_MEM(memic
->dev
, memic_bar_start_addr
)) >>
2332 bitmap_clear(rdma_udata_to_drv_context(
2333 &attrs
->driver_udata
,
2334 struct mlx5_ib_ucontext
,
2335 ibucontext
)->dm_pages
,
2337 DIV_ROUND_UP(act_size
, PAGE_SIZE
));
2344 static int mlx5_ib_alloc_pd(struct ib_pd
*ibpd
, struct ib_udata
*udata
)
2346 struct mlx5_ib_pd
*pd
= to_mpd(ibpd
);
2347 struct ib_device
*ibdev
= ibpd
->device
;
2348 struct mlx5_ib_alloc_pd_resp resp
;
2350 u32 out
[MLX5_ST_SZ_DW(alloc_pd_out
)] = {};
2351 u32 in
[MLX5_ST_SZ_DW(alloc_pd_in
)] = {};
2353 struct mlx5_ib_ucontext
*context
= rdma_udata_to_drv_context(
2354 udata
, struct mlx5_ib_ucontext
, ibucontext
);
2356 uid
= context
? context
->devx_uid
: 0;
2357 MLX5_SET(alloc_pd_in
, in
, opcode
, MLX5_CMD_OP_ALLOC_PD
);
2358 MLX5_SET(alloc_pd_in
, in
, uid
, uid
);
2359 err
= mlx5_cmd_exec(to_mdev(ibdev
)->mdev
, in
, sizeof(in
),
2364 pd
->pdn
= MLX5_GET(alloc_pd_out
, out
, pd
);
2368 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
2369 mlx5_cmd_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
, uid
);
2377 static void mlx5_ib_dealloc_pd(struct ib_pd
*pd
, struct ib_udata
*udata
)
2379 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
2380 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
2382 mlx5_cmd_dealloc_pd(mdev
->mdev
, mpd
->pdn
, mpd
->uid
);
2386 MATCH_CRITERIA_ENABLE_OUTER_BIT
,
2387 MATCH_CRITERIA_ENABLE_MISC_BIT
,
2388 MATCH_CRITERIA_ENABLE_INNER_BIT
,
2389 MATCH_CRITERIA_ENABLE_MISC2_BIT
2392 #define HEADER_IS_ZERO(match_criteria, headers) \
2393 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2394 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2396 static u8 get_match_criteria_enable(u32 *match_criteria)
2398 u8 match_criteria_enable
;
2400 match_criteria_enable
=
2401 (!HEADER_IS_ZERO(match_criteria
, outer_headers
)) <<
2402 MATCH_CRITERIA_ENABLE_OUTER_BIT
;
2403 match_criteria_enable
|=
2404 (!HEADER_IS_ZERO(match_criteria
, misc_parameters
)) <<
2405 MATCH_CRITERIA_ENABLE_MISC_BIT
;
2406 match_criteria_enable
|=
2407 (!HEADER_IS_ZERO(match_criteria
, inner_headers
)) <<
2408 MATCH_CRITERIA_ENABLE_INNER_BIT
;
2409 match_criteria_enable
|=
2410 (!HEADER_IS_ZERO(match_criteria
, misc_parameters_2
)) <<
2411 MATCH_CRITERIA_ENABLE_MISC2_BIT
;
2413 return match_criteria_enable
;
2416 static int set_proto(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
2425 entry_mask
= MLX5_GET(fte_match_set_lyr_2_4
, outer_c
,
2427 entry_val
= MLX5_GET(fte_match_set_lyr_2_4
, outer_v
,
2430 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_protocol
, mask
);
2431 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_protocol
, val
);
2434 /* Don't override existing ip protocol */
2435 if (mask
!= entry_mask
|| val
!= entry_val
)
2441 static void set_flow_label(void *misc_c
, void *misc_v
, u32 mask
, u32 val
,
2445 MLX5_SET(fte_match_set_misc
,
2446 misc_c
, inner_ipv6_flow_label
, mask
);
2447 MLX5_SET(fte_match_set_misc
,
2448 misc_v
, inner_ipv6_flow_label
, val
);
2450 MLX5_SET(fte_match_set_misc
,
2451 misc_c
, outer_ipv6_flow_label
, mask
);
2452 MLX5_SET(fte_match_set_misc
,
2453 misc_v
, outer_ipv6_flow_label
, val
);
2457 static void set_tos(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
2459 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_ecn
, mask
);
2460 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_ecn
, val
);
2461 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_dscp
, mask
>> 2);
2462 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_dscp
, val
>> 2);
2465 static int check_mpls_supp_fields(u32 field_support
, const __be32
*set_mask
)
2467 if (MLX5_GET(fte_match_mpls
, set_mask
, mpls_label
) &&
2468 !(field_support
& MLX5_FIELD_SUPPORT_MPLS_LABEL
))
2471 if (MLX5_GET(fte_match_mpls
, set_mask
, mpls_exp
) &&
2472 !(field_support
& MLX5_FIELD_SUPPORT_MPLS_EXP
))
2475 if (MLX5_GET(fte_match_mpls
, set_mask
, mpls_s_bos
) &&
2476 !(field_support
& MLX5_FIELD_SUPPORT_MPLS_S_BOS
))
2479 if (MLX5_GET(fte_match_mpls
, set_mask
, mpls_ttl
) &&
2480 !(field_support
& MLX5_FIELD_SUPPORT_MPLS_TTL
))
2486 #define LAST_ETH_FIELD vlan_tag
2487 #define LAST_IB_FIELD sl
2488 #define LAST_IPV4_FIELD tos
2489 #define LAST_IPV6_FIELD traffic_class
2490 #define LAST_TCP_UDP_FIELD src_port
2491 #define LAST_TUNNEL_FIELD tunnel_id
2492 #define LAST_FLOW_TAG_FIELD tag_id
2493 #define LAST_DROP_FIELD size
2494 #define LAST_COUNTERS_FIELD counters
2496 /* Field is the last supported field */
2497 #define FIELDS_NOT_SUPPORTED(filter, field)\
2498 memchr_inv((void *)&filter.field +\
2499 sizeof(filter.field), 0,\
2501 offsetof(typeof(filter), field) -\
2502 sizeof(filter.field))
2504 int parse_flow_flow_action(struct mlx5_ib_flow_action
*maction
,
2506 struct mlx5_flow_act
*action
)
2509 switch (maction
->ib_action
.type
) {
2510 case IB_FLOW_ACTION_ESP
:
2511 if (action
->action
& (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT
|
2512 MLX5_FLOW_CONTEXT_ACTION_DECRYPT
))
2514 /* Currently only AES_GCM keymat is supported by the driver */
2515 action
->esp_id
= (uintptr_t)maction
->esp_aes_gcm
.ctx
;
2516 action
->action
|= is_egress
?
2517 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT
:
2518 MLX5_FLOW_CONTEXT_ACTION_DECRYPT
;
2520 case IB_FLOW_ACTION_UNSPECIFIED
:
2521 if (maction
->flow_action_raw
.sub_type
==
2522 MLX5_IB_FLOW_ACTION_MODIFY_HEADER
) {
2523 if (action
->action
& MLX5_FLOW_CONTEXT_ACTION_MOD_HDR
)
2525 action
->action
|= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR
;
2526 action
->modify_id
= maction
->flow_action_raw
.action_id
;
2529 if (maction
->flow_action_raw
.sub_type
==
2530 MLX5_IB_FLOW_ACTION_DECAP
) {
2531 if (action
->action
& MLX5_FLOW_CONTEXT_ACTION_DECAP
)
2533 action
->action
|= MLX5_FLOW_CONTEXT_ACTION_DECAP
;
2536 if (maction
->flow_action_raw
.sub_type
==
2537 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT
) {
2538 if (action
->action
&
2539 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT
)
2542 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT
;
2543 action
->reformat_id
=
2544 maction
->flow_action_raw
.action_id
;
2553 static int parse_flow_attr(struct mlx5_core_dev
*mdev
, u32
*match_c
,
2554 u32
*match_v
, const union ib_flow_spec
*ib_spec
,
2555 const struct ib_flow_attr
*flow_attr
,
2556 struct mlx5_flow_act
*action
, u32 prev_type
)
2558 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2560 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2562 void *misc_params2_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2564 void *misc_params2_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2571 if (ib_spec
->type
& IB_FLOW_SPEC_INNER
) {
2572 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2574 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2576 match_ipv
= MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2577 ft_field_support
.inner_ip_version
);
2579 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
2581 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
2583 match_ipv
= MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2584 ft_field_support
.outer_ip_version
);
2587 switch (ib_spec
->type
& ~IB_FLOW_SPEC_INNER
) {
2588 case IB_FLOW_SPEC_ETH
:
2589 if (FIELDS_NOT_SUPPORTED(ib_spec
->eth
.mask
, LAST_ETH_FIELD
))
2592 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2594 ib_spec
->eth
.mask
.dst_mac
);
2595 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2597 ib_spec
->eth
.val
.dst_mac
);
2599 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2601 ib_spec
->eth
.mask
.src_mac
);
2602 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2604 ib_spec
->eth
.val
.src_mac
);
2606 if (ib_spec
->eth
.mask
.vlan_tag
) {
2607 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2609 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2612 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2613 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
2614 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2615 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
2617 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2619 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
2620 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2622 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
2624 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2626 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
2627 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2629 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
2631 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2632 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
2633 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2634 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
2636 case IB_FLOW_SPEC_IPV4
:
2637 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv4
.mask
, LAST_IPV4_FIELD
))
2641 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2643 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2644 ip_version
, MLX5_FS_IPV4_VERSION
);
2646 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2648 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2649 ethertype
, ETH_P_IP
);
2652 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2653 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
2654 &ib_spec
->ipv4
.mask
.src_ip
,
2655 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
2656 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2657 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
2658 &ib_spec
->ipv4
.val
.src_ip
,
2659 sizeof(ib_spec
->ipv4
.val
.src_ip
));
2660 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2661 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
2662 &ib_spec
->ipv4
.mask
.dst_ip
,
2663 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
2664 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2665 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
2666 &ib_spec
->ipv4
.val
.dst_ip
,
2667 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
2669 set_tos(headers_c
, headers_v
,
2670 ib_spec
->ipv4
.mask
.tos
, ib_spec
->ipv4
.val
.tos
);
2672 if (set_proto(headers_c
, headers_v
,
2673 ib_spec
->ipv4
.mask
.proto
,
2674 ib_spec
->ipv4
.val
.proto
))
2677 case IB_FLOW_SPEC_IPV6
:
2678 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv6
.mask
, LAST_IPV6_FIELD
))
2682 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2684 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2685 ip_version
, MLX5_FS_IPV6_VERSION
);
2687 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
2689 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
2690 ethertype
, ETH_P_IPV6
);
2693 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2694 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
2695 &ib_spec
->ipv6
.mask
.src_ip
,
2696 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
2697 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2698 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
2699 &ib_spec
->ipv6
.val
.src_ip
,
2700 sizeof(ib_spec
->ipv6
.val
.src_ip
));
2701 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
2702 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
2703 &ib_spec
->ipv6
.mask
.dst_ip
,
2704 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
2705 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
2706 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
2707 &ib_spec
->ipv6
.val
.dst_ip
,
2708 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
2710 set_tos(headers_c
, headers_v
,
2711 ib_spec
->ipv6
.mask
.traffic_class
,
2712 ib_spec
->ipv6
.val
.traffic_class
);
2714 if (set_proto(headers_c
, headers_v
,
2715 ib_spec
->ipv6
.mask
.next_hdr
,
2716 ib_spec
->ipv6
.val
.next_hdr
))
2719 set_flow_label(misc_params_c
, misc_params_v
,
2720 ntohl(ib_spec
->ipv6
.mask
.flow_label
),
2721 ntohl(ib_spec
->ipv6
.val
.flow_label
),
2722 ib_spec
->type
& IB_FLOW_SPEC_INNER
);
2724 case IB_FLOW_SPEC_ESP
:
2725 if (ib_spec
->esp
.mask
.seq
)
2728 MLX5_SET(fte_match_set_misc
, misc_params_c
, outer_esp_spi
,
2729 ntohl(ib_spec
->esp
.mask
.spi
));
2730 MLX5_SET(fte_match_set_misc
, misc_params_v
, outer_esp_spi
,
2731 ntohl(ib_spec
->esp
.val
.spi
));
2733 case IB_FLOW_SPEC_TCP
:
2734 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
2735 LAST_TCP_UDP_FIELD
))
2738 if (set_proto(headers_c
, headers_v
, 0xff, IPPROTO_TCP
))
2741 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_sport
,
2742 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
2743 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_sport
,
2744 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
2746 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_dport
,
2747 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
2748 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_dport
,
2749 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
2751 case IB_FLOW_SPEC_UDP
:
2752 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
2753 LAST_TCP_UDP_FIELD
))
2756 if (set_proto(headers_c
, headers_v
, 0xff, IPPROTO_UDP
))
2759 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_sport
,
2760 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
2761 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_sport
,
2762 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
2764 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_dport
,
2765 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
2766 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_dport
,
2767 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
2769 case IB_FLOW_SPEC_GRE
:
2770 if (ib_spec
->gre
.mask
.c_ks_res0_ver
)
2773 if (set_proto(headers_c
, headers_v
, 0xff, IPPROTO_GRE
))
2776 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
2778 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
2781 MLX5_SET(fte_match_set_misc
, misc_params_c
, gre_protocol
,
2782 ntohs(ib_spec
->gre
.mask
.protocol
));
2783 MLX5_SET(fte_match_set_misc
, misc_params_v
, gre_protocol
,
2784 ntohs(ib_spec
->gre
.val
.protocol
));
2786 memcpy(MLX5_ADDR_OF(fte_match_set_misc
, misc_params_c
,
2788 &ib_spec
->gre
.mask
.key
,
2789 sizeof(ib_spec
->gre
.mask
.key
));
2790 memcpy(MLX5_ADDR_OF(fte_match_set_misc
, misc_params_v
,
2792 &ib_spec
->gre
.val
.key
,
2793 sizeof(ib_spec
->gre
.val
.key
));
2795 case IB_FLOW_SPEC_MPLS
:
2796 switch (prev_type
) {
2797 case IB_FLOW_SPEC_UDP
:
2798 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2799 ft_field_support
.outer_first_mpls_over_udp
),
2800 &ib_spec
->mpls
.mask
.tag
))
2803 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_v
,
2804 outer_first_mpls_over_udp
),
2805 &ib_spec
->mpls
.val
.tag
,
2806 sizeof(ib_spec
->mpls
.val
.tag
));
2807 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_c
,
2808 outer_first_mpls_over_udp
),
2809 &ib_spec
->mpls
.mask
.tag
,
2810 sizeof(ib_spec
->mpls
.mask
.tag
));
2812 case IB_FLOW_SPEC_GRE
:
2813 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2814 ft_field_support
.outer_first_mpls_over_gre
),
2815 &ib_spec
->mpls
.mask
.tag
))
2818 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_v
,
2819 outer_first_mpls_over_gre
),
2820 &ib_spec
->mpls
.val
.tag
,
2821 sizeof(ib_spec
->mpls
.val
.tag
));
2822 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_c
,
2823 outer_first_mpls_over_gre
),
2824 &ib_spec
->mpls
.mask
.tag
,
2825 sizeof(ib_spec
->mpls
.mask
.tag
));
2828 if (ib_spec
->type
& IB_FLOW_SPEC_INNER
) {
2829 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2830 ft_field_support
.inner_first_mpls
),
2831 &ib_spec
->mpls
.mask
.tag
))
2834 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_v
,
2836 &ib_spec
->mpls
.val
.tag
,
2837 sizeof(ib_spec
->mpls
.val
.tag
));
2838 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_c
,
2840 &ib_spec
->mpls
.mask
.tag
,
2841 sizeof(ib_spec
->mpls
.mask
.tag
));
2843 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2844 ft_field_support
.outer_first_mpls
),
2845 &ib_spec
->mpls
.mask
.tag
))
2848 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_v
,
2850 &ib_spec
->mpls
.val
.tag
,
2851 sizeof(ib_spec
->mpls
.val
.tag
));
2852 memcpy(MLX5_ADDR_OF(fte_match_set_misc2
, misc_params2_c
,
2854 &ib_spec
->mpls
.mask
.tag
,
2855 sizeof(ib_spec
->mpls
.mask
.tag
));
2859 case IB_FLOW_SPEC_VXLAN_TUNNEL
:
2860 if (FIELDS_NOT_SUPPORTED(ib_spec
->tunnel
.mask
,
2864 MLX5_SET(fte_match_set_misc
, misc_params_c
, vxlan_vni
,
2865 ntohl(ib_spec
->tunnel
.mask
.tunnel_id
));
2866 MLX5_SET(fte_match_set_misc
, misc_params_v
, vxlan_vni
,
2867 ntohl(ib_spec
->tunnel
.val
.tunnel_id
));
2869 case IB_FLOW_SPEC_ACTION_TAG
:
2870 if (FIELDS_NOT_SUPPORTED(ib_spec
->flow_tag
,
2871 LAST_FLOW_TAG_FIELD
))
2873 if (ib_spec
->flow_tag
.tag_id
>= BIT(24))
2876 action
->flow_tag
= ib_spec
->flow_tag
.tag_id
;
2877 action
->flags
|= FLOW_ACT_HAS_TAG
;
2879 case IB_FLOW_SPEC_ACTION_DROP
:
2880 if (FIELDS_NOT_SUPPORTED(ib_spec
->drop
,
2883 action
->action
|= MLX5_FLOW_CONTEXT_ACTION_DROP
;
2885 case IB_FLOW_SPEC_ACTION_HANDLE
:
2886 ret
= parse_flow_flow_action(to_mflow_act(ib_spec
->action
.act
),
2887 flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_EGRESS
, action
);
2891 case IB_FLOW_SPEC_ACTION_COUNT
:
2892 if (FIELDS_NOT_SUPPORTED(ib_spec
->flow_count
,
2893 LAST_COUNTERS_FIELD
))
2896 /* for now support only one counters spec per flow */
2897 if (action
->action
& MLX5_FLOW_CONTEXT_ACTION_COUNT
)
2900 action
->counters
= ib_spec
->flow_count
.counters
;
2901 action
->action
|= MLX5_FLOW_CONTEXT_ACTION_COUNT
;
2910 /* If a flow could catch both multicast and unicast packets,
2911 * it won't fall into the multicast flow steering table and this rule
2912 * could steal other multicast packets.
2914 static bool flow_is_multicast_only(const struct ib_flow_attr
*ib_attr
)
2916 union ib_flow_spec
*flow_spec
;
2918 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
2919 ib_attr
->num_of_specs
< 1)
2922 flow_spec
= (union ib_flow_spec
*)(ib_attr
+ 1);
2923 if (flow_spec
->type
== IB_FLOW_SPEC_IPV4
) {
2924 struct ib_flow_spec_ipv4
*ipv4_spec
;
2926 ipv4_spec
= (struct ib_flow_spec_ipv4
*)flow_spec
;
2927 if (ipv4_is_multicast(ipv4_spec
->val
.dst_ip
))
2933 if (flow_spec
->type
== IB_FLOW_SPEC_ETH
) {
2934 struct ib_flow_spec_eth
*eth_spec
;
2936 eth_spec
= (struct ib_flow_spec_eth
*)flow_spec
;
2937 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
2938 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
2950 static enum valid_spec
2951 is_valid_esp_aes_gcm(struct mlx5_core_dev
*mdev
,
2952 const struct mlx5_flow_spec
*spec
,
2953 const struct mlx5_flow_act
*flow_act
,
2956 const u32
*match_c
= spec
->match_criteria
;
2958 (flow_act
->action
& (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT
|
2959 MLX5_FLOW_CONTEXT_ACTION_DECRYPT
));
2960 bool is_ipsec
= mlx5_fs_is_ipsec_flow(match_c
);
2961 bool is_drop
= flow_act
->action
& MLX5_FLOW_CONTEXT_ACTION_DROP
;
2964 * Currently only crypto is supported in egress, when regular egress
2965 * rules would be supported, always return VALID_SPEC_NA.
2968 return VALID_SPEC_NA
;
2970 return is_crypto
&& is_ipsec
&&
2971 (!egress
|| (!is_drop
&& !(flow_act
->flags
& FLOW_ACT_HAS_TAG
))) ?
2972 VALID_SPEC_VALID
: VALID_SPEC_INVALID
;
2975 static bool is_valid_spec(struct mlx5_core_dev
*mdev
,
2976 const struct mlx5_flow_spec
*spec
,
2977 const struct mlx5_flow_act
*flow_act
,
2980 /* We curretly only support ipsec egress flow */
2981 return is_valid_esp_aes_gcm(mdev
, spec
, flow_act
, egress
) != VALID_SPEC_INVALID
;
2984 static bool is_valid_ethertype(struct mlx5_core_dev
*mdev
,
2985 const struct ib_flow_attr
*flow_attr
,
2988 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
2989 int match_ipv
= check_inner
?
2990 MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2991 ft_field_support
.inner_ip_version
) :
2992 MLX5_CAP_FLOWTABLE_NIC_RX(mdev
,
2993 ft_field_support
.outer_ip_version
);
2994 int inner_bit
= check_inner
? IB_FLOW_SPEC_INNER
: 0;
2995 bool ipv4_spec_valid
, ipv6_spec_valid
;
2996 unsigned int ip_spec_type
= 0;
2997 bool has_ethertype
= false;
2998 unsigned int spec_index
;
2999 bool mask_valid
= true;
3003 /* Validate that ethertype is correct */
3004 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
3005 if ((ib_spec
->type
== (IB_FLOW_SPEC_ETH
| inner_bit
)) &&
3006 ib_spec
->eth
.mask
.ether_type
) {
3007 mask_valid
= (ib_spec
->eth
.mask
.ether_type
==
3009 has_ethertype
= true;
3010 eth_type
= ntohs(ib_spec
->eth
.val
.ether_type
);
3011 } else if ((ib_spec
->type
== (IB_FLOW_SPEC_IPV4
| inner_bit
)) ||
3012 (ib_spec
->type
== (IB_FLOW_SPEC_IPV6
| inner_bit
))) {
3013 ip_spec_type
= ib_spec
->type
;
3015 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
3018 type_valid
= (!has_ethertype
) || (!ip_spec_type
);
3019 if (!type_valid
&& mask_valid
) {
3020 ipv4_spec_valid
= (eth_type
== ETH_P_IP
) &&
3021 (ip_spec_type
== (IB_FLOW_SPEC_IPV4
| inner_bit
));
3022 ipv6_spec_valid
= (eth_type
== ETH_P_IPV6
) &&
3023 (ip_spec_type
== (IB_FLOW_SPEC_IPV6
| inner_bit
));
3025 type_valid
= (ipv4_spec_valid
) || (ipv6_spec_valid
) ||
3026 (((eth_type
== ETH_P_MPLS_UC
) ||
3027 (eth_type
== ETH_P_MPLS_MC
)) && match_ipv
);
3033 static bool is_valid_attr(struct mlx5_core_dev
*mdev
,
3034 const struct ib_flow_attr
*flow_attr
)
3036 return is_valid_ethertype(mdev
, flow_attr
, false) &&
3037 is_valid_ethertype(mdev
, flow_attr
, true);
3040 static void put_flow_table(struct mlx5_ib_dev
*dev
,
3041 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
3043 prio
->refcount
-= !!ft_added
;
3044 if (!prio
->refcount
) {
3045 mlx5_destroy_flow_table(prio
->flow_table
);
3046 prio
->flow_table
= NULL
;
3050 static void counters_clear_description(struct ib_counters
*counters
)
3052 struct mlx5_ib_mcounters
*mcounters
= to_mcounters(counters
);
3054 mutex_lock(&mcounters
->mcntrs_mutex
);
3055 kfree(mcounters
->counters_data
);
3056 mcounters
->counters_data
= NULL
;
3057 mcounters
->cntrs_max_index
= 0;
3058 mutex_unlock(&mcounters
->mcntrs_mutex
);
3061 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
3063 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
3064 struct mlx5_ib_flow_handler
,
3066 struct mlx5_ib_flow_handler
*iter
, *tmp
;
3067 struct mlx5_ib_dev
*dev
= handler
->dev
;
3069 mutex_lock(&dev
->flow_db
->lock
);
3071 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
3072 mlx5_del_flow_rules(iter
->rule
);
3073 put_flow_table(dev
, iter
->prio
, true);
3074 list_del(&iter
->list
);
3078 mlx5_del_flow_rules(handler
->rule
);
3079 put_flow_table(dev
, handler
->prio
, true);
3080 if (handler
->ibcounters
&&
3081 atomic_read(&handler
->ibcounters
->usecnt
) == 1)
3082 counters_clear_description(handler
->ibcounters
);
3084 mutex_unlock(&dev
->flow_db
->lock
);
3085 if (handler
->flow_matcher
)
3086 atomic_dec(&handler
->flow_matcher
->usecnt
);
3092 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
3100 enum flow_table_type
{
3105 #define MLX5_FS_MAX_TYPES 6
3106 #define MLX5_FS_MAX_ENTRIES BIT(16)
3108 static struct mlx5_ib_flow_prio
*_get_prio(struct mlx5_flow_namespace
*ns
,
3109 struct mlx5_ib_flow_prio
*prio
,
3111 int num_entries
, int num_groups
,
3114 struct mlx5_flow_table
*ft
;
3116 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
3121 return ERR_CAST(ft
);
3123 prio
->flow_table
= ft
;
3128 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
3129 struct ib_flow_attr
*flow_attr
,
3130 enum flow_table_type ft_type
)
3132 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
3133 struct mlx5_flow_namespace
*ns
= NULL
;
3134 struct mlx5_ib_flow_prio
*prio
;
3135 struct mlx5_flow_table
*ft
;
3142 max_table_size
= BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
3144 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
3145 enum mlx5_flow_namespace_type fn_type
;
3147 if (flow_is_multicast_only(flow_attr
) &&
3149 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
3151 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
3153 if (ft_type
== MLX5_IB_FT_RX
) {
3154 fn_type
= MLX5_FLOW_NAMESPACE_BYPASS
;
3155 prio
= &dev
->flow_db
->prios
[priority
];
3157 MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
, decap
))
3158 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP
;
3160 MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
3161 reformat_l3_tunnel_to_l2
))
3162 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT
;
3165 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev
->mdev
,
3167 fn_type
= MLX5_FLOW_NAMESPACE_EGRESS
;
3168 prio
= &dev
->flow_db
->egress_prios
[priority
];
3170 MLX5_CAP_FLOWTABLE_NIC_TX(dev
->mdev
, reformat
))
3171 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT
;
3173 ns
= mlx5_get_flow_namespace(dev
->mdev
, fn_type
);
3174 num_entries
= MLX5_FS_MAX_ENTRIES
;
3175 num_groups
= MLX5_FS_MAX_TYPES
;
3176 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
3177 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
3178 ns
= mlx5_get_flow_namespace(dev
->mdev
,
3179 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
3180 build_leftovers_ft_param(&priority
,
3183 prio
= &dev
->flow_db
->prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
3184 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
3185 if (!MLX5_CAP_FLOWTABLE(dev
->mdev
,
3186 allow_sniffer_and_nic_rx_shared_tir
))
3187 return ERR_PTR(-ENOTSUPP
);
3189 ns
= mlx5_get_flow_namespace(dev
->mdev
, ft_type
== MLX5_IB_FT_RX
?
3190 MLX5_FLOW_NAMESPACE_SNIFFER_RX
:
3191 MLX5_FLOW_NAMESPACE_SNIFFER_TX
);
3193 prio
= &dev
->flow_db
->sniffer
[ft_type
];
3200 return ERR_PTR(-ENOTSUPP
);
3202 if (num_entries
> max_table_size
)
3203 return ERR_PTR(-ENOMEM
);
3205 ft
= prio
->flow_table
;
3207 return _get_prio(ns
, prio
, priority
, num_entries
, num_groups
,
3213 static void set_underlay_qp(struct mlx5_ib_dev
*dev
,
3214 struct mlx5_flow_spec
*spec
,
3217 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
,
3218 spec
->match_criteria
,
3220 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, spec
->match_value
,
3224 MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
3225 ft_field_support
.bth_dst_qp
)) {
3226 MLX5_SET(fte_match_set_misc
,
3227 misc_params_v
, bth_dst_qp
, underlay_qpn
);
3228 MLX5_SET(fte_match_set_misc
,
3229 misc_params_c
, bth_dst_qp
, 0xffffff);
3233 static int read_flow_counters(struct ib_device
*ibdev
,
3234 struct mlx5_read_counters_attr
*read_attr
)
3236 struct mlx5_fc
*fc
= read_attr
->hw_cntrs_hndl
;
3237 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3239 return mlx5_fc_query(dev
->mdev
, fc
,
3240 &read_attr
->out
[IB_COUNTER_PACKETS
],
3241 &read_attr
->out
[IB_COUNTER_BYTES
]);
3244 /* flow counters currently expose two counters packets and bytes */
3245 #define FLOW_COUNTERS_NUM 2
3246 static int counters_set_description(struct ib_counters
*counters
,
3247 enum mlx5_ib_counters_type counters_type
,
3248 struct mlx5_ib_flow_counters_desc
*desc_data
,
3251 struct mlx5_ib_mcounters
*mcounters
= to_mcounters(counters
);
3252 u32 cntrs_max_index
= 0;
3255 if (counters_type
!= MLX5_IB_COUNTERS_FLOW
)
3258 /* init the fields for the object */
3259 mcounters
->type
= counters_type
;
3260 mcounters
->read_counters
= read_flow_counters
;
3261 mcounters
->counters_num
= FLOW_COUNTERS_NUM
;
3262 mcounters
->ncounters
= ncounters
;
3263 /* each counter entry have both description and index pair */
3264 for (i
= 0; i
< ncounters
; i
++) {
3265 if (desc_data
[i
].description
> IB_COUNTER_BYTES
)
3268 if (cntrs_max_index
<= desc_data
[i
].index
)
3269 cntrs_max_index
= desc_data
[i
].index
+ 1;
3272 mutex_lock(&mcounters
->mcntrs_mutex
);
3273 mcounters
->counters_data
= desc_data
;
3274 mcounters
->cntrs_max_index
= cntrs_max_index
;
3275 mutex_unlock(&mcounters
->mcntrs_mutex
);
3280 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3281 static int flow_counters_set_data(struct ib_counters
*ibcounters
,
3282 struct mlx5_ib_create_flow
*ucmd
)
3284 struct mlx5_ib_mcounters
*mcounters
= to_mcounters(ibcounters
);
3285 struct mlx5_ib_flow_counters_data
*cntrs_data
= NULL
;
3286 struct mlx5_ib_flow_counters_desc
*desc_data
= NULL
;
3287 bool hw_hndl
= false;
3290 if (ucmd
&& ucmd
->ncounters_data
!= 0) {
3291 cntrs_data
= ucmd
->data
;
3292 if (cntrs_data
->ncounters
> MAX_COUNTERS_NUM
)
3295 desc_data
= kcalloc(cntrs_data
->ncounters
,
3301 if (copy_from_user(desc_data
,
3302 u64_to_user_ptr(cntrs_data
->counters_data
),
3303 sizeof(*desc_data
) * cntrs_data
->ncounters
)) {
3309 if (!mcounters
->hw_cntrs_hndl
) {
3310 mcounters
->hw_cntrs_hndl
= mlx5_fc_create(
3311 to_mdev(ibcounters
->device
)->mdev
, false);
3312 if (IS_ERR(mcounters
->hw_cntrs_hndl
)) {
3313 ret
= PTR_ERR(mcounters
->hw_cntrs_hndl
);
3320 /* counters already bound to at least one flow */
3321 if (mcounters
->cntrs_max_index
) {
3326 ret
= counters_set_description(ibcounters
,
3327 MLX5_IB_COUNTERS_FLOW
,
3329 cntrs_data
->ncounters
);
3333 } else if (!mcounters
->cntrs_max_index
) {
3334 /* counters not bound yet, must have udata passed */
3343 mlx5_fc_destroy(to_mdev(ibcounters
->device
)->mdev
,
3344 mcounters
->hw_cntrs_hndl
);
3345 mcounters
->hw_cntrs_hndl
= NULL
;
3352 static struct mlx5_ib_flow_handler
*_create_flow_rule(struct mlx5_ib_dev
*dev
,
3353 struct mlx5_ib_flow_prio
*ft_prio
,
3354 const struct ib_flow_attr
*flow_attr
,
3355 struct mlx5_flow_destination
*dst
,
3357 struct mlx5_ib_create_flow
*ucmd
)
3359 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
3360 struct mlx5_ib_flow_handler
*handler
;
3361 struct mlx5_flow_act flow_act
= {.flow_tag
= MLX5_FS_DEFAULT_FLOW_TAG
};
3362 struct mlx5_flow_spec
*spec
;
3363 struct mlx5_flow_destination dest_arr
[2] = {};
3364 struct mlx5_flow_destination
*rule_dst
= dest_arr
;
3365 const void *ib_flow
= (const void *)flow_attr
+ sizeof(*flow_attr
);
3366 unsigned int spec_index
;
3370 bool is_egress
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_EGRESS
;
3372 if (!is_valid_attr(dev
->mdev
, flow_attr
))
3373 return ERR_PTR(-EINVAL
);
3375 if (dev
->rep
&& is_egress
)
3376 return ERR_PTR(-EINVAL
);
3378 spec
= kvzalloc(sizeof(*spec
), GFP_KERNEL
);
3379 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
3380 if (!handler
|| !spec
) {
3385 INIT_LIST_HEAD(&handler
->list
);
3387 memcpy(&dest_arr
[0], dst
, sizeof(*dst
));
3391 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
3392 err
= parse_flow_attr(dev
->mdev
, spec
->match_criteria
,
3394 ib_flow
, flow_attr
, &flow_act
,
3399 prev_type
= ((union ib_flow_spec
*)ib_flow
)->type
;
3400 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
3403 if (!flow_is_multicast_only(flow_attr
))
3404 set_underlay_qp(dev
, spec
, underlay_qpn
);
3409 misc
= MLX5_ADDR_OF(fte_match_param
, spec
->match_value
,
3411 MLX5_SET(fte_match_set_misc
, misc
, source_port
,
3413 misc
= MLX5_ADDR_OF(fte_match_param
, spec
->match_criteria
,
3415 MLX5_SET_TO_ONES(fte_match_set_misc
, misc
, source_port
);
3418 spec
->match_criteria_enable
= get_match_criteria_enable(spec
->match_criteria
);
3421 !is_valid_spec(dev
->mdev
, spec
, &flow_act
, is_egress
)) {
3426 if (flow_act
.action
& MLX5_FLOW_CONTEXT_ACTION_COUNT
) {
3427 struct mlx5_ib_mcounters
*mcounters
;
3429 err
= flow_counters_set_data(flow_act
.counters
, ucmd
);
3433 mcounters
= to_mcounters(flow_act
.counters
);
3434 handler
->ibcounters
= flow_act
.counters
;
3435 dest_arr
[dest_num
].type
=
3436 MLX5_FLOW_DESTINATION_TYPE_COUNTER
;
3437 dest_arr
[dest_num
].counter_id
=
3438 mlx5_fc_id(mcounters
->hw_cntrs_hndl
);
3442 if (flow_act
.action
& MLX5_FLOW_CONTEXT_ACTION_DROP
) {
3443 if (!(flow_act
.action
& MLX5_FLOW_CONTEXT_ACTION_COUNT
)) {
3449 flow_act
.action
|= MLX5_FLOW_CONTEXT_ACTION_ALLOW
;
3452 dest_num
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
3453 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
3456 if ((flow_act
.flags
& FLOW_ACT_HAS_TAG
) &&
3457 (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
3458 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
)) {
3459 mlx5_ib_warn(dev
, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3460 flow_act
.flow_tag
, flow_attr
->type
);
3464 handler
->rule
= mlx5_add_flow_rules(ft
, spec
,
3466 rule_dst
, dest_num
);
3468 if (IS_ERR(handler
->rule
)) {
3469 err
= PTR_ERR(handler
->rule
);
3473 ft_prio
->refcount
++;
3474 handler
->prio
= ft_prio
;
3477 ft_prio
->flow_table
= ft
;
3479 if (err
&& handler
) {
3480 if (handler
->ibcounters
&&
3481 atomic_read(&handler
->ibcounters
->usecnt
) == 1)
3482 counters_clear_description(handler
->ibcounters
);
3486 return err
? ERR_PTR(err
) : handler
;
3489 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
3490 struct mlx5_ib_flow_prio
*ft_prio
,
3491 const struct ib_flow_attr
*flow_attr
,
3492 struct mlx5_flow_destination
*dst
)
3494 return _create_flow_rule(dev
, ft_prio
, flow_attr
, dst
, 0, NULL
);
3497 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
3498 struct mlx5_ib_flow_prio
*ft_prio
,
3499 struct ib_flow_attr
*flow_attr
,
3500 struct mlx5_flow_destination
*dst
)
3502 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
3503 struct mlx5_ib_flow_handler
*handler
= NULL
;
3505 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
3506 if (!IS_ERR(handler
)) {
3507 handler_dst
= create_flow_rule(dev
, ft_prio
,
3509 if (IS_ERR(handler_dst
)) {
3510 mlx5_del_flow_rules(handler
->rule
);
3511 ft_prio
->refcount
--;
3513 handler
= handler_dst
;
3515 list_add(&handler_dst
->list
, &handler
->list
);
3526 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
3527 struct mlx5_ib_flow_prio
*ft_prio
,
3528 struct ib_flow_attr
*flow_attr
,
3529 struct mlx5_flow_destination
*dst
)
3531 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
3532 struct mlx5_ib_flow_handler
*handler
= NULL
;
3535 struct ib_flow_attr flow_attr
;
3536 struct ib_flow_spec_eth eth_flow
;
3537 } leftovers_specs
[] = {
3541 .size
= sizeof(leftovers_specs
[0])
3544 .type
= IB_FLOW_SPEC_ETH
,
3545 .size
= sizeof(struct ib_flow_spec_eth
),
3546 .mask
= {.dst_mac
= {0x1} },
3547 .val
= {.dst_mac
= {0x1} }
3553 .size
= sizeof(leftovers_specs
[0])
3556 .type
= IB_FLOW_SPEC_ETH
,
3557 .size
= sizeof(struct ib_flow_spec_eth
),
3558 .mask
= {.dst_mac
= {0x1} },
3559 .val
= {.dst_mac
= {} }
3564 handler
= create_flow_rule(dev
, ft_prio
,
3565 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
3567 if (!IS_ERR(handler
) &&
3568 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
3569 handler_ucast
= create_flow_rule(dev
, ft_prio
,
3570 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
3572 if (IS_ERR(handler_ucast
)) {
3573 mlx5_del_flow_rules(handler
->rule
);
3574 ft_prio
->refcount
--;
3576 handler
= handler_ucast
;
3578 list_add(&handler_ucast
->list
, &handler
->list
);
3585 static struct mlx5_ib_flow_handler
*create_sniffer_rule(struct mlx5_ib_dev
*dev
,
3586 struct mlx5_ib_flow_prio
*ft_rx
,
3587 struct mlx5_ib_flow_prio
*ft_tx
,
3588 struct mlx5_flow_destination
*dst
)
3590 struct mlx5_ib_flow_handler
*handler_rx
;
3591 struct mlx5_ib_flow_handler
*handler_tx
;
3593 static const struct ib_flow_attr flow_attr
= {
3595 .size
= sizeof(flow_attr
)
3598 handler_rx
= create_flow_rule(dev
, ft_rx
, &flow_attr
, dst
);
3599 if (IS_ERR(handler_rx
)) {
3600 err
= PTR_ERR(handler_rx
);
3604 handler_tx
= create_flow_rule(dev
, ft_tx
, &flow_attr
, dst
);
3605 if (IS_ERR(handler_tx
)) {
3606 err
= PTR_ERR(handler_tx
);
3610 list_add(&handler_tx
->list
, &handler_rx
->list
);
3615 mlx5_del_flow_rules(handler_rx
->rule
);
3619 return ERR_PTR(err
);
3622 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
3623 struct ib_flow_attr
*flow_attr
,
3625 struct ib_udata
*udata
)
3627 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
3628 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
3629 struct mlx5_ib_flow_handler
*handler
= NULL
;
3630 struct mlx5_flow_destination
*dst
= NULL
;
3631 struct mlx5_ib_flow_prio
*ft_prio_tx
= NULL
;
3632 struct mlx5_ib_flow_prio
*ft_prio
;
3633 bool is_egress
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_EGRESS
;
3634 struct mlx5_ib_create_flow
*ucmd
= NULL
, ucmd_hdr
;
3635 size_t min_ucmd_sz
, required_ucmd_sz
;
3639 if (udata
&& udata
->inlen
) {
3640 min_ucmd_sz
= offsetof(typeof(ucmd_hdr
), reserved
) +
3641 sizeof(ucmd_hdr
.reserved
);
3642 if (udata
->inlen
< min_ucmd_sz
)
3643 return ERR_PTR(-EOPNOTSUPP
);
3645 err
= ib_copy_from_udata(&ucmd_hdr
, udata
, min_ucmd_sz
);
3647 return ERR_PTR(err
);
3649 /* currently supports only one counters data */
3650 if (ucmd_hdr
.ncounters_data
> 1)
3651 return ERR_PTR(-EINVAL
);
3653 required_ucmd_sz
= min_ucmd_sz
+
3654 sizeof(struct mlx5_ib_flow_counters_data
) *
3655 ucmd_hdr
.ncounters_data
;
3656 if (udata
->inlen
> required_ucmd_sz
&&
3657 !ib_is_udata_cleared(udata
, required_ucmd_sz
,
3658 udata
->inlen
- required_ucmd_sz
))
3659 return ERR_PTR(-EOPNOTSUPP
);
3661 ucmd
= kzalloc(required_ucmd_sz
, GFP_KERNEL
);
3663 return ERR_PTR(-ENOMEM
);
3665 err
= ib_copy_from_udata(ucmd
, udata
, required_ucmd_sz
);
3670 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
) {
3675 if (domain
!= IB_FLOW_DOMAIN_USER
||
3676 flow_attr
->port
> dev
->num_ports
||
3677 (flow_attr
->flags
& ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP
|
3678 IB_FLOW_ATTR_FLAGS_EGRESS
))) {
3684 (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
3685 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
)) {
3690 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
3696 mutex_lock(&dev
->flow_db
->lock
);
3698 ft_prio
= get_flow_table(dev
, flow_attr
,
3699 is_egress
? MLX5_IB_FT_TX
: MLX5_IB_FT_RX
);
3700 if (IS_ERR(ft_prio
)) {
3701 err
= PTR_ERR(ft_prio
);
3704 if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
3705 ft_prio_tx
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_TX
);
3706 if (IS_ERR(ft_prio_tx
)) {
3707 err
= PTR_ERR(ft_prio_tx
);
3714 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_PORT
;
3716 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
3717 if (mqp
->flags
& MLX5_IB_QP_RSS
)
3718 dst
->tir_num
= mqp
->rss_qp
.tirn
;
3720 dst
->tir_num
= mqp
->raw_packet_qp
.rq
.tirn
;
3723 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
3724 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
3725 handler
= create_dont_trap_rule(dev
, ft_prio
,
3728 underlay_qpn
= (mqp
->flags
& MLX5_IB_QP_UNDERLAY
) ?
3729 mqp
->underlay_qpn
: 0;
3730 handler
= _create_flow_rule(dev
, ft_prio
, flow_attr
,
3731 dst
, underlay_qpn
, ucmd
);
3733 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
3734 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
3735 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
3737 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
3738 handler
= create_sniffer_rule(dev
, ft_prio
, ft_prio_tx
, dst
);
3744 if (IS_ERR(handler
)) {
3745 err
= PTR_ERR(handler
);
3750 mutex_unlock(&dev
->flow_db
->lock
);
3754 return &handler
->ibflow
;
3757 put_flow_table(dev
, ft_prio
, false);
3759 put_flow_table(dev
, ft_prio_tx
, false);
3761 mutex_unlock(&dev
->flow_db
->lock
);
3765 return ERR_PTR(err
);
3768 static struct mlx5_ib_flow_prio
*
3769 _get_flow_table(struct mlx5_ib_dev
*dev
,
3770 struct mlx5_ib_flow_matcher
*fs_matcher
,
3773 struct mlx5_flow_namespace
*ns
= NULL
;
3774 struct mlx5_ib_flow_prio
*prio
;
3779 if (fs_matcher
->ns_type
== MLX5_FLOW_NAMESPACE_BYPASS
) {
3780 max_table_size
= BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
3782 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
, decap
))
3783 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP
;
3784 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
3785 reformat_l3_tunnel_to_l2
))
3786 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT
;
3787 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3788 max_table_size
= BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev
->mdev
,
3790 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev
->mdev
, reformat
))
3791 flags
|= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT
;
3794 if (max_table_size
< MLX5_FS_MAX_ENTRIES
)
3795 return ERR_PTR(-ENOMEM
);
3798 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
3800 priority
= ib_prio_to_core_prio(fs_matcher
->priority
, false);
3802 ns
= mlx5_get_flow_namespace(dev
->mdev
, fs_matcher
->ns_type
);
3804 return ERR_PTR(-ENOTSUPP
);
3806 if (fs_matcher
->ns_type
== MLX5_FLOW_NAMESPACE_BYPASS
)
3807 prio
= &dev
->flow_db
->prios
[priority
];
3809 prio
= &dev
->flow_db
->egress_prios
[priority
];
3811 if (prio
->flow_table
)
3814 return _get_prio(ns
, prio
, priority
, MLX5_FS_MAX_ENTRIES
,
3815 MLX5_FS_MAX_TYPES
, flags
);
3818 static struct mlx5_ib_flow_handler
*
3819 _create_raw_flow_rule(struct mlx5_ib_dev
*dev
,
3820 struct mlx5_ib_flow_prio
*ft_prio
,
3821 struct mlx5_flow_destination
*dst
,
3822 struct mlx5_ib_flow_matcher
*fs_matcher
,
3823 struct mlx5_flow_act
*flow_act
,
3824 void *cmd_in
, int inlen
,
3827 struct mlx5_ib_flow_handler
*handler
;
3828 struct mlx5_flow_spec
*spec
;
3829 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
3832 spec
= kvzalloc(sizeof(*spec
), GFP_KERNEL
);
3833 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
3834 if (!handler
|| !spec
) {
3839 INIT_LIST_HEAD(&handler
->list
);
3841 memcpy(spec
->match_value
, cmd_in
, inlen
);
3842 memcpy(spec
->match_criteria
, fs_matcher
->matcher_mask
.match_params
,
3843 fs_matcher
->mask_len
);
3844 spec
->match_criteria_enable
= fs_matcher
->match_criteria_enable
;
3846 handler
->rule
= mlx5_add_flow_rules(ft
, spec
,
3847 flow_act
, dst
, dst_num
);
3849 if (IS_ERR(handler
->rule
)) {
3850 err
= PTR_ERR(handler
->rule
);
3854 ft_prio
->refcount
++;
3855 handler
->prio
= ft_prio
;
3857 ft_prio
->flow_table
= ft
;
3863 return err
? ERR_PTR(err
) : handler
;
3866 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher
*fs_matcher
,
3870 void *match_v_set_lyr_2_4
, *match_c_set_lyr_2_4
;
3871 void *dmac
, *dmac_mask
;
3872 void *ipv4
, *ipv4_mask
;
3874 if (!(fs_matcher
->match_criteria_enable
&
3875 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT
)))
3878 match_c
= fs_matcher
->matcher_mask
.match_params
;
3879 match_v_set_lyr_2_4
= MLX5_ADDR_OF(fte_match_param
, match_v
,
3881 match_c_set_lyr_2_4
= MLX5_ADDR_OF(fte_match_param
, match_c
,
3884 dmac
= MLX5_ADDR_OF(fte_match_set_lyr_2_4
, match_v_set_lyr_2_4
,
3886 dmac_mask
= MLX5_ADDR_OF(fte_match_set_lyr_2_4
, match_c_set_lyr_2_4
,
3889 if (is_multicast_ether_addr(dmac
) &&
3890 is_multicast_ether_addr(dmac_mask
))
3893 ipv4
= MLX5_ADDR_OF(fte_match_set_lyr_2_4
, match_v_set_lyr_2_4
,
3894 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
);
3896 ipv4_mask
= MLX5_ADDR_OF(fte_match_set_lyr_2_4
, match_c_set_lyr_2_4
,
3897 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
);
3899 if (ipv4_is_multicast(*(__be32
*)(ipv4
)) &&
3900 ipv4_is_multicast(*(__be32
*)(ipv4_mask
)))
3906 struct mlx5_ib_flow_handler
*
3907 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev
*dev
,
3908 struct mlx5_ib_flow_matcher
*fs_matcher
,
3909 struct mlx5_flow_act
*flow_act
,
3911 void *cmd_in
, int inlen
, int dest_id
,
3914 struct mlx5_flow_destination
*dst
;
3915 struct mlx5_ib_flow_prio
*ft_prio
;
3916 struct mlx5_ib_flow_handler
*handler
;
3921 if (fs_matcher
->flow_type
!= MLX5_IB_FLOW_TYPE_NORMAL
)
3922 return ERR_PTR(-EOPNOTSUPP
);
3924 if (fs_matcher
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
3925 return ERR_PTR(-ENOMEM
);
3927 dst
= kcalloc(2, sizeof(*dst
), GFP_KERNEL
);
3929 return ERR_PTR(-ENOMEM
);
3931 mcast
= raw_fs_is_multicast(fs_matcher
, cmd_in
);
3932 mutex_lock(&dev
->flow_db
->lock
);
3934 ft_prio
= _get_flow_table(dev
, fs_matcher
, mcast
);
3935 if (IS_ERR(ft_prio
)) {
3936 err
= PTR_ERR(ft_prio
);
3940 if (dest_type
== MLX5_FLOW_DESTINATION_TYPE_TIR
) {
3941 dst
[dst_num
].type
= dest_type
;
3942 dst
[dst_num
].tir_num
= dest_id
;
3943 flow_act
->action
|= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
;
3944 } else if (dest_type
== MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE
) {
3945 dst
[dst_num
].type
= MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM
;
3946 dst
[dst_num
].ft_num
= dest_id
;
3947 flow_act
->action
|= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
;
3949 dst
[dst_num
].type
= MLX5_FLOW_DESTINATION_TYPE_PORT
;
3950 flow_act
->action
|= MLX5_FLOW_CONTEXT_ACTION_ALLOW
;
3955 if (flow_act
->action
& MLX5_FLOW_CONTEXT_ACTION_COUNT
) {
3956 dst
[dst_num
].type
= MLX5_FLOW_DESTINATION_TYPE_COUNTER
;
3957 dst
[dst_num
].counter_id
= counter_id
;
3961 handler
= _create_raw_flow_rule(dev
, ft_prio
, dst
, fs_matcher
, flow_act
,
3962 cmd_in
, inlen
, dst_num
);
3964 if (IS_ERR(handler
)) {
3965 err
= PTR_ERR(handler
);
3969 mutex_unlock(&dev
->flow_db
->lock
);
3970 atomic_inc(&fs_matcher
->usecnt
);
3971 handler
->flow_matcher
= fs_matcher
;
3978 put_flow_table(dev
, ft_prio
, false);
3980 mutex_unlock(&dev
->flow_db
->lock
);
3983 return ERR_PTR(err
);
3986 static u32
mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags
)
3990 if (mlx5_flags
& MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
)
3991 flags
|= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA
;
3996 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3997 static struct ib_flow_action
*
3998 mlx5_ib_create_flow_action_esp(struct ib_device
*device
,
3999 const struct ib_flow_action_attrs_esp
*attr
,
4000 struct uverbs_attr_bundle
*attrs
)
4002 struct mlx5_ib_dev
*mdev
= to_mdev(device
);
4003 struct ib_uverbs_flow_action_esp_keymat_aes_gcm
*aes_gcm
;
4004 struct mlx5_accel_esp_xfrm_attrs accel_attrs
= {};
4005 struct mlx5_ib_flow_action
*action
;
4010 err
= uverbs_get_flags64(
4011 &action_flags
, attrs
, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS
,
4012 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED
<< 1) - 1));
4014 return ERR_PTR(err
);
4016 flags
= mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags
);
4018 /* We current only support a subset of the standard features. Only a
4019 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
4020 * (with overlap). Full offload mode isn't supported.
4022 if (!attr
->keymat
|| attr
->replay
|| attr
->encap
||
4023 attr
->spi
|| attr
->seq
|| attr
->tfc_pad
||
4024 attr
->hard_limit_pkts
||
4025 (attr
->flags
& ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
|
4026 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT
)))
4027 return ERR_PTR(-EOPNOTSUPP
);
4029 if (attr
->keymat
->protocol
!=
4030 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM
)
4031 return ERR_PTR(-EOPNOTSUPP
);
4033 aes_gcm
= &attr
->keymat
->keymat
.aes_gcm
;
4035 if (aes_gcm
->icv_len
!= 16 ||
4036 aes_gcm
->iv_algo
!= IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ
)
4037 return ERR_PTR(-EOPNOTSUPP
);
4039 action
= kmalloc(sizeof(*action
), GFP_KERNEL
);
4041 return ERR_PTR(-ENOMEM
);
4043 action
->esp_aes_gcm
.ib_flags
= attr
->flags
;
4044 memcpy(&accel_attrs
.keymat
.aes_gcm
.aes_key
, &aes_gcm
->aes_key
,
4045 sizeof(accel_attrs
.keymat
.aes_gcm
.aes_key
));
4046 accel_attrs
.keymat
.aes_gcm
.key_len
= aes_gcm
->key_len
* 8;
4047 memcpy(&accel_attrs
.keymat
.aes_gcm
.salt
, &aes_gcm
->salt
,
4048 sizeof(accel_attrs
.keymat
.aes_gcm
.salt
));
4049 memcpy(&accel_attrs
.keymat
.aes_gcm
.seq_iv
, &aes_gcm
->iv
,
4050 sizeof(accel_attrs
.keymat
.aes_gcm
.seq_iv
));
4051 accel_attrs
.keymat
.aes_gcm
.icv_len
= aes_gcm
->icv_len
* 8;
4052 accel_attrs
.keymat
.aes_gcm
.iv_algo
= MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ
;
4053 accel_attrs
.keymat_type
= MLX5_ACCEL_ESP_KEYMAT_AES_GCM
;
4055 accel_attrs
.esn
= attr
->esn
;
4056 if (attr
->flags
& IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
)
4057 accel_attrs
.flags
|= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED
;
4058 if (attr
->flags
& IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
)
4059 accel_attrs
.flags
|= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP
;
4061 if (attr
->flags
& IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT
)
4062 accel_attrs
.action
|= MLX5_ACCEL_ESP_ACTION_ENCRYPT
;
4064 action
->esp_aes_gcm
.ctx
=
4065 mlx5_accel_esp_create_xfrm(mdev
->mdev
, &accel_attrs
, flags
);
4066 if (IS_ERR(action
->esp_aes_gcm
.ctx
)) {
4067 err
= PTR_ERR(action
->esp_aes_gcm
.ctx
);
4071 action
->esp_aes_gcm
.ib_flags
= attr
->flags
;
4073 return &action
->ib_action
;
4077 return ERR_PTR(err
);
4081 mlx5_ib_modify_flow_action_esp(struct ib_flow_action
*action
,
4082 const struct ib_flow_action_attrs_esp
*attr
,
4083 struct uverbs_attr_bundle
*attrs
)
4085 struct mlx5_ib_flow_action
*maction
= to_mflow_act(action
);
4086 struct mlx5_accel_esp_xfrm_attrs accel_attrs
;
4089 if (attr
->keymat
|| attr
->replay
|| attr
->encap
||
4090 attr
->spi
|| attr
->seq
|| attr
->tfc_pad
||
4091 attr
->hard_limit_pkts
||
4092 (attr
->flags
& ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
|
4093 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS
|
4094 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
)))
4097 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
4100 if (!(maction
->esp_aes_gcm
.ib_flags
&
4101 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
) &&
4102 attr
->flags
& (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED
|
4103 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
))
4106 memcpy(&accel_attrs
, &maction
->esp_aes_gcm
.ctx
->attrs
,
4107 sizeof(accel_attrs
));
4109 accel_attrs
.esn
= attr
->esn
;
4110 if (attr
->flags
& IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
)
4111 accel_attrs
.flags
|= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP
;
4113 accel_attrs
.flags
&= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP
;
4115 err
= mlx5_accel_esp_modify_xfrm(maction
->esp_aes_gcm
.ctx
,
4120 maction
->esp_aes_gcm
.ib_flags
&=
4121 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
;
4122 maction
->esp_aes_gcm
.ib_flags
|=
4123 attr
->flags
& IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW
;
4128 static int mlx5_ib_destroy_flow_action(struct ib_flow_action
*action
)
4130 struct mlx5_ib_flow_action
*maction
= to_mflow_act(action
);
4132 switch (action
->type
) {
4133 case IB_FLOW_ACTION_ESP
:
4135 * We only support aes_gcm by now, so we implicitly know this is
4136 * the underline crypto.
4138 mlx5_accel_esp_destroy_xfrm(maction
->esp_aes_gcm
.ctx
);
4140 case IB_FLOW_ACTION_UNSPECIFIED
:
4141 mlx5_ib_destroy_flow_action_raw(maction
);
4152 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
4154 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4155 struct mlx5_ib_qp
*mqp
= to_mqp(ibqp
);
4160 to_mpd(ibqp
->pd
)->uid
: 0;
4162 if (mqp
->flags
& MLX5_IB_QP_UNDERLAY
) {
4163 mlx5_ib_dbg(dev
, "Attaching a multi cast group to underlay QP is not supported\n");
4167 err
= mlx5_cmd_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
, uid
);
4169 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
4170 ibqp
->qp_num
, gid
->raw
);
4175 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
4177 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4182 to_mpd(ibqp
->pd
)->uid
: 0;
4183 err
= mlx5_cmd_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
, uid
);
4185 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
4186 ibqp
->qp_num
, gid
->raw
);
4191 static int init_node_data(struct mlx5_ib_dev
*dev
)
4195 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
4199 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
4201 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
4204 static ssize_t
fw_pages_show(struct device
*device
,
4205 struct device_attribute
*attr
, char *buf
)
4207 struct mlx5_ib_dev
*dev
=
4208 rdma_device_to_drv_device(device
, struct mlx5_ib_dev
, ib_dev
);
4210 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
4212 static DEVICE_ATTR_RO(fw_pages
);
4214 static ssize_t
reg_pages_show(struct device
*device
,
4215 struct device_attribute
*attr
, char *buf
)
4217 struct mlx5_ib_dev
*dev
=
4218 rdma_device_to_drv_device(device
, struct mlx5_ib_dev
, ib_dev
);
4220 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
4222 static DEVICE_ATTR_RO(reg_pages
);
4224 static ssize_t
hca_type_show(struct device
*device
,
4225 struct device_attribute
*attr
, char *buf
)
4227 struct mlx5_ib_dev
*dev
=
4228 rdma_device_to_drv_device(device
, struct mlx5_ib_dev
, ib_dev
);
4230 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
4232 static DEVICE_ATTR_RO(hca_type
);
4234 static ssize_t
hw_rev_show(struct device
*device
,
4235 struct device_attribute
*attr
, char *buf
)
4237 struct mlx5_ib_dev
*dev
=
4238 rdma_device_to_drv_device(device
, struct mlx5_ib_dev
, ib_dev
);
4240 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
4242 static DEVICE_ATTR_RO(hw_rev
);
4244 static ssize_t
board_id_show(struct device
*device
,
4245 struct device_attribute
*attr
, char *buf
)
4247 struct mlx5_ib_dev
*dev
=
4248 rdma_device_to_drv_device(device
, struct mlx5_ib_dev
, ib_dev
);
4250 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
4251 dev
->mdev
->board_id
);
4253 static DEVICE_ATTR_RO(board_id
);
4255 static struct attribute
*mlx5_class_attributes
[] = {
4256 &dev_attr_hw_rev
.attr
,
4257 &dev_attr_hca_type
.attr
,
4258 &dev_attr_board_id
.attr
,
4259 &dev_attr_fw_pages
.attr
,
4260 &dev_attr_reg_pages
.attr
,
4264 static const struct attribute_group mlx5_attr_group
= {
4265 .attrs
= mlx5_class_attributes
,
4268 static void pkey_change_handler(struct work_struct
*work
)
4270 struct mlx5_ib_port_resources
*ports
=
4271 container_of(work
, struct mlx5_ib_port_resources
,
4274 mutex_lock(&ports
->devr
->mutex
);
4275 mlx5_ib_gsi_pkey_change(ports
->gsi
);
4276 mutex_unlock(&ports
->devr
->mutex
);
4279 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
4281 struct mlx5_ib_qp
*mqp
;
4282 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
4283 struct mlx5_core_cq
*mcq
;
4284 struct list_head cq_armed_list
;
4285 unsigned long flags_qp
;
4286 unsigned long flags_cq
;
4287 unsigned long flags
;
4289 INIT_LIST_HEAD(&cq_armed_list
);
4291 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4292 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
4293 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
4294 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
4295 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
4296 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
4297 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
4298 if (send_mcq
->mcq
.comp
&&
4299 mqp
->ibqp
.send_cq
->comp_handler
) {
4300 if (!send_mcq
->mcq
.reset_notify_added
) {
4301 send_mcq
->mcq
.reset_notify_added
= 1;
4302 list_add_tail(&send_mcq
->mcq
.reset_notify
,
4306 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
4308 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
4309 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
4310 /* no handling is needed for SRQ */
4311 if (!mqp
->ibqp
.srq
) {
4312 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
4313 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
4314 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
4315 if (recv_mcq
->mcq
.comp
&&
4316 mqp
->ibqp
.recv_cq
->comp_handler
) {
4317 if (!recv_mcq
->mcq
.reset_notify_added
) {
4318 recv_mcq
->mcq
.reset_notify_added
= 1;
4319 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
4323 spin_unlock_irqrestore(&recv_mcq
->lock
,
4327 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
4329 /*At that point all inflight post send were put to be executed as of we
4330 * lock/unlock above locks Now need to arm all involved CQs.
4332 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
4335 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
4338 static void delay_drop_handler(struct work_struct
*work
)
4341 struct mlx5_ib_delay_drop
*delay_drop
=
4342 container_of(work
, struct mlx5_ib_delay_drop
,
4345 atomic_inc(&delay_drop
->events_cnt
);
4347 mutex_lock(&delay_drop
->lock
);
4348 err
= mlx5_core_set_delay_drop(delay_drop
->dev
->mdev
,
4349 delay_drop
->timeout
);
4351 mlx5_ib_warn(delay_drop
->dev
, "Failed to set delay drop, timeout=%u\n",
4352 delay_drop
->timeout
);
4353 delay_drop
->activate
= false;
4355 mutex_unlock(&delay_drop
->lock
);
4358 static void handle_general_event(struct mlx5_ib_dev
*ibdev
, struct mlx5_eqe
*eqe
,
4359 struct ib_event
*ibev
)
4361 switch (eqe
->sub_type
) {
4362 case MLX5_GENERAL_SUBTYPE_DELAY_DROP_TIMEOUT
:
4363 schedule_work(&ibdev
->delay_drop
.delay_drop_work
);
4365 default: /* do nothing */
4370 static int handle_port_change(struct mlx5_ib_dev
*ibdev
, struct mlx5_eqe
*eqe
,
4371 struct ib_event
*ibev
)
4373 u8 port
= (eqe
->data
.port
.port
>> 4) & 0xf;
4375 ibev
->element
.port_num
= port
;
4377 switch (eqe
->sub_type
) {
4378 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE
:
4379 case MLX5_PORT_CHANGE_SUBTYPE_DOWN
:
4380 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED
:
4381 /* In RoCE, port up/down events are handled in
4382 * mlx5_netdev_event().
4384 if (mlx5_ib_port_link_layer(&ibdev
->ib_dev
, port
) ==
4385 IB_LINK_LAYER_ETHERNET
)
4388 ibev
->event
= (eqe
->sub_type
== MLX5_PORT_CHANGE_SUBTYPE_ACTIVE
) ?
4389 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
4392 case MLX5_PORT_CHANGE_SUBTYPE_LID
:
4393 ibev
->event
= IB_EVENT_LID_CHANGE
;
4396 case MLX5_PORT_CHANGE_SUBTYPE_PKEY
:
4397 ibev
->event
= IB_EVENT_PKEY_CHANGE
;
4398 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
4401 case MLX5_PORT_CHANGE_SUBTYPE_GUID
:
4402 ibev
->event
= IB_EVENT_GID_CHANGE
;
4405 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG
:
4406 ibev
->event
= IB_EVENT_CLIENT_REREGISTER
;
4415 static void mlx5_ib_handle_event(struct work_struct
*_work
)
4417 struct mlx5_ib_event_work
*work
=
4418 container_of(_work
, struct mlx5_ib_event_work
, work
);
4419 struct mlx5_ib_dev
*ibdev
;
4420 struct ib_event ibev
;
4423 if (work
->is_slave
) {
4424 ibdev
= mlx5_ib_get_ibdev_from_mpi(work
->mpi
);
4431 switch (work
->event
) {
4432 case MLX5_DEV_EVENT_SYS_ERROR
:
4433 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
4434 mlx5_ib_handle_internal_error(ibdev
);
4435 ibev
.element
.port_num
= (u8
)(unsigned long)work
->param
;
4438 case MLX5_EVENT_TYPE_PORT_CHANGE
:
4439 if (handle_port_change(ibdev
, work
->param
, &ibev
))
4442 case MLX5_EVENT_TYPE_GENERAL_EVENT
:
4443 handle_general_event(ibdev
, work
->param
, &ibev
);
4449 ibev
.device
= &ibdev
->ib_dev
;
4451 if (!rdma_is_port_valid(&ibdev
->ib_dev
, ibev
.element
.port_num
)) {
4452 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", ibev
.element
.port_num
);
4456 if (ibdev
->ib_active
)
4457 ib_dispatch_event(&ibev
);
4460 ibdev
->ib_active
= false;
4465 static int mlx5_ib_event(struct notifier_block
*nb
,
4466 unsigned long event
, void *param
)
4468 struct mlx5_ib_event_work
*work
;
4470 work
= kmalloc(sizeof(*work
), GFP_ATOMIC
);
4474 INIT_WORK(&work
->work
, mlx5_ib_handle_event
);
4475 work
->dev
= container_of(nb
, struct mlx5_ib_dev
, mdev_events
);
4476 work
->is_slave
= false;
4477 work
->param
= param
;
4478 work
->event
= event
;
4480 queue_work(mlx5_ib_event_wq
, &work
->work
);
4485 static int mlx5_ib_event_slave_port(struct notifier_block
*nb
,
4486 unsigned long event
, void *param
)
4488 struct mlx5_ib_event_work
*work
;
4490 work
= kmalloc(sizeof(*work
), GFP_ATOMIC
);
4494 INIT_WORK(&work
->work
, mlx5_ib_handle_event
);
4495 work
->mpi
= container_of(nb
, struct mlx5_ib_multiport_info
, mdev_events
);
4496 work
->is_slave
= true;
4497 work
->param
= param
;
4498 work
->event
= event
;
4499 queue_work(mlx5_ib_event_wq
, &work
->work
);
4504 static int set_has_smi_cap(struct mlx5_ib_dev
*dev
)
4506 struct mlx5_hca_vport_context vport_ctx
;
4510 for (port
= 1; port
<= dev
->num_ports
; port
++) {
4511 dev
->mdev
->port_caps
[port
- 1].has_smi
= false;
4512 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) ==
4513 MLX5_CAP_PORT_TYPE_IB
) {
4514 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
)) {
4515 err
= mlx5_query_hca_vport_context(dev
->mdev
, 0,
4519 mlx5_ib_err(dev
, "query_hca_vport_context for port=%d failed %d\n",
4523 dev
->mdev
->port_caps
[port
- 1].has_smi
=
4526 dev
->mdev
->port_caps
[port
- 1].has_smi
= true;
4533 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
4537 for (port
= 1; port
<= dev
->num_ports
; port
++)
4538 mlx5_query_ext_port_caps(dev
, port
);
4541 static int get_port_caps(struct mlx5_ib_dev
*dev
, u8 port
)
4543 struct ib_device_attr
*dprops
= NULL
;
4544 struct ib_port_attr
*pprops
= NULL
;
4546 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
4548 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
4552 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
4556 err
= set_has_smi_cap(dev
);
4560 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
4562 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
4566 memset(pprops
, 0, sizeof(*pprops
));
4567 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
4569 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
4574 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
4576 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
4577 pprops
->gid_tbl_len
;
4578 mlx5_ib_dbg(dev
, "port %d: pkey_table_len %d, gid_table_len %d\n",
4579 port
, dprops
->max_pkeys
, pprops
->gid_tbl_len
);
4588 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
4592 err
= mlx5_mr_cache_cleanup(dev
);
4594 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
4597 mlx5_ib_destroy_qp(dev
->umrc
.qp
, NULL
);
4599 ib_free_cq(dev
->umrc
.cq
);
4601 ib_dealloc_pd(dev
->umrc
.pd
);
4608 static int create_umr_res(struct mlx5_ib_dev
*dev
)
4610 struct ib_qp_init_attr
*init_attr
= NULL
;
4611 struct ib_qp_attr
*attr
= NULL
;
4617 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
4618 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
4619 if (!attr
|| !init_attr
) {
4624 pd
= ib_alloc_pd(&dev
->ib_dev
, 0);
4626 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
4631 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
4633 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
4638 init_attr
->send_cq
= cq
;
4639 init_attr
->recv_cq
= cq
;
4640 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
4641 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
4642 init_attr
->cap
.max_send_sge
= 1;
4643 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
4644 init_attr
->port_num
= 1;
4645 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
4647 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
4651 qp
->device
= &dev
->ib_dev
;
4654 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
4655 qp
->send_cq
= init_attr
->send_cq
;
4656 qp
->recv_cq
= init_attr
->recv_cq
;
4658 attr
->qp_state
= IB_QPS_INIT
;
4660 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
4663 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
4667 memset(attr
, 0, sizeof(*attr
));
4668 attr
->qp_state
= IB_QPS_RTR
;
4669 attr
->path_mtu
= IB_MTU_256
;
4671 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
4673 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
4677 memset(attr
, 0, sizeof(*attr
));
4678 attr
->qp_state
= IB_QPS_RTS
;
4679 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
4681 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
4689 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
4690 ret
= mlx5_mr_cache_init(dev
);
4692 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
4702 mlx5_ib_destroy_qp(qp
, NULL
);
4703 dev
->umrc
.qp
= NULL
;
4707 dev
->umrc
.cq
= NULL
;
4711 dev
->umrc
.pd
= NULL
;
4719 static u8
mlx5_get_umr_fence(u8 umr_fence_cap
)
4721 switch (umr_fence_cap
) {
4722 case MLX5_CAP_UMR_FENCE_NONE
:
4723 return MLX5_FENCE_MODE_NONE
;
4724 case MLX5_CAP_UMR_FENCE_SMALL
:
4725 return MLX5_FENCE_MODE_INITIATOR_SMALL
;
4727 return MLX5_FENCE_MODE_STRONG_ORDERING
;
4731 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
4733 struct ib_srq_init_attr attr
;
4734 struct mlx5_ib_dev
*dev
;
4735 struct ib_device
*ibdev
;
4736 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
4740 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
4741 ibdev
= &dev
->ib_dev
;
4743 mutex_init(&devr
->mutex
);
4745 devr
->p0
= rdma_zalloc_drv_obj(ibdev
, ib_pd
);
4749 devr
->p0
->device
= ibdev
;
4750 devr
->p0
->uobject
= NULL
;
4751 atomic_set(&devr
->p0
->usecnt
, 0);
4753 ret
= mlx5_ib_alloc_pd(devr
->p0
, NULL
);
4757 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
);
4758 if (IS_ERR(devr
->c0
)) {
4759 ret
= PTR_ERR(devr
->c0
);
4762 devr
->c0
->device
= &dev
->ib_dev
;
4763 devr
->c0
->uobject
= NULL
;
4764 devr
->c0
->comp_handler
= NULL
;
4765 devr
->c0
->event_handler
= NULL
;
4766 devr
->c0
->cq_context
= NULL
;
4767 atomic_set(&devr
->c0
->usecnt
, 0);
4769 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
);
4770 if (IS_ERR(devr
->x0
)) {
4771 ret
= PTR_ERR(devr
->x0
);
4774 devr
->x0
->device
= &dev
->ib_dev
;
4775 devr
->x0
->inode
= NULL
;
4776 atomic_set(&devr
->x0
->usecnt
, 0);
4777 mutex_init(&devr
->x0
->tgt_qp_mutex
);
4778 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
4780 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
);
4781 if (IS_ERR(devr
->x1
)) {
4782 ret
= PTR_ERR(devr
->x1
);
4785 devr
->x1
->device
= &dev
->ib_dev
;
4786 devr
->x1
->inode
= NULL
;
4787 atomic_set(&devr
->x1
->usecnt
, 0);
4788 mutex_init(&devr
->x1
->tgt_qp_mutex
);
4789 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
4791 memset(&attr
, 0, sizeof(attr
));
4792 attr
.attr
.max_sge
= 1;
4793 attr
.attr
.max_wr
= 1;
4794 attr
.srq_type
= IB_SRQT_XRC
;
4795 attr
.ext
.cq
= devr
->c0
;
4796 attr
.ext
.xrc
.xrcd
= devr
->x0
;
4798 devr
->s0
= rdma_zalloc_drv_obj(ibdev
, ib_srq
);
4804 devr
->s0
->device
= &dev
->ib_dev
;
4805 devr
->s0
->pd
= devr
->p0
;
4806 devr
->s0
->srq_type
= IB_SRQT_XRC
;
4807 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
4808 devr
->s0
->ext
.cq
= devr
->c0
;
4809 ret
= mlx5_ib_create_srq(devr
->s0
, &attr
, NULL
);
4813 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
4814 atomic_inc(&devr
->s0
->ext
.cq
->usecnt
);
4815 atomic_inc(&devr
->p0
->usecnt
);
4816 atomic_set(&devr
->s0
->usecnt
, 0);
4818 memset(&attr
, 0, sizeof(attr
));
4819 attr
.attr
.max_sge
= 1;
4820 attr
.attr
.max_wr
= 1;
4821 attr
.srq_type
= IB_SRQT_BASIC
;
4822 devr
->s1
= rdma_zalloc_drv_obj(ibdev
, ib_srq
);
4828 devr
->s1
->device
= &dev
->ib_dev
;
4829 devr
->s1
->pd
= devr
->p0
;
4830 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
4831 devr
->s1
->ext
.cq
= devr
->c0
;
4833 ret
= mlx5_ib_create_srq(devr
->s1
, &attr
, NULL
);
4837 atomic_inc(&devr
->p0
->usecnt
);
4838 atomic_set(&devr
->s1
->usecnt
, 0);
4840 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
4841 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
4842 pkey_change_handler
);
4843 devr
->ports
[port
].devr
= devr
;
4851 mlx5_ib_destroy_srq(devr
->s0
, NULL
);
4855 mlx5_ib_dealloc_xrcd(devr
->x1
, NULL
);
4857 mlx5_ib_dealloc_xrcd(devr
->x0
, NULL
);
4859 mlx5_ib_destroy_cq(devr
->c0
, NULL
);
4861 mlx5_ib_dealloc_pd(devr
->p0
, NULL
);
4867 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
4869 struct mlx5_ib_dev
*dev
=
4870 container_of(devr
, struct mlx5_ib_dev
, devr
);
4873 mlx5_ib_destroy_srq(devr
->s1
, NULL
);
4875 mlx5_ib_destroy_srq(devr
->s0
, NULL
);
4877 mlx5_ib_dealloc_xrcd(devr
->x0
, NULL
);
4878 mlx5_ib_dealloc_xrcd(devr
->x1
, NULL
);
4879 mlx5_ib_destroy_cq(devr
->c0
, NULL
);
4880 mlx5_ib_dealloc_pd(devr
->p0
, NULL
);
4883 /* Make sure no change P_Key work items are still executing */
4884 for (port
= 0; port
< dev
->num_ports
; ++port
)
4885 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
4888 static u32
get_core_cap_flags(struct ib_device
*ibdev
,
4889 struct mlx5_hca_vport_context
*rep
)
4891 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4892 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
4893 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
4894 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
4895 bool raw_support
= !mlx5_core_mp_enabled(dev
->mdev
);
4898 if (rep
->grh_required
)
4899 ret
|= RDMA_CORE_CAP_IB_GRH_REQUIRED
;
4901 if (ll
== IB_LINK_LAYER_INFINIBAND
)
4902 return ret
| RDMA_CORE_PORT_IBA_IB
;
4905 ret
|= RDMA_CORE_PORT_RAW_PACKET
;
4907 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
4910 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
4913 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
4914 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
4916 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
4917 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
4922 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
4923 struct ib_port_immutable
*immutable
)
4925 struct ib_port_attr attr
;
4926 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
4927 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, port_num
);
4928 struct mlx5_hca_vport_context rep
= {0};
4931 err
= ib_query_port(ibdev
, port_num
, &attr
);
4935 if (ll
== IB_LINK_LAYER_INFINIBAND
) {
4936 err
= mlx5_query_hca_vport_context(dev
->mdev
, 0, port_num
, 0,
4942 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
4943 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
4944 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
, &rep
);
4945 if ((ll
== IB_LINK_LAYER_INFINIBAND
) || MLX5_CAP_GEN(dev
->mdev
, roce
))
4946 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
4951 static int mlx5_port_rep_immutable(struct ib_device
*ibdev
, u8 port_num
,
4952 struct ib_port_immutable
*immutable
)
4954 struct ib_port_attr attr
;
4957 immutable
->core_cap_flags
= RDMA_CORE_PORT_RAW_PACKET
;
4959 err
= ib_query_port(ibdev
, port_num
, &attr
);
4963 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
4964 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
4965 immutable
->core_cap_flags
= RDMA_CORE_PORT_RAW_PACKET
;
4970 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
)
4972 struct mlx5_ib_dev
*dev
=
4973 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
4974 snprintf(str
, IB_FW_VERSION_NAME_MAX
, "%d.%d.%04d",
4975 fw_rev_maj(dev
->mdev
), fw_rev_min(dev
->mdev
),
4976 fw_rev_sub(dev
->mdev
));
4979 static int mlx5_eth_lag_init(struct mlx5_ib_dev
*dev
)
4981 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4982 struct mlx5_flow_namespace
*ns
= mlx5_get_flow_namespace(mdev
,
4983 MLX5_FLOW_NAMESPACE_LAG
);
4984 struct mlx5_flow_table
*ft
;
4987 if (!ns
|| !mlx5_lag_is_roce(mdev
))
4990 err
= mlx5_cmd_create_vport_lag(mdev
);
4994 ft
= mlx5_create_lag_demux_flow_table(ns
, 0, 0);
4997 goto err_destroy_vport_lag
;
5000 dev
->flow_db
->lag_demux_ft
= ft
;
5001 dev
->lag_active
= true;
5004 err_destroy_vport_lag
:
5005 mlx5_cmd_destroy_vport_lag(mdev
);
5009 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev
*dev
)
5011 struct mlx5_core_dev
*mdev
= dev
->mdev
;
5013 if (dev
->lag_active
) {
5014 dev
->lag_active
= false;
5016 mlx5_destroy_flow_table(dev
->flow_db
->lag_demux_ft
);
5017 dev
->flow_db
->lag_demux_ft
= NULL
;
5019 mlx5_cmd_destroy_vport_lag(mdev
);
5023 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev
*dev
, u8 port_num
)
5027 dev
->roce
[port_num
].nb
.notifier_call
= mlx5_netdev_event
;
5028 err
= register_netdevice_notifier(&dev
->roce
[port_num
].nb
);
5030 dev
->roce
[port_num
].nb
.notifier_call
= NULL
;
5037 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev
*dev
, u8 port_num
)
5039 if (dev
->roce
[port_num
].nb
.notifier_call
) {
5040 unregister_netdevice_notifier(&dev
->roce
[port_num
].nb
);
5041 dev
->roce
[port_num
].nb
.notifier_call
= NULL
;
5045 static int mlx5_enable_eth(struct mlx5_ib_dev
*dev
)
5049 if (MLX5_CAP_GEN(dev
->mdev
, roce
)) {
5050 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
5055 err
= mlx5_eth_lag_init(dev
);
5057 goto err_disable_roce
;
5062 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
5063 mlx5_nic_vport_disable_roce(dev
->mdev
);
5068 static void mlx5_disable_eth(struct mlx5_ib_dev
*dev
)
5070 mlx5_eth_lag_cleanup(dev
);
5071 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
5072 mlx5_nic_vport_disable_roce(dev
->mdev
);
5075 struct mlx5_ib_counter
{
5080 #define INIT_Q_COUNTER(_name) \
5081 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
5083 static const struct mlx5_ib_counter basic_q_cnts
[] = {
5084 INIT_Q_COUNTER(rx_write_requests
),
5085 INIT_Q_COUNTER(rx_read_requests
),
5086 INIT_Q_COUNTER(rx_atomic_requests
),
5087 INIT_Q_COUNTER(out_of_buffer
),
5090 static const struct mlx5_ib_counter out_of_seq_q_cnts
[] = {
5091 INIT_Q_COUNTER(out_of_sequence
),
5094 static const struct mlx5_ib_counter retrans_q_cnts
[] = {
5095 INIT_Q_COUNTER(duplicate_request
),
5096 INIT_Q_COUNTER(rnr_nak_retry_err
),
5097 INIT_Q_COUNTER(packet_seq_err
),
5098 INIT_Q_COUNTER(implied_nak_seq_err
),
5099 INIT_Q_COUNTER(local_ack_timeout_err
),
5102 #define INIT_CONG_COUNTER(_name) \
5103 { .name = #_name, .offset = \
5104 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
5106 static const struct mlx5_ib_counter cong_cnts
[] = {
5107 INIT_CONG_COUNTER(rp_cnp_ignored
),
5108 INIT_CONG_COUNTER(rp_cnp_handled
),
5109 INIT_CONG_COUNTER(np_ecn_marked_roce_packets
),
5110 INIT_CONG_COUNTER(np_cnp_sent
),
5113 static const struct mlx5_ib_counter extended_err_cnts
[] = {
5114 INIT_Q_COUNTER(resp_local_length_error
),
5115 INIT_Q_COUNTER(resp_cqe_error
),
5116 INIT_Q_COUNTER(req_cqe_error
),
5117 INIT_Q_COUNTER(req_remote_invalid_request
),
5118 INIT_Q_COUNTER(req_remote_access_errors
),
5119 INIT_Q_COUNTER(resp_remote_access_errors
),
5120 INIT_Q_COUNTER(resp_cqe_flush_error
),
5121 INIT_Q_COUNTER(req_cqe_flush_error
),
5124 #define INIT_EXT_PPCNT_COUNTER(_name) \
5125 { .name = #_name, .offset = \
5126 MLX5_BYTE_OFF(ppcnt_reg, \
5127 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
5129 static const struct mlx5_ib_counter ext_ppcnt_cnts
[] = {
5130 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated
),
5133 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev
*dev
)
5137 for (i
= 0; i
< dev
->num_ports
; i
++) {
5138 if (dev
->port
[i
].cnts
.set_id_valid
)
5139 mlx5_core_dealloc_q_counter(dev
->mdev
,
5140 dev
->port
[i
].cnts
.set_id
);
5141 kfree(dev
->port
[i
].cnts
.names
);
5142 kfree(dev
->port
[i
].cnts
.offsets
);
5146 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev
*dev
,
5147 struct mlx5_ib_counters
*cnts
)
5151 num_counters
= ARRAY_SIZE(basic_q_cnts
);
5153 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
))
5154 num_counters
+= ARRAY_SIZE(out_of_seq_q_cnts
);
5156 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
))
5157 num_counters
+= ARRAY_SIZE(retrans_q_cnts
);
5159 if (MLX5_CAP_GEN(dev
->mdev
, enhanced_error_q_counters
))
5160 num_counters
+= ARRAY_SIZE(extended_err_cnts
);
5162 cnts
->num_q_counters
= num_counters
;
5164 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
5165 cnts
->num_cong_counters
= ARRAY_SIZE(cong_cnts
);
5166 num_counters
+= ARRAY_SIZE(cong_cnts
);
5168 if (MLX5_CAP_PCAM_FEATURE(dev
->mdev
, rx_icrc_encapsulated_counter
)) {
5169 cnts
->num_ext_ppcnt_counters
= ARRAY_SIZE(ext_ppcnt_cnts
);
5170 num_counters
+= ARRAY_SIZE(ext_ppcnt_cnts
);
5172 cnts
->names
= kcalloc(num_counters
, sizeof(cnts
->names
), GFP_KERNEL
);
5176 cnts
->offsets
= kcalloc(num_counters
,
5177 sizeof(cnts
->offsets
), GFP_KERNEL
);
5189 static void mlx5_ib_fill_counters(struct mlx5_ib_dev
*dev
,
5196 for (i
= 0; i
< ARRAY_SIZE(basic_q_cnts
); i
++, j
++) {
5197 names
[j
] = basic_q_cnts
[i
].name
;
5198 offsets
[j
] = basic_q_cnts
[i
].offset
;
5201 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
)) {
5202 for (i
= 0; i
< ARRAY_SIZE(out_of_seq_q_cnts
); i
++, j
++) {
5203 names
[j
] = out_of_seq_q_cnts
[i
].name
;
5204 offsets
[j
] = out_of_seq_q_cnts
[i
].offset
;
5208 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
5209 for (i
= 0; i
< ARRAY_SIZE(retrans_q_cnts
); i
++, j
++) {
5210 names
[j
] = retrans_q_cnts
[i
].name
;
5211 offsets
[j
] = retrans_q_cnts
[i
].offset
;
5215 if (MLX5_CAP_GEN(dev
->mdev
, enhanced_error_q_counters
)) {
5216 for (i
= 0; i
< ARRAY_SIZE(extended_err_cnts
); i
++, j
++) {
5217 names
[j
] = extended_err_cnts
[i
].name
;
5218 offsets
[j
] = extended_err_cnts
[i
].offset
;
5222 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
5223 for (i
= 0; i
< ARRAY_SIZE(cong_cnts
); i
++, j
++) {
5224 names
[j
] = cong_cnts
[i
].name
;
5225 offsets
[j
] = cong_cnts
[i
].offset
;
5229 if (MLX5_CAP_PCAM_FEATURE(dev
->mdev
, rx_icrc_encapsulated_counter
)) {
5230 for (i
= 0; i
< ARRAY_SIZE(ext_ppcnt_cnts
); i
++, j
++) {
5231 names
[j
] = ext_ppcnt_cnts
[i
].name
;
5232 offsets
[j
] = ext_ppcnt_cnts
[i
].offset
;
5237 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev
*dev
)
5243 is_shared
= MLX5_CAP_GEN(dev
->mdev
, log_max_uctx
) != 0;
5245 for (i
= 0; i
< dev
->num_ports
; i
++) {
5246 err
= __mlx5_ib_alloc_counters(dev
, &dev
->port
[i
].cnts
);
5250 mlx5_ib_fill_counters(dev
, dev
->port
[i
].cnts
.names
,
5251 dev
->port
[i
].cnts
.offsets
);
5253 err
= mlx5_cmd_alloc_q_counter(dev
->mdev
,
5254 &dev
->port
[i
].cnts
.set_id
,
5256 MLX5_SHARED_RESOURCE_UID
: 0);
5259 "couldn't allocate queue counter for port %d, err %d\n",
5263 dev
->port
[i
].cnts
.set_id_valid
= true;
5269 mlx5_ib_dealloc_counters(dev
);
5273 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
5276 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
5277 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
5279 /* We support only per port stats */
5283 return rdma_alloc_hw_stats_struct(port
->cnts
.names
,
5284 port
->cnts
.num_q_counters
+
5285 port
->cnts
.num_cong_counters
+
5286 port
->cnts
.num_ext_ppcnt_counters
,
5287 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
5290 static int mlx5_ib_query_q_counters(struct mlx5_core_dev
*mdev
,
5291 struct mlx5_ib_port
*port
,
5292 struct rdma_hw_stats
*stats
)
5294 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
5299 out
= kvzalloc(outlen
, GFP_KERNEL
);
5303 ret
= mlx5_core_query_q_counter(mdev
,
5304 port
->cnts
.set_id
, 0,
5309 for (i
= 0; i
< port
->cnts
.num_q_counters
; i
++) {
5310 val
= *(__be32
*)(out
+ port
->cnts
.offsets
[i
]);
5311 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
5319 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev
*dev
,
5320 struct mlx5_ib_port
*port
,
5321 struct rdma_hw_stats
*stats
)
5323 int offset
= port
->cnts
.num_q_counters
+ port
->cnts
.num_cong_counters
;
5324 int sz
= MLX5_ST_SZ_BYTES(ppcnt_reg
);
5328 out
= kvzalloc(sz
, GFP_KERNEL
);
5332 ret
= mlx5_cmd_query_ext_ppcnt_counters(dev
->mdev
, out
);
5336 for (i
= 0; i
< port
->cnts
.num_ext_ppcnt_counters
; i
++) {
5337 stats
->value
[i
+ offset
] =
5338 be64_to_cpup((__be64
*)(out
+
5339 port
->cnts
.offsets
[i
+ offset
]));
5347 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
5348 struct rdma_hw_stats
*stats
,
5349 u8 port_num
, int index
)
5351 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
5352 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
5353 struct mlx5_core_dev
*mdev
;
5354 int ret
, num_counters
;
5360 num_counters
= port
->cnts
.num_q_counters
+
5361 port
->cnts
.num_cong_counters
+
5362 port
->cnts
.num_ext_ppcnt_counters
;
5364 /* q_counters are per IB device, query the master mdev */
5365 ret
= mlx5_ib_query_q_counters(dev
->mdev
, port
, stats
);
5369 if (MLX5_CAP_PCAM_FEATURE(dev
->mdev
, rx_icrc_encapsulated_counter
)) {
5370 ret
= mlx5_ib_query_ext_ppcnt_counters(dev
, port
, stats
);
5375 if (MLX5_CAP_GEN(dev
->mdev
, cc_query_allowed
)) {
5376 mdev
= mlx5_ib_get_native_port_mdev(dev
, port_num
,
5379 /* If port is not affiliated yet, its in down state
5380 * which doesn't have any counters yet, so it would be
5381 * zero. So no need to read from the HCA.
5385 ret
= mlx5_lag_query_cong_counters(dev
->mdev
,
5387 port
->cnts
.num_q_counters
,
5388 port
->cnts
.num_cong_counters
,
5389 port
->cnts
.offsets
+
5390 port
->cnts
.num_q_counters
);
5392 mlx5_ib_put_native_port_mdev(dev
, port_num
);
5398 return num_counters
;
5401 static int mlx5_ib_rn_get_params(struct ib_device
*device
, u8 port_num
,
5402 enum rdma_netdev_t type
,
5403 struct rdma_netdev_alloc_params
*params
)
5405 if (type
!= RDMA_NETDEV_IPOIB
)
5408 return mlx5_rdma_rn_get_params(to_mdev(device
)->mdev
, device
, params
);
5411 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev
*dev
)
5413 if (!dev
->delay_drop
.dbg
)
5415 debugfs_remove_recursive(dev
->delay_drop
.dbg
->dir_debugfs
);
5416 kfree(dev
->delay_drop
.dbg
);
5417 dev
->delay_drop
.dbg
= NULL
;
5420 static void cancel_delay_drop(struct mlx5_ib_dev
*dev
)
5422 if (!(dev
->ib_dev
.attrs
.raw_packet_caps
& IB_RAW_PACKET_CAP_DELAY_DROP
))
5425 cancel_work_sync(&dev
->delay_drop
.delay_drop_work
);
5426 delay_drop_debugfs_cleanup(dev
);
5429 static ssize_t
delay_drop_timeout_read(struct file
*filp
, char __user
*buf
,
5430 size_t count
, loff_t
*pos
)
5432 struct mlx5_ib_delay_drop
*delay_drop
= filp
->private_data
;
5436 len
= snprintf(lbuf
, sizeof(lbuf
), "%u\n", delay_drop
->timeout
);
5437 return simple_read_from_buffer(buf
, count
, pos
, lbuf
, len
);
5440 static ssize_t
delay_drop_timeout_write(struct file
*filp
, const char __user
*buf
,
5441 size_t count
, loff_t
*pos
)
5443 struct mlx5_ib_delay_drop
*delay_drop
= filp
->private_data
;
5447 if (kstrtouint_from_user(buf
, count
, 0, &var
))
5450 timeout
= min_t(u32
, roundup(var
, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS
*
5453 mlx5_ib_dbg(delay_drop
->dev
, "Round delay drop timeout to %u usec\n",
5456 delay_drop
->timeout
= timeout
;
5461 static const struct file_operations fops_delay_drop_timeout
= {
5462 .owner
= THIS_MODULE
,
5463 .open
= simple_open
,
5464 .write
= delay_drop_timeout_write
,
5465 .read
= delay_drop_timeout_read
,
5468 static int delay_drop_debugfs_init(struct mlx5_ib_dev
*dev
)
5470 struct mlx5_ib_dbg_delay_drop
*dbg
;
5472 if (!mlx5_debugfs_root
)
5475 dbg
= kzalloc(sizeof(*dbg
), GFP_KERNEL
);
5479 dev
->delay_drop
.dbg
= dbg
;
5482 debugfs_create_dir("delay_drop",
5483 dev
->mdev
->priv
.dbg_root
);
5484 if (!dbg
->dir_debugfs
)
5487 dbg
->events_cnt_debugfs
=
5488 debugfs_create_atomic_t("num_timeout_events", 0400,
5490 &dev
->delay_drop
.events_cnt
);
5491 if (!dbg
->events_cnt_debugfs
)
5494 dbg
->rqs_cnt_debugfs
=
5495 debugfs_create_atomic_t("num_rqs", 0400,
5497 &dev
->delay_drop
.rqs_cnt
);
5498 if (!dbg
->rqs_cnt_debugfs
)
5501 dbg
->timeout_debugfs
=
5502 debugfs_create_file("timeout", 0600,
5505 &fops_delay_drop_timeout
);
5506 if (!dbg
->timeout_debugfs
)
5512 delay_drop_debugfs_cleanup(dev
);
5516 static void init_delay_drop(struct mlx5_ib_dev
*dev
)
5518 if (!(dev
->ib_dev
.attrs
.raw_packet_caps
& IB_RAW_PACKET_CAP_DELAY_DROP
))
5521 mutex_init(&dev
->delay_drop
.lock
);
5522 dev
->delay_drop
.dev
= dev
;
5523 dev
->delay_drop
.activate
= false;
5524 dev
->delay_drop
.timeout
= MLX5_MAX_DELAY_DROP_TIMEOUT_MS
* 1000;
5525 INIT_WORK(&dev
->delay_drop
.delay_drop_work
, delay_drop_handler
);
5526 atomic_set(&dev
->delay_drop
.rqs_cnt
, 0);
5527 atomic_set(&dev
->delay_drop
.events_cnt
, 0);
5529 if (delay_drop_debugfs_init(dev
))
5530 mlx5_ib_warn(dev
, "Failed to init delay drop debugfs\n");
5533 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5534 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev
*ibdev
,
5535 struct mlx5_ib_multiport_info
*mpi
)
5537 u8 port_num
= mlx5_core_native_port_num(mpi
->mdev
) - 1;
5538 struct mlx5_ib_port
*port
= &ibdev
->port
[port_num
];
5543 mlx5_ib_cleanup_cong_debugfs(ibdev
, port_num
);
5545 spin_lock(&port
->mp
.mpi_lock
);
5547 spin_unlock(&port
->mp
.mpi_lock
);
5551 if (mpi
->mdev_events
.notifier_call
)
5552 mlx5_notifier_unregister(mpi
->mdev
, &mpi
->mdev_events
);
5553 mpi
->mdev_events
.notifier_call
= NULL
;
5557 spin_unlock(&port
->mp
.mpi_lock
);
5558 mlx5_remove_netdev_notifier(ibdev
, port_num
);
5559 spin_lock(&port
->mp
.mpi_lock
);
5561 comps
= mpi
->mdev_refcnt
;
5563 mpi
->unaffiliate
= true;
5564 init_completion(&mpi
->unref_comp
);
5565 spin_unlock(&port
->mp
.mpi_lock
);
5567 for (i
= 0; i
< comps
; i
++)
5568 wait_for_completion(&mpi
->unref_comp
);
5570 spin_lock(&port
->mp
.mpi_lock
);
5571 mpi
->unaffiliate
= false;
5574 port
->mp
.mpi
= NULL
;
5576 list_add_tail(&mpi
->list
, &mlx5_ib_unaffiliated_port_list
);
5578 spin_unlock(&port
->mp
.mpi_lock
);
5580 err
= mlx5_nic_vport_unaffiliate_multiport(mpi
->mdev
);
5582 mlx5_ib_dbg(ibdev
, "unaffiliated port %d\n", port_num
+ 1);
5583 /* Log an error, still needed to cleanup the pointers and add
5584 * it back to the list.
5587 mlx5_ib_err(ibdev
, "Failed to unaffiliate port %u\n",
5590 ibdev
->roce
[port_num
].last_port_state
= IB_PORT_DOWN
;
5593 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5594 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev
*ibdev
,
5595 struct mlx5_ib_multiport_info
*mpi
)
5597 u8 port_num
= mlx5_core_native_port_num(mpi
->mdev
) - 1;
5600 spin_lock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
5601 if (ibdev
->port
[port_num
].mp
.mpi
) {
5602 mlx5_ib_dbg(ibdev
, "port %d already affiliated.\n",
5604 spin_unlock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
5608 ibdev
->port
[port_num
].mp
.mpi
= mpi
;
5610 mpi
->mdev_events
.notifier_call
= NULL
;
5611 spin_unlock(&ibdev
->port
[port_num
].mp
.mpi_lock
);
5613 err
= mlx5_nic_vport_affiliate_multiport(ibdev
->mdev
, mpi
->mdev
);
5617 err
= get_port_caps(ibdev
, mlx5_core_native_port_num(mpi
->mdev
));
5621 err
= mlx5_add_netdev_notifier(ibdev
, port_num
);
5623 mlx5_ib_err(ibdev
, "failed adding netdev notifier for port %u\n",
5628 mpi
->mdev_events
.notifier_call
= mlx5_ib_event_slave_port
;
5629 mlx5_notifier_register(mpi
->mdev
, &mpi
->mdev_events
);
5631 mlx5_ib_init_cong_debugfs(ibdev
, port_num
);
5636 mlx5_ib_unbind_slave_port(ibdev
, mpi
);
5640 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev
*dev
)
5642 int port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
5643 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
,
5645 struct mlx5_ib_multiport_info
*mpi
;
5649 if (!mlx5_core_is_mp_master(dev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
5652 err
= mlx5_query_nic_vport_system_image_guid(dev
->mdev
,
5653 &dev
->sys_image_guid
);
5657 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
5661 mutex_lock(&mlx5_ib_multiport_mutex
);
5662 for (i
= 0; i
< dev
->num_ports
; i
++) {
5665 /* build a stub multiport info struct for the native port. */
5666 if (i
== port_num
) {
5667 mpi
= kzalloc(sizeof(*mpi
), GFP_KERNEL
);
5669 mutex_unlock(&mlx5_ib_multiport_mutex
);
5670 mlx5_nic_vport_disable_roce(dev
->mdev
);
5674 mpi
->is_master
= true;
5675 mpi
->mdev
= dev
->mdev
;
5676 mpi
->sys_image_guid
= dev
->sys_image_guid
;
5677 dev
->port
[i
].mp
.mpi
= mpi
;
5683 list_for_each_entry(mpi
, &mlx5_ib_unaffiliated_port_list
,
5685 if (dev
->sys_image_guid
== mpi
->sys_image_guid
&&
5686 (mlx5_core_native_port_num(mpi
->mdev
) - 1) == i
) {
5687 bound
= mlx5_ib_bind_slave_port(dev
, mpi
);
5691 dev_dbg(&mpi
->mdev
->pdev
->dev
, "removing port from unaffiliated list.\n");
5692 mlx5_ib_dbg(dev
, "port %d bound\n", i
+ 1);
5693 list_del(&mpi
->list
);
5698 get_port_caps(dev
, i
+ 1);
5699 mlx5_ib_dbg(dev
, "no free port found for port %d\n",
5704 list_add_tail(&dev
->ib_dev_list
, &mlx5_ib_dev_list
);
5705 mutex_unlock(&mlx5_ib_multiport_mutex
);
5709 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev
*dev
)
5711 int port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
5712 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
,
5716 if (!mlx5_core_is_mp_master(dev
->mdev
) || ll
!= IB_LINK_LAYER_ETHERNET
)
5719 mutex_lock(&mlx5_ib_multiport_mutex
);
5720 for (i
= 0; i
< dev
->num_ports
; i
++) {
5721 if (dev
->port
[i
].mp
.mpi
) {
5722 /* Destroy the native port stub */
5723 if (i
== port_num
) {
5724 kfree(dev
->port
[i
].mp
.mpi
);
5725 dev
->port
[i
].mp
.mpi
= NULL
;
5727 mlx5_ib_dbg(dev
, "unbinding port_num: %d\n", i
+ 1);
5728 mlx5_ib_unbind_slave_port(dev
, dev
->port
[i
].mp
.mpi
);
5733 mlx5_ib_dbg(dev
, "removing from devlist\n");
5734 list_del(&dev
->ib_dev_list
);
5735 mutex_unlock(&mlx5_ib_multiport_mutex
);
5737 mlx5_nic_vport_disable_roce(dev
->mdev
);
5740 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5743 UVERBS_METHOD_DM_ALLOC
,
5744 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET
,
5745 UVERBS_ATTR_TYPE(u64
),
5747 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX
,
5748 UVERBS_ATTR_TYPE(u16
),
5751 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5752 mlx5_ib_flow_action
,
5753 UVERBS_OBJECT_FLOW_ACTION
,
5754 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE
,
5755 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS
,
5756 enum mlx5_ib_uapi_flow_action_flags
));
5758 static const struct uapi_definition mlx5_ib_defs
[] = {
5759 #if IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS)
5760 UAPI_DEF_CHAIN(mlx5_ib_devx_defs
),
5761 UAPI_DEF_CHAIN(mlx5_ib_flow_defs
),
5764 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_FLOW_ACTION
,
5765 &mlx5_ib_flow_action
),
5766 UAPI_DEF_CHAIN_OBJ_TREE(UVERBS_OBJECT_DM
, &mlx5_ib_dm
),
5770 static int mlx5_ib_read_counters(struct ib_counters
*counters
,
5771 struct ib_counters_read_attr
*read_attr
,
5772 struct uverbs_attr_bundle
*attrs
)
5774 struct mlx5_ib_mcounters
*mcounters
= to_mcounters(counters
);
5775 struct mlx5_read_counters_attr mread_attr
= {};
5776 struct mlx5_ib_flow_counters_desc
*desc
;
5779 mutex_lock(&mcounters
->mcntrs_mutex
);
5780 if (mcounters
->cntrs_max_index
> read_attr
->ncounters
) {
5785 mread_attr
.out
= kcalloc(mcounters
->counters_num
, sizeof(u64
),
5787 if (!mread_attr
.out
) {
5792 mread_attr
.hw_cntrs_hndl
= mcounters
->hw_cntrs_hndl
;
5793 mread_attr
.flags
= read_attr
->flags
;
5794 ret
= mcounters
->read_counters(counters
->device
, &mread_attr
);
5798 /* do the pass over the counters data array to assign according to the
5799 * descriptions and indexing pairs
5801 desc
= mcounters
->counters_data
;
5802 for (i
= 0; i
< mcounters
->ncounters
; i
++)
5803 read_attr
->counters_buff
[desc
[i
].index
] += mread_attr
.out
[desc
[i
].description
];
5806 kfree(mread_attr
.out
);
5808 mutex_unlock(&mcounters
->mcntrs_mutex
);
5812 static int mlx5_ib_destroy_counters(struct ib_counters
*counters
)
5814 struct mlx5_ib_mcounters
*mcounters
= to_mcounters(counters
);
5816 counters_clear_description(counters
);
5817 if (mcounters
->hw_cntrs_hndl
)
5818 mlx5_fc_destroy(to_mdev(counters
->device
)->mdev
,
5819 mcounters
->hw_cntrs_hndl
);
5826 static struct ib_counters
*mlx5_ib_create_counters(struct ib_device
*device
,
5827 struct uverbs_attr_bundle
*attrs
)
5829 struct mlx5_ib_mcounters
*mcounters
;
5831 mcounters
= kzalloc(sizeof(*mcounters
), GFP_KERNEL
);
5833 return ERR_PTR(-ENOMEM
);
5835 mutex_init(&mcounters
->mcntrs_mutex
);
5837 return &mcounters
->ibcntrs
;
5840 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev
*dev
)
5842 mlx5_ib_cleanup_multiport_master(dev
);
5843 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
)) {
5844 srcu_barrier(&dev
->mr_srcu
);
5845 cleanup_srcu_struct(&dev
->mr_srcu
);
5850 int mlx5_ib_stage_init_init(struct mlx5_ib_dev
*dev
)
5852 struct mlx5_core_dev
*mdev
= dev
->mdev
;
5856 dev
->port
= kcalloc(dev
->num_ports
, sizeof(*dev
->port
),
5861 for (i
= 0; i
< dev
->num_ports
; i
++) {
5862 spin_lock_init(&dev
->port
[i
].mp
.mpi_lock
);
5863 rwlock_init(&dev
->roce
[i
].netdev_lock
);
5866 err
= mlx5_ib_init_multiport_master(dev
);
5870 if (!mlx5_core_mp_enabled(mdev
)) {
5871 for (i
= 1; i
<= dev
->num_ports
; i
++) {
5872 err
= get_port_caps(dev
, i
);
5877 err
= get_port_caps(dev
, mlx5_core_native_port_num(mdev
));
5882 if (mlx5_use_mad_ifc(dev
))
5883 get_ext_port_caps(dev
);
5885 dev
->ib_dev
.owner
= THIS_MODULE
;
5886 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
5887 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
5888 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
5889 dev
->ib_dev
.num_comp_vectors
= mlx5_comp_vectors_count(mdev
);
5890 dev
->ib_dev
.dev
.parent
= &mdev
->pdev
->dev
;
5892 mutex_init(&dev
->cap_mask_mutex
);
5893 INIT_LIST_HEAD(&dev
->qp_list
);
5894 spin_lock_init(&dev
->reset_flow_resource_lock
);
5896 spin_lock_init(&dev
->memic
.memic_lock
);
5897 dev
->memic
.dev
= mdev
;
5899 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
)) {
5900 err
= init_srcu_struct(&dev
->mr_srcu
);
5907 mlx5_ib_cleanup_multiport_master(dev
);
5915 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev
*dev
)
5917 dev
->flow_db
= kzalloc(sizeof(*dev
->flow_db
), GFP_KERNEL
);
5922 mutex_init(&dev
->flow_db
->lock
);
5927 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev
*dev
)
5929 struct mlx5_ib_dev
*nic_dev
;
5931 nic_dev
= mlx5_ib_get_uplink_ibdev(dev
->mdev
->priv
.eswitch
);
5936 dev
->flow_db
= nic_dev
->flow_db
;
5941 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev
*dev
)
5943 kfree(dev
->flow_db
);
5946 static const struct ib_device_ops mlx5_ib_dev_ops
= {
5947 .add_gid
= mlx5_ib_add_gid
,
5948 .alloc_mr
= mlx5_ib_alloc_mr
,
5949 .alloc_pd
= mlx5_ib_alloc_pd
,
5950 .alloc_ucontext
= mlx5_ib_alloc_ucontext
,
5951 .attach_mcast
= mlx5_ib_mcg_attach
,
5952 .check_mr_status
= mlx5_ib_check_mr_status
,
5953 .create_ah
= mlx5_ib_create_ah
,
5954 .create_counters
= mlx5_ib_create_counters
,
5955 .create_cq
= mlx5_ib_create_cq
,
5956 .create_flow
= mlx5_ib_create_flow
,
5957 .create_qp
= mlx5_ib_create_qp
,
5958 .create_srq
= mlx5_ib_create_srq
,
5959 .dealloc_pd
= mlx5_ib_dealloc_pd
,
5960 .dealloc_ucontext
= mlx5_ib_dealloc_ucontext
,
5961 .del_gid
= mlx5_ib_del_gid
,
5962 .dereg_mr
= mlx5_ib_dereg_mr
,
5963 .destroy_ah
= mlx5_ib_destroy_ah
,
5964 .destroy_counters
= mlx5_ib_destroy_counters
,
5965 .destroy_cq
= mlx5_ib_destroy_cq
,
5966 .destroy_flow
= mlx5_ib_destroy_flow
,
5967 .destroy_flow_action
= mlx5_ib_destroy_flow_action
,
5968 .destroy_qp
= mlx5_ib_destroy_qp
,
5969 .destroy_srq
= mlx5_ib_destroy_srq
,
5970 .detach_mcast
= mlx5_ib_mcg_detach
,
5971 .disassociate_ucontext
= mlx5_ib_disassociate_ucontext
,
5972 .drain_rq
= mlx5_ib_drain_rq
,
5973 .drain_sq
= mlx5_ib_drain_sq
,
5974 .get_dev_fw_str
= get_dev_fw_str
,
5975 .get_dma_mr
= mlx5_ib_get_dma_mr
,
5976 .get_link_layer
= mlx5_ib_port_link_layer
,
5977 .map_mr_sg
= mlx5_ib_map_mr_sg
,
5978 .mmap
= mlx5_ib_mmap
,
5979 .modify_cq
= mlx5_ib_modify_cq
,
5980 .modify_device
= mlx5_ib_modify_device
,
5981 .modify_port
= mlx5_ib_modify_port
,
5982 .modify_qp
= mlx5_ib_modify_qp
,
5983 .modify_srq
= mlx5_ib_modify_srq
,
5984 .poll_cq
= mlx5_ib_poll_cq
,
5985 .post_recv
= mlx5_ib_post_recv
,
5986 .post_send
= mlx5_ib_post_send
,
5987 .post_srq_recv
= mlx5_ib_post_srq_recv
,
5988 .process_mad
= mlx5_ib_process_mad
,
5989 .query_ah
= mlx5_ib_query_ah
,
5990 .query_device
= mlx5_ib_query_device
,
5991 .query_gid
= mlx5_ib_query_gid
,
5992 .query_pkey
= mlx5_ib_query_pkey
,
5993 .query_qp
= mlx5_ib_query_qp
,
5994 .query_srq
= mlx5_ib_query_srq
,
5995 .read_counters
= mlx5_ib_read_counters
,
5996 .reg_user_mr
= mlx5_ib_reg_user_mr
,
5997 .req_notify_cq
= mlx5_ib_arm_cq
,
5998 .rereg_user_mr
= mlx5_ib_rereg_user_mr
,
5999 .resize_cq
= mlx5_ib_resize_cq
,
6001 INIT_RDMA_OBJ_SIZE(ib_ah
, mlx5_ib_ah
, ibah
),
6002 INIT_RDMA_OBJ_SIZE(ib_pd
, mlx5_ib_pd
, ibpd
),
6003 INIT_RDMA_OBJ_SIZE(ib_srq
, mlx5_ib_srq
, ibsrq
),
6004 INIT_RDMA_OBJ_SIZE(ib_ucontext
, mlx5_ib_ucontext
, ibucontext
),
6007 static const struct ib_device_ops mlx5_ib_dev_flow_ipsec_ops
= {
6008 .create_flow_action_esp
= mlx5_ib_create_flow_action_esp
,
6009 .modify_flow_action_esp
= mlx5_ib_modify_flow_action_esp
,
6012 static const struct ib_device_ops mlx5_ib_dev_ipoib_enhanced_ops
= {
6013 .rdma_netdev_get_params
= mlx5_ib_rn_get_params
,
6016 static const struct ib_device_ops mlx5_ib_dev_sriov_ops
= {
6017 .get_vf_config
= mlx5_ib_get_vf_config
,
6018 .get_vf_stats
= mlx5_ib_get_vf_stats
,
6019 .set_vf_guid
= mlx5_ib_set_vf_guid
,
6020 .set_vf_link_state
= mlx5_ib_set_vf_link_state
,
6023 static const struct ib_device_ops mlx5_ib_dev_mw_ops
= {
6024 .alloc_mw
= mlx5_ib_alloc_mw
,
6025 .dealloc_mw
= mlx5_ib_dealloc_mw
,
6028 static const struct ib_device_ops mlx5_ib_dev_xrc_ops
= {
6029 .alloc_xrcd
= mlx5_ib_alloc_xrcd
,
6030 .dealloc_xrcd
= mlx5_ib_dealloc_xrcd
,
6033 static const struct ib_device_ops mlx5_ib_dev_dm_ops
= {
6034 .alloc_dm
= mlx5_ib_alloc_dm
,
6035 .dealloc_dm
= mlx5_ib_dealloc_dm
,
6036 .reg_dm_mr
= mlx5_ib_reg_dm_mr
,
6039 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev
*dev
)
6041 struct mlx5_core_dev
*mdev
= dev
->mdev
;
6044 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
6045 dev
->ib_dev
.uverbs_cmd_mask
=
6046 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
6047 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
6048 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
6049 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
6050 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
6051 (1ull << IB_USER_VERBS_CMD_CREATE_AH
) |
6052 (1ull << IB_USER_VERBS_CMD_DESTROY_AH
) |
6053 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
6054 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
6055 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
6056 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
6057 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
6058 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
6059 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
6060 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
6061 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
6062 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
6063 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
6064 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
6065 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
6066 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
6067 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
6068 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
6069 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
6070 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
6071 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
6072 dev
->ib_dev
.uverbs_ex_cmd_mask
=
6073 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
6074 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
6075 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
) |
6076 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP
) |
6077 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ
) |
6078 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
6079 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
);
6081 if (MLX5_CAP_GEN(mdev
, ipoib_enhanced_offloads
) &&
6082 IS_ENABLED(CONFIG_MLX5_CORE_IPOIB
))
6083 ib_set_device_ops(&dev
->ib_dev
,
6084 &mlx5_ib_dev_ipoib_enhanced_ops
);
6086 if (mlx5_core_is_pf(mdev
))
6087 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_sriov_ops
);
6089 dev
->umr_fence
= mlx5_get_umr_fence(MLX5_CAP_GEN(mdev
, umr_fence
));
6091 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
6092 dev
->ib_dev
.uverbs_cmd_mask
|=
6093 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
6094 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
6095 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_mw_ops
);
6098 if (MLX5_CAP_GEN(mdev
, xrc
)) {
6099 dev
->ib_dev
.uverbs_cmd_mask
|=
6100 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
6101 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
6102 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_xrc_ops
);
6105 if (MLX5_CAP_DEV_MEM(mdev
, memic
))
6106 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_dm_ops
);
6108 if (mlx5_accel_ipsec_device_caps(dev
->mdev
) &
6109 MLX5_ACCEL_IPSEC_CAP_DEVICE
)
6110 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_flow_ipsec_ops
);
6111 dev
->ib_dev
.driver_id
= RDMA_DRIVER_MLX5
;
6112 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_ops
);
6114 if (IS_ENABLED(CONFIG_INFINIBAND_USER_ACCESS
))
6115 dev
->ib_dev
.driver_def
= mlx5_ib_defs
;
6117 err
= init_node_data(dev
);
6121 if ((MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_ETH
) &&
6122 (MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_uc
) ||
6123 MLX5_CAP_GEN(dev
->mdev
, disable_local_lb_mc
)))
6124 mutex_init(&dev
->lb
.mutex
);
6129 static const struct ib_device_ops mlx5_ib_dev_port_ops
= {
6130 .get_port_immutable
= mlx5_port_immutable
,
6131 .query_port
= mlx5_ib_query_port
,
6134 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev
*dev
)
6136 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_port_ops
);
6140 static const struct ib_device_ops mlx5_ib_dev_port_rep_ops
= {
6141 .get_port_immutable
= mlx5_port_rep_immutable
,
6142 .query_port
= mlx5_ib_rep_query_port
,
6145 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev
*dev
)
6147 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_port_rep_ops
);
6151 static const struct ib_device_ops mlx5_ib_dev_common_roce_ops
= {
6152 .create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
,
6153 .create_wq
= mlx5_ib_create_wq
,
6154 .destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
,
6155 .destroy_wq
= mlx5_ib_destroy_wq
,
6156 .get_netdev
= mlx5_ib_get_netdev
,
6157 .modify_wq
= mlx5_ib_modify_wq
,
6160 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev
*dev
)
6165 for (i
= 0; i
< dev
->num_ports
; i
++) {
6166 dev
->roce
[i
].dev
= dev
;
6167 dev
->roce
[i
].native_port_num
= i
+ 1;
6168 dev
->roce
[i
].last_port_state
= IB_PORT_DOWN
;
6171 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
6172 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
6173 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
6174 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
6175 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
6176 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
6177 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_common_roce_ops
);
6179 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
6181 return mlx5_add_netdev_notifier(dev
, port_num
);
6184 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev
*dev
)
6186 u8 port_num
= mlx5_core_native_port_num(dev
->mdev
) - 1;
6188 mlx5_remove_netdev_notifier(dev
, port_num
);
6191 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev
*dev
)
6193 struct mlx5_core_dev
*mdev
= dev
->mdev
;
6194 enum rdma_link_layer ll
;
6198 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
6199 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
6201 if (ll
== IB_LINK_LAYER_ETHERNET
)
6202 err
= mlx5_ib_stage_common_roce_init(dev
);
6207 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev
*dev
)
6209 mlx5_ib_stage_common_roce_cleanup(dev
);
6212 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev
*dev
)
6214 struct mlx5_core_dev
*mdev
= dev
->mdev
;
6215 enum rdma_link_layer ll
;
6219 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
6220 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
6222 if (ll
== IB_LINK_LAYER_ETHERNET
) {
6223 err
= mlx5_ib_stage_common_roce_init(dev
);
6227 err
= mlx5_enable_eth(dev
);
6234 mlx5_ib_stage_common_roce_cleanup(dev
);
6239 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev
*dev
)
6241 struct mlx5_core_dev
*mdev
= dev
->mdev
;
6242 enum rdma_link_layer ll
;
6245 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
6246 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
6248 if (ll
== IB_LINK_LAYER_ETHERNET
) {
6249 mlx5_disable_eth(dev
);
6250 mlx5_ib_stage_common_roce_cleanup(dev
);
6254 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev
*dev
)
6256 return create_dev_resources(&dev
->devr
);
6259 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev
*dev
)
6261 destroy_dev_resources(&dev
->devr
);
6264 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev
*dev
)
6266 mlx5_ib_internal_fill_odp_caps(dev
);
6268 return mlx5_ib_odp_init_one(dev
);
6271 static void mlx5_ib_stage_odp_cleanup(struct mlx5_ib_dev
*dev
)
6273 mlx5_ib_odp_cleanup_one(dev
);
6276 static const struct ib_device_ops mlx5_ib_dev_hw_stats_ops
= {
6277 .alloc_hw_stats
= mlx5_ib_alloc_hw_stats
,
6278 .get_hw_stats
= mlx5_ib_get_hw_stats
,
6281 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev
*dev
)
6283 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
)) {
6284 ib_set_device_ops(&dev
->ib_dev
, &mlx5_ib_dev_hw_stats_ops
);
6286 return mlx5_ib_alloc_counters(dev
);
6292 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev
*dev
)
6294 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
))
6295 mlx5_ib_dealloc_counters(dev
);
6298 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev
*dev
)
6300 mlx5_ib_init_cong_debugfs(dev
,
6301 mlx5_core_native_port_num(dev
->mdev
) - 1);
6305 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev
*dev
)
6307 mlx5_ib_cleanup_cong_debugfs(dev
,
6308 mlx5_core_native_port_num(dev
->mdev
) - 1);
6311 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev
*dev
)
6313 dev
->mdev
->priv
.uar
= mlx5_get_uars_page(dev
->mdev
);
6314 return PTR_ERR_OR_ZERO(dev
->mdev
->priv
.uar
);
6317 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev
*dev
)
6319 mlx5_put_uars_page(dev
->mdev
, dev
->mdev
->priv
.uar
);
6322 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev
*dev
)
6326 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->bfreg
, false, false);
6330 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->fp_bfreg
, false, true);
6332 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
6337 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev
*dev
)
6339 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
6340 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
6343 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev
*dev
)
6347 rdma_set_device_sysfs_group(&dev
->ib_dev
, &mlx5_attr_group
);
6348 if (!mlx5_lag_is_roce(dev
->mdev
))
6351 name
= "mlx5_bond_%d";
6352 return ib_register_device(&dev
->ib_dev
, name
);
6355 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev
*dev
)
6357 destroy_umrc_res(dev
);
6360 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev
*dev
)
6362 ib_unregister_device(&dev
->ib_dev
);
6365 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev
*dev
)
6367 return create_umr_res(dev
);
6370 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev
*dev
)
6372 init_delay_drop(dev
);
6377 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev
*dev
)
6379 cancel_delay_drop(dev
);
6382 static int mlx5_ib_stage_dev_notifier_init(struct mlx5_ib_dev
*dev
)
6384 dev
->mdev_events
.notifier_call
= mlx5_ib_event
;
6385 mlx5_notifier_register(dev
->mdev
, &dev
->mdev_events
);
6389 static void mlx5_ib_stage_dev_notifier_cleanup(struct mlx5_ib_dev
*dev
)
6391 mlx5_notifier_unregister(dev
->mdev
, &dev
->mdev_events
);
6394 static int mlx5_ib_stage_devx_init(struct mlx5_ib_dev
*dev
)
6398 uid
= mlx5_ib_devx_create(dev
, false);
6400 dev
->devx_whitelist_uid
= uid
;
6404 static void mlx5_ib_stage_devx_cleanup(struct mlx5_ib_dev
*dev
)
6406 if (dev
->devx_whitelist_uid
)
6407 mlx5_ib_devx_destroy(dev
, dev
->devx_whitelist_uid
);
6410 void __mlx5_ib_remove(struct mlx5_ib_dev
*dev
,
6411 const struct mlx5_ib_profile
*profile
,
6414 /* Number of stages to cleanup */
6417 if (profile
->stage
[stage
].cleanup
)
6418 profile
->stage
[stage
].cleanup(dev
);
6422 void *__mlx5_ib_add(struct mlx5_ib_dev
*dev
,
6423 const struct mlx5_ib_profile
*profile
)
6428 for (i
= 0; i
< MLX5_IB_STAGE_MAX
; i
++) {
6429 if (profile
->stage
[i
].init
) {
6430 err
= profile
->stage
[i
].init(dev
);
6436 dev
->profile
= profile
;
6437 dev
->ib_active
= true;
6442 __mlx5_ib_remove(dev
, profile
, i
);
6447 static const struct mlx5_ib_profile pf_profile
= {
6448 STAGE_CREATE(MLX5_IB_STAGE_INIT
,
6449 mlx5_ib_stage_init_init
,
6450 mlx5_ib_stage_init_cleanup
),
6451 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB
,
6452 mlx5_ib_stage_flow_db_init
,
6453 mlx5_ib_stage_flow_db_cleanup
),
6454 STAGE_CREATE(MLX5_IB_STAGE_CAPS
,
6455 mlx5_ib_stage_caps_init
,
6457 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB
,
6458 mlx5_ib_stage_non_default_cb
,
6460 STAGE_CREATE(MLX5_IB_STAGE_ROCE
,
6461 mlx5_ib_stage_roce_init
,
6462 mlx5_ib_stage_roce_cleanup
),
6463 STAGE_CREATE(MLX5_IB_STAGE_SRQ
,
6464 mlx5_init_srq_table
,
6465 mlx5_cleanup_srq_table
),
6466 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES
,
6467 mlx5_ib_stage_dev_res_init
,
6468 mlx5_ib_stage_dev_res_cleanup
),
6469 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER
,
6470 mlx5_ib_stage_dev_notifier_init
,
6471 mlx5_ib_stage_dev_notifier_cleanup
),
6472 STAGE_CREATE(MLX5_IB_STAGE_ODP
,
6473 mlx5_ib_stage_odp_init
,
6474 mlx5_ib_stage_odp_cleanup
),
6475 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS
,
6476 mlx5_ib_stage_counters_init
,
6477 mlx5_ib_stage_counters_cleanup
),
6478 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS
,
6479 mlx5_ib_stage_cong_debugfs_init
,
6480 mlx5_ib_stage_cong_debugfs_cleanup
),
6481 STAGE_CREATE(MLX5_IB_STAGE_UAR
,
6482 mlx5_ib_stage_uar_init
,
6483 mlx5_ib_stage_uar_cleanup
),
6484 STAGE_CREATE(MLX5_IB_STAGE_BFREG
,
6485 mlx5_ib_stage_bfrag_init
,
6486 mlx5_ib_stage_bfrag_cleanup
),
6487 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR
,
6489 mlx5_ib_stage_pre_ib_reg_umr_cleanup
),
6490 STAGE_CREATE(MLX5_IB_STAGE_WHITELIST_UID
,
6491 mlx5_ib_stage_devx_init
,
6492 mlx5_ib_stage_devx_cleanup
),
6493 STAGE_CREATE(MLX5_IB_STAGE_IB_REG
,
6494 mlx5_ib_stage_ib_reg_init
,
6495 mlx5_ib_stage_ib_reg_cleanup
),
6496 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR
,
6497 mlx5_ib_stage_post_ib_reg_umr_init
,
6499 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP
,
6500 mlx5_ib_stage_delay_drop_init
,
6501 mlx5_ib_stage_delay_drop_cleanup
),
6504 const struct mlx5_ib_profile uplink_rep_profile
= {
6505 STAGE_CREATE(MLX5_IB_STAGE_INIT
,
6506 mlx5_ib_stage_init_init
,
6507 mlx5_ib_stage_init_cleanup
),
6508 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB
,
6509 mlx5_ib_stage_flow_db_init
,
6510 mlx5_ib_stage_flow_db_cleanup
),
6511 STAGE_CREATE(MLX5_IB_STAGE_CAPS
,
6512 mlx5_ib_stage_caps_init
,
6514 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB
,
6515 mlx5_ib_stage_rep_non_default_cb
,
6517 STAGE_CREATE(MLX5_IB_STAGE_ROCE
,
6518 mlx5_ib_stage_rep_roce_init
,
6519 mlx5_ib_stage_rep_roce_cleanup
),
6520 STAGE_CREATE(MLX5_IB_STAGE_SRQ
,
6521 mlx5_init_srq_table
,
6522 mlx5_cleanup_srq_table
),
6523 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES
,
6524 mlx5_ib_stage_dev_res_init
,
6525 mlx5_ib_stage_dev_res_cleanup
),
6526 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_NOTIFIER
,
6527 mlx5_ib_stage_dev_notifier_init
,
6528 mlx5_ib_stage_dev_notifier_cleanup
),
6529 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS
,
6530 mlx5_ib_stage_counters_init
,
6531 mlx5_ib_stage_counters_cleanup
),
6532 STAGE_CREATE(MLX5_IB_STAGE_UAR
,
6533 mlx5_ib_stage_uar_init
,
6534 mlx5_ib_stage_uar_cleanup
),
6535 STAGE_CREATE(MLX5_IB_STAGE_BFREG
,
6536 mlx5_ib_stage_bfrag_init
,
6537 mlx5_ib_stage_bfrag_cleanup
),
6538 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR
,
6540 mlx5_ib_stage_pre_ib_reg_umr_cleanup
),
6541 STAGE_CREATE(MLX5_IB_STAGE_IB_REG
,
6542 mlx5_ib_stage_ib_reg_init
,
6543 mlx5_ib_stage_ib_reg_cleanup
),
6544 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR
,
6545 mlx5_ib_stage_post_ib_reg_umr_init
,
6549 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev
*mdev
)
6551 struct mlx5_ib_multiport_info
*mpi
;
6552 struct mlx5_ib_dev
*dev
;
6556 mpi
= kzalloc(sizeof(*mpi
), GFP_KERNEL
);
6562 err
= mlx5_query_nic_vport_system_image_guid(mdev
,
6563 &mpi
->sys_image_guid
);
6569 mutex_lock(&mlx5_ib_multiport_mutex
);
6570 list_for_each_entry(dev
, &mlx5_ib_dev_list
, ib_dev_list
) {
6571 if (dev
->sys_image_guid
== mpi
->sys_image_guid
)
6572 bound
= mlx5_ib_bind_slave_port(dev
, mpi
);
6575 rdma_roce_rescan_device(&dev
->ib_dev
);
6581 list_add_tail(&mpi
->list
, &mlx5_ib_unaffiliated_port_list
);
6582 dev_dbg(&mdev
->pdev
->dev
, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6584 mutex_unlock(&mlx5_ib_multiport_mutex
);
6589 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
6591 enum rdma_link_layer ll
;
6592 struct mlx5_ib_dev
*dev
;
6595 printk_once(KERN_INFO
"%s", mlx5_version
);
6597 if (MLX5_ESWITCH_MANAGER(mdev
) &&
6598 mlx5_ib_eswitch_mode(mdev
->priv
.eswitch
) == SRIOV_OFFLOADS
) {
6599 mlx5_ib_register_vport_reps(mdev
);
6603 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
6604 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
6606 if (mlx5_core_is_mp_slave(mdev
) && ll
== IB_LINK_LAYER_ETHERNET
)
6607 return mlx5_ib_add_slave_port(mdev
);
6609 dev
= ib_alloc_device(mlx5_ib_dev
, ib_dev
);
6614 dev
->num_ports
= max(MLX5_CAP_GEN(mdev
, num_ports
),
6615 MLX5_CAP_GEN(mdev
, num_vhca_ports
));
6617 return __mlx5_ib_add(dev
, &pf_profile
);
6620 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
6622 struct mlx5_ib_multiport_info
*mpi
;
6623 struct mlx5_ib_dev
*dev
;
6625 if (MLX5_ESWITCH_MANAGER(mdev
) && context
== mdev
) {
6626 mlx5_ib_unregister_vport_reps(mdev
);
6630 if (mlx5_core_is_mp_slave(mdev
)) {
6632 mutex_lock(&mlx5_ib_multiport_mutex
);
6634 mlx5_ib_unbind_slave_port(mpi
->ibdev
, mpi
);
6635 list_del(&mpi
->list
);
6636 mutex_unlock(&mlx5_ib_multiport_mutex
);
6641 __mlx5_ib_remove(dev
, dev
->profile
, MLX5_IB_STAGE_MAX
);
6643 ib_dealloc_device((struct ib_device
*)dev
);
6646 static struct mlx5_interface mlx5_ib_interface
= {
6648 .remove
= mlx5_ib_remove
,
6649 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
6652 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6654 mutex_lock(&xlt_emergency_page_mutex
);
6655 return xlt_emergency_page
;
6658 void mlx5_ib_put_xlt_emergency_page(void)
6660 mutex_unlock(&xlt_emergency_page_mutex
);
6663 static int __init
mlx5_ib_init(void)
6667 xlt_emergency_page
= __get_free_page(GFP_KERNEL
);
6668 if (!xlt_emergency_page
)
6671 mutex_init(&xlt_emergency_page_mutex
);
6673 mlx5_ib_event_wq
= alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6674 if (!mlx5_ib_event_wq
) {
6675 free_page(xlt_emergency_page
);
6681 err
= mlx5_register_interface(&mlx5_ib_interface
);
6686 static void __exit
mlx5_ib_cleanup(void)
6688 mlx5_unregister_interface(&mlx5_ib_interface
);
6689 destroy_workqueue(mlx5_ib_event_wq
);
6690 mutex_destroy(&xlt_emergency_page_mutex
);
6691 free_page(xlt_emergency_page
);
6694 module_init(mlx5_ib_init
);
6695 module_exit(mlx5_ib_cleanup
);