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RDMA: Remove useless MODULE_VERSION
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
41 #include <asm/pat.h>
42 #endif
43 #include <linux/sched.h>
44 #include <linux/sched/mm.h>
45 #include <linux/sched/task.h>
46 #include <linux/delay.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_cache.h>
50 #include <linux/mlx5/port.h>
51 #include <linux/mlx5/vport.h>
52 #include <linux/list.h>
53 #include <rdma/ib_smi.h>
54 #include <rdma/ib_umem.h>
55 #include <linux/in.h>
56 #include <linux/etherdevice.h>
57 #include <linux/mlx5/fs.h>
58 #include <linux/mlx5/vport.h>
59 #include "mlx5_ib.h"
60 #include "cmd.h"
61
62 #define DRIVER_NAME "mlx5_ib"
63 #define DRIVER_VERSION "5.0-0"
64
65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67 MODULE_LICENSE("Dual BSD/GPL");
68
69 static char mlx5_version[] =
70 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
71 DRIVER_VERSION "\n";
72
73 enum {
74 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
75 };
76
77 static enum rdma_link_layer
78 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
79 {
80 switch (port_type_cap) {
81 case MLX5_CAP_PORT_TYPE_IB:
82 return IB_LINK_LAYER_INFINIBAND;
83 case MLX5_CAP_PORT_TYPE_ETH:
84 return IB_LINK_LAYER_ETHERNET;
85 default:
86 return IB_LINK_LAYER_UNSPECIFIED;
87 }
88 }
89
90 static enum rdma_link_layer
91 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
92 {
93 struct mlx5_ib_dev *dev = to_mdev(device);
94 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
95
96 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
97 }
98
99 static int mlx5_netdev_event(struct notifier_block *this,
100 unsigned long event, void *ptr)
101 {
102 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
103 struct mlx5_ib_dev *ibdev = container_of(this, struct mlx5_ib_dev,
104 roce.nb);
105
106 switch (event) {
107 case NETDEV_REGISTER:
108 case NETDEV_UNREGISTER:
109 write_lock(&ibdev->roce.netdev_lock);
110 if (ndev->dev.parent == &ibdev->mdev->pdev->dev)
111 ibdev->roce.netdev = (event == NETDEV_UNREGISTER) ?
112 NULL : ndev;
113 write_unlock(&ibdev->roce.netdev_lock);
114 break;
115
116 case NETDEV_UP:
117 case NETDEV_DOWN: {
118 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
119 struct net_device *upper = NULL;
120
121 if (lag_ndev) {
122 upper = netdev_master_upper_dev_get(lag_ndev);
123 dev_put(lag_ndev);
124 }
125
126 if ((upper == ndev || (!upper && ndev == ibdev->roce.netdev))
127 && ibdev->ib_active) {
128 struct ib_event ibev = { };
129
130 ibev.device = &ibdev->ib_dev;
131 ibev.event = (event == NETDEV_UP) ?
132 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
133 ibev.element.port_num = 1;
134 ib_dispatch_event(&ibev);
135 }
136 break;
137 }
138
139 default:
140 break;
141 }
142
143 return NOTIFY_DONE;
144 }
145
146 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
147 u8 port_num)
148 {
149 struct mlx5_ib_dev *ibdev = to_mdev(device);
150 struct net_device *ndev;
151
152 ndev = mlx5_lag_get_roce_netdev(ibdev->mdev);
153 if (ndev)
154 return ndev;
155
156 /* Ensure ndev does not disappear before we invoke dev_hold()
157 */
158 read_lock(&ibdev->roce.netdev_lock);
159 ndev = ibdev->roce.netdev;
160 if (ndev)
161 dev_hold(ndev);
162 read_unlock(&ibdev->roce.netdev_lock);
163
164 return ndev;
165 }
166
167 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
168 u8 *active_width)
169 {
170 switch (eth_proto_oper) {
171 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
172 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
173 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
174 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
175 *active_width = IB_WIDTH_1X;
176 *active_speed = IB_SPEED_SDR;
177 break;
178 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
179 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
180 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
181 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
182 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
183 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
184 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
185 *active_width = IB_WIDTH_1X;
186 *active_speed = IB_SPEED_QDR;
187 break;
188 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
189 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
190 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
191 *active_width = IB_WIDTH_1X;
192 *active_speed = IB_SPEED_EDR;
193 break;
194 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
195 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
196 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
197 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
198 *active_width = IB_WIDTH_4X;
199 *active_speed = IB_SPEED_QDR;
200 break;
201 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
202 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
203 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
204 *active_width = IB_WIDTH_1X;
205 *active_speed = IB_SPEED_HDR;
206 break;
207 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
208 *active_width = IB_WIDTH_4X;
209 *active_speed = IB_SPEED_FDR;
210 break;
211 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
212 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
213 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
214 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
215 *active_width = IB_WIDTH_4X;
216 *active_speed = IB_SPEED_EDR;
217 break;
218 default:
219 return -EINVAL;
220 }
221
222 return 0;
223 }
224
225 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
226 struct ib_port_attr *props)
227 {
228 struct mlx5_ib_dev *dev = to_mdev(device);
229 struct mlx5_core_dev *mdev = dev->mdev;
230 struct net_device *ndev, *upper;
231 enum ib_mtu ndev_ib_mtu;
232 u16 qkey_viol_cntr;
233 u32 eth_prot_oper;
234 int err;
235
236 /* Possible bad flows are checked before filling out props so in case
237 * of an error it will still be zeroed out.
238 */
239 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper, port_num);
240 if (err)
241 return err;
242
243 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
244 &props->active_width);
245
246 props->port_cap_flags |= IB_PORT_CM_SUP;
247 props->port_cap_flags |= IB_PORT_IP_BASED_GIDS;
248
249 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
250 roce_address_table_size);
251 props->max_mtu = IB_MTU_4096;
252 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
253 props->pkey_tbl_len = 1;
254 props->state = IB_PORT_DOWN;
255 props->phys_state = 3;
256
257 mlx5_query_nic_vport_qkey_viol_cntr(dev->mdev, &qkey_viol_cntr);
258 props->qkey_viol_cntr = qkey_viol_cntr;
259
260 ndev = mlx5_ib_get_netdev(device, port_num);
261 if (!ndev)
262 return 0;
263
264 if (mlx5_lag_is_active(dev->mdev)) {
265 rcu_read_lock();
266 upper = netdev_master_upper_dev_get_rcu(ndev);
267 if (upper) {
268 dev_put(ndev);
269 ndev = upper;
270 dev_hold(ndev);
271 }
272 rcu_read_unlock();
273 }
274
275 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
276 props->state = IB_PORT_ACTIVE;
277 props->phys_state = 5;
278 }
279
280 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
281
282 dev_put(ndev);
283
284 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
285 return 0;
286 }
287
288 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
289 unsigned int index, const union ib_gid *gid,
290 const struct ib_gid_attr *attr)
291 {
292 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
293 u8 roce_version = 0;
294 u8 roce_l3_type = 0;
295 bool vlan = false;
296 u8 mac[ETH_ALEN];
297 u16 vlan_id = 0;
298
299 if (gid) {
300 gid_type = attr->gid_type;
301 ether_addr_copy(mac, attr->ndev->dev_addr);
302
303 if (is_vlan_dev(attr->ndev)) {
304 vlan = true;
305 vlan_id = vlan_dev_vlan_id(attr->ndev);
306 }
307 }
308
309 switch (gid_type) {
310 case IB_GID_TYPE_IB:
311 roce_version = MLX5_ROCE_VERSION_1;
312 break;
313 case IB_GID_TYPE_ROCE_UDP_ENCAP:
314 roce_version = MLX5_ROCE_VERSION_2;
315 if (ipv6_addr_v4mapped((void *)gid))
316 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
317 else
318 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
319 break;
320
321 default:
322 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
323 }
324
325 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
326 roce_l3_type, gid->raw, mac, vlan,
327 vlan_id);
328 }
329
330 static int mlx5_ib_add_gid(struct ib_device *device, u8 port_num,
331 unsigned int index, const union ib_gid *gid,
332 const struct ib_gid_attr *attr,
333 __always_unused void **context)
334 {
335 return set_roce_addr(to_mdev(device), port_num, index, gid, attr);
336 }
337
338 static int mlx5_ib_del_gid(struct ib_device *device, u8 port_num,
339 unsigned int index, __always_unused void **context)
340 {
341 return set_roce_addr(to_mdev(device), port_num, index, NULL, NULL);
342 }
343
344 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev, u8 port_num,
345 int index)
346 {
347 struct ib_gid_attr attr;
348 union ib_gid gid;
349
350 if (ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr))
351 return 0;
352
353 if (!attr.ndev)
354 return 0;
355
356 dev_put(attr.ndev);
357
358 if (attr.gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
359 return 0;
360
361 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
362 }
363
364 int mlx5_get_roce_gid_type(struct mlx5_ib_dev *dev, u8 port_num,
365 int index, enum ib_gid_type *gid_type)
366 {
367 struct ib_gid_attr attr;
368 union ib_gid gid;
369 int ret;
370
371 ret = ib_get_cached_gid(&dev->ib_dev, port_num, index, &gid, &attr);
372 if (ret)
373 return ret;
374
375 if (!attr.ndev)
376 return -ENODEV;
377
378 dev_put(attr.ndev);
379
380 *gid_type = attr.gid_type;
381
382 return 0;
383 }
384
385 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
386 {
387 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
388 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
389 return 0;
390 }
391
392 enum {
393 MLX5_VPORT_ACCESS_METHOD_MAD,
394 MLX5_VPORT_ACCESS_METHOD_HCA,
395 MLX5_VPORT_ACCESS_METHOD_NIC,
396 };
397
398 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
399 {
400 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
401 return MLX5_VPORT_ACCESS_METHOD_MAD;
402
403 if (mlx5_ib_port_link_layer(ibdev, 1) ==
404 IB_LINK_LAYER_ETHERNET)
405 return MLX5_VPORT_ACCESS_METHOD_NIC;
406
407 return MLX5_VPORT_ACCESS_METHOD_HCA;
408 }
409
410 static void get_atomic_caps(struct mlx5_ib_dev *dev,
411 struct ib_device_attr *props)
412 {
413 u8 tmp;
414 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
415 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
416 u8 atomic_req_8B_endianness_mode =
417 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
418
419 /* Check if HW supports 8 bytes standard atomic operations and capable
420 * of host endianness respond
421 */
422 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
423 if (((atomic_operations & tmp) == tmp) &&
424 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
425 (atomic_req_8B_endianness_mode)) {
426 props->atomic_cap = IB_ATOMIC_HCA;
427 } else {
428 props->atomic_cap = IB_ATOMIC_NONE;
429 }
430 }
431
432 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
433 __be64 *sys_image_guid)
434 {
435 struct mlx5_ib_dev *dev = to_mdev(ibdev);
436 struct mlx5_core_dev *mdev = dev->mdev;
437 u64 tmp;
438 int err;
439
440 switch (mlx5_get_vport_access_method(ibdev)) {
441 case MLX5_VPORT_ACCESS_METHOD_MAD:
442 return mlx5_query_mad_ifc_system_image_guid(ibdev,
443 sys_image_guid);
444
445 case MLX5_VPORT_ACCESS_METHOD_HCA:
446 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
447 break;
448
449 case MLX5_VPORT_ACCESS_METHOD_NIC:
450 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
451 break;
452
453 default:
454 return -EINVAL;
455 }
456
457 if (!err)
458 *sys_image_guid = cpu_to_be64(tmp);
459
460 return err;
461
462 }
463
464 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
465 u16 *max_pkeys)
466 {
467 struct mlx5_ib_dev *dev = to_mdev(ibdev);
468 struct mlx5_core_dev *mdev = dev->mdev;
469
470 switch (mlx5_get_vport_access_method(ibdev)) {
471 case MLX5_VPORT_ACCESS_METHOD_MAD:
472 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
473
474 case MLX5_VPORT_ACCESS_METHOD_HCA:
475 case MLX5_VPORT_ACCESS_METHOD_NIC:
476 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
477 pkey_table_size));
478 return 0;
479
480 default:
481 return -EINVAL;
482 }
483 }
484
485 static int mlx5_query_vendor_id(struct ib_device *ibdev,
486 u32 *vendor_id)
487 {
488 struct mlx5_ib_dev *dev = to_mdev(ibdev);
489
490 switch (mlx5_get_vport_access_method(ibdev)) {
491 case MLX5_VPORT_ACCESS_METHOD_MAD:
492 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
493
494 case MLX5_VPORT_ACCESS_METHOD_HCA:
495 case MLX5_VPORT_ACCESS_METHOD_NIC:
496 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
497
498 default:
499 return -EINVAL;
500 }
501 }
502
503 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
504 __be64 *node_guid)
505 {
506 u64 tmp;
507 int err;
508
509 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
510 case MLX5_VPORT_ACCESS_METHOD_MAD:
511 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
512
513 case MLX5_VPORT_ACCESS_METHOD_HCA:
514 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
515 break;
516
517 case MLX5_VPORT_ACCESS_METHOD_NIC:
518 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
519 break;
520
521 default:
522 return -EINVAL;
523 }
524
525 if (!err)
526 *node_guid = cpu_to_be64(tmp);
527
528 return err;
529 }
530
531 struct mlx5_reg_node_desc {
532 u8 desc[IB_DEVICE_NODE_DESC_MAX];
533 };
534
535 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
536 {
537 struct mlx5_reg_node_desc in;
538
539 if (mlx5_use_mad_ifc(dev))
540 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
541
542 memset(&in, 0, sizeof(in));
543
544 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
545 sizeof(struct mlx5_reg_node_desc),
546 MLX5_REG_NODE_DESC, 0, 0);
547 }
548
549 static int mlx5_ib_query_device(struct ib_device *ibdev,
550 struct ib_device_attr *props,
551 struct ib_udata *uhw)
552 {
553 struct mlx5_ib_dev *dev = to_mdev(ibdev);
554 struct mlx5_core_dev *mdev = dev->mdev;
555 int err = -ENOMEM;
556 int max_sq_desc;
557 int max_rq_sg;
558 int max_sq_sg;
559 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
560 struct mlx5_ib_query_device_resp resp = {};
561 size_t resp_len;
562 u64 max_tso;
563
564 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
565 if (uhw->outlen && uhw->outlen < resp_len)
566 return -EINVAL;
567 else
568 resp.response_length = resp_len;
569
570 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
571 return -EINVAL;
572
573 memset(props, 0, sizeof(*props));
574 err = mlx5_query_system_image_guid(ibdev,
575 &props->sys_image_guid);
576 if (err)
577 return err;
578
579 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
580 if (err)
581 return err;
582
583 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
584 if (err)
585 return err;
586
587 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
588 (fw_rev_min(dev->mdev) << 16) |
589 fw_rev_sub(dev->mdev);
590 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
591 IB_DEVICE_PORT_ACTIVE_EVENT |
592 IB_DEVICE_SYS_IMAGE_GUID |
593 IB_DEVICE_RC_RNR_NAK_GEN;
594
595 if (MLX5_CAP_GEN(mdev, pkv))
596 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
597 if (MLX5_CAP_GEN(mdev, qkv))
598 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
599 if (MLX5_CAP_GEN(mdev, apm))
600 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
601 if (MLX5_CAP_GEN(mdev, xrc))
602 props->device_cap_flags |= IB_DEVICE_XRC;
603 if (MLX5_CAP_GEN(mdev, imaicl)) {
604 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
605 IB_DEVICE_MEM_WINDOW_TYPE_2B;
606 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
607 /* We support 'Gappy' memory registration too */
608 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
609 }
610 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
611 if (MLX5_CAP_GEN(mdev, sho)) {
612 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
613 /* At this stage no support for signature handover */
614 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
615 IB_PROT_T10DIF_TYPE_2 |
616 IB_PROT_T10DIF_TYPE_3;
617 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
618 IB_GUARD_T10DIF_CSUM;
619 }
620 if (MLX5_CAP_GEN(mdev, block_lb_mc))
621 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
622
623 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads)) {
624 if (MLX5_CAP_ETH(mdev, csum_cap)) {
625 /* Legacy bit to support old userspace libraries */
626 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
627 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
628 }
629
630 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
631 props->raw_packet_caps |=
632 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
633
634 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
635 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
636 if (max_tso) {
637 resp.tso_caps.max_tso = 1 << max_tso;
638 resp.tso_caps.supported_qpts |=
639 1 << IB_QPT_RAW_PACKET;
640 resp.response_length += sizeof(resp.tso_caps);
641 }
642 }
643
644 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
645 resp.rss_caps.rx_hash_function =
646 MLX5_RX_HASH_FUNC_TOEPLITZ;
647 resp.rss_caps.rx_hash_fields_mask =
648 MLX5_RX_HASH_SRC_IPV4 |
649 MLX5_RX_HASH_DST_IPV4 |
650 MLX5_RX_HASH_SRC_IPV6 |
651 MLX5_RX_HASH_DST_IPV6 |
652 MLX5_RX_HASH_SRC_PORT_TCP |
653 MLX5_RX_HASH_DST_PORT_TCP |
654 MLX5_RX_HASH_SRC_PORT_UDP |
655 MLX5_RX_HASH_DST_PORT_UDP;
656 resp.response_length += sizeof(resp.rss_caps);
657 }
658 } else {
659 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
660 resp.response_length += sizeof(resp.tso_caps);
661 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
662 resp.response_length += sizeof(resp.rss_caps);
663 }
664
665 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
666 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
667 props->device_cap_flags |= IB_DEVICE_UD_TSO;
668 }
669
670 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
671 MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
672 /* Legacy bit to support old userspace libraries */
673 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
674 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
675 }
676
677 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
678 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
679
680 props->vendor_part_id = mdev->pdev->device;
681 props->hw_ver = mdev->pdev->revision;
682
683 props->max_mr_size = ~0ull;
684 props->page_size_cap = ~(min_page_size - 1);
685 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
686 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
687 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
688 sizeof(struct mlx5_wqe_data_seg);
689 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
690 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
691 sizeof(struct mlx5_wqe_raddr_seg)) /
692 sizeof(struct mlx5_wqe_data_seg);
693 props->max_sge = min(max_rq_sg, max_sq_sg);
694 props->max_sge_rd = MLX5_MAX_SGE_RD;
695 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
696 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
697 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
698 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
699 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
700 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
701 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
702 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
703 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
704 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
705 props->max_srq_sge = max_rq_sg - 1;
706 props->max_fast_reg_page_list_len =
707 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
708 get_atomic_caps(dev, props);
709 props->masked_atomic_cap = IB_ATOMIC_NONE;
710 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
711 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
712 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
713 props->max_mcast_grp;
714 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
715 props->max_ah = INT_MAX;
716 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
717 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
718
719 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
720 if (MLX5_CAP_GEN(mdev, pg))
721 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
722 props->odp_caps = dev->odp_caps;
723 #endif
724
725 if (MLX5_CAP_GEN(mdev, cd))
726 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
727
728 if (!mlx5_core_is_pf(mdev))
729 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
730
731 if (mlx5_ib_port_link_layer(ibdev, 1) ==
732 IB_LINK_LAYER_ETHERNET) {
733 props->rss_caps.max_rwq_indirection_tables =
734 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
735 props->rss_caps.max_rwq_indirection_table_size =
736 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
737 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
738 props->max_wq_type_rq =
739 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
740 }
741
742 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
743 resp.cqe_comp_caps.max_num =
744 MLX5_CAP_GEN(dev->mdev, cqe_compression) ?
745 MLX5_CAP_GEN(dev->mdev, cqe_compression_max_num) : 0;
746 resp.cqe_comp_caps.supported_format =
747 MLX5_IB_CQE_RES_FORMAT_HASH |
748 MLX5_IB_CQE_RES_FORMAT_CSUM;
749 resp.response_length += sizeof(resp.cqe_comp_caps);
750 }
751
752 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen)) {
753 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
754 MLX5_CAP_GEN(mdev, qos)) {
755 resp.packet_pacing_caps.qp_rate_limit_max =
756 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
757 resp.packet_pacing_caps.qp_rate_limit_min =
758 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
759 resp.packet_pacing_caps.supported_qpts |=
760 1 << IB_QPT_RAW_PACKET;
761 }
762 resp.response_length += sizeof(resp.packet_pacing_caps);
763 }
764
765 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
766 uhw->outlen)) {
767 resp.mlx5_ib_support_multi_pkt_send_wqes =
768 MLX5_CAP_ETH(mdev, multi_pkt_send_wqe);
769 resp.response_length +=
770 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
771 }
772
773 if (field_avail(typeof(resp), reserved, uhw->outlen))
774 resp.response_length += sizeof(resp.reserved);
775
776 if (uhw->outlen) {
777 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
778
779 if (err)
780 return err;
781 }
782
783 return 0;
784 }
785
786 enum mlx5_ib_width {
787 MLX5_IB_WIDTH_1X = 1 << 0,
788 MLX5_IB_WIDTH_2X = 1 << 1,
789 MLX5_IB_WIDTH_4X = 1 << 2,
790 MLX5_IB_WIDTH_8X = 1 << 3,
791 MLX5_IB_WIDTH_12X = 1 << 4
792 };
793
794 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
795 u8 *ib_width)
796 {
797 struct mlx5_ib_dev *dev = to_mdev(ibdev);
798 int err = 0;
799
800 if (active_width & MLX5_IB_WIDTH_1X) {
801 *ib_width = IB_WIDTH_1X;
802 } else if (active_width & MLX5_IB_WIDTH_2X) {
803 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
804 (int)active_width);
805 err = -EINVAL;
806 } else if (active_width & MLX5_IB_WIDTH_4X) {
807 *ib_width = IB_WIDTH_4X;
808 } else if (active_width & MLX5_IB_WIDTH_8X) {
809 *ib_width = IB_WIDTH_8X;
810 } else if (active_width & MLX5_IB_WIDTH_12X) {
811 *ib_width = IB_WIDTH_12X;
812 } else {
813 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
814 (int)active_width);
815 err = -EINVAL;
816 }
817
818 return err;
819 }
820
821 static int mlx5_mtu_to_ib_mtu(int mtu)
822 {
823 switch (mtu) {
824 case 256: return 1;
825 case 512: return 2;
826 case 1024: return 3;
827 case 2048: return 4;
828 case 4096: return 5;
829 default:
830 pr_warn("invalid mtu\n");
831 return -1;
832 }
833 }
834
835 enum ib_max_vl_num {
836 __IB_MAX_VL_0 = 1,
837 __IB_MAX_VL_0_1 = 2,
838 __IB_MAX_VL_0_3 = 3,
839 __IB_MAX_VL_0_7 = 4,
840 __IB_MAX_VL_0_14 = 5,
841 };
842
843 enum mlx5_vl_hw_cap {
844 MLX5_VL_HW_0 = 1,
845 MLX5_VL_HW_0_1 = 2,
846 MLX5_VL_HW_0_2 = 3,
847 MLX5_VL_HW_0_3 = 4,
848 MLX5_VL_HW_0_4 = 5,
849 MLX5_VL_HW_0_5 = 6,
850 MLX5_VL_HW_0_6 = 7,
851 MLX5_VL_HW_0_7 = 8,
852 MLX5_VL_HW_0_14 = 15
853 };
854
855 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
856 u8 *max_vl_num)
857 {
858 switch (vl_hw_cap) {
859 case MLX5_VL_HW_0:
860 *max_vl_num = __IB_MAX_VL_0;
861 break;
862 case MLX5_VL_HW_0_1:
863 *max_vl_num = __IB_MAX_VL_0_1;
864 break;
865 case MLX5_VL_HW_0_3:
866 *max_vl_num = __IB_MAX_VL_0_3;
867 break;
868 case MLX5_VL_HW_0_7:
869 *max_vl_num = __IB_MAX_VL_0_7;
870 break;
871 case MLX5_VL_HW_0_14:
872 *max_vl_num = __IB_MAX_VL_0_14;
873 break;
874
875 default:
876 return -EINVAL;
877 }
878
879 return 0;
880 }
881
882 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
883 struct ib_port_attr *props)
884 {
885 struct mlx5_ib_dev *dev = to_mdev(ibdev);
886 struct mlx5_core_dev *mdev = dev->mdev;
887 struct mlx5_hca_vport_context *rep;
888 u16 max_mtu;
889 u16 oper_mtu;
890 int err;
891 u8 ib_link_width_oper;
892 u8 vl_hw_cap;
893
894 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
895 if (!rep) {
896 err = -ENOMEM;
897 goto out;
898 }
899
900 /* props being zeroed by the caller, avoid zeroing it here */
901
902 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
903 if (err)
904 goto out;
905
906 props->lid = rep->lid;
907 props->lmc = rep->lmc;
908 props->sm_lid = rep->sm_lid;
909 props->sm_sl = rep->sm_sl;
910 props->state = rep->vport_state;
911 props->phys_state = rep->port_physical_state;
912 props->port_cap_flags = rep->cap_mask1;
913 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
914 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
915 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
916 props->bad_pkey_cntr = rep->pkey_violation_counter;
917 props->qkey_viol_cntr = rep->qkey_violation_counter;
918 props->subnet_timeout = rep->subnet_timeout;
919 props->init_type_reply = rep->init_type_reply;
920 props->grh_required = rep->grh_required;
921
922 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
923 if (err)
924 goto out;
925
926 err = translate_active_width(ibdev, ib_link_width_oper,
927 &props->active_width);
928 if (err)
929 goto out;
930 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
931 if (err)
932 goto out;
933
934 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
935
936 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
937
938 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
939
940 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
941
942 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
943 if (err)
944 goto out;
945
946 err = translate_max_vl_num(ibdev, vl_hw_cap,
947 &props->max_vl_num);
948 out:
949 kfree(rep);
950 return err;
951 }
952
953 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
954 struct ib_port_attr *props)
955 {
956 unsigned int count;
957 int ret;
958
959 switch (mlx5_get_vport_access_method(ibdev)) {
960 case MLX5_VPORT_ACCESS_METHOD_MAD:
961 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
962 break;
963
964 case MLX5_VPORT_ACCESS_METHOD_HCA:
965 ret = mlx5_query_hca_port(ibdev, port, props);
966 break;
967
968 case MLX5_VPORT_ACCESS_METHOD_NIC:
969 ret = mlx5_query_port_roce(ibdev, port, props);
970 break;
971
972 default:
973 ret = -EINVAL;
974 }
975
976 if (!ret && props) {
977 count = mlx5_core_reserved_gids_count(to_mdev(ibdev)->mdev);
978 props->gid_tbl_len -= count;
979 }
980 return ret;
981 }
982
983 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
984 union ib_gid *gid)
985 {
986 struct mlx5_ib_dev *dev = to_mdev(ibdev);
987 struct mlx5_core_dev *mdev = dev->mdev;
988
989 switch (mlx5_get_vport_access_method(ibdev)) {
990 case MLX5_VPORT_ACCESS_METHOD_MAD:
991 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
992
993 case MLX5_VPORT_ACCESS_METHOD_HCA:
994 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
995
996 default:
997 return -EINVAL;
998 }
999
1000 }
1001
1002 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1003 u16 *pkey)
1004 {
1005 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1006 struct mlx5_core_dev *mdev = dev->mdev;
1007
1008 switch (mlx5_get_vport_access_method(ibdev)) {
1009 case MLX5_VPORT_ACCESS_METHOD_MAD:
1010 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1011
1012 case MLX5_VPORT_ACCESS_METHOD_HCA:
1013 case MLX5_VPORT_ACCESS_METHOD_NIC:
1014 return mlx5_query_hca_vport_pkey(mdev, 0, port, 0, index,
1015 pkey);
1016 default:
1017 return -EINVAL;
1018 }
1019 }
1020
1021 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1022 struct ib_device_modify *props)
1023 {
1024 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1025 struct mlx5_reg_node_desc in;
1026 struct mlx5_reg_node_desc out;
1027 int err;
1028
1029 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1030 return -EOPNOTSUPP;
1031
1032 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1033 return 0;
1034
1035 /*
1036 * If possible, pass node desc to FW, so it can generate
1037 * a 144 trap. If cmd fails, just ignore.
1038 */
1039 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1040 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1041 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1042 if (err)
1043 return err;
1044
1045 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1046
1047 return err;
1048 }
1049
1050 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1051 u32 value)
1052 {
1053 struct mlx5_hca_vport_context ctx = {};
1054 int err;
1055
1056 err = mlx5_query_hca_vport_context(dev->mdev, 0,
1057 port_num, 0, &ctx);
1058 if (err)
1059 return err;
1060
1061 if (~ctx.cap_mask1_perm & mask) {
1062 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1063 mask, ctx.cap_mask1_perm);
1064 return -EINVAL;
1065 }
1066
1067 ctx.cap_mask1 = value;
1068 ctx.cap_mask1_perm = mask;
1069 err = mlx5_core_modify_hca_vport_context(dev->mdev, 0,
1070 port_num, 0, &ctx);
1071
1072 return err;
1073 }
1074
1075 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1076 struct ib_port_modify *props)
1077 {
1078 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1079 struct ib_port_attr attr;
1080 u32 tmp;
1081 int err;
1082 u32 change_mask;
1083 u32 value;
1084 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1085 IB_LINK_LAYER_INFINIBAND);
1086
1087 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1088 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1089 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1090 return set_port_caps_atomic(dev, port, change_mask, value);
1091 }
1092
1093 mutex_lock(&dev->cap_mask_mutex);
1094
1095 err = ib_query_port(ibdev, port, &attr);
1096 if (err)
1097 goto out;
1098
1099 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1100 ~props->clr_port_cap_mask;
1101
1102 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1103
1104 out:
1105 mutex_unlock(&dev->cap_mask_mutex);
1106 return err;
1107 }
1108
1109 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1110 {
1111 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1112 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1113 }
1114
1115 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1116 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1117 u32 *num_sys_pages)
1118 {
1119 int uars_per_sys_page;
1120 int bfregs_per_sys_page;
1121 int ref_bfregs = req->total_num_bfregs;
1122
1123 if (req->total_num_bfregs == 0)
1124 return -EINVAL;
1125
1126 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1127 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1128
1129 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1130 return -ENOMEM;
1131
1132 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1133 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1134 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1135 *num_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1136
1137 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1138 return -EINVAL;
1139
1140 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1141 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1142 lib_uar_4k ? "yes" : "no", ref_bfregs,
1143 req->total_num_bfregs, *num_sys_pages);
1144
1145 return 0;
1146 }
1147
1148 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1149 {
1150 struct mlx5_bfreg_info *bfregi;
1151 int err;
1152 int i;
1153
1154 bfregi = &context->bfregi;
1155 for (i = 0; i < bfregi->num_sys_pages; i++) {
1156 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1157 if (err)
1158 goto error;
1159
1160 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1161 }
1162 return 0;
1163
1164 error:
1165 for (--i; i >= 0; i--)
1166 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1167 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1168
1169 return err;
1170 }
1171
1172 static int deallocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1173 {
1174 struct mlx5_bfreg_info *bfregi;
1175 int err;
1176 int i;
1177
1178 bfregi = &context->bfregi;
1179 for (i = 0; i < bfregi->num_sys_pages; i++) {
1180 err = mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1181 if (err) {
1182 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1183 return err;
1184 }
1185 }
1186 return 0;
1187 }
1188
1189 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1190 struct ib_udata *udata)
1191 {
1192 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1193 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1194 struct mlx5_ib_alloc_ucontext_resp resp = {};
1195 struct mlx5_ib_ucontext *context;
1196 struct mlx5_bfreg_info *bfregi;
1197 int ver;
1198 int err;
1199 size_t reqlen;
1200 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1201 max_cqe_version);
1202 bool lib_uar_4k;
1203
1204 if (!dev->ib_active)
1205 return ERR_PTR(-EAGAIN);
1206
1207 if (udata->inlen < sizeof(struct ib_uverbs_cmd_hdr))
1208 return ERR_PTR(-EINVAL);
1209
1210 reqlen = udata->inlen - sizeof(struct ib_uverbs_cmd_hdr);
1211 if (reqlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1212 ver = 0;
1213 else if (reqlen >= min_req_v2)
1214 ver = 2;
1215 else
1216 return ERR_PTR(-EINVAL);
1217
1218 err = ib_copy_from_udata(&req, udata, min(reqlen, sizeof(req)));
1219 if (err)
1220 return ERR_PTR(err);
1221
1222 if (req.flags)
1223 return ERR_PTR(-EINVAL);
1224
1225 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1226 return ERR_PTR(-EOPNOTSUPP);
1227
1228 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1229 MLX5_NON_FP_BFREGS_PER_UAR);
1230 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1231 return ERR_PTR(-EINVAL);
1232
1233 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1234 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1235 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1236 resp.cache_line_size = cache_line_size();
1237 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1238 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1239 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1240 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1241 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1242 resp.cqe_version = min_t(__u8,
1243 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1244 req.max_cqe_version);
1245 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1246 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1247 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1248 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1249 resp.response_length = min(offsetof(typeof(resp), response_length) +
1250 sizeof(resp.response_length), udata->outlen);
1251
1252 context = kzalloc(sizeof(*context), GFP_KERNEL);
1253 if (!context)
1254 return ERR_PTR(-ENOMEM);
1255
1256 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1257 bfregi = &context->bfregi;
1258
1259 /* updates req->total_num_bfregs */
1260 err = calc_total_bfregs(dev, lib_uar_4k, &req, &bfregi->num_sys_pages);
1261 if (err)
1262 goto out_ctx;
1263
1264 mutex_init(&bfregi->lock);
1265 bfregi->lib_uar_4k = lib_uar_4k;
1266 bfregi->count = kcalloc(req.total_num_bfregs, sizeof(*bfregi->count),
1267 GFP_KERNEL);
1268 if (!bfregi->count) {
1269 err = -ENOMEM;
1270 goto out_ctx;
1271 }
1272
1273 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1274 sizeof(*bfregi->sys_pages),
1275 GFP_KERNEL);
1276 if (!bfregi->sys_pages) {
1277 err = -ENOMEM;
1278 goto out_count;
1279 }
1280
1281 err = allocate_uars(dev, context);
1282 if (err)
1283 goto out_sys_pages;
1284
1285 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1286 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1287 #endif
1288
1289 context->upd_xlt_page = __get_free_page(GFP_KERNEL);
1290 if (!context->upd_xlt_page) {
1291 err = -ENOMEM;
1292 goto out_uars;
1293 }
1294 mutex_init(&context->upd_xlt_page_mutex);
1295
1296 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain)) {
1297 err = mlx5_core_alloc_transport_domain(dev->mdev,
1298 &context->tdn);
1299 if (err)
1300 goto out_page;
1301 }
1302
1303 INIT_LIST_HEAD(&context->vma_private_list);
1304 INIT_LIST_HEAD(&context->db_page_list);
1305 mutex_init(&context->db_page_mutex);
1306
1307 resp.tot_bfregs = req.total_num_bfregs;
1308 resp.num_ports = MLX5_CAP_GEN(dev->mdev, num_ports);
1309
1310 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1311 resp.response_length += sizeof(resp.cqe_version);
1312
1313 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1314 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1315 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1316 resp.response_length += sizeof(resp.cmds_supp_uhw);
1317 }
1318
1319 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1320 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1321 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1322 resp.eth_min_inline++;
1323 }
1324 resp.response_length += sizeof(resp.eth_min_inline);
1325 }
1326
1327 /*
1328 * We don't want to expose information from the PCI bar that is located
1329 * after 4096 bytes, so if the arch only supports larger pages, let's
1330 * pretend we don't support reading the HCA's core clock. This is also
1331 * forced by mmap function.
1332 */
1333 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1334 if (PAGE_SIZE <= 4096) {
1335 resp.comp_mask |=
1336 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1337 resp.hca_core_clock_offset =
1338 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1339 }
1340 resp.response_length += sizeof(resp.hca_core_clock_offset) +
1341 sizeof(resp.reserved2);
1342 }
1343
1344 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1345 resp.response_length += sizeof(resp.log_uar_size);
1346
1347 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1348 resp.response_length += sizeof(resp.num_uars_per_page);
1349
1350 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1351 if (err)
1352 goto out_td;
1353
1354 bfregi->ver = ver;
1355 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1356 context->cqe_version = resp.cqe_version;
1357 context->lib_caps = req.lib_caps;
1358 print_lib_caps(dev, context->lib_caps);
1359
1360 return &context->ibucontext;
1361
1362 out_td:
1363 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1364 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1365
1366 out_page:
1367 free_page(context->upd_xlt_page);
1368
1369 out_uars:
1370 deallocate_uars(dev, context);
1371
1372 out_sys_pages:
1373 kfree(bfregi->sys_pages);
1374
1375 out_count:
1376 kfree(bfregi->count);
1377
1378 out_ctx:
1379 kfree(context);
1380
1381 return ERR_PTR(err);
1382 }
1383
1384 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1385 {
1386 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1387 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1388 struct mlx5_bfreg_info *bfregi;
1389
1390 bfregi = &context->bfregi;
1391 if (MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1392 mlx5_core_dealloc_transport_domain(dev->mdev, context->tdn);
1393
1394 free_page(context->upd_xlt_page);
1395 deallocate_uars(dev, context);
1396 kfree(bfregi->sys_pages);
1397 kfree(bfregi->count);
1398 kfree(context);
1399
1400 return 0;
1401 }
1402
1403 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1404 struct mlx5_bfreg_info *bfregi,
1405 int idx)
1406 {
1407 int fw_uars_per_page;
1408
1409 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1410
1411 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) +
1412 bfregi->sys_pages[idx] / fw_uars_per_page;
1413 }
1414
1415 static int get_command(unsigned long offset)
1416 {
1417 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1418 }
1419
1420 static int get_arg(unsigned long offset)
1421 {
1422 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1423 }
1424
1425 static int get_index(unsigned long offset)
1426 {
1427 return get_arg(offset);
1428 }
1429
1430 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1431 {
1432 /* vma_open is called when a new VMA is created on top of our VMA. This
1433 * is done through either mremap flow or split_vma (usually due to
1434 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1435 * as this VMA is strongly hardware related. Therefore we set the
1436 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1437 * calling us again and trying to do incorrect actions. We assume that
1438 * the original VMA size is exactly a single page, and therefore all
1439 * "splitting" operation will not happen to it.
1440 */
1441 area->vm_ops = NULL;
1442 }
1443
1444 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1445 {
1446 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1447
1448 /* It's guaranteed that all VMAs opened on a FD are closed before the
1449 * file itself is closed, therefore no sync is needed with the regular
1450 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1451 * However need a sync with accessing the vma as part of
1452 * mlx5_ib_disassociate_ucontext.
1453 * The close operation is usually called under mm->mmap_sem except when
1454 * process is exiting.
1455 * The exiting case is handled explicitly as part of
1456 * mlx5_ib_disassociate_ucontext.
1457 */
1458 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1459
1460 /* setting the vma context pointer to null in the mlx5_ib driver's
1461 * private data, to protect a race condition in
1462 * mlx5_ib_disassociate_ucontext().
1463 */
1464 mlx5_ib_vma_priv_data->vma = NULL;
1465 list_del(&mlx5_ib_vma_priv_data->list);
1466 kfree(mlx5_ib_vma_priv_data);
1467 }
1468
1469 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1470 .open = mlx5_ib_vma_open,
1471 .close = mlx5_ib_vma_close
1472 };
1473
1474 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1475 struct mlx5_ib_ucontext *ctx)
1476 {
1477 struct mlx5_ib_vma_private_data *vma_prv;
1478 struct list_head *vma_head = &ctx->vma_private_list;
1479
1480 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1481 if (!vma_prv)
1482 return -ENOMEM;
1483
1484 vma_prv->vma = vma;
1485 vma->vm_private_data = vma_prv;
1486 vma->vm_ops = &mlx5_ib_vm_ops;
1487
1488 list_add(&vma_prv->list, vma_head);
1489
1490 return 0;
1491 }
1492
1493 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1494 {
1495 int ret;
1496 struct vm_area_struct *vma;
1497 struct mlx5_ib_vma_private_data *vma_private, *n;
1498 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1499 struct task_struct *owning_process = NULL;
1500 struct mm_struct *owning_mm = NULL;
1501
1502 owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
1503 if (!owning_process)
1504 return;
1505
1506 owning_mm = get_task_mm(owning_process);
1507 if (!owning_mm) {
1508 pr_info("no mm, disassociate ucontext is pending task termination\n");
1509 while (1) {
1510 put_task_struct(owning_process);
1511 usleep_range(1000, 2000);
1512 owning_process = get_pid_task(ibcontext->tgid,
1513 PIDTYPE_PID);
1514 if (!owning_process ||
1515 owning_process->state == TASK_DEAD) {
1516 pr_info("disassociate ucontext done, task was terminated\n");
1517 /* in case task was dead need to release the
1518 * task struct.
1519 */
1520 if (owning_process)
1521 put_task_struct(owning_process);
1522 return;
1523 }
1524 }
1525 }
1526
1527 /* need to protect from a race on closing the vma as part of
1528 * mlx5_ib_vma_close.
1529 */
1530 down_write(&owning_mm->mmap_sem);
1531 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1532 list) {
1533 vma = vma_private->vma;
1534 ret = zap_vma_ptes(vma, vma->vm_start,
1535 PAGE_SIZE);
1536 WARN_ONCE(ret, "%s: zap_vma_ptes failed", __func__);
1537 /* context going to be destroyed, should
1538 * not access ops any more.
1539 */
1540 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1541 vma->vm_ops = NULL;
1542 list_del(&vma_private->list);
1543 kfree(vma_private);
1544 }
1545 up_write(&owning_mm->mmap_sem);
1546 mmput(owning_mm);
1547 put_task_struct(owning_process);
1548 }
1549
1550 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1551 {
1552 switch (cmd) {
1553 case MLX5_IB_MMAP_WC_PAGE:
1554 return "WC";
1555 case MLX5_IB_MMAP_REGULAR_PAGE:
1556 return "best effort WC";
1557 case MLX5_IB_MMAP_NC_PAGE:
1558 return "NC";
1559 default:
1560 return NULL;
1561 }
1562 }
1563
1564 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1565 struct vm_area_struct *vma,
1566 struct mlx5_ib_ucontext *context)
1567 {
1568 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1569 int err;
1570 unsigned long idx;
1571 phys_addr_t pfn, pa;
1572 pgprot_t prot;
1573 int uars_per_page;
1574
1575 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1576 return -EINVAL;
1577
1578 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
1579 idx = get_index(vma->vm_pgoff);
1580 if (idx % uars_per_page ||
1581 idx * uars_per_page >= bfregi->num_sys_pages) {
1582 mlx5_ib_warn(dev, "invalid uar index %lu\n", idx);
1583 return -EINVAL;
1584 }
1585
1586 switch (cmd) {
1587 case MLX5_IB_MMAP_WC_PAGE:
1588 /* Some architectures don't support WC memory */
1589 #if defined(CONFIG_X86)
1590 if (!pat_enabled())
1591 return -EPERM;
1592 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1593 return -EPERM;
1594 #endif
1595 /* fall through */
1596 case MLX5_IB_MMAP_REGULAR_PAGE:
1597 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1598 prot = pgprot_writecombine(vma->vm_page_prot);
1599 break;
1600 case MLX5_IB_MMAP_NC_PAGE:
1601 prot = pgprot_noncached(vma->vm_page_prot);
1602 break;
1603 default:
1604 return -EINVAL;
1605 }
1606
1607 pfn = uar_index2pfn(dev, bfregi, idx);
1608 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
1609
1610 vma->vm_page_prot = prot;
1611 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
1612 PAGE_SIZE, vma->vm_page_prot);
1613 if (err) {
1614 mlx5_ib_err(dev, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1615 err, vma->vm_start, &pfn, mmap_cmd2str(cmd));
1616 return -EAGAIN;
1617 }
1618
1619 pa = pfn << PAGE_SHIFT;
1620 mlx5_ib_dbg(dev, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd),
1621 vma->vm_start, &pa);
1622
1623 return mlx5_ib_set_vma_data(vma, context);
1624 }
1625
1626 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
1627 {
1628 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1629 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1630 unsigned long command;
1631 phys_addr_t pfn;
1632
1633 command = get_command(vma->vm_pgoff);
1634 switch (command) {
1635 case MLX5_IB_MMAP_WC_PAGE:
1636 case MLX5_IB_MMAP_NC_PAGE:
1637 case MLX5_IB_MMAP_REGULAR_PAGE:
1638 return uar_mmap(dev, command, vma, context);
1639
1640 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
1641 return -ENOSYS;
1642
1643 case MLX5_IB_MMAP_CORE_CLOCK:
1644 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1645 return -EINVAL;
1646
1647 if (vma->vm_flags & VM_WRITE)
1648 return -EPERM;
1649
1650 /* Don't expose to user-space information it shouldn't have */
1651 if (PAGE_SIZE > 4096)
1652 return -EOPNOTSUPP;
1653
1654 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
1655 pfn = (dev->mdev->iseg_base +
1656 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
1657 PAGE_SHIFT;
1658 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
1659 PAGE_SIZE, vma->vm_page_prot))
1660 return -EAGAIN;
1661
1662 mlx5_ib_dbg(dev, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1663 vma->vm_start,
1664 (unsigned long long)pfn << PAGE_SHIFT);
1665 break;
1666
1667 default:
1668 return -EINVAL;
1669 }
1670
1671 return 0;
1672 }
1673
1674 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
1675 struct ib_ucontext *context,
1676 struct ib_udata *udata)
1677 {
1678 struct mlx5_ib_alloc_pd_resp resp;
1679 struct mlx5_ib_pd *pd;
1680 int err;
1681
1682 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
1683 if (!pd)
1684 return ERR_PTR(-ENOMEM);
1685
1686 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
1687 if (err) {
1688 kfree(pd);
1689 return ERR_PTR(err);
1690 }
1691
1692 if (context) {
1693 resp.pdn = pd->pdn;
1694 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
1695 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
1696 kfree(pd);
1697 return ERR_PTR(-EFAULT);
1698 }
1699 }
1700
1701 return &pd->ibpd;
1702 }
1703
1704 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
1705 {
1706 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
1707 struct mlx5_ib_pd *mpd = to_mpd(pd);
1708
1709 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
1710 kfree(mpd);
1711
1712 return 0;
1713 }
1714
1715 enum {
1716 MATCH_CRITERIA_ENABLE_OUTER_BIT,
1717 MATCH_CRITERIA_ENABLE_MISC_BIT,
1718 MATCH_CRITERIA_ENABLE_INNER_BIT
1719 };
1720
1721 #define HEADER_IS_ZERO(match_criteria, headers) \
1722 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1723 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1724
1725 static u8 get_match_criteria_enable(u32 *match_criteria)
1726 {
1727 u8 match_criteria_enable;
1728
1729 match_criteria_enable =
1730 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
1731 MATCH_CRITERIA_ENABLE_OUTER_BIT;
1732 match_criteria_enable |=
1733 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
1734 MATCH_CRITERIA_ENABLE_MISC_BIT;
1735 match_criteria_enable |=
1736 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
1737 MATCH_CRITERIA_ENABLE_INNER_BIT;
1738
1739 return match_criteria_enable;
1740 }
1741
1742 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
1743 {
1744 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
1745 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
1746 }
1747
1748 static void set_flow_label(void *misc_c, void *misc_v, u8 mask, u8 val,
1749 bool inner)
1750 {
1751 if (inner) {
1752 MLX5_SET(fte_match_set_misc,
1753 misc_c, inner_ipv6_flow_label, mask);
1754 MLX5_SET(fte_match_set_misc,
1755 misc_v, inner_ipv6_flow_label, val);
1756 } else {
1757 MLX5_SET(fte_match_set_misc,
1758 misc_c, outer_ipv6_flow_label, mask);
1759 MLX5_SET(fte_match_set_misc,
1760 misc_v, outer_ipv6_flow_label, val);
1761 }
1762 }
1763
1764 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
1765 {
1766 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
1767 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
1768 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
1769 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
1770 }
1771
1772 #define LAST_ETH_FIELD vlan_tag
1773 #define LAST_IB_FIELD sl
1774 #define LAST_IPV4_FIELD tos
1775 #define LAST_IPV6_FIELD traffic_class
1776 #define LAST_TCP_UDP_FIELD src_port
1777 #define LAST_TUNNEL_FIELD tunnel_id
1778 #define LAST_FLOW_TAG_FIELD tag_id
1779 #define LAST_DROP_FIELD size
1780
1781 /* Field is the last supported field */
1782 #define FIELDS_NOT_SUPPORTED(filter, field)\
1783 memchr_inv((void *)&filter.field +\
1784 sizeof(filter.field), 0,\
1785 sizeof(filter) -\
1786 offsetof(typeof(filter), field) -\
1787 sizeof(filter.field))
1788
1789 #define IPV4_VERSION 4
1790 #define IPV6_VERSION 6
1791 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
1792 u32 *match_v, const union ib_flow_spec *ib_spec,
1793 u32 *tag_id, bool *is_drop)
1794 {
1795 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
1796 misc_parameters);
1797 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
1798 misc_parameters);
1799 void *headers_c;
1800 void *headers_v;
1801 int match_ipv;
1802
1803 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
1804 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1805 inner_headers);
1806 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1807 inner_headers);
1808 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1809 ft_field_support.inner_ip_version);
1810 } else {
1811 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
1812 outer_headers);
1813 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
1814 outer_headers);
1815 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
1816 ft_field_support.outer_ip_version);
1817 }
1818
1819 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
1820 case IB_FLOW_SPEC_ETH:
1821 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
1822 return -EOPNOTSUPP;
1823
1824 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1825 dmac_47_16),
1826 ib_spec->eth.mask.dst_mac);
1827 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1828 dmac_47_16),
1829 ib_spec->eth.val.dst_mac);
1830
1831 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1832 smac_47_16),
1833 ib_spec->eth.mask.src_mac);
1834 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1835 smac_47_16),
1836 ib_spec->eth.val.src_mac);
1837
1838 if (ib_spec->eth.mask.vlan_tag) {
1839 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1840 cvlan_tag, 1);
1841 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1842 cvlan_tag, 1);
1843
1844 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1845 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
1846 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1847 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
1848
1849 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1850 first_cfi,
1851 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
1852 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1853 first_cfi,
1854 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
1855
1856 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1857 first_prio,
1858 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
1859 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1860 first_prio,
1861 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
1862 }
1863 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1864 ethertype, ntohs(ib_spec->eth.mask.ether_type));
1865 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1866 ethertype, ntohs(ib_spec->eth.val.ether_type));
1867 break;
1868 case IB_FLOW_SPEC_IPV4:
1869 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
1870 return -EOPNOTSUPP;
1871
1872 if (match_ipv) {
1873 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1874 ip_version, 0xf);
1875 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1876 ip_version, IPV4_VERSION);
1877 } else {
1878 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1879 ethertype, 0xffff);
1880 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1881 ethertype, ETH_P_IP);
1882 }
1883
1884 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1885 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1886 &ib_spec->ipv4.mask.src_ip,
1887 sizeof(ib_spec->ipv4.mask.src_ip));
1888 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1889 src_ipv4_src_ipv6.ipv4_layout.ipv4),
1890 &ib_spec->ipv4.val.src_ip,
1891 sizeof(ib_spec->ipv4.val.src_ip));
1892 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1893 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1894 &ib_spec->ipv4.mask.dst_ip,
1895 sizeof(ib_spec->ipv4.mask.dst_ip));
1896 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1897 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
1898 &ib_spec->ipv4.val.dst_ip,
1899 sizeof(ib_spec->ipv4.val.dst_ip));
1900
1901 set_tos(headers_c, headers_v,
1902 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
1903
1904 set_proto(headers_c, headers_v,
1905 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
1906 break;
1907 case IB_FLOW_SPEC_IPV6:
1908 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
1909 return -EOPNOTSUPP;
1910
1911 if (match_ipv) {
1912 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1913 ip_version, 0xf);
1914 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1915 ip_version, IPV6_VERSION);
1916 } else {
1917 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
1918 ethertype, 0xffff);
1919 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
1920 ethertype, ETH_P_IPV6);
1921 }
1922
1923 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1924 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1925 &ib_spec->ipv6.mask.src_ip,
1926 sizeof(ib_spec->ipv6.mask.src_ip));
1927 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1928 src_ipv4_src_ipv6.ipv6_layout.ipv6),
1929 &ib_spec->ipv6.val.src_ip,
1930 sizeof(ib_spec->ipv6.val.src_ip));
1931 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
1932 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1933 &ib_spec->ipv6.mask.dst_ip,
1934 sizeof(ib_spec->ipv6.mask.dst_ip));
1935 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
1936 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
1937 &ib_spec->ipv6.val.dst_ip,
1938 sizeof(ib_spec->ipv6.val.dst_ip));
1939
1940 set_tos(headers_c, headers_v,
1941 ib_spec->ipv6.mask.traffic_class,
1942 ib_spec->ipv6.val.traffic_class);
1943
1944 set_proto(headers_c, headers_v,
1945 ib_spec->ipv6.mask.next_hdr,
1946 ib_spec->ipv6.val.next_hdr);
1947
1948 set_flow_label(misc_params_c, misc_params_v,
1949 ntohl(ib_spec->ipv6.mask.flow_label),
1950 ntohl(ib_spec->ipv6.val.flow_label),
1951 ib_spec->type & IB_FLOW_SPEC_INNER);
1952
1953 break;
1954 case IB_FLOW_SPEC_TCP:
1955 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1956 LAST_TCP_UDP_FIELD))
1957 return -EOPNOTSUPP;
1958
1959 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1960 0xff);
1961 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1962 IPPROTO_TCP);
1963
1964 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
1965 ntohs(ib_spec->tcp_udp.mask.src_port));
1966 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
1967 ntohs(ib_spec->tcp_udp.val.src_port));
1968
1969 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
1970 ntohs(ib_spec->tcp_udp.mask.dst_port));
1971 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
1972 ntohs(ib_spec->tcp_udp.val.dst_port));
1973 break;
1974 case IB_FLOW_SPEC_UDP:
1975 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
1976 LAST_TCP_UDP_FIELD))
1977 return -EOPNOTSUPP;
1978
1979 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
1980 0xff);
1981 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
1982 IPPROTO_UDP);
1983
1984 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
1985 ntohs(ib_spec->tcp_udp.mask.src_port));
1986 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
1987 ntohs(ib_spec->tcp_udp.val.src_port));
1988
1989 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
1990 ntohs(ib_spec->tcp_udp.mask.dst_port));
1991 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
1992 ntohs(ib_spec->tcp_udp.val.dst_port));
1993 break;
1994 case IB_FLOW_SPEC_VXLAN_TUNNEL:
1995 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
1996 LAST_TUNNEL_FIELD))
1997 return -EOPNOTSUPP;
1998
1999 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2000 ntohl(ib_spec->tunnel.mask.tunnel_id));
2001 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2002 ntohl(ib_spec->tunnel.val.tunnel_id));
2003 break;
2004 case IB_FLOW_SPEC_ACTION_TAG:
2005 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2006 LAST_FLOW_TAG_FIELD))
2007 return -EOPNOTSUPP;
2008 if (ib_spec->flow_tag.tag_id >= BIT(24))
2009 return -EINVAL;
2010
2011 *tag_id = ib_spec->flow_tag.tag_id;
2012 break;
2013 case IB_FLOW_SPEC_ACTION_DROP:
2014 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2015 LAST_DROP_FIELD))
2016 return -EOPNOTSUPP;
2017 *is_drop = true;
2018 break;
2019 default:
2020 return -EINVAL;
2021 }
2022
2023 return 0;
2024 }
2025
2026 /* If a flow could catch both multicast and unicast packets,
2027 * it won't fall into the multicast flow steering table and this rule
2028 * could steal other multicast packets.
2029 */
2030 static bool flow_is_multicast_only(struct ib_flow_attr *ib_attr)
2031 {
2032 struct ib_flow_spec_eth *eth_spec;
2033
2034 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2035 ib_attr->size < sizeof(struct ib_flow_attr) +
2036 sizeof(struct ib_flow_spec_eth) ||
2037 ib_attr->num_of_specs < 1)
2038 return false;
2039
2040 eth_spec = (struct ib_flow_spec_eth *)(ib_attr + 1);
2041 if (eth_spec->type != IB_FLOW_SPEC_ETH ||
2042 eth_spec->size != sizeof(*eth_spec))
2043 return false;
2044
2045 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2046 is_multicast_ether_addr(eth_spec->val.dst_mac);
2047 }
2048
2049 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2050 const struct ib_flow_attr *flow_attr,
2051 bool check_inner)
2052 {
2053 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2054 int match_ipv = check_inner ?
2055 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2056 ft_field_support.inner_ip_version) :
2057 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2058 ft_field_support.outer_ip_version);
2059 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2060 bool ipv4_spec_valid, ipv6_spec_valid;
2061 unsigned int ip_spec_type = 0;
2062 bool has_ethertype = false;
2063 unsigned int spec_index;
2064 bool mask_valid = true;
2065 u16 eth_type = 0;
2066 bool type_valid;
2067
2068 /* Validate that ethertype is correct */
2069 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2070 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2071 ib_spec->eth.mask.ether_type) {
2072 mask_valid = (ib_spec->eth.mask.ether_type ==
2073 htons(0xffff));
2074 has_ethertype = true;
2075 eth_type = ntohs(ib_spec->eth.val.ether_type);
2076 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2077 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2078 ip_spec_type = ib_spec->type;
2079 }
2080 ib_spec = (void *)ib_spec + ib_spec->size;
2081 }
2082
2083 type_valid = (!has_ethertype) || (!ip_spec_type);
2084 if (!type_valid && mask_valid) {
2085 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2086 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2087 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2088 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2089
2090 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2091 (((eth_type == ETH_P_MPLS_UC) ||
2092 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2093 }
2094
2095 return type_valid;
2096 }
2097
2098 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2099 const struct ib_flow_attr *flow_attr)
2100 {
2101 return is_valid_ethertype(mdev, flow_attr, false) &&
2102 is_valid_ethertype(mdev, flow_attr, true);
2103 }
2104
2105 static void put_flow_table(struct mlx5_ib_dev *dev,
2106 struct mlx5_ib_flow_prio *prio, bool ft_added)
2107 {
2108 prio->refcount -= !!ft_added;
2109 if (!prio->refcount) {
2110 mlx5_destroy_flow_table(prio->flow_table);
2111 prio->flow_table = NULL;
2112 }
2113 }
2114
2115 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2116 {
2117 struct mlx5_ib_dev *dev = to_mdev(flow_id->qp->device);
2118 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2119 struct mlx5_ib_flow_handler,
2120 ibflow);
2121 struct mlx5_ib_flow_handler *iter, *tmp;
2122
2123 mutex_lock(&dev->flow_db.lock);
2124
2125 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2126 mlx5_del_flow_rules(iter->rule);
2127 put_flow_table(dev, iter->prio, true);
2128 list_del(&iter->list);
2129 kfree(iter);
2130 }
2131
2132 mlx5_del_flow_rules(handler->rule);
2133 put_flow_table(dev, handler->prio, true);
2134 mutex_unlock(&dev->flow_db.lock);
2135
2136 kfree(handler);
2137
2138 return 0;
2139 }
2140
2141 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2142 {
2143 priority *= 2;
2144 if (!dont_trap)
2145 priority++;
2146 return priority;
2147 }
2148
2149 enum flow_table_type {
2150 MLX5_IB_FT_RX,
2151 MLX5_IB_FT_TX
2152 };
2153
2154 #define MLX5_FS_MAX_TYPES 6
2155 #define MLX5_FS_MAX_ENTRIES BIT(16)
2156 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
2157 struct ib_flow_attr *flow_attr,
2158 enum flow_table_type ft_type)
2159 {
2160 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
2161 struct mlx5_flow_namespace *ns = NULL;
2162 struct mlx5_ib_flow_prio *prio;
2163 struct mlx5_flow_table *ft;
2164 int max_table_size;
2165 int num_entries;
2166 int num_groups;
2167 int priority;
2168 int err = 0;
2169
2170 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
2171 log_max_ft_size));
2172 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2173 if (flow_is_multicast_only(flow_attr) &&
2174 !dont_trap)
2175 priority = MLX5_IB_FLOW_MCAST_PRIO;
2176 else
2177 priority = ib_prio_to_core_prio(flow_attr->priority,
2178 dont_trap);
2179 ns = mlx5_get_flow_namespace(dev->mdev,
2180 MLX5_FLOW_NAMESPACE_BYPASS);
2181 num_entries = MLX5_FS_MAX_ENTRIES;
2182 num_groups = MLX5_FS_MAX_TYPES;
2183 prio = &dev->flow_db.prios[priority];
2184 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2185 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2186 ns = mlx5_get_flow_namespace(dev->mdev,
2187 MLX5_FLOW_NAMESPACE_LEFTOVERS);
2188 build_leftovers_ft_param(&priority,
2189 &num_entries,
2190 &num_groups);
2191 prio = &dev->flow_db.prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
2192 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2193 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
2194 allow_sniffer_and_nic_rx_shared_tir))
2195 return ERR_PTR(-ENOTSUPP);
2196
2197 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
2198 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
2199 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
2200
2201 prio = &dev->flow_db.sniffer[ft_type];
2202 priority = 0;
2203 num_entries = 1;
2204 num_groups = 1;
2205 }
2206
2207 if (!ns)
2208 return ERR_PTR(-ENOTSUPP);
2209
2210 if (num_entries > max_table_size)
2211 return ERR_PTR(-ENOMEM);
2212
2213 ft = prio->flow_table;
2214 if (!ft) {
2215 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
2216 num_entries,
2217 num_groups,
2218 0, 0);
2219
2220 if (!IS_ERR(ft)) {
2221 prio->refcount = 0;
2222 prio->flow_table = ft;
2223 } else {
2224 err = PTR_ERR(ft);
2225 }
2226 }
2227
2228 return err ? ERR_PTR(err) : prio;
2229 }
2230
2231 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
2232 struct mlx5_ib_flow_prio *ft_prio,
2233 const struct ib_flow_attr *flow_attr,
2234 struct mlx5_flow_destination *dst)
2235 {
2236 struct mlx5_flow_table *ft = ft_prio->flow_table;
2237 struct mlx5_ib_flow_handler *handler;
2238 struct mlx5_flow_act flow_act = {0};
2239 struct mlx5_flow_spec *spec;
2240 struct mlx5_flow_destination *rule_dst = dst;
2241 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
2242 unsigned int spec_index;
2243 u32 flow_tag = MLX5_FS_DEFAULT_FLOW_TAG;
2244 bool is_drop = false;
2245 int err = 0;
2246 int dest_num = 1;
2247
2248 if (!is_valid_attr(dev->mdev, flow_attr))
2249 return ERR_PTR(-EINVAL);
2250
2251 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
2252 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
2253 if (!handler || !spec) {
2254 err = -ENOMEM;
2255 goto free;
2256 }
2257
2258 INIT_LIST_HEAD(&handler->list);
2259
2260 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2261 err = parse_flow_attr(dev->mdev, spec->match_criteria,
2262 spec->match_value,
2263 ib_flow, &flow_tag, &is_drop);
2264 if (err < 0)
2265 goto free;
2266
2267 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
2268 }
2269
2270 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
2271 if (is_drop) {
2272 flow_act.action = MLX5_FLOW_CONTEXT_ACTION_DROP;
2273 rule_dst = NULL;
2274 dest_num = 0;
2275 } else {
2276 flow_act.action = dst ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
2277 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
2278 }
2279
2280 if (flow_tag != MLX5_FS_DEFAULT_FLOW_TAG &&
2281 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2282 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
2283 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2284 flow_tag, flow_attr->type);
2285 err = -EINVAL;
2286 goto free;
2287 }
2288 flow_act.flow_tag = flow_tag;
2289 handler->rule = mlx5_add_flow_rules(ft, spec,
2290 &flow_act,
2291 rule_dst, dest_num);
2292
2293 if (IS_ERR(handler->rule)) {
2294 err = PTR_ERR(handler->rule);
2295 goto free;
2296 }
2297
2298 ft_prio->refcount++;
2299 handler->prio = ft_prio;
2300
2301 ft_prio->flow_table = ft;
2302 free:
2303 if (err)
2304 kfree(handler);
2305 kvfree(spec);
2306 return err ? ERR_PTR(err) : handler;
2307 }
2308
2309 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
2310 struct mlx5_ib_flow_prio *ft_prio,
2311 struct ib_flow_attr *flow_attr,
2312 struct mlx5_flow_destination *dst)
2313 {
2314 struct mlx5_ib_flow_handler *handler_dst = NULL;
2315 struct mlx5_ib_flow_handler *handler = NULL;
2316
2317 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
2318 if (!IS_ERR(handler)) {
2319 handler_dst = create_flow_rule(dev, ft_prio,
2320 flow_attr, dst);
2321 if (IS_ERR(handler_dst)) {
2322 mlx5_del_flow_rules(handler->rule);
2323 ft_prio->refcount--;
2324 kfree(handler);
2325 handler = handler_dst;
2326 } else {
2327 list_add(&handler_dst->list, &handler->list);
2328 }
2329 }
2330
2331 return handler;
2332 }
2333 enum {
2334 LEFTOVERS_MC,
2335 LEFTOVERS_UC,
2336 };
2337
2338 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
2339 struct mlx5_ib_flow_prio *ft_prio,
2340 struct ib_flow_attr *flow_attr,
2341 struct mlx5_flow_destination *dst)
2342 {
2343 struct mlx5_ib_flow_handler *handler_ucast = NULL;
2344 struct mlx5_ib_flow_handler *handler = NULL;
2345
2346 static struct {
2347 struct ib_flow_attr flow_attr;
2348 struct ib_flow_spec_eth eth_flow;
2349 } leftovers_specs[] = {
2350 [LEFTOVERS_MC] = {
2351 .flow_attr = {
2352 .num_of_specs = 1,
2353 .size = sizeof(leftovers_specs[0])
2354 },
2355 .eth_flow = {
2356 .type = IB_FLOW_SPEC_ETH,
2357 .size = sizeof(struct ib_flow_spec_eth),
2358 .mask = {.dst_mac = {0x1} },
2359 .val = {.dst_mac = {0x1} }
2360 }
2361 },
2362 [LEFTOVERS_UC] = {
2363 .flow_attr = {
2364 .num_of_specs = 1,
2365 .size = sizeof(leftovers_specs[0])
2366 },
2367 .eth_flow = {
2368 .type = IB_FLOW_SPEC_ETH,
2369 .size = sizeof(struct ib_flow_spec_eth),
2370 .mask = {.dst_mac = {0x1} },
2371 .val = {.dst_mac = {} }
2372 }
2373 }
2374 };
2375
2376 handler = create_flow_rule(dev, ft_prio,
2377 &leftovers_specs[LEFTOVERS_MC].flow_attr,
2378 dst);
2379 if (!IS_ERR(handler) &&
2380 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
2381 handler_ucast = create_flow_rule(dev, ft_prio,
2382 &leftovers_specs[LEFTOVERS_UC].flow_attr,
2383 dst);
2384 if (IS_ERR(handler_ucast)) {
2385 mlx5_del_flow_rules(handler->rule);
2386 ft_prio->refcount--;
2387 kfree(handler);
2388 handler = handler_ucast;
2389 } else {
2390 list_add(&handler_ucast->list, &handler->list);
2391 }
2392 }
2393
2394 return handler;
2395 }
2396
2397 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
2398 struct mlx5_ib_flow_prio *ft_rx,
2399 struct mlx5_ib_flow_prio *ft_tx,
2400 struct mlx5_flow_destination *dst)
2401 {
2402 struct mlx5_ib_flow_handler *handler_rx;
2403 struct mlx5_ib_flow_handler *handler_tx;
2404 int err;
2405 static const struct ib_flow_attr flow_attr = {
2406 .num_of_specs = 0,
2407 .size = sizeof(flow_attr)
2408 };
2409
2410 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
2411 if (IS_ERR(handler_rx)) {
2412 err = PTR_ERR(handler_rx);
2413 goto err;
2414 }
2415
2416 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
2417 if (IS_ERR(handler_tx)) {
2418 err = PTR_ERR(handler_tx);
2419 goto err_tx;
2420 }
2421
2422 list_add(&handler_tx->list, &handler_rx->list);
2423
2424 return handler_rx;
2425
2426 err_tx:
2427 mlx5_del_flow_rules(handler_rx->rule);
2428 ft_rx->refcount--;
2429 kfree(handler_rx);
2430 err:
2431 return ERR_PTR(err);
2432 }
2433
2434 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
2435 struct ib_flow_attr *flow_attr,
2436 int domain)
2437 {
2438 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2439 struct mlx5_ib_qp *mqp = to_mqp(qp);
2440 struct mlx5_ib_flow_handler *handler = NULL;
2441 struct mlx5_flow_destination *dst = NULL;
2442 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
2443 struct mlx5_ib_flow_prio *ft_prio;
2444 int err;
2445
2446 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO)
2447 return ERR_PTR(-ENOMEM);
2448
2449 if (domain != IB_FLOW_DOMAIN_USER ||
2450 flow_attr->port > MLX5_CAP_GEN(dev->mdev, num_ports) ||
2451 (flow_attr->flags & ~IB_FLOW_ATTR_FLAGS_DONT_TRAP))
2452 return ERR_PTR(-EINVAL);
2453
2454 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
2455 if (!dst)
2456 return ERR_PTR(-ENOMEM);
2457
2458 mutex_lock(&dev->flow_db.lock);
2459
2460 ft_prio = get_flow_table(dev, flow_attr, MLX5_IB_FT_RX);
2461 if (IS_ERR(ft_prio)) {
2462 err = PTR_ERR(ft_prio);
2463 goto unlock;
2464 }
2465 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2466 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
2467 if (IS_ERR(ft_prio_tx)) {
2468 err = PTR_ERR(ft_prio_tx);
2469 ft_prio_tx = NULL;
2470 goto destroy_ft;
2471 }
2472 }
2473
2474 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
2475 if (mqp->flags & MLX5_IB_QP_RSS)
2476 dst->tir_num = mqp->rss_qp.tirn;
2477 else
2478 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
2479
2480 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
2481 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
2482 handler = create_dont_trap_rule(dev, ft_prio,
2483 flow_attr, dst);
2484 } else {
2485 handler = create_flow_rule(dev, ft_prio, flow_attr,
2486 dst);
2487 }
2488 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
2489 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
2490 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
2491 dst);
2492 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
2493 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
2494 } else {
2495 err = -EINVAL;
2496 goto destroy_ft;
2497 }
2498
2499 if (IS_ERR(handler)) {
2500 err = PTR_ERR(handler);
2501 handler = NULL;
2502 goto destroy_ft;
2503 }
2504
2505 mutex_unlock(&dev->flow_db.lock);
2506 kfree(dst);
2507
2508 return &handler->ibflow;
2509
2510 destroy_ft:
2511 put_flow_table(dev, ft_prio, false);
2512 if (ft_prio_tx)
2513 put_flow_table(dev, ft_prio_tx, false);
2514 unlock:
2515 mutex_unlock(&dev->flow_db.lock);
2516 kfree(dst);
2517 kfree(handler);
2518 return ERR_PTR(err);
2519 }
2520
2521 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2522 {
2523 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2524 int err;
2525
2526 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
2527 if (err)
2528 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
2529 ibqp->qp_num, gid->raw);
2530
2531 return err;
2532 }
2533
2534 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
2535 {
2536 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2537 int err;
2538
2539 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
2540 if (err)
2541 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
2542 ibqp->qp_num, gid->raw);
2543
2544 return err;
2545 }
2546
2547 static int init_node_data(struct mlx5_ib_dev *dev)
2548 {
2549 int err;
2550
2551 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
2552 if (err)
2553 return err;
2554
2555 dev->mdev->rev_id = dev->mdev->pdev->revision;
2556
2557 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
2558 }
2559
2560 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
2561 char *buf)
2562 {
2563 struct mlx5_ib_dev *dev =
2564 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2565
2566 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
2567 }
2568
2569 static ssize_t show_reg_pages(struct device *device,
2570 struct device_attribute *attr, char *buf)
2571 {
2572 struct mlx5_ib_dev *dev =
2573 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2574
2575 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
2576 }
2577
2578 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
2579 char *buf)
2580 {
2581 struct mlx5_ib_dev *dev =
2582 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2583 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
2584 }
2585
2586 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
2587 char *buf)
2588 {
2589 struct mlx5_ib_dev *dev =
2590 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2591 return sprintf(buf, "%x\n", dev->mdev->rev_id);
2592 }
2593
2594 static ssize_t show_board(struct device *device, struct device_attribute *attr,
2595 char *buf)
2596 {
2597 struct mlx5_ib_dev *dev =
2598 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
2599 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
2600 dev->mdev->board_id);
2601 }
2602
2603 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
2604 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
2605 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
2606 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
2607 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
2608
2609 static struct device_attribute *mlx5_class_attributes[] = {
2610 &dev_attr_hw_rev,
2611 &dev_attr_hca_type,
2612 &dev_attr_board_id,
2613 &dev_attr_fw_pages,
2614 &dev_attr_reg_pages,
2615 };
2616
2617 static void pkey_change_handler(struct work_struct *work)
2618 {
2619 struct mlx5_ib_port_resources *ports =
2620 container_of(work, struct mlx5_ib_port_resources,
2621 pkey_change_work);
2622
2623 mutex_lock(&ports->devr->mutex);
2624 mlx5_ib_gsi_pkey_change(ports->gsi);
2625 mutex_unlock(&ports->devr->mutex);
2626 }
2627
2628 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
2629 {
2630 struct mlx5_ib_qp *mqp;
2631 struct mlx5_ib_cq *send_mcq, *recv_mcq;
2632 struct mlx5_core_cq *mcq;
2633 struct list_head cq_armed_list;
2634 unsigned long flags_qp;
2635 unsigned long flags_cq;
2636 unsigned long flags;
2637
2638 INIT_LIST_HEAD(&cq_armed_list);
2639
2640 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2641 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
2642 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
2643 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
2644 if (mqp->sq.tail != mqp->sq.head) {
2645 send_mcq = to_mcq(mqp->ibqp.send_cq);
2646 spin_lock_irqsave(&send_mcq->lock, flags_cq);
2647 if (send_mcq->mcq.comp &&
2648 mqp->ibqp.send_cq->comp_handler) {
2649 if (!send_mcq->mcq.reset_notify_added) {
2650 send_mcq->mcq.reset_notify_added = 1;
2651 list_add_tail(&send_mcq->mcq.reset_notify,
2652 &cq_armed_list);
2653 }
2654 }
2655 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
2656 }
2657 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
2658 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
2659 /* no handling is needed for SRQ */
2660 if (!mqp->ibqp.srq) {
2661 if (mqp->rq.tail != mqp->rq.head) {
2662 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
2663 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
2664 if (recv_mcq->mcq.comp &&
2665 mqp->ibqp.recv_cq->comp_handler) {
2666 if (!recv_mcq->mcq.reset_notify_added) {
2667 recv_mcq->mcq.reset_notify_added = 1;
2668 list_add_tail(&recv_mcq->mcq.reset_notify,
2669 &cq_armed_list);
2670 }
2671 }
2672 spin_unlock_irqrestore(&recv_mcq->lock,
2673 flags_cq);
2674 }
2675 }
2676 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
2677 }
2678 /*At that point all inflight post send were put to be executed as of we
2679 * lock/unlock above locks Now need to arm all involved CQs.
2680 */
2681 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
2682 mcq->comp(mcq);
2683 }
2684 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
2685 }
2686
2687 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
2688 enum mlx5_dev_event event, unsigned long param)
2689 {
2690 struct mlx5_ib_dev *ibdev = (struct mlx5_ib_dev *)context;
2691 struct ib_event ibev;
2692 bool fatal = false;
2693 u8 port = 0;
2694
2695 switch (event) {
2696 case MLX5_DEV_EVENT_SYS_ERROR:
2697 ibev.event = IB_EVENT_DEVICE_FATAL;
2698 mlx5_ib_handle_internal_error(ibdev);
2699 fatal = true;
2700 break;
2701
2702 case MLX5_DEV_EVENT_PORT_UP:
2703 case MLX5_DEV_EVENT_PORT_DOWN:
2704 case MLX5_DEV_EVENT_PORT_INITIALIZED:
2705 port = (u8)param;
2706
2707 /* In RoCE, port up/down events are handled in
2708 * mlx5_netdev_event().
2709 */
2710 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
2711 IB_LINK_LAYER_ETHERNET)
2712 return;
2713
2714 ibev.event = (event == MLX5_DEV_EVENT_PORT_UP) ?
2715 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
2716 break;
2717
2718 case MLX5_DEV_EVENT_LID_CHANGE:
2719 ibev.event = IB_EVENT_LID_CHANGE;
2720 port = (u8)param;
2721 break;
2722
2723 case MLX5_DEV_EVENT_PKEY_CHANGE:
2724 ibev.event = IB_EVENT_PKEY_CHANGE;
2725 port = (u8)param;
2726
2727 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
2728 break;
2729
2730 case MLX5_DEV_EVENT_GUID_CHANGE:
2731 ibev.event = IB_EVENT_GID_CHANGE;
2732 port = (u8)param;
2733 break;
2734
2735 case MLX5_DEV_EVENT_CLIENT_REREG:
2736 ibev.event = IB_EVENT_CLIENT_REREGISTER;
2737 port = (u8)param;
2738 break;
2739 default:
2740 return;
2741 }
2742
2743 ibev.device = &ibdev->ib_dev;
2744 ibev.element.port_num = port;
2745
2746 if (port < 1 || port > ibdev->num_ports) {
2747 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
2748 return;
2749 }
2750
2751 if (ibdev->ib_active)
2752 ib_dispatch_event(&ibev);
2753
2754 if (fatal)
2755 ibdev->ib_active = false;
2756 }
2757
2758 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
2759 {
2760 struct mlx5_hca_vport_context vport_ctx;
2761 int err;
2762 int port;
2763
2764 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2765 dev->mdev->port_caps[port - 1].has_smi = false;
2766 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
2767 MLX5_CAP_PORT_TYPE_IB) {
2768 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
2769 err = mlx5_query_hca_vport_context(dev->mdev, 0,
2770 port, 0,
2771 &vport_ctx);
2772 if (err) {
2773 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
2774 port, err);
2775 return err;
2776 }
2777 dev->mdev->port_caps[port - 1].has_smi =
2778 vport_ctx.has_smi;
2779 } else {
2780 dev->mdev->port_caps[port - 1].has_smi = true;
2781 }
2782 }
2783 }
2784 return 0;
2785 }
2786
2787 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
2788 {
2789 int port;
2790
2791 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++)
2792 mlx5_query_ext_port_caps(dev, port);
2793 }
2794
2795 static int get_port_caps(struct mlx5_ib_dev *dev)
2796 {
2797 struct ib_device_attr *dprops = NULL;
2798 struct ib_port_attr *pprops = NULL;
2799 int err = -ENOMEM;
2800 int port;
2801 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
2802
2803 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
2804 if (!pprops)
2805 goto out;
2806
2807 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
2808 if (!dprops)
2809 goto out;
2810
2811 err = set_has_smi_cap(dev);
2812 if (err)
2813 goto out;
2814
2815 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
2816 if (err) {
2817 mlx5_ib_warn(dev, "query_device failed %d\n", err);
2818 goto out;
2819 }
2820
2821 for (port = 1; port <= MLX5_CAP_GEN(dev->mdev, num_ports); port++) {
2822 memset(pprops, 0, sizeof(*pprops));
2823 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
2824 if (err) {
2825 mlx5_ib_warn(dev, "query_port %d failed %d\n",
2826 port, err);
2827 break;
2828 }
2829 dev->mdev->port_caps[port - 1].pkey_table_len =
2830 dprops->max_pkeys;
2831 dev->mdev->port_caps[port - 1].gid_table_len =
2832 pprops->gid_tbl_len;
2833 mlx5_ib_dbg(dev, "pkey_table_len %d, gid_table_len %d\n",
2834 dprops->max_pkeys, pprops->gid_tbl_len);
2835 }
2836
2837 out:
2838 kfree(pprops);
2839 kfree(dprops);
2840
2841 return err;
2842 }
2843
2844 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
2845 {
2846 int err;
2847
2848 err = mlx5_mr_cache_cleanup(dev);
2849 if (err)
2850 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
2851
2852 mlx5_ib_destroy_qp(dev->umrc.qp);
2853 ib_free_cq(dev->umrc.cq);
2854 ib_dealloc_pd(dev->umrc.pd);
2855 }
2856
2857 enum {
2858 MAX_UMR_WR = 128,
2859 };
2860
2861 static int create_umr_res(struct mlx5_ib_dev *dev)
2862 {
2863 struct ib_qp_init_attr *init_attr = NULL;
2864 struct ib_qp_attr *attr = NULL;
2865 struct ib_pd *pd;
2866 struct ib_cq *cq;
2867 struct ib_qp *qp;
2868 int ret;
2869
2870 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
2871 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
2872 if (!attr || !init_attr) {
2873 ret = -ENOMEM;
2874 goto error_0;
2875 }
2876
2877 pd = ib_alloc_pd(&dev->ib_dev, 0);
2878 if (IS_ERR(pd)) {
2879 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
2880 ret = PTR_ERR(pd);
2881 goto error_0;
2882 }
2883
2884 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
2885 if (IS_ERR(cq)) {
2886 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
2887 ret = PTR_ERR(cq);
2888 goto error_2;
2889 }
2890
2891 init_attr->send_cq = cq;
2892 init_attr->recv_cq = cq;
2893 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
2894 init_attr->cap.max_send_wr = MAX_UMR_WR;
2895 init_attr->cap.max_send_sge = 1;
2896 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
2897 init_attr->port_num = 1;
2898 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
2899 if (IS_ERR(qp)) {
2900 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
2901 ret = PTR_ERR(qp);
2902 goto error_3;
2903 }
2904 qp->device = &dev->ib_dev;
2905 qp->real_qp = qp;
2906 qp->uobject = NULL;
2907 qp->qp_type = MLX5_IB_QPT_REG_UMR;
2908
2909 attr->qp_state = IB_QPS_INIT;
2910 attr->port_num = 1;
2911 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
2912 IB_QP_PORT, NULL);
2913 if (ret) {
2914 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
2915 goto error_4;
2916 }
2917
2918 memset(attr, 0, sizeof(*attr));
2919 attr->qp_state = IB_QPS_RTR;
2920 attr->path_mtu = IB_MTU_256;
2921
2922 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2923 if (ret) {
2924 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
2925 goto error_4;
2926 }
2927
2928 memset(attr, 0, sizeof(*attr));
2929 attr->qp_state = IB_QPS_RTS;
2930 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
2931 if (ret) {
2932 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
2933 goto error_4;
2934 }
2935
2936 dev->umrc.qp = qp;
2937 dev->umrc.cq = cq;
2938 dev->umrc.pd = pd;
2939
2940 sema_init(&dev->umrc.sem, MAX_UMR_WR);
2941 ret = mlx5_mr_cache_init(dev);
2942 if (ret) {
2943 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
2944 goto error_4;
2945 }
2946
2947 kfree(attr);
2948 kfree(init_attr);
2949
2950 return 0;
2951
2952 error_4:
2953 mlx5_ib_destroy_qp(qp);
2954
2955 error_3:
2956 ib_free_cq(cq);
2957
2958 error_2:
2959 ib_dealloc_pd(pd);
2960
2961 error_0:
2962 kfree(attr);
2963 kfree(init_attr);
2964 return ret;
2965 }
2966
2967 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
2968 {
2969 switch (umr_fence_cap) {
2970 case MLX5_CAP_UMR_FENCE_NONE:
2971 return MLX5_FENCE_MODE_NONE;
2972 case MLX5_CAP_UMR_FENCE_SMALL:
2973 return MLX5_FENCE_MODE_INITIATOR_SMALL;
2974 default:
2975 return MLX5_FENCE_MODE_STRONG_ORDERING;
2976 }
2977 }
2978
2979 static int create_dev_resources(struct mlx5_ib_resources *devr)
2980 {
2981 struct ib_srq_init_attr attr;
2982 struct mlx5_ib_dev *dev;
2983 struct ib_cq_init_attr cq_attr = {.cqe = 1};
2984 int port;
2985 int ret = 0;
2986
2987 dev = container_of(devr, struct mlx5_ib_dev, devr);
2988
2989 mutex_init(&devr->mutex);
2990
2991 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
2992 if (IS_ERR(devr->p0)) {
2993 ret = PTR_ERR(devr->p0);
2994 goto error0;
2995 }
2996 devr->p0->device = &dev->ib_dev;
2997 devr->p0->uobject = NULL;
2998 atomic_set(&devr->p0->usecnt, 0);
2999
3000 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
3001 if (IS_ERR(devr->c0)) {
3002 ret = PTR_ERR(devr->c0);
3003 goto error1;
3004 }
3005 devr->c0->device = &dev->ib_dev;
3006 devr->c0->uobject = NULL;
3007 devr->c0->comp_handler = NULL;
3008 devr->c0->event_handler = NULL;
3009 devr->c0->cq_context = NULL;
3010 atomic_set(&devr->c0->usecnt, 0);
3011
3012 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3013 if (IS_ERR(devr->x0)) {
3014 ret = PTR_ERR(devr->x0);
3015 goto error2;
3016 }
3017 devr->x0->device = &dev->ib_dev;
3018 devr->x0->inode = NULL;
3019 atomic_set(&devr->x0->usecnt, 0);
3020 mutex_init(&devr->x0->tgt_qp_mutex);
3021 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
3022
3023 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
3024 if (IS_ERR(devr->x1)) {
3025 ret = PTR_ERR(devr->x1);
3026 goto error3;
3027 }
3028 devr->x1->device = &dev->ib_dev;
3029 devr->x1->inode = NULL;
3030 atomic_set(&devr->x1->usecnt, 0);
3031 mutex_init(&devr->x1->tgt_qp_mutex);
3032 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
3033
3034 memset(&attr, 0, sizeof(attr));
3035 attr.attr.max_sge = 1;
3036 attr.attr.max_wr = 1;
3037 attr.srq_type = IB_SRQT_XRC;
3038 attr.ext.xrc.cq = devr->c0;
3039 attr.ext.xrc.xrcd = devr->x0;
3040
3041 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3042 if (IS_ERR(devr->s0)) {
3043 ret = PTR_ERR(devr->s0);
3044 goto error4;
3045 }
3046 devr->s0->device = &dev->ib_dev;
3047 devr->s0->pd = devr->p0;
3048 devr->s0->uobject = NULL;
3049 devr->s0->event_handler = NULL;
3050 devr->s0->srq_context = NULL;
3051 devr->s0->srq_type = IB_SRQT_XRC;
3052 devr->s0->ext.xrc.xrcd = devr->x0;
3053 devr->s0->ext.xrc.cq = devr->c0;
3054 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
3055 atomic_inc(&devr->s0->ext.xrc.cq->usecnt);
3056 atomic_inc(&devr->p0->usecnt);
3057 atomic_set(&devr->s0->usecnt, 0);
3058
3059 memset(&attr, 0, sizeof(attr));
3060 attr.attr.max_sge = 1;
3061 attr.attr.max_wr = 1;
3062 attr.srq_type = IB_SRQT_BASIC;
3063 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
3064 if (IS_ERR(devr->s1)) {
3065 ret = PTR_ERR(devr->s1);
3066 goto error5;
3067 }
3068 devr->s1->device = &dev->ib_dev;
3069 devr->s1->pd = devr->p0;
3070 devr->s1->uobject = NULL;
3071 devr->s1->event_handler = NULL;
3072 devr->s1->srq_context = NULL;
3073 devr->s1->srq_type = IB_SRQT_BASIC;
3074 devr->s1->ext.xrc.cq = devr->c0;
3075 atomic_inc(&devr->p0->usecnt);
3076 atomic_set(&devr->s0->usecnt, 0);
3077
3078 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
3079 INIT_WORK(&devr->ports[port].pkey_change_work,
3080 pkey_change_handler);
3081 devr->ports[port].devr = devr;
3082 }
3083
3084 return 0;
3085
3086 error5:
3087 mlx5_ib_destroy_srq(devr->s0);
3088 error4:
3089 mlx5_ib_dealloc_xrcd(devr->x1);
3090 error3:
3091 mlx5_ib_dealloc_xrcd(devr->x0);
3092 error2:
3093 mlx5_ib_destroy_cq(devr->c0);
3094 error1:
3095 mlx5_ib_dealloc_pd(devr->p0);
3096 error0:
3097 return ret;
3098 }
3099
3100 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
3101 {
3102 struct mlx5_ib_dev *dev =
3103 container_of(devr, struct mlx5_ib_dev, devr);
3104 int port;
3105
3106 mlx5_ib_destroy_srq(devr->s1);
3107 mlx5_ib_destroy_srq(devr->s0);
3108 mlx5_ib_dealloc_xrcd(devr->x0);
3109 mlx5_ib_dealloc_xrcd(devr->x1);
3110 mlx5_ib_destroy_cq(devr->c0);
3111 mlx5_ib_dealloc_pd(devr->p0);
3112
3113 /* Make sure no change P_Key work items are still executing */
3114 for (port = 0; port < dev->num_ports; ++port)
3115 cancel_work_sync(&devr->ports[port].pkey_change_work);
3116 }
3117
3118 static u32 get_core_cap_flags(struct ib_device *ibdev)
3119 {
3120 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3121 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
3122 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
3123 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
3124 u32 ret = 0;
3125
3126 if (ll == IB_LINK_LAYER_INFINIBAND)
3127 return RDMA_CORE_PORT_IBA_IB;
3128
3129 ret = RDMA_CORE_PORT_RAW_PACKET;
3130
3131 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
3132 return ret;
3133
3134 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
3135 return ret;
3136
3137 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
3138 ret |= RDMA_CORE_PORT_IBA_ROCE;
3139
3140 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
3141 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
3142
3143 return ret;
3144 }
3145
3146 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
3147 struct ib_port_immutable *immutable)
3148 {
3149 struct ib_port_attr attr;
3150 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3151 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
3152 int err;
3153
3154 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3155
3156 err = ib_query_port(ibdev, port_num, &attr);
3157 if (err)
3158 return err;
3159
3160 immutable->pkey_tbl_len = attr.pkey_tbl_len;
3161 immutable->gid_tbl_len = attr.gid_tbl_len;
3162 immutable->core_cap_flags = get_core_cap_flags(ibdev);
3163 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
3164 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
3165
3166 return 0;
3167 }
3168
3169 static void get_dev_fw_str(struct ib_device *ibdev, char *str,
3170 size_t str_len)
3171 {
3172 struct mlx5_ib_dev *dev =
3173 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
3174 snprintf(str, str_len, "%d.%d.%04d", fw_rev_maj(dev->mdev),
3175 fw_rev_min(dev->mdev), fw_rev_sub(dev->mdev));
3176 }
3177
3178 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
3179 {
3180 struct mlx5_core_dev *mdev = dev->mdev;
3181 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
3182 MLX5_FLOW_NAMESPACE_LAG);
3183 struct mlx5_flow_table *ft;
3184 int err;
3185
3186 if (!ns || !mlx5_lag_is_active(mdev))
3187 return 0;
3188
3189 err = mlx5_cmd_create_vport_lag(mdev);
3190 if (err)
3191 return err;
3192
3193 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
3194 if (IS_ERR(ft)) {
3195 err = PTR_ERR(ft);
3196 goto err_destroy_vport_lag;
3197 }
3198
3199 dev->flow_db.lag_demux_ft = ft;
3200 return 0;
3201
3202 err_destroy_vport_lag:
3203 mlx5_cmd_destroy_vport_lag(mdev);
3204 return err;
3205 }
3206
3207 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
3208 {
3209 struct mlx5_core_dev *mdev = dev->mdev;
3210
3211 if (dev->flow_db.lag_demux_ft) {
3212 mlx5_destroy_flow_table(dev->flow_db.lag_demux_ft);
3213 dev->flow_db.lag_demux_ft = NULL;
3214
3215 mlx5_cmd_destroy_vport_lag(mdev);
3216 }
3217 }
3218
3219 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev)
3220 {
3221 int err;
3222
3223 dev->roce.nb.notifier_call = mlx5_netdev_event;
3224 err = register_netdevice_notifier(&dev->roce.nb);
3225 if (err) {
3226 dev->roce.nb.notifier_call = NULL;
3227 return err;
3228 }
3229
3230 return 0;
3231 }
3232
3233 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev)
3234 {
3235 if (dev->roce.nb.notifier_call) {
3236 unregister_netdevice_notifier(&dev->roce.nb);
3237 dev->roce.nb.notifier_call = NULL;
3238 }
3239 }
3240
3241 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
3242 {
3243 int err;
3244
3245 err = mlx5_add_netdev_notifier(dev);
3246 if (err)
3247 return err;
3248
3249 if (MLX5_CAP_GEN(dev->mdev, roce)) {
3250 err = mlx5_nic_vport_enable_roce(dev->mdev);
3251 if (err)
3252 goto err_unregister_netdevice_notifier;
3253 }
3254
3255 err = mlx5_eth_lag_init(dev);
3256 if (err)
3257 goto err_disable_roce;
3258
3259 return 0;
3260
3261 err_disable_roce:
3262 if (MLX5_CAP_GEN(dev->mdev, roce))
3263 mlx5_nic_vport_disable_roce(dev->mdev);
3264
3265 err_unregister_netdevice_notifier:
3266 mlx5_remove_netdev_notifier(dev);
3267 return err;
3268 }
3269
3270 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
3271 {
3272 mlx5_eth_lag_cleanup(dev);
3273 if (MLX5_CAP_GEN(dev->mdev, roce))
3274 mlx5_nic_vport_disable_roce(dev->mdev);
3275 }
3276
3277 struct mlx5_ib_counter {
3278 const char *name;
3279 size_t offset;
3280 };
3281
3282 #define INIT_Q_COUNTER(_name) \
3283 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3284
3285 static const struct mlx5_ib_counter basic_q_cnts[] = {
3286 INIT_Q_COUNTER(rx_write_requests),
3287 INIT_Q_COUNTER(rx_read_requests),
3288 INIT_Q_COUNTER(rx_atomic_requests),
3289 INIT_Q_COUNTER(out_of_buffer),
3290 };
3291
3292 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
3293 INIT_Q_COUNTER(out_of_sequence),
3294 };
3295
3296 static const struct mlx5_ib_counter retrans_q_cnts[] = {
3297 INIT_Q_COUNTER(duplicate_request),
3298 INIT_Q_COUNTER(rnr_nak_retry_err),
3299 INIT_Q_COUNTER(packet_seq_err),
3300 INIT_Q_COUNTER(implied_nak_seq_err),
3301 INIT_Q_COUNTER(local_ack_timeout_err),
3302 };
3303
3304 #define INIT_CONG_COUNTER(_name) \
3305 { .name = #_name, .offset = \
3306 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
3307
3308 static const struct mlx5_ib_counter cong_cnts[] = {
3309 INIT_CONG_COUNTER(rp_cnp_ignored),
3310 INIT_CONG_COUNTER(rp_cnp_handled),
3311 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
3312 INIT_CONG_COUNTER(np_cnp_sent),
3313 };
3314
3315 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
3316 {
3317 unsigned int i;
3318
3319 for (i = 0; i < dev->num_ports; i++) {
3320 mlx5_core_dealloc_q_counter(dev->mdev,
3321 dev->port[i].cnts.set_id);
3322 kfree(dev->port[i].cnts.names);
3323 kfree(dev->port[i].cnts.offsets);
3324 }
3325 }
3326
3327 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
3328 struct mlx5_ib_counters *cnts)
3329 {
3330 u32 num_counters;
3331
3332 num_counters = ARRAY_SIZE(basic_q_cnts);
3333
3334 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
3335 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
3336
3337 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
3338 num_counters += ARRAY_SIZE(retrans_q_cnts);
3339 cnts->num_q_counters = num_counters;
3340
3341 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3342 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
3343 num_counters += ARRAY_SIZE(cong_cnts);
3344 }
3345
3346 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
3347 if (!cnts->names)
3348 return -ENOMEM;
3349
3350 cnts->offsets = kcalloc(num_counters,
3351 sizeof(cnts->offsets), GFP_KERNEL);
3352 if (!cnts->offsets)
3353 goto err_names;
3354
3355 return 0;
3356
3357 err_names:
3358 kfree(cnts->names);
3359 return -ENOMEM;
3360 }
3361
3362 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
3363 const char **names,
3364 size_t *offsets)
3365 {
3366 int i;
3367 int j = 0;
3368
3369 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
3370 names[j] = basic_q_cnts[i].name;
3371 offsets[j] = basic_q_cnts[i].offset;
3372 }
3373
3374 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
3375 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
3376 names[j] = out_of_seq_q_cnts[i].name;
3377 offsets[j] = out_of_seq_q_cnts[i].offset;
3378 }
3379 }
3380
3381 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
3382 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
3383 names[j] = retrans_q_cnts[i].name;
3384 offsets[j] = retrans_q_cnts[i].offset;
3385 }
3386 }
3387
3388 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3389 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
3390 names[j] = cong_cnts[i].name;
3391 offsets[j] = cong_cnts[i].offset;
3392 }
3393 }
3394 }
3395
3396 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
3397 {
3398 int i;
3399 int ret;
3400
3401 for (i = 0; i < dev->num_ports; i++) {
3402 struct mlx5_ib_port *port = &dev->port[i];
3403
3404 ret = mlx5_core_alloc_q_counter(dev->mdev,
3405 &port->cnts.set_id);
3406 if (ret) {
3407 mlx5_ib_warn(dev,
3408 "couldn't allocate queue counter for port %d, err %d\n",
3409 i + 1, ret);
3410 goto dealloc_counters;
3411 }
3412
3413 ret = __mlx5_ib_alloc_counters(dev, &port->cnts);
3414 if (ret)
3415 goto dealloc_counters;
3416
3417 mlx5_ib_fill_counters(dev, port->cnts.names,
3418 port->cnts.offsets);
3419 }
3420
3421 return 0;
3422
3423 dealloc_counters:
3424 while (--i >= 0)
3425 mlx5_core_dealloc_q_counter(dev->mdev,
3426 dev->port[i].cnts.set_id);
3427
3428 return ret;
3429 }
3430
3431 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
3432 u8 port_num)
3433 {
3434 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3435 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3436
3437 /* We support only per port stats */
3438 if (port_num == 0)
3439 return NULL;
3440
3441 return rdma_alloc_hw_stats_struct(port->cnts.names,
3442 port->cnts.num_q_counters +
3443 port->cnts.num_cong_counters,
3444 RDMA_HW_STATS_DEFAULT_LIFESPAN);
3445 }
3446
3447 static int mlx5_ib_query_q_counters(struct mlx5_ib_dev *dev,
3448 struct mlx5_ib_port *port,
3449 struct rdma_hw_stats *stats)
3450 {
3451 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
3452 void *out;
3453 __be32 val;
3454 int ret, i;
3455
3456 out = kvzalloc(outlen, GFP_KERNEL);
3457 if (!out)
3458 return -ENOMEM;
3459
3460 ret = mlx5_core_query_q_counter(dev->mdev,
3461 port->cnts.set_id, 0,
3462 out, outlen);
3463 if (ret)
3464 goto free;
3465
3466 for (i = 0; i < port->cnts.num_q_counters; i++) {
3467 val = *(__be32 *)(out + port->cnts.offsets[i]);
3468 stats->value[i] = (u64)be32_to_cpu(val);
3469 }
3470
3471 free:
3472 kvfree(out);
3473 return ret;
3474 }
3475
3476 static int mlx5_ib_query_cong_counters(struct mlx5_ib_dev *dev,
3477 struct mlx5_ib_port *port,
3478 struct rdma_hw_stats *stats)
3479 {
3480 int outlen = MLX5_ST_SZ_BYTES(query_cong_statistics_out);
3481 void *out;
3482 int ret, i;
3483 int offset = port->cnts.num_q_counters;
3484
3485 out = kvzalloc(outlen, GFP_KERNEL);
3486 if (!out)
3487 return -ENOMEM;
3488
3489 ret = mlx5_cmd_query_cong_counter(dev->mdev, false, out, outlen);
3490 if (ret)
3491 goto free;
3492
3493 for (i = 0; i < port->cnts.num_cong_counters; i++) {
3494 stats->value[i + offset] =
3495 be64_to_cpup((__be64 *)(out +
3496 port->cnts.offsets[i + offset]));
3497 }
3498
3499 free:
3500 kvfree(out);
3501 return ret;
3502 }
3503
3504 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
3505 struct rdma_hw_stats *stats,
3506 u8 port_num, int index)
3507 {
3508 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3509 struct mlx5_ib_port *port = &dev->port[port_num - 1];
3510 int ret, num_counters;
3511
3512 if (!stats)
3513 return -EINVAL;
3514
3515 ret = mlx5_ib_query_q_counters(dev, port, stats);
3516 if (ret)
3517 return ret;
3518 num_counters = port->cnts.num_q_counters;
3519
3520 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
3521 ret = mlx5_ib_query_cong_counters(dev, port, stats);
3522 if (ret)
3523 return ret;
3524 num_counters += port->cnts.num_cong_counters;
3525 }
3526
3527 return num_counters;
3528 }
3529
3530 static void mlx5_ib_free_rdma_netdev(struct net_device *netdev)
3531 {
3532 return mlx5_rdma_netdev_free(netdev);
3533 }
3534
3535 static struct net_device*
3536 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
3537 u8 port_num,
3538 enum rdma_netdev_t type,
3539 const char *name,
3540 unsigned char name_assign_type,
3541 void (*setup)(struct net_device *))
3542 {
3543 struct net_device *netdev;
3544 struct rdma_netdev *rn;
3545
3546 if (type != RDMA_NETDEV_IPOIB)
3547 return ERR_PTR(-EOPNOTSUPP);
3548
3549 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
3550 name, setup);
3551 if (likely(!IS_ERR_OR_NULL(netdev))) {
3552 rn = netdev_priv(netdev);
3553 rn->free_rdma_netdev = mlx5_ib_free_rdma_netdev;
3554 }
3555 return netdev;
3556 }
3557
3558 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
3559 {
3560 struct mlx5_ib_dev *dev;
3561 enum rdma_link_layer ll;
3562 int port_type_cap;
3563 const char *name;
3564 int err;
3565 int i;
3566
3567 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
3568 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
3569
3570 printk_once(KERN_INFO "%s", mlx5_version);
3571
3572 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
3573 if (!dev)
3574 return NULL;
3575
3576 dev->mdev = mdev;
3577
3578 dev->port = kcalloc(MLX5_CAP_GEN(mdev, num_ports), sizeof(*dev->port),
3579 GFP_KERNEL);
3580 if (!dev->port)
3581 goto err_dealloc;
3582
3583 rwlock_init(&dev->roce.netdev_lock);
3584 err = get_port_caps(dev);
3585 if (err)
3586 goto err_free_port;
3587
3588 if (mlx5_use_mad_ifc(dev))
3589 get_ext_port_caps(dev);
3590
3591 if (!mlx5_lag_is_active(mdev))
3592 name = "mlx5_%d";
3593 else
3594 name = "mlx5_bond_%d";
3595
3596 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
3597 dev->ib_dev.owner = THIS_MODULE;
3598 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
3599 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
3600 dev->num_ports = MLX5_CAP_GEN(mdev, num_ports);
3601 dev->ib_dev.phys_port_cnt = dev->num_ports;
3602 dev->ib_dev.num_comp_vectors =
3603 dev->mdev->priv.eq_table.num_comp_vectors;
3604 dev->ib_dev.dev.parent = &mdev->pdev->dev;
3605
3606 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
3607 dev->ib_dev.uverbs_cmd_mask =
3608 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
3609 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
3610 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
3611 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
3612 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
3613 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
3614 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
3615 (1ull << IB_USER_VERBS_CMD_REG_MR) |
3616 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
3617 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
3618 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
3619 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
3620 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
3621 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
3622 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
3623 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
3624 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
3625 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
3626 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
3627 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
3628 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
3629 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
3630 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
3631 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
3632 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
3633 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
3634 dev->ib_dev.uverbs_ex_cmd_mask =
3635 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
3636 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
3637 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
3638 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP);
3639
3640 dev->ib_dev.query_device = mlx5_ib_query_device;
3641 dev->ib_dev.query_port = mlx5_ib_query_port;
3642 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
3643 if (ll == IB_LINK_LAYER_ETHERNET)
3644 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
3645 dev->ib_dev.query_gid = mlx5_ib_query_gid;
3646 dev->ib_dev.add_gid = mlx5_ib_add_gid;
3647 dev->ib_dev.del_gid = mlx5_ib_del_gid;
3648 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
3649 dev->ib_dev.modify_device = mlx5_ib_modify_device;
3650 dev->ib_dev.modify_port = mlx5_ib_modify_port;
3651 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
3652 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
3653 dev->ib_dev.mmap = mlx5_ib_mmap;
3654 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
3655 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
3656 dev->ib_dev.create_ah = mlx5_ib_create_ah;
3657 dev->ib_dev.query_ah = mlx5_ib_query_ah;
3658 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
3659 dev->ib_dev.create_srq = mlx5_ib_create_srq;
3660 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
3661 dev->ib_dev.query_srq = mlx5_ib_query_srq;
3662 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
3663 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
3664 dev->ib_dev.create_qp = mlx5_ib_create_qp;
3665 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
3666 dev->ib_dev.query_qp = mlx5_ib_query_qp;
3667 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
3668 dev->ib_dev.post_send = mlx5_ib_post_send;
3669 dev->ib_dev.post_recv = mlx5_ib_post_recv;
3670 dev->ib_dev.create_cq = mlx5_ib_create_cq;
3671 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
3672 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
3673 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
3674 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
3675 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
3676 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
3677 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
3678 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
3679 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
3680 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
3681 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
3682 dev->ib_dev.process_mad = mlx5_ib_process_mad;
3683 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
3684 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
3685 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
3686 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
3687 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
3688 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
3689 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
3690
3691 if (mlx5_core_is_pf(mdev)) {
3692 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
3693 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
3694 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
3695 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
3696 }
3697
3698 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
3699
3700 mlx5_ib_internal_fill_odp_caps(dev);
3701
3702 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
3703
3704 if (MLX5_CAP_GEN(mdev, imaicl)) {
3705 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
3706 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
3707 dev->ib_dev.uverbs_cmd_mask |=
3708 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
3709 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
3710 }
3711
3712 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3713 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
3714 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
3715 }
3716
3717 if (MLX5_CAP_GEN(mdev, xrc)) {
3718 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
3719 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
3720 dev->ib_dev.uverbs_cmd_mask |=
3721 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
3722 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
3723 }
3724
3725 if (mlx5_ib_port_link_layer(&dev->ib_dev, 1) ==
3726 IB_LINK_LAYER_ETHERNET) {
3727 dev->ib_dev.create_flow = mlx5_ib_create_flow;
3728 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
3729 dev->ib_dev.create_wq = mlx5_ib_create_wq;
3730 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
3731 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
3732 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
3733 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
3734 dev->ib_dev.uverbs_ex_cmd_mask |=
3735 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
3736 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW) |
3737 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
3738 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
3739 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
3740 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
3741 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
3742 }
3743 err = init_node_data(dev);
3744 if (err)
3745 goto err_free_port;
3746
3747 mutex_init(&dev->flow_db.lock);
3748 mutex_init(&dev->cap_mask_mutex);
3749 INIT_LIST_HEAD(&dev->qp_list);
3750 spin_lock_init(&dev->reset_flow_resource_lock);
3751
3752 if (ll == IB_LINK_LAYER_ETHERNET) {
3753 err = mlx5_enable_eth(dev);
3754 if (err)
3755 goto err_free_port;
3756 }
3757
3758 err = create_dev_resources(&dev->devr);
3759 if (err)
3760 goto err_disable_eth;
3761
3762 err = mlx5_ib_odp_init_one(dev);
3763 if (err)
3764 goto err_rsrc;
3765
3766 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
3767 err = mlx5_ib_alloc_counters(dev);
3768 if (err)
3769 goto err_odp;
3770 }
3771
3772 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
3773 if (!dev->mdev->priv.uar)
3774 goto err_cnt;
3775
3776 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
3777 if (err)
3778 goto err_uar_page;
3779
3780 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
3781 if (err)
3782 goto err_bfreg;
3783
3784 err = ib_register_device(&dev->ib_dev, NULL);
3785 if (err)
3786 goto err_fp_bfreg;
3787
3788 err = create_umr_res(dev);
3789 if (err)
3790 goto err_dev;
3791
3792 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
3793 err = device_create_file(&dev->ib_dev.dev,
3794 mlx5_class_attributes[i]);
3795 if (err)
3796 goto err_umrc;
3797 }
3798
3799 dev->ib_active = true;
3800
3801 return dev;
3802
3803 err_umrc:
3804 destroy_umrc_res(dev);
3805
3806 err_dev:
3807 ib_unregister_device(&dev->ib_dev);
3808
3809 err_fp_bfreg:
3810 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3811
3812 err_bfreg:
3813 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3814
3815 err_uar_page:
3816 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
3817
3818 err_cnt:
3819 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3820 mlx5_ib_dealloc_counters(dev);
3821
3822 err_odp:
3823 mlx5_ib_odp_remove_one(dev);
3824
3825 err_rsrc:
3826 destroy_dev_resources(&dev->devr);
3827
3828 err_disable_eth:
3829 if (ll == IB_LINK_LAYER_ETHERNET) {
3830 mlx5_disable_eth(dev);
3831 mlx5_remove_netdev_notifier(dev);
3832 }
3833
3834 err_free_port:
3835 kfree(dev->port);
3836
3837 err_dealloc:
3838 ib_dealloc_device((struct ib_device *)dev);
3839
3840 return NULL;
3841 }
3842
3843 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
3844 {
3845 struct mlx5_ib_dev *dev = context;
3846 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev, 1);
3847
3848 mlx5_remove_netdev_notifier(dev);
3849 ib_unregister_device(&dev->ib_dev);
3850 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
3851 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
3852 mlx5_put_uars_page(dev->mdev, mdev->priv.uar);
3853 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
3854 mlx5_ib_dealloc_counters(dev);
3855 destroy_umrc_res(dev);
3856 mlx5_ib_odp_remove_one(dev);
3857 destroy_dev_resources(&dev->devr);
3858 if (ll == IB_LINK_LAYER_ETHERNET)
3859 mlx5_disable_eth(dev);
3860 kfree(dev->port);
3861 ib_dealloc_device(&dev->ib_dev);
3862 }
3863
3864 static struct mlx5_interface mlx5_ib_interface = {
3865 .add = mlx5_ib_add,
3866 .remove = mlx5_ib_remove,
3867 .event = mlx5_ib_event,
3868 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3869 .pfault = mlx5_ib_pfault,
3870 #endif
3871 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
3872 };
3873
3874 static int __init mlx5_ib_init(void)
3875 {
3876 int err;
3877
3878 mlx5_ib_odp_init();
3879
3880 err = mlx5_register_interface(&mlx5_ib_interface);
3881
3882 return err;
3883 }
3884
3885 static void __exit mlx5_ib_cleanup(void)
3886 {
3887 mlx5_unregister_interface(&mlx5_ib_interface);
3888 }
3889
3890 module_init(mlx5_ib_init);
3891 module_exit(mlx5_ib_cleanup);
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