2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/highmem.h>
34 #include <linux/module.h>
35 #include <linux/init.h>
36 #include <linux/errno.h>
37 #include <linux/pci.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/slab.h>
40 #if defined(CONFIG_X86)
43 #include <linux/sched.h>
44 #include <linux/sched/mm.h>
45 #include <linux/sched/task.h>
46 #include <linux/delay.h>
47 #include <rdma/ib_user_verbs.h>
48 #include <rdma/ib_addr.h>
49 #include <rdma/ib_cache.h>
50 #include <linux/mlx5/port.h>
51 #include <linux/mlx5/vport.h>
52 #include <linux/list.h>
53 #include <rdma/ib_smi.h>
54 #include <rdma/ib_umem.h>
56 #include <linux/etherdevice.h>
57 #include <linux/mlx5/fs.h>
58 #include <linux/mlx5/vport.h>
61 #define DRIVER_NAME "mlx5_ib"
62 #define DRIVER_VERSION "2.2-1"
63 #define DRIVER_RELDATE "Feb 2014"
65 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
67 MODULE_LICENSE("Dual BSD/GPL");
68 MODULE_VERSION(DRIVER_VERSION
);
70 static char mlx5_version
[] =
71 DRIVER_NAME
": Mellanox Connect-IB Infiniband driver v"
72 DRIVER_VERSION
" (" DRIVER_RELDATE
")\n";
75 MLX5_ATOMIC_SIZE_QP_8BYTES
= 1 << 3,
78 static enum rdma_link_layer
79 mlx5_port_type_cap_to_rdma_ll(int port_type_cap
)
81 switch (port_type_cap
) {
82 case MLX5_CAP_PORT_TYPE_IB
:
83 return IB_LINK_LAYER_INFINIBAND
;
84 case MLX5_CAP_PORT_TYPE_ETH
:
85 return IB_LINK_LAYER_ETHERNET
;
87 return IB_LINK_LAYER_UNSPECIFIED
;
91 static enum rdma_link_layer
92 mlx5_ib_port_link_layer(struct ib_device
*device
, u8 port_num
)
94 struct mlx5_ib_dev
*dev
= to_mdev(device
);
95 int port_type_cap
= MLX5_CAP_GEN(dev
->mdev
, port_type
);
97 return mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
100 static int mlx5_netdev_event(struct notifier_block
*this,
101 unsigned long event
, void *ptr
)
103 struct net_device
*ndev
= netdev_notifier_info_to_dev(ptr
);
104 struct mlx5_ib_dev
*ibdev
= container_of(this, struct mlx5_ib_dev
,
108 case NETDEV_REGISTER
:
109 case NETDEV_UNREGISTER
:
110 write_lock(&ibdev
->roce
.netdev_lock
);
111 if (ndev
->dev
.parent
== &ibdev
->mdev
->pdev
->dev
)
112 ibdev
->roce
.netdev
= (event
== NETDEV_UNREGISTER
) ?
114 write_unlock(&ibdev
->roce
.netdev_lock
);
119 struct net_device
*lag_ndev
= mlx5_lag_get_roce_netdev(ibdev
->mdev
);
120 struct net_device
*upper
= NULL
;
123 upper
= netdev_master_upper_dev_get(lag_ndev
);
127 if ((upper
== ndev
|| (!upper
&& ndev
== ibdev
->roce
.netdev
))
128 && ibdev
->ib_active
) {
129 struct ib_event ibev
= { };
131 ibev
.device
= &ibdev
->ib_dev
;
132 ibev
.event
= (event
== NETDEV_UP
) ?
133 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
134 ibev
.element
.port_num
= 1;
135 ib_dispatch_event(&ibev
);
147 static struct net_device
*mlx5_ib_get_netdev(struct ib_device
*device
,
150 struct mlx5_ib_dev
*ibdev
= to_mdev(device
);
151 struct net_device
*ndev
;
153 ndev
= mlx5_lag_get_roce_netdev(ibdev
->mdev
);
157 /* Ensure ndev does not disappear before we invoke dev_hold()
159 read_lock(&ibdev
->roce
.netdev_lock
);
160 ndev
= ibdev
->roce
.netdev
;
163 read_unlock(&ibdev
->roce
.netdev_lock
);
168 static int mlx5_query_port_roce(struct ib_device
*device
, u8 port_num
,
169 struct ib_port_attr
*props
)
171 struct mlx5_ib_dev
*dev
= to_mdev(device
);
172 struct net_device
*ndev
, *upper
;
173 enum ib_mtu ndev_ib_mtu
;
176 /* props being zeroed by the caller, avoid zeroing it here */
178 props
->port_cap_flags
|= IB_PORT_CM_SUP
;
179 props
->port_cap_flags
|= IB_PORT_IP_BASED_GIDS
;
181 props
->gid_tbl_len
= MLX5_CAP_ROCE(dev
->mdev
,
182 roce_address_table_size
);
183 props
->max_mtu
= IB_MTU_4096
;
184 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
185 props
->pkey_tbl_len
= 1;
186 props
->state
= IB_PORT_DOWN
;
187 props
->phys_state
= 3;
189 mlx5_query_nic_vport_qkey_viol_cntr(dev
->mdev
, &qkey_viol_cntr
);
190 props
->qkey_viol_cntr
= qkey_viol_cntr
;
192 ndev
= mlx5_ib_get_netdev(device
, port_num
);
196 if (mlx5_lag_is_active(dev
->mdev
)) {
198 upper
= netdev_master_upper_dev_get_rcu(ndev
);
207 if (netif_running(ndev
) && netif_carrier_ok(ndev
)) {
208 props
->state
= IB_PORT_ACTIVE
;
209 props
->phys_state
= 5;
212 ndev_ib_mtu
= iboe_get_mtu(ndev
->mtu
);
216 props
->active_mtu
= min(props
->max_mtu
, ndev_ib_mtu
);
218 props
->active_width
= IB_WIDTH_4X
; /* TODO */
219 props
->active_speed
= IB_SPEED_QDR
; /* TODO */
224 static void ib_gid_to_mlx5_roce_addr(const union ib_gid
*gid
,
225 const struct ib_gid_attr
*attr
,
228 #define MLX5_SET_RA(p, f, v) MLX5_SET(roce_addr_layout, p, f, v)
229 char *mlx5_addr_l3_addr
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
231 void *mlx5_addr_mac
= MLX5_ADDR_OF(roce_addr_layout
, mlx5_addr
,
237 ether_addr_copy(mlx5_addr_mac
, attr
->ndev
->dev_addr
);
239 if (is_vlan_dev(attr
->ndev
)) {
240 MLX5_SET_RA(mlx5_addr
, vlan_valid
, 1);
241 MLX5_SET_RA(mlx5_addr
, vlan_id
, vlan_dev_vlan_id(attr
->ndev
));
244 switch (attr
->gid_type
) {
246 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_1
);
248 case IB_GID_TYPE_ROCE_UDP_ENCAP
:
249 MLX5_SET_RA(mlx5_addr
, roce_version
, MLX5_ROCE_VERSION_2
);
256 if (attr
->gid_type
!= IB_GID_TYPE_IB
) {
257 if (ipv6_addr_v4mapped((void *)gid
))
258 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
259 MLX5_ROCE_L3_TYPE_IPV4
);
261 MLX5_SET_RA(mlx5_addr
, roce_l3_type
,
262 MLX5_ROCE_L3_TYPE_IPV6
);
265 if ((attr
->gid_type
== IB_GID_TYPE_IB
) ||
266 !ipv6_addr_v4mapped((void *)gid
))
267 memcpy(mlx5_addr_l3_addr
, gid
, sizeof(*gid
));
269 memcpy(&mlx5_addr_l3_addr
[12], &gid
->raw
[12], 4);
272 static int set_roce_addr(struct ib_device
*device
, u8 port_num
,
274 const union ib_gid
*gid
,
275 const struct ib_gid_attr
*attr
)
277 struct mlx5_ib_dev
*dev
= to_mdev(device
);
278 u32 in
[MLX5_ST_SZ_DW(set_roce_address_in
)] = {0};
279 u32 out
[MLX5_ST_SZ_DW(set_roce_address_out
)] = {0};
280 void *in_addr
= MLX5_ADDR_OF(set_roce_address_in
, in
, roce_address
);
281 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(device
, port_num
);
283 if (ll
!= IB_LINK_LAYER_ETHERNET
)
286 ib_gid_to_mlx5_roce_addr(gid
, attr
, in_addr
);
288 MLX5_SET(set_roce_address_in
, in
, roce_address_index
, index
);
289 MLX5_SET(set_roce_address_in
, in
, opcode
, MLX5_CMD_OP_SET_ROCE_ADDRESS
);
290 return mlx5_cmd_exec(dev
->mdev
, in
, sizeof(in
), out
, sizeof(out
));
293 static int mlx5_ib_add_gid(struct ib_device
*device
, u8 port_num
,
294 unsigned int index
, const union ib_gid
*gid
,
295 const struct ib_gid_attr
*attr
,
296 __always_unused
void **context
)
298 return set_roce_addr(device
, port_num
, index
, gid
, attr
);
301 static int mlx5_ib_del_gid(struct ib_device
*device
, u8 port_num
,
302 unsigned int index
, __always_unused
void **context
)
304 return set_roce_addr(device
, port_num
, index
, NULL
, NULL
);
307 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
310 struct ib_gid_attr attr
;
313 if (ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
))
321 if (attr
.gid_type
!= IB_GID_TYPE_ROCE_UDP_ENCAP
)
324 return cpu_to_be16(MLX5_CAP_ROCE(dev
->mdev
, r_roce_min_src_udp_port
));
327 int mlx5_get_roce_gid_type(struct mlx5_ib_dev
*dev
, u8 port_num
,
328 int index
, enum ib_gid_type
*gid_type
)
330 struct ib_gid_attr attr
;
334 ret
= ib_get_cached_gid(&dev
->ib_dev
, port_num
, index
, &gid
, &attr
);
343 *gid_type
= attr
.gid_type
;
348 static int mlx5_use_mad_ifc(struct mlx5_ib_dev
*dev
)
350 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) == MLX5_CAP_PORT_TYPE_IB
)
351 return !MLX5_CAP_GEN(dev
->mdev
, ib_virt
);
356 MLX5_VPORT_ACCESS_METHOD_MAD
,
357 MLX5_VPORT_ACCESS_METHOD_HCA
,
358 MLX5_VPORT_ACCESS_METHOD_NIC
,
361 static int mlx5_get_vport_access_method(struct ib_device
*ibdev
)
363 if (mlx5_use_mad_ifc(to_mdev(ibdev
)))
364 return MLX5_VPORT_ACCESS_METHOD_MAD
;
366 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
367 IB_LINK_LAYER_ETHERNET
)
368 return MLX5_VPORT_ACCESS_METHOD_NIC
;
370 return MLX5_VPORT_ACCESS_METHOD_HCA
;
373 static void get_atomic_caps(struct mlx5_ib_dev
*dev
,
374 struct ib_device_attr
*props
)
377 u8 atomic_operations
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_operations
);
378 u8 atomic_size_qp
= MLX5_CAP_ATOMIC(dev
->mdev
, atomic_size_qp
);
379 u8 atomic_req_8B_endianness_mode
=
380 MLX5_CAP_ATOMIC(dev
->mdev
, atomic_req_8B_endianess_mode
);
382 /* Check if HW supports 8 bytes standard atomic operations and capable
383 * of host endianness respond
385 tmp
= MLX5_ATOMIC_OPS_CMP_SWAP
| MLX5_ATOMIC_OPS_FETCH_ADD
;
386 if (((atomic_operations
& tmp
) == tmp
) &&
387 (atomic_size_qp
& MLX5_ATOMIC_SIZE_QP_8BYTES
) &&
388 (atomic_req_8B_endianness_mode
)) {
389 props
->atomic_cap
= IB_ATOMIC_HCA
;
391 props
->atomic_cap
= IB_ATOMIC_NONE
;
395 static int mlx5_query_system_image_guid(struct ib_device
*ibdev
,
396 __be64
*sys_image_guid
)
398 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
399 struct mlx5_core_dev
*mdev
= dev
->mdev
;
403 switch (mlx5_get_vport_access_method(ibdev
)) {
404 case MLX5_VPORT_ACCESS_METHOD_MAD
:
405 return mlx5_query_mad_ifc_system_image_guid(ibdev
,
408 case MLX5_VPORT_ACCESS_METHOD_HCA
:
409 err
= mlx5_query_hca_vport_system_image_guid(mdev
, &tmp
);
412 case MLX5_VPORT_ACCESS_METHOD_NIC
:
413 err
= mlx5_query_nic_vport_system_image_guid(mdev
, &tmp
);
421 *sys_image_guid
= cpu_to_be64(tmp
);
427 static int mlx5_query_max_pkeys(struct ib_device
*ibdev
,
430 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
431 struct mlx5_core_dev
*mdev
= dev
->mdev
;
433 switch (mlx5_get_vport_access_method(ibdev
)) {
434 case MLX5_VPORT_ACCESS_METHOD_MAD
:
435 return mlx5_query_mad_ifc_max_pkeys(ibdev
, max_pkeys
);
437 case MLX5_VPORT_ACCESS_METHOD_HCA
:
438 case MLX5_VPORT_ACCESS_METHOD_NIC
:
439 *max_pkeys
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
,
448 static int mlx5_query_vendor_id(struct ib_device
*ibdev
,
451 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
453 switch (mlx5_get_vport_access_method(ibdev
)) {
454 case MLX5_VPORT_ACCESS_METHOD_MAD
:
455 return mlx5_query_mad_ifc_vendor_id(ibdev
, vendor_id
);
457 case MLX5_VPORT_ACCESS_METHOD_HCA
:
458 case MLX5_VPORT_ACCESS_METHOD_NIC
:
459 return mlx5_core_query_vendor_id(dev
->mdev
, vendor_id
);
466 static int mlx5_query_node_guid(struct mlx5_ib_dev
*dev
,
472 switch (mlx5_get_vport_access_method(&dev
->ib_dev
)) {
473 case MLX5_VPORT_ACCESS_METHOD_MAD
:
474 return mlx5_query_mad_ifc_node_guid(dev
, node_guid
);
476 case MLX5_VPORT_ACCESS_METHOD_HCA
:
477 err
= mlx5_query_hca_vport_node_guid(dev
->mdev
, &tmp
);
480 case MLX5_VPORT_ACCESS_METHOD_NIC
:
481 err
= mlx5_query_nic_vport_node_guid(dev
->mdev
, &tmp
);
489 *node_guid
= cpu_to_be64(tmp
);
494 struct mlx5_reg_node_desc
{
495 u8 desc
[IB_DEVICE_NODE_DESC_MAX
];
498 static int mlx5_query_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
)
500 struct mlx5_reg_node_desc in
;
502 if (mlx5_use_mad_ifc(dev
))
503 return mlx5_query_mad_ifc_node_desc(dev
, node_desc
);
505 memset(&in
, 0, sizeof(in
));
507 return mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), node_desc
,
508 sizeof(struct mlx5_reg_node_desc
),
509 MLX5_REG_NODE_DESC
, 0, 0);
512 static int mlx5_ib_query_device(struct ib_device
*ibdev
,
513 struct ib_device_attr
*props
,
514 struct ib_udata
*uhw
)
516 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
517 struct mlx5_core_dev
*mdev
= dev
->mdev
;
522 u64 min_page_size
= 1ull << MLX5_CAP_GEN(mdev
, log_pg_sz
);
523 struct mlx5_ib_query_device_resp resp
= {};
527 resp_len
= sizeof(resp
.comp_mask
) + sizeof(resp
.response_length
);
528 if (uhw
->outlen
&& uhw
->outlen
< resp_len
)
531 resp
.response_length
= resp_len
;
533 if (uhw
->inlen
&& !ib_is_udata_cleared(uhw
, 0, uhw
->inlen
))
536 memset(props
, 0, sizeof(*props
));
537 err
= mlx5_query_system_image_guid(ibdev
,
538 &props
->sys_image_guid
);
542 err
= mlx5_query_max_pkeys(ibdev
, &props
->max_pkeys
);
546 err
= mlx5_query_vendor_id(ibdev
, &props
->vendor_id
);
550 props
->fw_ver
= ((u64
)fw_rev_maj(dev
->mdev
) << 32) |
551 (fw_rev_min(dev
->mdev
) << 16) |
552 fw_rev_sub(dev
->mdev
);
553 props
->device_cap_flags
= IB_DEVICE_CHANGE_PHY_PORT
|
554 IB_DEVICE_PORT_ACTIVE_EVENT
|
555 IB_DEVICE_SYS_IMAGE_GUID
|
556 IB_DEVICE_RC_RNR_NAK_GEN
;
558 if (MLX5_CAP_GEN(mdev
, pkv
))
559 props
->device_cap_flags
|= IB_DEVICE_BAD_PKEY_CNTR
;
560 if (MLX5_CAP_GEN(mdev
, qkv
))
561 props
->device_cap_flags
|= IB_DEVICE_BAD_QKEY_CNTR
;
562 if (MLX5_CAP_GEN(mdev
, apm
))
563 props
->device_cap_flags
|= IB_DEVICE_AUTO_PATH_MIG
;
564 if (MLX5_CAP_GEN(mdev
, xrc
))
565 props
->device_cap_flags
|= IB_DEVICE_XRC
;
566 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
567 props
->device_cap_flags
|= IB_DEVICE_MEM_WINDOW
|
568 IB_DEVICE_MEM_WINDOW_TYPE_2B
;
569 props
->max_mw
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
570 /* We support 'Gappy' memory registration too */
571 props
->device_cap_flags
|= IB_DEVICE_SG_GAPS_REG
;
573 props
->device_cap_flags
|= IB_DEVICE_MEM_MGT_EXTENSIONS
;
574 if (MLX5_CAP_GEN(mdev
, sho
)) {
575 props
->device_cap_flags
|= IB_DEVICE_SIGNATURE_HANDOVER
;
576 /* At this stage no support for signature handover */
577 props
->sig_prot_cap
= IB_PROT_T10DIF_TYPE_1
|
578 IB_PROT_T10DIF_TYPE_2
|
579 IB_PROT_T10DIF_TYPE_3
;
580 props
->sig_guard_cap
= IB_GUARD_T10DIF_CRC
|
581 IB_GUARD_T10DIF_CSUM
;
583 if (MLX5_CAP_GEN(mdev
, block_lb_mc
))
584 props
->device_cap_flags
|= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK
;
586 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
)) {
587 if (MLX5_CAP_ETH(mdev
, csum_cap
)) {
588 /* Legacy bit to support old userspace libraries */
589 props
->device_cap_flags
|= IB_DEVICE_RAW_IP_CSUM
;
590 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_IP_CSUM
;
593 if (MLX5_CAP_ETH(dev
->mdev
, vlan_cap
))
594 props
->raw_packet_caps
|=
595 IB_RAW_PACKET_CAP_CVLAN_STRIPPING
;
597 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
)) {
598 max_tso
= MLX5_CAP_ETH(mdev
, max_lso_cap
);
600 resp
.tso_caps
.max_tso
= 1 << max_tso
;
601 resp
.tso_caps
.supported_qpts
|=
602 1 << IB_QPT_RAW_PACKET
;
603 resp
.response_length
+= sizeof(resp
.tso_caps
);
607 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
)) {
608 resp
.rss_caps
.rx_hash_function
=
609 MLX5_RX_HASH_FUNC_TOEPLITZ
;
610 resp
.rss_caps
.rx_hash_fields_mask
=
611 MLX5_RX_HASH_SRC_IPV4
|
612 MLX5_RX_HASH_DST_IPV4
|
613 MLX5_RX_HASH_SRC_IPV6
|
614 MLX5_RX_HASH_DST_IPV6
|
615 MLX5_RX_HASH_SRC_PORT_TCP
|
616 MLX5_RX_HASH_DST_PORT_TCP
|
617 MLX5_RX_HASH_SRC_PORT_UDP
|
618 MLX5_RX_HASH_DST_PORT_UDP
;
619 resp
.response_length
+= sizeof(resp
.rss_caps
);
622 if (field_avail(typeof(resp
), tso_caps
, uhw
->outlen
))
623 resp
.response_length
+= sizeof(resp
.tso_caps
);
624 if (field_avail(typeof(resp
), rss_caps
, uhw
->outlen
))
625 resp
.response_length
+= sizeof(resp
.rss_caps
);
628 if (MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
629 props
->device_cap_flags
|= IB_DEVICE_UD_IP_CSUM
;
630 props
->device_cap_flags
|= IB_DEVICE_UD_TSO
;
633 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
634 MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
)) {
635 /* Legacy bit to support old userspace libraries */
636 props
->device_cap_flags
|= IB_DEVICE_RAW_SCATTER_FCS
;
637 props
->raw_packet_caps
|= IB_RAW_PACKET_CAP_SCATTER_FCS
;
640 if (mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
))
641 props
->device_cap_flags
|= IB_DEVICE_MANAGED_FLOW_STEERING
;
643 props
->vendor_part_id
= mdev
->pdev
->device
;
644 props
->hw_ver
= mdev
->pdev
->revision
;
646 props
->max_mr_size
= ~0ull;
647 props
->page_size_cap
= ~(min_page_size
- 1);
648 props
->max_qp
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp
);
649 props
->max_qp_wr
= 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
650 max_rq_sg
= MLX5_CAP_GEN(mdev
, max_wqe_sz_rq
) /
651 sizeof(struct mlx5_wqe_data_seg
);
652 max_sq_desc
= min_t(int, MLX5_CAP_GEN(mdev
, max_wqe_sz_sq
), 512);
653 max_sq_sg
= (max_sq_desc
- sizeof(struct mlx5_wqe_ctrl_seg
) -
654 sizeof(struct mlx5_wqe_raddr_seg
)) /
655 sizeof(struct mlx5_wqe_data_seg
);
656 props
->max_sge
= min(max_rq_sg
, max_sq_sg
);
657 props
->max_sge_rd
= MLX5_MAX_SGE_RD
;
658 props
->max_cq
= 1 << MLX5_CAP_GEN(mdev
, log_max_cq
);
659 props
->max_cqe
= (1 << MLX5_CAP_GEN(mdev
, log_max_cq_sz
)) - 1;
660 props
->max_mr
= 1 << MLX5_CAP_GEN(mdev
, log_max_mkey
);
661 props
->max_pd
= 1 << MLX5_CAP_GEN(mdev
, log_max_pd
);
662 props
->max_qp_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_req_qp
);
663 props
->max_qp_init_rd_atom
= 1 << MLX5_CAP_GEN(mdev
, log_max_ra_res_qp
);
664 props
->max_srq
= 1 << MLX5_CAP_GEN(mdev
, log_max_srq
);
665 props
->max_srq_wr
= (1 << MLX5_CAP_GEN(mdev
, log_max_srq_sz
)) - 1;
666 props
->local_ca_ack_delay
= MLX5_CAP_GEN(mdev
, local_ca_ack_delay
);
667 props
->max_res_rd_atom
= props
->max_qp_rd_atom
* props
->max_qp
;
668 props
->max_srq_sge
= max_rq_sg
- 1;
669 props
->max_fast_reg_page_list_len
=
670 1 << MLX5_CAP_GEN(mdev
, log_max_klm_list_size
);
671 get_atomic_caps(dev
, props
);
672 props
->masked_atomic_cap
= IB_ATOMIC_NONE
;
673 props
->max_mcast_grp
= 1 << MLX5_CAP_GEN(mdev
, log_max_mcg
);
674 props
->max_mcast_qp_attach
= MLX5_CAP_GEN(mdev
, max_qp_mcg
);
675 props
->max_total_mcast_qp_attach
= props
->max_mcast_qp_attach
*
676 props
->max_mcast_grp
;
677 props
->max_map_per_fmr
= INT_MAX
; /* no limit in ConnectIB */
678 props
->max_ah
= INT_MAX
;
679 props
->hca_core_clock
= MLX5_CAP_GEN(mdev
, device_frequency_khz
);
680 props
->timestamp_mask
= 0x7FFFFFFFFFFFFFFFULL
;
682 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
683 if (MLX5_CAP_GEN(mdev
, pg
))
684 props
->device_cap_flags
|= IB_DEVICE_ON_DEMAND_PAGING
;
685 props
->odp_caps
= dev
->odp_caps
;
688 if (MLX5_CAP_GEN(mdev
, cd
))
689 props
->device_cap_flags
|= IB_DEVICE_CROSS_CHANNEL
;
691 if (!mlx5_core_is_pf(mdev
))
692 props
->device_cap_flags
|= IB_DEVICE_VIRTUAL_FUNCTION
;
694 if (mlx5_ib_port_link_layer(ibdev
, 1) ==
695 IB_LINK_LAYER_ETHERNET
) {
696 props
->rss_caps
.max_rwq_indirection_tables
=
697 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt
);
698 props
->rss_caps
.max_rwq_indirection_table_size
=
699 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
);
700 props
->rss_caps
.supported_qpts
= 1 << IB_QPT_RAW_PACKET
;
701 props
->max_wq_type_rq
=
702 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_rq
);
705 if (field_avail(typeof(resp
), cqe_comp_caps
, uhw
->outlen
)) {
706 resp
.cqe_comp_caps
.max_num
=
707 MLX5_CAP_GEN(dev
->mdev
, cqe_compression
) ?
708 MLX5_CAP_GEN(dev
->mdev
, cqe_compression_max_num
) : 0;
709 resp
.cqe_comp_caps
.supported_format
=
710 MLX5_IB_CQE_RES_FORMAT_HASH
|
711 MLX5_IB_CQE_RES_FORMAT_CSUM
;
712 resp
.response_length
+= sizeof(resp
.cqe_comp_caps
);
715 if (field_avail(typeof(resp
), packet_pacing_caps
, uhw
->outlen
)) {
716 if (MLX5_CAP_QOS(mdev
, packet_pacing
) &&
717 MLX5_CAP_GEN(mdev
, qos
)) {
718 resp
.packet_pacing_caps
.qp_rate_limit_max
=
719 MLX5_CAP_QOS(mdev
, packet_pacing_max_rate
);
720 resp
.packet_pacing_caps
.qp_rate_limit_min
=
721 MLX5_CAP_QOS(mdev
, packet_pacing_min_rate
);
722 resp
.packet_pacing_caps
.supported_qpts
|=
723 1 << IB_QPT_RAW_PACKET
;
725 resp
.response_length
+= sizeof(resp
.packet_pacing_caps
);
728 if (field_avail(typeof(resp
), mlx5_ib_support_multi_pkt_send_wqes
,
730 resp
.mlx5_ib_support_multi_pkt_send_wqes
=
731 MLX5_CAP_ETH(mdev
, multi_pkt_send_wqe
);
732 resp
.response_length
+=
733 sizeof(resp
.mlx5_ib_support_multi_pkt_send_wqes
);
736 if (field_avail(typeof(resp
), reserved
, uhw
->outlen
))
737 resp
.response_length
+= sizeof(resp
.reserved
);
740 err
= ib_copy_to_udata(uhw
, &resp
, resp
.response_length
);
750 MLX5_IB_WIDTH_1X
= 1 << 0,
751 MLX5_IB_WIDTH_2X
= 1 << 1,
752 MLX5_IB_WIDTH_4X
= 1 << 2,
753 MLX5_IB_WIDTH_8X
= 1 << 3,
754 MLX5_IB_WIDTH_12X
= 1 << 4
757 static int translate_active_width(struct ib_device
*ibdev
, u8 active_width
,
760 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
763 if (active_width
& MLX5_IB_WIDTH_1X
) {
764 *ib_width
= IB_WIDTH_1X
;
765 } else if (active_width
& MLX5_IB_WIDTH_2X
) {
766 mlx5_ib_dbg(dev
, "active_width %d is not supported by IB spec\n",
769 } else if (active_width
& MLX5_IB_WIDTH_4X
) {
770 *ib_width
= IB_WIDTH_4X
;
771 } else if (active_width
& MLX5_IB_WIDTH_8X
) {
772 *ib_width
= IB_WIDTH_8X
;
773 } else if (active_width
& MLX5_IB_WIDTH_12X
) {
774 *ib_width
= IB_WIDTH_12X
;
776 mlx5_ib_dbg(dev
, "Invalid active_width %d\n",
784 static int mlx5_mtu_to_ib_mtu(int mtu
)
793 pr_warn("invalid mtu\n");
803 __IB_MAX_VL_0_14
= 5,
806 enum mlx5_vl_hw_cap
{
818 static int translate_max_vl_num(struct ib_device
*ibdev
, u8 vl_hw_cap
,
823 *max_vl_num
= __IB_MAX_VL_0
;
826 *max_vl_num
= __IB_MAX_VL_0_1
;
829 *max_vl_num
= __IB_MAX_VL_0_3
;
832 *max_vl_num
= __IB_MAX_VL_0_7
;
834 case MLX5_VL_HW_0_14
:
835 *max_vl_num
= __IB_MAX_VL_0_14
;
845 static int mlx5_query_hca_port(struct ib_device
*ibdev
, u8 port
,
846 struct ib_port_attr
*props
)
848 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
849 struct mlx5_core_dev
*mdev
= dev
->mdev
;
850 struct mlx5_hca_vport_context
*rep
;
854 u8 ib_link_width_oper
;
857 rep
= kzalloc(sizeof(*rep
), GFP_KERNEL
);
863 /* props being zeroed by the caller, avoid zeroing it here */
865 err
= mlx5_query_hca_vport_context(mdev
, 0, port
, 0, rep
);
869 props
->lid
= rep
->lid
;
870 props
->lmc
= rep
->lmc
;
871 props
->sm_lid
= rep
->sm_lid
;
872 props
->sm_sl
= rep
->sm_sl
;
873 props
->state
= rep
->vport_state
;
874 props
->phys_state
= rep
->port_physical_state
;
875 props
->port_cap_flags
= rep
->cap_mask1
;
876 props
->gid_tbl_len
= mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev
, gid_table_size
));
877 props
->max_msg_sz
= 1 << MLX5_CAP_GEN(mdev
, log_max_msg
);
878 props
->pkey_tbl_len
= mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev
, pkey_table_size
));
879 props
->bad_pkey_cntr
= rep
->pkey_violation_counter
;
880 props
->qkey_viol_cntr
= rep
->qkey_violation_counter
;
881 props
->subnet_timeout
= rep
->subnet_timeout
;
882 props
->init_type_reply
= rep
->init_type_reply
;
883 props
->grh_required
= rep
->grh_required
;
885 err
= mlx5_query_port_link_width_oper(mdev
, &ib_link_width_oper
, port
);
889 err
= translate_active_width(ibdev
, ib_link_width_oper
,
890 &props
->active_width
);
893 err
= mlx5_query_port_ib_proto_oper(mdev
, &props
->active_speed
, port
);
897 mlx5_query_port_max_mtu(mdev
, &max_mtu
, port
);
899 props
->max_mtu
= mlx5_mtu_to_ib_mtu(max_mtu
);
901 mlx5_query_port_oper_mtu(mdev
, &oper_mtu
, port
);
903 props
->active_mtu
= mlx5_mtu_to_ib_mtu(oper_mtu
);
905 err
= mlx5_query_port_vl_hw_cap(mdev
, &vl_hw_cap
, port
);
909 err
= translate_max_vl_num(ibdev
, vl_hw_cap
,
916 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
917 struct ib_port_attr
*props
)
919 switch (mlx5_get_vport_access_method(ibdev
)) {
920 case MLX5_VPORT_ACCESS_METHOD_MAD
:
921 return mlx5_query_mad_ifc_port(ibdev
, port
, props
);
923 case MLX5_VPORT_ACCESS_METHOD_HCA
:
924 return mlx5_query_hca_port(ibdev
, port
, props
);
926 case MLX5_VPORT_ACCESS_METHOD_NIC
:
927 return mlx5_query_port_roce(ibdev
, port
, props
);
934 static int mlx5_ib_query_gid(struct ib_device
*ibdev
, u8 port
, int index
,
937 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
938 struct mlx5_core_dev
*mdev
= dev
->mdev
;
940 switch (mlx5_get_vport_access_method(ibdev
)) {
941 case MLX5_VPORT_ACCESS_METHOD_MAD
:
942 return mlx5_query_mad_ifc_gids(ibdev
, port
, index
, gid
);
944 case MLX5_VPORT_ACCESS_METHOD_HCA
:
945 return mlx5_query_hca_vport_gid(mdev
, 0, port
, 0, index
, gid
);
953 static int mlx5_ib_query_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
956 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
957 struct mlx5_core_dev
*mdev
= dev
->mdev
;
959 switch (mlx5_get_vport_access_method(ibdev
)) {
960 case MLX5_VPORT_ACCESS_METHOD_MAD
:
961 return mlx5_query_mad_ifc_pkey(ibdev
, port
, index
, pkey
);
963 case MLX5_VPORT_ACCESS_METHOD_HCA
:
964 case MLX5_VPORT_ACCESS_METHOD_NIC
:
965 return mlx5_query_hca_vport_pkey(mdev
, 0, port
, 0, index
,
972 static int mlx5_ib_modify_device(struct ib_device
*ibdev
, int mask
,
973 struct ib_device_modify
*props
)
975 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
976 struct mlx5_reg_node_desc in
;
977 struct mlx5_reg_node_desc out
;
980 if (mask
& ~IB_DEVICE_MODIFY_NODE_DESC
)
983 if (!(mask
& IB_DEVICE_MODIFY_NODE_DESC
))
987 * If possible, pass node desc to FW, so it can generate
988 * a 144 trap. If cmd fails, just ignore.
990 memcpy(&in
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
991 err
= mlx5_core_access_reg(dev
->mdev
, &in
, sizeof(in
), &out
,
992 sizeof(out
), MLX5_REG_NODE_DESC
, 0, 1);
996 memcpy(ibdev
->node_desc
, props
->node_desc
, IB_DEVICE_NODE_DESC_MAX
);
1001 static int set_port_caps_atomic(struct mlx5_ib_dev
*dev
, u8 port_num
, u32 mask
,
1004 struct mlx5_hca_vport_context ctx
= {};
1007 err
= mlx5_query_hca_vport_context(dev
->mdev
, 0,
1012 if (~ctx
.cap_mask1_perm
& mask
) {
1013 mlx5_ib_warn(dev
, "trying to change bitmask 0x%X but change supported 0x%X\n",
1014 mask
, ctx
.cap_mask1_perm
);
1018 ctx
.cap_mask1
= value
;
1019 ctx
.cap_mask1_perm
= mask
;
1020 err
= mlx5_core_modify_hca_vport_context(dev
->mdev
, 0,
1026 static int mlx5_ib_modify_port(struct ib_device
*ibdev
, u8 port
, int mask
,
1027 struct ib_port_modify
*props
)
1029 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1030 struct ib_port_attr attr
;
1035 bool is_ib
= (mlx5_ib_port_link_layer(ibdev
, port
) ==
1036 IB_LINK_LAYER_INFINIBAND
);
1038 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
) && is_ib
) {
1039 change_mask
= props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1040 value
= ~props
->clr_port_cap_mask
| props
->set_port_cap_mask
;
1041 return set_port_caps_atomic(dev
, port
, change_mask
, value
);
1044 mutex_lock(&dev
->cap_mask_mutex
);
1046 err
= ib_query_port(ibdev
, port
, &attr
);
1050 tmp
= (attr
.port_cap_flags
| props
->set_port_cap_mask
) &
1051 ~props
->clr_port_cap_mask
;
1053 err
= mlx5_set_port_caps(dev
->mdev
, port
, tmp
);
1056 mutex_unlock(&dev
->cap_mask_mutex
);
1060 static void print_lib_caps(struct mlx5_ib_dev
*dev
, u64 caps
)
1062 mlx5_ib_dbg(dev
, "MLX5_LIB_CAP_4K_UAR = %s\n",
1063 caps
& MLX5_LIB_CAP_4K_UAR
? "y" : "n");
1066 static int calc_total_bfregs(struct mlx5_ib_dev
*dev
, bool lib_uar_4k
,
1067 struct mlx5_ib_alloc_ucontext_req_v2
*req
,
1070 int uars_per_sys_page
;
1071 int bfregs_per_sys_page
;
1072 int ref_bfregs
= req
->total_num_bfregs
;
1074 if (req
->total_num_bfregs
== 0)
1077 BUILD_BUG_ON(MLX5_MAX_BFREGS
% MLX5_NON_FP_BFREGS_IN_PAGE
);
1078 BUILD_BUG_ON(MLX5_MAX_BFREGS
< MLX5_NON_FP_BFREGS_IN_PAGE
);
1080 if (req
->total_num_bfregs
> MLX5_MAX_BFREGS
)
1083 uars_per_sys_page
= get_uars_per_sys_page(dev
, lib_uar_4k
);
1084 bfregs_per_sys_page
= uars_per_sys_page
* MLX5_NON_FP_BFREGS_PER_UAR
;
1085 req
->total_num_bfregs
= ALIGN(req
->total_num_bfregs
, bfregs_per_sys_page
);
1086 *num_sys_pages
= req
->total_num_bfregs
/ bfregs_per_sys_page
;
1088 if (req
->num_low_latency_bfregs
> req
->total_num_bfregs
- 1)
1091 mlx5_ib_dbg(dev
, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, alloated %d, using %d sys pages\n",
1092 MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? "yes" : "no",
1093 lib_uar_4k
? "yes" : "no", ref_bfregs
,
1094 req
->total_num_bfregs
, *num_sys_pages
);
1099 static int allocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1101 struct mlx5_bfreg_info
*bfregi
;
1105 bfregi
= &context
->bfregi
;
1106 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++) {
1107 err
= mlx5_cmd_alloc_uar(dev
->mdev
, &bfregi
->sys_pages
[i
]);
1111 mlx5_ib_dbg(dev
, "allocated uar %d\n", bfregi
->sys_pages
[i
]);
1116 for (--i
; i
>= 0; i
--)
1117 if (mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]))
1118 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1123 static int deallocate_uars(struct mlx5_ib_dev
*dev
, struct mlx5_ib_ucontext
*context
)
1125 struct mlx5_bfreg_info
*bfregi
;
1129 bfregi
= &context
->bfregi
;
1130 for (i
= 0; i
< bfregi
->num_sys_pages
; i
++) {
1131 err
= mlx5_cmd_free_uar(dev
->mdev
, bfregi
->sys_pages
[i
]);
1133 mlx5_ib_warn(dev
, "failed to free uar %d\n", i
);
1140 static struct ib_ucontext
*mlx5_ib_alloc_ucontext(struct ib_device
*ibdev
,
1141 struct ib_udata
*udata
)
1143 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
1144 struct mlx5_ib_alloc_ucontext_req_v2 req
= {};
1145 struct mlx5_ib_alloc_ucontext_resp resp
= {};
1146 struct mlx5_ib_ucontext
*context
;
1147 struct mlx5_bfreg_info
*bfregi
;
1151 size_t min_req_v2
= offsetof(struct mlx5_ib_alloc_ucontext_req_v2
,
1155 if (!dev
->ib_active
)
1156 return ERR_PTR(-EAGAIN
);
1158 if (udata
->inlen
< sizeof(struct ib_uverbs_cmd_hdr
))
1159 return ERR_PTR(-EINVAL
);
1161 reqlen
= udata
->inlen
- sizeof(struct ib_uverbs_cmd_hdr
);
1162 if (reqlen
== sizeof(struct mlx5_ib_alloc_ucontext_req
))
1164 else if (reqlen
>= min_req_v2
)
1167 return ERR_PTR(-EINVAL
);
1169 err
= ib_copy_from_udata(&req
, udata
, min(reqlen
, sizeof(req
)));
1171 return ERR_PTR(err
);
1174 return ERR_PTR(-EINVAL
);
1176 if (req
.comp_mask
|| req
.reserved0
|| req
.reserved1
|| req
.reserved2
)
1177 return ERR_PTR(-EOPNOTSUPP
);
1179 req
.total_num_bfregs
= ALIGN(req
.total_num_bfregs
,
1180 MLX5_NON_FP_BFREGS_PER_UAR
);
1181 if (req
.num_low_latency_bfregs
> req
.total_num_bfregs
- 1)
1182 return ERR_PTR(-EINVAL
);
1184 resp
.qp_tab_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp
);
1185 if (mlx5_core_is_pf(dev
->mdev
) && MLX5_CAP_GEN(dev
->mdev
, bf
))
1186 resp
.bf_reg_size
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
);
1187 resp
.cache_line_size
= cache_line_size();
1188 resp
.max_sq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
);
1189 resp
.max_rq_desc_sz
= MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
);
1190 resp
.max_send_wqebb
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1191 resp
.max_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
);
1192 resp
.max_srq_recv_wr
= 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_srq_sz
);
1193 resp
.cqe_version
= min_t(__u8
,
1194 (__u8
)MLX5_CAP_GEN(dev
->mdev
, cqe_version
),
1195 req
.max_cqe_version
);
1196 resp
.log_uar_size
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1197 MLX5_ADAPTER_PAGE_SHIFT
: PAGE_SHIFT
;
1198 resp
.num_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1199 MLX5_CAP_GEN(dev
->mdev
, num_of_uars_per_page
) : 1;
1200 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
1201 sizeof(resp
.response_length
), udata
->outlen
);
1203 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
1205 return ERR_PTR(-ENOMEM
);
1207 lib_uar_4k
= req
.lib_caps
& MLX5_LIB_CAP_4K_UAR
;
1208 bfregi
= &context
->bfregi
;
1210 /* updates req->total_num_bfregs */
1211 err
= calc_total_bfregs(dev
, lib_uar_4k
, &req
, &bfregi
->num_sys_pages
);
1215 mutex_init(&bfregi
->lock
);
1216 bfregi
->lib_uar_4k
= lib_uar_4k
;
1217 bfregi
->count
= kcalloc(req
.total_num_bfregs
, sizeof(*bfregi
->count
),
1219 if (!bfregi
->count
) {
1224 bfregi
->sys_pages
= kcalloc(bfregi
->num_sys_pages
,
1225 sizeof(*bfregi
->sys_pages
),
1227 if (!bfregi
->sys_pages
) {
1232 err
= allocate_uars(dev
, context
);
1236 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1237 context
->ibucontext
.invalidate_range
= &mlx5_ib_invalidate_range
;
1240 context
->upd_xlt_page
= __get_free_page(GFP_KERNEL
);
1241 if (!context
->upd_xlt_page
) {
1245 mutex_init(&context
->upd_xlt_page_mutex
);
1247 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
)) {
1248 err
= mlx5_core_alloc_transport_domain(dev
->mdev
,
1254 INIT_LIST_HEAD(&context
->vma_private_list
);
1255 INIT_LIST_HEAD(&context
->db_page_list
);
1256 mutex_init(&context
->db_page_mutex
);
1258 resp
.tot_bfregs
= req
.total_num_bfregs
;
1259 resp
.num_ports
= MLX5_CAP_GEN(dev
->mdev
, num_ports
);
1261 if (field_avail(typeof(resp
), cqe_version
, udata
->outlen
))
1262 resp
.response_length
+= sizeof(resp
.cqe_version
);
1264 if (field_avail(typeof(resp
), cmds_supp_uhw
, udata
->outlen
)) {
1265 resp
.cmds_supp_uhw
|= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE
|
1266 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH
;
1267 resp
.response_length
+= sizeof(resp
.cmds_supp_uhw
);
1270 if (field_avail(typeof(resp
), eth_min_inline
, udata
->outlen
)) {
1271 if (mlx5_ib_port_link_layer(ibdev
, 1) == IB_LINK_LAYER_ETHERNET
) {
1272 mlx5_query_min_inline(dev
->mdev
, &resp
.eth_min_inline
);
1273 resp
.eth_min_inline
++;
1275 resp
.response_length
+= sizeof(resp
.eth_min_inline
);
1279 * We don't want to expose information from the PCI bar that is located
1280 * after 4096 bytes, so if the arch only supports larger pages, let's
1281 * pretend we don't support reading the HCA's core clock. This is also
1282 * forced by mmap function.
1284 if (field_avail(typeof(resp
), hca_core_clock_offset
, udata
->outlen
)) {
1285 if (PAGE_SIZE
<= 4096) {
1287 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET
;
1288 resp
.hca_core_clock_offset
=
1289 offsetof(struct mlx5_init_seg
, internal_timer_h
) % PAGE_SIZE
;
1291 resp
.response_length
+= sizeof(resp
.hca_core_clock_offset
) +
1292 sizeof(resp
.reserved2
);
1295 if (field_avail(typeof(resp
), log_uar_size
, udata
->outlen
))
1296 resp
.response_length
+= sizeof(resp
.log_uar_size
);
1298 if (field_avail(typeof(resp
), num_uars_per_page
, udata
->outlen
))
1299 resp
.response_length
+= sizeof(resp
.num_uars_per_page
);
1301 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1306 bfregi
->num_low_latency_bfregs
= req
.num_low_latency_bfregs
;
1307 context
->cqe_version
= resp
.cqe_version
;
1308 context
->lib_caps
= req
.lib_caps
;
1309 print_lib_caps(dev
, context
->lib_caps
);
1311 return &context
->ibucontext
;
1314 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1315 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1318 free_page(context
->upd_xlt_page
);
1321 deallocate_uars(dev
, context
);
1324 kfree(bfregi
->sys_pages
);
1327 kfree(bfregi
->count
);
1332 return ERR_PTR(err
);
1335 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext
*ibcontext
)
1337 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1338 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1339 struct mlx5_bfreg_info
*bfregi
;
1341 bfregi
= &context
->bfregi
;
1342 if (MLX5_CAP_GEN(dev
->mdev
, log_max_transport_domain
))
1343 mlx5_core_dealloc_transport_domain(dev
->mdev
, context
->tdn
);
1345 free_page(context
->upd_xlt_page
);
1346 deallocate_uars(dev
, context
);
1347 kfree(bfregi
->sys_pages
);
1348 kfree(bfregi
->count
);
1354 static phys_addr_t
uar_index2pfn(struct mlx5_ib_dev
*dev
,
1355 struct mlx5_bfreg_info
*bfregi
,
1358 int fw_uars_per_page
;
1360 fw_uars_per_page
= MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ? MLX5_UARS_IN_PAGE
: 1;
1362 return (pci_resource_start(dev
->mdev
->pdev
, 0) >> PAGE_SHIFT
) +
1363 bfregi
->sys_pages
[idx
] / fw_uars_per_page
;
1366 static int get_command(unsigned long offset
)
1368 return (offset
>> MLX5_IB_MMAP_CMD_SHIFT
) & MLX5_IB_MMAP_CMD_MASK
;
1371 static int get_arg(unsigned long offset
)
1373 return offset
& ((1 << MLX5_IB_MMAP_CMD_SHIFT
) - 1);
1376 static int get_index(unsigned long offset
)
1378 return get_arg(offset
);
1381 static void mlx5_ib_vma_open(struct vm_area_struct
*area
)
1383 /* vma_open is called when a new VMA is created on top of our VMA. This
1384 * is done through either mremap flow or split_vma (usually due to
1385 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1386 * as this VMA is strongly hardware related. Therefore we set the
1387 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1388 * calling us again and trying to do incorrect actions. We assume that
1389 * the original VMA size is exactly a single page, and therefore all
1390 * "splitting" operation will not happen to it.
1392 area
->vm_ops
= NULL
;
1395 static void mlx5_ib_vma_close(struct vm_area_struct
*area
)
1397 struct mlx5_ib_vma_private_data
*mlx5_ib_vma_priv_data
;
1399 /* It's guaranteed that all VMAs opened on a FD are closed before the
1400 * file itself is closed, therefore no sync is needed with the regular
1401 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1402 * However need a sync with accessing the vma as part of
1403 * mlx5_ib_disassociate_ucontext.
1404 * The close operation is usually called under mm->mmap_sem except when
1405 * process is exiting.
1406 * The exiting case is handled explicitly as part of
1407 * mlx5_ib_disassociate_ucontext.
1409 mlx5_ib_vma_priv_data
= (struct mlx5_ib_vma_private_data
*)area
->vm_private_data
;
1411 /* setting the vma context pointer to null in the mlx5_ib driver's
1412 * private data, to protect a race condition in
1413 * mlx5_ib_disassociate_ucontext().
1415 mlx5_ib_vma_priv_data
->vma
= NULL
;
1416 list_del(&mlx5_ib_vma_priv_data
->list
);
1417 kfree(mlx5_ib_vma_priv_data
);
1420 static const struct vm_operations_struct mlx5_ib_vm_ops
= {
1421 .open
= mlx5_ib_vma_open
,
1422 .close
= mlx5_ib_vma_close
1425 static int mlx5_ib_set_vma_data(struct vm_area_struct
*vma
,
1426 struct mlx5_ib_ucontext
*ctx
)
1428 struct mlx5_ib_vma_private_data
*vma_prv
;
1429 struct list_head
*vma_head
= &ctx
->vma_private_list
;
1431 vma_prv
= kzalloc(sizeof(*vma_prv
), GFP_KERNEL
);
1436 vma
->vm_private_data
= vma_prv
;
1437 vma
->vm_ops
= &mlx5_ib_vm_ops
;
1439 list_add(&vma_prv
->list
, vma_head
);
1444 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext
*ibcontext
)
1447 struct vm_area_struct
*vma
;
1448 struct mlx5_ib_vma_private_data
*vma_private
, *n
;
1449 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1450 struct task_struct
*owning_process
= NULL
;
1451 struct mm_struct
*owning_mm
= NULL
;
1453 owning_process
= get_pid_task(ibcontext
->tgid
, PIDTYPE_PID
);
1454 if (!owning_process
)
1457 owning_mm
= get_task_mm(owning_process
);
1459 pr_info("no mm, disassociate ucontext is pending task termination\n");
1461 put_task_struct(owning_process
);
1462 usleep_range(1000, 2000);
1463 owning_process
= get_pid_task(ibcontext
->tgid
,
1465 if (!owning_process
||
1466 owning_process
->state
== TASK_DEAD
) {
1467 pr_info("disassociate ucontext done, task was terminated\n");
1468 /* in case task was dead need to release the
1472 put_task_struct(owning_process
);
1478 /* need to protect from a race on closing the vma as part of
1479 * mlx5_ib_vma_close.
1481 down_write(&owning_mm
->mmap_sem
);
1482 list_for_each_entry_safe(vma_private
, n
, &context
->vma_private_list
,
1484 vma
= vma_private
->vma
;
1485 ret
= zap_vma_ptes(vma
, vma
->vm_start
,
1487 WARN_ONCE(ret
, "%s: zap_vma_ptes failed", __func__
);
1488 /* context going to be destroyed, should
1489 * not access ops any more.
1491 vma
->vm_flags
&= ~(VM_SHARED
| VM_MAYSHARE
);
1493 list_del(&vma_private
->list
);
1496 up_write(&owning_mm
->mmap_sem
);
1498 put_task_struct(owning_process
);
1501 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd
)
1504 case MLX5_IB_MMAP_WC_PAGE
:
1506 case MLX5_IB_MMAP_REGULAR_PAGE
:
1507 return "best effort WC";
1508 case MLX5_IB_MMAP_NC_PAGE
:
1515 static int uar_mmap(struct mlx5_ib_dev
*dev
, enum mlx5_ib_mmap_cmd cmd
,
1516 struct vm_area_struct
*vma
,
1517 struct mlx5_ib_ucontext
*context
)
1519 struct mlx5_bfreg_info
*bfregi
= &context
->bfregi
;
1522 phys_addr_t pfn
, pa
;
1526 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1529 uars_per_page
= get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
);
1530 idx
= get_index(vma
->vm_pgoff
);
1531 if (idx
% uars_per_page
||
1532 idx
* uars_per_page
>= bfregi
->num_sys_pages
) {
1533 mlx5_ib_warn(dev
, "invalid uar index %lu\n", idx
);
1538 case MLX5_IB_MMAP_WC_PAGE
:
1539 /* Some architectures don't support WC memory */
1540 #if defined(CONFIG_X86)
1543 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
1547 case MLX5_IB_MMAP_REGULAR_PAGE
:
1548 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
1549 prot
= pgprot_writecombine(vma
->vm_page_prot
);
1551 case MLX5_IB_MMAP_NC_PAGE
:
1552 prot
= pgprot_noncached(vma
->vm_page_prot
);
1558 pfn
= uar_index2pfn(dev
, bfregi
, idx
);
1559 mlx5_ib_dbg(dev
, "uar idx 0x%lx, pfn %pa\n", idx
, &pfn
);
1561 vma
->vm_page_prot
= prot
;
1562 err
= io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1563 PAGE_SIZE
, vma
->vm_page_prot
);
1565 mlx5_ib_err(dev
, "io_remap_pfn_range failed with error=%d, vm_start=0x%lx, pfn=%pa, mmap_cmd=%s\n",
1566 err
, vma
->vm_start
, &pfn
, mmap_cmd2str(cmd
));
1570 pa
= pfn
<< PAGE_SHIFT
;
1571 mlx5_ib_dbg(dev
, "mapped %s at 0x%lx, PA %pa\n", mmap_cmd2str(cmd
),
1572 vma
->vm_start
, &pa
);
1574 return mlx5_ib_set_vma_data(vma
, context
);
1577 static int mlx5_ib_mmap(struct ib_ucontext
*ibcontext
, struct vm_area_struct
*vma
)
1579 struct mlx5_ib_ucontext
*context
= to_mucontext(ibcontext
);
1580 struct mlx5_ib_dev
*dev
= to_mdev(ibcontext
->device
);
1581 unsigned long command
;
1584 command
= get_command(vma
->vm_pgoff
);
1586 case MLX5_IB_MMAP_WC_PAGE
:
1587 case MLX5_IB_MMAP_NC_PAGE
:
1588 case MLX5_IB_MMAP_REGULAR_PAGE
:
1589 return uar_mmap(dev
, command
, vma
, context
);
1591 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
:
1594 case MLX5_IB_MMAP_CORE_CLOCK
:
1595 if (vma
->vm_end
- vma
->vm_start
!= PAGE_SIZE
)
1598 if (vma
->vm_flags
& VM_WRITE
)
1601 /* Don't expose to user-space information it shouldn't have */
1602 if (PAGE_SIZE
> 4096)
1605 vma
->vm_page_prot
= pgprot_noncached(vma
->vm_page_prot
);
1606 pfn
= (dev
->mdev
->iseg_base
+
1607 offsetof(struct mlx5_init_seg
, internal_timer_h
)) >>
1609 if (io_remap_pfn_range(vma
, vma
->vm_start
, pfn
,
1610 PAGE_SIZE
, vma
->vm_page_prot
))
1613 mlx5_ib_dbg(dev
, "mapped internal timer at 0x%lx, PA 0x%llx\n",
1615 (unsigned long long)pfn
<< PAGE_SHIFT
);
1625 static struct ib_pd
*mlx5_ib_alloc_pd(struct ib_device
*ibdev
,
1626 struct ib_ucontext
*context
,
1627 struct ib_udata
*udata
)
1629 struct mlx5_ib_alloc_pd_resp resp
;
1630 struct mlx5_ib_pd
*pd
;
1633 pd
= kmalloc(sizeof(*pd
), GFP_KERNEL
);
1635 return ERR_PTR(-ENOMEM
);
1637 err
= mlx5_core_alloc_pd(to_mdev(ibdev
)->mdev
, &pd
->pdn
);
1640 return ERR_PTR(err
);
1645 if (ib_copy_to_udata(udata
, &resp
, sizeof(resp
))) {
1646 mlx5_core_dealloc_pd(to_mdev(ibdev
)->mdev
, pd
->pdn
);
1648 return ERR_PTR(-EFAULT
);
1655 static int mlx5_ib_dealloc_pd(struct ib_pd
*pd
)
1657 struct mlx5_ib_dev
*mdev
= to_mdev(pd
->device
);
1658 struct mlx5_ib_pd
*mpd
= to_mpd(pd
);
1660 mlx5_core_dealloc_pd(mdev
->mdev
, mpd
->pdn
);
1667 MATCH_CRITERIA_ENABLE_OUTER_BIT
,
1668 MATCH_CRITERIA_ENABLE_MISC_BIT
,
1669 MATCH_CRITERIA_ENABLE_INNER_BIT
1672 #define HEADER_IS_ZERO(match_criteria, headers) \
1673 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
1674 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
1676 static u8 get_match_criteria_enable(u32 *match_criteria)
1678 u8 match_criteria_enable
;
1680 match_criteria_enable
=
1681 (!HEADER_IS_ZERO(match_criteria
, outer_headers
)) <<
1682 MATCH_CRITERIA_ENABLE_OUTER_BIT
;
1683 match_criteria_enable
|=
1684 (!HEADER_IS_ZERO(match_criteria
, misc_parameters
)) <<
1685 MATCH_CRITERIA_ENABLE_MISC_BIT
;
1686 match_criteria_enable
|=
1687 (!HEADER_IS_ZERO(match_criteria
, inner_headers
)) <<
1688 MATCH_CRITERIA_ENABLE_INNER_BIT
;
1690 return match_criteria_enable
;
1693 static void set_proto(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
1695 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_protocol
, mask
);
1696 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_protocol
, val
);
1699 static void set_flow_label(void *misc_c
, void *misc_v
, u8 mask
, u8 val
,
1703 MLX5_SET(fte_match_set_misc
,
1704 misc_c
, inner_ipv6_flow_label
, mask
);
1705 MLX5_SET(fte_match_set_misc
,
1706 misc_v
, inner_ipv6_flow_label
, val
);
1708 MLX5_SET(fte_match_set_misc
,
1709 misc_c
, outer_ipv6_flow_label
, mask
);
1710 MLX5_SET(fte_match_set_misc
,
1711 misc_v
, outer_ipv6_flow_label
, val
);
1715 static void set_tos(void *outer_c
, void *outer_v
, u8 mask
, u8 val
)
1717 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_ecn
, mask
);
1718 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_ecn
, val
);
1719 MLX5_SET(fte_match_set_lyr_2_4
, outer_c
, ip_dscp
, mask
>> 2);
1720 MLX5_SET(fte_match_set_lyr_2_4
, outer_v
, ip_dscp
, val
>> 2);
1723 #define LAST_ETH_FIELD vlan_tag
1724 #define LAST_IB_FIELD sl
1725 #define LAST_IPV4_FIELD tos
1726 #define LAST_IPV6_FIELD traffic_class
1727 #define LAST_TCP_UDP_FIELD src_port
1728 #define LAST_TUNNEL_FIELD tunnel_id
1729 #define LAST_FLOW_TAG_FIELD tag_id
1731 /* Field is the last supported field */
1732 #define FIELDS_NOT_SUPPORTED(filter, field)\
1733 memchr_inv((void *)&filter.field +\
1734 sizeof(filter.field), 0,\
1736 offsetof(typeof(filter), field) -\
1737 sizeof(filter.field))
1739 static int parse_flow_attr(u32
*match_c
, u32
*match_v
,
1740 const union ib_flow_spec
*ib_spec
, u32
*tag_id
)
1742 void *misc_params_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1744 void *misc_params_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1749 if (ib_spec
->type
& IB_FLOW_SPEC_INNER
) {
1750 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1752 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1755 headers_c
= MLX5_ADDR_OF(fte_match_param
, match_c
,
1757 headers_v
= MLX5_ADDR_OF(fte_match_param
, match_v
,
1761 switch (ib_spec
->type
& ~IB_FLOW_SPEC_INNER
) {
1762 case IB_FLOW_SPEC_ETH
:
1763 if (FIELDS_NOT_SUPPORTED(ib_spec
->eth
.mask
, LAST_ETH_FIELD
))
1766 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1768 ib_spec
->eth
.mask
.dst_mac
);
1769 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1771 ib_spec
->eth
.val
.dst_mac
);
1773 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1775 ib_spec
->eth
.mask
.src_mac
);
1776 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1778 ib_spec
->eth
.val
.src_mac
);
1780 if (ib_spec
->eth
.mask
.vlan_tag
) {
1781 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1783 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1786 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1787 first_vid
, ntohs(ib_spec
->eth
.mask
.vlan_tag
));
1788 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1789 first_vid
, ntohs(ib_spec
->eth
.val
.vlan_tag
));
1791 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1793 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 12);
1794 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1796 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 12);
1798 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1800 ntohs(ib_spec
->eth
.mask
.vlan_tag
) >> 13);
1801 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1803 ntohs(ib_spec
->eth
.val
.vlan_tag
) >> 13);
1805 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1806 ethertype
, ntohs(ib_spec
->eth
.mask
.ether_type
));
1807 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1808 ethertype
, ntohs(ib_spec
->eth
.val
.ether_type
));
1810 case IB_FLOW_SPEC_IPV4
:
1811 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv4
.mask
, LAST_IPV4_FIELD
))
1814 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1816 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1817 ethertype
, ETH_P_IP
);
1819 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1820 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1821 &ib_spec
->ipv4
.mask
.src_ip
,
1822 sizeof(ib_spec
->ipv4
.mask
.src_ip
));
1823 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1824 src_ipv4_src_ipv6
.ipv4_layout
.ipv4
),
1825 &ib_spec
->ipv4
.val
.src_ip
,
1826 sizeof(ib_spec
->ipv4
.val
.src_ip
));
1827 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1828 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1829 &ib_spec
->ipv4
.mask
.dst_ip
,
1830 sizeof(ib_spec
->ipv4
.mask
.dst_ip
));
1831 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1832 dst_ipv4_dst_ipv6
.ipv4_layout
.ipv4
),
1833 &ib_spec
->ipv4
.val
.dst_ip
,
1834 sizeof(ib_spec
->ipv4
.val
.dst_ip
));
1836 set_tos(headers_c
, headers_v
,
1837 ib_spec
->ipv4
.mask
.tos
, ib_spec
->ipv4
.val
.tos
);
1839 set_proto(headers_c
, headers_v
,
1840 ib_spec
->ipv4
.mask
.proto
, ib_spec
->ipv4
.val
.proto
);
1842 case IB_FLOW_SPEC_IPV6
:
1843 if (FIELDS_NOT_SUPPORTED(ib_spec
->ipv6
.mask
, LAST_IPV6_FIELD
))
1846 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
,
1848 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
,
1849 ethertype
, ETH_P_IPV6
);
1851 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1852 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1853 &ib_spec
->ipv6
.mask
.src_ip
,
1854 sizeof(ib_spec
->ipv6
.mask
.src_ip
));
1855 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1856 src_ipv4_src_ipv6
.ipv6_layout
.ipv6
),
1857 &ib_spec
->ipv6
.val
.src_ip
,
1858 sizeof(ib_spec
->ipv6
.val
.src_ip
));
1859 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_c
,
1860 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1861 &ib_spec
->ipv6
.mask
.dst_ip
,
1862 sizeof(ib_spec
->ipv6
.mask
.dst_ip
));
1863 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4
, headers_v
,
1864 dst_ipv4_dst_ipv6
.ipv6_layout
.ipv6
),
1865 &ib_spec
->ipv6
.val
.dst_ip
,
1866 sizeof(ib_spec
->ipv6
.val
.dst_ip
));
1868 set_tos(headers_c
, headers_v
,
1869 ib_spec
->ipv6
.mask
.traffic_class
,
1870 ib_spec
->ipv6
.val
.traffic_class
);
1872 set_proto(headers_c
, headers_v
,
1873 ib_spec
->ipv6
.mask
.next_hdr
,
1874 ib_spec
->ipv6
.val
.next_hdr
);
1876 set_flow_label(misc_params_c
, misc_params_v
,
1877 ntohl(ib_spec
->ipv6
.mask
.flow_label
),
1878 ntohl(ib_spec
->ipv6
.val
.flow_label
),
1879 ib_spec
->type
& IB_FLOW_SPEC_INNER
);
1882 case IB_FLOW_SPEC_TCP
:
1883 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
1884 LAST_TCP_UDP_FIELD
))
1887 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
1889 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
1892 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_sport
,
1893 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1894 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_sport
,
1895 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1897 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, tcp_dport
,
1898 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1899 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, tcp_dport
,
1900 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1902 case IB_FLOW_SPEC_UDP
:
1903 if (FIELDS_NOT_SUPPORTED(ib_spec
->tcp_udp
.mask
,
1904 LAST_TCP_UDP_FIELD
))
1907 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, ip_protocol
,
1909 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, ip_protocol
,
1912 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_sport
,
1913 ntohs(ib_spec
->tcp_udp
.mask
.src_port
));
1914 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_sport
,
1915 ntohs(ib_spec
->tcp_udp
.val
.src_port
));
1917 MLX5_SET(fte_match_set_lyr_2_4
, headers_c
, udp_dport
,
1918 ntohs(ib_spec
->tcp_udp
.mask
.dst_port
));
1919 MLX5_SET(fte_match_set_lyr_2_4
, headers_v
, udp_dport
,
1920 ntohs(ib_spec
->tcp_udp
.val
.dst_port
));
1922 case IB_FLOW_SPEC_VXLAN_TUNNEL
:
1923 if (FIELDS_NOT_SUPPORTED(ib_spec
->tunnel
.mask
,
1927 MLX5_SET(fte_match_set_misc
, misc_params_c
, vxlan_vni
,
1928 ntohl(ib_spec
->tunnel
.mask
.tunnel_id
));
1929 MLX5_SET(fte_match_set_misc
, misc_params_v
, vxlan_vni
,
1930 ntohl(ib_spec
->tunnel
.val
.tunnel_id
));
1932 case IB_FLOW_SPEC_ACTION_TAG
:
1933 if (FIELDS_NOT_SUPPORTED(ib_spec
->flow_tag
,
1934 LAST_FLOW_TAG_FIELD
))
1936 if (ib_spec
->flow_tag
.tag_id
>= BIT(24))
1939 *tag_id
= ib_spec
->flow_tag
.tag_id
;
1948 /* If a flow could catch both multicast and unicast packets,
1949 * it won't fall into the multicast flow steering table and this rule
1950 * could steal other multicast packets.
1952 static bool flow_is_multicast_only(struct ib_flow_attr
*ib_attr
)
1954 struct ib_flow_spec_eth
*eth_spec
;
1956 if (ib_attr
->type
!= IB_FLOW_ATTR_NORMAL
||
1957 ib_attr
->size
< sizeof(struct ib_flow_attr
) +
1958 sizeof(struct ib_flow_spec_eth
) ||
1959 ib_attr
->num_of_specs
< 1)
1962 eth_spec
= (struct ib_flow_spec_eth
*)(ib_attr
+ 1);
1963 if (eth_spec
->type
!= IB_FLOW_SPEC_ETH
||
1964 eth_spec
->size
!= sizeof(*eth_spec
))
1967 return is_multicast_ether_addr(eth_spec
->mask
.dst_mac
) &&
1968 is_multicast_ether_addr(eth_spec
->val
.dst_mac
);
1971 static bool is_valid_ethertype(const struct ib_flow_attr
*flow_attr
,
1974 union ib_flow_spec
*ib_spec
= (union ib_flow_spec
*)(flow_attr
+ 1);
1975 int inner_bit
= check_inner
? IB_FLOW_SPEC_INNER
: 0;
1976 bool ipv4_spec_valid
, ipv6_spec_valid
;
1977 unsigned int ip_spec_type
= 0;
1978 bool has_ethertype
= false;
1979 unsigned int spec_index
;
1980 bool mask_valid
= true;
1984 /* Validate that ethertype is correct */
1985 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
1986 if ((ib_spec
->type
== (IB_FLOW_SPEC_ETH
| inner_bit
)) &&
1987 ib_spec
->eth
.mask
.ether_type
) {
1988 mask_valid
= (ib_spec
->eth
.mask
.ether_type
==
1990 has_ethertype
= true;
1991 eth_type
= ntohs(ib_spec
->eth
.val
.ether_type
);
1992 } else if ((ib_spec
->type
== (IB_FLOW_SPEC_IPV4
| inner_bit
)) ||
1993 (ib_spec
->type
== (IB_FLOW_SPEC_IPV6
| inner_bit
))) {
1994 ip_spec_type
= ib_spec
->type
;
1996 ib_spec
= (void *)ib_spec
+ ib_spec
->size
;
1999 type_valid
= (!has_ethertype
) || (!ip_spec_type
);
2000 if (!type_valid
&& mask_valid
) {
2001 ipv4_spec_valid
= (eth_type
== ETH_P_IP
) &&
2002 (ip_spec_type
== (IB_FLOW_SPEC_IPV4
| inner_bit
));
2003 ipv6_spec_valid
= (eth_type
== ETH_P_IPV6
) &&
2004 (ip_spec_type
== (IB_FLOW_SPEC_IPV6
| inner_bit
));
2005 type_valid
= ipv4_spec_valid
|| ipv6_spec_valid
;
2011 static bool is_valid_attr(const struct ib_flow_attr
*flow_attr
)
2013 return is_valid_ethertype(flow_attr
, false) &&
2014 is_valid_ethertype(flow_attr
, true);
2017 static void put_flow_table(struct mlx5_ib_dev
*dev
,
2018 struct mlx5_ib_flow_prio
*prio
, bool ft_added
)
2020 prio
->refcount
-= !!ft_added
;
2021 if (!prio
->refcount
) {
2022 mlx5_destroy_flow_table(prio
->flow_table
);
2023 prio
->flow_table
= NULL
;
2027 static int mlx5_ib_destroy_flow(struct ib_flow
*flow_id
)
2029 struct mlx5_ib_dev
*dev
= to_mdev(flow_id
->qp
->device
);
2030 struct mlx5_ib_flow_handler
*handler
= container_of(flow_id
,
2031 struct mlx5_ib_flow_handler
,
2033 struct mlx5_ib_flow_handler
*iter
, *tmp
;
2035 mutex_lock(&dev
->flow_db
.lock
);
2037 list_for_each_entry_safe(iter
, tmp
, &handler
->list
, list
) {
2038 mlx5_del_flow_rules(iter
->rule
);
2039 put_flow_table(dev
, iter
->prio
, true);
2040 list_del(&iter
->list
);
2044 mlx5_del_flow_rules(handler
->rule
);
2045 put_flow_table(dev
, handler
->prio
, true);
2046 mutex_unlock(&dev
->flow_db
.lock
);
2053 static int ib_prio_to_core_prio(unsigned int priority
, bool dont_trap
)
2061 enum flow_table_type
{
2066 #define MLX5_FS_MAX_TYPES 6
2067 #define MLX5_FS_MAX_ENTRIES BIT(16)
2068 static struct mlx5_ib_flow_prio
*get_flow_table(struct mlx5_ib_dev
*dev
,
2069 struct ib_flow_attr
*flow_attr
,
2070 enum flow_table_type ft_type
)
2072 bool dont_trap
= flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
;
2073 struct mlx5_flow_namespace
*ns
= NULL
;
2074 struct mlx5_ib_flow_prio
*prio
;
2075 struct mlx5_flow_table
*ft
;
2082 max_table_size
= BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev
->mdev
,
2084 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
2085 if (flow_is_multicast_only(flow_attr
) &&
2087 priority
= MLX5_IB_FLOW_MCAST_PRIO
;
2089 priority
= ib_prio_to_core_prio(flow_attr
->priority
,
2091 ns
= mlx5_get_flow_namespace(dev
->mdev
,
2092 MLX5_FLOW_NAMESPACE_BYPASS
);
2093 num_entries
= MLX5_FS_MAX_ENTRIES
;
2094 num_groups
= MLX5_FS_MAX_TYPES
;
2095 prio
= &dev
->flow_db
.prios
[priority
];
2096 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2097 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
2098 ns
= mlx5_get_flow_namespace(dev
->mdev
,
2099 MLX5_FLOW_NAMESPACE_LEFTOVERS
);
2100 build_leftovers_ft_param(&priority
,
2103 prio
= &dev
->flow_db
.prios
[MLX5_IB_FLOW_LEFTOVERS_PRIO
];
2104 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2105 if (!MLX5_CAP_FLOWTABLE(dev
->mdev
,
2106 allow_sniffer_and_nic_rx_shared_tir
))
2107 return ERR_PTR(-ENOTSUPP
);
2109 ns
= mlx5_get_flow_namespace(dev
->mdev
, ft_type
== MLX5_IB_FT_RX
?
2110 MLX5_FLOW_NAMESPACE_SNIFFER_RX
:
2111 MLX5_FLOW_NAMESPACE_SNIFFER_TX
);
2113 prio
= &dev
->flow_db
.sniffer
[ft_type
];
2120 return ERR_PTR(-ENOTSUPP
);
2122 if (num_entries
> max_table_size
)
2123 return ERR_PTR(-ENOMEM
);
2125 ft
= prio
->flow_table
;
2127 ft
= mlx5_create_auto_grouped_flow_table(ns
, priority
,
2134 prio
->flow_table
= ft
;
2140 return err
? ERR_PTR(err
) : prio
;
2143 static struct mlx5_ib_flow_handler
*create_flow_rule(struct mlx5_ib_dev
*dev
,
2144 struct mlx5_ib_flow_prio
*ft_prio
,
2145 const struct ib_flow_attr
*flow_attr
,
2146 struct mlx5_flow_destination
*dst
)
2148 struct mlx5_flow_table
*ft
= ft_prio
->flow_table
;
2149 struct mlx5_ib_flow_handler
*handler
;
2150 struct mlx5_flow_act flow_act
= {0};
2151 struct mlx5_flow_spec
*spec
;
2152 const void *ib_flow
= (const void *)flow_attr
+ sizeof(*flow_attr
);
2153 unsigned int spec_index
;
2154 u32 flow_tag
= MLX5_FS_DEFAULT_FLOW_TAG
;
2157 if (!is_valid_attr(flow_attr
))
2158 return ERR_PTR(-EINVAL
);
2160 spec
= mlx5_vzalloc(sizeof(*spec
));
2161 handler
= kzalloc(sizeof(*handler
), GFP_KERNEL
);
2162 if (!handler
|| !spec
) {
2167 INIT_LIST_HEAD(&handler
->list
);
2169 for (spec_index
= 0; spec_index
< flow_attr
->num_of_specs
; spec_index
++) {
2170 err
= parse_flow_attr(spec
->match_criteria
,
2171 spec
->match_value
, ib_flow
, &flow_tag
);
2175 ib_flow
+= ((union ib_flow_spec
*)ib_flow
)->size
;
2178 spec
->match_criteria_enable
= get_match_criteria_enable(spec
->match_criteria
);
2179 flow_act
.action
= dst
? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST
:
2180 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO
;
2182 if (flow_tag
!= MLX5_FS_DEFAULT_FLOW_TAG
&&
2183 (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2184 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
)) {
2185 mlx5_ib_warn(dev
, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
2186 flow_tag
, flow_attr
->type
);
2190 flow_act
.flow_tag
= flow_tag
;
2191 handler
->rule
= mlx5_add_flow_rules(ft
, spec
,
2195 if (IS_ERR(handler
->rule
)) {
2196 err
= PTR_ERR(handler
->rule
);
2200 ft_prio
->refcount
++;
2201 handler
->prio
= ft_prio
;
2203 ft_prio
->flow_table
= ft
;
2208 return err
? ERR_PTR(err
) : handler
;
2211 static struct mlx5_ib_flow_handler
*create_dont_trap_rule(struct mlx5_ib_dev
*dev
,
2212 struct mlx5_ib_flow_prio
*ft_prio
,
2213 struct ib_flow_attr
*flow_attr
,
2214 struct mlx5_flow_destination
*dst
)
2216 struct mlx5_ib_flow_handler
*handler_dst
= NULL
;
2217 struct mlx5_ib_flow_handler
*handler
= NULL
;
2219 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
, NULL
);
2220 if (!IS_ERR(handler
)) {
2221 handler_dst
= create_flow_rule(dev
, ft_prio
,
2223 if (IS_ERR(handler_dst
)) {
2224 mlx5_del_flow_rules(handler
->rule
);
2225 ft_prio
->refcount
--;
2227 handler
= handler_dst
;
2229 list_add(&handler_dst
->list
, &handler
->list
);
2240 static struct mlx5_ib_flow_handler
*create_leftovers_rule(struct mlx5_ib_dev
*dev
,
2241 struct mlx5_ib_flow_prio
*ft_prio
,
2242 struct ib_flow_attr
*flow_attr
,
2243 struct mlx5_flow_destination
*dst
)
2245 struct mlx5_ib_flow_handler
*handler_ucast
= NULL
;
2246 struct mlx5_ib_flow_handler
*handler
= NULL
;
2249 struct ib_flow_attr flow_attr
;
2250 struct ib_flow_spec_eth eth_flow
;
2251 } leftovers_specs
[] = {
2255 .size
= sizeof(leftovers_specs
[0])
2258 .type
= IB_FLOW_SPEC_ETH
,
2259 .size
= sizeof(struct ib_flow_spec_eth
),
2260 .mask
= {.dst_mac
= {0x1} },
2261 .val
= {.dst_mac
= {0x1} }
2267 .size
= sizeof(leftovers_specs
[0])
2270 .type
= IB_FLOW_SPEC_ETH
,
2271 .size
= sizeof(struct ib_flow_spec_eth
),
2272 .mask
= {.dst_mac
= {0x1} },
2273 .val
= {.dst_mac
= {} }
2278 handler
= create_flow_rule(dev
, ft_prio
,
2279 &leftovers_specs
[LEFTOVERS_MC
].flow_attr
,
2281 if (!IS_ERR(handler
) &&
2282 flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
) {
2283 handler_ucast
= create_flow_rule(dev
, ft_prio
,
2284 &leftovers_specs
[LEFTOVERS_UC
].flow_attr
,
2286 if (IS_ERR(handler_ucast
)) {
2287 mlx5_del_flow_rules(handler
->rule
);
2288 ft_prio
->refcount
--;
2290 handler
= handler_ucast
;
2292 list_add(&handler_ucast
->list
, &handler
->list
);
2299 static struct mlx5_ib_flow_handler
*create_sniffer_rule(struct mlx5_ib_dev
*dev
,
2300 struct mlx5_ib_flow_prio
*ft_rx
,
2301 struct mlx5_ib_flow_prio
*ft_tx
,
2302 struct mlx5_flow_destination
*dst
)
2304 struct mlx5_ib_flow_handler
*handler_rx
;
2305 struct mlx5_ib_flow_handler
*handler_tx
;
2307 static const struct ib_flow_attr flow_attr
= {
2309 .size
= sizeof(flow_attr
)
2312 handler_rx
= create_flow_rule(dev
, ft_rx
, &flow_attr
, dst
);
2313 if (IS_ERR(handler_rx
)) {
2314 err
= PTR_ERR(handler_rx
);
2318 handler_tx
= create_flow_rule(dev
, ft_tx
, &flow_attr
, dst
);
2319 if (IS_ERR(handler_tx
)) {
2320 err
= PTR_ERR(handler_tx
);
2324 list_add(&handler_tx
->list
, &handler_rx
->list
);
2329 mlx5_del_flow_rules(handler_rx
->rule
);
2333 return ERR_PTR(err
);
2336 static struct ib_flow
*mlx5_ib_create_flow(struct ib_qp
*qp
,
2337 struct ib_flow_attr
*flow_attr
,
2340 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
2341 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
2342 struct mlx5_ib_flow_handler
*handler
= NULL
;
2343 struct mlx5_flow_destination
*dst
= NULL
;
2344 struct mlx5_ib_flow_prio
*ft_prio_tx
= NULL
;
2345 struct mlx5_ib_flow_prio
*ft_prio
;
2348 if (flow_attr
->priority
> MLX5_IB_FLOW_LAST_PRIO
)
2349 return ERR_PTR(-ENOMEM
);
2351 if (domain
!= IB_FLOW_DOMAIN_USER
||
2352 flow_attr
->port
> MLX5_CAP_GEN(dev
->mdev
, num_ports
) ||
2353 (flow_attr
->flags
& ~IB_FLOW_ATTR_FLAGS_DONT_TRAP
))
2354 return ERR_PTR(-EINVAL
);
2356 dst
= kzalloc(sizeof(*dst
), GFP_KERNEL
);
2358 return ERR_PTR(-ENOMEM
);
2360 mutex_lock(&dev
->flow_db
.lock
);
2362 ft_prio
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_RX
);
2363 if (IS_ERR(ft_prio
)) {
2364 err
= PTR_ERR(ft_prio
);
2367 if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2368 ft_prio_tx
= get_flow_table(dev
, flow_attr
, MLX5_IB_FT_TX
);
2369 if (IS_ERR(ft_prio_tx
)) {
2370 err
= PTR_ERR(ft_prio_tx
);
2376 dst
->type
= MLX5_FLOW_DESTINATION_TYPE_TIR
;
2377 if (mqp
->flags
& MLX5_IB_QP_RSS
)
2378 dst
->tir_num
= mqp
->rss_qp
.tirn
;
2380 dst
->tir_num
= mqp
->raw_packet_qp
.rq
.tirn
;
2382 if (flow_attr
->type
== IB_FLOW_ATTR_NORMAL
) {
2383 if (flow_attr
->flags
& IB_FLOW_ATTR_FLAGS_DONT_TRAP
) {
2384 handler
= create_dont_trap_rule(dev
, ft_prio
,
2387 handler
= create_flow_rule(dev
, ft_prio
, flow_attr
,
2390 } else if (flow_attr
->type
== IB_FLOW_ATTR_ALL_DEFAULT
||
2391 flow_attr
->type
== IB_FLOW_ATTR_MC_DEFAULT
) {
2392 handler
= create_leftovers_rule(dev
, ft_prio
, flow_attr
,
2394 } else if (flow_attr
->type
== IB_FLOW_ATTR_SNIFFER
) {
2395 handler
= create_sniffer_rule(dev
, ft_prio
, ft_prio_tx
, dst
);
2401 if (IS_ERR(handler
)) {
2402 err
= PTR_ERR(handler
);
2407 mutex_unlock(&dev
->flow_db
.lock
);
2410 return &handler
->ibflow
;
2413 put_flow_table(dev
, ft_prio
, false);
2415 put_flow_table(dev
, ft_prio_tx
, false);
2417 mutex_unlock(&dev
->flow_db
.lock
);
2420 return ERR_PTR(err
);
2423 static int mlx5_ib_mcg_attach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
2425 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2428 err
= mlx5_core_attach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
2430 mlx5_ib_warn(dev
, "failed attaching QPN 0x%x, MGID %pI6\n",
2431 ibqp
->qp_num
, gid
->raw
);
2436 static int mlx5_ib_mcg_detach(struct ib_qp
*ibqp
, union ib_gid
*gid
, u16 lid
)
2438 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2441 err
= mlx5_core_detach_mcg(dev
->mdev
, gid
, ibqp
->qp_num
);
2443 mlx5_ib_warn(dev
, "failed detaching QPN 0x%x, MGID %pI6\n",
2444 ibqp
->qp_num
, gid
->raw
);
2449 static int init_node_data(struct mlx5_ib_dev
*dev
)
2453 err
= mlx5_query_node_desc(dev
, dev
->ib_dev
.node_desc
);
2457 dev
->mdev
->rev_id
= dev
->mdev
->pdev
->revision
;
2459 return mlx5_query_node_guid(dev
, &dev
->ib_dev
.node_guid
);
2462 static ssize_t
show_fw_pages(struct device
*device
, struct device_attribute
*attr
,
2465 struct mlx5_ib_dev
*dev
=
2466 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2468 return sprintf(buf
, "%d\n", dev
->mdev
->priv
.fw_pages
);
2471 static ssize_t
show_reg_pages(struct device
*device
,
2472 struct device_attribute
*attr
, char *buf
)
2474 struct mlx5_ib_dev
*dev
=
2475 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2477 return sprintf(buf
, "%d\n", atomic_read(&dev
->mdev
->priv
.reg_pages
));
2480 static ssize_t
show_hca(struct device
*device
, struct device_attribute
*attr
,
2483 struct mlx5_ib_dev
*dev
=
2484 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2485 return sprintf(buf
, "MT%d\n", dev
->mdev
->pdev
->device
);
2488 static ssize_t
show_rev(struct device
*device
, struct device_attribute
*attr
,
2491 struct mlx5_ib_dev
*dev
=
2492 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2493 return sprintf(buf
, "%x\n", dev
->mdev
->rev_id
);
2496 static ssize_t
show_board(struct device
*device
, struct device_attribute
*attr
,
2499 struct mlx5_ib_dev
*dev
=
2500 container_of(device
, struct mlx5_ib_dev
, ib_dev
.dev
);
2501 return sprintf(buf
, "%.*s\n", MLX5_BOARD_ID_LEN
,
2502 dev
->mdev
->board_id
);
2505 static DEVICE_ATTR(hw_rev
, S_IRUGO
, show_rev
, NULL
);
2506 static DEVICE_ATTR(hca_type
, S_IRUGO
, show_hca
, NULL
);
2507 static DEVICE_ATTR(board_id
, S_IRUGO
, show_board
, NULL
);
2508 static DEVICE_ATTR(fw_pages
, S_IRUGO
, show_fw_pages
, NULL
);
2509 static DEVICE_ATTR(reg_pages
, S_IRUGO
, show_reg_pages
, NULL
);
2511 static struct device_attribute
*mlx5_class_attributes
[] = {
2516 &dev_attr_reg_pages
,
2519 static void pkey_change_handler(struct work_struct
*work
)
2521 struct mlx5_ib_port_resources
*ports
=
2522 container_of(work
, struct mlx5_ib_port_resources
,
2525 mutex_lock(&ports
->devr
->mutex
);
2526 mlx5_ib_gsi_pkey_change(ports
->gsi
);
2527 mutex_unlock(&ports
->devr
->mutex
);
2530 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev
*ibdev
)
2532 struct mlx5_ib_qp
*mqp
;
2533 struct mlx5_ib_cq
*send_mcq
, *recv_mcq
;
2534 struct mlx5_core_cq
*mcq
;
2535 struct list_head cq_armed_list
;
2536 unsigned long flags_qp
;
2537 unsigned long flags_cq
;
2538 unsigned long flags
;
2540 INIT_LIST_HEAD(&cq_armed_list
);
2542 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
2543 spin_lock_irqsave(&ibdev
->reset_flow_resource_lock
, flags
);
2544 list_for_each_entry(mqp
, &ibdev
->qp_list
, qps_list
) {
2545 spin_lock_irqsave(&mqp
->sq
.lock
, flags_qp
);
2546 if (mqp
->sq
.tail
!= mqp
->sq
.head
) {
2547 send_mcq
= to_mcq(mqp
->ibqp
.send_cq
);
2548 spin_lock_irqsave(&send_mcq
->lock
, flags_cq
);
2549 if (send_mcq
->mcq
.comp
&&
2550 mqp
->ibqp
.send_cq
->comp_handler
) {
2551 if (!send_mcq
->mcq
.reset_notify_added
) {
2552 send_mcq
->mcq
.reset_notify_added
= 1;
2553 list_add_tail(&send_mcq
->mcq
.reset_notify
,
2557 spin_unlock_irqrestore(&send_mcq
->lock
, flags_cq
);
2559 spin_unlock_irqrestore(&mqp
->sq
.lock
, flags_qp
);
2560 spin_lock_irqsave(&mqp
->rq
.lock
, flags_qp
);
2561 /* no handling is needed for SRQ */
2562 if (!mqp
->ibqp
.srq
) {
2563 if (mqp
->rq
.tail
!= mqp
->rq
.head
) {
2564 recv_mcq
= to_mcq(mqp
->ibqp
.recv_cq
);
2565 spin_lock_irqsave(&recv_mcq
->lock
, flags_cq
);
2566 if (recv_mcq
->mcq
.comp
&&
2567 mqp
->ibqp
.recv_cq
->comp_handler
) {
2568 if (!recv_mcq
->mcq
.reset_notify_added
) {
2569 recv_mcq
->mcq
.reset_notify_added
= 1;
2570 list_add_tail(&recv_mcq
->mcq
.reset_notify
,
2574 spin_unlock_irqrestore(&recv_mcq
->lock
,
2578 spin_unlock_irqrestore(&mqp
->rq
.lock
, flags_qp
);
2580 /*At that point all inflight post send were put to be executed as of we
2581 * lock/unlock above locks Now need to arm all involved CQs.
2583 list_for_each_entry(mcq
, &cq_armed_list
, reset_notify
) {
2586 spin_unlock_irqrestore(&ibdev
->reset_flow_resource_lock
, flags
);
2589 static void mlx5_ib_event(struct mlx5_core_dev
*dev
, void *context
,
2590 enum mlx5_dev_event event
, unsigned long param
)
2592 struct mlx5_ib_dev
*ibdev
= (struct mlx5_ib_dev
*)context
;
2593 struct ib_event ibev
;
2598 case MLX5_DEV_EVENT_SYS_ERROR
:
2599 ibev
.event
= IB_EVENT_DEVICE_FATAL
;
2600 mlx5_ib_handle_internal_error(ibdev
);
2604 case MLX5_DEV_EVENT_PORT_UP
:
2605 case MLX5_DEV_EVENT_PORT_DOWN
:
2606 case MLX5_DEV_EVENT_PORT_INITIALIZED
:
2609 /* In RoCE, port up/down events are handled in
2610 * mlx5_netdev_event().
2612 if (mlx5_ib_port_link_layer(&ibdev
->ib_dev
, port
) ==
2613 IB_LINK_LAYER_ETHERNET
)
2616 ibev
.event
= (event
== MLX5_DEV_EVENT_PORT_UP
) ?
2617 IB_EVENT_PORT_ACTIVE
: IB_EVENT_PORT_ERR
;
2620 case MLX5_DEV_EVENT_LID_CHANGE
:
2621 ibev
.event
= IB_EVENT_LID_CHANGE
;
2625 case MLX5_DEV_EVENT_PKEY_CHANGE
:
2626 ibev
.event
= IB_EVENT_PKEY_CHANGE
;
2629 schedule_work(&ibdev
->devr
.ports
[port
- 1].pkey_change_work
);
2632 case MLX5_DEV_EVENT_GUID_CHANGE
:
2633 ibev
.event
= IB_EVENT_GID_CHANGE
;
2637 case MLX5_DEV_EVENT_CLIENT_REREG
:
2638 ibev
.event
= IB_EVENT_CLIENT_REREGISTER
;
2645 ibev
.device
= &ibdev
->ib_dev
;
2646 ibev
.element
.port_num
= port
;
2648 if (port
< 1 || port
> ibdev
->num_ports
) {
2649 mlx5_ib_warn(ibdev
, "warning: event on port %d\n", port
);
2653 if (ibdev
->ib_active
)
2654 ib_dispatch_event(&ibev
);
2657 ibdev
->ib_active
= false;
2660 static int set_has_smi_cap(struct mlx5_ib_dev
*dev
)
2662 struct mlx5_hca_vport_context vport_ctx
;
2666 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
2667 dev
->mdev
->port_caps
[port
- 1].has_smi
= false;
2668 if (MLX5_CAP_GEN(dev
->mdev
, port_type
) ==
2669 MLX5_CAP_PORT_TYPE_IB
) {
2670 if (MLX5_CAP_GEN(dev
->mdev
, ib_virt
)) {
2671 err
= mlx5_query_hca_vport_context(dev
->mdev
, 0,
2675 mlx5_ib_err(dev
, "query_hca_vport_context for port=%d failed %d\n",
2679 dev
->mdev
->port_caps
[port
- 1].has_smi
=
2682 dev
->mdev
->port_caps
[port
- 1].has_smi
= true;
2689 static void get_ext_port_caps(struct mlx5_ib_dev
*dev
)
2693 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++)
2694 mlx5_query_ext_port_caps(dev
, port
);
2697 static int get_port_caps(struct mlx5_ib_dev
*dev
)
2699 struct ib_device_attr
*dprops
= NULL
;
2700 struct ib_port_attr
*pprops
= NULL
;
2703 struct ib_udata uhw
= {.inlen
= 0, .outlen
= 0};
2705 pprops
= kmalloc(sizeof(*pprops
), GFP_KERNEL
);
2709 dprops
= kmalloc(sizeof(*dprops
), GFP_KERNEL
);
2713 err
= set_has_smi_cap(dev
);
2717 err
= mlx5_ib_query_device(&dev
->ib_dev
, dprops
, &uhw
);
2719 mlx5_ib_warn(dev
, "query_device failed %d\n", err
);
2723 for (port
= 1; port
<= MLX5_CAP_GEN(dev
->mdev
, num_ports
); port
++) {
2724 memset(pprops
, 0, sizeof(*pprops
));
2725 err
= mlx5_ib_query_port(&dev
->ib_dev
, port
, pprops
);
2727 mlx5_ib_warn(dev
, "query_port %d failed %d\n",
2731 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
=
2733 dev
->mdev
->port_caps
[port
- 1].gid_table_len
=
2734 pprops
->gid_tbl_len
;
2735 mlx5_ib_dbg(dev
, "pkey_table_len %d, gid_table_len %d\n",
2736 dprops
->max_pkeys
, pprops
->gid_tbl_len
);
2746 static void destroy_umrc_res(struct mlx5_ib_dev
*dev
)
2750 err
= mlx5_mr_cache_cleanup(dev
);
2752 mlx5_ib_warn(dev
, "mr cache cleanup failed\n");
2754 mlx5_ib_destroy_qp(dev
->umrc
.qp
);
2755 ib_free_cq(dev
->umrc
.cq
);
2756 ib_dealloc_pd(dev
->umrc
.pd
);
2763 static int create_umr_res(struct mlx5_ib_dev
*dev
)
2765 struct ib_qp_init_attr
*init_attr
= NULL
;
2766 struct ib_qp_attr
*attr
= NULL
;
2772 attr
= kzalloc(sizeof(*attr
), GFP_KERNEL
);
2773 init_attr
= kzalloc(sizeof(*init_attr
), GFP_KERNEL
);
2774 if (!attr
|| !init_attr
) {
2779 pd
= ib_alloc_pd(&dev
->ib_dev
, 0);
2781 mlx5_ib_dbg(dev
, "Couldn't create PD for sync UMR QP\n");
2786 cq
= ib_alloc_cq(&dev
->ib_dev
, NULL
, 128, 0, IB_POLL_SOFTIRQ
);
2788 mlx5_ib_dbg(dev
, "Couldn't create CQ for sync UMR QP\n");
2793 init_attr
->send_cq
= cq
;
2794 init_attr
->recv_cq
= cq
;
2795 init_attr
->sq_sig_type
= IB_SIGNAL_ALL_WR
;
2796 init_attr
->cap
.max_send_wr
= MAX_UMR_WR
;
2797 init_attr
->cap
.max_send_sge
= 1;
2798 init_attr
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2799 init_attr
->port_num
= 1;
2800 qp
= mlx5_ib_create_qp(pd
, init_attr
, NULL
);
2802 mlx5_ib_dbg(dev
, "Couldn't create sync UMR QP\n");
2806 qp
->device
= &dev
->ib_dev
;
2809 qp
->qp_type
= MLX5_IB_QPT_REG_UMR
;
2811 attr
->qp_state
= IB_QPS_INIT
;
2813 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
| IB_QP_PKEY_INDEX
|
2816 mlx5_ib_dbg(dev
, "Couldn't modify UMR QP\n");
2820 memset(attr
, 0, sizeof(*attr
));
2821 attr
->qp_state
= IB_QPS_RTR
;
2822 attr
->path_mtu
= IB_MTU_256
;
2824 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2826 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rtr\n");
2830 memset(attr
, 0, sizeof(*attr
));
2831 attr
->qp_state
= IB_QPS_RTS
;
2832 ret
= mlx5_ib_modify_qp(qp
, attr
, IB_QP_STATE
, NULL
);
2834 mlx5_ib_dbg(dev
, "Couldn't modify umr QP to rts\n");
2842 sema_init(&dev
->umrc
.sem
, MAX_UMR_WR
);
2843 ret
= mlx5_mr_cache_init(dev
);
2845 mlx5_ib_warn(dev
, "mr cache init failed %d\n", ret
);
2855 mlx5_ib_destroy_qp(qp
);
2869 static int create_dev_resources(struct mlx5_ib_resources
*devr
)
2871 struct ib_srq_init_attr attr
;
2872 struct mlx5_ib_dev
*dev
;
2873 struct ib_cq_init_attr cq_attr
= {.cqe
= 1};
2877 dev
= container_of(devr
, struct mlx5_ib_dev
, devr
);
2879 mutex_init(&devr
->mutex
);
2881 devr
->p0
= mlx5_ib_alloc_pd(&dev
->ib_dev
, NULL
, NULL
);
2882 if (IS_ERR(devr
->p0
)) {
2883 ret
= PTR_ERR(devr
->p0
);
2886 devr
->p0
->device
= &dev
->ib_dev
;
2887 devr
->p0
->uobject
= NULL
;
2888 atomic_set(&devr
->p0
->usecnt
, 0);
2890 devr
->c0
= mlx5_ib_create_cq(&dev
->ib_dev
, &cq_attr
, NULL
, NULL
);
2891 if (IS_ERR(devr
->c0
)) {
2892 ret
= PTR_ERR(devr
->c0
);
2895 devr
->c0
->device
= &dev
->ib_dev
;
2896 devr
->c0
->uobject
= NULL
;
2897 devr
->c0
->comp_handler
= NULL
;
2898 devr
->c0
->event_handler
= NULL
;
2899 devr
->c0
->cq_context
= NULL
;
2900 atomic_set(&devr
->c0
->usecnt
, 0);
2902 devr
->x0
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2903 if (IS_ERR(devr
->x0
)) {
2904 ret
= PTR_ERR(devr
->x0
);
2907 devr
->x0
->device
= &dev
->ib_dev
;
2908 devr
->x0
->inode
= NULL
;
2909 atomic_set(&devr
->x0
->usecnt
, 0);
2910 mutex_init(&devr
->x0
->tgt_qp_mutex
);
2911 INIT_LIST_HEAD(&devr
->x0
->tgt_qp_list
);
2913 devr
->x1
= mlx5_ib_alloc_xrcd(&dev
->ib_dev
, NULL
, NULL
);
2914 if (IS_ERR(devr
->x1
)) {
2915 ret
= PTR_ERR(devr
->x1
);
2918 devr
->x1
->device
= &dev
->ib_dev
;
2919 devr
->x1
->inode
= NULL
;
2920 atomic_set(&devr
->x1
->usecnt
, 0);
2921 mutex_init(&devr
->x1
->tgt_qp_mutex
);
2922 INIT_LIST_HEAD(&devr
->x1
->tgt_qp_list
);
2924 memset(&attr
, 0, sizeof(attr
));
2925 attr
.attr
.max_sge
= 1;
2926 attr
.attr
.max_wr
= 1;
2927 attr
.srq_type
= IB_SRQT_XRC
;
2928 attr
.ext
.xrc
.cq
= devr
->c0
;
2929 attr
.ext
.xrc
.xrcd
= devr
->x0
;
2931 devr
->s0
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2932 if (IS_ERR(devr
->s0
)) {
2933 ret
= PTR_ERR(devr
->s0
);
2936 devr
->s0
->device
= &dev
->ib_dev
;
2937 devr
->s0
->pd
= devr
->p0
;
2938 devr
->s0
->uobject
= NULL
;
2939 devr
->s0
->event_handler
= NULL
;
2940 devr
->s0
->srq_context
= NULL
;
2941 devr
->s0
->srq_type
= IB_SRQT_XRC
;
2942 devr
->s0
->ext
.xrc
.xrcd
= devr
->x0
;
2943 devr
->s0
->ext
.xrc
.cq
= devr
->c0
;
2944 atomic_inc(&devr
->s0
->ext
.xrc
.xrcd
->usecnt
);
2945 atomic_inc(&devr
->s0
->ext
.xrc
.cq
->usecnt
);
2946 atomic_inc(&devr
->p0
->usecnt
);
2947 atomic_set(&devr
->s0
->usecnt
, 0);
2949 memset(&attr
, 0, sizeof(attr
));
2950 attr
.attr
.max_sge
= 1;
2951 attr
.attr
.max_wr
= 1;
2952 attr
.srq_type
= IB_SRQT_BASIC
;
2953 devr
->s1
= mlx5_ib_create_srq(devr
->p0
, &attr
, NULL
);
2954 if (IS_ERR(devr
->s1
)) {
2955 ret
= PTR_ERR(devr
->s1
);
2958 devr
->s1
->device
= &dev
->ib_dev
;
2959 devr
->s1
->pd
= devr
->p0
;
2960 devr
->s1
->uobject
= NULL
;
2961 devr
->s1
->event_handler
= NULL
;
2962 devr
->s1
->srq_context
= NULL
;
2963 devr
->s1
->srq_type
= IB_SRQT_BASIC
;
2964 devr
->s1
->ext
.xrc
.cq
= devr
->c0
;
2965 atomic_inc(&devr
->p0
->usecnt
);
2966 atomic_set(&devr
->s0
->usecnt
, 0);
2968 for (port
= 0; port
< ARRAY_SIZE(devr
->ports
); ++port
) {
2969 INIT_WORK(&devr
->ports
[port
].pkey_change_work
,
2970 pkey_change_handler
);
2971 devr
->ports
[port
].devr
= devr
;
2977 mlx5_ib_destroy_srq(devr
->s0
);
2979 mlx5_ib_dealloc_xrcd(devr
->x1
);
2981 mlx5_ib_dealloc_xrcd(devr
->x0
);
2983 mlx5_ib_destroy_cq(devr
->c0
);
2985 mlx5_ib_dealloc_pd(devr
->p0
);
2990 static void destroy_dev_resources(struct mlx5_ib_resources
*devr
)
2992 struct mlx5_ib_dev
*dev
=
2993 container_of(devr
, struct mlx5_ib_dev
, devr
);
2996 mlx5_ib_destroy_srq(devr
->s1
);
2997 mlx5_ib_destroy_srq(devr
->s0
);
2998 mlx5_ib_dealloc_xrcd(devr
->x0
);
2999 mlx5_ib_dealloc_xrcd(devr
->x1
);
3000 mlx5_ib_destroy_cq(devr
->c0
);
3001 mlx5_ib_dealloc_pd(devr
->p0
);
3003 /* Make sure no change P_Key work items are still executing */
3004 for (port
= 0; port
< dev
->num_ports
; ++port
)
3005 cancel_work_sync(&devr
->ports
[port
].pkey_change_work
);
3008 static u32
get_core_cap_flags(struct ib_device
*ibdev
)
3010 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3011 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, 1);
3012 u8 l3_type_cap
= MLX5_CAP_ROCE(dev
->mdev
, l3_type
);
3013 u8 roce_version_cap
= MLX5_CAP_ROCE(dev
->mdev
, roce_version
);
3016 if (ll
== IB_LINK_LAYER_INFINIBAND
)
3017 return RDMA_CORE_PORT_IBA_IB
;
3019 ret
= RDMA_CORE_PORT_RAW_PACKET
;
3021 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV4_CAP
))
3024 if (!(l3_type_cap
& MLX5_ROCE_L3_TYPE_IPV6_CAP
))
3027 if (roce_version_cap
& MLX5_ROCE_VERSION_1_CAP
)
3028 ret
|= RDMA_CORE_PORT_IBA_ROCE
;
3030 if (roce_version_cap
& MLX5_ROCE_VERSION_2_CAP
)
3031 ret
|= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP
;
3036 static int mlx5_port_immutable(struct ib_device
*ibdev
, u8 port_num
,
3037 struct ib_port_immutable
*immutable
)
3039 struct ib_port_attr attr
;
3040 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3041 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(ibdev
, port_num
);
3044 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
3046 err
= ib_query_port(ibdev
, port_num
, &attr
);
3050 immutable
->pkey_tbl_len
= attr
.pkey_tbl_len
;
3051 immutable
->gid_tbl_len
= attr
.gid_tbl_len
;
3052 immutable
->core_cap_flags
= get_core_cap_flags(ibdev
);
3053 if ((ll
== IB_LINK_LAYER_INFINIBAND
) || MLX5_CAP_GEN(dev
->mdev
, roce
))
3054 immutable
->max_mad_size
= IB_MGMT_MAD_SIZE
;
3059 static void get_dev_fw_str(struct ib_device
*ibdev
, char *str
,
3062 struct mlx5_ib_dev
*dev
=
3063 container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
3064 snprintf(str
, str_len
, "%d.%d.%04d", fw_rev_maj(dev
->mdev
),
3065 fw_rev_min(dev
->mdev
), fw_rev_sub(dev
->mdev
));
3068 static int mlx5_eth_lag_init(struct mlx5_ib_dev
*dev
)
3070 struct mlx5_core_dev
*mdev
= dev
->mdev
;
3071 struct mlx5_flow_namespace
*ns
= mlx5_get_flow_namespace(mdev
,
3072 MLX5_FLOW_NAMESPACE_LAG
);
3073 struct mlx5_flow_table
*ft
;
3076 if (!ns
|| !mlx5_lag_is_active(mdev
))
3079 err
= mlx5_cmd_create_vport_lag(mdev
);
3083 ft
= mlx5_create_lag_demux_flow_table(ns
, 0, 0);
3086 goto err_destroy_vport_lag
;
3089 dev
->flow_db
.lag_demux_ft
= ft
;
3092 err_destroy_vport_lag
:
3093 mlx5_cmd_destroy_vport_lag(mdev
);
3097 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev
*dev
)
3099 struct mlx5_core_dev
*mdev
= dev
->mdev
;
3101 if (dev
->flow_db
.lag_demux_ft
) {
3102 mlx5_destroy_flow_table(dev
->flow_db
.lag_demux_ft
);
3103 dev
->flow_db
.lag_demux_ft
= NULL
;
3105 mlx5_cmd_destroy_vport_lag(mdev
);
3109 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev
*dev
)
3113 dev
->roce
.nb
.notifier_call
= mlx5_netdev_event
;
3114 err
= register_netdevice_notifier(&dev
->roce
.nb
);
3116 dev
->roce
.nb
.notifier_call
= NULL
;
3123 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev
*dev
)
3125 if (dev
->roce
.nb
.notifier_call
) {
3126 unregister_netdevice_notifier(&dev
->roce
.nb
);
3127 dev
->roce
.nb
.notifier_call
= NULL
;
3131 static int mlx5_enable_eth(struct mlx5_ib_dev
*dev
)
3135 err
= mlx5_add_netdev_notifier(dev
);
3139 if (MLX5_CAP_GEN(dev
->mdev
, roce
)) {
3140 err
= mlx5_nic_vport_enable_roce(dev
->mdev
);
3142 goto err_unregister_netdevice_notifier
;
3145 err
= mlx5_eth_lag_init(dev
);
3147 goto err_disable_roce
;
3152 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
3153 mlx5_nic_vport_disable_roce(dev
->mdev
);
3155 err_unregister_netdevice_notifier
:
3156 mlx5_remove_netdev_notifier(dev
);
3160 static void mlx5_disable_eth(struct mlx5_ib_dev
*dev
)
3162 mlx5_eth_lag_cleanup(dev
);
3163 if (MLX5_CAP_GEN(dev
->mdev
, roce
))
3164 mlx5_nic_vport_disable_roce(dev
->mdev
);
3167 struct mlx5_ib_q_counter
{
3172 #define INIT_Q_COUNTER(_name) \
3173 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
3175 static const struct mlx5_ib_q_counter basic_q_cnts
[] = {
3176 INIT_Q_COUNTER(rx_write_requests
),
3177 INIT_Q_COUNTER(rx_read_requests
),
3178 INIT_Q_COUNTER(rx_atomic_requests
),
3179 INIT_Q_COUNTER(out_of_buffer
),
3182 static const struct mlx5_ib_q_counter out_of_seq_q_cnts
[] = {
3183 INIT_Q_COUNTER(out_of_sequence
),
3186 static const struct mlx5_ib_q_counter retrans_q_cnts
[] = {
3187 INIT_Q_COUNTER(duplicate_request
),
3188 INIT_Q_COUNTER(rnr_nak_retry_err
),
3189 INIT_Q_COUNTER(packet_seq_err
),
3190 INIT_Q_COUNTER(implied_nak_seq_err
),
3191 INIT_Q_COUNTER(local_ack_timeout_err
),
3194 static void mlx5_ib_dealloc_q_counters(struct mlx5_ib_dev
*dev
)
3198 for (i
= 0; i
< dev
->num_ports
; i
++) {
3199 mlx5_core_dealloc_q_counter(dev
->mdev
,
3200 dev
->port
[i
].q_cnts
.set_id
);
3201 kfree(dev
->port
[i
].q_cnts
.names
);
3202 kfree(dev
->port
[i
].q_cnts
.offsets
);
3206 static int __mlx5_ib_alloc_q_counters(struct mlx5_ib_dev
*dev
,
3207 const char ***names
,
3213 num_counters
= ARRAY_SIZE(basic_q_cnts
);
3215 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
))
3216 num_counters
+= ARRAY_SIZE(out_of_seq_q_cnts
);
3218 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
))
3219 num_counters
+= ARRAY_SIZE(retrans_q_cnts
);
3221 *names
= kcalloc(num_counters
, sizeof(**names
), GFP_KERNEL
);
3225 *offsets
= kcalloc(num_counters
, sizeof(**offsets
), GFP_KERNEL
);
3229 *num
= num_counters
;
3238 static void mlx5_ib_fill_q_counters(struct mlx5_ib_dev
*dev
,
3245 for (i
= 0; i
< ARRAY_SIZE(basic_q_cnts
); i
++, j
++) {
3246 names
[j
] = basic_q_cnts
[i
].name
;
3247 offsets
[j
] = basic_q_cnts
[i
].offset
;
3250 if (MLX5_CAP_GEN(dev
->mdev
, out_of_seq_cnt
)) {
3251 for (i
= 0; i
< ARRAY_SIZE(out_of_seq_q_cnts
); i
++, j
++) {
3252 names
[j
] = out_of_seq_q_cnts
[i
].name
;
3253 offsets
[j
] = out_of_seq_q_cnts
[i
].offset
;
3257 if (MLX5_CAP_GEN(dev
->mdev
, retransmission_q_counters
)) {
3258 for (i
= 0; i
< ARRAY_SIZE(retrans_q_cnts
); i
++, j
++) {
3259 names
[j
] = retrans_q_cnts
[i
].name
;
3260 offsets
[j
] = retrans_q_cnts
[i
].offset
;
3265 static int mlx5_ib_alloc_q_counters(struct mlx5_ib_dev
*dev
)
3270 for (i
= 0; i
< dev
->num_ports
; i
++) {
3271 struct mlx5_ib_port
*port
= &dev
->port
[i
];
3273 ret
= mlx5_core_alloc_q_counter(dev
->mdev
,
3274 &port
->q_cnts
.set_id
);
3277 "couldn't allocate queue counter for port %d, err %d\n",
3279 goto dealloc_counters
;
3282 ret
= __mlx5_ib_alloc_q_counters(dev
,
3283 &port
->q_cnts
.names
,
3284 &port
->q_cnts
.offsets
,
3285 &port
->q_cnts
.num_counters
);
3287 goto dealloc_counters
;
3289 mlx5_ib_fill_q_counters(dev
, port
->q_cnts
.names
,
3290 port
->q_cnts
.offsets
);
3297 mlx5_core_dealloc_q_counter(dev
->mdev
,
3298 dev
->port
[i
].q_cnts
.set_id
);
3303 static struct rdma_hw_stats
*mlx5_ib_alloc_hw_stats(struct ib_device
*ibdev
,
3306 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3307 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
3309 /* We support only per port stats */
3313 return rdma_alloc_hw_stats_struct(port
->q_cnts
.names
,
3314 port
->q_cnts
.num_counters
,
3315 RDMA_HW_STATS_DEFAULT_LIFESPAN
);
3318 static int mlx5_ib_get_hw_stats(struct ib_device
*ibdev
,
3319 struct rdma_hw_stats
*stats
,
3320 u8 port_num
, int index
)
3322 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
3323 struct mlx5_ib_port
*port
= &dev
->port
[port_num
- 1];
3324 int outlen
= MLX5_ST_SZ_BYTES(query_q_counter_out
);
3333 out
= mlx5_vzalloc(outlen
);
3337 ret
= mlx5_core_query_q_counter(dev
->mdev
,
3338 port
->q_cnts
.set_id
, 0,
3343 for (i
= 0; i
< port
->q_cnts
.num_counters
; i
++) {
3344 val
= *(__be32
*)(out
+ port
->q_cnts
.offsets
[i
]);
3345 stats
->value
[i
] = (u64
)be32_to_cpu(val
);
3350 return port
->q_cnts
.num_counters
;
3353 static void *mlx5_ib_add(struct mlx5_core_dev
*mdev
)
3355 struct mlx5_ib_dev
*dev
;
3356 enum rdma_link_layer ll
;
3362 port_type_cap
= MLX5_CAP_GEN(mdev
, port_type
);
3363 ll
= mlx5_port_type_cap_to_rdma_ll(port_type_cap
);
3365 printk_once(KERN_INFO
"%s", mlx5_version
);
3367 dev
= (struct mlx5_ib_dev
*)ib_alloc_device(sizeof(*dev
));
3373 dev
->port
= kcalloc(MLX5_CAP_GEN(mdev
, num_ports
), sizeof(*dev
->port
),
3378 rwlock_init(&dev
->roce
.netdev_lock
);
3379 err
= get_port_caps(dev
);
3383 if (mlx5_use_mad_ifc(dev
))
3384 get_ext_port_caps(dev
);
3386 if (!mlx5_lag_is_active(mdev
))
3389 name
= "mlx5_bond_%d";
3391 strlcpy(dev
->ib_dev
.name
, name
, IB_DEVICE_NAME_MAX
);
3392 dev
->ib_dev
.owner
= THIS_MODULE
;
3393 dev
->ib_dev
.node_type
= RDMA_NODE_IB_CA
;
3394 dev
->ib_dev
.local_dma_lkey
= 0 /* not supported for now */;
3395 dev
->num_ports
= MLX5_CAP_GEN(mdev
, num_ports
);
3396 dev
->ib_dev
.phys_port_cnt
= dev
->num_ports
;
3397 dev
->ib_dev
.num_comp_vectors
=
3398 dev
->mdev
->priv
.eq_table
.num_comp_vectors
;
3399 dev
->ib_dev
.dev
.parent
= &mdev
->pdev
->dev
;
3401 dev
->ib_dev
.uverbs_abi_ver
= MLX5_IB_UVERBS_ABI_VERSION
;
3402 dev
->ib_dev
.uverbs_cmd_mask
=
3403 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT
) |
3404 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE
) |
3405 (1ull << IB_USER_VERBS_CMD_QUERY_PORT
) |
3406 (1ull << IB_USER_VERBS_CMD_ALLOC_PD
) |
3407 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD
) |
3408 (1ull << IB_USER_VERBS_CMD_CREATE_AH
) |
3409 (1ull << IB_USER_VERBS_CMD_DESTROY_AH
) |
3410 (1ull << IB_USER_VERBS_CMD_REG_MR
) |
3411 (1ull << IB_USER_VERBS_CMD_REREG_MR
) |
3412 (1ull << IB_USER_VERBS_CMD_DEREG_MR
) |
3413 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL
) |
3414 (1ull << IB_USER_VERBS_CMD_CREATE_CQ
) |
3415 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ
) |
3416 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ
) |
3417 (1ull << IB_USER_VERBS_CMD_CREATE_QP
) |
3418 (1ull << IB_USER_VERBS_CMD_MODIFY_QP
) |
3419 (1ull << IB_USER_VERBS_CMD_QUERY_QP
) |
3420 (1ull << IB_USER_VERBS_CMD_DESTROY_QP
) |
3421 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST
) |
3422 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST
) |
3423 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ
) |
3424 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ
) |
3425 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ
) |
3426 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ
) |
3427 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ
) |
3428 (1ull << IB_USER_VERBS_CMD_OPEN_QP
);
3429 dev
->ib_dev
.uverbs_ex_cmd_mask
=
3430 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE
) |
3431 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ
) |
3432 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP
) |
3433 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP
);
3435 dev
->ib_dev
.query_device
= mlx5_ib_query_device
;
3436 dev
->ib_dev
.query_port
= mlx5_ib_query_port
;
3437 dev
->ib_dev
.get_link_layer
= mlx5_ib_port_link_layer
;
3438 if (ll
== IB_LINK_LAYER_ETHERNET
)
3439 dev
->ib_dev
.get_netdev
= mlx5_ib_get_netdev
;
3440 dev
->ib_dev
.query_gid
= mlx5_ib_query_gid
;
3441 dev
->ib_dev
.add_gid
= mlx5_ib_add_gid
;
3442 dev
->ib_dev
.del_gid
= mlx5_ib_del_gid
;
3443 dev
->ib_dev
.query_pkey
= mlx5_ib_query_pkey
;
3444 dev
->ib_dev
.modify_device
= mlx5_ib_modify_device
;
3445 dev
->ib_dev
.modify_port
= mlx5_ib_modify_port
;
3446 dev
->ib_dev
.alloc_ucontext
= mlx5_ib_alloc_ucontext
;
3447 dev
->ib_dev
.dealloc_ucontext
= mlx5_ib_dealloc_ucontext
;
3448 dev
->ib_dev
.mmap
= mlx5_ib_mmap
;
3449 dev
->ib_dev
.alloc_pd
= mlx5_ib_alloc_pd
;
3450 dev
->ib_dev
.dealloc_pd
= mlx5_ib_dealloc_pd
;
3451 dev
->ib_dev
.create_ah
= mlx5_ib_create_ah
;
3452 dev
->ib_dev
.query_ah
= mlx5_ib_query_ah
;
3453 dev
->ib_dev
.destroy_ah
= mlx5_ib_destroy_ah
;
3454 dev
->ib_dev
.create_srq
= mlx5_ib_create_srq
;
3455 dev
->ib_dev
.modify_srq
= mlx5_ib_modify_srq
;
3456 dev
->ib_dev
.query_srq
= mlx5_ib_query_srq
;
3457 dev
->ib_dev
.destroy_srq
= mlx5_ib_destroy_srq
;
3458 dev
->ib_dev
.post_srq_recv
= mlx5_ib_post_srq_recv
;
3459 dev
->ib_dev
.create_qp
= mlx5_ib_create_qp
;
3460 dev
->ib_dev
.modify_qp
= mlx5_ib_modify_qp
;
3461 dev
->ib_dev
.query_qp
= mlx5_ib_query_qp
;
3462 dev
->ib_dev
.destroy_qp
= mlx5_ib_destroy_qp
;
3463 dev
->ib_dev
.post_send
= mlx5_ib_post_send
;
3464 dev
->ib_dev
.post_recv
= mlx5_ib_post_recv
;
3465 dev
->ib_dev
.create_cq
= mlx5_ib_create_cq
;
3466 dev
->ib_dev
.modify_cq
= mlx5_ib_modify_cq
;
3467 dev
->ib_dev
.resize_cq
= mlx5_ib_resize_cq
;
3468 dev
->ib_dev
.destroy_cq
= mlx5_ib_destroy_cq
;
3469 dev
->ib_dev
.poll_cq
= mlx5_ib_poll_cq
;
3470 dev
->ib_dev
.req_notify_cq
= mlx5_ib_arm_cq
;
3471 dev
->ib_dev
.get_dma_mr
= mlx5_ib_get_dma_mr
;
3472 dev
->ib_dev
.reg_user_mr
= mlx5_ib_reg_user_mr
;
3473 dev
->ib_dev
.rereg_user_mr
= mlx5_ib_rereg_user_mr
;
3474 dev
->ib_dev
.dereg_mr
= mlx5_ib_dereg_mr
;
3475 dev
->ib_dev
.attach_mcast
= mlx5_ib_mcg_attach
;
3476 dev
->ib_dev
.detach_mcast
= mlx5_ib_mcg_detach
;
3477 dev
->ib_dev
.process_mad
= mlx5_ib_process_mad
;
3478 dev
->ib_dev
.alloc_mr
= mlx5_ib_alloc_mr
;
3479 dev
->ib_dev
.map_mr_sg
= mlx5_ib_map_mr_sg
;
3480 dev
->ib_dev
.check_mr_status
= mlx5_ib_check_mr_status
;
3481 dev
->ib_dev
.get_port_immutable
= mlx5_port_immutable
;
3482 dev
->ib_dev
.get_dev_fw_str
= get_dev_fw_str
;
3483 if (mlx5_core_is_pf(mdev
)) {
3484 dev
->ib_dev
.get_vf_config
= mlx5_ib_get_vf_config
;
3485 dev
->ib_dev
.set_vf_link_state
= mlx5_ib_set_vf_link_state
;
3486 dev
->ib_dev
.get_vf_stats
= mlx5_ib_get_vf_stats
;
3487 dev
->ib_dev
.set_vf_guid
= mlx5_ib_set_vf_guid
;
3490 dev
->ib_dev
.disassociate_ucontext
= mlx5_ib_disassociate_ucontext
;
3492 mlx5_ib_internal_fill_odp_caps(dev
);
3494 if (MLX5_CAP_GEN(mdev
, imaicl
)) {
3495 dev
->ib_dev
.alloc_mw
= mlx5_ib_alloc_mw
;
3496 dev
->ib_dev
.dealloc_mw
= mlx5_ib_dealloc_mw
;
3497 dev
->ib_dev
.uverbs_cmd_mask
|=
3498 (1ull << IB_USER_VERBS_CMD_ALLOC_MW
) |
3499 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW
);
3502 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
)) {
3503 dev
->ib_dev
.get_hw_stats
= mlx5_ib_get_hw_stats
;
3504 dev
->ib_dev
.alloc_hw_stats
= mlx5_ib_alloc_hw_stats
;
3507 if (MLX5_CAP_GEN(mdev
, xrc
)) {
3508 dev
->ib_dev
.alloc_xrcd
= mlx5_ib_alloc_xrcd
;
3509 dev
->ib_dev
.dealloc_xrcd
= mlx5_ib_dealloc_xrcd
;
3510 dev
->ib_dev
.uverbs_cmd_mask
|=
3511 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD
) |
3512 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD
);
3515 if (mlx5_ib_port_link_layer(&dev
->ib_dev
, 1) ==
3516 IB_LINK_LAYER_ETHERNET
) {
3517 dev
->ib_dev
.create_flow
= mlx5_ib_create_flow
;
3518 dev
->ib_dev
.destroy_flow
= mlx5_ib_destroy_flow
;
3519 dev
->ib_dev
.create_wq
= mlx5_ib_create_wq
;
3520 dev
->ib_dev
.modify_wq
= mlx5_ib_modify_wq
;
3521 dev
->ib_dev
.destroy_wq
= mlx5_ib_destroy_wq
;
3522 dev
->ib_dev
.create_rwq_ind_table
= mlx5_ib_create_rwq_ind_table
;
3523 dev
->ib_dev
.destroy_rwq_ind_table
= mlx5_ib_destroy_rwq_ind_table
;
3524 dev
->ib_dev
.uverbs_ex_cmd_mask
|=
3525 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW
) |
3526 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW
) |
3527 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ
) |
3528 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ
) |
3529 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ
) |
3530 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL
) |
3531 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL
);
3533 err
= init_node_data(dev
);
3537 mutex_init(&dev
->flow_db
.lock
);
3538 mutex_init(&dev
->cap_mask_mutex
);
3539 INIT_LIST_HEAD(&dev
->qp_list
);
3540 spin_lock_init(&dev
->reset_flow_resource_lock
);
3542 if (ll
== IB_LINK_LAYER_ETHERNET
) {
3543 err
= mlx5_enable_eth(dev
);
3548 err
= create_dev_resources(&dev
->devr
);
3550 goto err_disable_eth
;
3552 err
= mlx5_ib_odp_init_one(dev
);
3556 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
)) {
3557 err
= mlx5_ib_alloc_q_counters(dev
);
3562 dev
->mdev
->priv
.uar
= mlx5_get_uars_page(dev
->mdev
);
3563 if (!dev
->mdev
->priv
.uar
)
3566 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->bfreg
, false, false);
3570 err
= mlx5_alloc_bfreg(dev
->mdev
, &dev
->fp_bfreg
, false, true);
3574 err
= ib_register_device(&dev
->ib_dev
, NULL
);
3578 err
= create_umr_res(dev
);
3582 for (i
= 0; i
< ARRAY_SIZE(mlx5_class_attributes
); i
++) {
3583 err
= device_create_file(&dev
->ib_dev
.dev
,
3584 mlx5_class_attributes
[i
]);
3589 dev
->ib_active
= true;
3594 destroy_umrc_res(dev
);
3597 ib_unregister_device(&dev
->ib_dev
);
3600 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
3603 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
3606 mlx5_put_uars_page(dev
->mdev
, dev
->mdev
->priv
.uar
);
3609 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
))
3610 mlx5_ib_dealloc_q_counters(dev
);
3613 mlx5_ib_odp_remove_one(dev
);
3616 destroy_dev_resources(&dev
->devr
);
3619 if (ll
== IB_LINK_LAYER_ETHERNET
) {
3620 mlx5_disable_eth(dev
);
3621 mlx5_remove_netdev_notifier(dev
);
3628 ib_dealloc_device((struct ib_device
*)dev
);
3633 static void mlx5_ib_remove(struct mlx5_core_dev
*mdev
, void *context
)
3635 struct mlx5_ib_dev
*dev
= context
;
3636 enum rdma_link_layer ll
= mlx5_ib_port_link_layer(&dev
->ib_dev
, 1);
3638 mlx5_remove_netdev_notifier(dev
);
3639 ib_unregister_device(&dev
->ib_dev
);
3640 mlx5_free_bfreg(dev
->mdev
, &dev
->fp_bfreg
);
3641 mlx5_free_bfreg(dev
->mdev
, &dev
->bfreg
);
3642 mlx5_put_uars_page(dev
->mdev
, mdev
->priv
.uar
);
3643 if (MLX5_CAP_GEN(dev
->mdev
, max_qp_cnt
))
3644 mlx5_ib_dealloc_q_counters(dev
);
3645 destroy_umrc_res(dev
);
3646 mlx5_ib_odp_remove_one(dev
);
3647 destroy_dev_resources(&dev
->devr
);
3648 if (ll
== IB_LINK_LAYER_ETHERNET
)
3649 mlx5_disable_eth(dev
);
3651 ib_dealloc_device(&dev
->ib_dev
);
3654 static struct mlx5_interface mlx5_ib_interface
= {
3656 .remove
= mlx5_ib_remove
,
3657 .event
= mlx5_ib_event
,
3658 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3659 .pfault
= mlx5_ib_pfault
,
3661 .protocol
= MLX5_INTERFACE_PROTOCOL_IB
,
3664 static int __init
mlx5_ib_init(void)
3670 err
= mlx5_register_interface(&mlx5_ib_interface
);
3675 static void __exit
mlx5_ib_cleanup(void)
3677 mlx5_unregister_interface(&mlx5_ib_interface
);
3680 module_init(mlx5_ib_init
);
3681 module_exit(mlx5_ib_cleanup
);