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RDMA/mlx5: Enable decap and packet reformat on flow tables
[mirror_ubuntu-focal-kernel.git] / drivers / infiniband / hw / mlx5 / main.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
43 #include <asm/pat.h>
44 #endif
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/list.h>
56 #include <rdma/ib_smi.h>
57 #include <rdma/ib_umem.h>
58 #include <linux/in.h>
59 #include <linux/etherdevice.h>
60 #include "mlx5_ib.h"
61 #include "ib_rep.h"
62 #include "cmd.h"
63 #include <linux/mlx5/fs_helpers.h>
64 #include <linux/mlx5/accel.h>
65 #include <rdma/uverbs_std_types.h>
66 #include <rdma/mlx5_user_ioctl_verbs.h>
67 #include <rdma/mlx5_user_ioctl_cmds.h>
68
69 #define UVERBS_MODULE_NAME mlx5_ib
70 #include <rdma/uverbs_named_ioctl.h>
71
72 #define DRIVER_NAME "mlx5_ib"
73 #define DRIVER_VERSION "5.0-0"
74
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
81 DRIVER_VERSION "\n";
82
83 struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89 };
90
91 enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93 };
94
95 static struct workqueue_struct *mlx5_ib_event_wq;
96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97 static LIST_HEAD(mlx5_ib_dev_list);
98 /*
99 * This mutex should be held when accessing either of the above lists
100 */
101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
103 /* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106 static unsigned long xlt_emergency_page;
107 static struct mutex xlt_emergency_page_mutex;
108
109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110 {
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117 }
118
119 static enum rdma_link_layer
120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
121 {
122 switch (port_type_cap) {
123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130 }
131
132 static enum rdma_link_layer
133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134 {
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139 }
140
141 static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144 {
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
149 ret = ibdev->query_port(ibdev, port_num, &attr);
150 if (!ret)
151 *state = attr.state;
152 return ret;
153 }
154
155 static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157 {
158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
168
169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
172 write_lock(&roce->netdev_lock);
173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
181 NULL : ndev;
182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
186 write_unlock(&roce->netdev_lock);
187 break;
188
189 case NETDEV_CHANGE:
190 case NETDEV_UP:
191 case NETDEV_DOWN: {
192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
200 if ((upper == ndev || (!upper && ndev == roce->netdev))
201 && ibdev->ib_active) {
202 struct ib_event ibev = { };
203 enum ib_port_state port_state;
204
205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
208
209 if (roce->last_port_state == port_state)
210 goto done;
211
212 roce->last_port_state = port_state;
213 ibev.device = &ibdev->ib_dev;
214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
219 goto done;
220
221 ibev.element.port_num = port_num;
222 ib_dispatch_event(&ibev);
223 }
224 break;
225 }
226
227 default:
228 break;
229 }
230 done:
231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
232 return NOTIFY_DONE;
233 }
234
235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237 {
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
245
246 ndev = mlx5_lag_get_roce_netdev(mdev);
247 if (ndev)
248 goto out;
249
250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
254 if (ndev)
255 dev_hold(ndev);
256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
257
258 out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
260 return ndev;
261 }
262
263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266 {
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
280 if (native_port_num)
281 *native_port_num = 1;
282
283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300 }
301
302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303 {
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322 out:
323 spin_unlock(&port->mp.mpi_lock);
324 }
325
326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328 {
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382 }
383
384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
386 {
387 struct mlx5_ib_dev *dev = to_mdev(device);
388 struct mlx5_core_dev *mdev;
389 struct net_device *ndev, *upper;
390 enum ib_mtu ndev_ib_mtu;
391 bool put_mdev = true;
392 u16 qkey_viol_cntr;
393 u32 eth_prot_oper;
394 u8 mdev_port_num;
395 int err;
396
397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
410 */
411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
413 if (err)
414 goto out;
415
416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
434 props->qkey_viol_cntr = qkey_viol_cntr;
435
436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
442 goto out;
443
444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
465 out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
469 }
470
471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
474 {
475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
490 }
491
492 switch (gid_type) {
493 case IB_GID_TYPE_IB:
494 roce_version = MLX5_ROCE_VERSION_1;
495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
502 break;
503
504 default:
505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
506 }
507
508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
510 vlan_id, port_num);
511 }
512
513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
514 __always_unused void **context)
515 {
516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
517 attr->index, &attr->gid, attr);
518 }
519
520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
522 {
523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
525 }
526
527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
529 {
530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534 }
535
536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537 {
538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
541 }
542
543 enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547 };
548
549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550 {
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559 }
560
561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
562 u8 atomic_size_qp,
563 struct ib_device_attr *props)
564 {
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
567 u8 atomic_req_8B_endianness_mode =
568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581 }
582
583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585 {
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589 }
590
591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593 {
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597 }
598
599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600 {
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605 }
606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608 {
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
626
627 default:
628 return -EINVAL;
629 }
630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
636 }
637
638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640 {
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657 }
658
659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661 {
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675 }
676
677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679 {
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
694
695 default:
696 return -EINVAL;
697 }
698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
703 }
704
705 struct mlx5_reg_node_desc {
706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
707 };
708
709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710 {
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721 }
722
723 static int mlx5_ib_query_device(struct ib_device *ibdev,
724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
726 {
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
728 struct mlx5_core_dev *mdev = dev->mdev;
729 int err = -ENOMEM;
730 int max_sq_desc;
731 int max_rq_sg;
732 int max_sq_sg;
733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
734 bool raw_support = !mlx5_core_mp_enabled(mdev);
735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
738
739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
746 return -EINVAL;
747
748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
753
754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
755 if (err)
756 return err;
757
758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
761
762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
768 IB_DEVICE_RC_RNR_NAK_GEN;
769
770 if (MLX5_CAP_GEN(mdev, pkv))
771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
772 if (MLX5_CAP_GEN(mdev, qkv))
773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
774 if (MLX5_CAP_GEN(mdev, apm))
775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
776 if (MLX5_CAP_GEN(mdev, xrc))
777 props->device_cap_flags |= IB_DEVICE_XRC;
778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
784 }
785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
786 if (MLX5_CAP_GEN(mdev, sho)) {
787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
797
798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
808
809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
843 }
844
845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
862 /* Legacy bit to support old userspace libraries */
863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
866
867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
880
881 props->max_mr_size = ~0ull;
882 props->page_size_cap = ~(min_page_size - 1);
883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
893 props->max_sge_rd = MLX5_MAX_SGE_RD;
894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
904 props->max_srq_sge = max_rq_sg - 1;
905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
907 get_atomic_caps_qp(dev, props);
908 props->masked_atomic_cap = IB_ATOMIC_NONE;
909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
914 props->max_ah = INT_MAX;
915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
917
918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
919 if (MLX5_CAP_GEN(mdev, pg))
920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922 #endif
923
924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
931 IB_LINK_LAYER_ETHERNET && raw_support) {
932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
949 }
950
951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
959 resp.response_length += sizeof(resp.cqe_comp_caps);
960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
973 }
974 }
975
976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
1010
1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1017 }
1018
1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1077 }
1078
1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1086 return 0;
1087 }
1088
1089 enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095 };
1096
1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
1099 {
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
1119 }
1120
1121 return err;
1122 }
1123
1124 static int mlx5_mtu_to_ib_mtu(int mtu)
1125 {
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
1135 }
1136 }
1137
1138 enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144 };
1145
1146 enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156 };
1157
1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160 {
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
1177
1178 default:
1179 return -EINVAL;
1180 }
1181
1182 return 0;
1183 }
1184
1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
1187 {
1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
1191 u16 max_mtu;
1192 u16 oper_mtu;
1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
1196
1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
1200 goto out;
1201 }
1202
1203 /* props being zeroed by the caller, avoid zeroing it here */
1204
1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1206 if (err)
1207 goto out;
1208
1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
1223
1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1225 if (err)
1226 goto out;
1227
1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1230 if (err)
1231 goto out;
1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1233 if (err)
1234 goto out;
1235
1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1237
1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1239
1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1241
1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1243
1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1245 if (err)
1246 goto out;
1247
1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
1250 out:
1251 kfree(rep);
1252 return err;
1253 }
1254
1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
1257 {
1258 unsigned int count;
1259 int ret;
1260
1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1264 break;
1265
1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
1267 ret = mlx5_query_hca_port(ibdev, port, props);
1268 break;
1269
1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
1271 ret = mlx5_query_port_roce(ibdev, port, props);
1272 break;
1273
1274 default:
1275 ret = -EINVAL;
1276 }
1277
1278 if (!ret && props) {
1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1282
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1284 if (!mdev) {
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1287 */
1288 mdev = dev->mdev;
1289 port = 1;
1290 put_mdev = false;
1291 }
1292 count = mlx5_core_reserved_gids_count(mdev);
1293 if (put_mdev)
1294 mlx5_ib_put_native_port_mdev(dev, port);
1295 props->gid_tbl_len -= count;
1296 }
1297 return ret;
1298 }
1299
1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1302 {
1303 int ret;
1304
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1307 if (ret || !props)
1308 return ret;
1309
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1312
1313 return ret;
1314 }
1315
1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1317 union ib_gid *gid)
1318 {
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
1321
1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1325
1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1328
1329 default:
1330 return -EINVAL;
1331 }
1332
1333 }
1334
1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1337 {
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1341 u8 mdev_port_num;
1342 int err;
1343
1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1345 if (!mdev) {
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1348 */
1349 put_mdev = false;
1350 mdev = dev->mdev;
1351 mdev_port_num = 1;
1352 }
1353
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1355 index, pkey);
1356 if (put_mdev)
1357 mlx5_ib_put_native_port_mdev(dev, port);
1358
1359 return err;
1360 }
1361
1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1363 u16 *pkey)
1364 {
1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1368
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1372 default:
1373 return -EINVAL;
1374 }
1375 }
1376
1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1379 {
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1383 int err;
1384
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1386 return -EOPNOTSUPP;
1387
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1389 return 0;
1390
1391 /*
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1394 */
1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1398 if (err)
1399 return err;
1400
1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1402
1403 return err;
1404 }
1405
1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1407 u32 value)
1408 {
1409 struct mlx5_hca_vport_context ctx = {};
1410 struct mlx5_core_dev *mdev;
1411 u8 mdev_port_num;
1412 int err;
1413
1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1415 if (!mdev)
1416 return -ENODEV;
1417
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1419 if (err)
1420 goto out;
1421
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
1425 err = -EINVAL;
1426 goto out;
1427 }
1428
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1432 0, &ctx);
1433
1434 out:
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
1436
1437 return err;
1438 }
1439
1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1442 {
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1445 u32 tmp;
1446 int err;
1447 u32 change_mask;
1448 u32 value;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1451
1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1454 */
1455 if (!is_ib)
1456 return 0;
1457
1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1462 }
1463
1464 mutex_lock(&dev->cap_mask_mutex);
1465
1466 err = ib_query_port(ibdev, port, &attr);
1467 if (err)
1468 goto out;
1469
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1472
1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1474
1475 out:
1476 mutex_unlock(&dev->cap_mask_mutex);
1477 return err;
1478 }
1479
1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1481 {
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1484 }
1485
1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1487 {
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1491
1492 return MLX5_MAX_DYN_BFREGS;
1493 }
1494
1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1497 struct mlx5_bfreg_info *bfregi)
1498 {
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1502
1503 if (req->total_num_bfregs == 0)
1504 return -EINVAL;
1505
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1508
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1510 return -ENOMEM;
1511
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1514 /* This holds the required static allocation asked by the user */
1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1517 return -EINVAL;
1518
1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1523
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
1529
1530 return 0;
1531 }
1532
1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1534 {
1535 struct mlx5_bfreg_info *bfregi;
1536 int err;
1537 int i;
1538
1539 bfregi = &context->bfregi;
1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1542 if (err)
1543 goto error;
1544
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1546 }
1547
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1550
1551 return 0;
1552
1553 error:
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1557
1558 return err;
1559 }
1560
1561 static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
1563 {
1564 struct mlx5_bfreg_info *bfregi;
1565 int i;
1566
1567 bfregi = &context->bfregi;
1568 for (i = 0; i < bfregi->num_sys_pages; i++)
1569 if (i < bfregi->num_static_sys_pages ||
1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1572 }
1573
1574 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1575 {
1576 int err;
1577
1578 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1579 return 0;
1580
1581 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1582 if (err)
1583 return err;
1584
1585 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1586 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1587 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1588 return err;
1589
1590 mutex_lock(&dev->lb_mutex);
1591 dev->user_td++;
1592
1593 if (dev->user_td == 2)
1594 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1595
1596 mutex_unlock(&dev->lb_mutex);
1597 return err;
1598 }
1599
1600 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1601 {
1602 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1603 return;
1604
1605 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1606
1607 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1608 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1609 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1610 return;
1611
1612 mutex_lock(&dev->lb_mutex);
1613 dev->user_td--;
1614
1615 if (dev->user_td < 2)
1616 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1617
1618 mutex_unlock(&dev->lb_mutex);
1619 }
1620
1621 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1622 struct ib_udata *udata)
1623 {
1624 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1625 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1626 struct mlx5_ib_alloc_ucontext_resp resp = {};
1627 struct mlx5_core_dev *mdev = dev->mdev;
1628 struct mlx5_ib_ucontext *context;
1629 struct mlx5_bfreg_info *bfregi;
1630 int ver;
1631 int err;
1632 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1633 max_cqe_version);
1634 u32 dump_fill_mkey;
1635 bool lib_uar_4k;
1636
1637 if (!dev->ib_active)
1638 return ERR_PTR(-EAGAIN);
1639
1640 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1641 ver = 0;
1642 else if (udata->inlen >= min_req_v2)
1643 ver = 2;
1644 else
1645 return ERR_PTR(-EINVAL);
1646
1647 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1648 if (err)
1649 return ERR_PTR(err);
1650
1651 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1652 return ERR_PTR(-EOPNOTSUPP);
1653
1654 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1655 return ERR_PTR(-EOPNOTSUPP);
1656
1657 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1658 MLX5_NON_FP_BFREGS_PER_UAR);
1659 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1660 return ERR_PTR(-EINVAL);
1661
1662 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1663 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1664 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1665 resp.cache_line_size = cache_line_size();
1666 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1667 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1668 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1669 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1670 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1671 resp.cqe_version = min_t(__u8,
1672 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1673 req.max_cqe_version);
1674 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1675 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1676 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1677 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1678 resp.response_length = min(offsetof(typeof(resp), response_length) +
1679 sizeof(resp.response_length), udata->outlen);
1680
1681 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1682 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1683 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1684 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1685 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1686 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1687 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1688 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1689 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1690 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1691 }
1692
1693 context = kzalloc(sizeof(*context), GFP_KERNEL);
1694 if (!context)
1695 return ERR_PTR(-ENOMEM);
1696
1697 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1698 bfregi = &context->bfregi;
1699
1700 /* updates req->total_num_bfregs */
1701 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1702 if (err)
1703 goto out_ctx;
1704
1705 mutex_init(&bfregi->lock);
1706 bfregi->lib_uar_4k = lib_uar_4k;
1707 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1708 GFP_KERNEL);
1709 if (!bfregi->count) {
1710 err = -ENOMEM;
1711 goto out_ctx;
1712 }
1713
1714 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1715 sizeof(*bfregi->sys_pages),
1716 GFP_KERNEL);
1717 if (!bfregi->sys_pages) {
1718 err = -ENOMEM;
1719 goto out_count;
1720 }
1721
1722 err = allocate_uars(dev, context);
1723 if (err)
1724 goto out_sys_pages;
1725
1726 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1727 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1728 #endif
1729
1730 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1731 if (err)
1732 goto out_uars;
1733
1734 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1735 /* Block DEVX on Infiniband as of SELinux */
1736 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1737 err = -EPERM;
1738 goto out_td;
1739 }
1740
1741 err = mlx5_ib_devx_create(dev, context);
1742 if (err)
1743 goto out_td;
1744 }
1745
1746 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1747 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1748 if (err)
1749 goto out_mdev;
1750 }
1751
1752 INIT_LIST_HEAD(&context->vma_private_list);
1753 mutex_init(&context->vma_private_list_mutex);
1754 INIT_LIST_HEAD(&context->db_page_list);
1755 mutex_init(&context->db_page_mutex);
1756
1757 resp.tot_bfregs = req.total_num_bfregs;
1758 resp.num_ports = dev->num_ports;
1759
1760 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1761 resp.response_length += sizeof(resp.cqe_version);
1762
1763 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1764 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1765 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1766 resp.response_length += sizeof(resp.cmds_supp_uhw);
1767 }
1768
1769 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1770 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1771 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1772 resp.eth_min_inline++;
1773 }
1774 resp.response_length += sizeof(resp.eth_min_inline);
1775 }
1776
1777 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1778 if (mdev->clock_info)
1779 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1780 resp.response_length += sizeof(resp.clock_info_versions);
1781 }
1782
1783 /*
1784 * We don't want to expose information from the PCI bar that is located
1785 * after 4096 bytes, so if the arch only supports larger pages, let's
1786 * pretend we don't support reading the HCA's core clock. This is also
1787 * forced by mmap function.
1788 */
1789 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1790 if (PAGE_SIZE <= 4096) {
1791 resp.comp_mask |=
1792 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1793 resp.hca_core_clock_offset =
1794 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1795 }
1796 resp.response_length += sizeof(resp.hca_core_clock_offset);
1797 }
1798
1799 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1800 resp.response_length += sizeof(resp.log_uar_size);
1801
1802 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1803 resp.response_length += sizeof(resp.num_uars_per_page);
1804
1805 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1806 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1807 resp.response_length += sizeof(resp.num_dyn_bfregs);
1808 }
1809
1810 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1811 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1812 resp.dump_fill_mkey = dump_fill_mkey;
1813 resp.comp_mask |=
1814 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1815 }
1816 resp.response_length += sizeof(resp.dump_fill_mkey);
1817 }
1818
1819 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1820 if (err)
1821 goto out_mdev;
1822
1823 bfregi->ver = ver;
1824 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1825 context->cqe_version = resp.cqe_version;
1826 context->lib_caps = req.lib_caps;
1827 print_lib_caps(dev, context->lib_caps);
1828
1829 if (mlx5_lag_is_active(dev->mdev)) {
1830 u8 port = mlx5_core_native_port_num(dev->mdev);
1831
1832 atomic_set(&context->tx_port_affinity,
1833 atomic_add_return(
1834 1, &dev->roce[port].tx_port_affinity));
1835 }
1836
1837 return &context->ibucontext;
1838
1839 out_mdev:
1840 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1841 mlx5_ib_devx_destroy(dev, context);
1842 out_td:
1843 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1844
1845 out_uars:
1846 deallocate_uars(dev, context);
1847
1848 out_sys_pages:
1849 kfree(bfregi->sys_pages);
1850
1851 out_count:
1852 kfree(bfregi->count);
1853
1854 out_ctx:
1855 kfree(context);
1856
1857 return ERR_PTR(err);
1858 }
1859
1860 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1861 {
1862 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1863 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1864 struct mlx5_bfreg_info *bfregi;
1865
1866 if (context->devx_uid)
1867 mlx5_ib_devx_destroy(dev, context);
1868
1869 bfregi = &context->bfregi;
1870 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1871
1872 deallocate_uars(dev, context);
1873 kfree(bfregi->sys_pages);
1874 kfree(bfregi->count);
1875 kfree(context);
1876
1877 return 0;
1878 }
1879
1880 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1881 int uar_idx)
1882 {
1883 int fw_uars_per_page;
1884
1885 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1886
1887 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1888 }
1889
1890 static int get_command(unsigned long offset)
1891 {
1892 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1893 }
1894
1895 static int get_arg(unsigned long offset)
1896 {
1897 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1898 }
1899
1900 static int get_index(unsigned long offset)
1901 {
1902 return get_arg(offset);
1903 }
1904
1905 /* Index resides in an extra byte to enable larger values than 255 */
1906 static int get_extended_index(unsigned long offset)
1907 {
1908 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1909 }
1910
1911 static void mlx5_ib_vma_open(struct vm_area_struct *area)
1912 {
1913 /* vma_open is called when a new VMA is created on top of our VMA. This
1914 * is done through either mremap flow or split_vma (usually due to
1915 * mlock, madvise, munmap, etc.) We do not support a clone of the VMA,
1916 * as this VMA is strongly hardware related. Therefore we set the
1917 * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
1918 * calling us again and trying to do incorrect actions. We assume that
1919 * the original VMA size is exactly a single page, and therefore all
1920 * "splitting" operation will not happen to it.
1921 */
1922 area->vm_ops = NULL;
1923 }
1924
1925 static void mlx5_ib_vma_close(struct vm_area_struct *area)
1926 {
1927 struct mlx5_ib_vma_private_data *mlx5_ib_vma_priv_data;
1928
1929 /* It's guaranteed that all VMAs opened on a FD are closed before the
1930 * file itself is closed, therefore no sync is needed with the regular
1931 * closing flow. (e.g. mlx5 ib_dealloc_ucontext)
1932 * However need a sync with accessing the vma as part of
1933 * mlx5_ib_disassociate_ucontext.
1934 * The close operation is usually called under mm->mmap_sem except when
1935 * process is exiting.
1936 * The exiting case is handled explicitly as part of
1937 * mlx5_ib_disassociate_ucontext.
1938 */
1939 mlx5_ib_vma_priv_data = (struct mlx5_ib_vma_private_data *)area->vm_private_data;
1940
1941 /* setting the vma context pointer to null in the mlx5_ib driver's
1942 * private data, to protect a race condition in
1943 * mlx5_ib_disassociate_ucontext().
1944 */
1945 mlx5_ib_vma_priv_data->vma = NULL;
1946 mutex_lock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1947 list_del(&mlx5_ib_vma_priv_data->list);
1948 mutex_unlock(mlx5_ib_vma_priv_data->vma_private_list_mutex);
1949 kfree(mlx5_ib_vma_priv_data);
1950 }
1951
1952 static const struct vm_operations_struct mlx5_ib_vm_ops = {
1953 .open = mlx5_ib_vma_open,
1954 .close = mlx5_ib_vma_close
1955 };
1956
1957 static int mlx5_ib_set_vma_data(struct vm_area_struct *vma,
1958 struct mlx5_ib_ucontext *ctx)
1959 {
1960 struct mlx5_ib_vma_private_data *vma_prv;
1961 struct list_head *vma_head = &ctx->vma_private_list;
1962
1963 vma_prv = kzalloc(sizeof(*vma_prv), GFP_KERNEL);
1964 if (!vma_prv)
1965 return -ENOMEM;
1966
1967 vma_prv->vma = vma;
1968 vma_prv->vma_private_list_mutex = &ctx->vma_private_list_mutex;
1969 vma->vm_private_data = vma_prv;
1970 vma->vm_ops = &mlx5_ib_vm_ops;
1971
1972 mutex_lock(&ctx->vma_private_list_mutex);
1973 list_add(&vma_prv->list, vma_head);
1974 mutex_unlock(&ctx->vma_private_list_mutex);
1975
1976 return 0;
1977 }
1978
1979 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1980 {
1981 struct vm_area_struct *vma;
1982 struct mlx5_ib_vma_private_data *vma_private, *n;
1983 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1984
1985 mutex_lock(&context->vma_private_list_mutex);
1986 list_for_each_entry_safe(vma_private, n, &context->vma_private_list,
1987 list) {
1988 vma = vma_private->vma;
1989 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
1990 /* context going to be destroyed, should
1991 * not access ops any more.
1992 */
1993 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
1994 vma->vm_ops = NULL;
1995 list_del(&vma_private->list);
1996 kfree(vma_private);
1997 }
1998 mutex_unlock(&context->vma_private_list_mutex);
1999 }
2000
2001 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
2002 {
2003 switch (cmd) {
2004 case MLX5_IB_MMAP_WC_PAGE:
2005 return "WC";
2006 case MLX5_IB_MMAP_REGULAR_PAGE:
2007 return "best effort WC";
2008 case MLX5_IB_MMAP_NC_PAGE:
2009 return "NC";
2010 case MLX5_IB_MMAP_DEVICE_MEM:
2011 return "Device Memory";
2012 default:
2013 return NULL;
2014 }
2015 }
2016
2017 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
2018 struct vm_area_struct *vma,
2019 struct mlx5_ib_ucontext *context)
2020 {
2021 phys_addr_t pfn;
2022 int err;
2023
2024 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2025 return -EINVAL;
2026
2027 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
2028 return -EOPNOTSUPP;
2029
2030 if (vma->vm_flags & VM_WRITE)
2031 return -EPERM;
2032
2033 if (!dev->mdev->clock_info_page)
2034 return -EOPNOTSUPP;
2035
2036 pfn = page_to_pfn(dev->mdev->clock_info_page);
2037 err = remap_pfn_range(vma, vma->vm_start, pfn, PAGE_SIZE,
2038 vma->vm_page_prot);
2039 if (err)
2040 return err;
2041
2042 return mlx5_ib_set_vma_data(vma, context);
2043 }
2044
2045 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
2046 struct vm_area_struct *vma,
2047 struct mlx5_ib_ucontext *context)
2048 {
2049 struct mlx5_bfreg_info *bfregi = &context->bfregi;
2050 int err;
2051 unsigned long idx;
2052 phys_addr_t pfn;
2053 pgprot_t prot;
2054 u32 bfreg_dyn_idx = 0;
2055 u32 uar_index;
2056 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
2057 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
2058 bfregi->num_static_sys_pages;
2059
2060 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2061 return -EINVAL;
2062
2063 if (dyn_uar)
2064 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2065 else
2066 idx = get_index(vma->vm_pgoff);
2067
2068 if (idx >= max_valid_idx) {
2069 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2070 idx, max_valid_idx);
2071 return -EINVAL;
2072 }
2073
2074 switch (cmd) {
2075 case MLX5_IB_MMAP_WC_PAGE:
2076 case MLX5_IB_MMAP_ALLOC_WC:
2077 /* Some architectures don't support WC memory */
2078 #if defined(CONFIG_X86)
2079 if (!pat_enabled())
2080 return -EPERM;
2081 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2082 return -EPERM;
2083 #endif
2084 /* fall through */
2085 case MLX5_IB_MMAP_REGULAR_PAGE:
2086 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2087 prot = pgprot_writecombine(vma->vm_page_prot);
2088 break;
2089 case MLX5_IB_MMAP_NC_PAGE:
2090 prot = pgprot_noncached(vma->vm_page_prot);
2091 break;
2092 default:
2093 return -EINVAL;
2094 }
2095
2096 if (dyn_uar) {
2097 int uars_per_page;
2098
2099 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2100 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2101 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2102 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2103 bfreg_dyn_idx, bfregi->total_num_bfregs);
2104 return -EINVAL;
2105 }
2106
2107 mutex_lock(&bfregi->lock);
2108 /* Fail if uar already allocated, first bfreg index of each
2109 * page holds its count.
2110 */
2111 if (bfregi->count[bfreg_dyn_idx]) {
2112 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2113 mutex_unlock(&bfregi->lock);
2114 return -EINVAL;
2115 }
2116
2117 bfregi->count[bfreg_dyn_idx]++;
2118 mutex_unlock(&bfregi->lock);
2119
2120 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2121 if (err) {
2122 mlx5_ib_warn(dev, "UAR alloc failed\n");
2123 goto free_bfreg;
2124 }
2125 } else {
2126 uar_index = bfregi->sys_pages[idx];
2127 }
2128
2129 pfn = uar_index2pfn(dev, uar_index);
2130 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2131
2132 vma->vm_page_prot = prot;
2133 err = io_remap_pfn_range(vma, vma->vm_start, pfn,
2134 PAGE_SIZE, vma->vm_page_prot);
2135 if (err) {
2136 mlx5_ib_err(dev,
2137 "io_remap_pfn_range failed with error=%d, mmap_cmd=%s\n",
2138 err, mmap_cmd2str(cmd));
2139 err = -EAGAIN;
2140 goto err;
2141 }
2142
2143 err = mlx5_ib_set_vma_data(vma, context);
2144 if (err)
2145 goto err;
2146
2147 if (dyn_uar)
2148 bfregi->sys_pages[idx] = uar_index;
2149 return 0;
2150
2151 err:
2152 if (!dyn_uar)
2153 return err;
2154
2155 mlx5_cmd_free_uar(dev->mdev, idx);
2156
2157 free_bfreg:
2158 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2159
2160 return err;
2161 }
2162
2163 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2164 {
2165 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2166 struct mlx5_ib_dev *dev = to_mdev(context->device);
2167 u16 page_idx = get_extended_index(vma->vm_pgoff);
2168 size_t map_size = vma->vm_end - vma->vm_start;
2169 u32 npages = map_size >> PAGE_SHIFT;
2170 phys_addr_t pfn;
2171 pgprot_t prot;
2172
2173 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2174 page_idx + npages)
2175 return -EINVAL;
2176
2177 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2178 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2179 PAGE_SHIFT) +
2180 page_idx;
2181 prot = pgprot_writecombine(vma->vm_page_prot);
2182 vma->vm_page_prot = prot;
2183
2184 if (io_remap_pfn_range(vma, vma->vm_start, pfn, map_size,
2185 vma->vm_page_prot))
2186 return -EAGAIN;
2187
2188 return mlx5_ib_set_vma_data(vma, mctx);
2189 }
2190
2191 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2192 {
2193 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2194 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2195 unsigned long command;
2196 phys_addr_t pfn;
2197
2198 command = get_command(vma->vm_pgoff);
2199 switch (command) {
2200 case MLX5_IB_MMAP_WC_PAGE:
2201 case MLX5_IB_MMAP_NC_PAGE:
2202 case MLX5_IB_MMAP_REGULAR_PAGE:
2203 case MLX5_IB_MMAP_ALLOC_WC:
2204 return uar_mmap(dev, command, vma, context);
2205
2206 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2207 return -ENOSYS;
2208
2209 case MLX5_IB_MMAP_CORE_CLOCK:
2210 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2211 return -EINVAL;
2212
2213 if (vma->vm_flags & VM_WRITE)
2214 return -EPERM;
2215
2216 /* Don't expose to user-space information it shouldn't have */
2217 if (PAGE_SIZE > 4096)
2218 return -EOPNOTSUPP;
2219
2220 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2221 pfn = (dev->mdev->iseg_base +
2222 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2223 PAGE_SHIFT;
2224 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2225 PAGE_SIZE, vma->vm_page_prot))
2226 return -EAGAIN;
2227 break;
2228 case MLX5_IB_MMAP_CLOCK_INFO:
2229 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2230
2231 case MLX5_IB_MMAP_DEVICE_MEM:
2232 return dm_mmap(ibcontext, vma);
2233
2234 default:
2235 return -EINVAL;
2236 }
2237
2238 return 0;
2239 }
2240
2241 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2242 struct ib_ucontext *context,
2243 struct ib_dm_alloc_attr *attr,
2244 struct uverbs_attr_bundle *attrs)
2245 {
2246 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2247 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2248 phys_addr_t memic_addr;
2249 struct mlx5_ib_dm *dm;
2250 u64 start_offset;
2251 u32 page_idx;
2252 int err;
2253
2254 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2255 if (!dm)
2256 return ERR_PTR(-ENOMEM);
2257
2258 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2259 attr->length, act_size, attr->alignment);
2260
2261 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2262 act_size, attr->alignment);
2263 if (err)
2264 goto err_free;
2265
2266 start_offset = memic_addr & ~PAGE_MASK;
2267 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2268 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2269 PAGE_SHIFT;
2270
2271 err = uverbs_copy_to(attrs,
2272 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2273 &start_offset, sizeof(start_offset));
2274 if (err)
2275 goto err_dealloc;
2276
2277 err = uverbs_copy_to(attrs,
2278 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2279 &page_idx, sizeof(page_idx));
2280 if (err)
2281 goto err_dealloc;
2282
2283 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2284 DIV_ROUND_UP(act_size, PAGE_SIZE));
2285
2286 dm->dev_addr = memic_addr;
2287
2288 return &dm->ibdm;
2289
2290 err_dealloc:
2291 mlx5_cmd_dealloc_memic(memic, memic_addr,
2292 act_size);
2293 err_free:
2294 kfree(dm);
2295 return ERR_PTR(err);
2296 }
2297
2298 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2299 {
2300 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2301 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2302 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2303 u32 page_idx;
2304 int ret;
2305
2306 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2307 if (ret)
2308 return ret;
2309
2310 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2311 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2312 PAGE_SHIFT;
2313 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2314 page_idx,
2315 DIV_ROUND_UP(act_size, PAGE_SIZE));
2316
2317 kfree(dm);
2318
2319 return 0;
2320 }
2321
2322 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2323 struct ib_ucontext *context,
2324 struct ib_udata *udata)
2325 {
2326 struct mlx5_ib_alloc_pd_resp resp;
2327 struct mlx5_ib_pd *pd;
2328 int err;
2329
2330 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2331 if (!pd)
2332 return ERR_PTR(-ENOMEM);
2333
2334 err = mlx5_core_alloc_pd(to_mdev(ibdev)->mdev, &pd->pdn);
2335 if (err) {
2336 kfree(pd);
2337 return ERR_PTR(err);
2338 }
2339
2340 if (context) {
2341 resp.pdn = pd->pdn;
2342 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2343 mlx5_core_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn);
2344 kfree(pd);
2345 return ERR_PTR(-EFAULT);
2346 }
2347 }
2348
2349 return &pd->ibpd;
2350 }
2351
2352 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2353 {
2354 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2355 struct mlx5_ib_pd *mpd = to_mpd(pd);
2356
2357 mlx5_core_dealloc_pd(mdev->mdev, mpd->pdn);
2358 kfree(mpd);
2359
2360 return 0;
2361 }
2362
2363 enum {
2364 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2365 MATCH_CRITERIA_ENABLE_MISC_BIT,
2366 MATCH_CRITERIA_ENABLE_INNER_BIT,
2367 MATCH_CRITERIA_ENABLE_MISC2_BIT
2368 };
2369
2370 #define HEADER_IS_ZERO(match_criteria, headers) \
2371 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2372 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2373
2374 static u8 get_match_criteria_enable(u32 *match_criteria)
2375 {
2376 u8 match_criteria_enable;
2377
2378 match_criteria_enable =
2379 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2380 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2381 match_criteria_enable |=
2382 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2383 MATCH_CRITERIA_ENABLE_MISC_BIT;
2384 match_criteria_enable |=
2385 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2386 MATCH_CRITERIA_ENABLE_INNER_BIT;
2387 match_criteria_enable |=
2388 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2389 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2390
2391 return match_criteria_enable;
2392 }
2393
2394 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2395 {
2396 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2397 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2398 }
2399
2400 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2401 bool inner)
2402 {
2403 if (inner) {
2404 MLX5_SET(fte_match_set_misc,
2405 misc_c, inner_ipv6_flow_label, mask);
2406 MLX5_SET(fte_match_set_misc,
2407 misc_v, inner_ipv6_flow_label, val);
2408 } else {
2409 MLX5_SET(fte_match_set_misc,
2410 misc_c, outer_ipv6_flow_label, mask);
2411 MLX5_SET(fte_match_set_misc,
2412 misc_v, outer_ipv6_flow_label, val);
2413 }
2414 }
2415
2416 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2417 {
2418 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2419 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2420 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2421 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2422 }
2423
2424 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2425 {
2426 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2427 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2428 return -EOPNOTSUPP;
2429
2430 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2431 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2432 return -EOPNOTSUPP;
2433
2434 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2435 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2436 return -EOPNOTSUPP;
2437
2438 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2439 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2440 return -EOPNOTSUPP;
2441
2442 return 0;
2443 }
2444
2445 #define LAST_ETH_FIELD vlan_tag
2446 #define LAST_IB_FIELD sl
2447 #define LAST_IPV4_FIELD tos
2448 #define LAST_IPV6_FIELD traffic_class
2449 #define LAST_TCP_UDP_FIELD src_port
2450 #define LAST_TUNNEL_FIELD tunnel_id
2451 #define LAST_FLOW_TAG_FIELD tag_id
2452 #define LAST_DROP_FIELD size
2453 #define LAST_COUNTERS_FIELD counters
2454
2455 /* Field is the last supported field */
2456 #define FIELDS_NOT_SUPPORTED(filter, field)\
2457 memchr_inv((void *)&filter.field +\
2458 sizeof(filter.field), 0,\
2459 sizeof(filter) -\
2460 offsetof(typeof(filter), field) -\
2461 sizeof(filter.field))
2462
2463 static int parse_flow_flow_action(const union ib_flow_spec *ib_spec,
2464 const struct ib_flow_attr *flow_attr,
2465 struct mlx5_flow_act *action)
2466 {
2467 struct mlx5_ib_flow_action *maction = to_mflow_act(ib_spec->action.act);
2468
2469 switch (maction->ib_action.type) {
2470 case IB_FLOW_ACTION_ESP:
2471 /* Currently only AES_GCM keymat is supported by the driver */
2472 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2473 action->action |= flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS ?
2474 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2475 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2476 return 0;
2477 case IB_FLOW_ACTION_UNSPECIFIED:
2478 if (maction->flow_action_raw.sub_type ==
2479 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2480 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2481 action->modify_id = maction->flow_action_raw.action_id;
2482 return 0;
2483 }
2484 /* fall through */
2485 default:
2486 return -EOPNOTSUPP;
2487 }
2488 }
2489
2490 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2491 u32 *match_v, const union ib_flow_spec *ib_spec,
2492 const struct ib_flow_attr *flow_attr,
2493 struct mlx5_flow_act *action, u32 prev_type)
2494 {
2495 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2496 misc_parameters);
2497 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2498 misc_parameters);
2499 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2500 misc_parameters_2);
2501 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2502 misc_parameters_2);
2503 void *headers_c;
2504 void *headers_v;
2505 int match_ipv;
2506 int ret;
2507
2508 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2509 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2510 inner_headers);
2511 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2512 inner_headers);
2513 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2514 ft_field_support.inner_ip_version);
2515 } else {
2516 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2517 outer_headers);
2518 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2519 outer_headers);
2520 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2521 ft_field_support.outer_ip_version);
2522 }
2523
2524 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2525 case IB_FLOW_SPEC_ETH:
2526 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2527 return -EOPNOTSUPP;
2528
2529 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2530 dmac_47_16),
2531 ib_spec->eth.mask.dst_mac);
2532 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2533 dmac_47_16),
2534 ib_spec->eth.val.dst_mac);
2535
2536 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2537 smac_47_16),
2538 ib_spec->eth.mask.src_mac);
2539 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2540 smac_47_16),
2541 ib_spec->eth.val.src_mac);
2542
2543 if (ib_spec->eth.mask.vlan_tag) {
2544 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2545 cvlan_tag, 1);
2546 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2547 cvlan_tag, 1);
2548
2549 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2550 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2551 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2552 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2553
2554 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2555 first_cfi,
2556 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2557 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2558 first_cfi,
2559 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2560
2561 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2562 first_prio,
2563 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2564 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2565 first_prio,
2566 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2567 }
2568 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2569 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2570 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2571 ethertype, ntohs(ib_spec->eth.val.ether_type));
2572 break;
2573 case IB_FLOW_SPEC_IPV4:
2574 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2575 return -EOPNOTSUPP;
2576
2577 if (match_ipv) {
2578 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2579 ip_version, 0xf);
2580 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2581 ip_version, MLX5_FS_IPV4_VERSION);
2582 } else {
2583 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2584 ethertype, 0xffff);
2585 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2586 ethertype, ETH_P_IP);
2587 }
2588
2589 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2590 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2591 &ib_spec->ipv4.mask.src_ip,
2592 sizeof(ib_spec->ipv4.mask.src_ip));
2593 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2594 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2595 &ib_spec->ipv4.val.src_ip,
2596 sizeof(ib_spec->ipv4.val.src_ip));
2597 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2598 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2599 &ib_spec->ipv4.mask.dst_ip,
2600 sizeof(ib_spec->ipv4.mask.dst_ip));
2601 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2602 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2603 &ib_spec->ipv4.val.dst_ip,
2604 sizeof(ib_spec->ipv4.val.dst_ip));
2605
2606 set_tos(headers_c, headers_v,
2607 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2608
2609 set_proto(headers_c, headers_v,
2610 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2611 break;
2612 case IB_FLOW_SPEC_IPV6:
2613 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2614 return -EOPNOTSUPP;
2615
2616 if (match_ipv) {
2617 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2618 ip_version, 0xf);
2619 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2620 ip_version, MLX5_FS_IPV6_VERSION);
2621 } else {
2622 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2623 ethertype, 0xffff);
2624 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2625 ethertype, ETH_P_IPV6);
2626 }
2627
2628 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2629 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2630 &ib_spec->ipv6.mask.src_ip,
2631 sizeof(ib_spec->ipv6.mask.src_ip));
2632 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2633 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2634 &ib_spec->ipv6.val.src_ip,
2635 sizeof(ib_spec->ipv6.val.src_ip));
2636 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2637 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2638 &ib_spec->ipv6.mask.dst_ip,
2639 sizeof(ib_spec->ipv6.mask.dst_ip));
2640 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2641 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2642 &ib_spec->ipv6.val.dst_ip,
2643 sizeof(ib_spec->ipv6.val.dst_ip));
2644
2645 set_tos(headers_c, headers_v,
2646 ib_spec->ipv6.mask.traffic_class,
2647 ib_spec->ipv6.val.traffic_class);
2648
2649 set_proto(headers_c, headers_v,
2650 ib_spec->ipv6.mask.next_hdr,
2651 ib_spec->ipv6.val.next_hdr);
2652
2653 set_flow_label(misc_params_c, misc_params_v,
2654 ntohl(ib_spec->ipv6.mask.flow_label),
2655 ntohl(ib_spec->ipv6.val.flow_label),
2656 ib_spec->type & IB_FLOW_SPEC_INNER);
2657 break;
2658 case IB_FLOW_SPEC_ESP:
2659 if (ib_spec->esp.mask.seq)
2660 return -EOPNOTSUPP;
2661
2662 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2663 ntohl(ib_spec->esp.mask.spi));
2664 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2665 ntohl(ib_spec->esp.val.spi));
2666 break;
2667 case IB_FLOW_SPEC_TCP:
2668 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2669 LAST_TCP_UDP_FIELD))
2670 return -EOPNOTSUPP;
2671
2672 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2673 0xff);
2674 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2675 IPPROTO_TCP);
2676
2677 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2678 ntohs(ib_spec->tcp_udp.mask.src_port));
2679 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2680 ntohs(ib_spec->tcp_udp.val.src_port));
2681
2682 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2683 ntohs(ib_spec->tcp_udp.mask.dst_port));
2684 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2685 ntohs(ib_spec->tcp_udp.val.dst_port));
2686 break;
2687 case IB_FLOW_SPEC_UDP:
2688 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2689 LAST_TCP_UDP_FIELD))
2690 return -EOPNOTSUPP;
2691
2692 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2693 0xff);
2694 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2695 IPPROTO_UDP);
2696
2697 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2698 ntohs(ib_spec->tcp_udp.mask.src_port));
2699 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2700 ntohs(ib_spec->tcp_udp.val.src_port));
2701
2702 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2703 ntohs(ib_spec->tcp_udp.mask.dst_port));
2704 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2705 ntohs(ib_spec->tcp_udp.val.dst_port));
2706 break;
2707 case IB_FLOW_SPEC_GRE:
2708 if (ib_spec->gre.mask.c_ks_res0_ver)
2709 return -EOPNOTSUPP;
2710
2711 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2712 0xff);
2713 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2714 IPPROTO_GRE);
2715
2716 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2717 ntohs(ib_spec->gre.mask.protocol));
2718 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2719 ntohs(ib_spec->gre.val.protocol));
2720
2721 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2722 gre_key_h),
2723 &ib_spec->gre.mask.key,
2724 sizeof(ib_spec->gre.mask.key));
2725 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2726 gre_key_h),
2727 &ib_spec->gre.val.key,
2728 sizeof(ib_spec->gre.val.key));
2729 break;
2730 case IB_FLOW_SPEC_MPLS:
2731 switch (prev_type) {
2732 case IB_FLOW_SPEC_UDP:
2733 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2734 ft_field_support.outer_first_mpls_over_udp),
2735 &ib_spec->mpls.mask.tag))
2736 return -EOPNOTSUPP;
2737
2738 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2739 outer_first_mpls_over_udp),
2740 &ib_spec->mpls.val.tag,
2741 sizeof(ib_spec->mpls.val.tag));
2742 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2743 outer_first_mpls_over_udp),
2744 &ib_spec->mpls.mask.tag,
2745 sizeof(ib_spec->mpls.mask.tag));
2746 break;
2747 case IB_FLOW_SPEC_GRE:
2748 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2749 ft_field_support.outer_first_mpls_over_gre),
2750 &ib_spec->mpls.mask.tag))
2751 return -EOPNOTSUPP;
2752
2753 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2754 outer_first_mpls_over_gre),
2755 &ib_spec->mpls.val.tag,
2756 sizeof(ib_spec->mpls.val.tag));
2757 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2758 outer_first_mpls_over_gre),
2759 &ib_spec->mpls.mask.tag,
2760 sizeof(ib_spec->mpls.mask.tag));
2761 break;
2762 default:
2763 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2764 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2765 ft_field_support.inner_first_mpls),
2766 &ib_spec->mpls.mask.tag))
2767 return -EOPNOTSUPP;
2768
2769 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2770 inner_first_mpls),
2771 &ib_spec->mpls.val.tag,
2772 sizeof(ib_spec->mpls.val.tag));
2773 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2774 inner_first_mpls),
2775 &ib_spec->mpls.mask.tag,
2776 sizeof(ib_spec->mpls.mask.tag));
2777 } else {
2778 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2779 ft_field_support.outer_first_mpls),
2780 &ib_spec->mpls.mask.tag))
2781 return -EOPNOTSUPP;
2782
2783 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2784 outer_first_mpls),
2785 &ib_spec->mpls.val.tag,
2786 sizeof(ib_spec->mpls.val.tag));
2787 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2788 outer_first_mpls),
2789 &ib_spec->mpls.mask.tag,
2790 sizeof(ib_spec->mpls.mask.tag));
2791 }
2792 }
2793 break;
2794 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2795 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2796 LAST_TUNNEL_FIELD))
2797 return -EOPNOTSUPP;
2798
2799 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2800 ntohl(ib_spec->tunnel.mask.tunnel_id));
2801 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2802 ntohl(ib_spec->tunnel.val.tunnel_id));
2803 break;
2804 case IB_FLOW_SPEC_ACTION_TAG:
2805 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2806 LAST_FLOW_TAG_FIELD))
2807 return -EOPNOTSUPP;
2808 if (ib_spec->flow_tag.tag_id >= BIT(24))
2809 return -EINVAL;
2810
2811 action->flow_tag = ib_spec->flow_tag.tag_id;
2812 action->has_flow_tag = true;
2813 break;
2814 case IB_FLOW_SPEC_ACTION_DROP:
2815 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2816 LAST_DROP_FIELD))
2817 return -EOPNOTSUPP;
2818 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2819 break;
2820 case IB_FLOW_SPEC_ACTION_HANDLE:
2821 ret = parse_flow_flow_action(ib_spec, flow_attr, action);
2822 if (ret)
2823 return ret;
2824 break;
2825 case IB_FLOW_SPEC_ACTION_COUNT:
2826 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2827 LAST_COUNTERS_FIELD))
2828 return -EOPNOTSUPP;
2829
2830 /* for now support only one counters spec per flow */
2831 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2832 return -EINVAL;
2833
2834 action->counters = ib_spec->flow_count.counters;
2835 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2836 break;
2837 default:
2838 return -EINVAL;
2839 }
2840
2841 return 0;
2842 }
2843
2844 /* If a flow could catch both multicast and unicast packets,
2845 * it won't fall into the multicast flow steering table and this rule
2846 * could steal other multicast packets.
2847 */
2848 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2849 {
2850 union ib_flow_spec *flow_spec;
2851
2852 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2853 ib_attr->num_of_specs < 1)
2854 return false;
2855
2856 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2857 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2858 struct ib_flow_spec_ipv4 *ipv4_spec;
2859
2860 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2861 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2862 return true;
2863
2864 return false;
2865 }
2866
2867 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2868 struct ib_flow_spec_eth *eth_spec;
2869
2870 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2871 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2872 is_multicast_ether_addr(eth_spec->val.dst_mac);
2873 }
2874
2875 return false;
2876 }
2877
2878 enum valid_spec {
2879 VALID_SPEC_INVALID,
2880 VALID_SPEC_VALID,
2881 VALID_SPEC_NA,
2882 };
2883
2884 static enum valid_spec
2885 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2886 const struct mlx5_flow_spec *spec,
2887 const struct mlx5_flow_act *flow_act,
2888 bool egress)
2889 {
2890 const u32 *match_c = spec->match_criteria;
2891 bool is_crypto =
2892 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2893 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2894 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2895 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2896
2897 /*
2898 * Currently only crypto is supported in egress, when regular egress
2899 * rules would be supported, always return VALID_SPEC_NA.
2900 */
2901 if (!is_crypto)
2902 return VALID_SPEC_NA;
2903
2904 return is_crypto && is_ipsec &&
2905 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2906 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2907 }
2908
2909 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2910 const struct mlx5_flow_spec *spec,
2911 const struct mlx5_flow_act *flow_act,
2912 bool egress)
2913 {
2914 /* We curretly only support ipsec egress flow */
2915 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2916 }
2917
2918 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2919 const struct ib_flow_attr *flow_attr,
2920 bool check_inner)
2921 {
2922 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2923 int match_ipv = check_inner ?
2924 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2925 ft_field_support.inner_ip_version) :
2926 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2927 ft_field_support.outer_ip_version);
2928 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2929 bool ipv4_spec_valid, ipv6_spec_valid;
2930 unsigned int ip_spec_type = 0;
2931 bool has_ethertype = false;
2932 unsigned int spec_index;
2933 bool mask_valid = true;
2934 u16 eth_type = 0;
2935 bool type_valid;
2936
2937 /* Validate that ethertype is correct */
2938 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2939 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2940 ib_spec->eth.mask.ether_type) {
2941 mask_valid = (ib_spec->eth.mask.ether_type ==
2942 htons(0xffff));
2943 has_ethertype = true;
2944 eth_type = ntohs(ib_spec->eth.val.ether_type);
2945 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2946 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2947 ip_spec_type = ib_spec->type;
2948 }
2949 ib_spec = (void *)ib_spec + ib_spec->size;
2950 }
2951
2952 type_valid = (!has_ethertype) || (!ip_spec_type);
2953 if (!type_valid && mask_valid) {
2954 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2955 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2956 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2957 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2958
2959 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2960 (((eth_type == ETH_P_MPLS_UC) ||
2961 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2962 }
2963
2964 return type_valid;
2965 }
2966
2967 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2968 const struct ib_flow_attr *flow_attr)
2969 {
2970 return is_valid_ethertype(mdev, flow_attr, false) &&
2971 is_valid_ethertype(mdev, flow_attr, true);
2972 }
2973
2974 static void put_flow_table(struct mlx5_ib_dev *dev,
2975 struct mlx5_ib_flow_prio *prio, bool ft_added)
2976 {
2977 prio->refcount -= !!ft_added;
2978 if (!prio->refcount) {
2979 mlx5_destroy_flow_table(prio->flow_table);
2980 prio->flow_table = NULL;
2981 }
2982 }
2983
2984 static void counters_clear_description(struct ib_counters *counters)
2985 {
2986 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2987
2988 mutex_lock(&mcounters->mcntrs_mutex);
2989 kfree(mcounters->counters_data);
2990 mcounters->counters_data = NULL;
2991 mcounters->cntrs_max_index = 0;
2992 mutex_unlock(&mcounters->mcntrs_mutex);
2993 }
2994
2995 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2996 {
2997 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2998 struct mlx5_ib_flow_handler,
2999 ibflow);
3000 struct mlx5_ib_flow_handler *iter, *tmp;
3001 struct mlx5_ib_dev *dev = handler->dev;
3002
3003 mutex_lock(&dev->flow_db->lock);
3004
3005 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
3006 mlx5_del_flow_rules(iter->rule);
3007 put_flow_table(dev, iter->prio, true);
3008 list_del(&iter->list);
3009 kfree(iter);
3010 }
3011
3012 mlx5_del_flow_rules(handler->rule);
3013 put_flow_table(dev, handler->prio, true);
3014 if (handler->ibcounters &&
3015 atomic_read(&handler->ibcounters->usecnt) == 1)
3016 counters_clear_description(handler->ibcounters);
3017
3018 mutex_unlock(&dev->flow_db->lock);
3019 if (handler->flow_matcher)
3020 atomic_dec(&handler->flow_matcher->usecnt);
3021 kfree(handler);
3022
3023 return 0;
3024 }
3025
3026 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
3027 {
3028 priority *= 2;
3029 if (!dont_trap)
3030 priority++;
3031 return priority;
3032 }
3033
3034 enum flow_table_type {
3035 MLX5_IB_FT_RX,
3036 MLX5_IB_FT_TX
3037 };
3038
3039 #define MLX5_FS_MAX_TYPES 6
3040 #define MLX5_FS_MAX_ENTRIES BIT(16)
3041
3042 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3043 struct mlx5_ib_flow_prio *prio,
3044 int priority,
3045 int num_entries, int num_groups,
3046 u32 flags)
3047 {
3048 struct mlx5_flow_table *ft;
3049
3050 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3051 num_entries,
3052 num_groups,
3053 0, flags);
3054 if (IS_ERR(ft))
3055 return ERR_CAST(ft);
3056
3057 prio->flow_table = ft;
3058 prio->refcount = 0;
3059 return prio;
3060 }
3061
3062 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3063 struct ib_flow_attr *flow_attr,
3064 enum flow_table_type ft_type)
3065 {
3066 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3067 struct mlx5_flow_namespace *ns = NULL;
3068 struct mlx5_ib_flow_prio *prio;
3069 struct mlx5_flow_table *ft;
3070 int max_table_size;
3071 int num_entries;
3072 int num_groups;
3073 u32 flags = 0;
3074 int priority;
3075
3076 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3077 log_max_ft_size));
3078 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3079 enum mlx5_flow_namespace_type fn_type;
3080
3081 if (flow_is_multicast_only(flow_attr) &&
3082 !dont_trap)
3083 priority = MLX5_IB_FLOW_MCAST_PRIO;
3084 else
3085 priority = ib_prio_to_core_prio(flow_attr->priority,
3086 dont_trap);
3087 if (ft_type == MLX5_IB_FT_RX) {
3088 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3089 prio = &dev->flow_db->prios[priority];
3090 if (!dev->rep &&
3091 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3092 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3093 } else {
3094 max_table_size =
3095 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3096 log_max_ft_size));
3097 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3098 prio = &dev->flow_db->egress_prios[priority];
3099 if (!dev->rep &&
3100 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3101 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3102 }
3103 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3104 num_entries = MLX5_FS_MAX_ENTRIES;
3105 num_groups = MLX5_FS_MAX_TYPES;
3106 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3107 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3108 ns = mlx5_get_flow_namespace(dev->mdev,
3109 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3110 build_leftovers_ft_param(&priority,
3111 &num_entries,
3112 &num_groups);
3113 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3114 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3115 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3116 allow_sniffer_and_nic_rx_shared_tir))
3117 return ERR_PTR(-ENOTSUPP);
3118
3119 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3120 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3121 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3122
3123 prio = &dev->flow_db->sniffer[ft_type];
3124 priority = 0;
3125 num_entries = 1;
3126 num_groups = 1;
3127 }
3128
3129 if (!ns)
3130 return ERR_PTR(-ENOTSUPP);
3131
3132 if (num_entries > max_table_size)
3133 return ERR_PTR(-ENOMEM);
3134
3135 ft = prio->flow_table;
3136 if (!ft)
3137 return _get_prio(ns, prio, priority, num_entries, num_groups,
3138 flags);
3139
3140 return prio;
3141 }
3142
3143 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3144 struct mlx5_flow_spec *spec,
3145 u32 underlay_qpn)
3146 {
3147 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3148 spec->match_criteria,
3149 misc_parameters);
3150 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3151 misc_parameters);
3152
3153 if (underlay_qpn &&
3154 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3155 ft_field_support.bth_dst_qp)) {
3156 MLX5_SET(fte_match_set_misc,
3157 misc_params_v, bth_dst_qp, underlay_qpn);
3158 MLX5_SET(fte_match_set_misc,
3159 misc_params_c, bth_dst_qp, 0xffffff);
3160 }
3161 }
3162
3163 static int read_flow_counters(struct ib_device *ibdev,
3164 struct mlx5_read_counters_attr *read_attr)
3165 {
3166 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3167 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3168
3169 return mlx5_fc_query(dev->mdev, fc,
3170 &read_attr->out[IB_COUNTER_PACKETS],
3171 &read_attr->out[IB_COUNTER_BYTES]);
3172 }
3173
3174 /* flow counters currently expose two counters packets and bytes */
3175 #define FLOW_COUNTERS_NUM 2
3176 static int counters_set_description(struct ib_counters *counters,
3177 enum mlx5_ib_counters_type counters_type,
3178 struct mlx5_ib_flow_counters_desc *desc_data,
3179 u32 ncounters)
3180 {
3181 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3182 u32 cntrs_max_index = 0;
3183 int i;
3184
3185 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3186 return -EINVAL;
3187
3188 /* init the fields for the object */
3189 mcounters->type = counters_type;
3190 mcounters->read_counters = read_flow_counters;
3191 mcounters->counters_num = FLOW_COUNTERS_NUM;
3192 mcounters->ncounters = ncounters;
3193 /* each counter entry have both description and index pair */
3194 for (i = 0; i < ncounters; i++) {
3195 if (desc_data[i].description > IB_COUNTER_BYTES)
3196 return -EINVAL;
3197
3198 if (cntrs_max_index <= desc_data[i].index)
3199 cntrs_max_index = desc_data[i].index + 1;
3200 }
3201
3202 mutex_lock(&mcounters->mcntrs_mutex);
3203 mcounters->counters_data = desc_data;
3204 mcounters->cntrs_max_index = cntrs_max_index;
3205 mutex_unlock(&mcounters->mcntrs_mutex);
3206
3207 return 0;
3208 }
3209
3210 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3211 static int flow_counters_set_data(struct ib_counters *ibcounters,
3212 struct mlx5_ib_create_flow *ucmd)
3213 {
3214 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3215 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3216 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3217 bool hw_hndl = false;
3218 int ret = 0;
3219
3220 if (ucmd && ucmd->ncounters_data != 0) {
3221 cntrs_data = ucmd->data;
3222 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3223 return -EINVAL;
3224
3225 desc_data = kcalloc(cntrs_data->ncounters,
3226 sizeof(*desc_data),
3227 GFP_KERNEL);
3228 if (!desc_data)
3229 return -ENOMEM;
3230
3231 if (copy_from_user(desc_data,
3232 u64_to_user_ptr(cntrs_data->counters_data),
3233 sizeof(*desc_data) * cntrs_data->ncounters)) {
3234 ret = -EFAULT;
3235 goto free;
3236 }
3237 }
3238
3239 if (!mcounters->hw_cntrs_hndl) {
3240 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3241 to_mdev(ibcounters->device)->mdev, false);
3242 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3243 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3244 goto free;
3245 }
3246 hw_hndl = true;
3247 }
3248
3249 if (desc_data) {
3250 /* counters already bound to at least one flow */
3251 if (mcounters->cntrs_max_index) {
3252 ret = -EINVAL;
3253 goto free_hndl;
3254 }
3255
3256 ret = counters_set_description(ibcounters,
3257 MLX5_IB_COUNTERS_FLOW,
3258 desc_data,
3259 cntrs_data->ncounters);
3260 if (ret)
3261 goto free_hndl;
3262
3263 } else if (!mcounters->cntrs_max_index) {
3264 /* counters not bound yet, must have udata passed */
3265 ret = -EINVAL;
3266 goto free_hndl;
3267 }
3268
3269 return 0;
3270
3271 free_hndl:
3272 if (hw_hndl) {
3273 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3274 mcounters->hw_cntrs_hndl);
3275 mcounters->hw_cntrs_hndl = NULL;
3276 }
3277 free:
3278 kfree(desc_data);
3279 return ret;
3280 }
3281
3282 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3283 struct mlx5_ib_flow_prio *ft_prio,
3284 const struct ib_flow_attr *flow_attr,
3285 struct mlx5_flow_destination *dst,
3286 u32 underlay_qpn,
3287 struct mlx5_ib_create_flow *ucmd)
3288 {
3289 struct mlx5_flow_table *ft = ft_prio->flow_table;
3290 struct mlx5_ib_flow_handler *handler;
3291 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3292 struct mlx5_flow_spec *spec;
3293 struct mlx5_flow_destination dest_arr[2] = {};
3294 struct mlx5_flow_destination *rule_dst = dest_arr;
3295 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3296 unsigned int spec_index;
3297 u32 prev_type = 0;
3298 int err = 0;
3299 int dest_num = 0;
3300 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3301
3302 if (!is_valid_attr(dev->mdev, flow_attr))
3303 return ERR_PTR(-EINVAL);
3304
3305 if (dev->rep && is_egress)
3306 return ERR_PTR(-EINVAL);
3307
3308 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3309 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3310 if (!handler || !spec) {
3311 err = -ENOMEM;
3312 goto free;
3313 }
3314
3315 INIT_LIST_HEAD(&handler->list);
3316 if (dst) {
3317 memcpy(&dest_arr[0], dst, sizeof(*dst));
3318 dest_num++;
3319 }
3320
3321 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3322 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3323 spec->match_value,
3324 ib_flow, flow_attr, &flow_act,
3325 prev_type);
3326 if (err < 0)
3327 goto free;
3328
3329 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3330 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3331 }
3332
3333 if (!flow_is_multicast_only(flow_attr))
3334 set_underlay_qp(dev, spec, underlay_qpn);
3335
3336 if (dev->rep) {
3337 void *misc;
3338
3339 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3340 misc_parameters);
3341 MLX5_SET(fte_match_set_misc, misc, source_port,
3342 dev->rep->vport);
3343 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3344 misc_parameters);
3345 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3346 }
3347
3348 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3349
3350 if (is_egress &&
3351 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3352 err = -EINVAL;
3353 goto free;
3354 }
3355
3356 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3357 err = flow_counters_set_data(flow_act.counters, ucmd);
3358 if (err)
3359 goto free;
3360
3361 handler->ibcounters = flow_act.counters;
3362 dest_arr[dest_num].type =
3363 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3364 dest_arr[dest_num].counter =
3365 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3366 dest_num++;
3367 }
3368
3369 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3370 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3371 rule_dst = NULL;
3372 dest_num = 0;
3373 }
3374 } else {
3375 if (is_egress)
3376 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3377 else
3378 flow_act.action |=
3379 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3380 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3381 }
3382
3383 if (flow_act.has_flow_tag &&
3384 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3385 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3386 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3387 flow_act.flow_tag, flow_attr->type);
3388 err = -EINVAL;
3389 goto free;
3390 }
3391 handler->rule = mlx5_add_flow_rules(ft, spec,
3392 &flow_act,
3393 rule_dst, dest_num);
3394
3395 if (IS_ERR(handler->rule)) {
3396 err = PTR_ERR(handler->rule);
3397 goto free;
3398 }
3399
3400 ft_prio->refcount++;
3401 handler->prio = ft_prio;
3402 handler->dev = dev;
3403
3404 ft_prio->flow_table = ft;
3405 free:
3406 if (err && handler) {
3407 if (handler->ibcounters &&
3408 atomic_read(&handler->ibcounters->usecnt) == 1)
3409 counters_clear_description(handler->ibcounters);
3410 kfree(handler);
3411 }
3412 kvfree(spec);
3413 return err ? ERR_PTR(err) : handler;
3414 }
3415
3416 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3417 struct mlx5_ib_flow_prio *ft_prio,
3418 const struct ib_flow_attr *flow_attr,
3419 struct mlx5_flow_destination *dst)
3420 {
3421 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3422 }
3423
3424 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3425 struct mlx5_ib_flow_prio *ft_prio,
3426 struct ib_flow_attr *flow_attr,
3427 struct mlx5_flow_destination *dst)
3428 {
3429 struct mlx5_ib_flow_handler *handler_dst = NULL;
3430 struct mlx5_ib_flow_handler *handler = NULL;
3431
3432 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3433 if (!IS_ERR(handler)) {
3434 handler_dst = create_flow_rule(dev, ft_prio,
3435 flow_attr, dst);
3436 if (IS_ERR(handler_dst)) {
3437 mlx5_del_flow_rules(handler->rule);
3438 ft_prio->refcount--;
3439 kfree(handler);
3440 handler = handler_dst;
3441 } else {
3442 list_add(&handler_dst->list, &handler->list);
3443 }
3444 }
3445
3446 return handler;
3447 }
3448 enum {
3449 LEFTOVERS_MC,
3450 LEFTOVERS_UC,
3451 };
3452
3453 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3454 struct mlx5_ib_flow_prio *ft_prio,
3455 struct ib_flow_attr *flow_attr,
3456 struct mlx5_flow_destination *dst)
3457 {
3458 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3459 struct mlx5_ib_flow_handler *handler = NULL;
3460
3461 static struct {
3462 struct ib_flow_attr flow_attr;
3463 struct ib_flow_spec_eth eth_flow;
3464 } leftovers_specs[] = {
3465 [LEFTOVERS_MC] = {
3466 .flow_attr = {
3467 .num_of_specs = 1,
3468 .size = sizeof(leftovers_specs[0])
3469 },
3470 .eth_flow = {
3471 .type = IB_FLOW_SPEC_ETH,
3472 .size = sizeof(struct ib_flow_spec_eth),
3473 .mask = {.dst_mac = {0x1} },
3474 .val = {.dst_mac = {0x1} }
3475 }
3476 },
3477 [LEFTOVERS_UC] = {
3478 .flow_attr = {
3479 .num_of_specs = 1,
3480 .size = sizeof(leftovers_specs[0])
3481 },
3482 .eth_flow = {
3483 .type = IB_FLOW_SPEC_ETH,
3484 .size = sizeof(struct ib_flow_spec_eth),
3485 .mask = {.dst_mac = {0x1} },
3486 .val = {.dst_mac = {} }
3487 }
3488 }
3489 };
3490
3491 handler = create_flow_rule(dev, ft_prio,
3492 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3493 dst);
3494 if (!IS_ERR(handler) &&
3495 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3496 handler_ucast = create_flow_rule(dev, ft_prio,
3497 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3498 dst);
3499 if (IS_ERR(handler_ucast)) {
3500 mlx5_del_flow_rules(handler->rule);
3501 ft_prio->refcount--;
3502 kfree(handler);
3503 handler = handler_ucast;
3504 } else {
3505 list_add(&handler_ucast->list, &handler->list);
3506 }
3507 }
3508
3509 return handler;
3510 }
3511
3512 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3513 struct mlx5_ib_flow_prio *ft_rx,
3514 struct mlx5_ib_flow_prio *ft_tx,
3515 struct mlx5_flow_destination *dst)
3516 {
3517 struct mlx5_ib_flow_handler *handler_rx;
3518 struct mlx5_ib_flow_handler *handler_tx;
3519 int err;
3520 static const struct ib_flow_attr flow_attr = {
3521 .num_of_specs = 0,
3522 .size = sizeof(flow_attr)
3523 };
3524
3525 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3526 if (IS_ERR(handler_rx)) {
3527 err = PTR_ERR(handler_rx);
3528 goto err;
3529 }
3530
3531 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3532 if (IS_ERR(handler_tx)) {
3533 err = PTR_ERR(handler_tx);
3534 goto err_tx;
3535 }
3536
3537 list_add(&handler_tx->list, &handler_rx->list);
3538
3539 return handler_rx;
3540
3541 err_tx:
3542 mlx5_del_flow_rules(handler_rx->rule);
3543 ft_rx->refcount--;
3544 kfree(handler_rx);
3545 err:
3546 return ERR_PTR(err);
3547 }
3548
3549 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3550 struct ib_flow_attr *flow_attr,
3551 int domain,
3552 struct ib_udata *udata)
3553 {
3554 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3555 struct mlx5_ib_qp *mqp = to_mqp(qp);
3556 struct mlx5_ib_flow_handler *handler = NULL;
3557 struct mlx5_flow_destination *dst = NULL;
3558 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3559 struct mlx5_ib_flow_prio *ft_prio;
3560 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3561 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3562 size_t min_ucmd_sz, required_ucmd_sz;
3563 int err;
3564 int underlay_qpn;
3565
3566 if (udata && udata->inlen) {
3567 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3568 sizeof(ucmd_hdr.reserved);
3569 if (udata->inlen < min_ucmd_sz)
3570 return ERR_PTR(-EOPNOTSUPP);
3571
3572 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3573 if (err)
3574 return ERR_PTR(err);
3575
3576 /* currently supports only one counters data */
3577 if (ucmd_hdr.ncounters_data > 1)
3578 return ERR_PTR(-EINVAL);
3579
3580 required_ucmd_sz = min_ucmd_sz +
3581 sizeof(struct mlx5_ib_flow_counters_data) *
3582 ucmd_hdr.ncounters_data;
3583 if (udata->inlen > required_ucmd_sz &&
3584 !ib_is_udata_cleared(udata, required_ucmd_sz,
3585 udata->inlen - required_ucmd_sz))
3586 return ERR_PTR(-EOPNOTSUPP);
3587
3588 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3589 if (!ucmd)
3590 return ERR_PTR(-ENOMEM);
3591
3592 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3593 if (err)
3594 goto free_ucmd;
3595 }
3596
3597 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3598 err = -ENOMEM;
3599 goto free_ucmd;
3600 }
3601
3602 if (domain != IB_FLOW_DOMAIN_USER ||
3603 flow_attr->port > dev->num_ports ||
3604 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3605 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3606 err = -EINVAL;
3607 goto free_ucmd;
3608 }
3609
3610 if (is_egress &&
3611 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3612 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3613 err = -EINVAL;
3614 goto free_ucmd;
3615 }
3616
3617 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3618 if (!dst) {
3619 err = -ENOMEM;
3620 goto free_ucmd;
3621 }
3622
3623 mutex_lock(&dev->flow_db->lock);
3624
3625 ft_prio = get_flow_table(dev, flow_attr,
3626 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3627 if (IS_ERR(ft_prio)) {
3628 err = PTR_ERR(ft_prio);
3629 goto unlock;
3630 }
3631 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3632 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3633 if (IS_ERR(ft_prio_tx)) {
3634 err = PTR_ERR(ft_prio_tx);
3635 ft_prio_tx = NULL;
3636 goto destroy_ft;
3637 }
3638 }
3639
3640 if (is_egress) {
3641 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3642 } else {
3643 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3644 if (mqp->flags & MLX5_IB_QP_RSS)
3645 dst->tir_num = mqp->rss_qp.tirn;
3646 else
3647 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3648 }
3649
3650 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3651 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3652 handler = create_dont_trap_rule(dev, ft_prio,
3653 flow_attr, dst);
3654 } else {
3655 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3656 mqp->underlay_qpn : 0;
3657 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3658 dst, underlay_qpn, ucmd);
3659 }
3660 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3661 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3662 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3663 dst);
3664 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3665 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3666 } else {
3667 err = -EINVAL;
3668 goto destroy_ft;
3669 }
3670
3671 if (IS_ERR(handler)) {
3672 err = PTR_ERR(handler);
3673 handler = NULL;
3674 goto destroy_ft;
3675 }
3676
3677 mutex_unlock(&dev->flow_db->lock);
3678 kfree(dst);
3679 kfree(ucmd);
3680
3681 return &handler->ibflow;
3682
3683 destroy_ft:
3684 put_flow_table(dev, ft_prio, false);
3685 if (ft_prio_tx)
3686 put_flow_table(dev, ft_prio_tx, false);
3687 unlock:
3688 mutex_unlock(&dev->flow_db->lock);
3689 kfree(dst);
3690 free_ucmd:
3691 kfree(ucmd);
3692 return ERR_PTR(err);
3693 }
3694
3695 static struct mlx5_ib_flow_prio *_get_flow_table(struct mlx5_ib_dev *dev,
3696 int priority, bool mcast)
3697 {
3698 int max_table_size;
3699 struct mlx5_flow_namespace *ns = NULL;
3700 struct mlx5_ib_flow_prio *prio;
3701
3702 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3703 log_max_ft_size));
3704 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3705 return ERR_PTR(-ENOMEM);
3706
3707 if (mcast)
3708 priority = MLX5_IB_FLOW_MCAST_PRIO;
3709 else
3710 priority = ib_prio_to_core_prio(priority, false);
3711
3712 ns = mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS);
3713 if (!ns)
3714 return ERR_PTR(-ENOTSUPP);
3715
3716 prio = &dev->flow_db->prios[priority];
3717
3718 if (prio->flow_table)
3719 return prio;
3720
3721 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3722 MLX5_FS_MAX_TYPES, 0);
3723 }
3724
3725 static struct mlx5_ib_flow_handler *
3726 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3727 struct mlx5_ib_flow_prio *ft_prio,
3728 struct mlx5_flow_destination *dst,
3729 struct mlx5_ib_flow_matcher *fs_matcher,
3730 void *cmd_in, int inlen)
3731 {
3732 struct mlx5_ib_flow_handler *handler;
3733 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3734 struct mlx5_flow_spec *spec;
3735 struct mlx5_flow_table *ft = ft_prio->flow_table;
3736 int err = 0;
3737
3738 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3739 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3740 if (!handler || !spec) {
3741 err = -ENOMEM;
3742 goto free;
3743 }
3744
3745 INIT_LIST_HEAD(&handler->list);
3746
3747 memcpy(spec->match_value, cmd_in, inlen);
3748 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3749 fs_matcher->mask_len);
3750 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3751
3752 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3753 handler->rule = mlx5_add_flow_rules(ft, spec,
3754 &flow_act, dst, 1);
3755
3756 if (IS_ERR(handler->rule)) {
3757 err = PTR_ERR(handler->rule);
3758 goto free;
3759 }
3760
3761 ft_prio->refcount++;
3762 handler->prio = ft_prio;
3763 handler->dev = dev;
3764 ft_prio->flow_table = ft;
3765
3766 free:
3767 if (err)
3768 kfree(handler);
3769 kvfree(spec);
3770 return err ? ERR_PTR(err) : handler;
3771 }
3772
3773 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3774 void *match_v)
3775 {
3776 void *match_c;
3777 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3778 void *dmac, *dmac_mask;
3779 void *ipv4, *ipv4_mask;
3780
3781 if (!(fs_matcher->match_criteria_enable &
3782 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3783 return false;
3784
3785 match_c = fs_matcher->matcher_mask.match_params;
3786 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3787 outer_headers);
3788 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3789 outer_headers);
3790
3791 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3792 dmac_47_16);
3793 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3794 dmac_47_16);
3795
3796 if (is_multicast_ether_addr(dmac) &&
3797 is_multicast_ether_addr(dmac_mask))
3798 return true;
3799
3800 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3801 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3802
3803 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3804 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3805
3806 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3807 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3808 return true;
3809
3810 return false;
3811 }
3812
3813 struct mlx5_ib_flow_handler *
3814 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3815 struct mlx5_ib_flow_matcher *fs_matcher,
3816 void *cmd_in, int inlen, int dest_id,
3817 int dest_type)
3818 {
3819 struct mlx5_flow_destination *dst;
3820 struct mlx5_ib_flow_prio *ft_prio;
3821 int priority = fs_matcher->priority;
3822 struct mlx5_ib_flow_handler *handler;
3823 bool mcast;
3824 int err;
3825
3826 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3827 return ERR_PTR(-EOPNOTSUPP);
3828
3829 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3830 return ERR_PTR(-ENOMEM);
3831
3832 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3833 if (!dst)
3834 return ERR_PTR(-ENOMEM);
3835
3836 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3837 mutex_lock(&dev->flow_db->lock);
3838
3839 ft_prio = _get_flow_table(dev, priority, mcast);
3840 if (IS_ERR(ft_prio)) {
3841 err = PTR_ERR(ft_prio);
3842 goto unlock;
3843 }
3844
3845 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3846 dst->type = dest_type;
3847 dst->tir_num = dest_id;
3848 } else {
3849 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3850 dst->ft_num = dest_id;
3851 }
3852
3853 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, cmd_in,
3854 inlen);
3855
3856 if (IS_ERR(handler)) {
3857 err = PTR_ERR(handler);
3858 goto destroy_ft;
3859 }
3860
3861 mutex_unlock(&dev->flow_db->lock);
3862 atomic_inc(&fs_matcher->usecnt);
3863 handler->flow_matcher = fs_matcher;
3864
3865 kfree(dst);
3866
3867 return handler;
3868
3869 destroy_ft:
3870 put_flow_table(dev, ft_prio, false);
3871 unlock:
3872 mutex_unlock(&dev->flow_db->lock);
3873 kfree(dst);
3874
3875 return ERR_PTR(err);
3876 }
3877
3878 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3879 {
3880 u32 flags = 0;
3881
3882 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3883 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3884
3885 return flags;
3886 }
3887
3888 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3889 static struct ib_flow_action *
3890 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3891 const struct ib_flow_action_attrs_esp *attr,
3892 struct uverbs_attr_bundle *attrs)
3893 {
3894 struct mlx5_ib_dev *mdev = to_mdev(device);
3895 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3896 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3897 struct mlx5_ib_flow_action *action;
3898 u64 action_flags;
3899 u64 flags;
3900 int err = 0;
3901
3902 err = uverbs_get_flags64(
3903 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3904 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3905 if (err)
3906 return ERR_PTR(err);
3907
3908 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3909
3910 /* We current only support a subset of the standard features. Only a
3911 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3912 * (with overlap). Full offload mode isn't supported.
3913 */
3914 if (!attr->keymat || attr->replay || attr->encap ||
3915 attr->spi || attr->seq || attr->tfc_pad ||
3916 attr->hard_limit_pkts ||
3917 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3918 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3919 return ERR_PTR(-EOPNOTSUPP);
3920
3921 if (attr->keymat->protocol !=
3922 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3923 return ERR_PTR(-EOPNOTSUPP);
3924
3925 aes_gcm = &attr->keymat->keymat.aes_gcm;
3926
3927 if (aes_gcm->icv_len != 16 ||
3928 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3929 return ERR_PTR(-EOPNOTSUPP);
3930
3931 action = kmalloc(sizeof(*action), GFP_KERNEL);
3932 if (!action)
3933 return ERR_PTR(-ENOMEM);
3934
3935 action->esp_aes_gcm.ib_flags = attr->flags;
3936 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3937 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3938 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3939 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3940 sizeof(accel_attrs.keymat.aes_gcm.salt));
3941 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3942 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3943 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3944 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3945 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3946
3947 accel_attrs.esn = attr->esn;
3948 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3949 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3950 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3951 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3952
3953 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3954 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3955
3956 action->esp_aes_gcm.ctx =
3957 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3958 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3959 err = PTR_ERR(action->esp_aes_gcm.ctx);
3960 goto err_parse;
3961 }
3962
3963 action->esp_aes_gcm.ib_flags = attr->flags;
3964
3965 return &action->ib_action;
3966
3967 err_parse:
3968 kfree(action);
3969 return ERR_PTR(err);
3970 }
3971
3972 static int
3973 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3974 const struct ib_flow_action_attrs_esp *attr,
3975 struct uverbs_attr_bundle *attrs)
3976 {
3977 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3978 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3979 int err = 0;
3980
3981 if (attr->keymat || attr->replay || attr->encap ||
3982 attr->spi || attr->seq || attr->tfc_pad ||
3983 attr->hard_limit_pkts ||
3984 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3985 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3986 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3987 return -EOPNOTSUPP;
3988
3989 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3990 * be modified.
3991 */
3992 if (!(maction->esp_aes_gcm.ib_flags &
3993 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3994 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3995 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3996 return -EINVAL;
3997
3998 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3999 sizeof(accel_attrs));
4000
4001 accel_attrs.esn = attr->esn;
4002 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
4003 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4004 else
4005 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
4006
4007 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
4008 &accel_attrs);
4009 if (err)
4010 return err;
4011
4012 maction->esp_aes_gcm.ib_flags &=
4013 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4014 maction->esp_aes_gcm.ib_flags |=
4015 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4016
4017 return 0;
4018 }
4019
4020 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4021 {
4022 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4023
4024 switch (action->type) {
4025 case IB_FLOW_ACTION_ESP:
4026 /*
4027 * We only support aes_gcm by now, so we implicitly know this is
4028 * the underline crypto.
4029 */
4030 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4031 break;
4032 case IB_FLOW_ACTION_UNSPECIFIED:
4033 mlx5_ib_destroy_flow_action_raw(maction);
4034 break;
4035 default:
4036 WARN_ON(true);
4037 break;
4038 }
4039
4040 kfree(maction);
4041 return 0;
4042 }
4043
4044 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4045 {
4046 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4047 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4048 int err;
4049
4050 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4051 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4052 return -EOPNOTSUPP;
4053 }
4054
4055 err = mlx5_core_attach_mcg(dev->mdev, gid, ibqp->qp_num);
4056 if (err)
4057 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4058 ibqp->qp_num, gid->raw);
4059
4060 return err;
4061 }
4062
4063 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4064 {
4065 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4066 int err;
4067
4068 err = mlx5_core_detach_mcg(dev->mdev, gid, ibqp->qp_num);
4069 if (err)
4070 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4071 ibqp->qp_num, gid->raw);
4072
4073 return err;
4074 }
4075
4076 static int init_node_data(struct mlx5_ib_dev *dev)
4077 {
4078 int err;
4079
4080 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4081 if (err)
4082 return err;
4083
4084 dev->mdev->rev_id = dev->mdev->pdev->revision;
4085
4086 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4087 }
4088
4089 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4090 char *buf)
4091 {
4092 struct mlx5_ib_dev *dev =
4093 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4094
4095 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4096 }
4097
4098 static ssize_t show_reg_pages(struct device *device,
4099 struct device_attribute *attr, char *buf)
4100 {
4101 struct mlx5_ib_dev *dev =
4102 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4103
4104 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4105 }
4106
4107 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4108 char *buf)
4109 {
4110 struct mlx5_ib_dev *dev =
4111 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4112 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4113 }
4114
4115 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4116 char *buf)
4117 {
4118 struct mlx5_ib_dev *dev =
4119 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4120 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4121 }
4122
4123 static ssize_t show_board(struct device *device, struct device_attribute *attr,
4124 char *buf)
4125 {
4126 struct mlx5_ib_dev *dev =
4127 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4128 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4129 dev->mdev->board_id);
4130 }
4131
4132 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
4133 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4134 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4135 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4136 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4137
4138 static struct device_attribute *mlx5_class_attributes[] = {
4139 &dev_attr_hw_rev,
4140 &dev_attr_hca_type,
4141 &dev_attr_board_id,
4142 &dev_attr_fw_pages,
4143 &dev_attr_reg_pages,
4144 };
4145
4146 static void pkey_change_handler(struct work_struct *work)
4147 {
4148 struct mlx5_ib_port_resources *ports =
4149 container_of(work, struct mlx5_ib_port_resources,
4150 pkey_change_work);
4151
4152 mutex_lock(&ports->devr->mutex);
4153 mlx5_ib_gsi_pkey_change(ports->gsi);
4154 mutex_unlock(&ports->devr->mutex);
4155 }
4156
4157 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4158 {
4159 struct mlx5_ib_qp *mqp;
4160 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4161 struct mlx5_core_cq *mcq;
4162 struct list_head cq_armed_list;
4163 unsigned long flags_qp;
4164 unsigned long flags_cq;
4165 unsigned long flags;
4166
4167 INIT_LIST_HEAD(&cq_armed_list);
4168
4169 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4170 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4171 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4172 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4173 if (mqp->sq.tail != mqp->sq.head) {
4174 send_mcq = to_mcq(mqp->ibqp.send_cq);
4175 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4176 if (send_mcq->mcq.comp &&
4177 mqp->ibqp.send_cq->comp_handler) {
4178 if (!send_mcq->mcq.reset_notify_added) {
4179 send_mcq->mcq.reset_notify_added = 1;
4180 list_add_tail(&send_mcq->mcq.reset_notify,
4181 &cq_armed_list);
4182 }
4183 }
4184 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4185 }
4186 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4187 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4188 /* no handling is needed for SRQ */
4189 if (!mqp->ibqp.srq) {
4190 if (mqp->rq.tail != mqp->rq.head) {
4191 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4192 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4193 if (recv_mcq->mcq.comp &&
4194 mqp->ibqp.recv_cq->comp_handler) {
4195 if (!recv_mcq->mcq.reset_notify_added) {
4196 recv_mcq->mcq.reset_notify_added = 1;
4197 list_add_tail(&recv_mcq->mcq.reset_notify,
4198 &cq_armed_list);
4199 }
4200 }
4201 spin_unlock_irqrestore(&recv_mcq->lock,
4202 flags_cq);
4203 }
4204 }
4205 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4206 }
4207 /*At that point all inflight post send were put to be executed as of we
4208 * lock/unlock above locks Now need to arm all involved CQs.
4209 */
4210 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4211 mcq->comp(mcq);
4212 }
4213 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4214 }
4215
4216 static void delay_drop_handler(struct work_struct *work)
4217 {
4218 int err;
4219 struct mlx5_ib_delay_drop *delay_drop =
4220 container_of(work, struct mlx5_ib_delay_drop,
4221 delay_drop_work);
4222
4223 atomic_inc(&delay_drop->events_cnt);
4224
4225 mutex_lock(&delay_drop->lock);
4226 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4227 delay_drop->timeout);
4228 if (err) {
4229 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4230 delay_drop->timeout);
4231 delay_drop->activate = false;
4232 }
4233 mutex_unlock(&delay_drop->lock);
4234 }
4235
4236 static void mlx5_ib_handle_event(struct work_struct *_work)
4237 {
4238 struct mlx5_ib_event_work *work =
4239 container_of(_work, struct mlx5_ib_event_work, work);
4240 struct mlx5_ib_dev *ibdev;
4241 struct ib_event ibev;
4242 bool fatal = false;
4243 u8 port = (u8)work->param;
4244
4245 if (mlx5_core_is_mp_slave(work->dev)) {
4246 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4247 if (!ibdev)
4248 goto out;
4249 } else {
4250 ibdev = work->context;
4251 }
4252
4253 switch (work->event) {
4254 case MLX5_DEV_EVENT_SYS_ERROR:
4255 ibev.event = IB_EVENT_DEVICE_FATAL;
4256 mlx5_ib_handle_internal_error(ibdev);
4257 fatal = true;
4258 break;
4259
4260 case MLX5_DEV_EVENT_PORT_UP:
4261 case MLX5_DEV_EVENT_PORT_DOWN:
4262 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4263 /* In RoCE, port up/down events are handled in
4264 * mlx5_netdev_event().
4265 */
4266 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4267 IB_LINK_LAYER_ETHERNET)
4268 goto out;
4269
4270 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4271 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4272 break;
4273
4274 case MLX5_DEV_EVENT_LID_CHANGE:
4275 ibev.event = IB_EVENT_LID_CHANGE;
4276 break;
4277
4278 case MLX5_DEV_EVENT_PKEY_CHANGE:
4279 ibev.event = IB_EVENT_PKEY_CHANGE;
4280 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4281 break;
4282
4283 case MLX5_DEV_EVENT_GUID_CHANGE:
4284 ibev.event = IB_EVENT_GID_CHANGE;
4285 break;
4286
4287 case MLX5_DEV_EVENT_CLIENT_REREG:
4288 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4289 break;
4290 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4291 schedule_work(&ibdev->delay_drop.delay_drop_work);
4292 goto out;
4293 default:
4294 goto out;
4295 }
4296
4297 ibev.device = &ibdev->ib_dev;
4298 ibev.element.port_num = port;
4299
4300 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4301 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4302 goto out;
4303 }
4304
4305 if (ibdev->ib_active)
4306 ib_dispatch_event(&ibev);
4307
4308 if (fatal)
4309 ibdev->ib_active = false;
4310 out:
4311 kfree(work);
4312 }
4313
4314 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4315 enum mlx5_dev_event event, unsigned long param)
4316 {
4317 struct mlx5_ib_event_work *work;
4318
4319 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4320 if (!work)
4321 return;
4322
4323 INIT_WORK(&work->work, mlx5_ib_handle_event);
4324 work->dev = dev;
4325 work->param = param;
4326 work->context = context;
4327 work->event = event;
4328
4329 queue_work(mlx5_ib_event_wq, &work->work);
4330 }
4331
4332 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4333 {
4334 struct mlx5_hca_vport_context vport_ctx;
4335 int err;
4336 int port;
4337
4338 for (port = 1; port <= dev->num_ports; port++) {
4339 dev->mdev->port_caps[port - 1].has_smi = false;
4340 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4341 MLX5_CAP_PORT_TYPE_IB) {
4342 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4343 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4344 port, 0,
4345 &vport_ctx);
4346 if (err) {
4347 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4348 port, err);
4349 return err;
4350 }
4351 dev->mdev->port_caps[port - 1].has_smi =
4352 vport_ctx.has_smi;
4353 } else {
4354 dev->mdev->port_caps[port - 1].has_smi = true;
4355 }
4356 }
4357 }
4358 return 0;
4359 }
4360
4361 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4362 {
4363 int port;
4364
4365 for (port = 1; port <= dev->num_ports; port++)
4366 mlx5_query_ext_port_caps(dev, port);
4367 }
4368
4369 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4370 {
4371 struct ib_device_attr *dprops = NULL;
4372 struct ib_port_attr *pprops = NULL;
4373 int err = -ENOMEM;
4374 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4375
4376 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4377 if (!pprops)
4378 goto out;
4379
4380 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4381 if (!dprops)
4382 goto out;
4383
4384 err = set_has_smi_cap(dev);
4385 if (err)
4386 goto out;
4387
4388 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4389 if (err) {
4390 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4391 goto out;
4392 }
4393
4394 memset(pprops, 0, sizeof(*pprops));
4395 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4396 if (err) {
4397 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4398 port, err);
4399 goto out;
4400 }
4401
4402 dev->mdev->port_caps[port - 1].pkey_table_len =
4403 dprops->max_pkeys;
4404 dev->mdev->port_caps[port - 1].gid_table_len =
4405 pprops->gid_tbl_len;
4406 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4407 port, dprops->max_pkeys, pprops->gid_tbl_len);
4408
4409 out:
4410 kfree(pprops);
4411 kfree(dprops);
4412
4413 return err;
4414 }
4415
4416 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4417 {
4418 int err;
4419
4420 err = mlx5_mr_cache_cleanup(dev);
4421 if (err)
4422 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4423
4424 if (dev->umrc.qp)
4425 mlx5_ib_destroy_qp(dev->umrc.qp);
4426 if (dev->umrc.cq)
4427 ib_free_cq(dev->umrc.cq);
4428 if (dev->umrc.pd)
4429 ib_dealloc_pd(dev->umrc.pd);
4430 }
4431
4432 enum {
4433 MAX_UMR_WR = 128,
4434 };
4435
4436 static int create_umr_res(struct mlx5_ib_dev *dev)
4437 {
4438 struct ib_qp_init_attr *init_attr = NULL;
4439 struct ib_qp_attr *attr = NULL;
4440 struct ib_pd *pd;
4441 struct ib_cq *cq;
4442 struct ib_qp *qp;
4443 int ret;
4444
4445 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4446 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4447 if (!attr || !init_attr) {
4448 ret = -ENOMEM;
4449 goto error_0;
4450 }
4451
4452 pd = ib_alloc_pd(&dev->ib_dev, 0);
4453 if (IS_ERR(pd)) {
4454 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4455 ret = PTR_ERR(pd);
4456 goto error_0;
4457 }
4458
4459 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4460 if (IS_ERR(cq)) {
4461 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4462 ret = PTR_ERR(cq);
4463 goto error_2;
4464 }
4465
4466 init_attr->send_cq = cq;
4467 init_attr->recv_cq = cq;
4468 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4469 init_attr->cap.max_send_wr = MAX_UMR_WR;
4470 init_attr->cap.max_send_sge = 1;
4471 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4472 init_attr->port_num = 1;
4473 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4474 if (IS_ERR(qp)) {
4475 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4476 ret = PTR_ERR(qp);
4477 goto error_3;
4478 }
4479 qp->device = &dev->ib_dev;
4480 qp->real_qp = qp;
4481 qp->uobject = NULL;
4482 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4483 qp->send_cq = init_attr->send_cq;
4484 qp->recv_cq = init_attr->recv_cq;
4485
4486 attr->qp_state = IB_QPS_INIT;
4487 attr->port_num = 1;
4488 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4489 IB_QP_PORT, NULL);
4490 if (ret) {
4491 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4492 goto error_4;
4493 }
4494
4495 memset(attr, 0, sizeof(*attr));
4496 attr->qp_state = IB_QPS_RTR;
4497 attr->path_mtu = IB_MTU_256;
4498
4499 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4500 if (ret) {
4501 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4502 goto error_4;
4503 }
4504
4505 memset(attr, 0, sizeof(*attr));
4506 attr->qp_state = IB_QPS_RTS;
4507 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4508 if (ret) {
4509 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4510 goto error_4;
4511 }
4512
4513 dev->umrc.qp = qp;
4514 dev->umrc.cq = cq;
4515 dev->umrc.pd = pd;
4516
4517 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4518 ret = mlx5_mr_cache_init(dev);
4519 if (ret) {
4520 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4521 goto error_4;
4522 }
4523
4524 kfree(attr);
4525 kfree(init_attr);
4526
4527 return 0;
4528
4529 error_4:
4530 mlx5_ib_destroy_qp(qp);
4531 dev->umrc.qp = NULL;
4532
4533 error_3:
4534 ib_free_cq(cq);
4535 dev->umrc.cq = NULL;
4536
4537 error_2:
4538 ib_dealloc_pd(pd);
4539 dev->umrc.pd = NULL;
4540
4541 error_0:
4542 kfree(attr);
4543 kfree(init_attr);
4544 return ret;
4545 }
4546
4547 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4548 {
4549 switch (umr_fence_cap) {
4550 case MLX5_CAP_UMR_FENCE_NONE:
4551 return MLX5_FENCE_MODE_NONE;
4552 case MLX5_CAP_UMR_FENCE_SMALL:
4553 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4554 default:
4555 return MLX5_FENCE_MODE_STRONG_ORDERING;
4556 }
4557 }
4558
4559 static int create_dev_resources(struct mlx5_ib_resources *devr)
4560 {
4561 struct ib_srq_init_attr attr;
4562 struct mlx5_ib_dev *dev;
4563 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4564 int port;
4565 int ret = 0;
4566
4567 dev = container_of(devr, struct mlx5_ib_dev, devr);
4568
4569 mutex_init(&devr->mutex);
4570
4571 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4572 if (IS_ERR(devr->p0)) {
4573 ret = PTR_ERR(devr->p0);
4574 goto error0;
4575 }
4576 devr->p0->device = &dev->ib_dev;
4577 devr->p0->uobject = NULL;
4578 atomic_set(&devr->p0->usecnt, 0);
4579
4580 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4581 if (IS_ERR(devr->c0)) {
4582 ret = PTR_ERR(devr->c0);
4583 goto error1;
4584 }
4585 devr->c0->device = &dev->ib_dev;
4586 devr->c0->uobject = NULL;
4587 devr->c0->comp_handler = NULL;
4588 devr->c0->event_handler = NULL;
4589 devr->c0->cq_context = NULL;
4590 atomic_set(&devr->c0->usecnt, 0);
4591
4592 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4593 if (IS_ERR(devr->x0)) {
4594 ret = PTR_ERR(devr->x0);
4595 goto error2;
4596 }
4597 devr->x0->device = &dev->ib_dev;
4598 devr->x0->inode = NULL;
4599 atomic_set(&devr->x0->usecnt, 0);
4600 mutex_init(&devr->x0->tgt_qp_mutex);
4601 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4602
4603 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4604 if (IS_ERR(devr->x1)) {
4605 ret = PTR_ERR(devr->x1);
4606 goto error3;
4607 }
4608 devr->x1->device = &dev->ib_dev;
4609 devr->x1->inode = NULL;
4610 atomic_set(&devr->x1->usecnt, 0);
4611 mutex_init(&devr->x1->tgt_qp_mutex);
4612 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4613
4614 memset(&attr, 0, sizeof(attr));
4615 attr.attr.max_sge = 1;
4616 attr.attr.max_wr = 1;
4617 attr.srq_type = IB_SRQT_XRC;
4618 attr.ext.cq = devr->c0;
4619 attr.ext.xrc.xrcd = devr->x0;
4620
4621 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4622 if (IS_ERR(devr->s0)) {
4623 ret = PTR_ERR(devr->s0);
4624 goto error4;
4625 }
4626 devr->s0->device = &dev->ib_dev;
4627 devr->s0->pd = devr->p0;
4628 devr->s0->uobject = NULL;
4629 devr->s0->event_handler = NULL;
4630 devr->s0->srq_context = NULL;
4631 devr->s0->srq_type = IB_SRQT_XRC;
4632 devr->s0->ext.xrc.xrcd = devr->x0;
4633 devr->s0->ext.cq = devr->c0;
4634 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4635 atomic_inc(&devr->s0->ext.cq->usecnt);
4636 atomic_inc(&devr->p0->usecnt);
4637 atomic_set(&devr->s0->usecnt, 0);
4638
4639 memset(&attr, 0, sizeof(attr));
4640 attr.attr.max_sge = 1;
4641 attr.attr.max_wr = 1;
4642 attr.srq_type = IB_SRQT_BASIC;
4643 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4644 if (IS_ERR(devr->s1)) {
4645 ret = PTR_ERR(devr->s1);
4646 goto error5;
4647 }
4648 devr->s1->device = &dev->ib_dev;
4649 devr->s1->pd = devr->p0;
4650 devr->s1->uobject = NULL;
4651 devr->s1->event_handler = NULL;
4652 devr->s1->srq_context = NULL;
4653 devr->s1->srq_type = IB_SRQT_BASIC;
4654 devr->s1->ext.cq = devr->c0;
4655 atomic_inc(&devr->p0->usecnt);
4656 atomic_set(&devr->s1->usecnt, 0);
4657
4658 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4659 INIT_WORK(&devr->ports[port].pkey_change_work,
4660 pkey_change_handler);
4661 devr->ports[port].devr = devr;
4662 }
4663
4664 return 0;
4665
4666 error5:
4667 mlx5_ib_destroy_srq(devr->s0);
4668 error4:
4669 mlx5_ib_dealloc_xrcd(devr->x1);
4670 error3:
4671 mlx5_ib_dealloc_xrcd(devr->x0);
4672 error2:
4673 mlx5_ib_destroy_cq(devr->c0);
4674 error1:
4675 mlx5_ib_dealloc_pd(devr->p0);
4676 error0:
4677 return ret;
4678 }
4679
4680 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4681 {
4682 struct mlx5_ib_dev *dev =
4683 container_of(devr, struct mlx5_ib_dev, devr);
4684 int port;
4685
4686 mlx5_ib_destroy_srq(devr->s1);
4687 mlx5_ib_destroy_srq(devr->s0);
4688 mlx5_ib_dealloc_xrcd(devr->x0);
4689 mlx5_ib_dealloc_xrcd(devr->x1);
4690 mlx5_ib_destroy_cq(devr->c0);
4691 mlx5_ib_dealloc_pd(devr->p0);
4692
4693 /* Make sure no change P_Key work items are still executing */
4694 for (port = 0; port < dev->num_ports; ++port)
4695 cancel_work_sync(&devr->ports[port].pkey_change_work);
4696 }
4697
4698 static u32 get_core_cap_flags(struct ib_device *ibdev,
4699 struct mlx5_hca_vport_context *rep)
4700 {
4701 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4702 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4703 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4704 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4705 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4706 u32 ret = 0;
4707
4708 if (rep->grh_required)
4709 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4710
4711 if (ll == IB_LINK_LAYER_INFINIBAND)
4712 return ret | RDMA_CORE_PORT_IBA_IB;
4713
4714 if (raw_support)
4715 ret |= RDMA_CORE_PORT_RAW_PACKET;
4716
4717 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4718 return ret;
4719
4720 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4721 return ret;
4722
4723 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4724 ret |= RDMA_CORE_PORT_IBA_ROCE;
4725
4726 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4727 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4728
4729 return ret;
4730 }
4731
4732 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4733 struct ib_port_immutable *immutable)
4734 {
4735 struct ib_port_attr attr;
4736 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4737 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4738 struct mlx5_hca_vport_context rep = {0};
4739 int err;
4740
4741 err = ib_query_port(ibdev, port_num, &attr);
4742 if (err)
4743 return err;
4744
4745 if (ll == IB_LINK_LAYER_INFINIBAND) {
4746 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4747 &rep);
4748 if (err)
4749 return err;
4750 }
4751
4752 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4753 immutable->gid_tbl_len = attr.gid_tbl_len;
4754 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4755 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4756 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4757
4758 return 0;
4759 }
4760
4761 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4762 struct ib_port_immutable *immutable)
4763 {
4764 struct ib_port_attr attr;
4765 int err;
4766
4767 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4768
4769 err = ib_query_port(ibdev, port_num, &attr);
4770 if (err)
4771 return err;
4772
4773 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4774 immutable->gid_tbl_len = attr.gid_tbl_len;
4775 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4776
4777 return 0;
4778 }
4779
4780 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4781 {
4782 struct mlx5_ib_dev *dev =
4783 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4784 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4785 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4786 fw_rev_sub(dev->mdev));
4787 }
4788
4789 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4790 {
4791 struct mlx5_core_dev *mdev = dev->mdev;
4792 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4793 MLX5_FLOW_NAMESPACE_LAG);
4794 struct mlx5_flow_table *ft;
4795 int err;
4796
4797 if (!ns || !mlx5_lag_is_active(mdev))
4798 return 0;
4799
4800 err = mlx5_cmd_create_vport_lag(mdev);
4801 if (err)
4802 return err;
4803
4804 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4805 if (IS_ERR(ft)) {
4806 err = PTR_ERR(ft);
4807 goto err_destroy_vport_lag;
4808 }
4809
4810 dev->flow_db->lag_demux_ft = ft;
4811 return 0;
4812
4813 err_destroy_vport_lag:
4814 mlx5_cmd_destroy_vport_lag(mdev);
4815 return err;
4816 }
4817
4818 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4819 {
4820 struct mlx5_core_dev *mdev = dev->mdev;
4821
4822 if (dev->flow_db->lag_demux_ft) {
4823 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4824 dev->flow_db->lag_demux_ft = NULL;
4825
4826 mlx5_cmd_destroy_vport_lag(mdev);
4827 }
4828 }
4829
4830 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4831 {
4832 int err;
4833
4834 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4835 err = register_netdevice_notifier(&dev->roce[port_num].nb);
4836 if (err) {
4837 dev->roce[port_num].nb.notifier_call = NULL;
4838 return err;
4839 }
4840
4841 return 0;
4842 }
4843
4844 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4845 {
4846 if (dev->roce[port_num].nb.notifier_call) {
4847 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4848 dev->roce[port_num].nb.notifier_call = NULL;
4849 }
4850 }
4851
4852 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4853 {
4854 int err;
4855
4856 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4857 err = mlx5_nic_vport_enable_roce(dev->mdev);
4858 if (err)
4859 return err;
4860 }
4861
4862 err = mlx5_eth_lag_init(dev);
4863 if (err)
4864 goto err_disable_roce;
4865
4866 return 0;
4867
4868 err_disable_roce:
4869 if (MLX5_CAP_GEN(dev->mdev, roce))
4870 mlx5_nic_vport_disable_roce(dev->mdev);
4871
4872 return err;
4873 }
4874
4875 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4876 {
4877 mlx5_eth_lag_cleanup(dev);
4878 if (MLX5_CAP_GEN(dev->mdev, roce))
4879 mlx5_nic_vport_disable_roce(dev->mdev);
4880 }
4881
4882 struct mlx5_ib_counter {
4883 const char *name;
4884 size_t offset;
4885 };
4886
4887 #define INIT_Q_COUNTER(_name) \
4888 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4889
4890 static const struct mlx5_ib_counter basic_q_cnts[] = {
4891 INIT_Q_COUNTER(rx_write_requests),
4892 INIT_Q_COUNTER(rx_read_requests),
4893 INIT_Q_COUNTER(rx_atomic_requests),
4894 INIT_Q_COUNTER(out_of_buffer),
4895 };
4896
4897 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4898 INIT_Q_COUNTER(out_of_sequence),
4899 };
4900
4901 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4902 INIT_Q_COUNTER(duplicate_request),
4903 INIT_Q_COUNTER(rnr_nak_retry_err),
4904 INIT_Q_COUNTER(packet_seq_err),
4905 INIT_Q_COUNTER(implied_nak_seq_err),
4906 INIT_Q_COUNTER(local_ack_timeout_err),
4907 };
4908
4909 #define INIT_CONG_COUNTER(_name) \
4910 { .name = #_name, .offset = \
4911 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4912
4913 static const struct mlx5_ib_counter cong_cnts[] = {
4914 INIT_CONG_COUNTER(rp_cnp_ignored),
4915 INIT_CONG_COUNTER(rp_cnp_handled),
4916 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4917 INIT_CONG_COUNTER(np_cnp_sent),
4918 };
4919
4920 static const struct mlx5_ib_counter extended_err_cnts[] = {
4921 INIT_Q_COUNTER(resp_local_length_error),
4922 INIT_Q_COUNTER(resp_cqe_error),
4923 INIT_Q_COUNTER(req_cqe_error),
4924 INIT_Q_COUNTER(req_remote_invalid_request),
4925 INIT_Q_COUNTER(req_remote_access_errors),
4926 INIT_Q_COUNTER(resp_remote_access_errors),
4927 INIT_Q_COUNTER(resp_cqe_flush_error),
4928 INIT_Q_COUNTER(req_cqe_flush_error),
4929 };
4930
4931 #define INIT_EXT_PPCNT_COUNTER(_name) \
4932 { .name = #_name, .offset = \
4933 MLX5_BYTE_OFF(ppcnt_reg, \
4934 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4935
4936 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4937 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4938 };
4939
4940 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4941 {
4942 int i;
4943
4944 for (i = 0; i < dev->num_ports; i++) {
4945 if (dev->port[i].cnts.set_id_valid)
4946 mlx5_core_dealloc_q_counter(dev->mdev,
4947 dev->port[i].cnts.set_id);
4948 kfree(dev->port[i].cnts.names);
4949 kfree(dev->port[i].cnts.offsets);
4950 }
4951 }
4952
4953 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4954 struct mlx5_ib_counters *cnts)
4955 {
4956 u32 num_counters;
4957
4958 num_counters = ARRAY_SIZE(basic_q_cnts);
4959
4960 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4961 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4962
4963 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4964 num_counters += ARRAY_SIZE(retrans_q_cnts);
4965
4966 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4967 num_counters += ARRAY_SIZE(extended_err_cnts);
4968
4969 cnts->num_q_counters = num_counters;
4970
4971 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4972 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4973 num_counters += ARRAY_SIZE(cong_cnts);
4974 }
4975 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4976 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4977 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4978 }
4979 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4980 if (!cnts->names)
4981 return -ENOMEM;
4982
4983 cnts->offsets = kcalloc(num_counters,
4984 sizeof(cnts->offsets), GFP_KERNEL);
4985 if (!cnts->offsets)
4986 goto err_names;
4987
4988 return 0;
4989
4990 err_names:
4991 kfree(cnts->names);
4992 cnts->names = NULL;
4993 return -ENOMEM;
4994 }
4995
4996 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4997 const char **names,
4998 size_t *offsets)
4999 {
5000 int i;
5001 int j = 0;
5002
5003 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
5004 names[j] = basic_q_cnts[i].name;
5005 offsets[j] = basic_q_cnts[i].offset;
5006 }
5007
5008 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5009 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5010 names[j] = out_of_seq_q_cnts[i].name;
5011 offsets[j] = out_of_seq_q_cnts[i].offset;
5012 }
5013 }
5014
5015 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5016 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5017 names[j] = retrans_q_cnts[i].name;
5018 offsets[j] = retrans_q_cnts[i].offset;
5019 }
5020 }
5021
5022 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5023 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5024 names[j] = extended_err_cnts[i].name;
5025 offsets[j] = extended_err_cnts[i].offset;
5026 }
5027 }
5028
5029 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5030 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5031 names[j] = cong_cnts[i].name;
5032 offsets[j] = cong_cnts[i].offset;
5033 }
5034 }
5035
5036 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5037 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5038 names[j] = ext_ppcnt_cnts[i].name;
5039 offsets[j] = ext_ppcnt_cnts[i].offset;
5040 }
5041 }
5042 }
5043
5044 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5045 {
5046 int err = 0;
5047 int i;
5048
5049 for (i = 0; i < dev->num_ports; i++) {
5050 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5051 if (err)
5052 goto err_alloc;
5053
5054 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5055 dev->port[i].cnts.offsets);
5056
5057 err = mlx5_core_alloc_q_counter(dev->mdev,
5058 &dev->port[i].cnts.set_id);
5059 if (err) {
5060 mlx5_ib_warn(dev,
5061 "couldn't allocate queue counter for port %d, err %d\n",
5062 i + 1, err);
5063 goto err_alloc;
5064 }
5065 dev->port[i].cnts.set_id_valid = true;
5066 }
5067
5068 return 0;
5069
5070 err_alloc:
5071 mlx5_ib_dealloc_counters(dev);
5072 return err;
5073 }
5074
5075 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5076 u8 port_num)
5077 {
5078 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5079 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5080
5081 /* We support only per port stats */
5082 if (port_num == 0)
5083 return NULL;
5084
5085 return rdma_alloc_hw_stats_struct(port->cnts.names,
5086 port->cnts.num_q_counters +
5087 port->cnts.num_cong_counters +
5088 port->cnts.num_ext_ppcnt_counters,
5089 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5090 }
5091
5092 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5093 struct mlx5_ib_port *port,
5094 struct rdma_hw_stats *stats)
5095 {
5096 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5097 void *out;
5098 __be32 val;
5099 int ret, i;
5100
5101 out = kvzalloc(outlen, GFP_KERNEL);
5102 if (!out)
5103 return -ENOMEM;
5104
5105 ret = mlx5_core_query_q_counter(mdev,
5106 port->cnts.set_id, 0,
5107 out, outlen);
5108 if (ret)
5109 goto free;
5110
5111 for (i = 0; i < port->cnts.num_q_counters; i++) {
5112 val = *(__be32 *)(out + port->cnts.offsets[i]);
5113 stats->value[i] = (u64)be32_to_cpu(val);
5114 }
5115
5116 free:
5117 kvfree(out);
5118 return ret;
5119 }
5120
5121 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5122 struct mlx5_ib_port *port,
5123 struct rdma_hw_stats *stats)
5124 {
5125 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5126 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5127 int ret, i;
5128 void *out;
5129
5130 out = kvzalloc(sz, GFP_KERNEL);
5131 if (!out)
5132 return -ENOMEM;
5133
5134 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5135 if (ret)
5136 goto free;
5137
5138 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5139 stats->value[i + offset] =
5140 be64_to_cpup((__be64 *)(out +
5141 port->cnts.offsets[i + offset]));
5142 }
5143
5144 free:
5145 kvfree(out);
5146 return ret;
5147 }
5148
5149 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5150 struct rdma_hw_stats *stats,
5151 u8 port_num, int index)
5152 {
5153 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5154 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5155 struct mlx5_core_dev *mdev;
5156 int ret, num_counters;
5157 u8 mdev_port_num;
5158
5159 if (!stats)
5160 return -EINVAL;
5161
5162 num_counters = port->cnts.num_q_counters +
5163 port->cnts.num_cong_counters +
5164 port->cnts.num_ext_ppcnt_counters;
5165
5166 /* q_counters are per IB device, query the master mdev */
5167 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5168 if (ret)
5169 return ret;
5170
5171 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5172 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5173 if (ret)
5174 return ret;
5175 }
5176
5177 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5178 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5179 &mdev_port_num);
5180 if (!mdev) {
5181 /* If port is not affiliated yet, its in down state
5182 * which doesn't have any counters yet, so it would be
5183 * zero. So no need to read from the HCA.
5184 */
5185 goto done;
5186 }
5187 ret = mlx5_lag_query_cong_counters(dev->mdev,
5188 stats->value +
5189 port->cnts.num_q_counters,
5190 port->cnts.num_cong_counters,
5191 port->cnts.offsets +
5192 port->cnts.num_q_counters);
5193
5194 mlx5_ib_put_native_port_mdev(dev, port_num);
5195 if (ret)
5196 return ret;
5197 }
5198
5199 done:
5200 return num_counters;
5201 }
5202
5203 static struct net_device*
5204 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5205 u8 port_num,
5206 enum rdma_netdev_t type,
5207 const char *name,
5208 unsigned char name_assign_type,
5209 void (*setup)(struct net_device *))
5210 {
5211 struct net_device *netdev;
5212
5213 if (type != RDMA_NETDEV_IPOIB)
5214 return ERR_PTR(-EOPNOTSUPP);
5215
5216 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5217 name, setup);
5218 return netdev;
5219 }
5220
5221 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5222 {
5223 if (!dev->delay_drop.dbg)
5224 return;
5225 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5226 kfree(dev->delay_drop.dbg);
5227 dev->delay_drop.dbg = NULL;
5228 }
5229
5230 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5231 {
5232 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5233 return;
5234
5235 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5236 delay_drop_debugfs_cleanup(dev);
5237 }
5238
5239 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5240 size_t count, loff_t *pos)
5241 {
5242 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5243 char lbuf[20];
5244 int len;
5245
5246 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5247 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5248 }
5249
5250 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5251 size_t count, loff_t *pos)
5252 {
5253 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5254 u32 timeout;
5255 u32 var;
5256
5257 if (kstrtouint_from_user(buf, count, 0, &var))
5258 return -EFAULT;
5259
5260 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5261 1000);
5262 if (timeout != var)
5263 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5264 timeout);
5265
5266 delay_drop->timeout = timeout;
5267
5268 return count;
5269 }
5270
5271 static const struct file_operations fops_delay_drop_timeout = {
5272 .owner = THIS_MODULE,
5273 .open = simple_open,
5274 .write = delay_drop_timeout_write,
5275 .read = delay_drop_timeout_read,
5276 };
5277
5278 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5279 {
5280 struct mlx5_ib_dbg_delay_drop *dbg;
5281
5282 if (!mlx5_debugfs_root)
5283 return 0;
5284
5285 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5286 if (!dbg)
5287 return -ENOMEM;
5288
5289 dev->delay_drop.dbg = dbg;
5290
5291 dbg->dir_debugfs =
5292 debugfs_create_dir("delay_drop",
5293 dev->mdev->priv.dbg_root);
5294 if (!dbg->dir_debugfs)
5295 goto out_debugfs;
5296
5297 dbg->events_cnt_debugfs =
5298 debugfs_create_atomic_t("num_timeout_events", 0400,
5299 dbg->dir_debugfs,
5300 &dev->delay_drop.events_cnt);
5301 if (!dbg->events_cnt_debugfs)
5302 goto out_debugfs;
5303
5304 dbg->rqs_cnt_debugfs =
5305 debugfs_create_atomic_t("num_rqs", 0400,
5306 dbg->dir_debugfs,
5307 &dev->delay_drop.rqs_cnt);
5308 if (!dbg->rqs_cnt_debugfs)
5309 goto out_debugfs;
5310
5311 dbg->timeout_debugfs =
5312 debugfs_create_file("timeout", 0600,
5313 dbg->dir_debugfs,
5314 &dev->delay_drop,
5315 &fops_delay_drop_timeout);
5316 if (!dbg->timeout_debugfs)
5317 goto out_debugfs;
5318
5319 return 0;
5320
5321 out_debugfs:
5322 delay_drop_debugfs_cleanup(dev);
5323 return -ENOMEM;
5324 }
5325
5326 static void init_delay_drop(struct mlx5_ib_dev *dev)
5327 {
5328 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5329 return;
5330
5331 mutex_init(&dev->delay_drop.lock);
5332 dev->delay_drop.dev = dev;
5333 dev->delay_drop.activate = false;
5334 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5335 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5336 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5337 atomic_set(&dev->delay_drop.events_cnt, 0);
5338
5339 if (delay_drop_debugfs_init(dev))
5340 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5341 }
5342
5343 static const struct cpumask *
5344 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5345 {
5346 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5347
5348 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5349 }
5350
5351 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5352 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5353 struct mlx5_ib_multiport_info *mpi)
5354 {
5355 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5356 struct mlx5_ib_port *port = &ibdev->port[port_num];
5357 int comps;
5358 int err;
5359 int i;
5360
5361 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5362
5363 spin_lock(&port->mp.mpi_lock);
5364 if (!mpi->ibdev) {
5365 spin_unlock(&port->mp.mpi_lock);
5366 return;
5367 }
5368 mpi->ibdev = NULL;
5369
5370 spin_unlock(&port->mp.mpi_lock);
5371 mlx5_remove_netdev_notifier(ibdev, port_num);
5372 spin_lock(&port->mp.mpi_lock);
5373
5374 comps = mpi->mdev_refcnt;
5375 if (comps) {
5376 mpi->unaffiliate = true;
5377 init_completion(&mpi->unref_comp);
5378 spin_unlock(&port->mp.mpi_lock);
5379
5380 for (i = 0; i < comps; i++)
5381 wait_for_completion(&mpi->unref_comp);
5382
5383 spin_lock(&port->mp.mpi_lock);
5384 mpi->unaffiliate = false;
5385 }
5386
5387 port->mp.mpi = NULL;
5388
5389 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5390
5391 spin_unlock(&port->mp.mpi_lock);
5392
5393 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5394
5395 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5396 /* Log an error, still needed to cleanup the pointers and add
5397 * it back to the list.
5398 */
5399 if (err)
5400 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5401 port_num + 1);
5402
5403 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5404 }
5405
5406 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5407 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5408 struct mlx5_ib_multiport_info *mpi)
5409 {
5410 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5411 int err;
5412
5413 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5414 if (ibdev->port[port_num].mp.mpi) {
5415 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5416 port_num + 1);
5417 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5418 return false;
5419 }
5420
5421 ibdev->port[port_num].mp.mpi = mpi;
5422 mpi->ibdev = ibdev;
5423 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5424
5425 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5426 if (err)
5427 goto unbind;
5428
5429 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5430 if (err)
5431 goto unbind;
5432
5433 err = mlx5_add_netdev_notifier(ibdev, port_num);
5434 if (err) {
5435 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5436 port_num + 1);
5437 goto unbind;
5438 }
5439
5440 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5441 if (err)
5442 goto unbind;
5443
5444 return true;
5445
5446 unbind:
5447 mlx5_ib_unbind_slave_port(ibdev, mpi);
5448 return false;
5449 }
5450
5451 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5452 {
5453 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5454 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5455 port_num + 1);
5456 struct mlx5_ib_multiport_info *mpi;
5457 int err;
5458 int i;
5459
5460 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5461 return 0;
5462
5463 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5464 &dev->sys_image_guid);
5465 if (err)
5466 return err;
5467
5468 err = mlx5_nic_vport_enable_roce(dev->mdev);
5469 if (err)
5470 return err;
5471
5472 mutex_lock(&mlx5_ib_multiport_mutex);
5473 for (i = 0; i < dev->num_ports; i++) {
5474 bool bound = false;
5475
5476 /* build a stub multiport info struct for the native port. */
5477 if (i == port_num) {
5478 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5479 if (!mpi) {
5480 mutex_unlock(&mlx5_ib_multiport_mutex);
5481 mlx5_nic_vport_disable_roce(dev->mdev);
5482 return -ENOMEM;
5483 }
5484
5485 mpi->is_master = true;
5486 mpi->mdev = dev->mdev;
5487 mpi->sys_image_guid = dev->sys_image_guid;
5488 dev->port[i].mp.mpi = mpi;
5489 mpi->ibdev = dev;
5490 mpi = NULL;
5491 continue;
5492 }
5493
5494 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5495 list) {
5496 if (dev->sys_image_guid == mpi->sys_image_guid &&
5497 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5498 bound = mlx5_ib_bind_slave_port(dev, mpi);
5499 }
5500
5501 if (bound) {
5502 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5503 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5504 list_del(&mpi->list);
5505 break;
5506 }
5507 }
5508 if (!bound) {
5509 get_port_caps(dev, i + 1);
5510 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5511 i + 1);
5512 }
5513 }
5514
5515 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5516 mutex_unlock(&mlx5_ib_multiport_mutex);
5517 return err;
5518 }
5519
5520 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5521 {
5522 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5523 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5524 port_num + 1);
5525 int i;
5526
5527 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5528 return;
5529
5530 mutex_lock(&mlx5_ib_multiport_mutex);
5531 for (i = 0; i < dev->num_ports; i++) {
5532 if (dev->port[i].mp.mpi) {
5533 /* Destroy the native port stub */
5534 if (i == port_num) {
5535 kfree(dev->port[i].mp.mpi);
5536 dev->port[i].mp.mpi = NULL;
5537 } else {
5538 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5539 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5540 }
5541 }
5542 }
5543
5544 mlx5_ib_dbg(dev, "removing from devlist\n");
5545 list_del(&dev->ib_dev_list);
5546 mutex_unlock(&mlx5_ib_multiport_mutex);
5547
5548 mlx5_nic_vport_disable_roce(dev->mdev);
5549 }
5550
5551 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5552 mlx5_ib_dm,
5553 UVERBS_OBJECT_DM,
5554 UVERBS_METHOD_DM_ALLOC,
5555 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5556 UVERBS_ATTR_TYPE(u64),
5557 UA_MANDATORY),
5558 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5559 UVERBS_ATTR_TYPE(u16),
5560 UA_MANDATORY));
5561
5562 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5563 mlx5_ib_flow_action,
5564 UVERBS_OBJECT_FLOW_ACTION,
5565 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5566 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5567 enum mlx5_ib_uapi_flow_action_flags));
5568
5569 static int populate_specs_root(struct mlx5_ib_dev *dev)
5570 {
5571 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5572 size_t num_trees = 0;
5573
5574 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5575 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5576 trees[num_trees++] = &mlx5_ib_flow_action;
5577
5578 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5579 trees[num_trees++] = &mlx5_ib_dm;
5580
5581 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5582 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5583 trees[num_trees++] = mlx5_ib_get_devx_tree();
5584
5585 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5586
5587 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5588 trees[num_trees] = NULL;
5589 dev->ib_dev.driver_specs = trees;
5590
5591 return 0;
5592 }
5593
5594 static int mlx5_ib_read_counters(struct ib_counters *counters,
5595 struct ib_counters_read_attr *read_attr,
5596 struct uverbs_attr_bundle *attrs)
5597 {
5598 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5599 struct mlx5_read_counters_attr mread_attr = {};
5600 struct mlx5_ib_flow_counters_desc *desc;
5601 int ret, i;
5602
5603 mutex_lock(&mcounters->mcntrs_mutex);
5604 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5605 ret = -EINVAL;
5606 goto err_bound;
5607 }
5608
5609 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5610 GFP_KERNEL);
5611 if (!mread_attr.out) {
5612 ret = -ENOMEM;
5613 goto err_bound;
5614 }
5615
5616 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5617 mread_attr.flags = read_attr->flags;
5618 ret = mcounters->read_counters(counters->device, &mread_attr);
5619 if (ret)
5620 goto err_read;
5621
5622 /* do the pass over the counters data array to assign according to the
5623 * descriptions and indexing pairs
5624 */
5625 desc = mcounters->counters_data;
5626 for (i = 0; i < mcounters->ncounters; i++)
5627 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5628
5629 err_read:
5630 kfree(mread_attr.out);
5631 err_bound:
5632 mutex_unlock(&mcounters->mcntrs_mutex);
5633 return ret;
5634 }
5635
5636 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5637 {
5638 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5639
5640 counters_clear_description(counters);
5641 if (mcounters->hw_cntrs_hndl)
5642 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5643 mcounters->hw_cntrs_hndl);
5644
5645 kfree(mcounters);
5646
5647 return 0;
5648 }
5649
5650 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5651 struct uverbs_attr_bundle *attrs)
5652 {
5653 struct mlx5_ib_mcounters *mcounters;
5654
5655 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5656 if (!mcounters)
5657 return ERR_PTR(-ENOMEM);
5658
5659 mutex_init(&mcounters->mcntrs_mutex);
5660
5661 return &mcounters->ibcntrs;
5662 }
5663
5664 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5665 {
5666 mlx5_ib_cleanup_multiport_master(dev);
5667 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5668 cleanup_srcu_struct(&dev->mr_srcu);
5669 #endif
5670 kfree(dev->port);
5671 }
5672
5673 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5674 {
5675 struct mlx5_core_dev *mdev = dev->mdev;
5676 const char *name;
5677 int err;
5678 int i;
5679
5680 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5681 GFP_KERNEL);
5682 if (!dev->port)
5683 return -ENOMEM;
5684
5685 for (i = 0; i < dev->num_ports; i++) {
5686 spin_lock_init(&dev->port[i].mp.mpi_lock);
5687 rwlock_init(&dev->roce[i].netdev_lock);
5688 }
5689
5690 err = mlx5_ib_init_multiport_master(dev);
5691 if (err)
5692 goto err_free_port;
5693
5694 if (!mlx5_core_mp_enabled(mdev)) {
5695 for (i = 1; i <= dev->num_ports; i++) {
5696 err = get_port_caps(dev, i);
5697 if (err)
5698 break;
5699 }
5700 } else {
5701 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5702 }
5703 if (err)
5704 goto err_mp;
5705
5706 if (mlx5_use_mad_ifc(dev))
5707 get_ext_port_caps(dev);
5708
5709 if (!mlx5_lag_is_active(mdev))
5710 name = "mlx5_%d";
5711 else
5712 name = "mlx5_bond_%d";
5713
5714 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5715 dev->ib_dev.owner = THIS_MODULE;
5716 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
5717 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
5718 dev->ib_dev.phys_port_cnt = dev->num_ports;
5719 dev->ib_dev.num_comp_vectors =
5720 dev->mdev->priv.eq_table.num_comp_vectors;
5721 dev->ib_dev.dev.parent = &mdev->pdev->dev;
5722
5723 mutex_init(&dev->cap_mask_mutex);
5724 INIT_LIST_HEAD(&dev->qp_list);
5725 spin_lock_init(&dev->reset_flow_resource_lock);
5726
5727 spin_lock_init(&dev->memic.memic_lock);
5728 dev->memic.dev = mdev;
5729
5730 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5731 err = init_srcu_struct(&dev->mr_srcu);
5732 if (err)
5733 goto err_free_port;
5734 #endif
5735
5736 return 0;
5737 err_mp:
5738 mlx5_ib_cleanup_multiport_master(dev);
5739
5740 err_free_port:
5741 kfree(dev->port);
5742
5743 return -ENOMEM;
5744 }
5745
5746 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5747 {
5748 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5749
5750 if (!dev->flow_db)
5751 return -ENOMEM;
5752
5753 mutex_init(&dev->flow_db->lock);
5754
5755 return 0;
5756 }
5757
5758 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5759 {
5760 struct mlx5_ib_dev *nic_dev;
5761
5762 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5763
5764 if (!nic_dev)
5765 return -EINVAL;
5766
5767 dev->flow_db = nic_dev->flow_db;
5768
5769 return 0;
5770 }
5771
5772 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5773 {
5774 kfree(dev->flow_db);
5775 }
5776
5777 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5778 {
5779 struct mlx5_core_dev *mdev = dev->mdev;
5780 int err;
5781
5782 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5783 dev->ib_dev.uverbs_cmd_mask =
5784 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5785 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5786 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5787 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5788 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
5789 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5790 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
5791 (1ull << IB_USER_VERBS_CMD_REG_MR) |
5792 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
5793 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5794 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5795 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5796 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5797 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5798 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5799 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5800 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5801 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5802 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5803 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5804 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5805 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5806 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5807 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5808 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5809 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5810 dev->ib_dev.uverbs_ex_cmd_mask =
5811 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5812 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
5813 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
5814 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5815 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5816
5817 dev->ib_dev.query_device = mlx5_ib_query_device;
5818 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
5819 dev->ib_dev.query_gid = mlx5_ib_query_gid;
5820 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5821 dev->ib_dev.del_gid = mlx5_ib_del_gid;
5822 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5823 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5824 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5825 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5826 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5827 dev->ib_dev.mmap = mlx5_ib_mmap;
5828 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5829 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5830 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5831 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5832 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5833 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5834 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5835 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5836 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5837 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5838 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5839 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5840 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5841 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5842 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5843 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
5844 dev->ib_dev.post_send = mlx5_ib_post_send;
5845 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5846 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5847 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5848 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5849 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5850 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5851 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5852 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5853 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
5854 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
5855 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5856 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5857 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5858 dev->ib_dev.process_mad = mlx5_ib_process_mad;
5859 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
5860 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
5861 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
5862 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
5863 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5864 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5865 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
5866
5867 if (mlx5_core_is_pf(mdev)) {
5868 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5869 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5870 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5871 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5872 }
5873
5874 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5875
5876 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5877
5878 if (MLX5_CAP_GEN(mdev, imaicl)) {
5879 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5880 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5881 dev->ib_dev.uverbs_cmd_mask |=
5882 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5883 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5884 }
5885
5886 if (MLX5_CAP_GEN(mdev, xrc)) {
5887 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5888 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5889 dev->ib_dev.uverbs_cmd_mask |=
5890 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5891 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5892 }
5893
5894 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5895 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5896 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5897 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5898 }
5899
5900 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5901 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5902 dev->ib_dev.uverbs_ex_cmd_mask |=
5903 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5904 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5905 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5906 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5907 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5908 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5909 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5910 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5911 dev->ib_dev.read_counters = mlx5_ib_read_counters;
5912
5913 err = init_node_data(dev);
5914 if (err)
5915 return err;
5916
5917 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5918 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5919 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5920 mutex_init(&dev->lb_mutex);
5921
5922 return 0;
5923 }
5924
5925 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5926 {
5927 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5928 dev->ib_dev.query_port = mlx5_ib_query_port;
5929
5930 return 0;
5931 }
5932
5933 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5934 {
5935 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5936 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5937
5938 return 0;
5939 }
5940
5941 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5942 {
5943 u8 port_num;
5944 int i;
5945
5946 for (i = 0; i < dev->num_ports; i++) {
5947 dev->roce[i].dev = dev;
5948 dev->roce[i].native_port_num = i + 1;
5949 dev->roce[i].last_port_state = IB_PORT_DOWN;
5950 }
5951
5952 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5953 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5954 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5955 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5956 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5957 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5958
5959 dev->ib_dev.uverbs_ex_cmd_mask |=
5960 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5961 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5962 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5963 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5964 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5965
5966 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5967
5968 return mlx5_add_netdev_notifier(dev, port_num);
5969 }
5970
5971 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5972 {
5973 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5974
5975 mlx5_remove_netdev_notifier(dev, port_num);
5976 }
5977
5978 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5979 {
5980 struct mlx5_core_dev *mdev = dev->mdev;
5981 enum rdma_link_layer ll;
5982 int port_type_cap;
5983 int err = 0;
5984
5985 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5986 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5987
5988 if (ll == IB_LINK_LAYER_ETHERNET)
5989 err = mlx5_ib_stage_common_roce_init(dev);
5990
5991 return err;
5992 }
5993
5994 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5995 {
5996 mlx5_ib_stage_common_roce_cleanup(dev);
5997 }
5998
5999 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
6000 {
6001 struct mlx5_core_dev *mdev = dev->mdev;
6002 enum rdma_link_layer ll;
6003 int port_type_cap;
6004 int err;
6005
6006 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6007 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6008
6009 if (ll == IB_LINK_LAYER_ETHERNET) {
6010 err = mlx5_ib_stage_common_roce_init(dev);
6011 if (err)
6012 return err;
6013
6014 err = mlx5_enable_eth(dev);
6015 if (err)
6016 goto cleanup;
6017 }
6018
6019 return 0;
6020 cleanup:
6021 mlx5_ib_stage_common_roce_cleanup(dev);
6022
6023 return err;
6024 }
6025
6026 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6027 {
6028 struct mlx5_core_dev *mdev = dev->mdev;
6029 enum rdma_link_layer ll;
6030 int port_type_cap;
6031
6032 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6033 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6034
6035 if (ll == IB_LINK_LAYER_ETHERNET) {
6036 mlx5_disable_eth(dev);
6037 mlx5_ib_stage_common_roce_cleanup(dev);
6038 }
6039 }
6040
6041 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6042 {
6043 return create_dev_resources(&dev->devr);
6044 }
6045
6046 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6047 {
6048 destroy_dev_resources(&dev->devr);
6049 }
6050
6051 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6052 {
6053 mlx5_ib_internal_fill_odp_caps(dev);
6054
6055 return mlx5_ib_odp_init_one(dev);
6056 }
6057
6058 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6059 {
6060 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6061 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6062 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6063
6064 return mlx5_ib_alloc_counters(dev);
6065 }
6066
6067 return 0;
6068 }
6069
6070 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6071 {
6072 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6073 mlx5_ib_dealloc_counters(dev);
6074 }
6075
6076 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6077 {
6078 return mlx5_ib_init_cong_debugfs(dev,
6079 mlx5_core_native_port_num(dev->mdev) - 1);
6080 }
6081
6082 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6083 {
6084 mlx5_ib_cleanup_cong_debugfs(dev,
6085 mlx5_core_native_port_num(dev->mdev) - 1);
6086 }
6087
6088 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6089 {
6090 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6091 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6092 }
6093
6094 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6095 {
6096 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6097 }
6098
6099 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6100 {
6101 int err;
6102
6103 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6104 if (err)
6105 return err;
6106
6107 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6108 if (err)
6109 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6110
6111 return err;
6112 }
6113
6114 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6115 {
6116 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6117 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6118 }
6119
6120 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6121 {
6122 return populate_specs_root(dev);
6123 }
6124
6125 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6126 {
6127 return ib_register_device(&dev->ib_dev, NULL);
6128 }
6129
6130 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6131 {
6132 destroy_umrc_res(dev);
6133 }
6134
6135 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6136 {
6137 ib_unregister_device(&dev->ib_dev);
6138 }
6139
6140 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6141 {
6142 return create_umr_res(dev);
6143 }
6144
6145 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6146 {
6147 init_delay_drop(dev);
6148
6149 return 0;
6150 }
6151
6152 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6153 {
6154 cancel_delay_drop(dev);
6155 }
6156
6157 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
6158 {
6159 int err;
6160 int i;
6161
6162 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
6163 err = device_create_file(&dev->ib_dev.dev,
6164 mlx5_class_attributes[i]);
6165 if (err)
6166 return err;
6167 }
6168
6169 return 0;
6170 }
6171
6172 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6173 {
6174 mlx5_ib_register_vport_reps(dev);
6175
6176 return 0;
6177 }
6178
6179 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6180 {
6181 mlx5_ib_unregister_vport_reps(dev);
6182 }
6183
6184 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6185 const struct mlx5_ib_profile *profile,
6186 int stage)
6187 {
6188 /* Number of stages to cleanup */
6189 while (stage) {
6190 stage--;
6191 if (profile->stage[stage].cleanup)
6192 profile->stage[stage].cleanup(dev);
6193 }
6194
6195 ib_dealloc_device((struct ib_device *)dev);
6196 }
6197
6198 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6199 const struct mlx5_ib_profile *profile)
6200 {
6201 int err;
6202 int i;
6203
6204 printk_once(KERN_INFO "%s", mlx5_version);
6205
6206 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6207 if (profile->stage[i].init) {
6208 err = profile->stage[i].init(dev);
6209 if (err)
6210 goto err_out;
6211 }
6212 }
6213
6214 dev->profile = profile;
6215 dev->ib_active = true;
6216
6217 return dev;
6218
6219 err_out:
6220 __mlx5_ib_remove(dev, profile, i);
6221
6222 return NULL;
6223 }
6224
6225 static const struct mlx5_ib_profile pf_profile = {
6226 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6227 mlx5_ib_stage_init_init,
6228 mlx5_ib_stage_init_cleanup),
6229 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6230 mlx5_ib_stage_flow_db_init,
6231 mlx5_ib_stage_flow_db_cleanup),
6232 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6233 mlx5_ib_stage_caps_init,
6234 NULL),
6235 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6236 mlx5_ib_stage_non_default_cb,
6237 NULL),
6238 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6239 mlx5_ib_stage_roce_init,
6240 mlx5_ib_stage_roce_cleanup),
6241 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6242 mlx5_ib_stage_dev_res_init,
6243 mlx5_ib_stage_dev_res_cleanup),
6244 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6245 mlx5_ib_stage_odp_init,
6246 NULL),
6247 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6248 mlx5_ib_stage_counters_init,
6249 mlx5_ib_stage_counters_cleanup),
6250 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6251 mlx5_ib_stage_cong_debugfs_init,
6252 mlx5_ib_stage_cong_debugfs_cleanup),
6253 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6254 mlx5_ib_stage_uar_init,
6255 mlx5_ib_stage_uar_cleanup),
6256 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6257 mlx5_ib_stage_bfrag_init,
6258 mlx5_ib_stage_bfrag_cleanup),
6259 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6260 NULL,
6261 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6262 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6263 mlx5_ib_stage_populate_specs,
6264 NULL),
6265 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6266 mlx5_ib_stage_ib_reg_init,
6267 mlx5_ib_stage_ib_reg_cleanup),
6268 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6269 mlx5_ib_stage_post_ib_reg_umr_init,
6270 NULL),
6271 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6272 mlx5_ib_stage_delay_drop_init,
6273 mlx5_ib_stage_delay_drop_cleanup),
6274 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6275 mlx5_ib_stage_class_attr_init,
6276 NULL),
6277 };
6278
6279 static const struct mlx5_ib_profile nic_rep_profile = {
6280 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6281 mlx5_ib_stage_init_init,
6282 mlx5_ib_stage_init_cleanup),
6283 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6284 mlx5_ib_stage_flow_db_init,
6285 mlx5_ib_stage_flow_db_cleanup),
6286 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6287 mlx5_ib_stage_caps_init,
6288 NULL),
6289 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6290 mlx5_ib_stage_rep_non_default_cb,
6291 NULL),
6292 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6293 mlx5_ib_stage_rep_roce_init,
6294 mlx5_ib_stage_rep_roce_cleanup),
6295 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6296 mlx5_ib_stage_dev_res_init,
6297 mlx5_ib_stage_dev_res_cleanup),
6298 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6299 mlx5_ib_stage_counters_init,
6300 mlx5_ib_stage_counters_cleanup),
6301 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6302 mlx5_ib_stage_uar_init,
6303 mlx5_ib_stage_uar_cleanup),
6304 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6305 mlx5_ib_stage_bfrag_init,
6306 mlx5_ib_stage_bfrag_cleanup),
6307 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6308 NULL,
6309 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6310 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6311 mlx5_ib_stage_populate_specs,
6312 NULL),
6313 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6314 mlx5_ib_stage_ib_reg_init,
6315 mlx5_ib_stage_ib_reg_cleanup),
6316 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6317 mlx5_ib_stage_post_ib_reg_umr_init,
6318 NULL),
6319 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6320 mlx5_ib_stage_class_attr_init,
6321 NULL),
6322 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6323 mlx5_ib_stage_rep_reg_init,
6324 mlx5_ib_stage_rep_reg_cleanup),
6325 };
6326
6327 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6328 {
6329 struct mlx5_ib_multiport_info *mpi;
6330 struct mlx5_ib_dev *dev;
6331 bool bound = false;
6332 int err;
6333
6334 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6335 if (!mpi)
6336 return NULL;
6337
6338 mpi->mdev = mdev;
6339
6340 err = mlx5_query_nic_vport_system_image_guid(mdev,
6341 &mpi->sys_image_guid);
6342 if (err) {
6343 kfree(mpi);
6344 return NULL;
6345 }
6346
6347 mutex_lock(&mlx5_ib_multiport_mutex);
6348 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6349 if (dev->sys_image_guid == mpi->sys_image_guid)
6350 bound = mlx5_ib_bind_slave_port(dev, mpi);
6351
6352 if (bound) {
6353 rdma_roce_rescan_device(&dev->ib_dev);
6354 break;
6355 }
6356 }
6357
6358 if (!bound) {
6359 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6360 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6361 }
6362 mutex_unlock(&mlx5_ib_multiport_mutex);
6363
6364 return mpi;
6365 }
6366
6367 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6368 {
6369 enum rdma_link_layer ll;
6370 struct mlx5_ib_dev *dev;
6371 int port_type_cap;
6372
6373 printk_once(KERN_INFO "%s", mlx5_version);
6374
6375 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6376 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6377
6378 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6379 return mlx5_ib_add_slave_port(mdev);
6380
6381 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6382 if (!dev)
6383 return NULL;
6384
6385 dev->mdev = mdev;
6386 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6387 MLX5_CAP_GEN(mdev, num_vhca_ports));
6388
6389 if (MLX5_ESWITCH_MANAGER(mdev) &&
6390 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6391 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6392
6393 return __mlx5_ib_add(dev, &nic_rep_profile);
6394 }
6395
6396 return __mlx5_ib_add(dev, &pf_profile);
6397 }
6398
6399 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6400 {
6401 struct mlx5_ib_multiport_info *mpi;
6402 struct mlx5_ib_dev *dev;
6403
6404 if (mlx5_core_is_mp_slave(mdev)) {
6405 mpi = context;
6406 mutex_lock(&mlx5_ib_multiport_mutex);
6407 if (mpi->ibdev)
6408 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6409 list_del(&mpi->list);
6410 mutex_unlock(&mlx5_ib_multiport_mutex);
6411 return;
6412 }
6413
6414 dev = context;
6415 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6416 }
6417
6418 static struct mlx5_interface mlx5_ib_interface = {
6419 .add = mlx5_ib_add,
6420 .remove = mlx5_ib_remove,
6421 .event = mlx5_ib_event,
6422 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6423 .pfault = mlx5_ib_pfault,
6424 #endif
6425 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6426 };
6427
6428 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6429 {
6430 mutex_lock(&xlt_emergency_page_mutex);
6431 return xlt_emergency_page;
6432 }
6433
6434 void mlx5_ib_put_xlt_emergency_page(void)
6435 {
6436 mutex_unlock(&xlt_emergency_page_mutex);
6437 }
6438
6439 static int __init mlx5_ib_init(void)
6440 {
6441 int err;
6442
6443 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6444 if (!xlt_emergency_page)
6445 return -ENOMEM;
6446
6447 mutex_init(&xlt_emergency_page_mutex);
6448
6449 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6450 if (!mlx5_ib_event_wq) {
6451 free_page(xlt_emergency_page);
6452 return -ENOMEM;
6453 }
6454
6455 mlx5_ib_odp_init();
6456
6457 err = mlx5_register_interface(&mlx5_ib_interface);
6458
6459 return err;
6460 }
6461
6462 static void __exit mlx5_ib_cleanup(void)
6463 {
6464 mlx5_unregister_interface(&mlx5_ib_interface);
6465 destroy_workqueue(mlx5_ib_event_wq);
6466 mutex_destroy(&xlt_emergency_page_mutex);
6467 free_page(xlt_emergency_page);
6468 }
6469
6470 module_init(mlx5_ib_init);
6471 module_exit(mlx5_ib_cleanup);
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