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1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/debugfs.h>
34 #include <linux/highmem.h>
35 #include <linux/module.h>
36 #include <linux/init.h>
37 #include <linux/errno.h>
38 #include <linux/pci.h>
39 #include <linux/dma-mapping.h>
40 #include <linux/slab.h>
41 #include <linux/bitmap.h>
42 #if defined(CONFIG_X86)
43 #include <asm/pat.h>
44 #endif
45 #include <linux/sched.h>
46 #include <linux/sched/mm.h>
47 #include <linux/sched/task.h>
48 #include <linux/delay.h>
49 #include <rdma/ib_user_verbs.h>
50 #include <rdma/ib_addr.h>
51 #include <rdma/ib_cache.h>
52 #include <linux/mlx5/port.h>
53 #include <linux/mlx5/vport.h>
54 #include <linux/mlx5/fs.h>
55 #include <linux/list.h>
56 #include <rdma/ib_smi.h>
57 #include <rdma/ib_umem.h>
58 #include <linux/in.h>
59 #include <linux/etherdevice.h>
60 #include "mlx5_ib.h"
61 #include "ib_rep.h"
62 #include "cmd.h"
63 #include <linux/mlx5/fs_helpers.h>
64 #include <linux/mlx5/accel.h>
65 #include <rdma/uverbs_std_types.h>
66 #include <rdma/mlx5_user_ioctl_verbs.h>
67 #include <rdma/mlx5_user_ioctl_cmds.h>
68
69 #define UVERBS_MODULE_NAME mlx5_ib
70 #include <rdma/uverbs_named_ioctl.h>
71
72 #define DRIVER_NAME "mlx5_ib"
73 #define DRIVER_VERSION "5.0-0"
74
75 MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
76 MODULE_DESCRIPTION("Mellanox Connect-IB HCA IB driver");
77 MODULE_LICENSE("Dual BSD/GPL");
78
79 static char mlx5_version[] =
80 DRIVER_NAME ": Mellanox Connect-IB Infiniband driver v"
81 DRIVER_VERSION "\n";
82
83 struct mlx5_ib_event_work {
84 struct work_struct work;
85 struct mlx5_core_dev *dev;
86 void *context;
87 enum mlx5_dev_event event;
88 unsigned long param;
89 };
90
91 enum {
92 MLX5_ATOMIC_SIZE_QP_8BYTES = 1 << 3,
93 };
94
95 static struct workqueue_struct *mlx5_ib_event_wq;
96 static LIST_HEAD(mlx5_ib_unaffiliated_port_list);
97 static LIST_HEAD(mlx5_ib_dev_list);
98 /*
99 * This mutex should be held when accessing either of the above lists
100 */
101 static DEFINE_MUTEX(mlx5_ib_multiport_mutex);
102
103 /* We can't use an array for xlt_emergency_page because dma_map_single
104 * doesn't work on kernel modules memory
105 */
106 static unsigned long xlt_emergency_page;
107 static struct mutex xlt_emergency_page_mutex;
108
109 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi)
110 {
111 struct mlx5_ib_dev *dev;
112
113 mutex_lock(&mlx5_ib_multiport_mutex);
114 dev = mpi->ibdev;
115 mutex_unlock(&mlx5_ib_multiport_mutex);
116 return dev;
117 }
118
119 static enum rdma_link_layer
120 mlx5_port_type_cap_to_rdma_ll(int port_type_cap)
121 {
122 switch (port_type_cap) {
123 case MLX5_CAP_PORT_TYPE_IB:
124 return IB_LINK_LAYER_INFINIBAND;
125 case MLX5_CAP_PORT_TYPE_ETH:
126 return IB_LINK_LAYER_ETHERNET;
127 default:
128 return IB_LINK_LAYER_UNSPECIFIED;
129 }
130 }
131
132 static enum rdma_link_layer
133 mlx5_ib_port_link_layer(struct ib_device *device, u8 port_num)
134 {
135 struct mlx5_ib_dev *dev = to_mdev(device);
136 int port_type_cap = MLX5_CAP_GEN(dev->mdev, port_type);
137
138 return mlx5_port_type_cap_to_rdma_ll(port_type_cap);
139 }
140
141 static int get_port_state(struct ib_device *ibdev,
142 u8 port_num,
143 enum ib_port_state *state)
144 {
145 struct ib_port_attr attr;
146 int ret;
147
148 memset(&attr, 0, sizeof(attr));
149 ret = ibdev->query_port(ibdev, port_num, &attr);
150 if (!ret)
151 *state = attr.state;
152 return ret;
153 }
154
155 static int mlx5_netdev_event(struct notifier_block *this,
156 unsigned long event, void *ptr)
157 {
158 struct mlx5_roce *roce = container_of(this, struct mlx5_roce, nb);
159 struct net_device *ndev = netdev_notifier_info_to_dev(ptr);
160 u8 port_num = roce->native_port_num;
161 struct mlx5_core_dev *mdev;
162 struct mlx5_ib_dev *ibdev;
163
164 ibdev = roce->dev;
165 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
166 if (!mdev)
167 return NOTIFY_DONE;
168
169 switch (event) {
170 case NETDEV_REGISTER:
171 case NETDEV_UNREGISTER:
172 write_lock(&roce->netdev_lock);
173 if (ibdev->rep) {
174 struct mlx5_eswitch *esw = ibdev->mdev->priv.eswitch;
175 struct net_device *rep_ndev;
176
177 rep_ndev = mlx5_ib_get_rep_netdev(esw,
178 ibdev->rep->vport);
179 if (rep_ndev == ndev)
180 roce->netdev = (event == NETDEV_UNREGISTER) ?
181 NULL : ndev;
182 } else if (ndev->dev.parent == &mdev->pdev->dev) {
183 roce->netdev = (event == NETDEV_UNREGISTER) ?
184 NULL : ndev;
185 }
186 write_unlock(&roce->netdev_lock);
187 break;
188
189 case NETDEV_CHANGE:
190 case NETDEV_UP:
191 case NETDEV_DOWN: {
192 struct net_device *lag_ndev = mlx5_lag_get_roce_netdev(mdev);
193 struct net_device *upper = NULL;
194
195 if (lag_ndev) {
196 upper = netdev_master_upper_dev_get(lag_ndev);
197 dev_put(lag_ndev);
198 }
199
200 if ((upper == ndev || (!upper && ndev == roce->netdev))
201 && ibdev->ib_active) {
202 struct ib_event ibev = { };
203 enum ib_port_state port_state;
204
205 if (get_port_state(&ibdev->ib_dev, port_num,
206 &port_state))
207 goto done;
208
209 if (roce->last_port_state == port_state)
210 goto done;
211
212 roce->last_port_state = port_state;
213 ibev.device = &ibdev->ib_dev;
214 if (port_state == IB_PORT_DOWN)
215 ibev.event = IB_EVENT_PORT_ERR;
216 else if (port_state == IB_PORT_ACTIVE)
217 ibev.event = IB_EVENT_PORT_ACTIVE;
218 else
219 goto done;
220
221 ibev.element.port_num = port_num;
222 ib_dispatch_event(&ibev);
223 }
224 break;
225 }
226
227 default:
228 break;
229 }
230 done:
231 mlx5_ib_put_native_port_mdev(ibdev, port_num);
232 return NOTIFY_DONE;
233 }
234
235 static struct net_device *mlx5_ib_get_netdev(struct ib_device *device,
236 u8 port_num)
237 {
238 struct mlx5_ib_dev *ibdev = to_mdev(device);
239 struct net_device *ndev;
240 struct mlx5_core_dev *mdev;
241
242 mdev = mlx5_ib_get_native_port_mdev(ibdev, port_num, NULL);
243 if (!mdev)
244 return NULL;
245
246 ndev = mlx5_lag_get_roce_netdev(mdev);
247 if (ndev)
248 goto out;
249
250 /* Ensure ndev does not disappear before we invoke dev_hold()
251 */
252 read_lock(&ibdev->roce[port_num - 1].netdev_lock);
253 ndev = ibdev->roce[port_num - 1].netdev;
254 if (ndev)
255 dev_hold(ndev);
256 read_unlock(&ibdev->roce[port_num - 1].netdev_lock);
257
258 out:
259 mlx5_ib_put_native_port_mdev(ibdev, port_num);
260 return ndev;
261 }
262
263 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *ibdev,
264 u8 ib_port_num,
265 u8 *native_port_num)
266 {
267 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
268 ib_port_num);
269 struct mlx5_core_dev *mdev = NULL;
270 struct mlx5_ib_multiport_info *mpi;
271 struct mlx5_ib_port *port;
272
273 if (!mlx5_core_mp_enabled(ibdev->mdev) ||
274 ll != IB_LINK_LAYER_ETHERNET) {
275 if (native_port_num)
276 *native_port_num = ib_port_num;
277 return ibdev->mdev;
278 }
279
280 if (native_port_num)
281 *native_port_num = 1;
282
283 port = &ibdev->port[ib_port_num - 1];
284 if (!port)
285 return NULL;
286
287 spin_lock(&port->mp.mpi_lock);
288 mpi = ibdev->port[ib_port_num - 1].mp.mpi;
289 if (mpi && !mpi->unaffiliate) {
290 mdev = mpi->mdev;
291 /* If it's the master no need to refcount, it'll exist
292 * as long as the ib_dev exists.
293 */
294 if (!mpi->is_master)
295 mpi->mdev_refcnt++;
296 }
297 spin_unlock(&port->mp.mpi_lock);
298
299 return mdev;
300 }
301
302 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *ibdev, u8 port_num)
303 {
304 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&ibdev->ib_dev,
305 port_num);
306 struct mlx5_ib_multiport_info *mpi;
307 struct mlx5_ib_port *port;
308
309 if (!mlx5_core_mp_enabled(ibdev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
310 return;
311
312 port = &ibdev->port[port_num - 1];
313
314 spin_lock(&port->mp.mpi_lock);
315 mpi = ibdev->port[port_num - 1].mp.mpi;
316 if (mpi->is_master)
317 goto out;
318
319 mpi->mdev_refcnt--;
320 if (mpi->unaffiliate)
321 complete(&mpi->unref_comp);
322 out:
323 spin_unlock(&port->mp.mpi_lock);
324 }
325
326 static int translate_eth_proto_oper(u32 eth_proto_oper, u8 *active_speed,
327 u8 *active_width)
328 {
329 switch (eth_proto_oper) {
330 case MLX5E_PROT_MASK(MLX5E_1000BASE_CX_SGMII):
331 case MLX5E_PROT_MASK(MLX5E_1000BASE_KX):
332 case MLX5E_PROT_MASK(MLX5E_100BASE_TX):
333 case MLX5E_PROT_MASK(MLX5E_1000BASE_T):
334 *active_width = IB_WIDTH_1X;
335 *active_speed = IB_SPEED_SDR;
336 break;
337 case MLX5E_PROT_MASK(MLX5E_10GBASE_T):
338 case MLX5E_PROT_MASK(MLX5E_10GBASE_CX4):
339 case MLX5E_PROT_MASK(MLX5E_10GBASE_KX4):
340 case MLX5E_PROT_MASK(MLX5E_10GBASE_KR):
341 case MLX5E_PROT_MASK(MLX5E_10GBASE_CR):
342 case MLX5E_PROT_MASK(MLX5E_10GBASE_SR):
343 case MLX5E_PROT_MASK(MLX5E_10GBASE_ER):
344 *active_width = IB_WIDTH_1X;
345 *active_speed = IB_SPEED_QDR;
346 break;
347 case MLX5E_PROT_MASK(MLX5E_25GBASE_CR):
348 case MLX5E_PROT_MASK(MLX5E_25GBASE_KR):
349 case MLX5E_PROT_MASK(MLX5E_25GBASE_SR):
350 *active_width = IB_WIDTH_1X;
351 *active_speed = IB_SPEED_EDR;
352 break;
353 case MLX5E_PROT_MASK(MLX5E_40GBASE_CR4):
354 case MLX5E_PROT_MASK(MLX5E_40GBASE_KR4):
355 case MLX5E_PROT_MASK(MLX5E_40GBASE_SR4):
356 case MLX5E_PROT_MASK(MLX5E_40GBASE_LR4):
357 *active_width = IB_WIDTH_4X;
358 *active_speed = IB_SPEED_QDR;
359 break;
360 case MLX5E_PROT_MASK(MLX5E_50GBASE_CR2):
361 case MLX5E_PROT_MASK(MLX5E_50GBASE_KR2):
362 case MLX5E_PROT_MASK(MLX5E_50GBASE_SR2):
363 *active_width = IB_WIDTH_1X;
364 *active_speed = IB_SPEED_HDR;
365 break;
366 case MLX5E_PROT_MASK(MLX5E_56GBASE_R4):
367 *active_width = IB_WIDTH_4X;
368 *active_speed = IB_SPEED_FDR;
369 break;
370 case MLX5E_PROT_MASK(MLX5E_100GBASE_CR4):
371 case MLX5E_PROT_MASK(MLX5E_100GBASE_SR4):
372 case MLX5E_PROT_MASK(MLX5E_100GBASE_KR4):
373 case MLX5E_PROT_MASK(MLX5E_100GBASE_LR4):
374 *active_width = IB_WIDTH_4X;
375 *active_speed = IB_SPEED_EDR;
376 break;
377 default:
378 return -EINVAL;
379 }
380
381 return 0;
382 }
383
384 static int mlx5_query_port_roce(struct ib_device *device, u8 port_num,
385 struct ib_port_attr *props)
386 {
387 struct mlx5_ib_dev *dev = to_mdev(device);
388 struct mlx5_core_dev *mdev;
389 struct net_device *ndev, *upper;
390 enum ib_mtu ndev_ib_mtu;
391 bool put_mdev = true;
392 u16 qkey_viol_cntr;
393 u32 eth_prot_oper;
394 u8 mdev_port_num;
395 int err;
396
397 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
398 if (!mdev) {
399 /* This means the port isn't affiliated yet. Get the
400 * info for the master port instead.
401 */
402 put_mdev = false;
403 mdev = dev->mdev;
404 mdev_port_num = 1;
405 port_num = 1;
406 }
407
408 /* Possible bad flows are checked before filling out props so in case
409 * of an error it will still be zeroed out.
410 */
411 err = mlx5_query_port_eth_proto_oper(mdev, &eth_prot_oper,
412 mdev_port_num);
413 if (err)
414 goto out;
415
416 props->active_width = IB_WIDTH_4X;
417 props->active_speed = IB_SPEED_QDR;
418
419 translate_eth_proto_oper(eth_prot_oper, &props->active_speed,
420 &props->active_width);
421
422 props->port_cap_flags |= IB_PORT_CM_SUP;
423 props->ip_gids = true;
424
425 props->gid_tbl_len = MLX5_CAP_ROCE(dev->mdev,
426 roce_address_table_size);
427 props->max_mtu = IB_MTU_4096;
428 props->max_msg_sz = 1 << MLX5_CAP_GEN(dev->mdev, log_max_msg);
429 props->pkey_tbl_len = 1;
430 props->state = IB_PORT_DOWN;
431 props->phys_state = 3;
432
433 mlx5_query_nic_vport_qkey_viol_cntr(mdev, &qkey_viol_cntr);
434 props->qkey_viol_cntr = qkey_viol_cntr;
435
436 /* If this is a stub query for an unaffiliated port stop here */
437 if (!put_mdev)
438 goto out;
439
440 ndev = mlx5_ib_get_netdev(device, port_num);
441 if (!ndev)
442 goto out;
443
444 if (mlx5_lag_is_active(dev->mdev)) {
445 rcu_read_lock();
446 upper = netdev_master_upper_dev_get_rcu(ndev);
447 if (upper) {
448 dev_put(ndev);
449 ndev = upper;
450 dev_hold(ndev);
451 }
452 rcu_read_unlock();
453 }
454
455 if (netif_running(ndev) && netif_carrier_ok(ndev)) {
456 props->state = IB_PORT_ACTIVE;
457 props->phys_state = 5;
458 }
459
460 ndev_ib_mtu = iboe_get_mtu(ndev->mtu);
461
462 dev_put(ndev);
463
464 props->active_mtu = min(props->max_mtu, ndev_ib_mtu);
465 out:
466 if (put_mdev)
467 mlx5_ib_put_native_port_mdev(dev, port_num);
468 return err;
469 }
470
471 static int set_roce_addr(struct mlx5_ib_dev *dev, u8 port_num,
472 unsigned int index, const union ib_gid *gid,
473 const struct ib_gid_attr *attr)
474 {
475 enum ib_gid_type gid_type = IB_GID_TYPE_IB;
476 u8 roce_version = 0;
477 u8 roce_l3_type = 0;
478 bool vlan = false;
479 u8 mac[ETH_ALEN];
480 u16 vlan_id = 0;
481
482 if (gid) {
483 gid_type = attr->gid_type;
484 ether_addr_copy(mac, attr->ndev->dev_addr);
485
486 if (is_vlan_dev(attr->ndev)) {
487 vlan = true;
488 vlan_id = vlan_dev_vlan_id(attr->ndev);
489 }
490 }
491
492 switch (gid_type) {
493 case IB_GID_TYPE_IB:
494 roce_version = MLX5_ROCE_VERSION_1;
495 break;
496 case IB_GID_TYPE_ROCE_UDP_ENCAP:
497 roce_version = MLX5_ROCE_VERSION_2;
498 if (ipv6_addr_v4mapped((void *)gid))
499 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV4;
500 else
501 roce_l3_type = MLX5_ROCE_L3_TYPE_IPV6;
502 break;
503
504 default:
505 mlx5_ib_warn(dev, "Unexpected GID type %u\n", gid_type);
506 }
507
508 return mlx5_core_roce_gid_set(dev->mdev, index, roce_version,
509 roce_l3_type, gid->raw, mac, vlan,
510 vlan_id, port_num);
511 }
512
513 static int mlx5_ib_add_gid(const struct ib_gid_attr *attr,
514 __always_unused void **context)
515 {
516 return set_roce_addr(to_mdev(attr->device), attr->port_num,
517 attr->index, &attr->gid, attr);
518 }
519
520 static int mlx5_ib_del_gid(const struct ib_gid_attr *attr,
521 __always_unused void **context)
522 {
523 return set_roce_addr(to_mdev(attr->device), attr->port_num,
524 attr->index, NULL, NULL);
525 }
526
527 __be16 mlx5_get_roce_udp_sport(struct mlx5_ib_dev *dev,
528 const struct ib_gid_attr *attr)
529 {
530 if (attr->gid_type != IB_GID_TYPE_ROCE_UDP_ENCAP)
531 return 0;
532
533 return cpu_to_be16(MLX5_CAP_ROCE(dev->mdev, r_roce_min_src_udp_port));
534 }
535
536 static int mlx5_use_mad_ifc(struct mlx5_ib_dev *dev)
537 {
538 if (MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_IB)
539 return !MLX5_CAP_GEN(dev->mdev, ib_virt);
540 return 0;
541 }
542
543 enum {
544 MLX5_VPORT_ACCESS_METHOD_MAD,
545 MLX5_VPORT_ACCESS_METHOD_HCA,
546 MLX5_VPORT_ACCESS_METHOD_NIC,
547 };
548
549 static int mlx5_get_vport_access_method(struct ib_device *ibdev)
550 {
551 if (mlx5_use_mad_ifc(to_mdev(ibdev)))
552 return MLX5_VPORT_ACCESS_METHOD_MAD;
553
554 if (mlx5_ib_port_link_layer(ibdev, 1) ==
555 IB_LINK_LAYER_ETHERNET)
556 return MLX5_VPORT_ACCESS_METHOD_NIC;
557
558 return MLX5_VPORT_ACCESS_METHOD_HCA;
559 }
560
561 static void get_atomic_caps(struct mlx5_ib_dev *dev,
562 u8 atomic_size_qp,
563 struct ib_device_attr *props)
564 {
565 u8 tmp;
566 u8 atomic_operations = MLX5_CAP_ATOMIC(dev->mdev, atomic_operations);
567 u8 atomic_req_8B_endianness_mode =
568 MLX5_CAP_ATOMIC(dev->mdev, atomic_req_8B_endianness_mode);
569
570 /* Check if HW supports 8 bytes standard atomic operations and capable
571 * of host endianness respond
572 */
573 tmp = MLX5_ATOMIC_OPS_CMP_SWAP | MLX5_ATOMIC_OPS_FETCH_ADD;
574 if (((atomic_operations & tmp) == tmp) &&
575 (atomic_size_qp & MLX5_ATOMIC_SIZE_QP_8BYTES) &&
576 (atomic_req_8B_endianness_mode)) {
577 props->atomic_cap = IB_ATOMIC_HCA;
578 } else {
579 props->atomic_cap = IB_ATOMIC_NONE;
580 }
581 }
582
583 static void get_atomic_caps_qp(struct mlx5_ib_dev *dev,
584 struct ib_device_attr *props)
585 {
586 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_qp);
587
588 get_atomic_caps(dev, atomic_size_qp, props);
589 }
590
591 static void get_atomic_caps_dc(struct mlx5_ib_dev *dev,
592 struct ib_device_attr *props)
593 {
594 u8 atomic_size_qp = MLX5_CAP_ATOMIC(dev->mdev, atomic_size_dc);
595
596 get_atomic_caps(dev, atomic_size_qp, props);
597 }
598
599 bool mlx5_ib_dc_atomic_is_supported(struct mlx5_ib_dev *dev)
600 {
601 struct ib_device_attr props = {};
602
603 get_atomic_caps_dc(dev, &props);
604 return (props.atomic_cap == IB_ATOMIC_HCA) ? true : false;
605 }
606 static int mlx5_query_system_image_guid(struct ib_device *ibdev,
607 __be64 *sys_image_guid)
608 {
609 struct mlx5_ib_dev *dev = to_mdev(ibdev);
610 struct mlx5_core_dev *mdev = dev->mdev;
611 u64 tmp;
612 int err;
613
614 switch (mlx5_get_vport_access_method(ibdev)) {
615 case MLX5_VPORT_ACCESS_METHOD_MAD:
616 return mlx5_query_mad_ifc_system_image_guid(ibdev,
617 sys_image_guid);
618
619 case MLX5_VPORT_ACCESS_METHOD_HCA:
620 err = mlx5_query_hca_vport_system_image_guid(mdev, &tmp);
621 break;
622
623 case MLX5_VPORT_ACCESS_METHOD_NIC:
624 err = mlx5_query_nic_vport_system_image_guid(mdev, &tmp);
625 break;
626
627 default:
628 return -EINVAL;
629 }
630
631 if (!err)
632 *sys_image_guid = cpu_to_be64(tmp);
633
634 return err;
635
636 }
637
638 static int mlx5_query_max_pkeys(struct ib_device *ibdev,
639 u16 *max_pkeys)
640 {
641 struct mlx5_ib_dev *dev = to_mdev(ibdev);
642 struct mlx5_core_dev *mdev = dev->mdev;
643
644 switch (mlx5_get_vport_access_method(ibdev)) {
645 case MLX5_VPORT_ACCESS_METHOD_MAD:
646 return mlx5_query_mad_ifc_max_pkeys(ibdev, max_pkeys);
647
648 case MLX5_VPORT_ACCESS_METHOD_HCA:
649 case MLX5_VPORT_ACCESS_METHOD_NIC:
650 *max_pkeys = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev,
651 pkey_table_size));
652 return 0;
653
654 default:
655 return -EINVAL;
656 }
657 }
658
659 static int mlx5_query_vendor_id(struct ib_device *ibdev,
660 u32 *vendor_id)
661 {
662 struct mlx5_ib_dev *dev = to_mdev(ibdev);
663
664 switch (mlx5_get_vport_access_method(ibdev)) {
665 case MLX5_VPORT_ACCESS_METHOD_MAD:
666 return mlx5_query_mad_ifc_vendor_id(ibdev, vendor_id);
667
668 case MLX5_VPORT_ACCESS_METHOD_HCA:
669 case MLX5_VPORT_ACCESS_METHOD_NIC:
670 return mlx5_core_query_vendor_id(dev->mdev, vendor_id);
671
672 default:
673 return -EINVAL;
674 }
675 }
676
677 static int mlx5_query_node_guid(struct mlx5_ib_dev *dev,
678 __be64 *node_guid)
679 {
680 u64 tmp;
681 int err;
682
683 switch (mlx5_get_vport_access_method(&dev->ib_dev)) {
684 case MLX5_VPORT_ACCESS_METHOD_MAD:
685 return mlx5_query_mad_ifc_node_guid(dev, node_guid);
686
687 case MLX5_VPORT_ACCESS_METHOD_HCA:
688 err = mlx5_query_hca_vport_node_guid(dev->mdev, &tmp);
689 break;
690
691 case MLX5_VPORT_ACCESS_METHOD_NIC:
692 err = mlx5_query_nic_vport_node_guid(dev->mdev, &tmp);
693 break;
694
695 default:
696 return -EINVAL;
697 }
698
699 if (!err)
700 *node_guid = cpu_to_be64(tmp);
701
702 return err;
703 }
704
705 struct mlx5_reg_node_desc {
706 u8 desc[IB_DEVICE_NODE_DESC_MAX];
707 };
708
709 static int mlx5_query_node_desc(struct mlx5_ib_dev *dev, char *node_desc)
710 {
711 struct mlx5_reg_node_desc in;
712
713 if (mlx5_use_mad_ifc(dev))
714 return mlx5_query_mad_ifc_node_desc(dev, node_desc);
715
716 memset(&in, 0, sizeof(in));
717
718 return mlx5_core_access_reg(dev->mdev, &in, sizeof(in), node_desc,
719 sizeof(struct mlx5_reg_node_desc),
720 MLX5_REG_NODE_DESC, 0, 0);
721 }
722
723 static int mlx5_ib_query_device(struct ib_device *ibdev,
724 struct ib_device_attr *props,
725 struct ib_udata *uhw)
726 {
727 struct mlx5_ib_dev *dev = to_mdev(ibdev);
728 struct mlx5_core_dev *mdev = dev->mdev;
729 int err = -ENOMEM;
730 int max_sq_desc;
731 int max_rq_sg;
732 int max_sq_sg;
733 u64 min_page_size = 1ull << MLX5_CAP_GEN(mdev, log_pg_sz);
734 bool raw_support = !mlx5_core_mp_enabled(mdev);
735 struct mlx5_ib_query_device_resp resp = {};
736 size_t resp_len;
737 u64 max_tso;
738
739 resp_len = sizeof(resp.comp_mask) + sizeof(resp.response_length);
740 if (uhw->outlen && uhw->outlen < resp_len)
741 return -EINVAL;
742 else
743 resp.response_length = resp_len;
744
745 if (uhw->inlen && !ib_is_udata_cleared(uhw, 0, uhw->inlen))
746 return -EINVAL;
747
748 memset(props, 0, sizeof(*props));
749 err = mlx5_query_system_image_guid(ibdev,
750 &props->sys_image_guid);
751 if (err)
752 return err;
753
754 err = mlx5_query_max_pkeys(ibdev, &props->max_pkeys);
755 if (err)
756 return err;
757
758 err = mlx5_query_vendor_id(ibdev, &props->vendor_id);
759 if (err)
760 return err;
761
762 props->fw_ver = ((u64)fw_rev_maj(dev->mdev) << 32) |
763 (fw_rev_min(dev->mdev) << 16) |
764 fw_rev_sub(dev->mdev);
765 props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
766 IB_DEVICE_PORT_ACTIVE_EVENT |
767 IB_DEVICE_SYS_IMAGE_GUID |
768 IB_DEVICE_RC_RNR_NAK_GEN;
769
770 if (MLX5_CAP_GEN(mdev, pkv))
771 props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
772 if (MLX5_CAP_GEN(mdev, qkv))
773 props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
774 if (MLX5_CAP_GEN(mdev, apm))
775 props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
776 if (MLX5_CAP_GEN(mdev, xrc))
777 props->device_cap_flags |= IB_DEVICE_XRC;
778 if (MLX5_CAP_GEN(mdev, imaicl)) {
779 props->device_cap_flags |= IB_DEVICE_MEM_WINDOW |
780 IB_DEVICE_MEM_WINDOW_TYPE_2B;
781 props->max_mw = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
782 /* We support 'Gappy' memory registration too */
783 props->device_cap_flags |= IB_DEVICE_SG_GAPS_REG;
784 }
785 props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
786 if (MLX5_CAP_GEN(mdev, sho)) {
787 props->device_cap_flags |= IB_DEVICE_SIGNATURE_HANDOVER;
788 /* At this stage no support for signature handover */
789 props->sig_prot_cap = IB_PROT_T10DIF_TYPE_1 |
790 IB_PROT_T10DIF_TYPE_2 |
791 IB_PROT_T10DIF_TYPE_3;
792 props->sig_guard_cap = IB_GUARD_T10DIF_CRC |
793 IB_GUARD_T10DIF_CSUM;
794 }
795 if (MLX5_CAP_GEN(mdev, block_lb_mc))
796 props->device_cap_flags |= IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
797
798 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) && raw_support) {
799 if (MLX5_CAP_ETH(mdev, csum_cap)) {
800 /* Legacy bit to support old userspace libraries */
801 props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
802 props->raw_packet_caps |= IB_RAW_PACKET_CAP_IP_CSUM;
803 }
804
805 if (MLX5_CAP_ETH(dev->mdev, vlan_cap))
806 props->raw_packet_caps |=
807 IB_RAW_PACKET_CAP_CVLAN_STRIPPING;
808
809 if (field_avail(typeof(resp), tso_caps, uhw->outlen)) {
810 max_tso = MLX5_CAP_ETH(mdev, max_lso_cap);
811 if (max_tso) {
812 resp.tso_caps.max_tso = 1 << max_tso;
813 resp.tso_caps.supported_qpts |=
814 1 << IB_QPT_RAW_PACKET;
815 resp.response_length += sizeof(resp.tso_caps);
816 }
817 }
818
819 if (field_avail(typeof(resp), rss_caps, uhw->outlen)) {
820 resp.rss_caps.rx_hash_function =
821 MLX5_RX_HASH_FUNC_TOEPLITZ;
822 resp.rss_caps.rx_hash_fields_mask =
823 MLX5_RX_HASH_SRC_IPV4 |
824 MLX5_RX_HASH_DST_IPV4 |
825 MLX5_RX_HASH_SRC_IPV6 |
826 MLX5_RX_HASH_DST_IPV6 |
827 MLX5_RX_HASH_SRC_PORT_TCP |
828 MLX5_RX_HASH_DST_PORT_TCP |
829 MLX5_RX_HASH_SRC_PORT_UDP |
830 MLX5_RX_HASH_DST_PORT_UDP |
831 MLX5_RX_HASH_INNER;
832 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
833 MLX5_ACCEL_IPSEC_CAP_DEVICE)
834 resp.rss_caps.rx_hash_fields_mask |=
835 MLX5_RX_HASH_IPSEC_SPI;
836 resp.response_length += sizeof(resp.rss_caps);
837 }
838 } else {
839 if (field_avail(typeof(resp), tso_caps, uhw->outlen))
840 resp.response_length += sizeof(resp.tso_caps);
841 if (field_avail(typeof(resp), rss_caps, uhw->outlen))
842 resp.response_length += sizeof(resp.rss_caps);
843 }
844
845 if (MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
846 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
847 props->device_cap_flags |= IB_DEVICE_UD_TSO;
848 }
849
850 if (MLX5_CAP_GEN(dev->mdev, rq_delay_drop) &&
851 MLX5_CAP_GEN(dev->mdev, general_notification_event) &&
852 raw_support)
853 props->raw_packet_caps |= IB_RAW_PACKET_CAP_DELAY_DROP;
854
855 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads) &&
856 MLX5_CAP_IPOIB_ENHANCED(mdev, csum_cap))
857 props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
858
859 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
860 MLX5_CAP_ETH(dev->mdev, scatter_fcs) &&
861 raw_support) {
862 /* Legacy bit to support old userspace libraries */
863 props->device_cap_flags |= IB_DEVICE_RAW_SCATTER_FCS;
864 props->raw_packet_caps |= IB_RAW_PACKET_CAP_SCATTER_FCS;
865 }
866
867 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
868 props->max_dm_size =
869 MLX5_CAP_DEV_MEM(mdev, max_memic_size);
870 }
871
872 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS))
873 props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
874
875 if (MLX5_CAP_GEN(mdev, end_pad))
876 props->device_cap_flags |= IB_DEVICE_PCI_WRITE_END_PADDING;
877
878 props->vendor_part_id = mdev->pdev->device;
879 props->hw_ver = mdev->pdev->revision;
880
881 props->max_mr_size = ~0ull;
882 props->page_size_cap = ~(min_page_size - 1);
883 props->max_qp = 1 << MLX5_CAP_GEN(mdev, log_max_qp);
884 props->max_qp_wr = 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
885 max_rq_sg = MLX5_CAP_GEN(mdev, max_wqe_sz_rq) /
886 sizeof(struct mlx5_wqe_data_seg);
887 max_sq_desc = min_t(int, MLX5_CAP_GEN(mdev, max_wqe_sz_sq), 512);
888 max_sq_sg = (max_sq_desc - sizeof(struct mlx5_wqe_ctrl_seg) -
889 sizeof(struct mlx5_wqe_raddr_seg)) /
890 sizeof(struct mlx5_wqe_data_seg);
891 props->max_send_sge = max_sq_sg;
892 props->max_recv_sge = max_rq_sg;
893 props->max_sge_rd = MLX5_MAX_SGE_RD;
894 props->max_cq = 1 << MLX5_CAP_GEN(mdev, log_max_cq);
895 props->max_cqe = (1 << MLX5_CAP_GEN(mdev, log_max_cq_sz)) - 1;
896 props->max_mr = 1 << MLX5_CAP_GEN(mdev, log_max_mkey);
897 props->max_pd = 1 << MLX5_CAP_GEN(mdev, log_max_pd);
898 props->max_qp_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_req_qp);
899 props->max_qp_init_rd_atom = 1 << MLX5_CAP_GEN(mdev, log_max_ra_res_qp);
900 props->max_srq = 1 << MLX5_CAP_GEN(mdev, log_max_srq);
901 props->max_srq_wr = (1 << MLX5_CAP_GEN(mdev, log_max_srq_sz)) - 1;
902 props->local_ca_ack_delay = MLX5_CAP_GEN(mdev, local_ca_ack_delay);
903 props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
904 props->max_srq_sge = max_rq_sg - 1;
905 props->max_fast_reg_page_list_len =
906 1 << MLX5_CAP_GEN(mdev, log_max_klm_list_size);
907 get_atomic_caps_qp(dev, props);
908 props->masked_atomic_cap = IB_ATOMIC_NONE;
909 props->max_mcast_grp = 1 << MLX5_CAP_GEN(mdev, log_max_mcg);
910 props->max_mcast_qp_attach = MLX5_CAP_GEN(mdev, max_qp_mcg);
911 props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
912 props->max_mcast_grp;
913 props->max_map_per_fmr = INT_MAX; /* no limit in ConnectIB */
914 props->max_ah = INT_MAX;
915 props->hca_core_clock = MLX5_CAP_GEN(mdev, device_frequency_khz);
916 props->timestamp_mask = 0x7FFFFFFFFFFFFFFFULL;
917
918 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
919 if (MLX5_CAP_GEN(mdev, pg))
920 props->device_cap_flags |= IB_DEVICE_ON_DEMAND_PAGING;
921 props->odp_caps = dev->odp_caps;
922 #endif
923
924 if (MLX5_CAP_GEN(mdev, cd))
925 props->device_cap_flags |= IB_DEVICE_CROSS_CHANNEL;
926
927 if (!mlx5_core_is_pf(mdev))
928 props->device_cap_flags |= IB_DEVICE_VIRTUAL_FUNCTION;
929
930 if (mlx5_ib_port_link_layer(ibdev, 1) ==
931 IB_LINK_LAYER_ETHERNET && raw_support) {
932 props->rss_caps.max_rwq_indirection_tables =
933 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt);
934 props->rss_caps.max_rwq_indirection_table_size =
935 1 << MLX5_CAP_GEN(dev->mdev, log_max_rqt_size);
936 props->rss_caps.supported_qpts = 1 << IB_QPT_RAW_PACKET;
937 props->max_wq_type_rq =
938 1 << MLX5_CAP_GEN(dev->mdev, log_max_rq);
939 }
940
941 if (MLX5_CAP_GEN(mdev, tag_matching)) {
942 props->tm_caps.max_rndv_hdr_size = MLX5_TM_MAX_RNDV_MSG_SIZE;
943 props->tm_caps.max_num_tags =
944 (1 << MLX5_CAP_GEN(mdev, log_tag_matching_list_sz)) - 1;
945 props->tm_caps.flags = IB_TM_CAP_RC;
946 props->tm_caps.max_ops =
947 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
948 props->tm_caps.max_sge = MLX5_TM_MAX_SGE;
949 }
950
951 if (MLX5_CAP_GEN(dev->mdev, cq_moderation)) {
952 props->cq_caps.max_cq_moderation_count =
953 MLX5_MAX_CQ_COUNT;
954 props->cq_caps.max_cq_moderation_period =
955 MLX5_MAX_CQ_PERIOD;
956 }
957
958 if (field_avail(typeof(resp), cqe_comp_caps, uhw->outlen)) {
959 resp.response_length += sizeof(resp.cqe_comp_caps);
960
961 if (MLX5_CAP_GEN(dev->mdev, cqe_compression)) {
962 resp.cqe_comp_caps.max_num =
963 MLX5_CAP_GEN(dev->mdev,
964 cqe_compression_max_num);
965
966 resp.cqe_comp_caps.supported_format =
967 MLX5_IB_CQE_RES_FORMAT_HASH |
968 MLX5_IB_CQE_RES_FORMAT_CSUM;
969
970 if (MLX5_CAP_GEN(dev->mdev, mini_cqe_resp_stride_index))
971 resp.cqe_comp_caps.supported_format |=
972 MLX5_IB_CQE_RES_FORMAT_CSUM_STRIDX;
973 }
974 }
975
976 if (field_avail(typeof(resp), packet_pacing_caps, uhw->outlen) &&
977 raw_support) {
978 if (MLX5_CAP_QOS(mdev, packet_pacing) &&
979 MLX5_CAP_GEN(mdev, qos)) {
980 resp.packet_pacing_caps.qp_rate_limit_max =
981 MLX5_CAP_QOS(mdev, packet_pacing_max_rate);
982 resp.packet_pacing_caps.qp_rate_limit_min =
983 MLX5_CAP_QOS(mdev, packet_pacing_min_rate);
984 resp.packet_pacing_caps.supported_qpts |=
985 1 << IB_QPT_RAW_PACKET;
986 if (MLX5_CAP_QOS(mdev, packet_pacing_burst_bound) &&
987 MLX5_CAP_QOS(mdev, packet_pacing_typical_size))
988 resp.packet_pacing_caps.cap_flags |=
989 MLX5_IB_PP_SUPPORT_BURST;
990 }
991 resp.response_length += sizeof(resp.packet_pacing_caps);
992 }
993
994 if (field_avail(typeof(resp), mlx5_ib_support_multi_pkt_send_wqes,
995 uhw->outlen)) {
996 if (MLX5_CAP_ETH(mdev, multi_pkt_send_wqe))
997 resp.mlx5_ib_support_multi_pkt_send_wqes =
998 MLX5_IB_ALLOW_MPW;
999
1000 if (MLX5_CAP_ETH(mdev, enhanced_multi_pkt_send_wqe))
1001 resp.mlx5_ib_support_multi_pkt_send_wqes |=
1002 MLX5_IB_SUPPORT_EMPW;
1003
1004 resp.response_length +=
1005 sizeof(resp.mlx5_ib_support_multi_pkt_send_wqes);
1006 }
1007
1008 if (field_avail(typeof(resp), flags, uhw->outlen)) {
1009 resp.response_length += sizeof(resp.flags);
1010
1011 if (MLX5_CAP_GEN(mdev, cqe_compression_128))
1012 resp.flags |=
1013 MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_COMP;
1014
1015 if (MLX5_CAP_GEN(mdev, cqe_128_always))
1016 resp.flags |= MLX5_IB_QUERY_DEV_RESP_FLAGS_CQE_128B_PAD;
1017 }
1018
1019 if (field_avail(typeof(resp), sw_parsing_caps,
1020 uhw->outlen)) {
1021 resp.response_length += sizeof(resp.sw_parsing_caps);
1022 if (MLX5_CAP_ETH(mdev, swp)) {
1023 resp.sw_parsing_caps.sw_parsing_offloads |=
1024 MLX5_IB_SW_PARSING;
1025
1026 if (MLX5_CAP_ETH(mdev, swp_csum))
1027 resp.sw_parsing_caps.sw_parsing_offloads |=
1028 MLX5_IB_SW_PARSING_CSUM;
1029
1030 if (MLX5_CAP_ETH(mdev, swp_lso))
1031 resp.sw_parsing_caps.sw_parsing_offloads |=
1032 MLX5_IB_SW_PARSING_LSO;
1033
1034 if (resp.sw_parsing_caps.sw_parsing_offloads)
1035 resp.sw_parsing_caps.supported_qpts =
1036 BIT(IB_QPT_RAW_PACKET);
1037 }
1038 }
1039
1040 if (field_avail(typeof(resp), striding_rq_caps, uhw->outlen) &&
1041 raw_support) {
1042 resp.response_length += sizeof(resp.striding_rq_caps);
1043 if (MLX5_CAP_GEN(mdev, striding_rq)) {
1044 resp.striding_rq_caps.min_single_stride_log_num_of_bytes =
1045 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES;
1046 resp.striding_rq_caps.max_single_stride_log_num_of_bytes =
1047 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES;
1048 resp.striding_rq_caps.min_single_wqe_log_num_of_strides =
1049 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES;
1050 resp.striding_rq_caps.max_single_wqe_log_num_of_strides =
1051 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES;
1052 resp.striding_rq_caps.supported_qpts =
1053 BIT(IB_QPT_RAW_PACKET);
1054 }
1055 }
1056
1057 if (field_avail(typeof(resp), tunnel_offloads_caps,
1058 uhw->outlen)) {
1059 resp.response_length += sizeof(resp.tunnel_offloads_caps);
1060 if (MLX5_CAP_ETH(mdev, tunnel_stateless_vxlan))
1061 resp.tunnel_offloads_caps |=
1062 MLX5_IB_TUNNELED_OFFLOADS_VXLAN;
1063 if (MLX5_CAP_ETH(mdev, tunnel_stateless_geneve_rx))
1064 resp.tunnel_offloads_caps |=
1065 MLX5_IB_TUNNELED_OFFLOADS_GENEVE;
1066 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre))
1067 resp.tunnel_offloads_caps |=
1068 MLX5_IB_TUNNELED_OFFLOADS_GRE;
1069 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1070 MLX5_FLEX_PROTO_CW_MPLS_GRE)
1071 resp.tunnel_offloads_caps |=
1072 MLX5_IB_TUNNELED_OFFLOADS_MPLS_GRE;
1073 if (MLX5_CAP_GEN(mdev, flex_parser_protocols) &
1074 MLX5_FLEX_PROTO_CW_MPLS_UDP)
1075 resp.tunnel_offloads_caps |=
1076 MLX5_IB_TUNNELED_OFFLOADS_MPLS_UDP;
1077 }
1078
1079 if (uhw->outlen) {
1080 err = ib_copy_to_udata(uhw, &resp, resp.response_length);
1081
1082 if (err)
1083 return err;
1084 }
1085
1086 return 0;
1087 }
1088
1089 enum mlx5_ib_width {
1090 MLX5_IB_WIDTH_1X = 1 << 0,
1091 MLX5_IB_WIDTH_2X = 1 << 1,
1092 MLX5_IB_WIDTH_4X = 1 << 2,
1093 MLX5_IB_WIDTH_8X = 1 << 3,
1094 MLX5_IB_WIDTH_12X = 1 << 4
1095 };
1096
1097 static int translate_active_width(struct ib_device *ibdev, u8 active_width,
1098 u8 *ib_width)
1099 {
1100 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1101 int err = 0;
1102
1103 if (active_width & MLX5_IB_WIDTH_1X) {
1104 *ib_width = IB_WIDTH_1X;
1105 } else if (active_width & MLX5_IB_WIDTH_2X) {
1106 mlx5_ib_dbg(dev, "active_width %d is not supported by IB spec\n",
1107 (int)active_width);
1108 err = -EINVAL;
1109 } else if (active_width & MLX5_IB_WIDTH_4X) {
1110 *ib_width = IB_WIDTH_4X;
1111 } else if (active_width & MLX5_IB_WIDTH_8X) {
1112 *ib_width = IB_WIDTH_8X;
1113 } else if (active_width & MLX5_IB_WIDTH_12X) {
1114 *ib_width = IB_WIDTH_12X;
1115 } else {
1116 mlx5_ib_dbg(dev, "Invalid active_width %d\n",
1117 (int)active_width);
1118 err = -EINVAL;
1119 }
1120
1121 return err;
1122 }
1123
1124 static int mlx5_mtu_to_ib_mtu(int mtu)
1125 {
1126 switch (mtu) {
1127 case 256: return 1;
1128 case 512: return 2;
1129 case 1024: return 3;
1130 case 2048: return 4;
1131 case 4096: return 5;
1132 default:
1133 pr_warn("invalid mtu\n");
1134 return -1;
1135 }
1136 }
1137
1138 enum ib_max_vl_num {
1139 __IB_MAX_VL_0 = 1,
1140 __IB_MAX_VL_0_1 = 2,
1141 __IB_MAX_VL_0_3 = 3,
1142 __IB_MAX_VL_0_7 = 4,
1143 __IB_MAX_VL_0_14 = 5,
1144 };
1145
1146 enum mlx5_vl_hw_cap {
1147 MLX5_VL_HW_0 = 1,
1148 MLX5_VL_HW_0_1 = 2,
1149 MLX5_VL_HW_0_2 = 3,
1150 MLX5_VL_HW_0_3 = 4,
1151 MLX5_VL_HW_0_4 = 5,
1152 MLX5_VL_HW_0_5 = 6,
1153 MLX5_VL_HW_0_6 = 7,
1154 MLX5_VL_HW_0_7 = 8,
1155 MLX5_VL_HW_0_14 = 15
1156 };
1157
1158 static int translate_max_vl_num(struct ib_device *ibdev, u8 vl_hw_cap,
1159 u8 *max_vl_num)
1160 {
1161 switch (vl_hw_cap) {
1162 case MLX5_VL_HW_0:
1163 *max_vl_num = __IB_MAX_VL_0;
1164 break;
1165 case MLX5_VL_HW_0_1:
1166 *max_vl_num = __IB_MAX_VL_0_1;
1167 break;
1168 case MLX5_VL_HW_0_3:
1169 *max_vl_num = __IB_MAX_VL_0_3;
1170 break;
1171 case MLX5_VL_HW_0_7:
1172 *max_vl_num = __IB_MAX_VL_0_7;
1173 break;
1174 case MLX5_VL_HW_0_14:
1175 *max_vl_num = __IB_MAX_VL_0_14;
1176 break;
1177
1178 default:
1179 return -EINVAL;
1180 }
1181
1182 return 0;
1183 }
1184
1185 static int mlx5_query_hca_port(struct ib_device *ibdev, u8 port,
1186 struct ib_port_attr *props)
1187 {
1188 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1189 struct mlx5_core_dev *mdev = dev->mdev;
1190 struct mlx5_hca_vport_context *rep;
1191 u16 max_mtu;
1192 u16 oper_mtu;
1193 int err;
1194 u8 ib_link_width_oper;
1195 u8 vl_hw_cap;
1196
1197 rep = kzalloc(sizeof(*rep), GFP_KERNEL);
1198 if (!rep) {
1199 err = -ENOMEM;
1200 goto out;
1201 }
1202
1203 /* props being zeroed by the caller, avoid zeroing it here */
1204
1205 err = mlx5_query_hca_vport_context(mdev, 0, port, 0, rep);
1206 if (err)
1207 goto out;
1208
1209 props->lid = rep->lid;
1210 props->lmc = rep->lmc;
1211 props->sm_lid = rep->sm_lid;
1212 props->sm_sl = rep->sm_sl;
1213 props->state = rep->vport_state;
1214 props->phys_state = rep->port_physical_state;
1215 props->port_cap_flags = rep->cap_mask1;
1216 props->gid_tbl_len = mlx5_get_gid_table_len(MLX5_CAP_GEN(mdev, gid_table_size));
1217 props->max_msg_sz = 1 << MLX5_CAP_GEN(mdev, log_max_msg);
1218 props->pkey_tbl_len = mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(mdev, pkey_table_size));
1219 props->bad_pkey_cntr = rep->pkey_violation_counter;
1220 props->qkey_viol_cntr = rep->qkey_violation_counter;
1221 props->subnet_timeout = rep->subnet_timeout;
1222 props->init_type_reply = rep->init_type_reply;
1223
1224 err = mlx5_query_port_link_width_oper(mdev, &ib_link_width_oper, port);
1225 if (err)
1226 goto out;
1227
1228 err = translate_active_width(ibdev, ib_link_width_oper,
1229 &props->active_width);
1230 if (err)
1231 goto out;
1232 err = mlx5_query_port_ib_proto_oper(mdev, &props->active_speed, port);
1233 if (err)
1234 goto out;
1235
1236 mlx5_query_port_max_mtu(mdev, &max_mtu, port);
1237
1238 props->max_mtu = mlx5_mtu_to_ib_mtu(max_mtu);
1239
1240 mlx5_query_port_oper_mtu(mdev, &oper_mtu, port);
1241
1242 props->active_mtu = mlx5_mtu_to_ib_mtu(oper_mtu);
1243
1244 err = mlx5_query_port_vl_hw_cap(mdev, &vl_hw_cap, port);
1245 if (err)
1246 goto out;
1247
1248 err = translate_max_vl_num(ibdev, vl_hw_cap,
1249 &props->max_vl_num);
1250 out:
1251 kfree(rep);
1252 return err;
1253 }
1254
1255 int mlx5_ib_query_port(struct ib_device *ibdev, u8 port,
1256 struct ib_port_attr *props)
1257 {
1258 unsigned int count;
1259 int ret;
1260
1261 switch (mlx5_get_vport_access_method(ibdev)) {
1262 case MLX5_VPORT_ACCESS_METHOD_MAD:
1263 ret = mlx5_query_mad_ifc_port(ibdev, port, props);
1264 break;
1265
1266 case MLX5_VPORT_ACCESS_METHOD_HCA:
1267 ret = mlx5_query_hca_port(ibdev, port, props);
1268 break;
1269
1270 case MLX5_VPORT_ACCESS_METHOD_NIC:
1271 ret = mlx5_query_port_roce(ibdev, port, props);
1272 break;
1273
1274 default:
1275 ret = -EINVAL;
1276 }
1277
1278 if (!ret && props) {
1279 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1280 struct mlx5_core_dev *mdev;
1281 bool put_mdev = true;
1282
1283 mdev = mlx5_ib_get_native_port_mdev(dev, port, NULL);
1284 if (!mdev) {
1285 /* If the port isn't affiliated yet query the master.
1286 * The master and slave will have the same values.
1287 */
1288 mdev = dev->mdev;
1289 port = 1;
1290 put_mdev = false;
1291 }
1292 count = mlx5_core_reserved_gids_count(mdev);
1293 if (put_mdev)
1294 mlx5_ib_put_native_port_mdev(dev, port);
1295 props->gid_tbl_len -= count;
1296 }
1297 return ret;
1298 }
1299
1300 static int mlx5_ib_rep_query_port(struct ib_device *ibdev, u8 port,
1301 struct ib_port_attr *props)
1302 {
1303 int ret;
1304
1305 /* Only link layer == ethernet is valid for representors */
1306 ret = mlx5_query_port_roce(ibdev, port, props);
1307 if (ret || !props)
1308 return ret;
1309
1310 /* We don't support GIDS */
1311 props->gid_tbl_len = 0;
1312
1313 return ret;
1314 }
1315
1316 static int mlx5_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
1317 union ib_gid *gid)
1318 {
1319 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1320 struct mlx5_core_dev *mdev = dev->mdev;
1321
1322 switch (mlx5_get_vport_access_method(ibdev)) {
1323 case MLX5_VPORT_ACCESS_METHOD_MAD:
1324 return mlx5_query_mad_ifc_gids(ibdev, port, index, gid);
1325
1326 case MLX5_VPORT_ACCESS_METHOD_HCA:
1327 return mlx5_query_hca_vport_gid(mdev, 0, port, 0, index, gid);
1328
1329 default:
1330 return -EINVAL;
1331 }
1332
1333 }
1334
1335 static int mlx5_query_hca_nic_pkey(struct ib_device *ibdev, u8 port,
1336 u16 index, u16 *pkey)
1337 {
1338 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1339 struct mlx5_core_dev *mdev;
1340 bool put_mdev = true;
1341 u8 mdev_port_num;
1342 int err;
1343
1344 mdev = mlx5_ib_get_native_port_mdev(dev, port, &mdev_port_num);
1345 if (!mdev) {
1346 /* The port isn't affiliated yet, get the PKey from the master
1347 * port. For RoCE the PKey tables will be the same.
1348 */
1349 put_mdev = false;
1350 mdev = dev->mdev;
1351 mdev_port_num = 1;
1352 }
1353
1354 err = mlx5_query_hca_vport_pkey(mdev, 0, mdev_port_num, 0,
1355 index, pkey);
1356 if (put_mdev)
1357 mlx5_ib_put_native_port_mdev(dev, port);
1358
1359 return err;
1360 }
1361
1362 static int mlx5_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
1363 u16 *pkey)
1364 {
1365 switch (mlx5_get_vport_access_method(ibdev)) {
1366 case MLX5_VPORT_ACCESS_METHOD_MAD:
1367 return mlx5_query_mad_ifc_pkey(ibdev, port, index, pkey);
1368
1369 case MLX5_VPORT_ACCESS_METHOD_HCA:
1370 case MLX5_VPORT_ACCESS_METHOD_NIC:
1371 return mlx5_query_hca_nic_pkey(ibdev, port, index, pkey);
1372 default:
1373 return -EINVAL;
1374 }
1375 }
1376
1377 static int mlx5_ib_modify_device(struct ib_device *ibdev, int mask,
1378 struct ib_device_modify *props)
1379 {
1380 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1381 struct mlx5_reg_node_desc in;
1382 struct mlx5_reg_node_desc out;
1383 int err;
1384
1385 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
1386 return -EOPNOTSUPP;
1387
1388 if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
1389 return 0;
1390
1391 /*
1392 * If possible, pass node desc to FW, so it can generate
1393 * a 144 trap. If cmd fails, just ignore.
1394 */
1395 memcpy(&in, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1396 err = mlx5_core_access_reg(dev->mdev, &in, sizeof(in), &out,
1397 sizeof(out), MLX5_REG_NODE_DESC, 0, 1);
1398 if (err)
1399 return err;
1400
1401 memcpy(ibdev->node_desc, props->node_desc, IB_DEVICE_NODE_DESC_MAX);
1402
1403 return err;
1404 }
1405
1406 static int set_port_caps_atomic(struct mlx5_ib_dev *dev, u8 port_num, u32 mask,
1407 u32 value)
1408 {
1409 struct mlx5_hca_vport_context ctx = {};
1410 struct mlx5_core_dev *mdev;
1411 u8 mdev_port_num;
1412 int err;
1413
1414 mdev = mlx5_ib_get_native_port_mdev(dev, port_num, &mdev_port_num);
1415 if (!mdev)
1416 return -ENODEV;
1417
1418 err = mlx5_query_hca_vport_context(mdev, 0, mdev_port_num, 0, &ctx);
1419 if (err)
1420 goto out;
1421
1422 if (~ctx.cap_mask1_perm & mask) {
1423 mlx5_ib_warn(dev, "trying to change bitmask 0x%X but change supported 0x%X\n",
1424 mask, ctx.cap_mask1_perm);
1425 err = -EINVAL;
1426 goto out;
1427 }
1428
1429 ctx.cap_mask1 = value;
1430 ctx.cap_mask1_perm = mask;
1431 err = mlx5_core_modify_hca_vport_context(mdev, 0, mdev_port_num,
1432 0, &ctx);
1433
1434 out:
1435 mlx5_ib_put_native_port_mdev(dev, port_num);
1436
1437 return err;
1438 }
1439
1440 static int mlx5_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
1441 struct ib_port_modify *props)
1442 {
1443 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1444 struct ib_port_attr attr;
1445 u32 tmp;
1446 int err;
1447 u32 change_mask;
1448 u32 value;
1449 bool is_ib = (mlx5_ib_port_link_layer(ibdev, port) ==
1450 IB_LINK_LAYER_INFINIBAND);
1451
1452 /* CM layer calls ib_modify_port() regardless of the link layer. For
1453 * Ethernet ports, qkey violation and Port capabilities are meaningless.
1454 */
1455 if (!is_ib)
1456 return 0;
1457
1458 if (MLX5_CAP_GEN(dev->mdev, ib_virt) && is_ib) {
1459 change_mask = props->clr_port_cap_mask | props->set_port_cap_mask;
1460 value = ~props->clr_port_cap_mask | props->set_port_cap_mask;
1461 return set_port_caps_atomic(dev, port, change_mask, value);
1462 }
1463
1464 mutex_lock(&dev->cap_mask_mutex);
1465
1466 err = ib_query_port(ibdev, port, &attr);
1467 if (err)
1468 goto out;
1469
1470 tmp = (attr.port_cap_flags | props->set_port_cap_mask) &
1471 ~props->clr_port_cap_mask;
1472
1473 err = mlx5_set_port_caps(dev->mdev, port, tmp);
1474
1475 out:
1476 mutex_unlock(&dev->cap_mask_mutex);
1477 return err;
1478 }
1479
1480 static void print_lib_caps(struct mlx5_ib_dev *dev, u64 caps)
1481 {
1482 mlx5_ib_dbg(dev, "MLX5_LIB_CAP_4K_UAR = %s\n",
1483 caps & MLX5_LIB_CAP_4K_UAR ? "y" : "n");
1484 }
1485
1486 static u16 calc_dynamic_bfregs(int uars_per_sys_page)
1487 {
1488 /* Large page with non 4k uar support might limit the dynamic size */
1489 if (uars_per_sys_page == 1 && PAGE_SIZE > 4096)
1490 return MLX5_MIN_DYN_BFREGS;
1491
1492 return MLX5_MAX_DYN_BFREGS;
1493 }
1494
1495 static int calc_total_bfregs(struct mlx5_ib_dev *dev, bool lib_uar_4k,
1496 struct mlx5_ib_alloc_ucontext_req_v2 *req,
1497 struct mlx5_bfreg_info *bfregi)
1498 {
1499 int uars_per_sys_page;
1500 int bfregs_per_sys_page;
1501 int ref_bfregs = req->total_num_bfregs;
1502
1503 if (req->total_num_bfregs == 0)
1504 return -EINVAL;
1505
1506 BUILD_BUG_ON(MLX5_MAX_BFREGS % MLX5_NON_FP_BFREGS_IN_PAGE);
1507 BUILD_BUG_ON(MLX5_MAX_BFREGS < MLX5_NON_FP_BFREGS_IN_PAGE);
1508
1509 if (req->total_num_bfregs > MLX5_MAX_BFREGS)
1510 return -ENOMEM;
1511
1512 uars_per_sys_page = get_uars_per_sys_page(dev, lib_uar_4k);
1513 bfregs_per_sys_page = uars_per_sys_page * MLX5_NON_FP_BFREGS_PER_UAR;
1514 /* This holds the required static allocation asked by the user */
1515 req->total_num_bfregs = ALIGN(req->total_num_bfregs, bfregs_per_sys_page);
1516 if (req->num_low_latency_bfregs > req->total_num_bfregs - 1)
1517 return -EINVAL;
1518
1519 bfregi->num_static_sys_pages = req->total_num_bfregs / bfregs_per_sys_page;
1520 bfregi->num_dyn_bfregs = ALIGN(calc_dynamic_bfregs(uars_per_sys_page), bfregs_per_sys_page);
1521 bfregi->total_num_bfregs = req->total_num_bfregs + bfregi->num_dyn_bfregs;
1522 bfregi->num_sys_pages = bfregi->total_num_bfregs / bfregs_per_sys_page;
1523
1524 mlx5_ib_dbg(dev, "uar_4k: fw support %s, lib support %s, user requested %d bfregs, allocated %d, total bfregs %d, using %d sys pages\n",
1525 MLX5_CAP_GEN(dev->mdev, uar_4k) ? "yes" : "no",
1526 lib_uar_4k ? "yes" : "no", ref_bfregs,
1527 req->total_num_bfregs, bfregi->total_num_bfregs,
1528 bfregi->num_sys_pages);
1529
1530 return 0;
1531 }
1532
1533 static int allocate_uars(struct mlx5_ib_dev *dev, struct mlx5_ib_ucontext *context)
1534 {
1535 struct mlx5_bfreg_info *bfregi;
1536 int err;
1537 int i;
1538
1539 bfregi = &context->bfregi;
1540 for (i = 0; i < bfregi->num_static_sys_pages; i++) {
1541 err = mlx5_cmd_alloc_uar(dev->mdev, &bfregi->sys_pages[i]);
1542 if (err)
1543 goto error;
1544
1545 mlx5_ib_dbg(dev, "allocated uar %d\n", bfregi->sys_pages[i]);
1546 }
1547
1548 for (i = bfregi->num_static_sys_pages; i < bfregi->num_sys_pages; i++)
1549 bfregi->sys_pages[i] = MLX5_IB_INVALID_UAR_INDEX;
1550
1551 return 0;
1552
1553 error:
1554 for (--i; i >= 0; i--)
1555 if (mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]))
1556 mlx5_ib_warn(dev, "failed to free uar %d\n", i);
1557
1558 return err;
1559 }
1560
1561 static void deallocate_uars(struct mlx5_ib_dev *dev,
1562 struct mlx5_ib_ucontext *context)
1563 {
1564 struct mlx5_bfreg_info *bfregi;
1565 int i;
1566
1567 bfregi = &context->bfregi;
1568 for (i = 0; i < bfregi->num_sys_pages; i++)
1569 if (i < bfregi->num_static_sys_pages ||
1570 bfregi->sys_pages[i] != MLX5_IB_INVALID_UAR_INDEX)
1571 mlx5_cmd_free_uar(dev->mdev, bfregi->sys_pages[i]);
1572 }
1573
1574 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1575 {
1576 int err = 0;
1577
1578 mutex_lock(&dev->lb.mutex);
1579 if (td)
1580 dev->lb.user_td++;
1581 if (qp)
1582 dev->lb.qps++;
1583
1584 if (dev->lb.user_td == 2 ||
1585 dev->lb.qps == 1) {
1586 if (!dev->lb.enabled) {
1587 err = mlx5_nic_vport_update_local_lb(dev->mdev, true);
1588 dev->lb.enabled = true;
1589 }
1590 }
1591
1592 mutex_unlock(&dev->lb.mutex);
1593
1594 return err;
1595 }
1596
1597 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp)
1598 {
1599 mutex_lock(&dev->lb.mutex);
1600 if (td)
1601 dev->lb.user_td--;
1602 if (qp)
1603 dev->lb.qps--;
1604
1605 if (dev->lb.user_td == 1 &&
1606 dev->lb.qps == 0) {
1607 if (dev->lb.enabled) {
1608 mlx5_nic_vport_update_local_lb(dev->mdev, false);
1609 dev->lb.enabled = false;
1610 }
1611 }
1612
1613 mutex_unlock(&dev->lb.mutex);
1614 }
1615
1616 static int mlx5_ib_alloc_transport_domain(struct mlx5_ib_dev *dev, u32 *tdn)
1617 {
1618 int err;
1619
1620 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1621 return 0;
1622
1623 err = mlx5_core_alloc_transport_domain(dev->mdev, tdn);
1624 if (err)
1625 return err;
1626
1627 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1628 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1629 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1630 return err;
1631
1632 return mlx5_ib_enable_lb(dev, true, false);
1633 }
1634
1635 static void mlx5_ib_dealloc_transport_domain(struct mlx5_ib_dev *dev, u32 tdn)
1636 {
1637 if (!MLX5_CAP_GEN(dev->mdev, log_max_transport_domain))
1638 return;
1639
1640 mlx5_core_dealloc_transport_domain(dev->mdev, tdn);
1641
1642 if ((MLX5_CAP_GEN(dev->mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH) ||
1643 (!MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) &&
1644 !MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
1645 return;
1646
1647 mlx5_ib_disable_lb(dev, true, false);
1648 }
1649
1650 static struct ib_ucontext *mlx5_ib_alloc_ucontext(struct ib_device *ibdev,
1651 struct ib_udata *udata)
1652 {
1653 struct mlx5_ib_dev *dev = to_mdev(ibdev);
1654 struct mlx5_ib_alloc_ucontext_req_v2 req = {};
1655 struct mlx5_ib_alloc_ucontext_resp resp = {};
1656 struct mlx5_core_dev *mdev = dev->mdev;
1657 struct mlx5_ib_ucontext *context;
1658 struct mlx5_bfreg_info *bfregi;
1659 int ver;
1660 int err;
1661 size_t min_req_v2 = offsetof(struct mlx5_ib_alloc_ucontext_req_v2,
1662 max_cqe_version);
1663 u32 dump_fill_mkey;
1664 bool lib_uar_4k;
1665
1666 if (!dev->ib_active)
1667 return ERR_PTR(-EAGAIN);
1668
1669 if (udata->inlen == sizeof(struct mlx5_ib_alloc_ucontext_req))
1670 ver = 0;
1671 else if (udata->inlen >= min_req_v2)
1672 ver = 2;
1673 else
1674 return ERR_PTR(-EINVAL);
1675
1676 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1677 if (err)
1678 return ERR_PTR(err);
1679
1680 if (req.flags & ~MLX5_IB_ALLOC_UCTX_DEVX)
1681 return ERR_PTR(-EOPNOTSUPP);
1682
1683 if (req.comp_mask || req.reserved0 || req.reserved1 || req.reserved2)
1684 return ERR_PTR(-EOPNOTSUPP);
1685
1686 req.total_num_bfregs = ALIGN(req.total_num_bfregs,
1687 MLX5_NON_FP_BFREGS_PER_UAR);
1688 if (req.num_low_latency_bfregs > req.total_num_bfregs - 1)
1689 return ERR_PTR(-EINVAL);
1690
1691 resp.qp_tab_size = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp);
1692 if (mlx5_core_is_pf(dev->mdev) && MLX5_CAP_GEN(dev->mdev, bf))
1693 resp.bf_reg_size = 1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size);
1694 resp.cache_line_size = cache_line_size();
1695 resp.max_sq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq);
1696 resp.max_rq_desc_sz = MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq);
1697 resp.max_send_wqebb = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1698 resp.max_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz);
1699 resp.max_srq_recv_wr = 1 << MLX5_CAP_GEN(dev->mdev, log_max_srq_sz);
1700 resp.cqe_version = min_t(__u8,
1701 (__u8)MLX5_CAP_GEN(dev->mdev, cqe_version),
1702 req.max_cqe_version);
1703 resp.log_uar_size = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1704 MLX5_ADAPTER_PAGE_SHIFT : PAGE_SHIFT;
1705 resp.num_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1706 MLX5_CAP_GEN(dev->mdev, num_of_uars_per_page) : 1;
1707 resp.response_length = min(offsetof(typeof(resp), response_length) +
1708 sizeof(resp.response_length), udata->outlen);
1709
1710 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_DEVICE) {
1711 if (mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_EGRESS))
1712 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM;
1713 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA)
1714 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_REQ_METADATA;
1715 if (MLX5_CAP_FLOWTABLE(dev->mdev, flow_table_properties_nic_receive.ft_field_support.outer_esp_spi))
1716 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_SPI_STEERING;
1717 if (mlx5_accel_ipsec_device_caps(dev->mdev) & MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN)
1718 resp.flow_action_flags |= MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_TX_IV_IS_ESN;
1719 /* MLX5_USER_ALLOC_UCONTEXT_FLOW_ACTION_FLAGS_ESP_AES_GCM_FULL_OFFLOAD is currently always 0 */
1720 }
1721
1722 context = kzalloc(sizeof(*context), GFP_KERNEL);
1723 if (!context)
1724 return ERR_PTR(-ENOMEM);
1725
1726 lib_uar_4k = req.lib_caps & MLX5_LIB_CAP_4K_UAR;
1727 bfregi = &context->bfregi;
1728
1729 /* updates req->total_num_bfregs */
1730 err = calc_total_bfregs(dev, lib_uar_4k, &req, bfregi);
1731 if (err)
1732 goto out_ctx;
1733
1734 mutex_init(&bfregi->lock);
1735 bfregi->lib_uar_4k = lib_uar_4k;
1736 bfregi->count = kcalloc(bfregi->total_num_bfregs, sizeof(*bfregi->count),
1737 GFP_KERNEL);
1738 if (!bfregi->count) {
1739 err = -ENOMEM;
1740 goto out_ctx;
1741 }
1742
1743 bfregi->sys_pages = kcalloc(bfregi->num_sys_pages,
1744 sizeof(*bfregi->sys_pages),
1745 GFP_KERNEL);
1746 if (!bfregi->sys_pages) {
1747 err = -ENOMEM;
1748 goto out_count;
1749 }
1750
1751 err = allocate_uars(dev, context);
1752 if (err)
1753 goto out_sys_pages;
1754
1755 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1756 context->ibucontext.invalidate_range = &mlx5_ib_invalidate_range;
1757 #endif
1758
1759 err = mlx5_ib_alloc_transport_domain(dev, &context->tdn);
1760 if (err)
1761 goto out_uars;
1762
1763 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX) {
1764 /* Block DEVX on Infiniband as of SELinux */
1765 if (mlx5_ib_port_link_layer(ibdev, 1) != IB_LINK_LAYER_ETHERNET) {
1766 err = -EPERM;
1767 goto out_td;
1768 }
1769
1770 err = mlx5_ib_devx_create(dev, context);
1771 if (err)
1772 goto out_td;
1773 }
1774
1775 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1776 err = mlx5_cmd_dump_fill_mkey(dev->mdev, &dump_fill_mkey);
1777 if (err)
1778 goto out_mdev;
1779 }
1780
1781 INIT_LIST_HEAD(&context->db_page_list);
1782 mutex_init(&context->db_page_mutex);
1783
1784 resp.tot_bfregs = req.total_num_bfregs;
1785 resp.num_ports = dev->num_ports;
1786
1787 if (field_avail(typeof(resp), cqe_version, udata->outlen))
1788 resp.response_length += sizeof(resp.cqe_version);
1789
1790 if (field_avail(typeof(resp), cmds_supp_uhw, udata->outlen)) {
1791 resp.cmds_supp_uhw |= MLX5_USER_CMDS_SUPP_UHW_QUERY_DEVICE |
1792 MLX5_USER_CMDS_SUPP_UHW_CREATE_AH;
1793 resp.response_length += sizeof(resp.cmds_supp_uhw);
1794 }
1795
1796 if (field_avail(typeof(resp), eth_min_inline, udata->outlen)) {
1797 if (mlx5_ib_port_link_layer(ibdev, 1) == IB_LINK_LAYER_ETHERNET) {
1798 mlx5_query_min_inline(dev->mdev, &resp.eth_min_inline);
1799 resp.eth_min_inline++;
1800 }
1801 resp.response_length += sizeof(resp.eth_min_inline);
1802 }
1803
1804 if (field_avail(typeof(resp), clock_info_versions, udata->outlen)) {
1805 if (mdev->clock_info)
1806 resp.clock_info_versions = BIT(MLX5_IB_CLOCK_INFO_V1);
1807 resp.response_length += sizeof(resp.clock_info_versions);
1808 }
1809
1810 /*
1811 * We don't want to expose information from the PCI bar that is located
1812 * after 4096 bytes, so if the arch only supports larger pages, let's
1813 * pretend we don't support reading the HCA's core clock. This is also
1814 * forced by mmap function.
1815 */
1816 if (field_avail(typeof(resp), hca_core_clock_offset, udata->outlen)) {
1817 if (PAGE_SIZE <= 4096) {
1818 resp.comp_mask |=
1819 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET;
1820 resp.hca_core_clock_offset =
1821 offsetof(struct mlx5_init_seg, internal_timer_h) % PAGE_SIZE;
1822 }
1823 resp.response_length += sizeof(resp.hca_core_clock_offset);
1824 }
1825
1826 if (field_avail(typeof(resp), log_uar_size, udata->outlen))
1827 resp.response_length += sizeof(resp.log_uar_size);
1828
1829 if (field_avail(typeof(resp), num_uars_per_page, udata->outlen))
1830 resp.response_length += sizeof(resp.num_uars_per_page);
1831
1832 if (field_avail(typeof(resp), num_dyn_bfregs, udata->outlen)) {
1833 resp.num_dyn_bfregs = bfregi->num_dyn_bfregs;
1834 resp.response_length += sizeof(resp.num_dyn_bfregs);
1835 }
1836
1837 if (field_avail(typeof(resp), dump_fill_mkey, udata->outlen)) {
1838 if (MLX5_CAP_GEN(dev->mdev, dump_fill_mkey)) {
1839 resp.dump_fill_mkey = dump_fill_mkey;
1840 resp.comp_mask |=
1841 MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY;
1842 }
1843 resp.response_length += sizeof(resp.dump_fill_mkey);
1844 }
1845
1846 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1847 if (err)
1848 goto out_mdev;
1849
1850 bfregi->ver = ver;
1851 bfregi->num_low_latency_bfregs = req.num_low_latency_bfregs;
1852 context->cqe_version = resp.cqe_version;
1853 context->lib_caps = req.lib_caps;
1854 print_lib_caps(dev, context->lib_caps);
1855
1856 if (mlx5_lag_is_active(dev->mdev)) {
1857 u8 port = mlx5_core_native_port_num(dev->mdev);
1858
1859 atomic_set(&context->tx_port_affinity,
1860 atomic_add_return(
1861 1, &dev->roce[port].tx_port_affinity));
1862 }
1863
1864 return &context->ibucontext;
1865
1866 out_mdev:
1867 if (req.flags & MLX5_IB_ALLOC_UCTX_DEVX)
1868 mlx5_ib_devx_destroy(dev, context);
1869 out_td:
1870 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1871
1872 out_uars:
1873 deallocate_uars(dev, context);
1874
1875 out_sys_pages:
1876 kfree(bfregi->sys_pages);
1877
1878 out_count:
1879 kfree(bfregi->count);
1880
1881 out_ctx:
1882 kfree(context);
1883
1884 return ERR_PTR(err);
1885 }
1886
1887 static int mlx5_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
1888 {
1889 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
1890 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
1891 struct mlx5_bfreg_info *bfregi;
1892
1893 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1894 /* All umem's must be destroyed before destroying the ucontext. */
1895 mutex_lock(&ibcontext->per_mm_list_lock);
1896 WARN_ON(!list_empty(&ibcontext->per_mm_list));
1897 mutex_unlock(&ibcontext->per_mm_list_lock);
1898 #endif
1899
1900 if (context->devx_uid)
1901 mlx5_ib_devx_destroy(dev, context);
1902
1903 bfregi = &context->bfregi;
1904 mlx5_ib_dealloc_transport_domain(dev, context->tdn);
1905
1906 deallocate_uars(dev, context);
1907 kfree(bfregi->sys_pages);
1908 kfree(bfregi->count);
1909 kfree(context);
1910
1911 return 0;
1912 }
1913
1914 static phys_addr_t uar_index2pfn(struct mlx5_ib_dev *dev,
1915 int uar_idx)
1916 {
1917 int fw_uars_per_page;
1918
1919 fw_uars_per_page = MLX5_CAP_GEN(dev->mdev, uar_4k) ? MLX5_UARS_IN_PAGE : 1;
1920
1921 return (pci_resource_start(dev->mdev->pdev, 0) >> PAGE_SHIFT) + uar_idx / fw_uars_per_page;
1922 }
1923
1924 static int get_command(unsigned long offset)
1925 {
1926 return (offset >> MLX5_IB_MMAP_CMD_SHIFT) & MLX5_IB_MMAP_CMD_MASK;
1927 }
1928
1929 static int get_arg(unsigned long offset)
1930 {
1931 return offset & ((1 << MLX5_IB_MMAP_CMD_SHIFT) - 1);
1932 }
1933
1934 static int get_index(unsigned long offset)
1935 {
1936 return get_arg(offset);
1937 }
1938
1939 /* Index resides in an extra byte to enable larger values than 255 */
1940 static int get_extended_index(unsigned long offset)
1941 {
1942 return get_arg(offset) | ((offset >> 16) & 0xff) << 8;
1943 }
1944
1945
1946 static void mlx5_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
1947 {
1948 }
1949
1950 static inline char *mmap_cmd2str(enum mlx5_ib_mmap_cmd cmd)
1951 {
1952 switch (cmd) {
1953 case MLX5_IB_MMAP_WC_PAGE:
1954 return "WC";
1955 case MLX5_IB_MMAP_REGULAR_PAGE:
1956 return "best effort WC";
1957 case MLX5_IB_MMAP_NC_PAGE:
1958 return "NC";
1959 case MLX5_IB_MMAP_DEVICE_MEM:
1960 return "Device Memory";
1961 default:
1962 return NULL;
1963 }
1964 }
1965
1966 static int mlx5_ib_mmap_clock_info_page(struct mlx5_ib_dev *dev,
1967 struct vm_area_struct *vma,
1968 struct mlx5_ib_ucontext *context)
1969 {
1970 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
1971 return -EINVAL;
1972
1973 if (get_index(vma->vm_pgoff) != MLX5_IB_CLOCK_INFO_V1)
1974 return -EOPNOTSUPP;
1975
1976 if (vma->vm_flags & VM_WRITE)
1977 return -EPERM;
1978
1979 if (!dev->mdev->clock_info_page)
1980 return -EOPNOTSUPP;
1981
1982 return rdma_user_mmap_page(&context->ibucontext, vma,
1983 dev->mdev->clock_info_page, PAGE_SIZE);
1984 }
1985
1986 static int uar_mmap(struct mlx5_ib_dev *dev, enum mlx5_ib_mmap_cmd cmd,
1987 struct vm_area_struct *vma,
1988 struct mlx5_ib_ucontext *context)
1989 {
1990 struct mlx5_bfreg_info *bfregi = &context->bfregi;
1991 int err;
1992 unsigned long idx;
1993 phys_addr_t pfn;
1994 pgprot_t prot;
1995 u32 bfreg_dyn_idx = 0;
1996 u32 uar_index;
1997 int dyn_uar = (cmd == MLX5_IB_MMAP_ALLOC_WC);
1998 int max_valid_idx = dyn_uar ? bfregi->num_sys_pages :
1999 bfregi->num_static_sys_pages;
2000
2001 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2002 return -EINVAL;
2003
2004 if (dyn_uar)
2005 idx = get_extended_index(vma->vm_pgoff) + bfregi->num_static_sys_pages;
2006 else
2007 idx = get_index(vma->vm_pgoff);
2008
2009 if (idx >= max_valid_idx) {
2010 mlx5_ib_warn(dev, "invalid uar index %lu, max=%d\n",
2011 idx, max_valid_idx);
2012 return -EINVAL;
2013 }
2014
2015 switch (cmd) {
2016 case MLX5_IB_MMAP_WC_PAGE:
2017 case MLX5_IB_MMAP_ALLOC_WC:
2018 /* Some architectures don't support WC memory */
2019 #if defined(CONFIG_X86)
2020 if (!pat_enabled())
2021 return -EPERM;
2022 #elif !(defined(CONFIG_PPC) || (defined(CONFIG_ARM) && defined(CONFIG_MMU)))
2023 return -EPERM;
2024 #endif
2025 /* fall through */
2026 case MLX5_IB_MMAP_REGULAR_PAGE:
2027 /* For MLX5_IB_MMAP_REGULAR_PAGE do the best effort to get WC */
2028 prot = pgprot_writecombine(vma->vm_page_prot);
2029 break;
2030 case MLX5_IB_MMAP_NC_PAGE:
2031 prot = pgprot_noncached(vma->vm_page_prot);
2032 break;
2033 default:
2034 return -EINVAL;
2035 }
2036
2037 if (dyn_uar) {
2038 int uars_per_page;
2039
2040 uars_per_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k);
2041 bfreg_dyn_idx = idx * (uars_per_page * MLX5_NON_FP_BFREGS_PER_UAR);
2042 if (bfreg_dyn_idx >= bfregi->total_num_bfregs) {
2043 mlx5_ib_warn(dev, "invalid bfreg_dyn_idx %u, max=%u\n",
2044 bfreg_dyn_idx, bfregi->total_num_bfregs);
2045 return -EINVAL;
2046 }
2047
2048 mutex_lock(&bfregi->lock);
2049 /* Fail if uar already allocated, first bfreg index of each
2050 * page holds its count.
2051 */
2052 if (bfregi->count[bfreg_dyn_idx]) {
2053 mlx5_ib_warn(dev, "wrong offset, idx %lu is busy, bfregn=%u\n", idx, bfreg_dyn_idx);
2054 mutex_unlock(&bfregi->lock);
2055 return -EINVAL;
2056 }
2057
2058 bfregi->count[bfreg_dyn_idx]++;
2059 mutex_unlock(&bfregi->lock);
2060
2061 err = mlx5_cmd_alloc_uar(dev->mdev, &uar_index);
2062 if (err) {
2063 mlx5_ib_warn(dev, "UAR alloc failed\n");
2064 goto free_bfreg;
2065 }
2066 } else {
2067 uar_index = bfregi->sys_pages[idx];
2068 }
2069
2070 pfn = uar_index2pfn(dev, uar_index);
2071 mlx5_ib_dbg(dev, "uar idx 0x%lx, pfn %pa\n", idx, &pfn);
2072
2073 err = rdma_user_mmap_io(&context->ibucontext, vma, pfn, PAGE_SIZE,
2074 prot);
2075 if (err) {
2076 mlx5_ib_err(dev,
2077 "rdma_user_mmap_io failed with error=%d, mmap_cmd=%s\n",
2078 err, mmap_cmd2str(cmd));
2079 goto err;
2080 }
2081
2082 if (dyn_uar)
2083 bfregi->sys_pages[idx] = uar_index;
2084 return 0;
2085
2086 err:
2087 if (!dyn_uar)
2088 return err;
2089
2090 mlx5_cmd_free_uar(dev->mdev, idx);
2091
2092 free_bfreg:
2093 mlx5_ib_free_bfreg(dev, bfregi, bfreg_dyn_idx);
2094
2095 return err;
2096 }
2097
2098 static int dm_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
2099 {
2100 struct mlx5_ib_ucontext *mctx = to_mucontext(context);
2101 struct mlx5_ib_dev *dev = to_mdev(context->device);
2102 u16 page_idx = get_extended_index(vma->vm_pgoff);
2103 size_t map_size = vma->vm_end - vma->vm_start;
2104 u32 npages = map_size >> PAGE_SHIFT;
2105 phys_addr_t pfn;
2106
2107 if (find_next_zero_bit(mctx->dm_pages, page_idx + npages, page_idx) !=
2108 page_idx + npages)
2109 return -EINVAL;
2110
2111 pfn = ((pci_resource_start(dev->mdev->pdev, 0) +
2112 MLX5_CAP64_DEV_MEM(dev->mdev, memic_bar_start_addr)) >>
2113 PAGE_SHIFT) +
2114 page_idx;
2115 return rdma_user_mmap_io(context, vma, pfn, map_size,
2116 pgprot_writecombine(vma->vm_page_prot));
2117 }
2118
2119 static int mlx5_ib_mmap(struct ib_ucontext *ibcontext, struct vm_area_struct *vma)
2120 {
2121 struct mlx5_ib_ucontext *context = to_mucontext(ibcontext);
2122 struct mlx5_ib_dev *dev = to_mdev(ibcontext->device);
2123 unsigned long command;
2124 phys_addr_t pfn;
2125
2126 command = get_command(vma->vm_pgoff);
2127 switch (command) {
2128 case MLX5_IB_MMAP_WC_PAGE:
2129 case MLX5_IB_MMAP_NC_PAGE:
2130 case MLX5_IB_MMAP_REGULAR_PAGE:
2131 case MLX5_IB_MMAP_ALLOC_WC:
2132 return uar_mmap(dev, command, vma, context);
2133
2134 case MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES:
2135 return -ENOSYS;
2136
2137 case MLX5_IB_MMAP_CORE_CLOCK:
2138 if (vma->vm_end - vma->vm_start != PAGE_SIZE)
2139 return -EINVAL;
2140
2141 if (vma->vm_flags & VM_WRITE)
2142 return -EPERM;
2143
2144 /* Don't expose to user-space information it shouldn't have */
2145 if (PAGE_SIZE > 4096)
2146 return -EOPNOTSUPP;
2147
2148 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
2149 pfn = (dev->mdev->iseg_base +
2150 offsetof(struct mlx5_init_seg, internal_timer_h)) >>
2151 PAGE_SHIFT;
2152 if (io_remap_pfn_range(vma, vma->vm_start, pfn,
2153 PAGE_SIZE, vma->vm_page_prot))
2154 return -EAGAIN;
2155 break;
2156 case MLX5_IB_MMAP_CLOCK_INFO:
2157 return mlx5_ib_mmap_clock_info_page(dev, vma, context);
2158
2159 case MLX5_IB_MMAP_DEVICE_MEM:
2160 return dm_mmap(ibcontext, vma);
2161
2162 default:
2163 return -EINVAL;
2164 }
2165
2166 return 0;
2167 }
2168
2169 struct ib_dm *mlx5_ib_alloc_dm(struct ib_device *ibdev,
2170 struct ib_ucontext *context,
2171 struct ib_dm_alloc_attr *attr,
2172 struct uverbs_attr_bundle *attrs)
2173 {
2174 u64 act_size = roundup(attr->length, MLX5_MEMIC_BASE_SIZE);
2175 struct mlx5_memic *memic = &to_mdev(ibdev)->memic;
2176 phys_addr_t memic_addr;
2177 struct mlx5_ib_dm *dm;
2178 u64 start_offset;
2179 u32 page_idx;
2180 int err;
2181
2182 dm = kzalloc(sizeof(*dm), GFP_KERNEL);
2183 if (!dm)
2184 return ERR_PTR(-ENOMEM);
2185
2186 mlx5_ib_dbg(to_mdev(ibdev), "alloc_memic req: user_length=0x%llx act_length=0x%llx log_alignment=%d\n",
2187 attr->length, act_size, attr->alignment);
2188
2189 err = mlx5_cmd_alloc_memic(memic, &memic_addr,
2190 act_size, attr->alignment);
2191 if (err)
2192 goto err_free;
2193
2194 start_offset = memic_addr & ~PAGE_MASK;
2195 page_idx = (memic_addr - pci_resource_start(memic->dev->pdev, 0) -
2196 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2197 PAGE_SHIFT;
2198
2199 err = uverbs_copy_to(attrs,
2200 MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
2201 &start_offset, sizeof(start_offset));
2202 if (err)
2203 goto err_dealloc;
2204
2205 err = uverbs_copy_to(attrs,
2206 MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
2207 &page_idx, sizeof(page_idx));
2208 if (err)
2209 goto err_dealloc;
2210
2211 bitmap_set(to_mucontext(context)->dm_pages, page_idx,
2212 DIV_ROUND_UP(act_size, PAGE_SIZE));
2213
2214 dm->dev_addr = memic_addr;
2215
2216 return &dm->ibdm;
2217
2218 err_dealloc:
2219 mlx5_cmd_dealloc_memic(memic, memic_addr,
2220 act_size);
2221 err_free:
2222 kfree(dm);
2223 return ERR_PTR(err);
2224 }
2225
2226 int mlx5_ib_dealloc_dm(struct ib_dm *ibdm)
2227 {
2228 struct mlx5_memic *memic = &to_mdev(ibdm->device)->memic;
2229 struct mlx5_ib_dm *dm = to_mdm(ibdm);
2230 u64 act_size = roundup(dm->ibdm.length, MLX5_MEMIC_BASE_SIZE);
2231 u32 page_idx;
2232 int ret;
2233
2234 ret = mlx5_cmd_dealloc_memic(memic, dm->dev_addr, act_size);
2235 if (ret)
2236 return ret;
2237
2238 page_idx = (dm->dev_addr - pci_resource_start(memic->dev->pdev, 0) -
2239 MLX5_CAP64_DEV_MEM(memic->dev, memic_bar_start_addr)) >>
2240 PAGE_SHIFT;
2241 bitmap_clear(to_mucontext(ibdm->uobject->context)->dm_pages,
2242 page_idx,
2243 DIV_ROUND_UP(act_size, PAGE_SIZE));
2244
2245 kfree(dm);
2246
2247 return 0;
2248 }
2249
2250 static struct ib_pd *mlx5_ib_alloc_pd(struct ib_device *ibdev,
2251 struct ib_ucontext *context,
2252 struct ib_udata *udata)
2253 {
2254 struct mlx5_ib_alloc_pd_resp resp;
2255 struct mlx5_ib_pd *pd;
2256 int err;
2257 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {};
2258 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {};
2259 u16 uid = 0;
2260
2261 pd = kmalloc(sizeof(*pd), GFP_KERNEL);
2262 if (!pd)
2263 return ERR_PTR(-ENOMEM);
2264
2265 MLX5_SET(alloc_pd_in, in, opcode, MLX5_CMD_OP_ALLOC_PD);
2266 MLX5_SET(alloc_pd_in, in, uid, uid);
2267 err = mlx5_cmd_exec(to_mdev(ibdev)->mdev, in, sizeof(in),
2268 out, sizeof(out));
2269 if (err) {
2270 kfree(pd);
2271 return ERR_PTR(err);
2272 }
2273
2274 pd->pdn = MLX5_GET(alloc_pd_out, out, pd);
2275 pd->uid = uid;
2276 if (context) {
2277 resp.pdn = pd->pdn;
2278 if (ib_copy_to_udata(udata, &resp, sizeof(resp))) {
2279 mlx5_cmd_dealloc_pd(to_mdev(ibdev)->mdev, pd->pdn, uid);
2280 kfree(pd);
2281 return ERR_PTR(-EFAULT);
2282 }
2283 }
2284
2285 return &pd->ibpd;
2286 }
2287
2288 static int mlx5_ib_dealloc_pd(struct ib_pd *pd)
2289 {
2290 struct mlx5_ib_dev *mdev = to_mdev(pd->device);
2291 struct mlx5_ib_pd *mpd = to_mpd(pd);
2292
2293 mlx5_cmd_dealloc_pd(mdev->mdev, mpd->pdn, mpd->uid);
2294 kfree(mpd);
2295
2296 return 0;
2297 }
2298
2299 enum {
2300 MATCH_CRITERIA_ENABLE_OUTER_BIT,
2301 MATCH_CRITERIA_ENABLE_MISC_BIT,
2302 MATCH_CRITERIA_ENABLE_INNER_BIT,
2303 MATCH_CRITERIA_ENABLE_MISC2_BIT
2304 };
2305
2306 #define HEADER_IS_ZERO(match_criteria, headers) \
2307 !(memchr_inv(MLX5_ADDR_OF(fte_match_param, match_criteria, headers), \
2308 0, MLX5_FLD_SZ_BYTES(fte_match_param, headers))) \
2309
2310 static u8 get_match_criteria_enable(u32 *match_criteria)
2311 {
2312 u8 match_criteria_enable;
2313
2314 match_criteria_enable =
2315 (!HEADER_IS_ZERO(match_criteria, outer_headers)) <<
2316 MATCH_CRITERIA_ENABLE_OUTER_BIT;
2317 match_criteria_enable |=
2318 (!HEADER_IS_ZERO(match_criteria, misc_parameters)) <<
2319 MATCH_CRITERIA_ENABLE_MISC_BIT;
2320 match_criteria_enable |=
2321 (!HEADER_IS_ZERO(match_criteria, inner_headers)) <<
2322 MATCH_CRITERIA_ENABLE_INNER_BIT;
2323 match_criteria_enable |=
2324 (!HEADER_IS_ZERO(match_criteria, misc_parameters_2)) <<
2325 MATCH_CRITERIA_ENABLE_MISC2_BIT;
2326
2327 return match_criteria_enable;
2328 }
2329
2330 static void set_proto(void *outer_c, void *outer_v, u8 mask, u8 val)
2331 {
2332 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_protocol, mask);
2333 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_protocol, val);
2334 }
2335
2336 static void set_flow_label(void *misc_c, void *misc_v, u32 mask, u32 val,
2337 bool inner)
2338 {
2339 if (inner) {
2340 MLX5_SET(fte_match_set_misc,
2341 misc_c, inner_ipv6_flow_label, mask);
2342 MLX5_SET(fte_match_set_misc,
2343 misc_v, inner_ipv6_flow_label, val);
2344 } else {
2345 MLX5_SET(fte_match_set_misc,
2346 misc_c, outer_ipv6_flow_label, mask);
2347 MLX5_SET(fte_match_set_misc,
2348 misc_v, outer_ipv6_flow_label, val);
2349 }
2350 }
2351
2352 static void set_tos(void *outer_c, void *outer_v, u8 mask, u8 val)
2353 {
2354 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_ecn, mask);
2355 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_ecn, val);
2356 MLX5_SET(fte_match_set_lyr_2_4, outer_c, ip_dscp, mask >> 2);
2357 MLX5_SET(fte_match_set_lyr_2_4, outer_v, ip_dscp, val >> 2);
2358 }
2359
2360 static int check_mpls_supp_fields(u32 field_support, const __be32 *set_mask)
2361 {
2362 if (MLX5_GET(fte_match_mpls, set_mask, mpls_label) &&
2363 !(field_support & MLX5_FIELD_SUPPORT_MPLS_LABEL))
2364 return -EOPNOTSUPP;
2365
2366 if (MLX5_GET(fte_match_mpls, set_mask, mpls_exp) &&
2367 !(field_support & MLX5_FIELD_SUPPORT_MPLS_EXP))
2368 return -EOPNOTSUPP;
2369
2370 if (MLX5_GET(fte_match_mpls, set_mask, mpls_s_bos) &&
2371 !(field_support & MLX5_FIELD_SUPPORT_MPLS_S_BOS))
2372 return -EOPNOTSUPP;
2373
2374 if (MLX5_GET(fte_match_mpls, set_mask, mpls_ttl) &&
2375 !(field_support & MLX5_FIELD_SUPPORT_MPLS_TTL))
2376 return -EOPNOTSUPP;
2377
2378 return 0;
2379 }
2380
2381 #define LAST_ETH_FIELD vlan_tag
2382 #define LAST_IB_FIELD sl
2383 #define LAST_IPV4_FIELD tos
2384 #define LAST_IPV6_FIELD traffic_class
2385 #define LAST_TCP_UDP_FIELD src_port
2386 #define LAST_TUNNEL_FIELD tunnel_id
2387 #define LAST_FLOW_TAG_FIELD tag_id
2388 #define LAST_DROP_FIELD size
2389 #define LAST_COUNTERS_FIELD counters
2390
2391 /* Field is the last supported field */
2392 #define FIELDS_NOT_SUPPORTED(filter, field)\
2393 memchr_inv((void *)&filter.field +\
2394 sizeof(filter.field), 0,\
2395 sizeof(filter) -\
2396 offsetof(typeof(filter), field) -\
2397 sizeof(filter.field))
2398
2399 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
2400 bool is_egress,
2401 struct mlx5_flow_act *action)
2402 {
2403
2404 switch (maction->ib_action.type) {
2405 case IB_FLOW_ACTION_ESP:
2406 if (action->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2407 MLX5_FLOW_CONTEXT_ACTION_DECRYPT))
2408 return -EINVAL;
2409 /* Currently only AES_GCM keymat is supported by the driver */
2410 action->esp_id = (uintptr_t)maction->esp_aes_gcm.ctx;
2411 action->action |= is_egress ?
2412 MLX5_FLOW_CONTEXT_ACTION_ENCRYPT :
2413 MLX5_FLOW_CONTEXT_ACTION_DECRYPT;
2414 return 0;
2415 case IB_FLOW_ACTION_UNSPECIFIED:
2416 if (maction->flow_action_raw.sub_type ==
2417 MLX5_IB_FLOW_ACTION_MODIFY_HEADER) {
2418 if (action->action & MLX5_FLOW_CONTEXT_ACTION_MOD_HDR)
2419 return -EINVAL;
2420 action->action |= MLX5_FLOW_CONTEXT_ACTION_MOD_HDR;
2421 action->modify_id = maction->flow_action_raw.action_id;
2422 return 0;
2423 }
2424 if (maction->flow_action_raw.sub_type ==
2425 MLX5_IB_FLOW_ACTION_DECAP) {
2426 if (action->action & MLX5_FLOW_CONTEXT_ACTION_DECAP)
2427 return -EINVAL;
2428 action->action |= MLX5_FLOW_CONTEXT_ACTION_DECAP;
2429 return 0;
2430 }
2431 if (maction->flow_action_raw.sub_type ==
2432 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT) {
2433 if (action->action &
2434 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT)
2435 return -EINVAL;
2436 action->action |=
2437 MLX5_FLOW_CONTEXT_ACTION_PACKET_REFORMAT;
2438 action->reformat_id =
2439 maction->flow_action_raw.action_id;
2440 return 0;
2441 }
2442 /* fall through */
2443 default:
2444 return -EOPNOTSUPP;
2445 }
2446 }
2447
2448 static int parse_flow_attr(struct mlx5_core_dev *mdev, u32 *match_c,
2449 u32 *match_v, const union ib_flow_spec *ib_spec,
2450 const struct ib_flow_attr *flow_attr,
2451 struct mlx5_flow_act *action, u32 prev_type)
2452 {
2453 void *misc_params_c = MLX5_ADDR_OF(fte_match_param, match_c,
2454 misc_parameters);
2455 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, match_v,
2456 misc_parameters);
2457 void *misc_params2_c = MLX5_ADDR_OF(fte_match_param, match_c,
2458 misc_parameters_2);
2459 void *misc_params2_v = MLX5_ADDR_OF(fte_match_param, match_v,
2460 misc_parameters_2);
2461 void *headers_c;
2462 void *headers_v;
2463 int match_ipv;
2464 int ret;
2465
2466 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2467 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2468 inner_headers);
2469 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2470 inner_headers);
2471 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2472 ft_field_support.inner_ip_version);
2473 } else {
2474 headers_c = MLX5_ADDR_OF(fte_match_param, match_c,
2475 outer_headers);
2476 headers_v = MLX5_ADDR_OF(fte_match_param, match_v,
2477 outer_headers);
2478 match_ipv = MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2479 ft_field_support.outer_ip_version);
2480 }
2481
2482 switch (ib_spec->type & ~IB_FLOW_SPEC_INNER) {
2483 case IB_FLOW_SPEC_ETH:
2484 if (FIELDS_NOT_SUPPORTED(ib_spec->eth.mask, LAST_ETH_FIELD))
2485 return -EOPNOTSUPP;
2486
2487 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2488 dmac_47_16),
2489 ib_spec->eth.mask.dst_mac);
2490 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2491 dmac_47_16),
2492 ib_spec->eth.val.dst_mac);
2493
2494 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2495 smac_47_16),
2496 ib_spec->eth.mask.src_mac);
2497 ether_addr_copy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2498 smac_47_16),
2499 ib_spec->eth.val.src_mac);
2500
2501 if (ib_spec->eth.mask.vlan_tag) {
2502 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2503 cvlan_tag, 1);
2504 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2505 cvlan_tag, 1);
2506
2507 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2508 first_vid, ntohs(ib_spec->eth.mask.vlan_tag));
2509 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2510 first_vid, ntohs(ib_spec->eth.val.vlan_tag));
2511
2512 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2513 first_cfi,
2514 ntohs(ib_spec->eth.mask.vlan_tag) >> 12);
2515 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2516 first_cfi,
2517 ntohs(ib_spec->eth.val.vlan_tag) >> 12);
2518
2519 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2520 first_prio,
2521 ntohs(ib_spec->eth.mask.vlan_tag) >> 13);
2522 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2523 first_prio,
2524 ntohs(ib_spec->eth.val.vlan_tag) >> 13);
2525 }
2526 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2527 ethertype, ntohs(ib_spec->eth.mask.ether_type));
2528 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2529 ethertype, ntohs(ib_spec->eth.val.ether_type));
2530 break;
2531 case IB_FLOW_SPEC_IPV4:
2532 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv4.mask, LAST_IPV4_FIELD))
2533 return -EOPNOTSUPP;
2534
2535 if (match_ipv) {
2536 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2537 ip_version, 0xf);
2538 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2539 ip_version, MLX5_FS_IPV4_VERSION);
2540 } else {
2541 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2542 ethertype, 0xffff);
2543 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2544 ethertype, ETH_P_IP);
2545 }
2546
2547 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2548 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2549 &ib_spec->ipv4.mask.src_ip,
2550 sizeof(ib_spec->ipv4.mask.src_ip));
2551 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2552 src_ipv4_src_ipv6.ipv4_layout.ipv4),
2553 &ib_spec->ipv4.val.src_ip,
2554 sizeof(ib_spec->ipv4.val.src_ip));
2555 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2556 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2557 &ib_spec->ipv4.mask.dst_ip,
2558 sizeof(ib_spec->ipv4.mask.dst_ip));
2559 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2560 dst_ipv4_dst_ipv6.ipv4_layout.ipv4),
2561 &ib_spec->ipv4.val.dst_ip,
2562 sizeof(ib_spec->ipv4.val.dst_ip));
2563
2564 set_tos(headers_c, headers_v,
2565 ib_spec->ipv4.mask.tos, ib_spec->ipv4.val.tos);
2566
2567 set_proto(headers_c, headers_v,
2568 ib_spec->ipv4.mask.proto, ib_spec->ipv4.val.proto);
2569 break;
2570 case IB_FLOW_SPEC_IPV6:
2571 if (FIELDS_NOT_SUPPORTED(ib_spec->ipv6.mask, LAST_IPV6_FIELD))
2572 return -EOPNOTSUPP;
2573
2574 if (match_ipv) {
2575 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2576 ip_version, 0xf);
2577 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2578 ip_version, MLX5_FS_IPV6_VERSION);
2579 } else {
2580 MLX5_SET(fte_match_set_lyr_2_4, headers_c,
2581 ethertype, 0xffff);
2582 MLX5_SET(fte_match_set_lyr_2_4, headers_v,
2583 ethertype, ETH_P_IPV6);
2584 }
2585
2586 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2587 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2588 &ib_spec->ipv6.mask.src_ip,
2589 sizeof(ib_spec->ipv6.mask.src_ip));
2590 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2591 src_ipv4_src_ipv6.ipv6_layout.ipv6),
2592 &ib_spec->ipv6.val.src_ip,
2593 sizeof(ib_spec->ipv6.val.src_ip));
2594 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_c,
2595 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2596 &ib_spec->ipv6.mask.dst_ip,
2597 sizeof(ib_spec->ipv6.mask.dst_ip));
2598 memcpy(MLX5_ADDR_OF(fte_match_set_lyr_2_4, headers_v,
2599 dst_ipv4_dst_ipv6.ipv6_layout.ipv6),
2600 &ib_spec->ipv6.val.dst_ip,
2601 sizeof(ib_spec->ipv6.val.dst_ip));
2602
2603 set_tos(headers_c, headers_v,
2604 ib_spec->ipv6.mask.traffic_class,
2605 ib_spec->ipv6.val.traffic_class);
2606
2607 set_proto(headers_c, headers_v,
2608 ib_spec->ipv6.mask.next_hdr,
2609 ib_spec->ipv6.val.next_hdr);
2610
2611 set_flow_label(misc_params_c, misc_params_v,
2612 ntohl(ib_spec->ipv6.mask.flow_label),
2613 ntohl(ib_spec->ipv6.val.flow_label),
2614 ib_spec->type & IB_FLOW_SPEC_INNER);
2615 break;
2616 case IB_FLOW_SPEC_ESP:
2617 if (ib_spec->esp.mask.seq)
2618 return -EOPNOTSUPP;
2619
2620 MLX5_SET(fte_match_set_misc, misc_params_c, outer_esp_spi,
2621 ntohl(ib_spec->esp.mask.spi));
2622 MLX5_SET(fte_match_set_misc, misc_params_v, outer_esp_spi,
2623 ntohl(ib_spec->esp.val.spi));
2624 break;
2625 case IB_FLOW_SPEC_TCP:
2626 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2627 LAST_TCP_UDP_FIELD))
2628 return -EOPNOTSUPP;
2629
2630 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2631 0xff);
2632 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2633 IPPROTO_TCP);
2634
2635 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_sport,
2636 ntohs(ib_spec->tcp_udp.mask.src_port));
2637 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_sport,
2638 ntohs(ib_spec->tcp_udp.val.src_port));
2639
2640 MLX5_SET(fte_match_set_lyr_2_4, headers_c, tcp_dport,
2641 ntohs(ib_spec->tcp_udp.mask.dst_port));
2642 MLX5_SET(fte_match_set_lyr_2_4, headers_v, tcp_dport,
2643 ntohs(ib_spec->tcp_udp.val.dst_port));
2644 break;
2645 case IB_FLOW_SPEC_UDP:
2646 if (FIELDS_NOT_SUPPORTED(ib_spec->tcp_udp.mask,
2647 LAST_TCP_UDP_FIELD))
2648 return -EOPNOTSUPP;
2649
2650 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2651 0xff);
2652 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2653 IPPROTO_UDP);
2654
2655 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_sport,
2656 ntohs(ib_spec->tcp_udp.mask.src_port));
2657 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_sport,
2658 ntohs(ib_spec->tcp_udp.val.src_port));
2659
2660 MLX5_SET(fte_match_set_lyr_2_4, headers_c, udp_dport,
2661 ntohs(ib_spec->tcp_udp.mask.dst_port));
2662 MLX5_SET(fte_match_set_lyr_2_4, headers_v, udp_dport,
2663 ntohs(ib_spec->tcp_udp.val.dst_port));
2664 break;
2665 case IB_FLOW_SPEC_GRE:
2666 if (ib_spec->gre.mask.c_ks_res0_ver)
2667 return -EOPNOTSUPP;
2668
2669 MLX5_SET(fte_match_set_lyr_2_4, headers_c, ip_protocol,
2670 0xff);
2671 MLX5_SET(fte_match_set_lyr_2_4, headers_v, ip_protocol,
2672 IPPROTO_GRE);
2673
2674 MLX5_SET(fte_match_set_misc, misc_params_c, gre_protocol,
2675 ntohs(ib_spec->gre.mask.protocol));
2676 MLX5_SET(fte_match_set_misc, misc_params_v, gre_protocol,
2677 ntohs(ib_spec->gre.val.protocol));
2678
2679 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_c,
2680 gre_key_h),
2681 &ib_spec->gre.mask.key,
2682 sizeof(ib_spec->gre.mask.key));
2683 memcpy(MLX5_ADDR_OF(fte_match_set_misc, misc_params_v,
2684 gre_key_h),
2685 &ib_spec->gre.val.key,
2686 sizeof(ib_spec->gre.val.key));
2687 break;
2688 case IB_FLOW_SPEC_MPLS:
2689 switch (prev_type) {
2690 case IB_FLOW_SPEC_UDP:
2691 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2692 ft_field_support.outer_first_mpls_over_udp),
2693 &ib_spec->mpls.mask.tag))
2694 return -EOPNOTSUPP;
2695
2696 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2697 outer_first_mpls_over_udp),
2698 &ib_spec->mpls.val.tag,
2699 sizeof(ib_spec->mpls.val.tag));
2700 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2701 outer_first_mpls_over_udp),
2702 &ib_spec->mpls.mask.tag,
2703 sizeof(ib_spec->mpls.mask.tag));
2704 break;
2705 case IB_FLOW_SPEC_GRE:
2706 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2707 ft_field_support.outer_first_mpls_over_gre),
2708 &ib_spec->mpls.mask.tag))
2709 return -EOPNOTSUPP;
2710
2711 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2712 outer_first_mpls_over_gre),
2713 &ib_spec->mpls.val.tag,
2714 sizeof(ib_spec->mpls.val.tag));
2715 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2716 outer_first_mpls_over_gre),
2717 &ib_spec->mpls.mask.tag,
2718 sizeof(ib_spec->mpls.mask.tag));
2719 break;
2720 default:
2721 if (ib_spec->type & IB_FLOW_SPEC_INNER) {
2722 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2723 ft_field_support.inner_first_mpls),
2724 &ib_spec->mpls.mask.tag))
2725 return -EOPNOTSUPP;
2726
2727 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2728 inner_first_mpls),
2729 &ib_spec->mpls.val.tag,
2730 sizeof(ib_spec->mpls.val.tag));
2731 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2732 inner_first_mpls),
2733 &ib_spec->mpls.mask.tag,
2734 sizeof(ib_spec->mpls.mask.tag));
2735 } else {
2736 if (check_mpls_supp_fields(MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2737 ft_field_support.outer_first_mpls),
2738 &ib_spec->mpls.mask.tag))
2739 return -EOPNOTSUPP;
2740
2741 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_v,
2742 outer_first_mpls),
2743 &ib_spec->mpls.val.tag,
2744 sizeof(ib_spec->mpls.val.tag));
2745 memcpy(MLX5_ADDR_OF(fte_match_set_misc2, misc_params2_c,
2746 outer_first_mpls),
2747 &ib_spec->mpls.mask.tag,
2748 sizeof(ib_spec->mpls.mask.tag));
2749 }
2750 }
2751 break;
2752 case IB_FLOW_SPEC_VXLAN_TUNNEL:
2753 if (FIELDS_NOT_SUPPORTED(ib_spec->tunnel.mask,
2754 LAST_TUNNEL_FIELD))
2755 return -EOPNOTSUPP;
2756
2757 MLX5_SET(fte_match_set_misc, misc_params_c, vxlan_vni,
2758 ntohl(ib_spec->tunnel.mask.tunnel_id));
2759 MLX5_SET(fte_match_set_misc, misc_params_v, vxlan_vni,
2760 ntohl(ib_spec->tunnel.val.tunnel_id));
2761 break;
2762 case IB_FLOW_SPEC_ACTION_TAG:
2763 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_tag,
2764 LAST_FLOW_TAG_FIELD))
2765 return -EOPNOTSUPP;
2766 if (ib_spec->flow_tag.tag_id >= BIT(24))
2767 return -EINVAL;
2768
2769 action->flow_tag = ib_spec->flow_tag.tag_id;
2770 action->has_flow_tag = true;
2771 break;
2772 case IB_FLOW_SPEC_ACTION_DROP:
2773 if (FIELDS_NOT_SUPPORTED(ib_spec->drop,
2774 LAST_DROP_FIELD))
2775 return -EOPNOTSUPP;
2776 action->action |= MLX5_FLOW_CONTEXT_ACTION_DROP;
2777 break;
2778 case IB_FLOW_SPEC_ACTION_HANDLE:
2779 ret = parse_flow_flow_action(to_mflow_act(ib_spec->action.act),
2780 flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS, action);
2781 if (ret)
2782 return ret;
2783 break;
2784 case IB_FLOW_SPEC_ACTION_COUNT:
2785 if (FIELDS_NOT_SUPPORTED(ib_spec->flow_count,
2786 LAST_COUNTERS_FIELD))
2787 return -EOPNOTSUPP;
2788
2789 /* for now support only one counters spec per flow */
2790 if (action->action & MLX5_FLOW_CONTEXT_ACTION_COUNT)
2791 return -EINVAL;
2792
2793 action->counters = ib_spec->flow_count.counters;
2794 action->action |= MLX5_FLOW_CONTEXT_ACTION_COUNT;
2795 break;
2796 default:
2797 return -EINVAL;
2798 }
2799
2800 return 0;
2801 }
2802
2803 /* If a flow could catch both multicast and unicast packets,
2804 * it won't fall into the multicast flow steering table and this rule
2805 * could steal other multicast packets.
2806 */
2807 static bool flow_is_multicast_only(const struct ib_flow_attr *ib_attr)
2808 {
2809 union ib_flow_spec *flow_spec;
2810
2811 if (ib_attr->type != IB_FLOW_ATTR_NORMAL ||
2812 ib_attr->num_of_specs < 1)
2813 return false;
2814
2815 flow_spec = (union ib_flow_spec *)(ib_attr + 1);
2816 if (flow_spec->type == IB_FLOW_SPEC_IPV4) {
2817 struct ib_flow_spec_ipv4 *ipv4_spec;
2818
2819 ipv4_spec = (struct ib_flow_spec_ipv4 *)flow_spec;
2820 if (ipv4_is_multicast(ipv4_spec->val.dst_ip))
2821 return true;
2822
2823 return false;
2824 }
2825
2826 if (flow_spec->type == IB_FLOW_SPEC_ETH) {
2827 struct ib_flow_spec_eth *eth_spec;
2828
2829 eth_spec = (struct ib_flow_spec_eth *)flow_spec;
2830 return is_multicast_ether_addr(eth_spec->mask.dst_mac) &&
2831 is_multicast_ether_addr(eth_spec->val.dst_mac);
2832 }
2833
2834 return false;
2835 }
2836
2837 enum valid_spec {
2838 VALID_SPEC_INVALID,
2839 VALID_SPEC_VALID,
2840 VALID_SPEC_NA,
2841 };
2842
2843 static enum valid_spec
2844 is_valid_esp_aes_gcm(struct mlx5_core_dev *mdev,
2845 const struct mlx5_flow_spec *spec,
2846 const struct mlx5_flow_act *flow_act,
2847 bool egress)
2848 {
2849 const u32 *match_c = spec->match_criteria;
2850 bool is_crypto =
2851 (flow_act->action & (MLX5_FLOW_CONTEXT_ACTION_ENCRYPT |
2852 MLX5_FLOW_CONTEXT_ACTION_DECRYPT));
2853 bool is_ipsec = mlx5_fs_is_ipsec_flow(match_c);
2854 bool is_drop = flow_act->action & MLX5_FLOW_CONTEXT_ACTION_DROP;
2855
2856 /*
2857 * Currently only crypto is supported in egress, when regular egress
2858 * rules would be supported, always return VALID_SPEC_NA.
2859 */
2860 if (!is_crypto)
2861 return VALID_SPEC_NA;
2862
2863 return is_crypto && is_ipsec &&
2864 (!egress || (!is_drop && !flow_act->has_flow_tag)) ?
2865 VALID_SPEC_VALID : VALID_SPEC_INVALID;
2866 }
2867
2868 static bool is_valid_spec(struct mlx5_core_dev *mdev,
2869 const struct mlx5_flow_spec *spec,
2870 const struct mlx5_flow_act *flow_act,
2871 bool egress)
2872 {
2873 /* We curretly only support ipsec egress flow */
2874 return is_valid_esp_aes_gcm(mdev, spec, flow_act, egress) != VALID_SPEC_INVALID;
2875 }
2876
2877 static bool is_valid_ethertype(struct mlx5_core_dev *mdev,
2878 const struct ib_flow_attr *flow_attr,
2879 bool check_inner)
2880 {
2881 union ib_flow_spec *ib_spec = (union ib_flow_spec *)(flow_attr + 1);
2882 int match_ipv = check_inner ?
2883 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2884 ft_field_support.inner_ip_version) :
2885 MLX5_CAP_FLOWTABLE_NIC_RX(mdev,
2886 ft_field_support.outer_ip_version);
2887 int inner_bit = check_inner ? IB_FLOW_SPEC_INNER : 0;
2888 bool ipv4_spec_valid, ipv6_spec_valid;
2889 unsigned int ip_spec_type = 0;
2890 bool has_ethertype = false;
2891 unsigned int spec_index;
2892 bool mask_valid = true;
2893 u16 eth_type = 0;
2894 bool type_valid;
2895
2896 /* Validate that ethertype is correct */
2897 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
2898 if ((ib_spec->type == (IB_FLOW_SPEC_ETH | inner_bit)) &&
2899 ib_spec->eth.mask.ether_type) {
2900 mask_valid = (ib_spec->eth.mask.ether_type ==
2901 htons(0xffff));
2902 has_ethertype = true;
2903 eth_type = ntohs(ib_spec->eth.val.ether_type);
2904 } else if ((ib_spec->type == (IB_FLOW_SPEC_IPV4 | inner_bit)) ||
2905 (ib_spec->type == (IB_FLOW_SPEC_IPV6 | inner_bit))) {
2906 ip_spec_type = ib_spec->type;
2907 }
2908 ib_spec = (void *)ib_spec + ib_spec->size;
2909 }
2910
2911 type_valid = (!has_ethertype) || (!ip_spec_type);
2912 if (!type_valid && mask_valid) {
2913 ipv4_spec_valid = (eth_type == ETH_P_IP) &&
2914 (ip_spec_type == (IB_FLOW_SPEC_IPV4 | inner_bit));
2915 ipv6_spec_valid = (eth_type == ETH_P_IPV6) &&
2916 (ip_spec_type == (IB_FLOW_SPEC_IPV6 | inner_bit));
2917
2918 type_valid = (ipv4_spec_valid) || (ipv6_spec_valid) ||
2919 (((eth_type == ETH_P_MPLS_UC) ||
2920 (eth_type == ETH_P_MPLS_MC)) && match_ipv);
2921 }
2922
2923 return type_valid;
2924 }
2925
2926 static bool is_valid_attr(struct mlx5_core_dev *mdev,
2927 const struct ib_flow_attr *flow_attr)
2928 {
2929 return is_valid_ethertype(mdev, flow_attr, false) &&
2930 is_valid_ethertype(mdev, flow_attr, true);
2931 }
2932
2933 static void put_flow_table(struct mlx5_ib_dev *dev,
2934 struct mlx5_ib_flow_prio *prio, bool ft_added)
2935 {
2936 prio->refcount -= !!ft_added;
2937 if (!prio->refcount) {
2938 mlx5_destroy_flow_table(prio->flow_table);
2939 prio->flow_table = NULL;
2940 }
2941 }
2942
2943 static void counters_clear_description(struct ib_counters *counters)
2944 {
2945 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
2946
2947 mutex_lock(&mcounters->mcntrs_mutex);
2948 kfree(mcounters->counters_data);
2949 mcounters->counters_data = NULL;
2950 mcounters->cntrs_max_index = 0;
2951 mutex_unlock(&mcounters->mcntrs_mutex);
2952 }
2953
2954 static int mlx5_ib_destroy_flow(struct ib_flow *flow_id)
2955 {
2956 struct mlx5_ib_flow_handler *handler = container_of(flow_id,
2957 struct mlx5_ib_flow_handler,
2958 ibflow);
2959 struct mlx5_ib_flow_handler *iter, *tmp;
2960 struct mlx5_ib_dev *dev = handler->dev;
2961
2962 mutex_lock(&dev->flow_db->lock);
2963
2964 list_for_each_entry_safe(iter, tmp, &handler->list, list) {
2965 mlx5_del_flow_rules(iter->rule);
2966 put_flow_table(dev, iter->prio, true);
2967 list_del(&iter->list);
2968 kfree(iter);
2969 }
2970
2971 mlx5_del_flow_rules(handler->rule);
2972 put_flow_table(dev, handler->prio, true);
2973 if (handler->ibcounters &&
2974 atomic_read(&handler->ibcounters->usecnt) == 1)
2975 counters_clear_description(handler->ibcounters);
2976
2977 mutex_unlock(&dev->flow_db->lock);
2978 if (handler->flow_matcher)
2979 atomic_dec(&handler->flow_matcher->usecnt);
2980 kfree(handler);
2981
2982 return 0;
2983 }
2984
2985 static int ib_prio_to_core_prio(unsigned int priority, bool dont_trap)
2986 {
2987 priority *= 2;
2988 if (!dont_trap)
2989 priority++;
2990 return priority;
2991 }
2992
2993 enum flow_table_type {
2994 MLX5_IB_FT_RX,
2995 MLX5_IB_FT_TX
2996 };
2997
2998 #define MLX5_FS_MAX_TYPES 6
2999 #define MLX5_FS_MAX_ENTRIES BIT(16)
3000
3001 static struct mlx5_ib_flow_prio *_get_prio(struct mlx5_flow_namespace *ns,
3002 struct mlx5_ib_flow_prio *prio,
3003 int priority,
3004 int num_entries, int num_groups,
3005 u32 flags)
3006 {
3007 struct mlx5_flow_table *ft;
3008
3009 ft = mlx5_create_auto_grouped_flow_table(ns, priority,
3010 num_entries,
3011 num_groups,
3012 0, flags);
3013 if (IS_ERR(ft))
3014 return ERR_CAST(ft);
3015
3016 prio->flow_table = ft;
3017 prio->refcount = 0;
3018 return prio;
3019 }
3020
3021 static struct mlx5_ib_flow_prio *get_flow_table(struct mlx5_ib_dev *dev,
3022 struct ib_flow_attr *flow_attr,
3023 enum flow_table_type ft_type)
3024 {
3025 bool dont_trap = flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP;
3026 struct mlx5_flow_namespace *ns = NULL;
3027 struct mlx5_ib_flow_prio *prio;
3028 struct mlx5_flow_table *ft;
3029 int max_table_size;
3030 int num_entries;
3031 int num_groups;
3032 u32 flags = 0;
3033 int priority;
3034
3035 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3036 log_max_ft_size));
3037 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3038 enum mlx5_flow_namespace_type fn_type;
3039
3040 if (flow_is_multicast_only(flow_attr) &&
3041 !dont_trap)
3042 priority = MLX5_IB_FLOW_MCAST_PRIO;
3043 else
3044 priority = ib_prio_to_core_prio(flow_attr->priority,
3045 dont_trap);
3046 if (ft_type == MLX5_IB_FT_RX) {
3047 fn_type = MLX5_FLOW_NAMESPACE_BYPASS;
3048 prio = &dev->flow_db->prios[priority];
3049 if (!dev->rep &&
3050 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3051 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3052 if (!dev->rep &&
3053 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3054 reformat_l3_tunnel_to_l2))
3055 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3056 } else {
3057 max_table_size =
3058 BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3059 log_max_ft_size));
3060 fn_type = MLX5_FLOW_NAMESPACE_EGRESS;
3061 prio = &dev->flow_db->egress_prios[priority];
3062 if (!dev->rep &&
3063 MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3064 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3065 }
3066 ns = mlx5_get_flow_namespace(dev->mdev, fn_type);
3067 num_entries = MLX5_FS_MAX_ENTRIES;
3068 num_groups = MLX5_FS_MAX_TYPES;
3069 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3070 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3071 ns = mlx5_get_flow_namespace(dev->mdev,
3072 MLX5_FLOW_NAMESPACE_LEFTOVERS);
3073 build_leftovers_ft_param(&priority,
3074 &num_entries,
3075 &num_groups);
3076 prio = &dev->flow_db->prios[MLX5_IB_FLOW_LEFTOVERS_PRIO];
3077 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3078 if (!MLX5_CAP_FLOWTABLE(dev->mdev,
3079 allow_sniffer_and_nic_rx_shared_tir))
3080 return ERR_PTR(-ENOTSUPP);
3081
3082 ns = mlx5_get_flow_namespace(dev->mdev, ft_type == MLX5_IB_FT_RX ?
3083 MLX5_FLOW_NAMESPACE_SNIFFER_RX :
3084 MLX5_FLOW_NAMESPACE_SNIFFER_TX);
3085
3086 prio = &dev->flow_db->sniffer[ft_type];
3087 priority = 0;
3088 num_entries = 1;
3089 num_groups = 1;
3090 }
3091
3092 if (!ns)
3093 return ERR_PTR(-ENOTSUPP);
3094
3095 if (num_entries > max_table_size)
3096 return ERR_PTR(-ENOMEM);
3097
3098 ft = prio->flow_table;
3099 if (!ft)
3100 return _get_prio(ns, prio, priority, num_entries, num_groups,
3101 flags);
3102
3103 return prio;
3104 }
3105
3106 static void set_underlay_qp(struct mlx5_ib_dev *dev,
3107 struct mlx5_flow_spec *spec,
3108 u32 underlay_qpn)
3109 {
3110 void *misc_params_c = MLX5_ADDR_OF(fte_match_param,
3111 spec->match_criteria,
3112 misc_parameters);
3113 void *misc_params_v = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3114 misc_parameters);
3115
3116 if (underlay_qpn &&
3117 MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3118 ft_field_support.bth_dst_qp)) {
3119 MLX5_SET(fte_match_set_misc,
3120 misc_params_v, bth_dst_qp, underlay_qpn);
3121 MLX5_SET(fte_match_set_misc,
3122 misc_params_c, bth_dst_qp, 0xffffff);
3123 }
3124 }
3125
3126 static int read_flow_counters(struct ib_device *ibdev,
3127 struct mlx5_read_counters_attr *read_attr)
3128 {
3129 struct mlx5_fc *fc = read_attr->hw_cntrs_hndl;
3130 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3131
3132 return mlx5_fc_query(dev->mdev, fc,
3133 &read_attr->out[IB_COUNTER_PACKETS],
3134 &read_attr->out[IB_COUNTER_BYTES]);
3135 }
3136
3137 /* flow counters currently expose two counters packets and bytes */
3138 #define FLOW_COUNTERS_NUM 2
3139 static int counters_set_description(struct ib_counters *counters,
3140 enum mlx5_ib_counters_type counters_type,
3141 struct mlx5_ib_flow_counters_desc *desc_data,
3142 u32 ncounters)
3143 {
3144 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
3145 u32 cntrs_max_index = 0;
3146 int i;
3147
3148 if (counters_type != MLX5_IB_COUNTERS_FLOW)
3149 return -EINVAL;
3150
3151 /* init the fields for the object */
3152 mcounters->type = counters_type;
3153 mcounters->read_counters = read_flow_counters;
3154 mcounters->counters_num = FLOW_COUNTERS_NUM;
3155 mcounters->ncounters = ncounters;
3156 /* each counter entry have both description and index pair */
3157 for (i = 0; i < ncounters; i++) {
3158 if (desc_data[i].description > IB_COUNTER_BYTES)
3159 return -EINVAL;
3160
3161 if (cntrs_max_index <= desc_data[i].index)
3162 cntrs_max_index = desc_data[i].index + 1;
3163 }
3164
3165 mutex_lock(&mcounters->mcntrs_mutex);
3166 mcounters->counters_data = desc_data;
3167 mcounters->cntrs_max_index = cntrs_max_index;
3168 mutex_unlock(&mcounters->mcntrs_mutex);
3169
3170 return 0;
3171 }
3172
3173 #define MAX_COUNTERS_NUM (USHRT_MAX / (sizeof(u32) * 2))
3174 static int flow_counters_set_data(struct ib_counters *ibcounters,
3175 struct mlx5_ib_create_flow *ucmd)
3176 {
3177 struct mlx5_ib_mcounters *mcounters = to_mcounters(ibcounters);
3178 struct mlx5_ib_flow_counters_data *cntrs_data = NULL;
3179 struct mlx5_ib_flow_counters_desc *desc_data = NULL;
3180 bool hw_hndl = false;
3181 int ret = 0;
3182
3183 if (ucmd && ucmd->ncounters_data != 0) {
3184 cntrs_data = ucmd->data;
3185 if (cntrs_data->ncounters > MAX_COUNTERS_NUM)
3186 return -EINVAL;
3187
3188 desc_data = kcalloc(cntrs_data->ncounters,
3189 sizeof(*desc_data),
3190 GFP_KERNEL);
3191 if (!desc_data)
3192 return -ENOMEM;
3193
3194 if (copy_from_user(desc_data,
3195 u64_to_user_ptr(cntrs_data->counters_data),
3196 sizeof(*desc_data) * cntrs_data->ncounters)) {
3197 ret = -EFAULT;
3198 goto free;
3199 }
3200 }
3201
3202 if (!mcounters->hw_cntrs_hndl) {
3203 mcounters->hw_cntrs_hndl = mlx5_fc_create(
3204 to_mdev(ibcounters->device)->mdev, false);
3205 if (IS_ERR(mcounters->hw_cntrs_hndl)) {
3206 ret = PTR_ERR(mcounters->hw_cntrs_hndl);
3207 goto free;
3208 }
3209 hw_hndl = true;
3210 }
3211
3212 if (desc_data) {
3213 /* counters already bound to at least one flow */
3214 if (mcounters->cntrs_max_index) {
3215 ret = -EINVAL;
3216 goto free_hndl;
3217 }
3218
3219 ret = counters_set_description(ibcounters,
3220 MLX5_IB_COUNTERS_FLOW,
3221 desc_data,
3222 cntrs_data->ncounters);
3223 if (ret)
3224 goto free_hndl;
3225
3226 } else if (!mcounters->cntrs_max_index) {
3227 /* counters not bound yet, must have udata passed */
3228 ret = -EINVAL;
3229 goto free_hndl;
3230 }
3231
3232 return 0;
3233
3234 free_hndl:
3235 if (hw_hndl) {
3236 mlx5_fc_destroy(to_mdev(ibcounters->device)->mdev,
3237 mcounters->hw_cntrs_hndl);
3238 mcounters->hw_cntrs_hndl = NULL;
3239 }
3240 free:
3241 kfree(desc_data);
3242 return ret;
3243 }
3244
3245 static struct mlx5_ib_flow_handler *_create_flow_rule(struct mlx5_ib_dev *dev,
3246 struct mlx5_ib_flow_prio *ft_prio,
3247 const struct ib_flow_attr *flow_attr,
3248 struct mlx5_flow_destination *dst,
3249 u32 underlay_qpn,
3250 struct mlx5_ib_create_flow *ucmd)
3251 {
3252 struct mlx5_flow_table *ft = ft_prio->flow_table;
3253 struct mlx5_ib_flow_handler *handler;
3254 struct mlx5_flow_act flow_act = {.flow_tag = MLX5_FS_DEFAULT_FLOW_TAG};
3255 struct mlx5_flow_spec *spec;
3256 struct mlx5_flow_destination dest_arr[2] = {};
3257 struct mlx5_flow_destination *rule_dst = dest_arr;
3258 const void *ib_flow = (const void *)flow_attr + sizeof(*flow_attr);
3259 unsigned int spec_index;
3260 u32 prev_type = 0;
3261 int err = 0;
3262 int dest_num = 0;
3263 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3264
3265 if (!is_valid_attr(dev->mdev, flow_attr))
3266 return ERR_PTR(-EINVAL);
3267
3268 if (dev->rep && is_egress)
3269 return ERR_PTR(-EINVAL);
3270
3271 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3272 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3273 if (!handler || !spec) {
3274 err = -ENOMEM;
3275 goto free;
3276 }
3277
3278 INIT_LIST_HEAD(&handler->list);
3279 if (dst) {
3280 memcpy(&dest_arr[0], dst, sizeof(*dst));
3281 dest_num++;
3282 }
3283
3284 for (spec_index = 0; spec_index < flow_attr->num_of_specs; spec_index++) {
3285 err = parse_flow_attr(dev->mdev, spec->match_criteria,
3286 spec->match_value,
3287 ib_flow, flow_attr, &flow_act,
3288 prev_type);
3289 if (err < 0)
3290 goto free;
3291
3292 prev_type = ((union ib_flow_spec *)ib_flow)->type;
3293 ib_flow += ((union ib_flow_spec *)ib_flow)->size;
3294 }
3295
3296 if (!flow_is_multicast_only(flow_attr))
3297 set_underlay_qp(dev, spec, underlay_qpn);
3298
3299 if (dev->rep) {
3300 void *misc;
3301
3302 misc = MLX5_ADDR_OF(fte_match_param, spec->match_value,
3303 misc_parameters);
3304 MLX5_SET(fte_match_set_misc, misc, source_port,
3305 dev->rep->vport);
3306 misc = MLX5_ADDR_OF(fte_match_param, spec->match_criteria,
3307 misc_parameters);
3308 MLX5_SET_TO_ONES(fte_match_set_misc, misc, source_port);
3309 }
3310
3311 spec->match_criteria_enable = get_match_criteria_enable(spec->match_criteria);
3312
3313 if (is_egress &&
3314 !is_valid_spec(dev->mdev, spec, &flow_act, is_egress)) {
3315 err = -EINVAL;
3316 goto free;
3317 }
3318
3319 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT) {
3320 err = flow_counters_set_data(flow_act.counters, ucmd);
3321 if (err)
3322 goto free;
3323
3324 handler->ibcounters = flow_act.counters;
3325 dest_arr[dest_num].type =
3326 MLX5_FLOW_DESTINATION_TYPE_COUNTER;
3327 dest_arr[dest_num].counter =
3328 to_mcounters(flow_act.counters)->hw_cntrs_hndl;
3329 dest_num++;
3330 }
3331
3332 if (flow_act.action & MLX5_FLOW_CONTEXT_ACTION_DROP) {
3333 if (!(flow_act.action & MLX5_FLOW_CONTEXT_ACTION_COUNT)) {
3334 rule_dst = NULL;
3335 dest_num = 0;
3336 }
3337 } else {
3338 if (is_egress)
3339 flow_act.action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3340 else
3341 flow_act.action |=
3342 dest_num ? MLX5_FLOW_CONTEXT_ACTION_FWD_DEST :
3343 MLX5_FLOW_CONTEXT_ACTION_FWD_NEXT_PRIO;
3344 }
3345
3346 if (flow_act.has_flow_tag &&
3347 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3348 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3349 mlx5_ib_warn(dev, "Flow tag %u and attribute type %x isn't allowed in leftovers\n",
3350 flow_act.flow_tag, flow_attr->type);
3351 err = -EINVAL;
3352 goto free;
3353 }
3354 handler->rule = mlx5_add_flow_rules(ft, spec,
3355 &flow_act,
3356 rule_dst, dest_num);
3357
3358 if (IS_ERR(handler->rule)) {
3359 err = PTR_ERR(handler->rule);
3360 goto free;
3361 }
3362
3363 ft_prio->refcount++;
3364 handler->prio = ft_prio;
3365 handler->dev = dev;
3366
3367 ft_prio->flow_table = ft;
3368 free:
3369 if (err && handler) {
3370 if (handler->ibcounters &&
3371 atomic_read(&handler->ibcounters->usecnt) == 1)
3372 counters_clear_description(handler->ibcounters);
3373 kfree(handler);
3374 }
3375 kvfree(spec);
3376 return err ? ERR_PTR(err) : handler;
3377 }
3378
3379 static struct mlx5_ib_flow_handler *create_flow_rule(struct mlx5_ib_dev *dev,
3380 struct mlx5_ib_flow_prio *ft_prio,
3381 const struct ib_flow_attr *flow_attr,
3382 struct mlx5_flow_destination *dst)
3383 {
3384 return _create_flow_rule(dev, ft_prio, flow_attr, dst, 0, NULL);
3385 }
3386
3387 static struct mlx5_ib_flow_handler *create_dont_trap_rule(struct mlx5_ib_dev *dev,
3388 struct mlx5_ib_flow_prio *ft_prio,
3389 struct ib_flow_attr *flow_attr,
3390 struct mlx5_flow_destination *dst)
3391 {
3392 struct mlx5_ib_flow_handler *handler_dst = NULL;
3393 struct mlx5_ib_flow_handler *handler = NULL;
3394
3395 handler = create_flow_rule(dev, ft_prio, flow_attr, NULL);
3396 if (!IS_ERR(handler)) {
3397 handler_dst = create_flow_rule(dev, ft_prio,
3398 flow_attr, dst);
3399 if (IS_ERR(handler_dst)) {
3400 mlx5_del_flow_rules(handler->rule);
3401 ft_prio->refcount--;
3402 kfree(handler);
3403 handler = handler_dst;
3404 } else {
3405 list_add(&handler_dst->list, &handler->list);
3406 }
3407 }
3408
3409 return handler;
3410 }
3411 enum {
3412 LEFTOVERS_MC,
3413 LEFTOVERS_UC,
3414 };
3415
3416 static struct mlx5_ib_flow_handler *create_leftovers_rule(struct mlx5_ib_dev *dev,
3417 struct mlx5_ib_flow_prio *ft_prio,
3418 struct ib_flow_attr *flow_attr,
3419 struct mlx5_flow_destination *dst)
3420 {
3421 struct mlx5_ib_flow_handler *handler_ucast = NULL;
3422 struct mlx5_ib_flow_handler *handler = NULL;
3423
3424 static struct {
3425 struct ib_flow_attr flow_attr;
3426 struct ib_flow_spec_eth eth_flow;
3427 } leftovers_specs[] = {
3428 [LEFTOVERS_MC] = {
3429 .flow_attr = {
3430 .num_of_specs = 1,
3431 .size = sizeof(leftovers_specs[0])
3432 },
3433 .eth_flow = {
3434 .type = IB_FLOW_SPEC_ETH,
3435 .size = sizeof(struct ib_flow_spec_eth),
3436 .mask = {.dst_mac = {0x1} },
3437 .val = {.dst_mac = {0x1} }
3438 }
3439 },
3440 [LEFTOVERS_UC] = {
3441 .flow_attr = {
3442 .num_of_specs = 1,
3443 .size = sizeof(leftovers_specs[0])
3444 },
3445 .eth_flow = {
3446 .type = IB_FLOW_SPEC_ETH,
3447 .size = sizeof(struct ib_flow_spec_eth),
3448 .mask = {.dst_mac = {0x1} },
3449 .val = {.dst_mac = {} }
3450 }
3451 }
3452 };
3453
3454 handler = create_flow_rule(dev, ft_prio,
3455 &leftovers_specs[LEFTOVERS_MC].flow_attr,
3456 dst);
3457 if (!IS_ERR(handler) &&
3458 flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT) {
3459 handler_ucast = create_flow_rule(dev, ft_prio,
3460 &leftovers_specs[LEFTOVERS_UC].flow_attr,
3461 dst);
3462 if (IS_ERR(handler_ucast)) {
3463 mlx5_del_flow_rules(handler->rule);
3464 ft_prio->refcount--;
3465 kfree(handler);
3466 handler = handler_ucast;
3467 } else {
3468 list_add(&handler_ucast->list, &handler->list);
3469 }
3470 }
3471
3472 return handler;
3473 }
3474
3475 static struct mlx5_ib_flow_handler *create_sniffer_rule(struct mlx5_ib_dev *dev,
3476 struct mlx5_ib_flow_prio *ft_rx,
3477 struct mlx5_ib_flow_prio *ft_tx,
3478 struct mlx5_flow_destination *dst)
3479 {
3480 struct mlx5_ib_flow_handler *handler_rx;
3481 struct mlx5_ib_flow_handler *handler_tx;
3482 int err;
3483 static const struct ib_flow_attr flow_attr = {
3484 .num_of_specs = 0,
3485 .size = sizeof(flow_attr)
3486 };
3487
3488 handler_rx = create_flow_rule(dev, ft_rx, &flow_attr, dst);
3489 if (IS_ERR(handler_rx)) {
3490 err = PTR_ERR(handler_rx);
3491 goto err;
3492 }
3493
3494 handler_tx = create_flow_rule(dev, ft_tx, &flow_attr, dst);
3495 if (IS_ERR(handler_tx)) {
3496 err = PTR_ERR(handler_tx);
3497 goto err_tx;
3498 }
3499
3500 list_add(&handler_tx->list, &handler_rx->list);
3501
3502 return handler_rx;
3503
3504 err_tx:
3505 mlx5_del_flow_rules(handler_rx->rule);
3506 ft_rx->refcount--;
3507 kfree(handler_rx);
3508 err:
3509 return ERR_PTR(err);
3510 }
3511
3512 static struct ib_flow *mlx5_ib_create_flow(struct ib_qp *qp,
3513 struct ib_flow_attr *flow_attr,
3514 int domain,
3515 struct ib_udata *udata)
3516 {
3517 struct mlx5_ib_dev *dev = to_mdev(qp->device);
3518 struct mlx5_ib_qp *mqp = to_mqp(qp);
3519 struct mlx5_ib_flow_handler *handler = NULL;
3520 struct mlx5_flow_destination *dst = NULL;
3521 struct mlx5_ib_flow_prio *ft_prio_tx = NULL;
3522 struct mlx5_ib_flow_prio *ft_prio;
3523 bool is_egress = flow_attr->flags & IB_FLOW_ATTR_FLAGS_EGRESS;
3524 struct mlx5_ib_create_flow *ucmd = NULL, ucmd_hdr;
3525 size_t min_ucmd_sz, required_ucmd_sz;
3526 int err;
3527 int underlay_qpn;
3528
3529 if (udata && udata->inlen) {
3530 min_ucmd_sz = offsetof(typeof(ucmd_hdr), reserved) +
3531 sizeof(ucmd_hdr.reserved);
3532 if (udata->inlen < min_ucmd_sz)
3533 return ERR_PTR(-EOPNOTSUPP);
3534
3535 err = ib_copy_from_udata(&ucmd_hdr, udata, min_ucmd_sz);
3536 if (err)
3537 return ERR_PTR(err);
3538
3539 /* currently supports only one counters data */
3540 if (ucmd_hdr.ncounters_data > 1)
3541 return ERR_PTR(-EINVAL);
3542
3543 required_ucmd_sz = min_ucmd_sz +
3544 sizeof(struct mlx5_ib_flow_counters_data) *
3545 ucmd_hdr.ncounters_data;
3546 if (udata->inlen > required_ucmd_sz &&
3547 !ib_is_udata_cleared(udata, required_ucmd_sz,
3548 udata->inlen - required_ucmd_sz))
3549 return ERR_PTR(-EOPNOTSUPP);
3550
3551 ucmd = kzalloc(required_ucmd_sz, GFP_KERNEL);
3552 if (!ucmd)
3553 return ERR_PTR(-ENOMEM);
3554
3555 err = ib_copy_from_udata(ucmd, udata, required_ucmd_sz);
3556 if (err)
3557 goto free_ucmd;
3558 }
3559
3560 if (flow_attr->priority > MLX5_IB_FLOW_LAST_PRIO) {
3561 err = -ENOMEM;
3562 goto free_ucmd;
3563 }
3564
3565 if (domain != IB_FLOW_DOMAIN_USER ||
3566 flow_attr->port > dev->num_ports ||
3567 (flow_attr->flags & ~(IB_FLOW_ATTR_FLAGS_DONT_TRAP |
3568 IB_FLOW_ATTR_FLAGS_EGRESS))) {
3569 err = -EINVAL;
3570 goto free_ucmd;
3571 }
3572
3573 if (is_egress &&
3574 (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3575 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT)) {
3576 err = -EINVAL;
3577 goto free_ucmd;
3578 }
3579
3580 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3581 if (!dst) {
3582 err = -ENOMEM;
3583 goto free_ucmd;
3584 }
3585
3586 mutex_lock(&dev->flow_db->lock);
3587
3588 ft_prio = get_flow_table(dev, flow_attr,
3589 is_egress ? MLX5_IB_FT_TX : MLX5_IB_FT_RX);
3590 if (IS_ERR(ft_prio)) {
3591 err = PTR_ERR(ft_prio);
3592 goto unlock;
3593 }
3594 if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3595 ft_prio_tx = get_flow_table(dev, flow_attr, MLX5_IB_FT_TX);
3596 if (IS_ERR(ft_prio_tx)) {
3597 err = PTR_ERR(ft_prio_tx);
3598 ft_prio_tx = NULL;
3599 goto destroy_ft;
3600 }
3601 }
3602
3603 if (is_egress) {
3604 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3605 } else {
3606 dst->type = MLX5_FLOW_DESTINATION_TYPE_TIR;
3607 if (mqp->flags & MLX5_IB_QP_RSS)
3608 dst->tir_num = mqp->rss_qp.tirn;
3609 else
3610 dst->tir_num = mqp->raw_packet_qp.rq.tirn;
3611 }
3612
3613 if (flow_attr->type == IB_FLOW_ATTR_NORMAL) {
3614 if (flow_attr->flags & IB_FLOW_ATTR_FLAGS_DONT_TRAP) {
3615 handler = create_dont_trap_rule(dev, ft_prio,
3616 flow_attr, dst);
3617 } else {
3618 underlay_qpn = (mqp->flags & MLX5_IB_QP_UNDERLAY) ?
3619 mqp->underlay_qpn : 0;
3620 handler = _create_flow_rule(dev, ft_prio, flow_attr,
3621 dst, underlay_qpn, ucmd);
3622 }
3623 } else if (flow_attr->type == IB_FLOW_ATTR_ALL_DEFAULT ||
3624 flow_attr->type == IB_FLOW_ATTR_MC_DEFAULT) {
3625 handler = create_leftovers_rule(dev, ft_prio, flow_attr,
3626 dst);
3627 } else if (flow_attr->type == IB_FLOW_ATTR_SNIFFER) {
3628 handler = create_sniffer_rule(dev, ft_prio, ft_prio_tx, dst);
3629 } else {
3630 err = -EINVAL;
3631 goto destroy_ft;
3632 }
3633
3634 if (IS_ERR(handler)) {
3635 err = PTR_ERR(handler);
3636 handler = NULL;
3637 goto destroy_ft;
3638 }
3639
3640 mutex_unlock(&dev->flow_db->lock);
3641 kfree(dst);
3642 kfree(ucmd);
3643
3644 return &handler->ibflow;
3645
3646 destroy_ft:
3647 put_flow_table(dev, ft_prio, false);
3648 if (ft_prio_tx)
3649 put_flow_table(dev, ft_prio_tx, false);
3650 unlock:
3651 mutex_unlock(&dev->flow_db->lock);
3652 kfree(dst);
3653 free_ucmd:
3654 kfree(ucmd);
3655 return ERR_PTR(err);
3656 }
3657
3658 static struct mlx5_ib_flow_prio *
3659 _get_flow_table(struct mlx5_ib_dev *dev,
3660 struct mlx5_ib_flow_matcher *fs_matcher,
3661 bool mcast)
3662 {
3663 struct mlx5_flow_namespace *ns = NULL;
3664 struct mlx5_ib_flow_prio *prio;
3665 int max_table_size;
3666 u32 flags = 0;
3667 int priority;
3668
3669 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS) {
3670 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3671 log_max_ft_size));
3672 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev, decap))
3673 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_DECAP;
3674 if (MLX5_CAP_FLOWTABLE_NIC_RX(dev->mdev,
3675 reformat_l3_tunnel_to_l2))
3676 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3677 } else { /* Can only be MLX5_FLOW_NAMESPACE_EGRESS */
3678 max_table_size = BIT(MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev,
3679 log_max_ft_size));
3680 if (MLX5_CAP_FLOWTABLE_NIC_TX(dev->mdev, reformat))
3681 flags |= MLX5_FLOW_TABLE_TUNNEL_EN_REFORMAT;
3682 }
3683
3684 if (max_table_size < MLX5_FS_MAX_ENTRIES)
3685 return ERR_PTR(-ENOMEM);
3686
3687 if (mcast)
3688 priority = MLX5_IB_FLOW_MCAST_PRIO;
3689 else
3690 priority = ib_prio_to_core_prio(fs_matcher->priority, false);
3691
3692 ns = mlx5_get_flow_namespace(dev->mdev, fs_matcher->ns_type);
3693 if (!ns)
3694 return ERR_PTR(-ENOTSUPP);
3695
3696 if (fs_matcher->ns_type == MLX5_FLOW_NAMESPACE_BYPASS)
3697 prio = &dev->flow_db->prios[priority];
3698 else
3699 prio = &dev->flow_db->egress_prios[priority];
3700
3701 if (prio->flow_table)
3702 return prio;
3703
3704 return _get_prio(ns, prio, priority, MLX5_FS_MAX_ENTRIES,
3705 MLX5_FS_MAX_TYPES, flags);
3706 }
3707
3708 static struct mlx5_ib_flow_handler *
3709 _create_raw_flow_rule(struct mlx5_ib_dev *dev,
3710 struct mlx5_ib_flow_prio *ft_prio,
3711 struct mlx5_flow_destination *dst,
3712 struct mlx5_ib_flow_matcher *fs_matcher,
3713 struct mlx5_flow_act *flow_act,
3714 void *cmd_in, int inlen)
3715 {
3716 struct mlx5_ib_flow_handler *handler;
3717 struct mlx5_flow_spec *spec;
3718 struct mlx5_flow_table *ft = ft_prio->flow_table;
3719 int err = 0;
3720
3721 spec = kvzalloc(sizeof(*spec), GFP_KERNEL);
3722 handler = kzalloc(sizeof(*handler), GFP_KERNEL);
3723 if (!handler || !spec) {
3724 err = -ENOMEM;
3725 goto free;
3726 }
3727
3728 INIT_LIST_HEAD(&handler->list);
3729
3730 memcpy(spec->match_value, cmd_in, inlen);
3731 memcpy(spec->match_criteria, fs_matcher->matcher_mask.match_params,
3732 fs_matcher->mask_len);
3733 spec->match_criteria_enable = fs_matcher->match_criteria_enable;
3734
3735 handler->rule = mlx5_add_flow_rules(ft, spec,
3736 flow_act, dst, 1);
3737
3738 if (IS_ERR(handler->rule)) {
3739 err = PTR_ERR(handler->rule);
3740 goto free;
3741 }
3742
3743 ft_prio->refcount++;
3744 handler->prio = ft_prio;
3745 handler->dev = dev;
3746 ft_prio->flow_table = ft;
3747
3748 free:
3749 if (err)
3750 kfree(handler);
3751 kvfree(spec);
3752 return err ? ERR_PTR(err) : handler;
3753 }
3754
3755 static bool raw_fs_is_multicast(struct mlx5_ib_flow_matcher *fs_matcher,
3756 void *match_v)
3757 {
3758 void *match_c;
3759 void *match_v_set_lyr_2_4, *match_c_set_lyr_2_4;
3760 void *dmac, *dmac_mask;
3761 void *ipv4, *ipv4_mask;
3762
3763 if (!(fs_matcher->match_criteria_enable &
3764 (1 << MATCH_CRITERIA_ENABLE_OUTER_BIT)))
3765 return false;
3766
3767 match_c = fs_matcher->matcher_mask.match_params;
3768 match_v_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_v,
3769 outer_headers);
3770 match_c_set_lyr_2_4 = MLX5_ADDR_OF(fte_match_param, match_c,
3771 outer_headers);
3772
3773 dmac = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3774 dmac_47_16);
3775 dmac_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3776 dmac_47_16);
3777
3778 if (is_multicast_ether_addr(dmac) &&
3779 is_multicast_ether_addr(dmac_mask))
3780 return true;
3781
3782 ipv4 = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_v_set_lyr_2_4,
3783 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3784
3785 ipv4_mask = MLX5_ADDR_OF(fte_match_set_lyr_2_4, match_c_set_lyr_2_4,
3786 dst_ipv4_dst_ipv6.ipv4_layout.ipv4);
3787
3788 if (ipv4_is_multicast(*(__be32 *)(ipv4)) &&
3789 ipv4_is_multicast(*(__be32 *)(ipv4_mask)))
3790 return true;
3791
3792 return false;
3793 }
3794
3795 struct mlx5_ib_flow_handler *
3796 mlx5_ib_raw_fs_rule_add(struct mlx5_ib_dev *dev,
3797 struct mlx5_ib_flow_matcher *fs_matcher,
3798 struct mlx5_flow_act *flow_act,
3799 void *cmd_in, int inlen, int dest_id,
3800 int dest_type)
3801 {
3802 struct mlx5_flow_destination *dst;
3803 struct mlx5_ib_flow_prio *ft_prio;
3804 struct mlx5_ib_flow_handler *handler;
3805 bool mcast;
3806 int err;
3807
3808 if (fs_matcher->flow_type != MLX5_IB_FLOW_TYPE_NORMAL)
3809 return ERR_PTR(-EOPNOTSUPP);
3810
3811 if (fs_matcher->priority > MLX5_IB_FLOW_LAST_PRIO)
3812 return ERR_PTR(-ENOMEM);
3813
3814 dst = kzalloc(sizeof(*dst), GFP_KERNEL);
3815 if (!dst)
3816 return ERR_PTR(-ENOMEM);
3817
3818 mcast = raw_fs_is_multicast(fs_matcher, cmd_in);
3819 mutex_lock(&dev->flow_db->lock);
3820
3821 ft_prio = _get_flow_table(dev, fs_matcher, mcast);
3822 if (IS_ERR(ft_prio)) {
3823 err = PTR_ERR(ft_prio);
3824 goto unlock;
3825 }
3826
3827 if (dest_type == MLX5_FLOW_DESTINATION_TYPE_TIR) {
3828 dst->type = dest_type;
3829 dst->tir_num = dest_id;
3830 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3831 } else if (dest_type == MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE) {
3832 dst->type = MLX5_FLOW_DESTINATION_TYPE_FLOW_TABLE_NUM;
3833 dst->ft_num = dest_id;
3834 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_FWD_DEST;
3835 } else {
3836 dst->type = MLX5_FLOW_DESTINATION_TYPE_PORT;
3837 flow_act->action |= MLX5_FLOW_CONTEXT_ACTION_ALLOW;
3838 }
3839
3840 handler = _create_raw_flow_rule(dev, ft_prio, dst, fs_matcher, flow_act,
3841 cmd_in, inlen);
3842
3843 if (IS_ERR(handler)) {
3844 err = PTR_ERR(handler);
3845 goto destroy_ft;
3846 }
3847
3848 mutex_unlock(&dev->flow_db->lock);
3849 atomic_inc(&fs_matcher->usecnt);
3850 handler->flow_matcher = fs_matcher;
3851
3852 kfree(dst);
3853
3854 return handler;
3855
3856 destroy_ft:
3857 put_flow_table(dev, ft_prio, false);
3858 unlock:
3859 mutex_unlock(&dev->flow_db->lock);
3860 kfree(dst);
3861
3862 return ERR_PTR(err);
3863 }
3864
3865 static u32 mlx5_ib_flow_action_flags_to_accel_xfrm_flags(u32 mlx5_flags)
3866 {
3867 u32 flags = 0;
3868
3869 if (mlx5_flags & MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA)
3870 flags |= MLX5_ACCEL_XFRM_FLAG_REQUIRE_METADATA;
3871
3872 return flags;
3873 }
3874
3875 #define MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED MLX5_IB_UAPI_FLOW_ACTION_FLAGS_REQUIRE_METADATA
3876 static struct ib_flow_action *
3877 mlx5_ib_create_flow_action_esp(struct ib_device *device,
3878 const struct ib_flow_action_attrs_esp *attr,
3879 struct uverbs_attr_bundle *attrs)
3880 {
3881 struct mlx5_ib_dev *mdev = to_mdev(device);
3882 struct ib_uverbs_flow_action_esp_keymat_aes_gcm *aes_gcm;
3883 struct mlx5_accel_esp_xfrm_attrs accel_attrs = {};
3884 struct mlx5_ib_flow_action *action;
3885 u64 action_flags;
3886 u64 flags;
3887 int err = 0;
3888
3889 err = uverbs_get_flags64(
3890 &action_flags, attrs, MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
3891 ((MLX5_FLOW_ACTION_ESP_CREATE_LAST_SUPPORTED << 1) - 1));
3892 if (err)
3893 return ERR_PTR(err);
3894
3895 flags = mlx5_ib_flow_action_flags_to_accel_xfrm_flags(action_flags);
3896
3897 /* We current only support a subset of the standard features. Only a
3898 * keymat of type AES_GCM, with icv_len == 16, iv_algo == SEQ and esn
3899 * (with overlap). Full offload mode isn't supported.
3900 */
3901 if (!attr->keymat || attr->replay || attr->encap ||
3902 attr->spi || attr->seq || attr->tfc_pad ||
3903 attr->hard_limit_pkts ||
3904 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3905 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)))
3906 return ERR_PTR(-EOPNOTSUPP);
3907
3908 if (attr->keymat->protocol !=
3909 IB_UVERBS_FLOW_ACTION_ESP_KEYMAT_AES_GCM)
3910 return ERR_PTR(-EOPNOTSUPP);
3911
3912 aes_gcm = &attr->keymat->keymat.aes_gcm;
3913
3914 if (aes_gcm->icv_len != 16 ||
3915 aes_gcm->iv_algo != IB_UVERBS_FLOW_ACTION_IV_ALGO_SEQ)
3916 return ERR_PTR(-EOPNOTSUPP);
3917
3918 action = kmalloc(sizeof(*action), GFP_KERNEL);
3919 if (!action)
3920 return ERR_PTR(-ENOMEM);
3921
3922 action->esp_aes_gcm.ib_flags = attr->flags;
3923 memcpy(&accel_attrs.keymat.aes_gcm.aes_key, &aes_gcm->aes_key,
3924 sizeof(accel_attrs.keymat.aes_gcm.aes_key));
3925 accel_attrs.keymat.aes_gcm.key_len = aes_gcm->key_len * 8;
3926 memcpy(&accel_attrs.keymat.aes_gcm.salt, &aes_gcm->salt,
3927 sizeof(accel_attrs.keymat.aes_gcm.salt));
3928 memcpy(&accel_attrs.keymat.aes_gcm.seq_iv, &aes_gcm->iv,
3929 sizeof(accel_attrs.keymat.aes_gcm.seq_iv));
3930 accel_attrs.keymat.aes_gcm.icv_len = aes_gcm->icv_len * 8;
3931 accel_attrs.keymat.aes_gcm.iv_algo = MLX5_ACCEL_ESP_AES_GCM_IV_ALGO_SEQ;
3932 accel_attrs.keymat_type = MLX5_ACCEL_ESP_KEYMAT_AES_GCM;
3933
3934 accel_attrs.esn = attr->esn;
3935 if (attr->flags & IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED)
3936 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_TRIGGERED;
3937 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3938 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3939
3940 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ENCRYPT)
3941 accel_attrs.action |= MLX5_ACCEL_ESP_ACTION_ENCRYPT;
3942
3943 action->esp_aes_gcm.ctx =
3944 mlx5_accel_esp_create_xfrm(mdev->mdev, &accel_attrs, flags);
3945 if (IS_ERR(action->esp_aes_gcm.ctx)) {
3946 err = PTR_ERR(action->esp_aes_gcm.ctx);
3947 goto err_parse;
3948 }
3949
3950 action->esp_aes_gcm.ib_flags = attr->flags;
3951
3952 return &action->ib_action;
3953
3954 err_parse:
3955 kfree(action);
3956 return ERR_PTR(err);
3957 }
3958
3959 static int
3960 mlx5_ib_modify_flow_action_esp(struct ib_flow_action *action,
3961 const struct ib_flow_action_attrs_esp *attr,
3962 struct uverbs_attr_bundle *attrs)
3963 {
3964 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
3965 struct mlx5_accel_esp_xfrm_attrs accel_attrs;
3966 int err = 0;
3967
3968 if (attr->keymat || attr->replay || attr->encap ||
3969 attr->spi || attr->seq || attr->tfc_pad ||
3970 attr->hard_limit_pkts ||
3971 (attr->flags & ~(IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3972 IB_FLOW_ACTION_ESP_FLAGS_MOD_ESP_ATTRS |
3973 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)))
3974 return -EOPNOTSUPP;
3975
3976 /* Only the ESN value or the MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP can
3977 * be modified.
3978 */
3979 if (!(maction->esp_aes_gcm.ib_flags &
3980 IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED) &&
3981 attr->flags & (IB_FLOW_ACTION_ESP_FLAGS_ESN_TRIGGERED |
3982 IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW))
3983 return -EINVAL;
3984
3985 memcpy(&accel_attrs, &maction->esp_aes_gcm.ctx->attrs,
3986 sizeof(accel_attrs));
3987
3988 accel_attrs.esn = attr->esn;
3989 if (attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW)
3990 accel_attrs.flags |= MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3991 else
3992 accel_attrs.flags &= ~MLX5_ACCEL_ESP_FLAGS_ESN_STATE_OVERLAP;
3993
3994 err = mlx5_accel_esp_modify_xfrm(maction->esp_aes_gcm.ctx,
3995 &accel_attrs);
3996 if (err)
3997 return err;
3998
3999 maction->esp_aes_gcm.ib_flags &=
4000 ~IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4001 maction->esp_aes_gcm.ib_flags |=
4002 attr->flags & IB_UVERBS_FLOW_ACTION_ESP_FLAGS_ESN_NEW_WINDOW;
4003
4004 return 0;
4005 }
4006
4007 static int mlx5_ib_destroy_flow_action(struct ib_flow_action *action)
4008 {
4009 struct mlx5_ib_flow_action *maction = to_mflow_act(action);
4010
4011 switch (action->type) {
4012 case IB_FLOW_ACTION_ESP:
4013 /*
4014 * We only support aes_gcm by now, so we implicitly know this is
4015 * the underline crypto.
4016 */
4017 mlx5_accel_esp_destroy_xfrm(maction->esp_aes_gcm.ctx);
4018 break;
4019 case IB_FLOW_ACTION_UNSPECIFIED:
4020 mlx5_ib_destroy_flow_action_raw(maction);
4021 break;
4022 default:
4023 WARN_ON(true);
4024 break;
4025 }
4026
4027 kfree(maction);
4028 return 0;
4029 }
4030
4031 static int mlx5_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4032 {
4033 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4034 struct mlx5_ib_qp *mqp = to_mqp(ibqp);
4035 int err;
4036 u16 uid;
4037
4038 uid = ibqp->pd ?
4039 to_mpd(ibqp->pd)->uid : 0;
4040
4041 if (mqp->flags & MLX5_IB_QP_UNDERLAY) {
4042 mlx5_ib_dbg(dev, "Attaching a multi cast group to underlay QP is not supported\n");
4043 return -EOPNOTSUPP;
4044 }
4045
4046 err = mlx5_cmd_attach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4047 if (err)
4048 mlx5_ib_warn(dev, "failed attaching QPN 0x%x, MGID %pI6\n",
4049 ibqp->qp_num, gid->raw);
4050
4051 return err;
4052 }
4053
4054 static int mlx5_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
4055 {
4056 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4057 int err;
4058 u16 uid;
4059
4060 uid = ibqp->pd ?
4061 to_mpd(ibqp->pd)->uid : 0;
4062 err = mlx5_cmd_detach_mcg(dev->mdev, gid, ibqp->qp_num, uid);
4063 if (err)
4064 mlx5_ib_warn(dev, "failed detaching QPN 0x%x, MGID %pI6\n",
4065 ibqp->qp_num, gid->raw);
4066
4067 return err;
4068 }
4069
4070 static int init_node_data(struct mlx5_ib_dev *dev)
4071 {
4072 int err;
4073
4074 err = mlx5_query_node_desc(dev, dev->ib_dev.node_desc);
4075 if (err)
4076 return err;
4077
4078 dev->mdev->rev_id = dev->mdev->pdev->revision;
4079
4080 return mlx5_query_node_guid(dev, &dev->ib_dev.node_guid);
4081 }
4082
4083 static ssize_t show_fw_pages(struct device *device, struct device_attribute *attr,
4084 char *buf)
4085 {
4086 struct mlx5_ib_dev *dev =
4087 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4088
4089 return sprintf(buf, "%d\n", dev->mdev->priv.fw_pages);
4090 }
4091
4092 static ssize_t show_reg_pages(struct device *device,
4093 struct device_attribute *attr, char *buf)
4094 {
4095 struct mlx5_ib_dev *dev =
4096 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4097
4098 return sprintf(buf, "%d\n", atomic_read(&dev->mdev->priv.reg_pages));
4099 }
4100
4101 static ssize_t show_hca(struct device *device, struct device_attribute *attr,
4102 char *buf)
4103 {
4104 struct mlx5_ib_dev *dev =
4105 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4106 return sprintf(buf, "MT%d\n", dev->mdev->pdev->device);
4107 }
4108
4109 static ssize_t show_rev(struct device *device, struct device_attribute *attr,
4110 char *buf)
4111 {
4112 struct mlx5_ib_dev *dev =
4113 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4114 return sprintf(buf, "%x\n", dev->mdev->rev_id);
4115 }
4116
4117 static ssize_t show_board(struct device *device, struct device_attribute *attr,
4118 char *buf)
4119 {
4120 struct mlx5_ib_dev *dev =
4121 container_of(device, struct mlx5_ib_dev, ib_dev.dev);
4122 return sprintf(buf, "%.*s\n", MLX5_BOARD_ID_LEN,
4123 dev->mdev->board_id);
4124 }
4125
4126 static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
4127 static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
4128 static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
4129 static DEVICE_ATTR(fw_pages, S_IRUGO, show_fw_pages, NULL);
4130 static DEVICE_ATTR(reg_pages, S_IRUGO, show_reg_pages, NULL);
4131
4132 static struct device_attribute *mlx5_class_attributes[] = {
4133 &dev_attr_hw_rev,
4134 &dev_attr_hca_type,
4135 &dev_attr_board_id,
4136 &dev_attr_fw_pages,
4137 &dev_attr_reg_pages,
4138 };
4139
4140 static void pkey_change_handler(struct work_struct *work)
4141 {
4142 struct mlx5_ib_port_resources *ports =
4143 container_of(work, struct mlx5_ib_port_resources,
4144 pkey_change_work);
4145
4146 mutex_lock(&ports->devr->mutex);
4147 mlx5_ib_gsi_pkey_change(ports->gsi);
4148 mutex_unlock(&ports->devr->mutex);
4149 }
4150
4151 static void mlx5_ib_handle_internal_error(struct mlx5_ib_dev *ibdev)
4152 {
4153 struct mlx5_ib_qp *mqp;
4154 struct mlx5_ib_cq *send_mcq, *recv_mcq;
4155 struct mlx5_core_cq *mcq;
4156 struct list_head cq_armed_list;
4157 unsigned long flags_qp;
4158 unsigned long flags_cq;
4159 unsigned long flags;
4160
4161 INIT_LIST_HEAD(&cq_armed_list);
4162
4163 /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
4164 spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
4165 list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
4166 spin_lock_irqsave(&mqp->sq.lock, flags_qp);
4167 if (mqp->sq.tail != mqp->sq.head) {
4168 send_mcq = to_mcq(mqp->ibqp.send_cq);
4169 spin_lock_irqsave(&send_mcq->lock, flags_cq);
4170 if (send_mcq->mcq.comp &&
4171 mqp->ibqp.send_cq->comp_handler) {
4172 if (!send_mcq->mcq.reset_notify_added) {
4173 send_mcq->mcq.reset_notify_added = 1;
4174 list_add_tail(&send_mcq->mcq.reset_notify,
4175 &cq_armed_list);
4176 }
4177 }
4178 spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
4179 }
4180 spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
4181 spin_lock_irqsave(&mqp->rq.lock, flags_qp);
4182 /* no handling is needed for SRQ */
4183 if (!mqp->ibqp.srq) {
4184 if (mqp->rq.tail != mqp->rq.head) {
4185 recv_mcq = to_mcq(mqp->ibqp.recv_cq);
4186 spin_lock_irqsave(&recv_mcq->lock, flags_cq);
4187 if (recv_mcq->mcq.comp &&
4188 mqp->ibqp.recv_cq->comp_handler) {
4189 if (!recv_mcq->mcq.reset_notify_added) {
4190 recv_mcq->mcq.reset_notify_added = 1;
4191 list_add_tail(&recv_mcq->mcq.reset_notify,
4192 &cq_armed_list);
4193 }
4194 }
4195 spin_unlock_irqrestore(&recv_mcq->lock,
4196 flags_cq);
4197 }
4198 }
4199 spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
4200 }
4201 /*At that point all inflight post send were put to be executed as of we
4202 * lock/unlock above locks Now need to arm all involved CQs.
4203 */
4204 list_for_each_entry(mcq, &cq_armed_list, reset_notify) {
4205 mcq->comp(mcq);
4206 }
4207 spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
4208 }
4209
4210 static void delay_drop_handler(struct work_struct *work)
4211 {
4212 int err;
4213 struct mlx5_ib_delay_drop *delay_drop =
4214 container_of(work, struct mlx5_ib_delay_drop,
4215 delay_drop_work);
4216
4217 atomic_inc(&delay_drop->events_cnt);
4218
4219 mutex_lock(&delay_drop->lock);
4220 err = mlx5_core_set_delay_drop(delay_drop->dev->mdev,
4221 delay_drop->timeout);
4222 if (err) {
4223 mlx5_ib_warn(delay_drop->dev, "Failed to set delay drop, timeout=%u\n",
4224 delay_drop->timeout);
4225 delay_drop->activate = false;
4226 }
4227 mutex_unlock(&delay_drop->lock);
4228 }
4229
4230 static void mlx5_ib_handle_event(struct work_struct *_work)
4231 {
4232 struct mlx5_ib_event_work *work =
4233 container_of(_work, struct mlx5_ib_event_work, work);
4234 struct mlx5_ib_dev *ibdev;
4235 struct ib_event ibev;
4236 bool fatal = false;
4237 u8 port = (u8)work->param;
4238
4239 if (mlx5_core_is_mp_slave(work->dev)) {
4240 ibdev = mlx5_ib_get_ibdev_from_mpi(work->context);
4241 if (!ibdev)
4242 goto out;
4243 } else {
4244 ibdev = work->context;
4245 }
4246
4247 switch (work->event) {
4248 case MLX5_DEV_EVENT_SYS_ERROR:
4249 ibev.event = IB_EVENT_DEVICE_FATAL;
4250 mlx5_ib_handle_internal_error(ibdev);
4251 fatal = true;
4252 break;
4253
4254 case MLX5_DEV_EVENT_PORT_UP:
4255 case MLX5_DEV_EVENT_PORT_DOWN:
4256 case MLX5_DEV_EVENT_PORT_INITIALIZED:
4257 /* In RoCE, port up/down events are handled in
4258 * mlx5_netdev_event().
4259 */
4260 if (mlx5_ib_port_link_layer(&ibdev->ib_dev, port) ==
4261 IB_LINK_LAYER_ETHERNET)
4262 goto out;
4263
4264 ibev.event = (work->event == MLX5_DEV_EVENT_PORT_UP) ?
4265 IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
4266 break;
4267
4268 case MLX5_DEV_EVENT_LID_CHANGE:
4269 ibev.event = IB_EVENT_LID_CHANGE;
4270 break;
4271
4272 case MLX5_DEV_EVENT_PKEY_CHANGE:
4273 ibev.event = IB_EVENT_PKEY_CHANGE;
4274 schedule_work(&ibdev->devr.ports[port - 1].pkey_change_work);
4275 break;
4276
4277 case MLX5_DEV_EVENT_GUID_CHANGE:
4278 ibev.event = IB_EVENT_GID_CHANGE;
4279 break;
4280
4281 case MLX5_DEV_EVENT_CLIENT_REREG:
4282 ibev.event = IB_EVENT_CLIENT_REREGISTER;
4283 break;
4284 case MLX5_DEV_EVENT_DELAY_DROP_TIMEOUT:
4285 schedule_work(&ibdev->delay_drop.delay_drop_work);
4286 goto out;
4287 default:
4288 goto out;
4289 }
4290
4291 ibev.device = &ibdev->ib_dev;
4292 ibev.element.port_num = port;
4293
4294 if (!rdma_is_port_valid(&ibdev->ib_dev, port)) {
4295 mlx5_ib_warn(ibdev, "warning: event on port %d\n", port);
4296 goto out;
4297 }
4298
4299 if (ibdev->ib_active)
4300 ib_dispatch_event(&ibev);
4301
4302 if (fatal)
4303 ibdev->ib_active = false;
4304 out:
4305 kfree(work);
4306 }
4307
4308 static void mlx5_ib_event(struct mlx5_core_dev *dev, void *context,
4309 enum mlx5_dev_event event, unsigned long param)
4310 {
4311 struct mlx5_ib_event_work *work;
4312
4313 work = kmalloc(sizeof(*work), GFP_ATOMIC);
4314 if (!work)
4315 return;
4316
4317 INIT_WORK(&work->work, mlx5_ib_handle_event);
4318 work->dev = dev;
4319 work->param = param;
4320 work->context = context;
4321 work->event = event;
4322
4323 queue_work(mlx5_ib_event_wq, &work->work);
4324 }
4325
4326 static int set_has_smi_cap(struct mlx5_ib_dev *dev)
4327 {
4328 struct mlx5_hca_vport_context vport_ctx;
4329 int err;
4330 int port;
4331
4332 for (port = 1; port <= dev->num_ports; port++) {
4333 dev->mdev->port_caps[port - 1].has_smi = false;
4334 if (MLX5_CAP_GEN(dev->mdev, port_type) ==
4335 MLX5_CAP_PORT_TYPE_IB) {
4336 if (MLX5_CAP_GEN(dev->mdev, ib_virt)) {
4337 err = mlx5_query_hca_vport_context(dev->mdev, 0,
4338 port, 0,
4339 &vport_ctx);
4340 if (err) {
4341 mlx5_ib_err(dev, "query_hca_vport_context for port=%d failed %d\n",
4342 port, err);
4343 return err;
4344 }
4345 dev->mdev->port_caps[port - 1].has_smi =
4346 vport_ctx.has_smi;
4347 } else {
4348 dev->mdev->port_caps[port - 1].has_smi = true;
4349 }
4350 }
4351 }
4352 return 0;
4353 }
4354
4355 static void get_ext_port_caps(struct mlx5_ib_dev *dev)
4356 {
4357 int port;
4358
4359 for (port = 1; port <= dev->num_ports; port++)
4360 mlx5_query_ext_port_caps(dev, port);
4361 }
4362
4363 static int get_port_caps(struct mlx5_ib_dev *dev, u8 port)
4364 {
4365 struct ib_device_attr *dprops = NULL;
4366 struct ib_port_attr *pprops = NULL;
4367 int err = -ENOMEM;
4368 struct ib_udata uhw = {.inlen = 0, .outlen = 0};
4369
4370 pprops = kmalloc(sizeof(*pprops), GFP_KERNEL);
4371 if (!pprops)
4372 goto out;
4373
4374 dprops = kmalloc(sizeof(*dprops), GFP_KERNEL);
4375 if (!dprops)
4376 goto out;
4377
4378 err = set_has_smi_cap(dev);
4379 if (err)
4380 goto out;
4381
4382 err = mlx5_ib_query_device(&dev->ib_dev, dprops, &uhw);
4383 if (err) {
4384 mlx5_ib_warn(dev, "query_device failed %d\n", err);
4385 goto out;
4386 }
4387
4388 memset(pprops, 0, sizeof(*pprops));
4389 err = mlx5_ib_query_port(&dev->ib_dev, port, pprops);
4390 if (err) {
4391 mlx5_ib_warn(dev, "query_port %d failed %d\n",
4392 port, err);
4393 goto out;
4394 }
4395
4396 dev->mdev->port_caps[port - 1].pkey_table_len =
4397 dprops->max_pkeys;
4398 dev->mdev->port_caps[port - 1].gid_table_len =
4399 pprops->gid_tbl_len;
4400 mlx5_ib_dbg(dev, "port %d: pkey_table_len %d, gid_table_len %d\n",
4401 port, dprops->max_pkeys, pprops->gid_tbl_len);
4402
4403 out:
4404 kfree(pprops);
4405 kfree(dprops);
4406
4407 return err;
4408 }
4409
4410 static void destroy_umrc_res(struct mlx5_ib_dev *dev)
4411 {
4412 int err;
4413
4414 err = mlx5_mr_cache_cleanup(dev);
4415 if (err)
4416 mlx5_ib_warn(dev, "mr cache cleanup failed\n");
4417
4418 if (dev->umrc.qp)
4419 mlx5_ib_destroy_qp(dev->umrc.qp);
4420 if (dev->umrc.cq)
4421 ib_free_cq(dev->umrc.cq);
4422 if (dev->umrc.pd)
4423 ib_dealloc_pd(dev->umrc.pd);
4424 }
4425
4426 enum {
4427 MAX_UMR_WR = 128,
4428 };
4429
4430 static int create_umr_res(struct mlx5_ib_dev *dev)
4431 {
4432 struct ib_qp_init_attr *init_attr = NULL;
4433 struct ib_qp_attr *attr = NULL;
4434 struct ib_pd *pd;
4435 struct ib_cq *cq;
4436 struct ib_qp *qp;
4437 int ret;
4438
4439 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
4440 init_attr = kzalloc(sizeof(*init_attr), GFP_KERNEL);
4441 if (!attr || !init_attr) {
4442 ret = -ENOMEM;
4443 goto error_0;
4444 }
4445
4446 pd = ib_alloc_pd(&dev->ib_dev, 0);
4447 if (IS_ERR(pd)) {
4448 mlx5_ib_dbg(dev, "Couldn't create PD for sync UMR QP\n");
4449 ret = PTR_ERR(pd);
4450 goto error_0;
4451 }
4452
4453 cq = ib_alloc_cq(&dev->ib_dev, NULL, 128, 0, IB_POLL_SOFTIRQ);
4454 if (IS_ERR(cq)) {
4455 mlx5_ib_dbg(dev, "Couldn't create CQ for sync UMR QP\n");
4456 ret = PTR_ERR(cq);
4457 goto error_2;
4458 }
4459
4460 init_attr->send_cq = cq;
4461 init_attr->recv_cq = cq;
4462 init_attr->sq_sig_type = IB_SIGNAL_ALL_WR;
4463 init_attr->cap.max_send_wr = MAX_UMR_WR;
4464 init_attr->cap.max_send_sge = 1;
4465 init_attr->qp_type = MLX5_IB_QPT_REG_UMR;
4466 init_attr->port_num = 1;
4467 qp = mlx5_ib_create_qp(pd, init_attr, NULL);
4468 if (IS_ERR(qp)) {
4469 mlx5_ib_dbg(dev, "Couldn't create sync UMR QP\n");
4470 ret = PTR_ERR(qp);
4471 goto error_3;
4472 }
4473 qp->device = &dev->ib_dev;
4474 qp->real_qp = qp;
4475 qp->uobject = NULL;
4476 qp->qp_type = MLX5_IB_QPT_REG_UMR;
4477 qp->send_cq = init_attr->send_cq;
4478 qp->recv_cq = init_attr->recv_cq;
4479
4480 attr->qp_state = IB_QPS_INIT;
4481 attr->port_num = 1;
4482 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE | IB_QP_PKEY_INDEX |
4483 IB_QP_PORT, NULL);
4484 if (ret) {
4485 mlx5_ib_dbg(dev, "Couldn't modify UMR QP\n");
4486 goto error_4;
4487 }
4488
4489 memset(attr, 0, sizeof(*attr));
4490 attr->qp_state = IB_QPS_RTR;
4491 attr->path_mtu = IB_MTU_256;
4492
4493 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4494 if (ret) {
4495 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rtr\n");
4496 goto error_4;
4497 }
4498
4499 memset(attr, 0, sizeof(*attr));
4500 attr->qp_state = IB_QPS_RTS;
4501 ret = mlx5_ib_modify_qp(qp, attr, IB_QP_STATE, NULL);
4502 if (ret) {
4503 mlx5_ib_dbg(dev, "Couldn't modify umr QP to rts\n");
4504 goto error_4;
4505 }
4506
4507 dev->umrc.qp = qp;
4508 dev->umrc.cq = cq;
4509 dev->umrc.pd = pd;
4510
4511 sema_init(&dev->umrc.sem, MAX_UMR_WR);
4512 ret = mlx5_mr_cache_init(dev);
4513 if (ret) {
4514 mlx5_ib_warn(dev, "mr cache init failed %d\n", ret);
4515 goto error_4;
4516 }
4517
4518 kfree(attr);
4519 kfree(init_attr);
4520
4521 return 0;
4522
4523 error_4:
4524 mlx5_ib_destroy_qp(qp);
4525 dev->umrc.qp = NULL;
4526
4527 error_3:
4528 ib_free_cq(cq);
4529 dev->umrc.cq = NULL;
4530
4531 error_2:
4532 ib_dealloc_pd(pd);
4533 dev->umrc.pd = NULL;
4534
4535 error_0:
4536 kfree(attr);
4537 kfree(init_attr);
4538 return ret;
4539 }
4540
4541 static u8 mlx5_get_umr_fence(u8 umr_fence_cap)
4542 {
4543 switch (umr_fence_cap) {
4544 case MLX5_CAP_UMR_FENCE_NONE:
4545 return MLX5_FENCE_MODE_NONE;
4546 case MLX5_CAP_UMR_FENCE_SMALL:
4547 return MLX5_FENCE_MODE_INITIATOR_SMALL;
4548 default:
4549 return MLX5_FENCE_MODE_STRONG_ORDERING;
4550 }
4551 }
4552
4553 static int create_dev_resources(struct mlx5_ib_resources *devr)
4554 {
4555 struct ib_srq_init_attr attr;
4556 struct mlx5_ib_dev *dev;
4557 struct ib_cq_init_attr cq_attr = {.cqe = 1};
4558 int port;
4559 int ret = 0;
4560
4561 dev = container_of(devr, struct mlx5_ib_dev, devr);
4562
4563 mutex_init(&devr->mutex);
4564
4565 devr->p0 = mlx5_ib_alloc_pd(&dev->ib_dev, NULL, NULL);
4566 if (IS_ERR(devr->p0)) {
4567 ret = PTR_ERR(devr->p0);
4568 goto error0;
4569 }
4570 devr->p0->device = &dev->ib_dev;
4571 devr->p0->uobject = NULL;
4572 atomic_set(&devr->p0->usecnt, 0);
4573
4574 devr->c0 = mlx5_ib_create_cq(&dev->ib_dev, &cq_attr, NULL, NULL);
4575 if (IS_ERR(devr->c0)) {
4576 ret = PTR_ERR(devr->c0);
4577 goto error1;
4578 }
4579 devr->c0->device = &dev->ib_dev;
4580 devr->c0->uobject = NULL;
4581 devr->c0->comp_handler = NULL;
4582 devr->c0->event_handler = NULL;
4583 devr->c0->cq_context = NULL;
4584 atomic_set(&devr->c0->usecnt, 0);
4585
4586 devr->x0 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4587 if (IS_ERR(devr->x0)) {
4588 ret = PTR_ERR(devr->x0);
4589 goto error2;
4590 }
4591 devr->x0->device = &dev->ib_dev;
4592 devr->x0->inode = NULL;
4593 atomic_set(&devr->x0->usecnt, 0);
4594 mutex_init(&devr->x0->tgt_qp_mutex);
4595 INIT_LIST_HEAD(&devr->x0->tgt_qp_list);
4596
4597 devr->x1 = mlx5_ib_alloc_xrcd(&dev->ib_dev, NULL, NULL);
4598 if (IS_ERR(devr->x1)) {
4599 ret = PTR_ERR(devr->x1);
4600 goto error3;
4601 }
4602 devr->x1->device = &dev->ib_dev;
4603 devr->x1->inode = NULL;
4604 atomic_set(&devr->x1->usecnt, 0);
4605 mutex_init(&devr->x1->tgt_qp_mutex);
4606 INIT_LIST_HEAD(&devr->x1->tgt_qp_list);
4607
4608 memset(&attr, 0, sizeof(attr));
4609 attr.attr.max_sge = 1;
4610 attr.attr.max_wr = 1;
4611 attr.srq_type = IB_SRQT_XRC;
4612 attr.ext.cq = devr->c0;
4613 attr.ext.xrc.xrcd = devr->x0;
4614
4615 devr->s0 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4616 if (IS_ERR(devr->s0)) {
4617 ret = PTR_ERR(devr->s0);
4618 goto error4;
4619 }
4620 devr->s0->device = &dev->ib_dev;
4621 devr->s0->pd = devr->p0;
4622 devr->s0->uobject = NULL;
4623 devr->s0->event_handler = NULL;
4624 devr->s0->srq_context = NULL;
4625 devr->s0->srq_type = IB_SRQT_XRC;
4626 devr->s0->ext.xrc.xrcd = devr->x0;
4627 devr->s0->ext.cq = devr->c0;
4628 atomic_inc(&devr->s0->ext.xrc.xrcd->usecnt);
4629 atomic_inc(&devr->s0->ext.cq->usecnt);
4630 atomic_inc(&devr->p0->usecnt);
4631 atomic_set(&devr->s0->usecnt, 0);
4632
4633 memset(&attr, 0, sizeof(attr));
4634 attr.attr.max_sge = 1;
4635 attr.attr.max_wr = 1;
4636 attr.srq_type = IB_SRQT_BASIC;
4637 devr->s1 = mlx5_ib_create_srq(devr->p0, &attr, NULL);
4638 if (IS_ERR(devr->s1)) {
4639 ret = PTR_ERR(devr->s1);
4640 goto error5;
4641 }
4642 devr->s1->device = &dev->ib_dev;
4643 devr->s1->pd = devr->p0;
4644 devr->s1->uobject = NULL;
4645 devr->s1->event_handler = NULL;
4646 devr->s1->srq_context = NULL;
4647 devr->s1->srq_type = IB_SRQT_BASIC;
4648 devr->s1->ext.cq = devr->c0;
4649 atomic_inc(&devr->p0->usecnt);
4650 atomic_set(&devr->s1->usecnt, 0);
4651
4652 for (port = 0; port < ARRAY_SIZE(devr->ports); ++port) {
4653 INIT_WORK(&devr->ports[port].pkey_change_work,
4654 pkey_change_handler);
4655 devr->ports[port].devr = devr;
4656 }
4657
4658 return 0;
4659
4660 error5:
4661 mlx5_ib_destroy_srq(devr->s0);
4662 error4:
4663 mlx5_ib_dealloc_xrcd(devr->x1);
4664 error3:
4665 mlx5_ib_dealloc_xrcd(devr->x0);
4666 error2:
4667 mlx5_ib_destroy_cq(devr->c0);
4668 error1:
4669 mlx5_ib_dealloc_pd(devr->p0);
4670 error0:
4671 return ret;
4672 }
4673
4674 static void destroy_dev_resources(struct mlx5_ib_resources *devr)
4675 {
4676 struct mlx5_ib_dev *dev =
4677 container_of(devr, struct mlx5_ib_dev, devr);
4678 int port;
4679
4680 mlx5_ib_destroy_srq(devr->s1);
4681 mlx5_ib_destroy_srq(devr->s0);
4682 mlx5_ib_dealloc_xrcd(devr->x0);
4683 mlx5_ib_dealloc_xrcd(devr->x1);
4684 mlx5_ib_destroy_cq(devr->c0);
4685 mlx5_ib_dealloc_pd(devr->p0);
4686
4687 /* Make sure no change P_Key work items are still executing */
4688 for (port = 0; port < dev->num_ports; ++port)
4689 cancel_work_sync(&devr->ports[port].pkey_change_work);
4690 }
4691
4692 static u32 get_core_cap_flags(struct ib_device *ibdev,
4693 struct mlx5_hca_vport_context *rep)
4694 {
4695 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4696 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, 1);
4697 u8 l3_type_cap = MLX5_CAP_ROCE(dev->mdev, l3_type);
4698 u8 roce_version_cap = MLX5_CAP_ROCE(dev->mdev, roce_version);
4699 bool raw_support = !mlx5_core_mp_enabled(dev->mdev);
4700 u32 ret = 0;
4701
4702 if (rep->grh_required)
4703 ret |= RDMA_CORE_CAP_IB_GRH_REQUIRED;
4704
4705 if (ll == IB_LINK_LAYER_INFINIBAND)
4706 return ret | RDMA_CORE_PORT_IBA_IB;
4707
4708 if (raw_support)
4709 ret |= RDMA_CORE_PORT_RAW_PACKET;
4710
4711 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV4_CAP))
4712 return ret;
4713
4714 if (!(l3_type_cap & MLX5_ROCE_L3_TYPE_IPV6_CAP))
4715 return ret;
4716
4717 if (roce_version_cap & MLX5_ROCE_VERSION_1_CAP)
4718 ret |= RDMA_CORE_PORT_IBA_ROCE;
4719
4720 if (roce_version_cap & MLX5_ROCE_VERSION_2_CAP)
4721 ret |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
4722
4723 return ret;
4724 }
4725
4726 static int mlx5_port_immutable(struct ib_device *ibdev, u8 port_num,
4727 struct ib_port_immutable *immutable)
4728 {
4729 struct ib_port_attr attr;
4730 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4731 enum rdma_link_layer ll = mlx5_ib_port_link_layer(ibdev, port_num);
4732 struct mlx5_hca_vport_context rep = {0};
4733 int err;
4734
4735 err = ib_query_port(ibdev, port_num, &attr);
4736 if (err)
4737 return err;
4738
4739 if (ll == IB_LINK_LAYER_INFINIBAND) {
4740 err = mlx5_query_hca_vport_context(dev->mdev, 0, port_num, 0,
4741 &rep);
4742 if (err)
4743 return err;
4744 }
4745
4746 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4747 immutable->gid_tbl_len = attr.gid_tbl_len;
4748 immutable->core_cap_flags = get_core_cap_flags(ibdev, &rep);
4749 if ((ll == IB_LINK_LAYER_INFINIBAND) || MLX5_CAP_GEN(dev->mdev, roce))
4750 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
4751
4752 return 0;
4753 }
4754
4755 static int mlx5_port_rep_immutable(struct ib_device *ibdev, u8 port_num,
4756 struct ib_port_immutable *immutable)
4757 {
4758 struct ib_port_attr attr;
4759 int err;
4760
4761 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4762
4763 err = ib_query_port(ibdev, port_num, &attr);
4764 if (err)
4765 return err;
4766
4767 immutable->pkey_tbl_len = attr.pkey_tbl_len;
4768 immutable->gid_tbl_len = attr.gid_tbl_len;
4769 immutable->core_cap_flags = RDMA_CORE_PORT_RAW_PACKET;
4770
4771 return 0;
4772 }
4773
4774 static void get_dev_fw_str(struct ib_device *ibdev, char *str)
4775 {
4776 struct mlx5_ib_dev *dev =
4777 container_of(ibdev, struct mlx5_ib_dev, ib_dev);
4778 snprintf(str, IB_FW_VERSION_NAME_MAX, "%d.%d.%04d",
4779 fw_rev_maj(dev->mdev), fw_rev_min(dev->mdev),
4780 fw_rev_sub(dev->mdev));
4781 }
4782
4783 static int mlx5_eth_lag_init(struct mlx5_ib_dev *dev)
4784 {
4785 struct mlx5_core_dev *mdev = dev->mdev;
4786 struct mlx5_flow_namespace *ns = mlx5_get_flow_namespace(mdev,
4787 MLX5_FLOW_NAMESPACE_LAG);
4788 struct mlx5_flow_table *ft;
4789 int err;
4790
4791 if (!ns || !mlx5_lag_is_active(mdev))
4792 return 0;
4793
4794 err = mlx5_cmd_create_vport_lag(mdev);
4795 if (err)
4796 return err;
4797
4798 ft = mlx5_create_lag_demux_flow_table(ns, 0, 0);
4799 if (IS_ERR(ft)) {
4800 err = PTR_ERR(ft);
4801 goto err_destroy_vport_lag;
4802 }
4803
4804 dev->flow_db->lag_demux_ft = ft;
4805 return 0;
4806
4807 err_destroy_vport_lag:
4808 mlx5_cmd_destroy_vport_lag(mdev);
4809 return err;
4810 }
4811
4812 static void mlx5_eth_lag_cleanup(struct mlx5_ib_dev *dev)
4813 {
4814 struct mlx5_core_dev *mdev = dev->mdev;
4815
4816 if (dev->flow_db->lag_demux_ft) {
4817 mlx5_destroy_flow_table(dev->flow_db->lag_demux_ft);
4818 dev->flow_db->lag_demux_ft = NULL;
4819
4820 mlx5_cmd_destroy_vport_lag(mdev);
4821 }
4822 }
4823
4824 static int mlx5_add_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4825 {
4826 int err;
4827
4828 dev->roce[port_num].nb.notifier_call = mlx5_netdev_event;
4829 err = register_netdevice_notifier(&dev->roce[port_num].nb);
4830 if (err) {
4831 dev->roce[port_num].nb.notifier_call = NULL;
4832 return err;
4833 }
4834
4835 return 0;
4836 }
4837
4838 static void mlx5_remove_netdev_notifier(struct mlx5_ib_dev *dev, u8 port_num)
4839 {
4840 if (dev->roce[port_num].nb.notifier_call) {
4841 unregister_netdevice_notifier(&dev->roce[port_num].nb);
4842 dev->roce[port_num].nb.notifier_call = NULL;
4843 }
4844 }
4845
4846 static int mlx5_enable_eth(struct mlx5_ib_dev *dev)
4847 {
4848 int err;
4849
4850 if (MLX5_CAP_GEN(dev->mdev, roce)) {
4851 err = mlx5_nic_vport_enable_roce(dev->mdev);
4852 if (err)
4853 return err;
4854 }
4855
4856 err = mlx5_eth_lag_init(dev);
4857 if (err)
4858 goto err_disable_roce;
4859
4860 return 0;
4861
4862 err_disable_roce:
4863 if (MLX5_CAP_GEN(dev->mdev, roce))
4864 mlx5_nic_vport_disable_roce(dev->mdev);
4865
4866 return err;
4867 }
4868
4869 static void mlx5_disable_eth(struct mlx5_ib_dev *dev)
4870 {
4871 mlx5_eth_lag_cleanup(dev);
4872 if (MLX5_CAP_GEN(dev->mdev, roce))
4873 mlx5_nic_vport_disable_roce(dev->mdev);
4874 }
4875
4876 struct mlx5_ib_counter {
4877 const char *name;
4878 size_t offset;
4879 };
4880
4881 #define INIT_Q_COUNTER(_name) \
4882 { .name = #_name, .offset = MLX5_BYTE_OFF(query_q_counter_out, _name)}
4883
4884 static const struct mlx5_ib_counter basic_q_cnts[] = {
4885 INIT_Q_COUNTER(rx_write_requests),
4886 INIT_Q_COUNTER(rx_read_requests),
4887 INIT_Q_COUNTER(rx_atomic_requests),
4888 INIT_Q_COUNTER(out_of_buffer),
4889 };
4890
4891 static const struct mlx5_ib_counter out_of_seq_q_cnts[] = {
4892 INIT_Q_COUNTER(out_of_sequence),
4893 };
4894
4895 static const struct mlx5_ib_counter retrans_q_cnts[] = {
4896 INIT_Q_COUNTER(duplicate_request),
4897 INIT_Q_COUNTER(rnr_nak_retry_err),
4898 INIT_Q_COUNTER(packet_seq_err),
4899 INIT_Q_COUNTER(implied_nak_seq_err),
4900 INIT_Q_COUNTER(local_ack_timeout_err),
4901 };
4902
4903 #define INIT_CONG_COUNTER(_name) \
4904 { .name = #_name, .offset = \
4905 MLX5_BYTE_OFF(query_cong_statistics_out, _name ## _high)}
4906
4907 static const struct mlx5_ib_counter cong_cnts[] = {
4908 INIT_CONG_COUNTER(rp_cnp_ignored),
4909 INIT_CONG_COUNTER(rp_cnp_handled),
4910 INIT_CONG_COUNTER(np_ecn_marked_roce_packets),
4911 INIT_CONG_COUNTER(np_cnp_sent),
4912 };
4913
4914 static const struct mlx5_ib_counter extended_err_cnts[] = {
4915 INIT_Q_COUNTER(resp_local_length_error),
4916 INIT_Q_COUNTER(resp_cqe_error),
4917 INIT_Q_COUNTER(req_cqe_error),
4918 INIT_Q_COUNTER(req_remote_invalid_request),
4919 INIT_Q_COUNTER(req_remote_access_errors),
4920 INIT_Q_COUNTER(resp_remote_access_errors),
4921 INIT_Q_COUNTER(resp_cqe_flush_error),
4922 INIT_Q_COUNTER(req_cqe_flush_error),
4923 };
4924
4925 #define INIT_EXT_PPCNT_COUNTER(_name) \
4926 { .name = #_name, .offset = \
4927 MLX5_BYTE_OFF(ppcnt_reg, \
4928 counter_set.eth_extended_cntrs_grp_data_layout._name##_high)}
4929
4930 static const struct mlx5_ib_counter ext_ppcnt_cnts[] = {
4931 INIT_EXT_PPCNT_COUNTER(rx_icrc_encapsulated),
4932 };
4933
4934 static void mlx5_ib_dealloc_counters(struct mlx5_ib_dev *dev)
4935 {
4936 int i;
4937
4938 for (i = 0; i < dev->num_ports; i++) {
4939 if (dev->port[i].cnts.set_id_valid)
4940 mlx5_core_dealloc_q_counter(dev->mdev,
4941 dev->port[i].cnts.set_id);
4942 kfree(dev->port[i].cnts.names);
4943 kfree(dev->port[i].cnts.offsets);
4944 }
4945 }
4946
4947 static int __mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev,
4948 struct mlx5_ib_counters *cnts)
4949 {
4950 u32 num_counters;
4951
4952 num_counters = ARRAY_SIZE(basic_q_cnts);
4953
4954 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt))
4955 num_counters += ARRAY_SIZE(out_of_seq_q_cnts);
4956
4957 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters))
4958 num_counters += ARRAY_SIZE(retrans_q_cnts);
4959
4960 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters))
4961 num_counters += ARRAY_SIZE(extended_err_cnts);
4962
4963 cnts->num_q_counters = num_counters;
4964
4965 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
4966 cnts->num_cong_counters = ARRAY_SIZE(cong_cnts);
4967 num_counters += ARRAY_SIZE(cong_cnts);
4968 }
4969 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
4970 cnts->num_ext_ppcnt_counters = ARRAY_SIZE(ext_ppcnt_cnts);
4971 num_counters += ARRAY_SIZE(ext_ppcnt_cnts);
4972 }
4973 cnts->names = kcalloc(num_counters, sizeof(cnts->names), GFP_KERNEL);
4974 if (!cnts->names)
4975 return -ENOMEM;
4976
4977 cnts->offsets = kcalloc(num_counters,
4978 sizeof(cnts->offsets), GFP_KERNEL);
4979 if (!cnts->offsets)
4980 goto err_names;
4981
4982 return 0;
4983
4984 err_names:
4985 kfree(cnts->names);
4986 cnts->names = NULL;
4987 return -ENOMEM;
4988 }
4989
4990 static void mlx5_ib_fill_counters(struct mlx5_ib_dev *dev,
4991 const char **names,
4992 size_t *offsets)
4993 {
4994 int i;
4995 int j = 0;
4996
4997 for (i = 0; i < ARRAY_SIZE(basic_q_cnts); i++, j++) {
4998 names[j] = basic_q_cnts[i].name;
4999 offsets[j] = basic_q_cnts[i].offset;
5000 }
5001
5002 if (MLX5_CAP_GEN(dev->mdev, out_of_seq_cnt)) {
5003 for (i = 0; i < ARRAY_SIZE(out_of_seq_q_cnts); i++, j++) {
5004 names[j] = out_of_seq_q_cnts[i].name;
5005 offsets[j] = out_of_seq_q_cnts[i].offset;
5006 }
5007 }
5008
5009 if (MLX5_CAP_GEN(dev->mdev, retransmission_q_counters)) {
5010 for (i = 0; i < ARRAY_SIZE(retrans_q_cnts); i++, j++) {
5011 names[j] = retrans_q_cnts[i].name;
5012 offsets[j] = retrans_q_cnts[i].offset;
5013 }
5014 }
5015
5016 if (MLX5_CAP_GEN(dev->mdev, enhanced_error_q_counters)) {
5017 for (i = 0; i < ARRAY_SIZE(extended_err_cnts); i++, j++) {
5018 names[j] = extended_err_cnts[i].name;
5019 offsets[j] = extended_err_cnts[i].offset;
5020 }
5021 }
5022
5023 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5024 for (i = 0; i < ARRAY_SIZE(cong_cnts); i++, j++) {
5025 names[j] = cong_cnts[i].name;
5026 offsets[j] = cong_cnts[i].offset;
5027 }
5028 }
5029
5030 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5031 for (i = 0; i < ARRAY_SIZE(ext_ppcnt_cnts); i++, j++) {
5032 names[j] = ext_ppcnt_cnts[i].name;
5033 offsets[j] = ext_ppcnt_cnts[i].offset;
5034 }
5035 }
5036 }
5037
5038 static int mlx5_ib_alloc_counters(struct mlx5_ib_dev *dev)
5039 {
5040 int err = 0;
5041 int i;
5042
5043 for (i = 0; i < dev->num_ports; i++) {
5044 err = __mlx5_ib_alloc_counters(dev, &dev->port[i].cnts);
5045 if (err)
5046 goto err_alloc;
5047
5048 mlx5_ib_fill_counters(dev, dev->port[i].cnts.names,
5049 dev->port[i].cnts.offsets);
5050
5051 err = mlx5_core_alloc_q_counter(dev->mdev,
5052 &dev->port[i].cnts.set_id);
5053 if (err) {
5054 mlx5_ib_warn(dev,
5055 "couldn't allocate queue counter for port %d, err %d\n",
5056 i + 1, err);
5057 goto err_alloc;
5058 }
5059 dev->port[i].cnts.set_id_valid = true;
5060 }
5061
5062 return 0;
5063
5064 err_alloc:
5065 mlx5_ib_dealloc_counters(dev);
5066 return err;
5067 }
5068
5069 static struct rdma_hw_stats *mlx5_ib_alloc_hw_stats(struct ib_device *ibdev,
5070 u8 port_num)
5071 {
5072 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5073 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5074
5075 /* We support only per port stats */
5076 if (port_num == 0)
5077 return NULL;
5078
5079 return rdma_alloc_hw_stats_struct(port->cnts.names,
5080 port->cnts.num_q_counters +
5081 port->cnts.num_cong_counters +
5082 port->cnts.num_ext_ppcnt_counters,
5083 RDMA_HW_STATS_DEFAULT_LIFESPAN);
5084 }
5085
5086 static int mlx5_ib_query_q_counters(struct mlx5_core_dev *mdev,
5087 struct mlx5_ib_port *port,
5088 struct rdma_hw_stats *stats)
5089 {
5090 int outlen = MLX5_ST_SZ_BYTES(query_q_counter_out);
5091 void *out;
5092 __be32 val;
5093 int ret, i;
5094
5095 out = kvzalloc(outlen, GFP_KERNEL);
5096 if (!out)
5097 return -ENOMEM;
5098
5099 ret = mlx5_core_query_q_counter(mdev,
5100 port->cnts.set_id, 0,
5101 out, outlen);
5102 if (ret)
5103 goto free;
5104
5105 for (i = 0; i < port->cnts.num_q_counters; i++) {
5106 val = *(__be32 *)(out + port->cnts.offsets[i]);
5107 stats->value[i] = (u64)be32_to_cpu(val);
5108 }
5109
5110 free:
5111 kvfree(out);
5112 return ret;
5113 }
5114
5115 static int mlx5_ib_query_ext_ppcnt_counters(struct mlx5_ib_dev *dev,
5116 struct mlx5_ib_port *port,
5117 struct rdma_hw_stats *stats)
5118 {
5119 int offset = port->cnts.num_q_counters + port->cnts.num_cong_counters;
5120 int sz = MLX5_ST_SZ_BYTES(ppcnt_reg);
5121 int ret, i;
5122 void *out;
5123
5124 out = kvzalloc(sz, GFP_KERNEL);
5125 if (!out)
5126 return -ENOMEM;
5127
5128 ret = mlx5_cmd_query_ext_ppcnt_counters(dev->mdev, out);
5129 if (ret)
5130 goto free;
5131
5132 for (i = 0; i < port->cnts.num_ext_ppcnt_counters; i++) {
5133 stats->value[i + offset] =
5134 be64_to_cpup((__be64 *)(out +
5135 port->cnts.offsets[i + offset]));
5136 }
5137
5138 free:
5139 kvfree(out);
5140 return ret;
5141 }
5142
5143 static int mlx5_ib_get_hw_stats(struct ib_device *ibdev,
5144 struct rdma_hw_stats *stats,
5145 u8 port_num, int index)
5146 {
5147 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5148 struct mlx5_ib_port *port = &dev->port[port_num - 1];
5149 struct mlx5_core_dev *mdev;
5150 int ret, num_counters;
5151 u8 mdev_port_num;
5152
5153 if (!stats)
5154 return -EINVAL;
5155
5156 num_counters = port->cnts.num_q_counters +
5157 port->cnts.num_cong_counters +
5158 port->cnts.num_ext_ppcnt_counters;
5159
5160 /* q_counters are per IB device, query the master mdev */
5161 ret = mlx5_ib_query_q_counters(dev->mdev, port, stats);
5162 if (ret)
5163 return ret;
5164
5165 if (MLX5_CAP_PCAM_FEATURE(dev->mdev, rx_icrc_encapsulated_counter)) {
5166 ret = mlx5_ib_query_ext_ppcnt_counters(dev, port, stats);
5167 if (ret)
5168 return ret;
5169 }
5170
5171 if (MLX5_CAP_GEN(dev->mdev, cc_query_allowed)) {
5172 mdev = mlx5_ib_get_native_port_mdev(dev, port_num,
5173 &mdev_port_num);
5174 if (!mdev) {
5175 /* If port is not affiliated yet, its in down state
5176 * which doesn't have any counters yet, so it would be
5177 * zero. So no need to read from the HCA.
5178 */
5179 goto done;
5180 }
5181 ret = mlx5_lag_query_cong_counters(dev->mdev,
5182 stats->value +
5183 port->cnts.num_q_counters,
5184 port->cnts.num_cong_counters,
5185 port->cnts.offsets +
5186 port->cnts.num_q_counters);
5187
5188 mlx5_ib_put_native_port_mdev(dev, port_num);
5189 if (ret)
5190 return ret;
5191 }
5192
5193 done:
5194 return num_counters;
5195 }
5196
5197 static struct net_device*
5198 mlx5_ib_alloc_rdma_netdev(struct ib_device *hca,
5199 u8 port_num,
5200 enum rdma_netdev_t type,
5201 const char *name,
5202 unsigned char name_assign_type,
5203 void (*setup)(struct net_device *))
5204 {
5205 struct net_device *netdev;
5206
5207 if (type != RDMA_NETDEV_IPOIB)
5208 return ERR_PTR(-EOPNOTSUPP);
5209
5210 netdev = mlx5_rdma_netdev_alloc(to_mdev(hca)->mdev, hca,
5211 name, setup);
5212 return netdev;
5213 }
5214
5215 static void delay_drop_debugfs_cleanup(struct mlx5_ib_dev *dev)
5216 {
5217 if (!dev->delay_drop.dbg)
5218 return;
5219 debugfs_remove_recursive(dev->delay_drop.dbg->dir_debugfs);
5220 kfree(dev->delay_drop.dbg);
5221 dev->delay_drop.dbg = NULL;
5222 }
5223
5224 static void cancel_delay_drop(struct mlx5_ib_dev *dev)
5225 {
5226 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5227 return;
5228
5229 cancel_work_sync(&dev->delay_drop.delay_drop_work);
5230 delay_drop_debugfs_cleanup(dev);
5231 }
5232
5233 static ssize_t delay_drop_timeout_read(struct file *filp, char __user *buf,
5234 size_t count, loff_t *pos)
5235 {
5236 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5237 char lbuf[20];
5238 int len;
5239
5240 len = snprintf(lbuf, sizeof(lbuf), "%u\n", delay_drop->timeout);
5241 return simple_read_from_buffer(buf, count, pos, lbuf, len);
5242 }
5243
5244 static ssize_t delay_drop_timeout_write(struct file *filp, const char __user *buf,
5245 size_t count, loff_t *pos)
5246 {
5247 struct mlx5_ib_delay_drop *delay_drop = filp->private_data;
5248 u32 timeout;
5249 u32 var;
5250
5251 if (kstrtouint_from_user(buf, count, 0, &var))
5252 return -EFAULT;
5253
5254 timeout = min_t(u32, roundup(var, 100), MLX5_MAX_DELAY_DROP_TIMEOUT_MS *
5255 1000);
5256 if (timeout != var)
5257 mlx5_ib_dbg(delay_drop->dev, "Round delay drop timeout to %u usec\n",
5258 timeout);
5259
5260 delay_drop->timeout = timeout;
5261
5262 return count;
5263 }
5264
5265 static const struct file_operations fops_delay_drop_timeout = {
5266 .owner = THIS_MODULE,
5267 .open = simple_open,
5268 .write = delay_drop_timeout_write,
5269 .read = delay_drop_timeout_read,
5270 };
5271
5272 static int delay_drop_debugfs_init(struct mlx5_ib_dev *dev)
5273 {
5274 struct mlx5_ib_dbg_delay_drop *dbg;
5275
5276 if (!mlx5_debugfs_root)
5277 return 0;
5278
5279 dbg = kzalloc(sizeof(*dbg), GFP_KERNEL);
5280 if (!dbg)
5281 return -ENOMEM;
5282
5283 dev->delay_drop.dbg = dbg;
5284
5285 dbg->dir_debugfs =
5286 debugfs_create_dir("delay_drop",
5287 dev->mdev->priv.dbg_root);
5288 if (!dbg->dir_debugfs)
5289 goto out_debugfs;
5290
5291 dbg->events_cnt_debugfs =
5292 debugfs_create_atomic_t("num_timeout_events", 0400,
5293 dbg->dir_debugfs,
5294 &dev->delay_drop.events_cnt);
5295 if (!dbg->events_cnt_debugfs)
5296 goto out_debugfs;
5297
5298 dbg->rqs_cnt_debugfs =
5299 debugfs_create_atomic_t("num_rqs", 0400,
5300 dbg->dir_debugfs,
5301 &dev->delay_drop.rqs_cnt);
5302 if (!dbg->rqs_cnt_debugfs)
5303 goto out_debugfs;
5304
5305 dbg->timeout_debugfs =
5306 debugfs_create_file("timeout", 0600,
5307 dbg->dir_debugfs,
5308 &dev->delay_drop,
5309 &fops_delay_drop_timeout);
5310 if (!dbg->timeout_debugfs)
5311 goto out_debugfs;
5312
5313 return 0;
5314
5315 out_debugfs:
5316 delay_drop_debugfs_cleanup(dev);
5317 return -ENOMEM;
5318 }
5319
5320 static void init_delay_drop(struct mlx5_ib_dev *dev)
5321 {
5322 if (!(dev->ib_dev.attrs.raw_packet_caps & IB_RAW_PACKET_CAP_DELAY_DROP))
5323 return;
5324
5325 mutex_init(&dev->delay_drop.lock);
5326 dev->delay_drop.dev = dev;
5327 dev->delay_drop.activate = false;
5328 dev->delay_drop.timeout = MLX5_MAX_DELAY_DROP_TIMEOUT_MS * 1000;
5329 INIT_WORK(&dev->delay_drop.delay_drop_work, delay_drop_handler);
5330 atomic_set(&dev->delay_drop.rqs_cnt, 0);
5331 atomic_set(&dev->delay_drop.events_cnt, 0);
5332
5333 if (delay_drop_debugfs_init(dev))
5334 mlx5_ib_warn(dev, "Failed to init delay drop debugfs\n");
5335 }
5336
5337 static const struct cpumask *
5338 mlx5_ib_get_vector_affinity(struct ib_device *ibdev, int comp_vector)
5339 {
5340 struct mlx5_ib_dev *dev = to_mdev(ibdev);
5341
5342 return mlx5_get_vector_affinity_hint(dev->mdev, comp_vector);
5343 }
5344
5345 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5346 static void mlx5_ib_unbind_slave_port(struct mlx5_ib_dev *ibdev,
5347 struct mlx5_ib_multiport_info *mpi)
5348 {
5349 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5350 struct mlx5_ib_port *port = &ibdev->port[port_num];
5351 int comps;
5352 int err;
5353 int i;
5354
5355 mlx5_ib_cleanup_cong_debugfs(ibdev, port_num);
5356
5357 spin_lock(&port->mp.mpi_lock);
5358 if (!mpi->ibdev) {
5359 spin_unlock(&port->mp.mpi_lock);
5360 return;
5361 }
5362 mpi->ibdev = NULL;
5363
5364 spin_unlock(&port->mp.mpi_lock);
5365 mlx5_remove_netdev_notifier(ibdev, port_num);
5366 spin_lock(&port->mp.mpi_lock);
5367
5368 comps = mpi->mdev_refcnt;
5369 if (comps) {
5370 mpi->unaffiliate = true;
5371 init_completion(&mpi->unref_comp);
5372 spin_unlock(&port->mp.mpi_lock);
5373
5374 for (i = 0; i < comps; i++)
5375 wait_for_completion(&mpi->unref_comp);
5376
5377 spin_lock(&port->mp.mpi_lock);
5378 mpi->unaffiliate = false;
5379 }
5380
5381 port->mp.mpi = NULL;
5382
5383 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
5384
5385 spin_unlock(&port->mp.mpi_lock);
5386
5387 err = mlx5_nic_vport_unaffiliate_multiport(mpi->mdev);
5388
5389 mlx5_ib_dbg(ibdev, "unaffiliated port %d\n", port_num + 1);
5390 /* Log an error, still needed to cleanup the pointers and add
5391 * it back to the list.
5392 */
5393 if (err)
5394 mlx5_ib_err(ibdev, "Failed to unaffiliate port %u\n",
5395 port_num + 1);
5396
5397 ibdev->roce[port_num].last_port_state = IB_PORT_DOWN;
5398 }
5399
5400 /* The mlx5_ib_multiport_mutex should be held when calling this function */
5401 static bool mlx5_ib_bind_slave_port(struct mlx5_ib_dev *ibdev,
5402 struct mlx5_ib_multiport_info *mpi)
5403 {
5404 u8 port_num = mlx5_core_native_port_num(mpi->mdev) - 1;
5405 int err;
5406
5407 spin_lock(&ibdev->port[port_num].mp.mpi_lock);
5408 if (ibdev->port[port_num].mp.mpi) {
5409 mlx5_ib_dbg(ibdev, "port %d already affiliated.\n",
5410 port_num + 1);
5411 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5412 return false;
5413 }
5414
5415 ibdev->port[port_num].mp.mpi = mpi;
5416 mpi->ibdev = ibdev;
5417 spin_unlock(&ibdev->port[port_num].mp.mpi_lock);
5418
5419 err = mlx5_nic_vport_affiliate_multiport(ibdev->mdev, mpi->mdev);
5420 if (err)
5421 goto unbind;
5422
5423 err = get_port_caps(ibdev, mlx5_core_native_port_num(mpi->mdev));
5424 if (err)
5425 goto unbind;
5426
5427 err = mlx5_add_netdev_notifier(ibdev, port_num);
5428 if (err) {
5429 mlx5_ib_err(ibdev, "failed adding netdev notifier for port %u\n",
5430 port_num + 1);
5431 goto unbind;
5432 }
5433
5434 err = mlx5_ib_init_cong_debugfs(ibdev, port_num);
5435 if (err)
5436 goto unbind;
5437
5438 return true;
5439
5440 unbind:
5441 mlx5_ib_unbind_slave_port(ibdev, mpi);
5442 return false;
5443 }
5444
5445 static int mlx5_ib_init_multiport_master(struct mlx5_ib_dev *dev)
5446 {
5447 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5448 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5449 port_num + 1);
5450 struct mlx5_ib_multiport_info *mpi;
5451 int err;
5452 int i;
5453
5454 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5455 return 0;
5456
5457 err = mlx5_query_nic_vport_system_image_guid(dev->mdev,
5458 &dev->sys_image_guid);
5459 if (err)
5460 return err;
5461
5462 err = mlx5_nic_vport_enable_roce(dev->mdev);
5463 if (err)
5464 return err;
5465
5466 mutex_lock(&mlx5_ib_multiport_mutex);
5467 for (i = 0; i < dev->num_ports; i++) {
5468 bool bound = false;
5469
5470 /* build a stub multiport info struct for the native port. */
5471 if (i == port_num) {
5472 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
5473 if (!mpi) {
5474 mutex_unlock(&mlx5_ib_multiport_mutex);
5475 mlx5_nic_vport_disable_roce(dev->mdev);
5476 return -ENOMEM;
5477 }
5478
5479 mpi->is_master = true;
5480 mpi->mdev = dev->mdev;
5481 mpi->sys_image_guid = dev->sys_image_guid;
5482 dev->port[i].mp.mpi = mpi;
5483 mpi->ibdev = dev;
5484 mpi = NULL;
5485 continue;
5486 }
5487
5488 list_for_each_entry(mpi, &mlx5_ib_unaffiliated_port_list,
5489 list) {
5490 if (dev->sys_image_guid == mpi->sys_image_guid &&
5491 (mlx5_core_native_port_num(mpi->mdev) - 1) == i) {
5492 bound = mlx5_ib_bind_slave_port(dev, mpi);
5493 }
5494
5495 if (bound) {
5496 dev_dbg(&mpi->mdev->pdev->dev, "removing port from unaffiliated list.\n");
5497 mlx5_ib_dbg(dev, "port %d bound\n", i + 1);
5498 list_del(&mpi->list);
5499 break;
5500 }
5501 }
5502 if (!bound) {
5503 get_port_caps(dev, i + 1);
5504 mlx5_ib_dbg(dev, "no free port found for port %d\n",
5505 i + 1);
5506 }
5507 }
5508
5509 list_add_tail(&dev->ib_dev_list, &mlx5_ib_dev_list);
5510 mutex_unlock(&mlx5_ib_multiport_mutex);
5511 return err;
5512 }
5513
5514 static void mlx5_ib_cleanup_multiport_master(struct mlx5_ib_dev *dev)
5515 {
5516 int port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5517 enum rdma_link_layer ll = mlx5_ib_port_link_layer(&dev->ib_dev,
5518 port_num + 1);
5519 int i;
5520
5521 if (!mlx5_core_is_mp_master(dev->mdev) || ll != IB_LINK_LAYER_ETHERNET)
5522 return;
5523
5524 mutex_lock(&mlx5_ib_multiport_mutex);
5525 for (i = 0; i < dev->num_ports; i++) {
5526 if (dev->port[i].mp.mpi) {
5527 /* Destroy the native port stub */
5528 if (i == port_num) {
5529 kfree(dev->port[i].mp.mpi);
5530 dev->port[i].mp.mpi = NULL;
5531 } else {
5532 mlx5_ib_dbg(dev, "unbinding port_num: %d\n", i + 1);
5533 mlx5_ib_unbind_slave_port(dev, dev->port[i].mp.mpi);
5534 }
5535 }
5536 }
5537
5538 mlx5_ib_dbg(dev, "removing from devlist\n");
5539 list_del(&dev->ib_dev_list);
5540 mutex_unlock(&mlx5_ib_multiport_mutex);
5541
5542 mlx5_nic_vport_disable_roce(dev->mdev);
5543 }
5544
5545 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5546 mlx5_ib_dm,
5547 UVERBS_OBJECT_DM,
5548 UVERBS_METHOD_DM_ALLOC,
5549 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_START_OFFSET,
5550 UVERBS_ATTR_TYPE(u64),
5551 UA_MANDATORY),
5552 UVERBS_ATTR_PTR_OUT(MLX5_IB_ATTR_ALLOC_DM_RESP_PAGE_INDEX,
5553 UVERBS_ATTR_TYPE(u16),
5554 UA_MANDATORY));
5555
5556 ADD_UVERBS_ATTRIBUTES_SIMPLE(
5557 mlx5_ib_flow_action,
5558 UVERBS_OBJECT_FLOW_ACTION,
5559 UVERBS_METHOD_FLOW_ACTION_ESP_CREATE,
5560 UVERBS_ATTR_FLAGS_IN(MLX5_IB_ATTR_CREATE_FLOW_ACTION_FLAGS,
5561 enum mlx5_ib_uapi_flow_action_flags));
5562
5563 static int populate_specs_root(struct mlx5_ib_dev *dev)
5564 {
5565 const struct uverbs_object_tree_def **trees = dev->driver_trees;
5566 size_t num_trees = 0;
5567
5568 if (mlx5_accel_ipsec_device_caps(dev->mdev) &
5569 MLX5_ACCEL_IPSEC_CAP_DEVICE)
5570 trees[num_trees++] = &mlx5_ib_flow_action;
5571
5572 if (MLX5_CAP_DEV_MEM(dev->mdev, memic))
5573 trees[num_trees++] = &mlx5_ib_dm;
5574
5575 if (MLX5_CAP_GEN_64(dev->mdev, general_obj_types) &
5576 MLX5_GENERAL_OBJ_TYPES_CAP_UCTX)
5577 trees[num_trees++] = mlx5_ib_get_devx_tree();
5578
5579 num_trees += mlx5_ib_get_flow_trees(trees + num_trees);
5580
5581 WARN_ON(num_trees >= ARRAY_SIZE(dev->driver_trees));
5582 trees[num_trees] = NULL;
5583 dev->ib_dev.driver_specs = trees;
5584
5585 return 0;
5586 }
5587
5588 static int mlx5_ib_read_counters(struct ib_counters *counters,
5589 struct ib_counters_read_attr *read_attr,
5590 struct uverbs_attr_bundle *attrs)
5591 {
5592 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5593 struct mlx5_read_counters_attr mread_attr = {};
5594 struct mlx5_ib_flow_counters_desc *desc;
5595 int ret, i;
5596
5597 mutex_lock(&mcounters->mcntrs_mutex);
5598 if (mcounters->cntrs_max_index > read_attr->ncounters) {
5599 ret = -EINVAL;
5600 goto err_bound;
5601 }
5602
5603 mread_attr.out = kcalloc(mcounters->counters_num, sizeof(u64),
5604 GFP_KERNEL);
5605 if (!mread_attr.out) {
5606 ret = -ENOMEM;
5607 goto err_bound;
5608 }
5609
5610 mread_attr.hw_cntrs_hndl = mcounters->hw_cntrs_hndl;
5611 mread_attr.flags = read_attr->flags;
5612 ret = mcounters->read_counters(counters->device, &mread_attr);
5613 if (ret)
5614 goto err_read;
5615
5616 /* do the pass over the counters data array to assign according to the
5617 * descriptions and indexing pairs
5618 */
5619 desc = mcounters->counters_data;
5620 for (i = 0; i < mcounters->ncounters; i++)
5621 read_attr->counters_buff[desc[i].index] += mread_attr.out[desc[i].description];
5622
5623 err_read:
5624 kfree(mread_attr.out);
5625 err_bound:
5626 mutex_unlock(&mcounters->mcntrs_mutex);
5627 return ret;
5628 }
5629
5630 static int mlx5_ib_destroy_counters(struct ib_counters *counters)
5631 {
5632 struct mlx5_ib_mcounters *mcounters = to_mcounters(counters);
5633
5634 counters_clear_description(counters);
5635 if (mcounters->hw_cntrs_hndl)
5636 mlx5_fc_destroy(to_mdev(counters->device)->mdev,
5637 mcounters->hw_cntrs_hndl);
5638
5639 kfree(mcounters);
5640
5641 return 0;
5642 }
5643
5644 static struct ib_counters *mlx5_ib_create_counters(struct ib_device *device,
5645 struct uverbs_attr_bundle *attrs)
5646 {
5647 struct mlx5_ib_mcounters *mcounters;
5648
5649 mcounters = kzalloc(sizeof(*mcounters), GFP_KERNEL);
5650 if (!mcounters)
5651 return ERR_PTR(-ENOMEM);
5652
5653 mutex_init(&mcounters->mcntrs_mutex);
5654
5655 return &mcounters->ibcntrs;
5656 }
5657
5658 void mlx5_ib_stage_init_cleanup(struct mlx5_ib_dev *dev)
5659 {
5660 mlx5_ib_cleanup_multiport_master(dev);
5661 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5662 cleanup_srcu_struct(&dev->mr_srcu);
5663 #endif
5664 kfree(dev->port);
5665 }
5666
5667 int mlx5_ib_stage_init_init(struct mlx5_ib_dev *dev)
5668 {
5669 struct mlx5_core_dev *mdev = dev->mdev;
5670 const char *name;
5671 int err;
5672 int i;
5673
5674 dev->port = kcalloc(dev->num_ports, sizeof(*dev->port),
5675 GFP_KERNEL);
5676 if (!dev->port)
5677 return -ENOMEM;
5678
5679 for (i = 0; i < dev->num_ports; i++) {
5680 spin_lock_init(&dev->port[i].mp.mpi_lock);
5681 rwlock_init(&dev->roce[i].netdev_lock);
5682 }
5683
5684 err = mlx5_ib_init_multiport_master(dev);
5685 if (err)
5686 goto err_free_port;
5687
5688 if (!mlx5_core_mp_enabled(mdev)) {
5689 for (i = 1; i <= dev->num_ports; i++) {
5690 err = get_port_caps(dev, i);
5691 if (err)
5692 break;
5693 }
5694 } else {
5695 err = get_port_caps(dev, mlx5_core_native_port_num(mdev));
5696 }
5697 if (err)
5698 goto err_mp;
5699
5700 if (mlx5_use_mad_ifc(dev))
5701 get_ext_port_caps(dev);
5702
5703 if (!mlx5_lag_is_active(mdev))
5704 name = "mlx5_%d";
5705 else
5706 name = "mlx5_bond_%d";
5707
5708 strlcpy(dev->ib_dev.name, name, IB_DEVICE_NAME_MAX);
5709 dev->ib_dev.owner = THIS_MODULE;
5710 dev->ib_dev.node_type = RDMA_NODE_IB_CA;
5711 dev->ib_dev.local_dma_lkey = 0 /* not supported for now */;
5712 dev->ib_dev.phys_port_cnt = dev->num_ports;
5713 dev->ib_dev.num_comp_vectors =
5714 dev->mdev->priv.eq_table.num_comp_vectors;
5715 dev->ib_dev.dev.parent = &mdev->pdev->dev;
5716
5717 mutex_init(&dev->cap_mask_mutex);
5718 INIT_LIST_HEAD(&dev->qp_list);
5719 spin_lock_init(&dev->reset_flow_resource_lock);
5720
5721 spin_lock_init(&dev->memic.memic_lock);
5722 dev->memic.dev = mdev;
5723
5724 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
5725 err = init_srcu_struct(&dev->mr_srcu);
5726 if (err)
5727 goto err_free_port;
5728 #endif
5729
5730 return 0;
5731 err_mp:
5732 mlx5_ib_cleanup_multiport_master(dev);
5733
5734 err_free_port:
5735 kfree(dev->port);
5736
5737 return -ENOMEM;
5738 }
5739
5740 static int mlx5_ib_stage_flow_db_init(struct mlx5_ib_dev *dev)
5741 {
5742 dev->flow_db = kzalloc(sizeof(*dev->flow_db), GFP_KERNEL);
5743
5744 if (!dev->flow_db)
5745 return -ENOMEM;
5746
5747 mutex_init(&dev->flow_db->lock);
5748
5749 return 0;
5750 }
5751
5752 int mlx5_ib_stage_rep_flow_db_init(struct mlx5_ib_dev *dev)
5753 {
5754 struct mlx5_ib_dev *nic_dev;
5755
5756 nic_dev = mlx5_ib_get_uplink_ibdev(dev->mdev->priv.eswitch);
5757
5758 if (!nic_dev)
5759 return -EINVAL;
5760
5761 dev->flow_db = nic_dev->flow_db;
5762
5763 return 0;
5764 }
5765
5766 static void mlx5_ib_stage_flow_db_cleanup(struct mlx5_ib_dev *dev)
5767 {
5768 kfree(dev->flow_db);
5769 }
5770
5771 int mlx5_ib_stage_caps_init(struct mlx5_ib_dev *dev)
5772 {
5773 struct mlx5_core_dev *mdev = dev->mdev;
5774 int err;
5775
5776 dev->ib_dev.uverbs_abi_ver = MLX5_IB_UVERBS_ABI_VERSION;
5777 dev->ib_dev.uverbs_cmd_mask =
5778 (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
5779 (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
5780 (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
5781 (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
5782 (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
5783 (1ull << IB_USER_VERBS_CMD_CREATE_AH) |
5784 (1ull << IB_USER_VERBS_CMD_DESTROY_AH) |
5785 (1ull << IB_USER_VERBS_CMD_REG_MR) |
5786 (1ull << IB_USER_VERBS_CMD_REREG_MR) |
5787 (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
5788 (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
5789 (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
5790 (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
5791 (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
5792 (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
5793 (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
5794 (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
5795 (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
5796 (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
5797 (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
5798 (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
5799 (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
5800 (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
5801 (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
5802 (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
5803 (1ull << IB_USER_VERBS_CMD_OPEN_QP);
5804 dev->ib_dev.uverbs_ex_cmd_mask =
5805 (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
5806 (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
5807 (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP) |
5808 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_QP) |
5809 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
5810
5811 dev->ib_dev.query_device = mlx5_ib_query_device;
5812 dev->ib_dev.get_link_layer = mlx5_ib_port_link_layer;
5813 dev->ib_dev.query_gid = mlx5_ib_query_gid;
5814 dev->ib_dev.add_gid = mlx5_ib_add_gid;
5815 dev->ib_dev.del_gid = mlx5_ib_del_gid;
5816 dev->ib_dev.query_pkey = mlx5_ib_query_pkey;
5817 dev->ib_dev.modify_device = mlx5_ib_modify_device;
5818 dev->ib_dev.modify_port = mlx5_ib_modify_port;
5819 dev->ib_dev.alloc_ucontext = mlx5_ib_alloc_ucontext;
5820 dev->ib_dev.dealloc_ucontext = mlx5_ib_dealloc_ucontext;
5821 dev->ib_dev.mmap = mlx5_ib_mmap;
5822 dev->ib_dev.alloc_pd = mlx5_ib_alloc_pd;
5823 dev->ib_dev.dealloc_pd = mlx5_ib_dealloc_pd;
5824 dev->ib_dev.create_ah = mlx5_ib_create_ah;
5825 dev->ib_dev.query_ah = mlx5_ib_query_ah;
5826 dev->ib_dev.destroy_ah = mlx5_ib_destroy_ah;
5827 dev->ib_dev.create_srq = mlx5_ib_create_srq;
5828 dev->ib_dev.modify_srq = mlx5_ib_modify_srq;
5829 dev->ib_dev.query_srq = mlx5_ib_query_srq;
5830 dev->ib_dev.destroy_srq = mlx5_ib_destroy_srq;
5831 dev->ib_dev.post_srq_recv = mlx5_ib_post_srq_recv;
5832 dev->ib_dev.create_qp = mlx5_ib_create_qp;
5833 dev->ib_dev.modify_qp = mlx5_ib_modify_qp;
5834 dev->ib_dev.query_qp = mlx5_ib_query_qp;
5835 dev->ib_dev.destroy_qp = mlx5_ib_destroy_qp;
5836 dev->ib_dev.drain_sq = mlx5_ib_drain_sq;
5837 dev->ib_dev.drain_rq = mlx5_ib_drain_rq;
5838 dev->ib_dev.post_send = mlx5_ib_post_send;
5839 dev->ib_dev.post_recv = mlx5_ib_post_recv;
5840 dev->ib_dev.create_cq = mlx5_ib_create_cq;
5841 dev->ib_dev.modify_cq = mlx5_ib_modify_cq;
5842 dev->ib_dev.resize_cq = mlx5_ib_resize_cq;
5843 dev->ib_dev.destroy_cq = mlx5_ib_destroy_cq;
5844 dev->ib_dev.poll_cq = mlx5_ib_poll_cq;
5845 dev->ib_dev.req_notify_cq = mlx5_ib_arm_cq;
5846 dev->ib_dev.get_dma_mr = mlx5_ib_get_dma_mr;
5847 dev->ib_dev.reg_user_mr = mlx5_ib_reg_user_mr;
5848 dev->ib_dev.rereg_user_mr = mlx5_ib_rereg_user_mr;
5849 dev->ib_dev.dereg_mr = mlx5_ib_dereg_mr;
5850 dev->ib_dev.attach_mcast = mlx5_ib_mcg_attach;
5851 dev->ib_dev.detach_mcast = mlx5_ib_mcg_detach;
5852 dev->ib_dev.process_mad = mlx5_ib_process_mad;
5853 dev->ib_dev.alloc_mr = mlx5_ib_alloc_mr;
5854 dev->ib_dev.map_mr_sg = mlx5_ib_map_mr_sg;
5855 dev->ib_dev.check_mr_status = mlx5_ib_check_mr_status;
5856 dev->ib_dev.get_dev_fw_str = get_dev_fw_str;
5857 dev->ib_dev.get_vector_affinity = mlx5_ib_get_vector_affinity;
5858 if (MLX5_CAP_GEN(mdev, ipoib_enhanced_offloads))
5859 dev->ib_dev.alloc_rdma_netdev = mlx5_ib_alloc_rdma_netdev;
5860
5861 if (mlx5_core_is_pf(mdev)) {
5862 dev->ib_dev.get_vf_config = mlx5_ib_get_vf_config;
5863 dev->ib_dev.set_vf_link_state = mlx5_ib_set_vf_link_state;
5864 dev->ib_dev.get_vf_stats = mlx5_ib_get_vf_stats;
5865 dev->ib_dev.set_vf_guid = mlx5_ib_set_vf_guid;
5866 }
5867
5868 dev->ib_dev.disassociate_ucontext = mlx5_ib_disassociate_ucontext;
5869
5870 dev->umr_fence = mlx5_get_umr_fence(MLX5_CAP_GEN(mdev, umr_fence));
5871
5872 if (MLX5_CAP_GEN(mdev, imaicl)) {
5873 dev->ib_dev.alloc_mw = mlx5_ib_alloc_mw;
5874 dev->ib_dev.dealloc_mw = mlx5_ib_dealloc_mw;
5875 dev->ib_dev.uverbs_cmd_mask |=
5876 (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
5877 (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
5878 }
5879
5880 if (MLX5_CAP_GEN(mdev, xrc)) {
5881 dev->ib_dev.alloc_xrcd = mlx5_ib_alloc_xrcd;
5882 dev->ib_dev.dealloc_xrcd = mlx5_ib_dealloc_xrcd;
5883 dev->ib_dev.uverbs_cmd_mask |=
5884 (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
5885 (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
5886 }
5887
5888 if (MLX5_CAP_DEV_MEM(mdev, memic)) {
5889 dev->ib_dev.alloc_dm = mlx5_ib_alloc_dm;
5890 dev->ib_dev.dealloc_dm = mlx5_ib_dealloc_dm;
5891 dev->ib_dev.reg_dm_mr = mlx5_ib_reg_dm_mr;
5892 }
5893
5894 dev->ib_dev.create_flow = mlx5_ib_create_flow;
5895 dev->ib_dev.destroy_flow = mlx5_ib_destroy_flow;
5896 dev->ib_dev.uverbs_ex_cmd_mask |=
5897 (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
5898 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
5899 dev->ib_dev.create_flow_action_esp = mlx5_ib_create_flow_action_esp;
5900 dev->ib_dev.destroy_flow_action = mlx5_ib_destroy_flow_action;
5901 dev->ib_dev.modify_flow_action_esp = mlx5_ib_modify_flow_action_esp;
5902 dev->ib_dev.driver_id = RDMA_DRIVER_MLX5;
5903 dev->ib_dev.create_counters = mlx5_ib_create_counters;
5904 dev->ib_dev.destroy_counters = mlx5_ib_destroy_counters;
5905 dev->ib_dev.read_counters = mlx5_ib_read_counters;
5906
5907 err = init_node_data(dev);
5908 if (err)
5909 return err;
5910
5911 if ((MLX5_CAP_GEN(dev->mdev, port_type) == MLX5_CAP_PORT_TYPE_ETH) &&
5912 (MLX5_CAP_GEN(dev->mdev, disable_local_lb_uc) ||
5913 MLX5_CAP_GEN(dev->mdev, disable_local_lb_mc)))
5914 mutex_init(&dev->lb.mutex);
5915
5916 return 0;
5917 }
5918
5919 static int mlx5_ib_stage_non_default_cb(struct mlx5_ib_dev *dev)
5920 {
5921 dev->ib_dev.get_port_immutable = mlx5_port_immutable;
5922 dev->ib_dev.query_port = mlx5_ib_query_port;
5923
5924 return 0;
5925 }
5926
5927 int mlx5_ib_stage_rep_non_default_cb(struct mlx5_ib_dev *dev)
5928 {
5929 dev->ib_dev.get_port_immutable = mlx5_port_rep_immutable;
5930 dev->ib_dev.query_port = mlx5_ib_rep_query_port;
5931
5932 return 0;
5933 }
5934
5935 static int mlx5_ib_stage_common_roce_init(struct mlx5_ib_dev *dev)
5936 {
5937 u8 port_num;
5938 int i;
5939
5940 for (i = 0; i < dev->num_ports; i++) {
5941 dev->roce[i].dev = dev;
5942 dev->roce[i].native_port_num = i + 1;
5943 dev->roce[i].last_port_state = IB_PORT_DOWN;
5944 }
5945
5946 dev->ib_dev.get_netdev = mlx5_ib_get_netdev;
5947 dev->ib_dev.create_wq = mlx5_ib_create_wq;
5948 dev->ib_dev.modify_wq = mlx5_ib_modify_wq;
5949 dev->ib_dev.destroy_wq = mlx5_ib_destroy_wq;
5950 dev->ib_dev.create_rwq_ind_table = mlx5_ib_create_rwq_ind_table;
5951 dev->ib_dev.destroy_rwq_ind_table = mlx5_ib_destroy_rwq_ind_table;
5952
5953 dev->ib_dev.uverbs_ex_cmd_mask |=
5954 (1ull << IB_USER_VERBS_EX_CMD_CREATE_WQ) |
5955 (1ull << IB_USER_VERBS_EX_CMD_MODIFY_WQ) |
5956 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_WQ) |
5957 (1ull << IB_USER_VERBS_EX_CMD_CREATE_RWQ_IND_TBL) |
5958 (1ull << IB_USER_VERBS_EX_CMD_DESTROY_RWQ_IND_TBL);
5959
5960 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5961
5962 return mlx5_add_netdev_notifier(dev, port_num);
5963 }
5964
5965 static void mlx5_ib_stage_common_roce_cleanup(struct mlx5_ib_dev *dev)
5966 {
5967 u8 port_num = mlx5_core_native_port_num(dev->mdev) - 1;
5968
5969 mlx5_remove_netdev_notifier(dev, port_num);
5970 }
5971
5972 int mlx5_ib_stage_rep_roce_init(struct mlx5_ib_dev *dev)
5973 {
5974 struct mlx5_core_dev *mdev = dev->mdev;
5975 enum rdma_link_layer ll;
5976 int port_type_cap;
5977 int err = 0;
5978
5979 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
5980 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
5981
5982 if (ll == IB_LINK_LAYER_ETHERNET)
5983 err = mlx5_ib_stage_common_roce_init(dev);
5984
5985 return err;
5986 }
5987
5988 void mlx5_ib_stage_rep_roce_cleanup(struct mlx5_ib_dev *dev)
5989 {
5990 mlx5_ib_stage_common_roce_cleanup(dev);
5991 }
5992
5993 static int mlx5_ib_stage_roce_init(struct mlx5_ib_dev *dev)
5994 {
5995 struct mlx5_core_dev *mdev = dev->mdev;
5996 enum rdma_link_layer ll;
5997 int port_type_cap;
5998 int err;
5999
6000 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6001 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6002
6003 if (ll == IB_LINK_LAYER_ETHERNET) {
6004 err = mlx5_ib_stage_common_roce_init(dev);
6005 if (err)
6006 return err;
6007
6008 err = mlx5_enable_eth(dev);
6009 if (err)
6010 goto cleanup;
6011 }
6012
6013 return 0;
6014 cleanup:
6015 mlx5_ib_stage_common_roce_cleanup(dev);
6016
6017 return err;
6018 }
6019
6020 static void mlx5_ib_stage_roce_cleanup(struct mlx5_ib_dev *dev)
6021 {
6022 struct mlx5_core_dev *mdev = dev->mdev;
6023 enum rdma_link_layer ll;
6024 int port_type_cap;
6025
6026 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6027 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6028
6029 if (ll == IB_LINK_LAYER_ETHERNET) {
6030 mlx5_disable_eth(dev);
6031 mlx5_ib_stage_common_roce_cleanup(dev);
6032 }
6033 }
6034
6035 int mlx5_ib_stage_dev_res_init(struct mlx5_ib_dev *dev)
6036 {
6037 return create_dev_resources(&dev->devr);
6038 }
6039
6040 void mlx5_ib_stage_dev_res_cleanup(struct mlx5_ib_dev *dev)
6041 {
6042 destroy_dev_resources(&dev->devr);
6043 }
6044
6045 static int mlx5_ib_stage_odp_init(struct mlx5_ib_dev *dev)
6046 {
6047 mlx5_ib_internal_fill_odp_caps(dev);
6048
6049 return mlx5_ib_odp_init_one(dev);
6050 }
6051
6052 int mlx5_ib_stage_counters_init(struct mlx5_ib_dev *dev)
6053 {
6054 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt)) {
6055 dev->ib_dev.get_hw_stats = mlx5_ib_get_hw_stats;
6056 dev->ib_dev.alloc_hw_stats = mlx5_ib_alloc_hw_stats;
6057
6058 return mlx5_ib_alloc_counters(dev);
6059 }
6060
6061 return 0;
6062 }
6063
6064 void mlx5_ib_stage_counters_cleanup(struct mlx5_ib_dev *dev)
6065 {
6066 if (MLX5_CAP_GEN(dev->mdev, max_qp_cnt))
6067 mlx5_ib_dealloc_counters(dev);
6068 }
6069
6070 static int mlx5_ib_stage_cong_debugfs_init(struct mlx5_ib_dev *dev)
6071 {
6072 return mlx5_ib_init_cong_debugfs(dev,
6073 mlx5_core_native_port_num(dev->mdev) - 1);
6074 }
6075
6076 static void mlx5_ib_stage_cong_debugfs_cleanup(struct mlx5_ib_dev *dev)
6077 {
6078 mlx5_ib_cleanup_cong_debugfs(dev,
6079 mlx5_core_native_port_num(dev->mdev) - 1);
6080 }
6081
6082 static int mlx5_ib_stage_uar_init(struct mlx5_ib_dev *dev)
6083 {
6084 dev->mdev->priv.uar = mlx5_get_uars_page(dev->mdev);
6085 return PTR_ERR_OR_ZERO(dev->mdev->priv.uar);
6086 }
6087
6088 static void mlx5_ib_stage_uar_cleanup(struct mlx5_ib_dev *dev)
6089 {
6090 mlx5_put_uars_page(dev->mdev, dev->mdev->priv.uar);
6091 }
6092
6093 int mlx5_ib_stage_bfrag_init(struct mlx5_ib_dev *dev)
6094 {
6095 int err;
6096
6097 err = mlx5_alloc_bfreg(dev->mdev, &dev->bfreg, false, false);
6098 if (err)
6099 return err;
6100
6101 err = mlx5_alloc_bfreg(dev->mdev, &dev->fp_bfreg, false, true);
6102 if (err)
6103 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6104
6105 return err;
6106 }
6107
6108 void mlx5_ib_stage_bfrag_cleanup(struct mlx5_ib_dev *dev)
6109 {
6110 mlx5_free_bfreg(dev->mdev, &dev->fp_bfreg);
6111 mlx5_free_bfreg(dev->mdev, &dev->bfreg);
6112 }
6113
6114 static int mlx5_ib_stage_populate_specs(struct mlx5_ib_dev *dev)
6115 {
6116 return populate_specs_root(dev);
6117 }
6118
6119 int mlx5_ib_stage_ib_reg_init(struct mlx5_ib_dev *dev)
6120 {
6121 return ib_register_device(&dev->ib_dev, NULL);
6122 }
6123
6124 void mlx5_ib_stage_pre_ib_reg_umr_cleanup(struct mlx5_ib_dev *dev)
6125 {
6126 destroy_umrc_res(dev);
6127 }
6128
6129 void mlx5_ib_stage_ib_reg_cleanup(struct mlx5_ib_dev *dev)
6130 {
6131 ib_unregister_device(&dev->ib_dev);
6132 }
6133
6134 int mlx5_ib_stage_post_ib_reg_umr_init(struct mlx5_ib_dev *dev)
6135 {
6136 return create_umr_res(dev);
6137 }
6138
6139 static int mlx5_ib_stage_delay_drop_init(struct mlx5_ib_dev *dev)
6140 {
6141 init_delay_drop(dev);
6142
6143 return 0;
6144 }
6145
6146 static void mlx5_ib_stage_delay_drop_cleanup(struct mlx5_ib_dev *dev)
6147 {
6148 cancel_delay_drop(dev);
6149 }
6150
6151 int mlx5_ib_stage_class_attr_init(struct mlx5_ib_dev *dev)
6152 {
6153 int err;
6154 int i;
6155
6156 for (i = 0; i < ARRAY_SIZE(mlx5_class_attributes); i++) {
6157 err = device_create_file(&dev->ib_dev.dev,
6158 mlx5_class_attributes[i]);
6159 if (err)
6160 return err;
6161 }
6162
6163 return 0;
6164 }
6165
6166 static int mlx5_ib_stage_rep_reg_init(struct mlx5_ib_dev *dev)
6167 {
6168 mlx5_ib_register_vport_reps(dev);
6169
6170 return 0;
6171 }
6172
6173 static void mlx5_ib_stage_rep_reg_cleanup(struct mlx5_ib_dev *dev)
6174 {
6175 mlx5_ib_unregister_vport_reps(dev);
6176 }
6177
6178 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
6179 const struct mlx5_ib_profile *profile,
6180 int stage)
6181 {
6182 /* Number of stages to cleanup */
6183 while (stage) {
6184 stage--;
6185 if (profile->stage[stage].cleanup)
6186 profile->stage[stage].cleanup(dev);
6187 }
6188
6189 ib_dealloc_device((struct ib_device *)dev);
6190 }
6191
6192 void *__mlx5_ib_add(struct mlx5_ib_dev *dev,
6193 const struct mlx5_ib_profile *profile)
6194 {
6195 int err;
6196 int i;
6197
6198 printk_once(KERN_INFO "%s", mlx5_version);
6199
6200 for (i = 0; i < MLX5_IB_STAGE_MAX; i++) {
6201 if (profile->stage[i].init) {
6202 err = profile->stage[i].init(dev);
6203 if (err)
6204 goto err_out;
6205 }
6206 }
6207
6208 dev->profile = profile;
6209 dev->ib_active = true;
6210
6211 return dev;
6212
6213 err_out:
6214 __mlx5_ib_remove(dev, profile, i);
6215
6216 return NULL;
6217 }
6218
6219 static const struct mlx5_ib_profile pf_profile = {
6220 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6221 mlx5_ib_stage_init_init,
6222 mlx5_ib_stage_init_cleanup),
6223 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6224 mlx5_ib_stage_flow_db_init,
6225 mlx5_ib_stage_flow_db_cleanup),
6226 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6227 mlx5_ib_stage_caps_init,
6228 NULL),
6229 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6230 mlx5_ib_stage_non_default_cb,
6231 NULL),
6232 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6233 mlx5_ib_stage_roce_init,
6234 mlx5_ib_stage_roce_cleanup),
6235 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6236 mlx5_ib_stage_dev_res_init,
6237 mlx5_ib_stage_dev_res_cleanup),
6238 STAGE_CREATE(MLX5_IB_STAGE_ODP,
6239 mlx5_ib_stage_odp_init,
6240 NULL),
6241 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6242 mlx5_ib_stage_counters_init,
6243 mlx5_ib_stage_counters_cleanup),
6244 STAGE_CREATE(MLX5_IB_STAGE_CONG_DEBUGFS,
6245 mlx5_ib_stage_cong_debugfs_init,
6246 mlx5_ib_stage_cong_debugfs_cleanup),
6247 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6248 mlx5_ib_stage_uar_init,
6249 mlx5_ib_stage_uar_cleanup),
6250 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6251 mlx5_ib_stage_bfrag_init,
6252 mlx5_ib_stage_bfrag_cleanup),
6253 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6254 NULL,
6255 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6256 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6257 mlx5_ib_stage_populate_specs,
6258 NULL),
6259 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6260 mlx5_ib_stage_ib_reg_init,
6261 mlx5_ib_stage_ib_reg_cleanup),
6262 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6263 mlx5_ib_stage_post_ib_reg_umr_init,
6264 NULL),
6265 STAGE_CREATE(MLX5_IB_STAGE_DELAY_DROP,
6266 mlx5_ib_stage_delay_drop_init,
6267 mlx5_ib_stage_delay_drop_cleanup),
6268 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6269 mlx5_ib_stage_class_attr_init,
6270 NULL),
6271 };
6272
6273 static const struct mlx5_ib_profile nic_rep_profile = {
6274 STAGE_CREATE(MLX5_IB_STAGE_INIT,
6275 mlx5_ib_stage_init_init,
6276 mlx5_ib_stage_init_cleanup),
6277 STAGE_CREATE(MLX5_IB_STAGE_FLOW_DB,
6278 mlx5_ib_stage_flow_db_init,
6279 mlx5_ib_stage_flow_db_cleanup),
6280 STAGE_CREATE(MLX5_IB_STAGE_CAPS,
6281 mlx5_ib_stage_caps_init,
6282 NULL),
6283 STAGE_CREATE(MLX5_IB_STAGE_NON_DEFAULT_CB,
6284 mlx5_ib_stage_rep_non_default_cb,
6285 NULL),
6286 STAGE_CREATE(MLX5_IB_STAGE_ROCE,
6287 mlx5_ib_stage_rep_roce_init,
6288 mlx5_ib_stage_rep_roce_cleanup),
6289 STAGE_CREATE(MLX5_IB_STAGE_DEVICE_RESOURCES,
6290 mlx5_ib_stage_dev_res_init,
6291 mlx5_ib_stage_dev_res_cleanup),
6292 STAGE_CREATE(MLX5_IB_STAGE_COUNTERS,
6293 mlx5_ib_stage_counters_init,
6294 mlx5_ib_stage_counters_cleanup),
6295 STAGE_CREATE(MLX5_IB_STAGE_UAR,
6296 mlx5_ib_stage_uar_init,
6297 mlx5_ib_stage_uar_cleanup),
6298 STAGE_CREATE(MLX5_IB_STAGE_BFREG,
6299 mlx5_ib_stage_bfrag_init,
6300 mlx5_ib_stage_bfrag_cleanup),
6301 STAGE_CREATE(MLX5_IB_STAGE_PRE_IB_REG_UMR,
6302 NULL,
6303 mlx5_ib_stage_pre_ib_reg_umr_cleanup),
6304 STAGE_CREATE(MLX5_IB_STAGE_SPECS,
6305 mlx5_ib_stage_populate_specs,
6306 NULL),
6307 STAGE_CREATE(MLX5_IB_STAGE_IB_REG,
6308 mlx5_ib_stage_ib_reg_init,
6309 mlx5_ib_stage_ib_reg_cleanup),
6310 STAGE_CREATE(MLX5_IB_STAGE_POST_IB_REG_UMR,
6311 mlx5_ib_stage_post_ib_reg_umr_init,
6312 NULL),
6313 STAGE_CREATE(MLX5_IB_STAGE_CLASS_ATTR,
6314 mlx5_ib_stage_class_attr_init,
6315 NULL),
6316 STAGE_CREATE(MLX5_IB_STAGE_REP_REG,
6317 mlx5_ib_stage_rep_reg_init,
6318 mlx5_ib_stage_rep_reg_cleanup),
6319 };
6320
6321 static void *mlx5_ib_add_slave_port(struct mlx5_core_dev *mdev)
6322 {
6323 struct mlx5_ib_multiport_info *mpi;
6324 struct mlx5_ib_dev *dev;
6325 bool bound = false;
6326 int err;
6327
6328 mpi = kzalloc(sizeof(*mpi), GFP_KERNEL);
6329 if (!mpi)
6330 return NULL;
6331
6332 mpi->mdev = mdev;
6333
6334 err = mlx5_query_nic_vport_system_image_guid(mdev,
6335 &mpi->sys_image_guid);
6336 if (err) {
6337 kfree(mpi);
6338 return NULL;
6339 }
6340
6341 mutex_lock(&mlx5_ib_multiport_mutex);
6342 list_for_each_entry(dev, &mlx5_ib_dev_list, ib_dev_list) {
6343 if (dev->sys_image_guid == mpi->sys_image_guid)
6344 bound = mlx5_ib_bind_slave_port(dev, mpi);
6345
6346 if (bound) {
6347 rdma_roce_rescan_device(&dev->ib_dev);
6348 break;
6349 }
6350 }
6351
6352 if (!bound) {
6353 list_add_tail(&mpi->list, &mlx5_ib_unaffiliated_port_list);
6354 dev_dbg(&mdev->pdev->dev, "no suitable IB device found to bind to, added to unaffiliated list.\n");
6355 }
6356 mutex_unlock(&mlx5_ib_multiport_mutex);
6357
6358 return mpi;
6359 }
6360
6361 static void *mlx5_ib_add(struct mlx5_core_dev *mdev)
6362 {
6363 enum rdma_link_layer ll;
6364 struct mlx5_ib_dev *dev;
6365 int port_type_cap;
6366
6367 printk_once(KERN_INFO "%s", mlx5_version);
6368
6369 port_type_cap = MLX5_CAP_GEN(mdev, port_type);
6370 ll = mlx5_port_type_cap_to_rdma_ll(port_type_cap);
6371
6372 if (mlx5_core_is_mp_slave(mdev) && ll == IB_LINK_LAYER_ETHERNET)
6373 return mlx5_ib_add_slave_port(mdev);
6374
6375 dev = (struct mlx5_ib_dev *)ib_alloc_device(sizeof(*dev));
6376 if (!dev)
6377 return NULL;
6378
6379 dev->mdev = mdev;
6380 dev->num_ports = max(MLX5_CAP_GEN(mdev, num_ports),
6381 MLX5_CAP_GEN(mdev, num_vhca_ports));
6382
6383 if (MLX5_ESWITCH_MANAGER(mdev) &&
6384 mlx5_ib_eswitch_mode(mdev->priv.eswitch) == SRIOV_OFFLOADS) {
6385 dev->rep = mlx5_ib_vport_rep(mdev->priv.eswitch, 0);
6386
6387 return __mlx5_ib_add(dev, &nic_rep_profile);
6388 }
6389
6390 return __mlx5_ib_add(dev, &pf_profile);
6391 }
6392
6393 static void mlx5_ib_remove(struct mlx5_core_dev *mdev, void *context)
6394 {
6395 struct mlx5_ib_multiport_info *mpi;
6396 struct mlx5_ib_dev *dev;
6397
6398 if (mlx5_core_is_mp_slave(mdev)) {
6399 mpi = context;
6400 mutex_lock(&mlx5_ib_multiport_mutex);
6401 if (mpi->ibdev)
6402 mlx5_ib_unbind_slave_port(mpi->ibdev, mpi);
6403 list_del(&mpi->list);
6404 mutex_unlock(&mlx5_ib_multiport_mutex);
6405 return;
6406 }
6407
6408 dev = context;
6409 __mlx5_ib_remove(dev, dev->profile, MLX5_IB_STAGE_MAX);
6410 }
6411
6412 static struct mlx5_interface mlx5_ib_interface = {
6413 .add = mlx5_ib_add,
6414 .remove = mlx5_ib_remove,
6415 .event = mlx5_ib_event,
6416 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
6417 .pfault = mlx5_ib_pfault,
6418 #endif
6419 .protocol = MLX5_INTERFACE_PROTOCOL_IB,
6420 };
6421
6422 unsigned long mlx5_ib_get_xlt_emergency_page(void)
6423 {
6424 mutex_lock(&xlt_emergency_page_mutex);
6425 return xlt_emergency_page;
6426 }
6427
6428 void mlx5_ib_put_xlt_emergency_page(void)
6429 {
6430 mutex_unlock(&xlt_emergency_page_mutex);
6431 }
6432
6433 static int __init mlx5_ib_init(void)
6434 {
6435 int err;
6436
6437 xlt_emergency_page = __get_free_page(GFP_KERNEL);
6438 if (!xlt_emergency_page)
6439 return -ENOMEM;
6440
6441 mutex_init(&xlt_emergency_page_mutex);
6442
6443 mlx5_ib_event_wq = alloc_ordered_workqueue("mlx5_ib_event_wq", 0);
6444 if (!mlx5_ib_event_wq) {
6445 free_page(xlt_emergency_page);
6446 return -ENOMEM;
6447 }
6448
6449 mlx5_ib_odp_init();
6450
6451 err = mlx5_register_interface(&mlx5_ib_interface);
6452
6453 return err;
6454 }
6455
6456 static void __exit mlx5_ib_cleanup(void)
6457 {
6458 mlx5_unregister_interface(&mlx5_ib_interface);
6459 destroy_workqueue(mlx5_ib_event_wq);
6460 mutex_destroy(&xlt_emergency_page_mutex);
6461 free_page(xlt_emergency_page);
6462 }
6463
6464 module_init(mlx5_ib_init);
6465 module_exit(mlx5_ib_cleanup);