2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
49 #define mlx5_ib_dbg(dev, format, arg...) \
50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
51 __LINE__, current->pid, ##arg)
53 #define mlx5_ib_err(dev, format, arg...) \
54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
55 __LINE__, current->pid, ##arg)
57 #define mlx5_ib_warn(dev, format, arg...) \
58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
59 __LINE__, current->pid, ##arg)
61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
62 sizeof(((type *)0)->fld) <= (sz))
63 #define MLX5_IB_DEFAULT_UIDX 0xffffff
64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
69 MLX5_IB_MMAP_CMD_SHIFT
= 8,
70 MLX5_IB_MMAP_CMD_MASK
= 0xff,
73 enum mlx5_ib_mmap_cmd
{
74 MLX5_IB_MMAP_REGULAR_PAGE
= 0,
75 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
= 1,
76 MLX5_IB_MMAP_WC_PAGE
= 2,
77 MLX5_IB_MMAP_NC_PAGE
= 3,
78 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
79 MLX5_IB_MMAP_CORE_CLOCK
= 5,
83 MLX5_RES_SCAT_DATA32_CQE
= 0x1,
84 MLX5_RES_SCAT_DATA64_CQE
= 0x2,
85 MLX5_REQ_SCAT_DATA32_CQE
= 0x11,
86 MLX5_REQ_SCAT_DATA64_CQE
= 0x22,
89 enum mlx5_ib_latency_class
{
90 MLX5_IB_LATENCY_CLASS_LOW
,
91 MLX5_IB_LATENCY_CLASS_MEDIUM
,
92 MLX5_IB_LATENCY_CLASS_HIGH
,
95 enum mlx5_ib_mad_ifc_flags
{
96 MLX5_MAD_IFC_IGNORE_MKEY
= 1,
97 MLX5_MAD_IFC_IGNORE_BKEY
= 2,
98 MLX5_MAD_IFC_NET_VIEW
= 4,
102 MLX5_CROSS_CHANNEL_BFREG
= 0,
110 struct mlx5_ib_vma_private_data
{
111 struct list_head list
;
112 struct vm_area_struct
*vma
;
115 struct mlx5_ib_ucontext
{
116 struct ib_ucontext ibucontext
;
117 struct list_head db_page_list
;
119 /* protect doorbell record alloc/free
121 struct mutex db_page_mutex
;
122 struct mlx5_bfreg_info bfregi
;
124 /* Transport Domain number */
126 struct list_head vma_private_list
;
128 unsigned long upd_xlt_page
;
129 /* protect ODP/KSM */
130 struct mutex upd_xlt_page_mutex
;
134 static inline struct mlx5_ib_ucontext
*to_mucontext(struct ib_ucontext
*ibucontext
)
136 return container_of(ibucontext
, struct mlx5_ib_ucontext
, ibucontext
);
144 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
145 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
146 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
147 #error "Invalid number of bypass priorities"
149 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
151 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
152 #define MLX5_IB_NUM_SNIFFER_FTS 2
153 struct mlx5_ib_flow_prio
{
154 struct mlx5_flow_table
*flow_table
;
155 unsigned int refcount
;
158 struct mlx5_ib_flow_handler
{
159 struct list_head list
;
160 struct ib_flow ibflow
;
161 struct mlx5_ib_flow_prio
*prio
;
162 struct mlx5_flow_handle
*rule
;
165 struct mlx5_ib_flow_db
{
166 struct mlx5_ib_flow_prio prios
[MLX5_IB_NUM_FLOW_FT
];
167 struct mlx5_ib_flow_prio sniffer
[MLX5_IB_NUM_SNIFFER_FTS
];
168 struct mlx5_flow_table
*lag_demux_ft
;
169 /* Protect flow steering bypass flow tables
170 * when add/del flow rules.
171 * only single add/removal of flow steering rule could be done
177 /* Use macros here so that don't have to duplicate
178 * enum ib_send_flags and enum ib_qp_type for low-level driver
181 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
182 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
183 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
184 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
185 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
186 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
188 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
190 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
191 * creates the actual hardware QP.
193 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
194 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
196 #define MLX5_IB_UMR_OCTOWORD 16
197 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
199 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
200 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
201 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
202 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
203 #define MLX5_IB_UPD_XLT_PD BIT(4)
204 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
205 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
207 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
209 * These flags are intended for internal use by the mlx5_ib driver, and they
210 * rely on the range reserved for that use in the ib_qp_create_flags enum.
213 /* Create a UD QP whose source QP number is 1 */
214 static inline enum ib_qp_create_flags
mlx5_ib_create_qp_sqpn_qp1(void)
216 return IB_QP_CREATE_RESERVED_START
;
224 enum mlx5_ib_rq_flags
{
225 MLX5_IB_RQ_CVLAN_STRIPPING
= 1 << 0,
231 struct wr_list
*w_list
;
235 /* serialize post to the work queue
252 struct mlx5_core_qp core_qp
;
258 struct ib_umem
*umem
;
260 unsigned int page_shift
;
280 struct mlx5_ib_rwq_ind_table
{
281 struct ib_rwq_ind_table ib_rwq_ind_tbl
;
285 struct mlx5_ib_ubuffer
{
286 struct ib_umem
*umem
;
291 struct mlx5_ib_qp_base
{
292 struct mlx5_ib_qp
*container_mibqp
;
293 struct mlx5_core_qp mqp
;
294 struct mlx5_ib_ubuffer ubuffer
;
297 struct mlx5_ib_qp_trans
{
298 struct mlx5_ib_qp_base base
;
305 struct mlx5_ib_rss_qp
{
310 struct mlx5_ib_qp_base base
;
311 struct mlx5_ib_wq
*rq
;
312 struct mlx5_ib_ubuffer ubuffer
;
313 struct mlx5_db
*doorbell
;
320 struct mlx5_ib_qp_base base
;
321 struct mlx5_ib_wq
*sq
;
322 struct mlx5_ib_ubuffer ubuffer
;
323 struct mlx5_db
*doorbell
;
328 struct mlx5_ib_raw_packet_qp
{
329 struct mlx5_ib_sq sq
;
330 struct mlx5_ib_rq rq
;
335 unsigned long offset
;
336 struct mlx5_sq_bfreg
*bfreg
;
342 struct mlx5_ib_qp_trans trans_qp
;
343 struct mlx5_ib_raw_packet_qp raw_packet_qp
;
344 struct mlx5_ib_rss_qp rss_qp
;
349 struct mlx5_ib_wq rq
;
353 struct mlx5_ib_wq sq
;
355 /* serialize qp state modifications
367 /* only for user space QPs. For kernel
368 * we have it from the bf object
374 /* Store signature errors */
377 struct list_head qps_list
;
378 struct list_head cq_recv_list
;
379 struct list_head cq_send_list
;
383 struct mlx5_ib_cq_buf
{
385 struct ib_umem
*umem
;
390 enum mlx5_ib_qp_flags
{
391 MLX5_IB_QP_LSO
= IB_QP_CREATE_IPOIB_UD_LSO
,
392 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
,
393 MLX5_IB_QP_CROSS_CHANNEL
= IB_QP_CREATE_CROSS_CHANNEL
,
394 MLX5_IB_QP_MANAGED_SEND
= IB_QP_CREATE_MANAGED_SEND
,
395 MLX5_IB_QP_MANAGED_RECV
= IB_QP_CREATE_MANAGED_RECV
,
396 MLX5_IB_QP_SIGNATURE_HANDLING
= 1 << 5,
397 /* QP uses 1 as its source QP number */
398 MLX5_IB_QP_SQPN_QP1
= 1 << 6,
399 MLX5_IB_QP_CAP_SCATTER_FCS
= 1 << 7,
400 MLX5_IB_QP_RSS
= 1 << 8,
401 MLX5_IB_QP_CVLAN_STRIPPING
= 1 << 9,
405 struct ib_send_wr wr
;
409 unsigned int page_shift
;
410 unsigned int xlt_size
;
416 static inline struct mlx5_umr_wr
*umr_wr(struct ib_send_wr
*wr
)
418 return container_of(wr
, struct mlx5_umr_wr
, wr
);
421 struct mlx5_shared_mr_info
{
423 struct ib_umem
*umem
;
428 struct mlx5_core_cq mcq
;
429 struct mlx5_ib_cq_buf buf
;
432 /* serialize access to the CQ
438 struct mutex resize_mutex
;
439 struct mlx5_ib_cq_buf
*resize_buf
;
440 struct ib_umem
*resize_umem
;
442 struct list_head list_send_qp
;
443 struct list_head list_recv_qp
;
445 struct list_head wc_list
;
446 enum ib_cq_notify_flags notify_flags
;
447 struct work_struct notify_work
;
452 struct list_head list
;
457 struct mlx5_core_srq msrq
;
461 /* protect SRQ hanlding
467 struct ib_umem
*umem
;
468 /* serialize arming a SRQ
474 struct mlx5_ib_xrcd
{
475 struct ib_xrcd ibxrcd
;
479 enum mlx5_ib_mtt_access_flags
{
480 MLX5_IB_MTT_READ
= (1 << 0),
481 MLX5_IB_MTT_WRITE
= (1 << 1),
484 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
494 struct mlx5_core_mkey mmkey
;
495 struct ib_umem
*umem
;
496 struct mlx5_shared_mr_info
*smr_info
;
497 struct list_head list
;
501 struct mlx5_ib_dev
*dev
;
502 u32 out
[MLX5_ST_SZ_DW(create_mkey_out
)];
503 struct mlx5_core_sig_ctx
*sig
;
506 int access_flags
; /* Needed for rereg MR */
508 struct mlx5_ib_mr
*parent
;
509 atomic_t num_leaf_free
;
510 wait_queue_head_t q_leaf_free
;
515 struct mlx5_core_mkey mmkey
;
519 struct mlx5_ib_umr_context
{
521 enum ib_wc_status status
;
522 struct completion done
;
529 /* control access to UMR QP
531 struct semaphore sem
;
540 struct mlx5_cache_ent
{
541 struct list_head head
;
542 /* sync access to the cahce entry
559 struct dentry
*fsize
;
561 struct dentry
*fmiss
;
562 struct dentry
*flimit
;
564 struct mlx5_ib_dev
*dev
;
565 struct work_struct work
;
566 struct delayed_work dwork
;
568 struct completion
compl;
571 struct mlx5_mr_cache
{
572 struct workqueue_struct
*wq
;
573 struct mlx5_cache_ent ent
[MAX_MR_CACHE_ENTRIES
];
576 unsigned long last_add
;
579 struct mlx5_ib_gsi_qp
;
581 struct mlx5_ib_port_resources
{
582 struct mlx5_ib_resources
*devr
;
583 struct mlx5_ib_gsi_qp
*gsi
;
584 struct work_struct pkey_change_work
;
587 struct mlx5_ib_resources
{
594 struct mlx5_ib_port_resources ports
[2];
595 /* Protects changes to the port resources */
599 struct mlx5_ib_counters
{
603 u32 num_cong_counters
;
607 struct mlx5_ib_port
{
608 struct mlx5_ib_counters cnts
;
612 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
615 rwlock_t netdev_lock
;
616 struct net_device
*netdev
;
617 struct notifier_block nb
;
622 struct ib_device ib_dev
;
623 struct mlx5_core_dev
*mdev
;
624 struct mlx5_roce roce
;
626 /* serialize update of capability mask
628 struct mutex cap_mask_mutex
;
630 struct umr_common umrc
;
631 /* sync used page count stats
633 struct mlx5_ib_resources devr
;
634 struct mlx5_mr_cache cache
;
635 struct timer_list delay_timer
;
636 /* Prevents soft lock on massive reg MRs */
637 struct mutex slow_path_mutex
;
639 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
640 struct ib_odp_caps odp_caps
;
643 * Sleepable RCU that prevents destruction of MRs while they are still
644 * being used by a page fault handler.
646 struct srcu_struct mr_srcu
;
649 struct mlx5_ib_flow_db flow_db
;
650 /* protect resources needed as part of reset flow */
651 spinlock_t reset_flow_resource_lock
;
652 struct list_head qp_list
;
653 /* Array with num_ports elements */
654 struct mlx5_ib_port
*port
;
655 struct mlx5_sq_bfreg bfreg
;
656 struct mlx5_sq_bfreg fp_bfreg
;
659 static inline struct mlx5_ib_cq
*to_mibcq(struct mlx5_core_cq
*mcq
)
661 return container_of(mcq
, struct mlx5_ib_cq
, mcq
);
664 static inline struct mlx5_ib_xrcd
*to_mxrcd(struct ib_xrcd
*ibxrcd
)
666 return container_of(ibxrcd
, struct mlx5_ib_xrcd
, ibxrcd
);
669 static inline struct mlx5_ib_dev
*to_mdev(struct ib_device
*ibdev
)
671 return container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
674 static inline struct mlx5_ib_cq
*to_mcq(struct ib_cq
*ibcq
)
676 return container_of(ibcq
, struct mlx5_ib_cq
, ibcq
);
679 static inline struct mlx5_ib_qp
*to_mibqp(struct mlx5_core_qp
*mqp
)
681 return container_of(mqp
, struct mlx5_ib_qp_base
, mqp
)->container_mibqp
;
684 static inline struct mlx5_ib_rwq
*to_mibrwq(struct mlx5_core_qp
*core_qp
)
686 return container_of(core_qp
, struct mlx5_ib_rwq
, core_qp
);
689 static inline struct mlx5_ib_mr
*to_mibmr(struct mlx5_core_mkey
*mmkey
)
691 return container_of(mmkey
, struct mlx5_ib_mr
, mmkey
);
694 static inline struct mlx5_ib_pd
*to_mpd(struct ib_pd
*ibpd
)
696 return container_of(ibpd
, struct mlx5_ib_pd
, ibpd
);
699 static inline struct mlx5_ib_srq
*to_msrq(struct ib_srq
*ibsrq
)
701 return container_of(ibsrq
, struct mlx5_ib_srq
, ibsrq
);
704 static inline struct mlx5_ib_qp
*to_mqp(struct ib_qp
*ibqp
)
706 return container_of(ibqp
, struct mlx5_ib_qp
, ibqp
);
709 static inline struct mlx5_ib_rwq
*to_mrwq(struct ib_wq
*ibwq
)
711 return container_of(ibwq
, struct mlx5_ib_rwq
, ibwq
);
714 static inline struct mlx5_ib_rwq_ind_table
*to_mrwq_ind_table(struct ib_rwq_ind_table
*ib_rwq_ind_tbl
)
716 return container_of(ib_rwq_ind_tbl
, struct mlx5_ib_rwq_ind_table
, ib_rwq_ind_tbl
);
719 static inline struct mlx5_ib_srq
*to_mibsrq(struct mlx5_core_srq
*msrq
)
721 return container_of(msrq
, struct mlx5_ib_srq
, msrq
);
724 static inline struct mlx5_ib_mr
*to_mmr(struct ib_mr
*ibmr
)
726 return container_of(ibmr
, struct mlx5_ib_mr
, ibmr
);
729 static inline struct mlx5_ib_mw
*to_mmw(struct ib_mw
*ibmw
)
731 return container_of(ibmw
, struct mlx5_ib_mw
, ibmw
);
734 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext
*context
, unsigned long virt
,
736 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext
*context
, struct mlx5_db
*db
);
737 void __mlx5_ib_cq_clean(struct mlx5_ib_cq
*cq
, u32 qpn
, struct mlx5_ib_srq
*srq
);
738 void mlx5_ib_cq_clean(struct mlx5_ib_cq
*cq
, u32 qpn
, struct mlx5_ib_srq
*srq
);
739 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq
*srq
, int wqe_index
);
740 int mlx5_MAD_IFC(struct mlx5_ib_dev
*dev
, int ignore_mkey
, int ignore_bkey
,
741 u8 port
, const struct ib_wc
*in_wc
, const struct ib_grh
*in_grh
,
742 const void *in_mad
, void *response_mad
);
743 struct ib_ah
*mlx5_ib_create_ah(struct ib_pd
*pd
, struct rdma_ah_attr
*ah_attr
,
744 struct ib_udata
*udata
);
745 int mlx5_ib_query_ah(struct ib_ah
*ibah
, struct rdma_ah_attr
*ah_attr
);
746 int mlx5_ib_destroy_ah(struct ib_ah
*ah
);
747 struct ib_srq
*mlx5_ib_create_srq(struct ib_pd
*pd
,
748 struct ib_srq_init_attr
*init_attr
,
749 struct ib_udata
*udata
);
750 int mlx5_ib_modify_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*attr
,
751 enum ib_srq_attr_mask attr_mask
, struct ib_udata
*udata
);
752 int mlx5_ib_query_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*srq_attr
);
753 int mlx5_ib_destroy_srq(struct ib_srq
*srq
);
754 int mlx5_ib_post_srq_recv(struct ib_srq
*ibsrq
, struct ib_recv_wr
*wr
,
755 struct ib_recv_wr
**bad_wr
);
756 struct ib_qp
*mlx5_ib_create_qp(struct ib_pd
*pd
,
757 struct ib_qp_init_attr
*init_attr
,
758 struct ib_udata
*udata
);
759 int mlx5_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
760 int attr_mask
, struct ib_udata
*udata
);
761 int mlx5_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
762 struct ib_qp_init_attr
*qp_init_attr
);
763 int mlx5_ib_destroy_qp(struct ib_qp
*qp
);
764 int mlx5_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
765 struct ib_send_wr
**bad_wr
);
766 int mlx5_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
767 struct ib_recv_wr
**bad_wr
);
768 void *mlx5_get_send_wqe(struct mlx5_ib_qp
*qp
, int n
);
769 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp
*qp
, int send
, int wqe_index
,
770 void *buffer
, u32 length
,
771 struct mlx5_ib_qp_base
*base
);
772 struct ib_cq
*mlx5_ib_create_cq(struct ib_device
*ibdev
,
773 const struct ib_cq_init_attr
*attr
,
774 struct ib_ucontext
*context
,
775 struct ib_udata
*udata
);
776 int mlx5_ib_destroy_cq(struct ib_cq
*cq
);
777 int mlx5_ib_poll_cq(struct ib_cq
*ibcq
, int num_entries
, struct ib_wc
*wc
);
778 int mlx5_ib_arm_cq(struct ib_cq
*ibcq
, enum ib_cq_notify_flags flags
);
779 int mlx5_ib_modify_cq(struct ib_cq
*cq
, u16 cq_count
, u16 cq_period
);
780 int mlx5_ib_resize_cq(struct ib_cq
*ibcq
, int entries
, struct ib_udata
*udata
);
781 struct ib_mr
*mlx5_ib_get_dma_mr(struct ib_pd
*pd
, int acc
);
782 struct ib_mr
*mlx5_ib_reg_user_mr(struct ib_pd
*pd
, u64 start
, u64 length
,
783 u64 virt_addr
, int access_flags
,
784 struct ib_udata
*udata
);
785 struct ib_mw
*mlx5_ib_alloc_mw(struct ib_pd
*pd
, enum ib_mw_type type
,
786 struct ib_udata
*udata
);
787 int mlx5_ib_dealloc_mw(struct ib_mw
*mw
);
788 int mlx5_ib_update_xlt(struct mlx5_ib_mr
*mr
, u64 idx
, int npages
,
789 int page_shift
, int flags
);
790 struct mlx5_ib_mr
*mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd
*pd
,
792 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr
*mr
);
793 int mlx5_ib_rereg_user_mr(struct ib_mr
*ib_mr
, int flags
, u64 start
,
794 u64 length
, u64 virt_addr
, int access_flags
,
795 struct ib_pd
*pd
, struct ib_udata
*udata
);
796 int mlx5_ib_dereg_mr(struct ib_mr
*ibmr
);
797 struct ib_mr
*mlx5_ib_alloc_mr(struct ib_pd
*pd
,
798 enum ib_mr_type mr_type
,
800 int mlx5_ib_map_mr_sg(struct ib_mr
*ibmr
, struct scatterlist
*sg
, int sg_nents
,
801 unsigned int *sg_offset
);
802 int mlx5_ib_process_mad(struct ib_device
*ibdev
, int mad_flags
, u8 port_num
,
803 const struct ib_wc
*in_wc
, const struct ib_grh
*in_grh
,
804 const struct ib_mad_hdr
*in
, size_t in_mad_size
,
805 struct ib_mad_hdr
*out
, size_t *out_mad_size
,
806 u16
*out_mad_pkey_index
);
807 struct ib_xrcd
*mlx5_ib_alloc_xrcd(struct ib_device
*ibdev
,
808 struct ib_ucontext
*context
,
809 struct ib_udata
*udata
);
810 int mlx5_ib_dealloc_xrcd(struct ib_xrcd
*xrcd
);
811 int mlx5_ib_get_buf_offset(u64 addr
, int page_shift
, u32
*offset
);
812 int mlx5_query_ext_port_caps(struct mlx5_ib_dev
*dev
, u8 port
);
813 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device
*ibdev
,
814 struct ib_smp
*out_mad
);
815 int mlx5_query_mad_ifc_system_image_guid(struct ib_device
*ibdev
,
816 __be64
*sys_image_guid
);
817 int mlx5_query_mad_ifc_max_pkeys(struct ib_device
*ibdev
,
819 int mlx5_query_mad_ifc_vendor_id(struct ib_device
*ibdev
,
821 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
);
822 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev
*dev
, __be64
*node_guid
);
823 int mlx5_query_mad_ifc_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
825 int mlx5_query_mad_ifc_gids(struct ib_device
*ibdev
, u8 port
, int index
,
827 int mlx5_query_mad_ifc_port(struct ib_device
*ibdev
, u8 port
,
828 struct ib_port_attr
*props
);
829 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
830 struct ib_port_attr
*props
);
831 int mlx5_ib_init_fmr(struct mlx5_ib_dev
*dev
);
832 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev
*dev
);
833 void mlx5_ib_cont_pages(struct ib_umem
*umem
, u64 addr
,
834 unsigned long max_page_shift
,
835 int *count
, int *shift
,
836 int *ncont
, int *order
);
837 void __mlx5_ib_populate_pas(struct mlx5_ib_dev
*dev
, struct ib_umem
*umem
,
838 int page_shift
, size_t offset
, size_t num_pages
,
839 __be64
*pas
, int access_flags
);
840 void mlx5_ib_populate_pas(struct mlx5_ib_dev
*dev
, struct ib_umem
*umem
,
841 int page_shift
, __be64
*pas
, int access_flags
);
842 void mlx5_ib_copy_pas(u64
*old
, u64
*new, int step
, int num
);
843 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev
*dev
, struct ib_cq
*ibcq
);
844 int mlx5_mr_cache_init(struct mlx5_ib_dev
*dev
);
845 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev
*dev
);
847 struct mlx5_ib_mr
*mlx5_mr_cache_alloc(struct mlx5_ib_dev
*dev
, int entry
);
848 void mlx5_mr_cache_free(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
);
849 int mlx5_ib_check_mr_status(struct ib_mr
*ibmr
, u32 check_mask
,
850 struct ib_mr_status
*mr_status
);
851 struct ib_wq
*mlx5_ib_create_wq(struct ib_pd
*pd
,
852 struct ib_wq_init_attr
*init_attr
,
853 struct ib_udata
*udata
);
854 int mlx5_ib_destroy_wq(struct ib_wq
*wq
);
855 int mlx5_ib_modify_wq(struct ib_wq
*wq
, struct ib_wq_attr
*wq_attr
,
856 u32 wq_attr_mask
, struct ib_udata
*udata
);
857 struct ib_rwq_ind_table
*mlx5_ib_create_rwq_ind_table(struct ib_device
*device
,
858 struct ib_rwq_ind_table_init_attr
*init_attr
,
859 struct ib_udata
*udata
);
860 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table
*wq_ind_table
);
862 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
863 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev
*dev
);
864 void mlx5_ib_pfault(struct mlx5_core_dev
*mdev
, void *context
,
865 struct mlx5_pagefault
*pfault
);
866 int mlx5_ib_odp_init_one(struct mlx5_ib_dev
*ibdev
);
867 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev
*ibdev
);
868 int __init
mlx5_ib_odp_init(void);
869 void mlx5_ib_odp_cleanup(void);
870 void mlx5_ib_invalidate_range(struct ib_umem
*umem
, unsigned long start
,
872 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent
*ent
);
873 void mlx5_odp_populate_klm(struct mlx5_klm
*pklm
, size_t offset
,
874 size_t nentries
, struct mlx5_ib_mr
*mr
, int flags
);
875 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
876 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev
*dev
)
881 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev
*ibdev
) { return 0; }
882 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev
*ibdev
) {}
883 static inline int mlx5_ib_odp_init(void) { return 0; }
884 static inline void mlx5_ib_odp_cleanup(void) {}
885 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent
*ent
) {}
886 static inline void mlx5_odp_populate_klm(struct mlx5_klm
*pklm
, size_t offset
,
887 size_t nentries
, struct mlx5_ib_mr
*mr
,
890 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
892 int mlx5_ib_get_vf_config(struct ib_device
*device
, int vf
,
893 u8 port
, struct ifla_vf_info
*info
);
894 int mlx5_ib_set_vf_link_state(struct ib_device
*device
, int vf
,
896 int mlx5_ib_get_vf_stats(struct ib_device
*device
, int vf
,
897 u8 port
, struct ifla_vf_stats
*stats
);
898 int mlx5_ib_set_vf_guid(struct ib_device
*device
, int vf
, u8 port
,
901 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
903 int mlx5_get_roce_gid_type(struct mlx5_ib_dev
*dev
, u8 port_num
,
904 int index
, enum ib_gid_type
*gid_type
);
906 /* GSI QP helper functions */
907 struct ib_qp
*mlx5_ib_gsi_create_qp(struct ib_pd
*pd
,
908 struct ib_qp_init_attr
*init_attr
);
909 int mlx5_ib_gsi_destroy_qp(struct ib_qp
*qp
);
910 int mlx5_ib_gsi_modify_qp(struct ib_qp
*qp
, struct ib_qp_attr
*attr
,
912 int mlx5_ib_gsi_query_qp(struct ib_qp
*qp
, struct ib_qp_attr
*qp_attr
,
914 struct ib_qp_init_attr
*qp_init_attr
);
915 int mlx5_ib_gsi_post_send(struct ib_qp
*qp
, struct ib_send_wr
*wr
,
916 struct ib_send_wr
**bad_wr
);
917 int mlx5_ib_gsi_post_recv(struct ib_qp
*qp
, struct ib_recv_wr
*wr
,
918 struct ib_recv_wr
**bad_wr
);
919 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp
*gsi
);
921 int mlx5_ib_generate_wc(struct ib_cq
*ibcq
, struct ib_wc
*wc
);
923 static inline void init_query_mad(struct ib_smp
*mad
)
925 mad
->base_version
= 1;
926 mad
->mgmt_class
= IB_MGMT_CLASS_SUBN_LID_ROUTED
;
927 mad
->class_version
= 1;
928 mad
->method
= IB_MGMT_METHOD_GET
;
931 static inline u8
convert_access(int acc
)
933 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? MLX5_PERM_ATOMIC
: 0) |
934 (acc
& IB_ACCESS_REMOTE_WRITE
? MLX5_PERM_REMOTE_WRITE
: 0) |
935 (acc
& IB_ACCESS_REMOTE_READ
? MLX5_PERM_REMOTE_READ
: 0) |
936 (acc
& IB_ACCESS_LOCAL_WRITE
? MLX5_PERM_LOCAL_WRITE
: 0) |
937 MLX5_PERM_LOCAL_READ
;
940 static inline int is_qp1(enum ib_qp_type qp_type
)
942 return qp_type
== MLX5_IB_QPT_HW_GSI
;
945 #define MLX5_MAX_UMR_SHIFT 16
946 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
948 static inline u32
check_cq_create_flags(u32 flags
)
951 * It returns non-zero value for unsupported CQ
952 * create flags, otherwise it returns zero.
954 return (flags
& ~(IB_CQ_FLAGS_IGNORE_OVERRUN
|
955 IB_CQ_FLAGS_TIMESTAMP_COMPLETION
));
958 static inline int verify_assign_uidx(u8 cqe_version
, u32 cmd_uidx
,
962 if ((cmd_uidx
== MLX5_IB_DEFAULT_UIDX
) ||
963 (cmd_uidx
& ~MLX5_USER_ASSIGNED_UIDX_MASK
))
965 *user_index
= cmd_uidx
;
967 *user_index
= MLX5_IB_DEFAULT_UIDX
;
973 static inline int get_qp_user_index(struct mlx5_ib_ucontext
*ucontext
,
974 struct mlx5_ib_create_qp
*ucmd
,
978 u8 cqe_version
= ucontext
->cqe_version
;
980 if (field_avail(struct mlx5_ib_create_qp
, uidx
, inlen
) &&
981 !cqe_version
&& (ucmd
->uidx
== MLX5_IB_DEFAULT_UIDX
))
984 if (!!(field_avail(struct mlx5_ib_create_qp
, uidx
, inlen
) !=
988 return verify_assign_uidx(cqe_version
, ucmd
->uidx
, user_index
);
991 static inline int get_srq_user_index(struct mlx5_ib_ucontext
*ucontext
,
992 struct mlx5_ib_create_srq
*ucmd
,
996 u8 cqe_version
= ucontext
->cqe_version
;
998 if (field_avail(struct mlx5_ib_create_srq
, uidx
, inlen
) &&
999 !cqe_version
&& (ucmd
->uidx
== MLX5_IB_DEFAULT_UIDX
))
1002 if (!!(field_avail(struct mlx5_ib_create_srq
, uidx
, inlen
) !=
1006 return verify_assign_uidx(cqe_version
, ucmd
->uidx
, user_index
);
1009 static inline int get_uars_per_sys_page(struct mlx5_ib_dev
*dev
, bool lib_support
)
1011 return lib_support
&& MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1012 MLX5_UARS_IN_PAGE
: 1;
1015 static inline int get_num_uars(struct mlx5_ib_dev
*dev
,
1016 struct mlx5_bfreg_info
*bfregi
)
1018 return get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
) * bfregi
->num_sys_pages
;
1021 #endif /* MLX5_IB_H */