2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
36 #include <linux/kernel.h>
37 #include <linux/sched.h>
38 #include <rdma/ib_verbs.h>
39 #include <rdma/ib_smi.h>
40 #include <linux/mlx5/driver.h>
41 #include <linux/mlx5/cq.h>
42 #include <linux/mlx5/qp.h>
43 #include <linux/mlx5/srq.h>
44 #include <linux/types.h>
45 #include <linux/mlx5/transobj.h>
46 #include <rdma/ib_user_verbs.h>
47 #include <rdma/mlx5-abi.h>
49 #define mlx5_ib_dbg(dev, format, arg...) \
50 pr_debug("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
51 __LINE__, current->pid, ##arg)
53 #define mlx5_ib_err(dev, format, arg...) \
54 pr_err("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
55 __LINE__, current->pid, ##arg)
57 #define mlx5_ib_warn(dev, format, arg...) \
58 pr_warn("%s:%s:%d:(pid %d): " format, (dev)->ib_dev.name, __func__, \
59 __LINE__, current->pid, ##arg)
61 #define field_avail(type, fld, sz) (offsetof(type, fld) + \
62 sizeof(((type *)0)->fld) <= (sz))
63 #define MLX5_IB_DEFAULT_UIDX 0xffffff
64 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
66 #define MLX5_MKEY_PAGE_SHIFT_MASK __mlx5_mask(mkc, log_page_size)
69 MLX5_IB_MMAP_CMD_SHIFT
= 8,
70 MLX5_IB_MMAP_CMD_MASK
= 0xff,
73 enum mlx5_ib_mmap_cmd
{
74 MLX5_IB_MMAP_REGULAR_PAGE
= 0,
75 MLX5_IB_MMAP_GET_CONTIGUOUS_PAGES
= 1,
76 MLX5_IB_MMAP_WC_PAGE
= 2,
77 MLX5_IB_MMAP_NC_PAGE
= 3,
78 /* 5 is chosen in order to be compatible with old versions of libmlx5 */
79 MLX5_IB_MMAP_CORE_CLOCK
= 5,
83 MLX5_RES_SCAT_DATA32_CQE
= 0x1,
84 MLX5_RES_SCAT_DATA64_CQE
= 0x2,
85 MLX5_REQ_SCAT_DATA32_CQE
= 0x11,
86 MLX5_REQ_SCAT_DATA64_CQE
= 0x22,
89 enum mlx5_ib_latency_class
{
90 MLX5_IB_LATENCY_CLASS_LOW
,
91 MLX5_IB_LATENCY_CLASS_MEDIUM
,
92 MLX5_IB_LATENCY_CLASS_HIGH
,
95 enum mlx5_ib_mad_ifc_flags
{
96 MLX5_MAD_IFC_IGNORE_MKEY
= 1,
97 MLX5_MAD_IFC_IGNORE_BKEY
= 2,
98 MLX5_MAD_IFC_NET_VIEW
= 4,
102 MLX5_CROSS_CHANNEL_BFREG
= 0,
111 MLX5_TM_MAX_RNDV_MSG_SIZE
= 64,
115 struct mlx5_ib_vma_private_data
{
116 struct list_head list
;
117 struct vm_area_struct
*vma
;
120 struct mlx5_ib_ucontext
{
121 struct ib_ucontext ibucontext
;
122 struct list_head db_page_list
;
124 /* protect doorbell record alloc/free
126 struct mutex db_page_mutex
;
127 struct mlx5_bfreg_info bfregi
;
129 /* Transport Domain number */
131 struct list_head vma_private_list
;
133 unsigned long upd_xlt_page
;
134 /* protect ODP/KSM */
135 struct mutex upd_xlt_page_mutex
;
139 static inline struct mlx5_ib_ucontext
*to_mucontext(struct ib_ucontext
*ibucontext
)
141 return container_of(ibucontext
, struct mlx5_ib_ucontext
, ibucontext
);
149 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
150 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
151 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
152 #error "Invalid number of bypass priorities"
154 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
156 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
157 #define MLX5_IB_NUM_SNIFFER_FTS 2
158 struct mlx5_ib_flow_prio
{
159 struct mlx5_flow_table
*flow_table
;
160 unsigned int refcount
;
163 struct mlx5_ib_flow_handler
{
164 struct list_head list
;
165 struct ib_flow ibflow
;
166 struct mlx5_ib_flow_prio
*prio
;
167 struct mlx5_flow_handle
*rule
;
170 struct mlx5_ib_flow_db
{
171 struct mlx5_ib_flow_prio prios
[MLX5_IB_NUM_FLOW_FT
];
172 struct mlx5_ib_flow_prio sniffer
[MLX5_IB_NUM_SNIFFER_FTS
];
173 struct mlx5_flow_table
*lag_demux_ft
;
174 /* Protect flow steering bypass flow tables
175 * when add/del flow rules.
176 * only single add/removal of flow steering rule could be done
182 /* Use macros here so that don't have to duplicate
183 * enum ib_send_flags and enum ib_qp_type for low-level driver
186 #define MLX5_IB_SEND_UMR_ENABLE_MR (IB_SEND_RESERVED_START << 0)
187 #define MLX5_IB_SEND_UMR_DISABLE_MR (IB_SEND_RESERVED_START << 1)
188 #define MLX5_IB_SEND_UMR_FAIL_IF_FREE (IB_SEND_RESERVED_START << 2)
189 #define MLX5_IB_SEND_UMR_UPDATE_XLT (IB_SEND_RESERVED_START << 3)
190 #define MLX5_IB_SEND_UMR_UPDATE_TRANSLATION (IB_SEND_RESERVED_START << 4)
191 #define MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS IB_SEND_RESERVED_END
193 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
195 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
196 * creates the actual hardware QP.
198 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
199 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
201 #define MLX5_IB_UMR_OCTOWORD 16
202 #define MLX5_IB_UMR_XLT_ALIGNMENT 64
204 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
205 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
206 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
207 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
208 #define MLX5_IB_UPD_XLT_PD BIT(4)
209 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
210 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
212 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
214 * These flags are intended for internal use by the mlx5_ib driver, and they
215 * rely on the range reserved for that use in the ib_qp_create_flags enum.
218 /* Create a UD QP whose source QP number is 1 */
219 static inline enum ib_qp_create_flags
mlx5_ib_create_qp_sqpn_qp1(void)
221 return IB_QP_CREATE_RESERVED_START
;
229 enum mlx5_ib_rq_flags
{
230 MLX5_IB_RQ_CVLAN_STRIPPING
= 1 << 0,
231 MLX5_IB_RQ_PCI_WRITE_END_PADDING
= 1 << 1,
237 struct wr_list
*w_list
;
241 /* serialize post to the work queue
256 enum mlx5_ib_wq_flags
{
257 MLX5_IB_WQ_FLAGS_DELAY_DROP
= 0x1,
258 MLX5_IB_WQ_FLAGS_STRIDING_RQ
= 0x2,
261 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
262 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
263 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
264 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
268 struct mlx5_core_qp core_qp
;
275 u32 two_byte_shift_en
;
276 u32 single_stride_log_num_of_bytes
;
277 struct ib_umem
*umem
;
279 unsigned int page_shift
;
286 u32 create_flags
; /* Use enum mlx5_ib_wq_flags */
300 struct mlx5_ib_rwq_ind_table
{
301 struct ib_rwq_ind_table ib_rwq_ind_tbl
;
305 struct mlx5_ib_ubuffer
{
306 struct ib_umem
*umem
;
311 struct mlx5_ib_qp_base
{
312 struct mlx5_ib_qp
*container_mibqp
;
313 struct mlx5_core_qp mqp
;
314 struct mlx5_ib_ubuffer ubuffer
;
317 struct mlx5_ib_qp_trans
{
318 struct mlx5_ib_qp_base base
;
325 struct mlx5_ib_rss_qp
{
330 struct mlx5_ib_qp_base base
;
331 struct mlx5_ib_wq
*rq
;
332 struct mlx5_ib_ubuffer ubuffer
;
333 struct mlx5_db
*doorbell
;
340 struct mlx5_ib_qp_base base
;
341 struct mlx5_ib_wq
*sq
;
342 struct mlx5_ib_ubuffer ubuffer
;
343 struct mlx5_db
*doorbell
;
348 struct mlx5_ib_raw_packet_qp
{
349 struct mlx5_ib_sq sq
;
350 struct mlx5_ib_rq rq
;
355 unsigned long offset
;
356 struct mlx5_sq_bfreg
*bfreg
;
362 struct mlx5_ib_qp_trans trans_qp
;
363 struct mlx5_ib_raw_packet_qp raw_packet_qp
;
364 struct mlx5_ib_rss_qp rss_qp
;
369 struct mlx5_ib_wq rq
;
373 struct mlx5_ib_wq sq
;
375 /* serialize qp state modifications
387 /* only for user space QPs. For kernel
388 * we have it from the bf object
394 /* Store signature errors */
397 struct list_head qps_list
;
398 struct list_head cq_recv_list
;
399 struct list_head cq_send_list
;
402 bool tunnel_offload_en
;
405 struct mlx5_ib_cq_buf
{
407 struct ib_umem
*umem
;
412 enum mlx5_ib_qp_flags
{
413 MLX5_IB_QP_LSO
= IB_QP_CREATE_IPOIB_UD_LSO
,
414 MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
,
415 MLX5_IB_QP_CROSS_CHANNEL
= IB_QP_CREATE_CROSS_CHANNEL
,
416 MLX5_IB_QP_MANAGED_SEND
= IB_QP_CREATE_MANAGED_SEND
,
417 MLX5_IB_QP_MANAGED_RECV
= IB_QP_CREATE_MANAGED_RECV
,
418 MLX5_IB_QP_SIGNATURE_HANDLING
= 1 << 5,
419 /* QP uses 1 as its source QP number */
420 MLX5_IB_QP_SQPN_QP1
= 1 << 6,
421 MLX5_IB_QP_CAP_SCATTER_FCS
= 1 << 7,
422 MLX5_IB_QP_RSS
= 1 << 8,
423 MLX5_IB_QP_CVLAN_STRIPPING
= 1 << 9,
424 MLX5_IB_QP_UNDERLAY
= 1 << 10,
425 MLX5_IB_QP_PCI_WRITE_END_PADDING
= 1 << 11,
426 MLX5_IB_QP_TUNNEL_OFFLOAD
= 1 << 12,
430 struct ib_send_wr wr
;
434 unsigned int page_shift
;
435 unsigned int xlt_size
;
441 static inline struct mlx5_umr_wr
*umr_wr(struct ib_send_wr
*wr
)
443 return container_of(wr
, struct mlx5_umr_wr
, wr
);
446 struct mlx5_shared_mr_info
{
448 struct ib_umem
*umem
;
451 enum mlx5_ib_cq_pr_flags
{
452 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD
= 1 << 0,
457 struct mlx5_core_cq mcq
;
458 struct mlx5_ib_cq_buf buf
;
461 /* serialize access to the CQ
467 struct mutex resize_mutex
;
468 struct mlx5_ib_cq_buf
*resize_buf
;
469 struct ib_umem
*resize_umem
;
471 struct list_head list_send_qp
;
472 struct list_head list_recv_qp
;
474 struct list_head wc_list
;
475 enum ib_cq_notify_flags notify_flags
;
476 struct work_struct notify_work
;
477 u16 private_flags
; /* Use mlx5_ib_cq_pr_flags */
482 struct list_head list
;
487 struct mlx5_core_srq msrq
;
491 /* protect SRQ hanlding
497 struct ib_umem
*umem
;
498 /* serialize arming a SRQ
504 struct mlx5_ib_xrcd
{
505 struct ib_xrcd ibxrcd
;
509 enum mlx5_ib_mtt_access_flags
{
510 MLX5_IB_MTT_READ
= (1 << 0),
511 MLX5_IB_MTT_WRITE
= (1 << 1),
514 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
524 struct mlx5_core_mkey mmkey
;
525 struct ib_umem
*umem
;
526 struct mlx5_shared_mr_info
*smr_info
;
527 struct list_head list
;
529 bool allocated_from_cache
;
531 struct mlx5_ib_dev
*dev
;
532 u32 out
[MLX5_ST_SZ_DW(create_mkey_out
)];
533 struct mlx5_core_sig_ctx
*sig
;
536 int access_flags
; /* Needed for rereg MR */
538 struct mlx5_ib_mr
*parent
;
539 atomic_t num_leaf_free
;
540 wait_queue_head_t q_leaf_free
;
545 struct mlx5_core_mkey mmkey
;
549 struct mlx5_ib_umr_context
{
551 enum ib_wc_status status
;
552 struct completion done
;
559 /* control access to UMR QP
561 struct semaphore sem
;
570 struct mlx5_cache_ent
{
571 struct list_head head
;
572 /* sync access to the cahce entry
589 struct dentry
*fsize
;
591 struct dentry
*fmiss
;
592 struct dentry
*flimit
;
594 struct mlx5_ib_dev
*dev
;
595 struct work_struct work
;
596 struct delayed_work dwork
;
598 struct completion
compl;
601 struct mlx5_mr_cache
{
602 struct workqueue_struct
*wq
;
603 struct mlx5_cache_ent ent
[MAX_MR_CACHE_ENTRIES
];
606 unsigned long last_add
;
609 struct mlx5_ib_gsi_qp
;
611 struct mlx5_ib_port_resources
{
612 struct mlx5_ib_resources
*devr
;
613 struct mlx5_ib_gsi_qp
*gsi
;
614 struct work_struct pkey_change_work
;
617 struct mlx5_ib_resources
{
624 struct mlx5_ib_port_resources ports
[2];
625 /* Protects changes to the port resources */
629 struct mlx5_ib_counters
{
633 u32 num_cong_counters
;
637 struct mlx5_ib_port
{
638 struct mlx5_ib_counters cnts
;
642 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
645 rwlock_t netdev_lock
;
646 struct net_device
*netdev
;
647 struct notifier_block nb
;
649 enum ib_port_state last_port_state
;
652 struct mlx5_ib_dbg_param
{
654 struct mlx5_ib_dev
*dev
;
655 struct dentry
*dentry
;
658 enum mlx5_ib_dbg_cc_types
{
659 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE
,
660 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI
,
661 MLX5_IB_DBG_CC_RP_TIME_RESET
,
662 MLX5_IB_DBG_CC_RP_BYTE_RESET
,
663 MLX5_IB_DBG_CC_RP_THRESHOLD
,
664 MLX5_IB_DBG_CC_RP_AI_RATE
,
665 MLX5_IB_DBG_CC_RP_HAI_RATE
,
666 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC
,
667 MLX5_IB_DBG_CC_RP_MIN_RATE
,
668 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP
,
669 MLX5_IB_DBG_CC_RP_DCE_TCP_G
,
670 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT
,
671 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD
,
672 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE
,
673 MLX5_IB_DBG_CC_RP_GD
,
674 MLX5_IB_DBG_CC_NP_CNP_DSCP
,
675 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE
,
676 MLX5_IB_DBG_CC_NP_CNP_PRIO
,
680 struct mlx5_ib_dbg_cc_params
{
682 struct mlx5_ib_dbg_param params
[MLX5_IB_DBG_CC_MAX
];
686 MLX5_MAX_DELAY_DROP_TIMEOUT_MS
= 100,
689 struct mlx5_ib_dbg_delay_drop
{
690 struct dentry
*dir_debugfs
;
691 struct dentry
*rqs_cnt_debugfs
;
692 struct dentry
*events_cnt_debugfs
;
693 struct dentry
*timeout_debugfs
;
696 struct mlx5_ib_delay_drop
{
697 struct mlx5_ib_dev
*dev
;
698 struct work_struct delay_drop_work
;
699 /* serialize setting of delay drop */
705 struct mlx5_ib_dbg_delay_drop
*dbg
;
709 struct ib_device ib_dev
;
710 struct mlx5_core_dev
*mdev
;
711 struct mlx5_roce roce
;
713 /* serialize update of capability mask
715 struct mutex cap_mask_mutex
;
717 struct umr_common umrc
;
718 /* sync used page count stats
720 struct mlx5_ib_resources devr
;
721 struct mlx5_mr_cache cache
;
722 struct timer_list delay_timer
;
723 /* Prevents soft lock on massive reg MRs */
724 struct mutex slow_path_mutex
;
726 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
727 struct ib_odp_caps odp_caps
;
730 * Sleepable RCU that prevents destruction of MRs while they are still
731 * being used by a page fault handler.
733 struct srcu_struct mr_srcu
;
736 struct mlx5_ib_flow_db flow_db
;
737 /* protect resources needed as part of reset flow */
738 spinlock_t reset_flow_resource_lock
;
739 struct list_head qp_list
;
740 /* Array with num_ports elements */
741 struct mlx5_ib_port
*port
;
742 struct mlx5_sq_bfreg bfreg
;
743 struct mlx5_sq_bfreg fp_bfreg
;
744 struct mlx5_ib_delay_drop delay_drop
;
745 struct mlx5_ib_dbg_cc_params
*dbg_cc_params
;
747 /* protect the user_td */
748 struct mutex lb_mutex
;
753 static inline struct mlx5_ib_cq
*to_mibcq(struct mlx5_core_cq
*mcq
)
755 return container_of(mcq
, struct mlx5_ib_cq
, mcq
);
758 static inline struct mlx5_ib_xrcd
*to_mxrcd(struct ib_xrcd
*ibxrcd
)
760 return container_of(ibxrcd
, struct mlx5_ib_xrcd
, ibxrcd
);
763 static inline struct mlx5_ib_dev
*to_mdev(struct ib_device
*ibdev
)
765 return container_of(ibdev
, struct mlx5_ib_dev
, ib_dev
);
768 static inline struct mlx5_ib_cq
*to_mcq(struct ib_cq
*ibcq
)
770 return container_of(ibcq
, struct mlx5_ib_cq
, ibcq
);
773 static inline struct mlx5_ib_qp
*to_mibqp(struct mlx5_core_qp
*mqp
)
775 return container_of(mqp
, struct mlx5_ib_qp_base
, mqp
)->container_mibqp
;
778 static inline struct mlx5_ib_rwq
*to_mibrwq(struct mlx5_core_qp
*core_qp
)
780 return container_of(core_qp
, struct mlx5_ib_rwq
, core_qp
);
783 static inline struct mlx5_ib_mr
*to_mibmr(struct mlx5_core_mkey
*mmkey
)
785 return container_of(mmkey
, struct mlx5_ib_mr
, mmkey
);
788 static inline struct mlx5_ib_pd
*to_mpd(struct ib_pd
*ibpd
)
790 return container_of(ibpd
, struct mlx5_ib_pd
, ibpd
);
793 static inline struct mlx5_ib_srq
*to_msrq(struct ib_srq
*ibsrq
)
795 return container_of(ibsrq
, struct mlx5_ib_srq
, ibsrq
);
798 static inline struct mlx5_ib_qp
*to_mqp(struct ib_qp
*ibqp
)
800 return container_of(ibqp
, struct mlx5_ib_qp
, ibqp
);
803 static inline struct mlx5_ib_rwq
*to_mrwq(struct ib_wq
*ibwq
)
805 return container_of(ibwq
, struct mlx5_ib_rwq
, ibwq
);
808 static inline struct mlx5_ib_rwq_ind_table
*to_mrwq_ind_table(struct ib_rwq_ind_table
*ib_rwq_ind_tbl
)
810 return container_of(ib_rwq_ind_tbl
, struct mlx5_ib_rwq_ind_table
, ib_rwq_ind_tbl
);
813 static inline struct mlx5_ib_srq
*to_mibsrq(struct mlx5_core_srq
*msrq
)
815 return container_of(msrq
, struct mlx5_ib_srq
, msrq
);
818 static inline struct mlx5_ib_mr
*to_mmr(struct ib_mr
*ibmr
)
820 return container_of(ibmr
, struct mlx5_ib_mr
, ibmr
);
823 static inline struct mlx5_ib_mw
*to_mmw(struct ib_mw
*ibmw
)
825 return container_of(ibmw
, struct mlx5_ib_mw
, ibmw
);
828 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext
*context
, unsigned long virt
,
830 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext
*context
, struct mlx5_db
*db
);
831 void __mlx5_ib_cq_clean(struct mlx5_ib_cq
*cq
, u32 qpn
, struct mlx5_ib_srq
*srq
);
832 void mlx5_ib_cq_clean(struct mlx5_ib_cq
*cq
, u32 qpn
, struct mlx5_ib_srq
*srq
);
833 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq
*srq
, int wqe_index
);
834 int mlx5_MAD_IFC(struct mlx5_ib_dev
*dev
, int ignore_mkey
, int ignore_bkey
,
835 u8 port
, const struct ib_wc
*in_wc
, const struct ib_grh
*in_grh
,
836 const void *in_mad
, void *response_mad
);
837 struct ib_ah
*mlx5_ib_create_ah(struct ib_pd
*pd
, struct rdma_ah_attr
*ah_attr
,
838 struct ib_udata
*udata
);
839 int mlx5_ib_query_ah(struct ib_ah
*ibah
, struct rdma_ah_attr
*ah_attr
);
840 int mlx5_ib_destroy_ah(struct ib_ah
*ah
);
841 struct ib_srq
*mlx5_ib_create_srq(struct ib_pd
*pd
,
842 struct ib_srq_init_attr
*init_attr
,
843 struct ib_udata
*udata
);
844 int mlx5_ib_modify_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*attr
,
845 enum ib_srq_attr_mask attr_mask
, struct ib_udata
*udata
);
846 int mlx5_ib_query_srq(struct ib_srq
*ibsrq
, struct ib_srq_attr
*srq_attr
);
847 int mlx5_ib_destroy_srq(struct ib_srq
*srq
);
848 int mlx5_ib_post_srq_recv(struct ib_srq
*ibsrq
, struct ib_recv_wr
*wr
,
849 struct ib_recv_wr
**bad_wr
);
850 struct ib_qp
*mlx5_ib_create_qp(struct ib_pd
*pd
,
851 struct ib_qp_init_attr
*init_attr
,
852 struct ib_udata
*udata
);
853 int mlx5_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
854 int attr_mask
, struct ib_udata
*udata
);
855 int mlx5_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
856 struct ib_qp_init_attr
*qp_init_attr
);
857 int mlx5_ib_destroy_qp(struct ib_qp
*qp
);
858 int mlx5_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
859 struct ib_send_wr
**bad_wr
);
860 int mlx5_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
861 struct ib_recv_wr
**bad_wr
);
862 void *mlx5_get_send_wqe(struct mlx5_ib_qp
*qp
, int n
);
863 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp
*qp
, int send
, int wqe_index
,
864 void *buffer
, u32 length
,
865 struct mlx5_ib_qp_base
*base
);
866 struct ib_cq
*mlx5_ib_create_cq(struct ib_device
*ibdev
,
867 const struct ib_cq_init_attr
*attr
,
868 struct ib_ucontext
*context
,
869 struct ib_udata
*udata
);
870 int mlx5_ib_destroy_cq(struct ib_cq
*cq
);
871 int mlx5_ib_poll_cq(struct ib_cq
*ibcq
, int num_entries
, struct ib_wc
*wc
);
872 int mlx5_ib_arm_cq(struct ib_cq
*ibcq
, enum ib_cq_notify_flags flags
);
873 int mlx5_ib_modify_cq(struct ib_cq
*cq
, u16 cq_count
, u16 cq_period
);
874 int mlx5_ib_resize_cq(struct ib_cq
*ibcq
, int entries
, struct ib_udata
*udata
);
875 struct ib_mr
*mlx5_ib_get_dma_mr(struct ib_pd
*pd
, int acc
);
876 struct ib_mr
*mlx5_ib_reg_user_mr(struct ib_pd
*pd
, u64 start
, u64 length
,
877 u64 virt_addr
, int access_flags
,
878 struct ib_udata
*udata
);
879 struct ib_mw
*mlx5_ib_alloc_mw(struct ib_pd
*pd
, enum ib_mw_type type
,
880 struct ib_udata
*udata
);
881 int mlx5_ib_dealloc_mw(struct ib_mw
*mw
);
882 int mlx5_ib_update_xlt(struct mlx5_ib_mr
*mr
, u64 idx
, int npages
,
883 int page_shift
, int flags
);
884 struct mlx5_ib_mr
*mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd
*pd
,
886 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr
*mr
);
887 int mlx5_ib_rereg_user_mr(struct ib_mr
*ib_mr
, int flags
, u64 start
,
888 u64 length
, u64 virt_addr
, int access_flags
,
889 struct ib_pd
*pd
, struct ib_udata
*udata
);
890 int mlx5_ib_dereg_mr(struct ib_mr
*ibmr
);
891 struct ib_mr
*mlx5_ib_alloc_mr(struct ib_pd
*pd
,
892 enum ib_mr_type mr_type
,
894 int mlx5_ib_map_mr_sg(struct ib_mr
*ibmr
, struct scatterlist
*sg
, int sg_nents
,
895 unsigned int *sg_offset
);
896 int mlx5_ib_process_mad(struct ib_device
*ibdev
, int mad_flags
, u8 port_num
,
897 const struct ib_wc
*in_wc
, const struct ib_grh
*in_grh
,
898 const struct ib_mad_hdr
*in
, size_t in_mad_size
,
899 struct ib_mad_hdr
*out
, size_t *out_mad_size
,
900 u16
*out_mad_pkey_index
);
901 struct ib_xrcd
*mlx5_ib_alloc_xrcd(struct ib_device
*ibdev
,
902 struct ib_ucontext
*context
,
903 struct ib_udata
*udata
);
904 int mlx5_ib_dealloc_xrcd(struct ib_xrcd
*xrcd
);
905 int mlx5_ib_get_buf_offset(u64 addr
, int page_shift
, u32
*offset
);
906 int mlx5_query_ext_port_caps(struct mlx5_ib_dev
*dev
, u8 port
);
907 int mlx5_query_mad_ifc_smp_attr_node_info(struct ib_device
*ibdev
,
908 struct ib_smp
*out_mad
);
909 int mlx5_query_mad_ifc_system_image_guid(struct ib_device
*ibdev
,
910 __be64
*sys_image_guid
);
911 int mlx5_query_mad_ifc_max_pkeys(struct ib_device
*ibdev
,
913 int mlx5_query_mad_ifc_vendor_id(struct ib_device
*ibdev
,
915 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev
*dev
, char *node_desc
);
916 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev
*dev
, __be64
*node_guid
);
917 int mlx5_query_mad_ifc_pkey(struct ib_device
*ibdev
, u8 port
, u16 index
,
919 int mlx5_query_mad_ifc_gids(struct ib_device
*ibdev
, u8 port
, int index
,
921 int mlx5_query_mad_ifc_port(struct ib_device
*ibdev
, u8 port
,
922 struct ib_port_attr
*props
);
923 int mlx5_ib_query_port(struct ib_device
*ibdev
, u8 port
,
924 struct ib_port_attr
*props
);
925 int mlx5_ib_init_fmr(struct mlx5_ib_dev
*dev
);
926 void mlx5_ib_cleanup_fmr(struct mlx5_ib_dev
*dev
);
927 void mlx5_ib_cont_pages(struct ib_umem
*umem
, u64 addr
,
928 unsigned long max_page_shift
,
929 int *count
, int *shift
,
930 int *ncont
, int *order
);
931 void __mlx5_ib_populate_pas(struct mlx5_ib_dev
*dev
, struct ib_umem
*umem
,
932 int page_shift
, size_t offset
, size_t num_pages
,
933 __be64
*pas
, int access_flags
);
934 void mlx5_ib_populate_pas(struct mlx5_ib_dev
*dev
, struct ib_umem
*umem
,
935 int page_shift
, __be64
*pas
, int access_flags
);
936 void mlx5_ib_copy_pas(u64
*old
, u64
*new, int step
, int num
);
937 int mlx5_ib_get_cqe_size(struct mlx5_ib_dev
*dev
, struct ib_cq
*ibcq
);
938 int mlx5_mr_cache_init(struct mlx5_ib_dev
*dev
);
939 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev
*dev
);
941 struct mlx5_ib_mr
*mlx5_mr_cache_alloc(struct mlx5_ib_dev
*dev
, int entry
);
942 void mlx5_mr_cache_free(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
);
943 int mlx5_ib_check_mr_status(struct ib_mr
*ibmr
, u32 check_mask
,
944 struct ib_mr_status
*mr_status
);
945 struct ib_wq
*mlx5_ib_create_wq(struct ib_pd
*pd
,
946 struct ib_wq_init_attr
*init_attr
,
947 struct ib_udata
*udata
);
948 int mlx5_ib_destroy_wq(struct ib_wq
*wq
);
949 int mlx5_ib_modify_wq(struct ib_wq
*wq
, struct ib_wq_attr
*wq_attr
,
950 u32 wq_attr_mask
, struct ib_udata
*udata
);
951 struct ib_rwq_ind_table
*mlx5_ib_create_rwq_ind_table(struct ib_device
*device
,
952 struct ib_rwq_ind_table_init_attr
*init_attr
,
953 struct ib_udata
*udata
);
954 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table
*wq_ind_table
);
956 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
957 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev
*dev
);
958 void mlx5_ib_pfault(struct mlx5_core_dev
*mdev
, void *context
,
959 struct mlx5_pagefault
*pfault
);
960 int mlx5_ib_odp_init_one(struct mlx5_ib_dev
*ibdev
);
961 void mlx5_ib_odp_remove_one(struct mlx5_ib_dev
*ibdev
);
962 int __init
mlx5_ib_odp_init(void);
963 void mlx5_ib_odp_cleanup(void);
964 void mlx5_ib_invalidate_range(struct ib_umem
*umem
, unsigned long start
,
966 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent
*ent
);
967 void mlx5_odp_populate_klm(struct mlx5_klm
*pklm
, size_t offset
,
968 size_t nentries
, struct mlx5_ib_mr
*mr
, int flags
);
969 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
970 static inline void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev
*dev
)
975 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev
*ibdev
) { return 0; }
976 static inline void mlx5_ib_odp_remove_one(struct mlx5_ib_dev
*ibdev
) {}
977 static inline int mlx5_ib_odp_init(void) { return 0; }
978 static inline void mlx5_ib_odp_cleanup(void) {}
979 static inline void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent
*ent
) {}
980 static inline void mlx5_odp_populate_klm(struct mlx5_klm
*pklm
, size_t offset
,
981 size_t nentries
, struct mlx5_ib_mr
*mr
,
984 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
986 int mlx5_ib_get_vf_config(struct ib_device
*device
, int vf
,
987 u8 port
, struct ifla_vf_info
*info
);
988 int mlx5_ib_set_vf_link_state(struct ib_device
*device
, int vf
,
990 int mlx5_ib_get_vf_stats(struct ib_device
*device
, int vf
,
991 u8 port
, struct ifla_vf_stats
*stats
);
992 int mlx5_ib_set_vf_guid(struct ib_device
*device
, int vf
, u8 port
,
995 __be16
mlx5_get_roce_udp_sport(struct mlx5_ib_dev
*dev
, u8 port_num
,
997 int mlx5_get_roce_gid_type(struct mlx5_ib_dev
*dev
, u8 port_num
,
998 int index
, enum ib_gid_type
*gid_type
);
1000 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev
*dev
);
1001 int mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev
*dev
);
1003 /* GSI QP helper functions */
1004 struct ib_qp
*mlx5_ib_gsi_create_qp(struct ib_pd
*pd
,
1005 struct ib_qp_init_attr
*init_attr
);
1006 int mlx5_ib_gsi_destroy_qp(struct ib_qp
*qp
);
1007 int mlx5_ib_gsi_modify_qp(struct ib_qp
*qp
, struct ib_qp_attr
*attr
,
1009 int mlx5_ib_gsi_query_qp(struct ib_qp
*qp
, struct ib_qp_attr
*qp_attr
,
1011 struct ib_qp_init_attr
*qp_init_attr
);
1012 int mlx5_ib_gsi_post_send(struct ib_qp
*qp
, struct ib_send_wr
*wr
,
1013 struct ib_send_wr
**bad_wr
);
1014 int mlx5_ib_gsi_post_recv(struct ib_qp
*qp
, struct ib_recv_wr
*wr
,
1015 struct ib_recv_wr
**bad_wr
);
1016 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp
*gsi
);
1018 int mlx5_ib_generate_wc(struct ib_cq
*ibcq
, struct ib_wc
*wc
);
1020 static inline void init_query_mad(struct ib_smp
*mad
)
1022 mad
->base_version
= 1;
1023 mad
->mgmt_class
= IB_MGMT_CLASS_SUBN_LID_ROUTED
;
1024 mad
->class_version
= 1;
1025 mad
->method
= IB_MGMT_METHOD_GET
;
1028 static inline u8
convert_access(int acc
)
1030 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? MLX5_PERM_ATOMIC
: 0) |
1031 (acc
& IB_ACCESS_REMOTE_WRITE
? MLX5_PERM_REMOTE_WRITE
: 0) |
1032 (acc
& IB_ACCESS_REMOTE_READ
? MLX5_PERM_REMOTE_READ
: 0) |
1033 (acc
& IB_ACCESS_LOCAL_WRITE
? MLX5_PERM_LOCAL_WRITE
: 0) |
1034 MLX5_PERM_LOCAL_READ
;
1037 static inline int is_qp1(enum ib_qp_type qp_type
)
1039 return qp_type
== MLX5_IB_QPT_HW_GSI
;
1042 #define MLX5_MAX_UMR_SHIFT 16
1043 #define MLX5_MAX_UMR_PAGES (1 << MLX5_MAX_UMR_SHIFT)
1045 static inline u32
check_cq_create_flags(u32 flags
)
1048 * It returns non-zero value for unsupported CQ
1049 * create flags, otherwise it returns zero.
1051 return (flags
& ~(IB_CQ_FLAGS_IGNORE_OVERRUN
|
1052 IB_CQ_FLAGS_TIMESTAMP_COMPLETION
));
1055 static inline int verify_assign_uidx(u8 cqe_version
, u32 cmd_uidx
,
1059 if ((cmd_uidx
== MLX5_IB_DEFAULT_UIDX
) ||
1060 (cmd_uidx
& ~MLX5_USER_ASSIGNED_UIDX_MASK
))
1062 *user_index
= cmd_uidx
;
1064 *user_index
= MLX5_IB_DEFAULT_UIDX
;
1070 static inline int get_qp_user_index(struct mlx5_ib_ucontext
*ucontext
,
1071 struct mlx5_ib_create_qp
*ucmd
,
1075 u8 cqe_version
= ucontext
->cqe_version
;
1077 if (field_avail(struct mlx5_ib_create_qp
, uidx
, inlen
) &&
1078 !cqe_version
&& (ucmd
->uidx
== MLX5_IB_DEFAULT_UIDX
))
1081 if (!!(field_avail(struct mlx5_ib_create_qp
, uidx
, inlen
) !=
1085 return verify_assign_uidx(cqe_version
, ucmd
->uidx
, user_index
);
1088 static inline int get_srq_user_index(struct mlx5_ib_ucontext
*ucontext
,
1089 struct mlx5_ib_create_srq
*ucmd
,
1093 u8 cqe_version
= ucontext
->cqe_version
;
1095 if (field_avail(struct mlx5_ib_create_srq
, uidx
, inlen
) &&
1096 !cqe_version
&& (ucmd
->uidx
== MLX5_IB_DEFAULT_UIDX
))
1099 if (!!(field_avail(struct mlx5_ib_create_srq
, uidx
, inlen
) !=
1103 return verify_assign_uidx(cqe_version
, ucmd
->uidx
, user_index
);
1106 static inline int get_uars_per_sys_page(struct mlx5_ib_dev
*dev
, bool lib_support
)
1108 return lib_support
&& MLX5_CAP_GEN(dev
->mdev
, uar_4k
) ?
1109 MLX5_UARS_IN_PAGE
: 1;
1112 static inline int get_num_uars(struct mlx5_ib_dev
*dev
,
1113 struct mlx5_bfreg_info
*bfregi
)
1115 return get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
) * bfregi
->num_sys_pages
;
1118 #endif /* MLX5_IB_H */