2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_umem_odp.h>
41 #include <rdma/ib_verbs.h>
45 MAX_PENDING_REG_MR
= 8,
48 #define MLX5_UMR_ALIGN 2048
50 static void clean_mr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
);
51 static void dereg_mr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
);
52 static int mr_cache_max_order(struct mlx5_ib_dev
*dev
);
53 static int unreg_umr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
);
55 static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev
*dev
)
57 return !MLX5_CAP_GEN(dev
->mdev
, umr_indirect_mkey_disabled
);
60 static int destroy_mkey(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
)
62 int err
= mlx5_core_destroy_mkey(dev
->mdev
, &mr
->mmkey
);
64 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
))
65 /* Wait until all page fault handlers using the mr complete. */
66 synchronize_srcu(&dev
->mr_srcu
);
71 static int order2idx(struct mlx5_ib_dev
*dev
, int order
)
73 struct mlx5_mr_cache
*cache
= &dev
->cache
;
75 if (order
< cache
->ent
[0].order
)
78 return order
- cache
->ent
[0].order
;
81 static bool use_umr_mtt_update(struct mlx5_ib_mr
*mr
, u64 start
, u64 length
)
83 return ((u64
)1 << mr
->order
) * MLX5_ADAPTER_PAGE_SIZE
>=
84 length
+ (start
& (MLX5_ADAPTER_PAGE_SIZE
- 1));
87 static void update_odp_mr(struct mlx5_ib_mr
*mr
)
91 * This barrier prevents the compiler from moving the
92 * setting of umem->odp_data->private to point to our
93 * MR, before reg_umr finished, to ensure that the MR
94 * initialization have finished before starting to
95 * handle invalidations.
98 to_ib_umem_odp(mr
->umem
)->private = mr
;
100 * Make sure we will see the new
101 * umem->odp_data->private value in the invalidation
102 * routines, before we can get page faults on the
103 * MR. Page faults can happen once we put the MR in
104 * the tree, below this line. Without the barrier,
105 * there can be a fault handling and an invalidation
106 * before umem->odp_data->private == mr is visible to
107 * the invalidation handler.
113 static void reg_mr_callback(int status
, struct mlx5_async_work
*context
)
115 struct mlx5_ib_mr
*mr
=
116 container_of(context
, struct mlx5_ib_mr
, cb_work
);
117 struct mlx5_ib_dev
*dev
= mr
->dev
;
118 struct mlx5_mr_cache
*cache
= &dev
->cache
;
119 int c
= order2idx(dev
, mr
->order
);
120 struct mlx5_cache_ent
*ent
= &cache
->ent
[c
];
123 struct xarray
*mkeys
= &dev
->mdev
->priv
.mkey_table
;
126 spin_lock_irqsave(&ent
->lock
, flags
);
128 spin_unlock_irqrestore(&ent
->lock
, flags
);
130 mlx5_ib_warn(dev
, "async reg mr failed. status %d\n", status
);
133 mod_timer(&dev
->delay_timer
, jiffies
+ HZ
);
137 mr
->mmkey
.type
= MLX5_MKEY_MR
;
138 spin_lock_irqsave(&dev
->mdev
->priv
.mkey_lock
, flags
);
139 key
= dev
->mdev
->priv
.mkey_key
++;
140 spin_unlock_irqrestore(&dev
->mdev
->priv
.mkey_lock
, flags
);
141 mr
->mmkey
.key
= mlx5_idx_to_mkey(MLX5_GET(create_mkey_out
, mr
->out
, mkey_index
)) | key
;
143 cache
->last_add
= jiffies
;
145 spin_lock_irqsave(&ent
->lock
, flags
);
146 list_add_tail(&mr
->list
, &ent
->head
);
149 spin_unlock_irqrestore(&ent
->lock
, flags
);
151 xa_lock_irqsave(mkeys
, flags
);
152 err
= xa_err(__xa_store(mkeys
, mlx5_base_mkey(mr
->mmkey
.key
),
153 &mr
->mmkey
, GFP_ATOMIC
));
154 xa_unlock_irqrestore(mkeys
, flags
);
156 pr_err("Error inserting to mkey tree. 0x%x\n", -err
);
158 if (!completion_done(&ent
->compl))
159 complete(&ent
->compl);
162 static int add_keys(struct mlx5_ib_dev
*dev
, int c
, int num
)
164 struct mlx5_mr_cache
*cache
= &dev
->cache
;
165 struct mlx5_cache_ent
*ent
= &cache
->ent
[c
];
166 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
167 struct mlx5_ib_mr
*mr
;
173 in
= kzalloc(inlen
, GFP_KERNEL
);
177 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
178 for (i
= 0; i
< num
; i
++) {
179 if (ent
->pending
>= MAX_PENDING_REG_MR
) {
184 mr
= kzalloc(sizeof(*mr
), GFP_KERNEL
);
189 mr
->order
= ent
->order
;
190 mr
->allocated_from_cache
= 1;
193 MLX5_SET(mkc
, mkc
, free
, 1);
194 MLX5_SET(mkc
, mkc
, umr_en
, 1);
195 MLX5_SET(mkc
, mkc
, access_mode_1_0
, ent
->access_mode
& 0x3);
196 MLX5_SET(mkc
, mkc
, access_mode_4_2
,
197 (ent
->access_mode
>> 2) & 0x7);
199 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
200 MLX5_SET(mkc
, mkc
, translations_octword_size
, ent
->xlt
);
201 MLX5_SET(mkc
, mkc
, log_page_size
, ent
->page
);
203 spin_lock_irq(&ent
->lock
);
205 spin_unlock_irq(&ent
->lock
);
206 err
= mlx5_core_create_mkey_cb(dev
->mdev
, &mr
->mmkey
,
207 &dev
->async_ctx
, in
, inlen
,
208 mr
->out
, sizeof(mr
->out
),
209 reg_mr_callback
, &mr
->cb_work
);
211 spin_lock_irq(&ent
->lock
);
213 spin_unlock_irq(&ent
->lock
);
214 mlx5_ib_warn(dev
, "create mkey failed %d\n", err
);
224 static void remove_keys(struct mlx5_ib_dev
*dev
, int c
, int num
)
226 struct mlx5_mr_cache
*cache
= &dev
->cache
;
227 struct mlx5_cache_ent
*ent
= &cache
->ent
[c
];
228 struct mlx5_ib_mr
*tmp_mr
;
229 struct mlx5_ib_mr
*mr
;
233 for (i
= 0; i
< num
; i
++) {
234 spin_lock_irq(&ent
->lock
);
235 if (list_empty(&ent
->head
)) {
236 spin_unlock_irq(&ent
->lock
);
239 mr
= list_first_entry(&ent
->head
, struct mlx5_ib_mr
, list
);
240 list_move(&mr
->list
, &del_list
);
243 spin_unlock_irq(&ent
->lock
);
244 mlx5_core_destroy_mkey(dev
->mdev
, &mr
->mmkey
);
247 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
))
248 synchronize_srcu(&dev
->mr_srcu
);
250 list_for_each_entry_safe(mr
, tmp_mr
, &del_list
, list
) {
256 static ssize_t
size_write(struct file
*filp
, const char __user
*buf
,
257 size_t count
, loff_t
*pos
)
259 struct mlx5_cache_ent
*ent
= filp
->private_data
;
260 struct mlx5_ib_dev
*dev
= ent
->dev
;
266 count
= min(count
, sizeof(lbuf
) - 1);
267 if (copy_from_user(lbuf
, buf
, count
))
270 c
= order2idx(dev
, ent
->order
);
272 if (sscanf(lbuf
, "%u", &var
) != 1)
275 if (var
< ent
->limit
)
278 if (var
> ent
->size
) {
280 err
= add_keys(dev
, c
, var
- ent
->size
);
281 if (err
&& err
!= -EAGAIN
)
284 usleep_range(3000, 5000);
286 } else if (var
< ent
->size
) {
287 remove_keys(dev
, c
, ent
->size
- var
);
293 static ssize_t
size_read(struct file
*filp
, char __user
*buf
, size_t count
,
296 struct mlx5_cache_ent
*ent
= filp
->private_data
;
300 err
= snprintf(lbuf
, sizeof(lbuf
), "%d\n", ent
->size
);
304 return simple_read_from_buffer(buf
, count
, pos
, lbuf
, err
);
307 static const struct file_operations size_fops
= {
308 .owner
= THIS_MODULE
,
314 static ssize_t
limit_write(struct file
*filp
, const char __user
*buf
,
315 size_t count
, loff_t
*pos
)
317 struct mlx5_cache_ent
*ent
= filp
->private_data
;
318 struct mlx5_ib_dev
*dev
= ent
->dev
;
324 count
= min(count
, sizeof(lbuf
) - 1);
325 if (copy_from_user(lbuf
, buf
, count
))
328 c
= order2idx(dev
, ent
->order
);
330 if (sscanf(lbuf
, "%u", &var
) != 1)
338 if (ent
->cur
< ent
->limit
) {
339 err
= add_keys(dev
, c
, 2 * ent
->limit
- ent
->cur
);
347 static ssize_t
limit_read(struct file
*filp
, char __user
*buf
, size_t count
,
350 struct mlx5_cache_ent
*ent
= filp
->private_data
;
354 err
= snprintf(lbuf
, sizeof(lbuf
), "%d\n", ent
->limit
);
358 return simple_read_from_buffer(buf
, count
, pos
, lbuf
, err
);
361 static const struct file_operations limit_fops
= {
362 .owner
= THIS_MODULE
,
364 .write
= limit_write
,
368 static int someone_adding(struct mlx5_mr_cache
*cache
)
372 for (i
= 0; i
< MAX_MR_CACHE_ENTRIES
; i
++) {
373 if (cache
->ent
[i
].cur
< cache
->ent
[i
].limit
)
380 static void __cache_work_func(struct mlx5_cache_ent
*ent
)
382 struct mlx5_ib_dev
*dev
= ent
->dev
;
383 struct mlx5_mr_cache
*cache
= &dev
->cache
;
384 int i
= order2idx(dev
, ent
->order
);
390 ent
= &dev
->cache
.ent
[i
];
391 if (ent
->cur
< 2 * ent
->limit
&& !dev
->fill_delay
) {
392 err
= add_keys(dev
, i
, 1);
393 if (ent
->cur
< 2 * ent
->limit
) {
394 if (err
== -EAGAIN
) {
395 mlx5_ib_dbg(dev
, "returned eagain, order %d\n",
397 queue_delayed_work(cache
->wq
, &ent
->dwork
,
398 msecs_to_jiffies(3));
400 mlx5_ib_warn(dev
, "command failed order %d, err %d\n",
402 queue_delayed_work(cache
->wq
, &ent
->dwork
,
403 msecs_to_jiffies(1000));
405 queue_work(cache
->wq
, &ent
->work
);
408 } else if (ent
->cur
> 2 * ent
->limit
) {
410 * The remove_keys() logic is performed as garbage collection
411 * task. Such task is intended to be run when no other active
412 * processes are running.
414 * The need_resched() will return TRUE if there are user tasks
415 * to be activated in near future.
417 * In such case, we don't execute remove_keys() and postpone
418 * the garbage collection work to try to run in next cycle,
419 * in order to free CPU resources to other tasks.
421 if (!need_resched() && !someone_adding(cache
) &&
422 time_after(jiffies
, cache
->last_add
+ 300 * HZ
)) {
423 remove_keys(dev
, i
, 1);
424 if (ent
->cur
> ent
->limit
)
425 queue_work(cache
->wq
, &ent
->work
);
427 queue_delayed_work(cache
->wq
, &ent
->dwork
, 300 * HZ
);
432 static void delayed_cache_work_func(struct work_struct
*work
)
434 struct mlx5_cache_ent
*ent
;
436 ent
= container_of(work
, struct mlx5_cache_ent
, dwork
.work
);
437 __cache_work_func(ent
);
440 static void cache_work_func(struct work_struct
*work
)
442 struct mlx5_cache_ent
*ent
;
444 ent
= container_of(work
, struct mlx5_cache_ent
, work
);
445 __cache_work_func(ent
);
448 struct mlx5_ib_mr
*mlx5_mr_cache_alloc(struct mlx5_ib_dev
*dev
, int entry
)
450 struct mlx5_mr_cache
*cache
= &dev
->cache
;
451 struct mlx5_cache_ent
*ent
;
452 struct mlx5_ib_mr
*mr
;
455 if (entry
< 0 || entry
>= MAX_MR_CACHE_ENTRIES
) {
456 mlx5_ib_err(dev
, "cache entry %d is out of range\n", entry
);
460 ent
= &cache
->ent
[entry
];
462 spin_lock_irq(&ent
->lock
);
463 if (list_empty(&ent
->head
)) {
464 spin_unlock_irq(&ent
->lock
);
466 err
= add_keys(dev
, entry
, 1);
467 if (err
&& err
!= -EAGAIN
)
470 wait_for_completion(&ent
->compl);
472 mr
= list_first_entry(&ent
->head
, struct mlx5_ib_mr
,
476 spin_unlock_irq(&ent
->lock
);
477 if (ent
->cur
< ent
->limit
)
478 queue_work(cache
->wq
, &ent
->work
);
484 static struct mlx5_ib_mr
*alloc_cached_mr(struct mlx5_ib_dev
*dev
, int order
)
486 struct mlx5_mr_cache
*cache
= &dev
->cache
;
487 struct mlx5_ib_mr
*mr
= NULL
;
488 struct mlx5_cache_ent
*ent
;
489 int last_umr_cache_entry
;
493 c
= order2idx(dev
, order
);
494 last_umr_cache_entry
= order2idx(dev
, mr_cache_max_order(dev
));
495 if (c
< 0 || c
> last_umr_cache_entry
) {
496 mlx5_ib_warn(dev
, "order %d, cache index %d\n", order
, c
);
500 for (i
= c
; i
<= last_umr_cache_entry
; i
++) {
501 ent
= &cache
->ent
[i
];
503 mlx5_ib_dbg(dev
, "order %d, cache index %d\n", ent
->order
, i
);
505 spin_lock_irq(&ent
->lock
);
506 if (!list_empty(&ent
->head
)) {
507 mr
= list_first_entry(&ent
->head
, struct mlx5_ib_mr
,
511 spin_unlock_irq(&ent
->lock
);
512 if (ent
->cur
< ent
->limit
)
513 queue_work(cache
->wq
, &ent
->work
);
516 spin_unlock_irq(&ent
->lock
);
518 queue_work(cache
->wq
, &ent
->work
);
522 cache
->ent
[c
].miss
++;
527 void mlx5_mr_cache_free(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
)
529 struct mlx5_mr_cache
*cache
= &dev
->cache
;
530 struct mlx5_cache_ent
*ent
;
534 if (!mr
->allocated_from_cache
)
537 c
= order2idx(dev
, mr
->order
);
538 WARN_ON(c
< 0 || c
>= MAX_MR_CACHE_ENTRIES
);
540 if (unreg_umr(dev
, mr
)) {
541 mr
->allocated_from_cache
= false;
542 destroy_mkey(dev
, mr
);
543 ent
= &cache
->ent
[c
];
544 if (ent
->cur
< ent
->limit
)
545 queue_work(cache
->wq
, &ent
->work
);
549 ent
= &cache
->ent
[c
];
550 spin_lock_irq(&ent
->lock
);
551 list_add_tail(&mr
->list
, &ent
->head
);
553 if (ent
->cur
> 2 * ent
->limit
)
555 spin_unlock_irq(&ent
->lock
);
558 queue_work(cache
->wq
, &ent
->work
);
561 static void clean_keys(struct mlx5_ib_dev
*dev
, int c
)
563 struct mlx5_mr_cache
*cache
= &dev
->cache
;
564 struct mlx5_cache_ent
*ent
= &cache
->ent
[c
];
565 struct mlx5_ib_mr
*tmp_mr
;
566 struct mlx5_ib_mr
*mr
;
569 cancel_delayed_work(&ent
->dwork
);
571 spin_lock_irq(&ent
->lock
);
572 if (list_empty(&ent
->head
)) {
573 spin_unlock_irq(&ent
->lock
);
576 mr
= list_first_entry(&ent
->head
, struct mlx5_ib_mr
, list
);
577 list_move(&mr
->list
, &del_list
);
580 spin_unlock_irq(&ent
->lock
);
581 mlx5_core_destroy_mkey(dev
->mdev
, &mr
->mmkey
);
584 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
585 synchronize_srcu(&dev
->mr_srcu
);
588 list_for_each_entry_safe(mr
, tmp_mr
, &del_list
, list
) {
594 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev
*dev
)
596 if (!mlx5_debugfs_root
|| dev
->is_rep
)
599 debugfs_remove_recursive(dev
->cache
.root
);
600 dev
->cache
.root
= NULL
;
603 static void mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev
*dev
)
605 struct mlx5_mr_cache
*cache
= &dev
->cache
;
606 struct mlx5_cache_ent
*ent
;
610 if (!mlx5_debugfs_root
|| dev
->is_rep
)
613 cache
->root
= debugfs_create_dir("mr_cache", dev
->mdev
->priv
.dbg_root
);
615 for (i
= 0; i
< MAX_MR_CACHE_ENTRIES
; i
++) {
616 ent
= &cache
->ent
[i
];
617 sprintf(ent
->name
, "%d", ent
->order
);
618 dir
= debugfs_create_dir(ent
->name
, cache
->root
);
619 debugfs_create_file("size", 0600, dir
, ent
, &size_fops
);
620 debugfs_create_file("limit", 0600, dir
, ent
, &limit_fops
);
621 debugfs_create_u32("cur", 0400, dir
, &ent
->cur
);
622 debugfs_create_u32("miss", 0600, dir
, &ent
->miss
);
626 static void delay_time_func(struct timer_list
*t
)
628 struct mlx5_ib_dev
*dev
= from_timer(dev
, t
, delay_timer
);
633 int mlx5_mr_cache_init(struct mlx5_ib_dev
*dev
)
635 struct mlx5_mr_cache
*cache
= &dev
->cache
;
636 struct mlx5_cache_ent
*ent
;
639 mutex_init(&dev
->slow_path_mutex
);
640 cache
->wq
= alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM
);
642 mlx5_ib_warn(dev
, "failed to create work queue\n");
646 mlx5_cmd_init_async_ctx(dev
->mdev
, &dev
->async_ctx
);
647 timer_setup(&dev
->delay_timer
, delay_time_func
, 0);
648 for (i
= 0; i
< MAX_MR_CACHE_ENTRIES
; i
++) {
649 ent
= &cache
->ent
[i
];
650 INIT_LIST_HEAD(&ent
->head
);
651 spin_lock_init(&ent
->lock
);
656 init_completion(&ent
->compl);
657 INIT_WORK(&ent
->work
, cache_work_func
);
658 INIT_DELAYED_WORK(&ent
->dwork
, delayed_cache_work_func
);
660 if (i
> MR_CACHE_LAST_STD_ENTRY
) {
661 mlx5_odp_init_mr_cache_entry(ent
);
665 if (ent
->order
> mr_cache_max_order(dev
))
668 ent
->page
= PAGE_SHIFT
;
669 ent
->xlt
= (1 << ent
->order
) * sizeof(struct mlx5_mtt
) /
670 MLX5_IB_UMR_OCTOWORD
;
671 ent
->access_mode
= MLX5_MKC_ACCESS_MODE_MTT
;
672 if ((dev
->mdev
->profile
->mask
& MLX5_PROF_MASK_MR_CACHE
) &&
674 mlx5_core_is_pf(dev
->mdev
))
675 ent
->limit
= dev
->mdev
->profile
->mr_cache
[i
].limit
;
678 queue_work(cache
->wq
, &ent
->work
);
681 mlx5_mr_cache_debugfs_init(dev
);
686 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev
*dev
)
693 dev
->cache
.stopped
= 1;
694 flush_workqueue(dev
->cache
.wq
);
696 mlx5_mr_cache_debugfs_cleanup(dev
);
697 mlx5_cmd_cleanup_async_ctx(&dev
->async_ctx
);
699 for (i
= 0; i
< MAX_MR_CACHE_ENTRIES
; i
++)
702 destroy_workqueue(dev
->cache
.wq
);
703 del_timer_sync(&dev
->delay_timer
);
708 struct ib_mr
*mlx5_ib_get_dma_mr(struct ib_pd
*pd
, int acc
)
710 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
711 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
712 struct mlx5_core_dev
*mdev
= dev
->mdev
;
713 struct mlx5_ib_mr
*mr
;
718 mr
= kzalloc(sizeof(*mr
), GFP_KERNEL
);
720 return ERR_PTR(-ENOMEM
);
722 in
= kzalloc(inlen
, GFP_KERNEL
);
728 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
730 MLX5_SET(mkc
, mkc
, access_mode_1_0
, MLX5_MKC_ACCESS_MODE_PA
);
731 MLX5_SET(mkc
, mkc
, a
, !!(acc
& IB_ACCESS_REMOTE_ATOMIC
));
732 MLX5_SET(mkc
, mkc
, rw
, !!(acc
& IB_ACCESS_REMOTE_WRITE
));
733 MLX5_SET(mkc
, mkc
, rr
, !!(acc
& IB_ACCESS_REMOTE_READ
));
734 MLX5_SET(mkc
, mkc
, lw
, !!(acc
& IB_ACCESS_LOCAL_WRITE
));
735 MLX5_SET(mkc
, mkc
, lr
, 1);
737 MLX5_SET(mkc
, mkc
, length64
, 1);
738 MLX5_SET(mkc
, mkc
, pd
, to_mpd(pd
)->pdn
);
739 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
740 MLX5_SET64(mkc
, mkc
, start_addr
, 0);
742 err
= mlx5_core_create_mkey(mdev
, &mr
->mmkey
, in
, inlen
);
747 mr
->mmkey
.type
= MLX5_MKEY_MR
;
748 mr
->ibmr
.lkey
= mr
->mmkey
.key
;
749 mr
->ibmr
.rkey
= mr
->mmkey
.key
;
763 static int get_octo_len(u64 addr
, u64 len
, int page_shift
)
765 u64 page_size
= 1ULL << page_shift
;
769 offset
= addr
& (page_size
- 1);
770 npages
= ALIGN(len
+ offset
, page_size
) >> page_shift
;
771 return (npages
+ 1) / 2;
774 static int mr_cache_max_order(struct mlx5_ib_dev
*dev
)
776 if (MLX5_CAP_GEN(dev
->mdev
, umr_extended_translation_offset
))
777 return MR_CACHE_LAST_STD_ENTRY
+ 2;
778 return MLX5_MAX_UMR_SHIFT
;
781 static int mr_umem_get(struct mlx5_ib_dev
*dev
, struct ib_udata
*udata
,
782 u64 start
, u64 length
, int access_flags
,
783 struct ib_umem
**umem
, int *npages
, int *page_shift
,
784 int *ncont
, int *order
)
791 u
= ib_umem_get(udata
, start
, length
, access_flags
, 0);
792 err
= PTR_ERR_OR_ZERO(u
);
794 mlx5_ib_dbg(dev
, "umem get failed (%d)\n", err
);
798 mlx5_ib_cont_pages(u
, start
, MLX5_MKEY_PAGE_SHIFT_MASK
, npages
,
799 page_shift
, ncont
, order
);
801 mlx5_ib_warn(dev
, "avoid zero region\n");
808 mlx5_ib_dbg(dev
, "npages %d, ncont %d, order %d, page_shift %d\n",
809 *npages
, *ncont
, *order
, *page_shift
);
814 static void mlx5_ib_umr_done(struct ib_cq
*cq
, struct ib_wc
*wc
)
816 struct mlx5_ib_umr_context
*context
=
817 container_of(wc
->wr_cqe
, struct mlx5_ib_umr_context
, cqe
);
819 context
->status
= wc
->status
;
820 complete(&context
->done
);
823 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context
*context
)
825 context
->cqe
.done
= mlx5_ib_umr_done
;
826 context
->status
= -1;
827 init_completion(&context
->done
);
830 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev
*dev
,
831 struct mlx5_umr_wr
*umrwr
)
833 struct umr_common
*umrc
= &dev
->umrc
;
834 const struct ib_send_wr
*bad
;
836 struct mlx5_ib_umr_context umr_context
;
838 mlx5_ib_init_umr_context(&umr_context
);
839 umrwr
->wr
.wr_cqe
= &umr_context
.cqe
;
842 err
= ib_post_send(umrc
->qp
, &umrwr
->wr
, &bad
);
844 mlx5_ib_warn(dev
, "UMR post send failed, err %d\n", err
);
846 wait_for_completion(&umr_context
.done
);
847 if (umr_context
.status
!= IB_WC_SUCCESS
) {
848 mlx5_ib_warn(dev
, "reg umr failed (%u)\n",
857 static struct mlx5_ib_mr
*alloc_mr_from_cache(
858 struct ib_pd
*pd
, struct ib_umem
*umem
,
859 u64 virt_addr
, u64 len
, int npages
,
860 int page_shift
, int order
, int access_flags
)
862 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
863 struct mlx5_ib_mr
*mr
;
867 for (i
= 0; i
< 1; i
++) {
868 mr
= alloc_cached_mr(dev
, order
);
872 err
= add_keys(dev
, order2idx(dev
, order
), 1);
873 if (err
&& err
!= -EAGAIN
) {
874 mlx5_ib_warn(dev
, "add_keys failed, err %d\n", err
);
880 return ERR_PTR(-EAGAIN
);
884 mr
->access_flags
= access_flags
;
885 mr
->desc_size
= sizeof(struct mlx5_mtt
);
886 mr
->mmkey
.iova
= virt_addr
;
887 mr
->mmkey
.size
= len
;
888 mr
->mmkey
.pd
= to_mpd(pd
)->pdn
;
893 static inline int populate_xlt(struct mlx5_ib_mr
*mr
, int idx
, int npages
,
894 void *xlt
, int page_shift
, size_t size
,
897 struct mlx5_ib_dev
*dev
= mr
->dev
;
898 struct ib_umem
*umem
= mr
->umem
;
900 if (flags
& MLX5_IB_UPD_XLT_INDIRECT
) {
901 if (!umr_can_use_indirect_mkey(dev
))
903 mlx5_odp_populate_klm(xlt
, idx
, npages
, mr
, flags
);
907 npages
= min_t(size_t, npages
, ib_umem_num_pages(umem
) - idx
);
909 if (!(flags
& MLX5_IB_UPD_XLT_ZAP
)) {
910 __mlx5_ib_populate_pas(dev
, umem
, page_shift
,
912 MLX5_IB_MTT_PRESENT
);
913 /* Clear padding after the pages
914 * brought from the umem.
916 memset(xlt
+ (npages
* sizeof(struct mlx5_mtt
)), 0,
917 size
- npages
* sizeof(struct mlx5_mtt
));
923 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
924 MLX5_UMR_MTT_ALIGNMENT)
925 #define MLX5_SPARE_UMR_CHUNK 0x10000
927 int mlx5_ib_update_xlt(struct mlx5_ib_mr
*mr
, u64 idx
, int npages
,
928 int page_shift
, int flags
)
930 struct mlx5_ib_dev
*dev
= mr
->dev
;
931 struct device
*ddev
= dev
->ib_dev
.dev
.parent
;
935 struct mlx5_umr_wr wr
;
938 int desc_size
= (flags
& MLX5_IB_UPD_XLT_INDIRECT
)
939 ? sizeof(struct mlx5_klm
)
940 : sizeof(struct mlx5_mtt
);
941 const int page_align
= MLX5_UMR_MTT_ALIGNMENT
/ desc_size
;
942 const int page_mask
= page_align
- 1;
943 size_t pages_mapped
= 0;
944 size_t pages_to_map
= 0;
945 size_t pages_iter
= 0;
947 bool use_emergency_page
= false;
949 if ((flags
& MLX5_IB_UPD_XLT_INDIRECT
) &&
950 !umr_can_use_indirect_mkey(dev
))
953 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
954 * so we need to align the offset and length accordingly
956 if (idx
& page_mask
) {
957 npages
+= idx
& page_mask
;
961 gfp
= flags
& MLX5_IB_UPD_XLT_ATOMIC
? GFP_ATOMIC
: GFP_KERNEL
;
962 gfp
|= __GFP_ZERO
| __GFP_NOWARN
;
964 pages_to_map
= ALIGN(npages
, page_align
);
965 size
= desc_size
* pages_to_map
;
966 size
= min_t(int, size
, MLX5_MAX_UMR_CHUNK
);
968 xlt
= (void *)__get_free_pages(gfp
, get_order(size
));
969 if (!xlt
&& size
> MLX5_SPARE_UMR_CHUNK
) {
970 mlx5_ib_dbg(dev
, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
971 size
, get_order(size
), MLX5_SPARE_UMR_CHUNK
);
973 size
= MLX5_SPARE_UMR_CHUNK
;
974 xlt
= (void *)__get_free_pages(gfp
, get_order(size
));
978 mlx5_ib_warn(dev
, "Using XLT emergency buffer\n");
979 xlt
= (void *)mlx5_ib_get_xlt_emergency_page();
981 memset(xlt
, 0, size
);
982 use_emergency_page
= true;
984 pages_iter
= size
/ desc_size
;
985 dma
= dma_map_single(ddev
, xlt
, size
, DMA_TO_DEVICE
);
986 if (dma_mapping_error(ddev
, dma
)) {
987 mlx5_ib_err(dev
, "unable to map DMA during XLT update.\n");
993 sg
.lkey
= dev
->umrc
.pd
->local_dma_lkey
;
995 memset(&wr
, 0, sizeof(wr
));
996 wr
.wr
.send_flags
= MLX5_IB_SEND_UMR_UPDATE_XLT
;
997 if (!(flags
& MLX5_IB_UPD_XLT_ENABLE
))
998 wr
.wr
.send_flags
|= MLX5_IB_SEND_UMR_FAIL_IF_FREE
;
1001 wr
.wr
.opcode
= MLX5_IB_WR_UMR
;
1003 wr
.pd
= mr
->ibmr
.pd
;
1004 wr
.mkey
= mr
->mmkey
.key
;
1005 wr
.length
= mr
->mmkey
.size
;
1006 wr
.virt_addr
= mr
->mmkey
.iova
;
1007 wr
.access_flags
= mr
->access_flags
;
1008 wr
.page_shift
= page_shift
;
1010 for (pages_mapped
= 0;
1011 pages_mapped
< pages_to_map
&& !err
;
1012 pages_mapped
+= pages_iter
, idx
+= pages_iter
) {
1013 npages
= min_t(int, pages_iter
, pages_to_map
- pages_mapped
);
1014 dma_sync_single_for_cpu(ddev
, dma
, size
, DMA_TO_DEVICE
);
1015 npages
= populate_xlt(mr
, idx
, npages
, xlt
,
1016 page_shift
, size
, flags
);
1018 dma_sync_single_for_device(ddev
, dma
, size
, DMA_TO_DEVICE
);
1020 sg
.length
= ALIGN(npages
* desc_size
,
1021 MLX5_UMR_MTT_ALIGNMENT
);
1023 if (pages_mapped
+ pages_iter
>= pages_to_map
) {
1024 if (flags
& MLX5_IB_UPD_XLT_ENABLE
)
1026 MLX5_IB_SEND_UMR_ENABLE_MR
|
1027 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
|
1028 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
;
1029 if (flags
& MLX5_IB_UPD_XLT_PD
||
1030 flags
& MLX5_IB_UPD_XLT_ACCESS
)
1032 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
;
1033 if (flags
& MLX5_IB_UPD_XLT_ADDR
)
1035 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
;
1038 wr
.offset
= idx
* desc_size
;
1039 wr
.xlt_size
= sg
.length
;
1041 err
= mlx5_ib_post_send_wait(dev
, &wr
);
1043 dma_unmap_single(ddev
, dma
, size
, DMA_TO_DEVICE
);
1046 if (use_emergency_page
)
1047 mlx5_ib_put_xlt_emergency_page();
1049 free_pages((unsigned long)xlt
, get_order(size
));
1055 * If ibmr is NULL it will be allocated by reg_create.
1056 * Else, the given ibmr will be used.
1058 static struct mlx5_ib_mr
*reg_create(struct ib_mr
*ibmr
, struct ib_pd
*pd
,
1059 u64 virt_addr
, u64 length
,
1060 struct ib_umem
*umem
, int npages
,
1061 int page_shift
, int access_flags
,
1064 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1065 struct mlx5_ib_mr
*mr
;
1071 bool pg_cap
= !!(MLX5_CAP_GEN(dev
->mdev
, pg
));
1073 mr
= ibmr
? to_mmr(ibmr
) : kzalloc(sizeof(*mr
), GFP_KERNEL
);
1075 return ERR_PTR(-ENOMEM
);
1078 mr
->access_flags
= access_flags
;
1080 inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
1082 inlen
+= sizeof(*pas
) * roundup(npages
, 2);
1083 in
= kvzalloc(inlen
, GFP_KERNEL
);
1088 pas
= (__be64
*)MLX5_ADDR_OF(create_mkey_in
, in
, klm_pas_mtt
);
1089 if (populate
&& !(access_flags
& IB_ACCESS_ON_DEMAND
))
1090 mlx5_ib_populate_pas(dev
, umem
, page_shift
, pas
,
1091 pg_cap
? MLX5_IB_MTT_PRESENT
: 0);
1093 /* The pg_access bit allows setting the access flags
1094 * in the page list submitted with the command. */
1095 MLX5_SET(create_mkey_in
, in
, pg_access
, !!(pg_cap
));
1097 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
1098 MLX5_SET(mkc
, mkc
, free
, !populate
);
1099 MLX5_SET(mkc
, mkc
, access_mode_1_0
, MLX5_MKC_ACCESS_MODE_MTT
);
1100 MLX5_SET(mkc
, mkc
, a
, !!(access_flags
& IB_ACCESS_REMOTE_ATOMIC
));
1101 MLX5_SET(mkc
, mkc
, rw
, !!(access_flags
& IB_ACCESS_REMOTE_WRITE
));
1102 MLX5_SET(mkc
, mkc
, rr
, !!(access_flags
& IB_ACCESS_REMOTE_READ
));
1103 MLX5_SET(mkc
, mkc
, lw
, !!(access_flags
& IB_ACCESS_LOCAL_WRITE
));
1104 MLX5_SET(mkc
, mkc
, lr
, 1);
1105 MLX5_SET(mkc
, mkc
, umr_en
, 1);
1107 MLX5_SET64(mkc
, mkc
, start_addr
, virt_addr
);
1108 MLX5_SET64(mkc
, mkc
, len
, length
);
1109 MLX5_SET(mkc
, mkc
, pd
, to_mpd(pd
)->pdn
);
1110 MLX5_SET(mkc
, mkc
, bsf_octword_size
, 0);
1111 MLX5_SET(mkc
, mkc
, translations_octword_size
,
1112 get_octo_len(virt_addr
, length
, page_shift
));
1113 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
1114 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
1116 MLX5_SET(create_mkey_in
, in
, translations_octword_actual_size
,
1117 get_octo_len(virt_addr
, length
, page_shift
));
1120 err
= mlx5_core_create_mkey(dev
->mdev
, &mr
->mmkey
, in
, inlen
);
1122 mlx5_ib_warn(dev
, "create mkey failed\n");
1125 mr
->mmkey
.type
= MLX5_MKEY_MR
;
1126 mr
->desc_size
= sizeof(struct mlx5_mtt
);
1130 mlx5_ib_dbg(dev
, "mkey = 0x%x\n", mr
->mmkey
.key
);
1141 return ERR_PTR(err
);
1144 static void set_mr_fields(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
,
1145 int npages
, u64 length
, int access_flags
)
1147 mr
->npages
= npages
;
1148 atomic_add(npages
, &dev
->mdev
->priv
.reg_pages
);
1149 mr
->ibmr
.lkey
= mr
->mmkey
.key
;
1150 mr
->ibmr
.rkey
= mr
->mmkey
.key
;
1151 mr
->ibmr
.length
= length
;
1152 mr
->access_flags
= access_flags
;
1155 static struct ib_mr
*mlx5_ib_get_dm_mr(struct ib_pd
*pd
, u64 start_addr
,
1156 u64 length
, int acc
, int mode
)
1158 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1159 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
1160 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1161 struct mlx5_ib_mr
*mr
;
1166 mr
= kzalloc(sizeof(*mr
), GFP_KERNEL
);
1168 return ERR_PTR(-ENOMEM
);
1170 in
= kzalloc(inlen
, GFP_KERNEL
);
1176 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
1178 MLX5_SET(mkc
, mkc
, access_mode_1_0
, mode
& 0x3);
1179 MLX5_SET(mkc
, mkc
, access_mode_4_2
, (mode
>> 2) & 0x7);
1180 MLX5_SET(mkc
, mkc
, a
, !!(acc
& IB_ACCESS_REMOTE_ATOMIC
));
1181 MLX5_SET(mkc
, mkc
, rw
, !!(acc
& IB_ACCESS_REMOTE_WRITE
));
1182 MLX5_SET(mkc
, mkc
, rr
, !!(acc
& IB_ACCESS_REMOTE_READ
));
1183 MLX5_SET(mkc
, mkc
, lw
, !!(acc
& IB_ACCESS_LOCAL_WRITE
));
1184 MLX5_SET(mkc
, mkc
, lr
, 1);
1186 MLX5_SET64(mkc
, mkc
, len
, length
);
1187 MLX5_SET(mkc
, mkc
, pd
, to_mpd(pd
)->pdn
);
1188 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
1189 MLX5_SET64(mkc
, mkc
, start_addr
, start_addr
);
1191 err
= mlx5_core_create_mkey(mdev
, &mr
->mmkey
, in
, inlen
);
1198 set_mr_fields(dev
, mr
, 0, length
, acc
);
1208 return ERR_PTR(err
);
1211 int mlx5_ib_advise_mr(struct ib_pd
*pd
,
1212 enum ib_uverbs_advise_mr_advice advice
,
1214 struct ib_sge
*sg_list
,
1216 struct uverbs_attr_bundle
*attrs
)
1218 if (advice
!= IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH
&&
1219 advice
!= IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE
)
1222 return mlx5_ib_advise_mr_prefetch(pd
, advice
, flags
,
1226 struct ib_mr
*mlx5_ib_reg_dm_mr(struct ib_pd
*pd
, struct ib_dm
*dm
,
1227 struct ib_dm_mr_attr
*attr
,
1228 struct uverbs_attr_bundle
*attrs
)
1230 struct mlx5_ib_dm
*mdm
= to_mdm(dm
);
1231 struct mlx5_core_dev
*dev
= to_mdev(dm
->device
)->mdev
;
1232 u64 start_addr
= mdm
->dev_addr
+ attr
->offset
;
1235 switch (mdm
->type
) {
1236 case MLX5_IB_UAPI_DM_TYPE_MEMIC
:
1237 if (attr
->access_flags
& ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS
)
1238 return ERR_PTR(-EINVAL
);
1240 mode
= MLX5_MKC_ACCESS_MODE_MEMIC
;
1241 start_addr
-= pci_resource_start(dev
->pdev
, 0);
1243 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM
:
1244 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM
:
1245 if (attr
->access_flags
& ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS
)
1246 return ERR_PTR(-EINVAL
);
1248 mode
= MLX5_MKC_ACCESS_MODE_SW_ICM
;
1251 return ERR_PTR(-EINVAL
);
1254 return mlx5_ib_get_dm_mr(pd
, start_addr
, attr
->length
,
1255 attr
->access_flags
, mode
);
1258 struct ib_mr
*mlx5_ib_reg_user_mr(struct ib_pd
*pd
, u64 start
, u64 length
,
1259 u64 virt_addr
, int access_flags
,
1260 struct ib_udata
*udata
)
1262 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1263 struct mlx5_ib_mr
*mr
= NULL
;
1265 struct ib_umem
*umem
;
1272 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM
))
1273 return ERR_PTR(-EOPNOTSUPP
);
1275 mlx5_ib_dbg(dev
, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1276 start
, virt_addr
, length
, access_flags
);
1278 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
) && !start
&&
1279 length
== U64_MAX
) {
1280 if (!(access_flags
& IB_ACCESS_ON_DEMAND
) ||
1281 !(dev
->odp_caps
.general_caps
& IB_ODP_SUPPORT_IMPLICIT
))
1282 return ERR_PTR(-EINVAL
);
1284 mr
= mlx5_ib_alloc_implicit_mr(to_mpd(pd
), udata
, access_flags
);
1286 return ERR_CAST(mr
);
1290 err
= mr_umem_get(dev
, udata
, start
, length
, access_flags
, &umem
,
1291 &npages
, &page_shift
, &ncont
, &order
);
1294 return ERR_PTR(err
);
1296 use_umr
= !MLX5_CAP_GEN(dev
->mdev
, umr_modify_entity_size_disabled
) &&
1297 (!MLX5_CAP_GEN(dev
->mdev
, umr_modify_atomic_disabled
) ||
1298 !MLX5_CAP_GEN(dev
->mdev
, atomic
));
1300 if (order
<= mr_cache_max_order(dev
) && use_umr
) {
1301 mr
= alloc_mr_from_cache(pd
, umem
, virt_addr
, length
, ncont
,
1302 page_shift
, order
, access_flags
);
1303 if (PTR_ERR(mr
) == -EAGAIN
) {
1304 mlx5_ib_dbg(dev
, "cache empty for order %d\n", order
);
1307 } else if (!MLX5_CAP_GEN(dev
->mdev
, umr_extended_translation_offset
)) {
1308 if (access_flags
& IB_ACCESS_ON_DEMAND
) {
1310 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n");
1317 mutex_lock(&dev
->slow_path_mutex
);
1318 mr
= reg_create(NULL
, pd
, virt_addr
, length
, umem
, ncont
,
1319 page_shift
, access_flags
, !use_umr
);
1320 mutex_unlock(&dev
->slow_path_mutex
);
1328 mlx5_ib_dbg(dev
, "mkey 0x%x\n", mr
->mmkey
.key
);
1331 set_mr_fields(dev
, mr
, npages
, length
, access_flags
);
1336 int update_xlt_flags
= MLX5_IB_UPD_XLT_ENABLE
;
1338 if (access_flags
& IB_ACCESS_ON_DEMAND
)
1339 update_xlt_flags
|= MLX5_IB_UPD_XLT_ZAP
;
1341 err
= mlx5_ib_update_xlt(mr
, 0, ncont
, page_shift
,
1346 return ERR_PTR(err
);
1350 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
)) {
1352 atomic_set(&mr
->num_pending_prefetch
, 0);
1357 ib_umem_release(umem
);
1358 return ERR_PTR(err
);
1361 static int unreg_umr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
)
1363 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1364 struct mlx5_umr_wr umrwr
= {};
1366 if (mdev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
)
1369 umrwr
.wr
.send_flags
= MLX5_IB_SEND_UMR_DISABLE_MR
|
1370 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
;
1371 umrwr
.wr
.opcode
= MLX5_IB_WR_UMR
;
1372 umrwr
.pd
= dev
->umrc
.pd
;
1373 umrwr
.mkey
= mr
->mmkey
.key
;
1374 umrwr
.ignore_free_state
= 1;
1376 return mlx5_ib_post_send_wait(dev
, &umrwr
);
1379 static int rereg_umr(struct ib_pd
*pd
, struct mlx5_ib_mr
*mr
,
1380 int access_flags
, int flags
)
1382 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1383 struct mlx5_umr_wr umrwr
= {};
1386 umrwr
.wr
.send_flags
= MLX5_IB_SEND_UMR_FAIL_IF_FREE
;
1388 umrwr
.wr
.opcode
= MLX5_IB_WR_UMR
;
1389 umrwr
.mkey
= mr
->mmkey
.key
;
1391 if (flags
& IB_MR_REREG_PD
|| flags
& IB_MR_REREG_ACCESS
) {
1393 umrwr
.access_flags
= access_flags
;
1394 umrwr
.wr
.send_flags
|= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
;
1397 err
= mlx5_ib_post_send_wait(dev
, &umrwr
);
1402 int mlx5_ib_rereg_user_mr(struct ib_mr
*ib_mr
, int flags
, u64 start
,
1403 u64 length
, u64 virt_addr
, int new_access_flags
,
1404 struct ib_pd
*new_pd
, struct ib_udata
*udata
)
1406 struct mlx5_ib_dev
*dev
= to_mdev(ib_mr
->device
);
1407 struct mlx5_ib_mr
*mr
= to_mmr(ib_mr
);
1408 struct ib_pd
*pd
= (flags
& IB_MR_REREG_PD
) ? new_pd
: ib_mr
->pd
;
1409 int access_flags
= flags
& IB_MR_REREG_ACCESS
?
1420 mlx5_ib_dbg(dev
, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1421 start
, virt_addr
, length
, access_flags
);
1423 atomic_sub(mr
->npages
, &dev
->mdev
->priv
.reg_pages
);
1428 if (flags
& IB_MR_REREG_TRANS
) {
1432 addr
= mr
->umem
->address
;
1433 len
= mr
->umem
->length
;
1436 if (flags
!= IB_MR_REREG_PD
) {
1438 * Replace umem. This needs to be done whether or not UMR is
1441 flags
|= IB_MR_REREG_TRANS
;
1442 ib_umem_release(mr
->umem
);
1444 err
= mr_umem_get(dev
, udata
, addr
, len
, access_flags
,
1445 &mr
->umem
, &npages
, &page_shift
, &ncont
,
1451 if (flags
& IB_MR_REREG_TRANS
&& !use_umr_mtt_update(mr
, addr
, len
)) {
1453 * UMR can't be used - MKey needs to be replaced.
1455 if (mr
->allocated_from_cache
)
1456 err
= unreg_umr(dev
, mr
);
1458 err
= destroy_mkey(dev
, mr
);
1462 mr
= reg_create(ib_mr
, pd
, addr
, len
, mr
->umem
, ncont
,
1463 page_shift
, access_flags
, true);
1471 mr
->allocated_from_cache
= 0;
1472 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING
))
1479 mr
->access_flags
= access_flags
;
1480 mr
->mmkey
.iova
= addr
;
1481 mr
->mmkey
.size
= len
;
1482 mr
->mmkey
.pd
= to_mpd(pd
)->pdn
;
1484 if (flags
& IB_MR_REREG_TRANS
) {
1485 upd_flags
= MLX5_IB_UPD_XLT_ADDR
;
1486 if (flags
& IB_MR_REREG_PD
)
1487 upd_flags
|= MLX5_IB_UPD_XLT_PD
;
1488 if (flags
& IB_MR_REREG_ACCESS
)
1489 upd_flags
|= MLX5_IB_UPD_XLT_ACCESS
;
1490 err
= mlx5_ib_update_xlt(mr
, 0, npages
, page_shift
,
1493 err
= rereg_umr(pd
, mr
, access_flags
, flags
);
1500 set_mr_fields(dev
, mr
, npages
, len
, access_flags
);
1506 ib_umem_release(mr
->umem
);
1514 mlx5_alloc_priv_descs(struct ib_device
*device
,
1515 struct mlx5_ib_mr
*mr
,
1519 int size
= ndescs
* desc_size
;
1523 add_size
= max_t(int, MLX5_UMR_ALIGN
- ARCH_KMALLOC_MINALIGN
, 0);
1525 mr
->descs_alloc
= kzalloc(size
+ add_size
, GFP_KERNEL
);
1526 if (!mr
->descs_alloc
)
1529 mr
->descs
= PTR_ALIGN(mr
->descs_alloc
, MLX5_UMR_ALIGN
);
1531 mr
->desc_map
= dma_map_single(device
->dev
.parent
, mr
->descs
,
1532 size
, DMA_TO_DEVICE
);
1533 if (dma_mapping_error(device
->dev
.parent
, mr
->desc_map
)) {
1540 kfree(mr
->descs_alloc
);
1546 mlx5_free_priv_descs(struct mlx5_ib_mr
*mr
)
1549 struct ib_device
*device
= mr
->ibmr
.device
;
1550 int size
= mr
->max_descs
* mr
->desc_size
;
1552 dma_unmap_single(device
->dev
.parent
, mr
->desc_map
,
1553 size
, DMA_TO_DEVICE
);
1554 kfree(mr
->descs_alloc
);
1559 static void clean_mr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
)
1561 int allocated_from_cache
= mr
->allocated_from_cache
;
1564 if (mlx5_core_destroy_psv(dev
->mdev
,
1565 mr
->sig
->psv_memory
.psv_idx
))
1566 mlx5_ib_warn(dev
, "failed to destroy mem psv %d\n",
1567 mr
->sig
->psv_memory
.psv_idx
);
1568 if (mlx5_core_destroy_psv(dev
->mdev
,
1569 mr
->sig
->psv_wire
.psv_idx
))
1570 mlx5_ib_warn(dev
, "failed to destroy wire psv %d\n",
1571 mr
->sig
->psv_wire
.psv_idx
);
1576 if (!allocated_from_cache
) {
1577 destroy_mkey(dev
, mr
);
1578 mlx5_free_priv_descs(mr
);
1582 static void dereg_mr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_mr
*mr
)
1584 int npages
= mr
->npages
;
1585 struct ib_umem
*umem
= mr
->umem
;
1587 if (is_odp_mr(mr
)) {
1588 struct ib_umem_odp
*umem_odp
= to_ib_umem_odp(umem
);
1590 /* Prevent new page faults and
1591 * prefetch requests from succeeding
1595 /* dequeue pending prefetch requests for the mr */
1596 if (atomic_read(&mr
->num_pending_prefetch
))
1597 flush_workqueue(system_unbound_wq
);
1598 WARN_ON(atomic_read(&mr
->num_pending_prefetch
));
1600 /* Wait for all running page-fault handlers to finish. */
1601 synchronize_srcu(&dev
->mr_srcu
);
1602 /* Destroy all page mappings */
1603 if (umem_odp
->page_list
)
1604 mlx5_ib_invalidate_range(umem_odp
,
1605 ib_umem_start(umem_odp
),
1606 ib_umem_end(umem_odp
));
1608 mlx5_ib_free_implicit_mr(mr
);
1610 * We kill the umem before the MR for ODP,
1611 * so that there will not be any invalidations in
1612 * flight, looking at the *mr struct.
1614 ib_umem_release(umem
);
1615 atomic_sub(npages
, &dev
->mdev
->priv
.reg_pages
);
1617 /* Avoid double-freeing the umem. */
1624 * We should unregister the DMA address from the HCA before
1625 * remove the DMA mapping.
1627 mlx5_mr_cache_free(dev
, mr
);
1628 ib_umem_release(umem
);
1630 atomic_sub(npages
, &dev
->mdev
->priv
.reg_pages
);
1632 if (!mr
->allocated_from_cache
)
1636 int mlx5_ib_dereg_mr(struct ib_mr
*ibmr
, struct ib_udata
*udata
)
1638 struct mlx5_ib_mr
*mmr
= to_mmr(ibmr
);
1640 if (ibmr
->type
== IB_MR_TYPE_INTEGRITY
) {
1641 dereg_mr(to_mdev(mmr
->mtt_mr
->ibmr
.device
), mmr
->mtt_mr
);
1642 dereg_mr(to_mdev(mmr
->klm_mr
->ibmr
.device
), mmr
->klm_mr
);
1645 dereg_mr(to_mdev(ibmr
->device
), mmr
);
1650 static void mlx5_set_umr_free_mkey(struct ib_pd
*pd
, u32
*in
, int ndescs
,
1651 int access_mode
, int page_shift
)
1655 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
1657 MLX5_SET(mkc
, mkc
, free
, 1);
1658 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
1659 MLX5_SET(mkc
, mkc
, pd
, to_mpd(pd
)->pdn
);
1660 MLX5_SET(mkc
, mkc
, translations_octword_size
, ndescs
);
1661 MLX5_SET(mkc
, mkc
, access_mode_1_0
, access_mode
& 0x3);
1662 MLX5_SET(mkc
, mkc
, access_mode_4_2
, (access_mode
>> 2) & 0x7);
1663 MLX5_SET(mkc
, mkc
, umr_en
, 1);
1664 MLX5_SET(mkc
, mkc
, log_page_size
, page_shift
);
1667 static int _mlx5_alloc_mkey_descs(struct ib_pd
*pd
, struct mlx5_ib_mr
*mr
,
1668 int ndescs
, int desc_size
, int page_shift
,
1669 int access_mode
, u32
*in
, int inlen
)
1671 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1674 mr
->access_mode
= access_mode
;
1675 mr
->desc_size
= desc_size
;
1676 mr
->max_descs
= ndescs
;
1678 err
= mlx5_alloc_priv_descs(pd
->device
, mr
, ndescs
, desc_size
);
1682 mlx5_set_umr_free_mkey(pd
, in
, ndescs
, access_mode
, page_shift
);
1684 err
= mlx5_core_create_mkey(dev
->mdev
, &mr
->mmkey
, in
, inlen
);
1686 goto err_free_descs
;
1688 mr
->mmkey
.type
= MLX5_MKEY_MR
;
1689 mr
->ibmr
.lkey
= mr
->mmkey
.key
;
1690 mr
->ibmr
.rkey
= mr
->mmkey
.key
;
1695 mlx5_free_priv_descs(mr
);
1699 static struct mlx5_ib_mr
*mlx5_ib_alloc_pi_mr(struct ib_pd
*pd
,
1700 u32 max_num_sg
, u32 max_num_meta_sg
,
1701 int desc_size
, int access_mode
)
1703 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
1704 int ndescs
= ALIGN(max_num_sg
+ max_num_meta_sg
, 4);
1706 struct mlx5_ib_mr
*mr
;
1710 mr
= kzalloc(sizeof(*mr
), GFP_KERNEL
);
1712 return ERR_PTR(-ENOMEM
);
1715 mr
->ibmr
.device
= pd
->device
;
1717 in
= kzalloc(inlen
, GFP_KERNEL
);
1723 if (access_mode
== MLX5_MKC_ACCESS_MODE_MTT
)
1724 page_shift
= PAGE_SHIFT
;
1726 err
= _mlx5_alloc_mkey_descs(pd
, mr
, ndescs
, desc_size
, page_shift
,
1727 access_mode
, in
, inlen
);
1740 return ERR_PTR(err
);
1743 static int mlx5_alloc_mem_reg_descs(struct ib_pd
*pd
, struct mlx5_ib_mr
*mr
,
1744 int ndescs
, u32
*in
, int inlen
)
1746 return _mlx5_alloc_mkey_descs(pd
, mr
, ndescs
, sizeof(struct mlx5_mtt
),
1747 PAGE_SHIFT
, MLX5_MKC_ACCESS_MODE_MTT
, in
,
1751 static int mlx5_alloc_sg_gaps_descs(struct ib_pd
*pd
, struct mlx5_ib_mr
*mr
,
1752 int ndescs
, u32
*in
, int inlen
)
1754 return _mlx5_alloc_mkey_descs(pd
, mr
, ndescs
, sizeof(struct mlx5_klm
),
1755 0, MLX5_MKC_ACCESS_MODE_KLMS
, in
, inlen
);
1758 static int mlx5_alloc_integrity_descs(struct ib_pd
*pd
, struct mlx5_ib_mr
*mr
,
1759 int max_num_sg
, int max_num_meta_sg
,
1762 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1767 mr
->sig
= kzalloc(sizeof(*mr
->sig
), GFP_KERNEL
);
1771 /* create mem & wire PSVs */
1772 err
= mlx5_core_create_psv(dev
->mdev
, to_mpd(pd
)->pdn
, 2, psv_index
);
1776 mr
->sig
->psv_memory
.psv_idx
= psv_index
[0];
1777 mr
->sig
->psv_wire
.psv_idx
= psv_index
[1];
1779 mr
->sig
->sig_status_checked
= true;
1780 mr
->sig
->sig_err_exists
= false;
1781 /* Next UMR, Arm SIGERR */
1782 ++mr
->sig
->sigerr_count
;
1783 mr
->klm_mr
= mlx5_ib_alloc_pi_mr(pd
, max_num_sg
, max_num_meta_sg
,
1784 sizeof(struct mlx5_klm
),
1785 MLX5_MKC_ACCESS_MODE_KLMS
);
1786 if (IS_ERR(mr
->klm_mr
)) {
1787 err
= PTR_ERR(mr
->klm_mr
);
1788 goto err_destroy_psv
;
1790 mr
->mtt_mr
= mlx5_ib_alloc_pi_mr(pd
, max_num_sg
, max_num_meta_sg
,
1791 sizeof(struct mlx5_mtt
),
1792 MLX5_MKC_ACCESS_MODE_MTT
);
1793 if (IS_ERR(mr
->mtt_mr
)) {
1794 err
= PTR_ERR(mr
->mtt_mr
);
1795 goto err_free_klm_mr
;
1798 /* Set bsf descriptors for mkey */
1799 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
1800 MLX5_SET(mkc
, mkc
, bsf_en
, 1);
1801 MLX5_SET(mkc
, mkc
, bsf_octword_size
, MLX5_MKEY_BSF_OCTO_SIZE
);
1803 err
= _mlx5_alloc_mkey_descs(pd
, mr
, 4, sizeof(struct mlx5_klm
), 0,
1804 MLX5_MKC_ACCESS_MODE_KLMS
, in
, inlen
);
1806 goto err_free_mtt_mr
;
1811 dereg_mr(to_mdev(mr
->mtt_mr
->ibmr
.device
), mr
->mtt_mr
);
1814 dereg_mr(to_mdev(mr
->klm_mr
->ibmr
.device
), mr
->klm_mr
);
1817 if (mlx5_core_destroy_psv(dev
->mdev
, mr
->sig
->psv_memory
.psv_idx
))
1818 mlx5_ib_warn(dev
, "failed to destroy mem psv %d\n",
1819 mr
->sig
->psv_memory
.psv_idx
);
1820 if (mlx5_core_destroy_psv(dev
->mdev
, mr
->sig
->psv_wire
.psv_idx
))
1821 mlx5_ib_warn(dev
, "failed to destroy wire psv %d\n",
1822 mr
->sig
->psv_wire
.psv_idx
);
1829 static struct ib_mr
*__mlx5_ib_alloc_mr(struct ib_pd
*pd
,
1830 enum ib_mr_type mr_type
, u32 max_num_sg
,
1831 u32 max_num_meta_sg
)
1833 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1834 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
1835 int ndescs
= ALIGN(max_num_sg
, 4);
1836 struct mlx5_ib_mr
*mr
;
1840 mr
= kzalloc(sizeof(*mr
), GFP_KERNEL
);
1842 return ERR_PTR(-ENOMEM
);
1844 in
= kzalloc(inlen
, GFP_KERNEL
);
1850 mr
->ibmr
.device
= pd
->device
;
1854 case IB_MR_TYPE_MEM_REG
:
1855 err
= mlx5_alloc_mem_reg_descs(pd
, mr
, ndescs
, in
, inlen
);
1857 case IB_MR_TYPE_SG_GAPS
:
1858 err
= mlx5_alloc_sg_gaps_descs(pd
, mr
, ndescs
, in
, inlen
);
1860 case IB_MR_TYPE_INTEGRITY
:
1861 err
= mlx5_alloc_integrity_descs(pd
, mr
, max_num_sg
,
1862 max_num_meta_sg
, in
, inlen
);
1865 mlx5_ib_warn(dev
, "Invalid mr type %d\n", mr_type
);
1880 return ERR_PTR(err
);
1883 struct ib_mr
*mlx5_ib_alloc_mr(struct ib_pd
*pd
, enum ib_mr_type mr_type
,
1884 u32 max_num_sg
, struct ib_udata
*udata
)
1886 return __mlx5_ib_alloc_mr(pd
, mr_type
, max_num_sg
, 0);
1889 struct ib_mr
*mlx5_ib_alloc_mr_integrity(struct ib_pd
*pd
,
1890 u32 max_num_sg
, u32 max_num_meta_sg
)
1892 return __mlx5_ib_alloc_mr(pd
, IB_MR_TYPE_INTEGRITY
, max_num_sg
,
1896 struct ib_mw
*mlx5_ib_alloc_mw(struct ib_pd
*pd
, enum ib_mw_type type
,
1897 struct ib_udata
*udata
)
1899 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
1900 int inlen
= MLX5_ST_SZ_BYTES(create_mkey_in
);
1901 struct mlx5_ib_mw
*mw
= NULL
;
1906 struct mlx5_ib_alloc_mw req
= {};
1909 __u32 response_length
;
1912 err
= ib_copy_from_udata(&req
, udata
, min(udata
->inlen
, sizeof(req
)));
1914 return ERR_PTR(err
);
1916 if (req
.comp_mask
|| req
.reserved1
|| req
.reserved2
)
1917 return ERR_PTR(-EOPNOTSUPP
);
1919 if (udata
->inlen
> sizeof(req
) &&
1920 !ib_is_udata_cleared(udata
, sizeof(req
),
1921 udata
->inlen
- sizeof(req
)))
1922 return ERR_PTR(-EOPNOTSUPP
);
1924 ndescs
= req
.num_klms
? roundup(req
.num_klms
, 4) : roundup(1, 4);
1926 mw
= kzalloc(sizeof(*mw
), GFP_KERNEL
);
1927 in
= kzalloc(inlen
, GFP_KERNEL
);
1933 mkc
= MLX5_ADDR_OF(create_mkey_in
, in
, memory_key_mkey_entry
);
1935 MLX5_SET(mkc
, mkc
, free
, 1);
1936 MLX5_SET(mkc
, mkc
, translations_octword_size
, ndescs
);
1937 MLX5_SET(mkc
, mkc
, pd
, to_mpd(pd
)->pdn
);
1938 MLX5_SET(mkc
, mkc
, umr_en
, 1);
1939 MLX5_SET(mkc
, mkc
, lr
, 1);
1940 MLX5_SET(mkc
, mkc
, access_mode_1_0
, MLX5_MKC_ACCESS_MODE_KLMS
);
1941 MLX5_SET(mkc
, mkc
, en_rinval
, !!((type
== IB_MW_TYPE_2
)));
1942 MLX5_SET(mkc
, mkc
, qpn
, 0xffffff);
1944 err
= mlx5_core_create_mkey(dev
->mdev
, &mw
->mmkey
, in
, inlen
);
1948 mw
->mmkey
.type
= MLX5_MKEY_MW
;
1949 mw
->ibmw
.rkey
= mw
->mmkey
.key
;
1950 mw
->ndescs
= ndescs
;
1952 resp
.response_length
= min(offsetof(typeof(resp
), response_length
) +
1953 sizeof(resp
.response_length
), udata
->outlen
);
1954 if (resp
.response_length
) {
1955 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
1957 mlx5_core_destroy_mkey(dev
->mdev
, &mw
->mmkey
);
1968 return ERR_PTR(err
);
1971 int mlx5_ib_dealloc_mw(struct ib_mw
*mw
)
1973 struct mlx5_ib_mw
*mmw
= to_mmw(mw
);
1976 err
= mlx5_core_destroy_mkey((to_mdev(mw
->device
))->mdev
,
1983 int mlx5_ib_check_mr_status(struct ib_mr
*ibmr
, u32 check_mask
,
1984 struct ib_mr_status
*mr_status
)
1986 struct mlx5_ib_mr
*mmr
= to_mmr(ibmr
);
1989 if (check_mask
& ~IB_MR_CHECK_SIG_STATUS
) {
1990 pr_err("Invalid status check mask\n");
1995 mr_status
->fail_status
= 0;
1996 if (check_mask
& IB_MR_CHECK_SIG_STATUS
) {
1999 pr_err("signature status check requested on a non-signature enabled MR\n");
2003 mmr
->sig
->sig_status_checked
= true;
2004 if (!mmr
->sig
->sig_err_exists
)
2007 if (ibmr
->lkey
== mmr
->sig
->err_item
.key
)
2008 memcpy(&mr_status
->sig_err
, &mmr
->sig
->err_item
,
2009 sizeof(mr_status
->sig_err
));
2011 mr_status
->sig_err
.err_type
= IB_SIG_BAD_GUARD
;
2012 mr_status
->sig_err
.sig_err_offset
= 0;
2013 mr_status
->sig_err
.key
= mmr
->sig
->err_item
.key
;
2016 mmr
->sig
->sig_err_exists
= false;
2017 mr_status
->fail_status
|= IB_MR_CHECK_SIG_STATUS
;
2025 mlx5_ib_map_pa_mr_sg_pi(struct ib_mr
*ibmr
, struct scatterlist
*data_sg
,
2026 int data_sg_nents
, unsigned int *data_sg_offset
,
2027 struct scatterlist
*meta_sg
, int meta_sg_nents
,
2028 unsigned int *meta_sg_offset
)
2030 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2031 unsigned int sg_offset
= 0;
2034 mr
->meta_length
= 0;
2035 if (data_sg_nents
== 1) {
2039 sg_offset
= *data_sg_offset
;
2040 mr
->data_length
= sg_dma_len(data_sg
) - sg_offset
;
2041 mr
->data_iova
= sg_dma_address(data_sg
) + sg_offset
;
2042 if (meta_sg_nents
== 1) {
2044 mr
->meta_ndescs
= 1;
2046 sg_offset
= *meta_sg_offset
;
2049 mr
->meta_length
= sg_dma_len(meta_sg
) - sg_offset
;
2050 mr
->pi_iova
= sg_dma_address(meta_sg
) + sg_offset
;
2052 ibmr
->length
= mr
->data_length
+ mr
->meta_length
;
2059 mlx5_ib_sg_to_klms(struct mlx5_ib_mr
*mr
,
2060 struct scatterlist
*sgl
,
2061 unsigned short sg_nents
,
2062 unsigned int *sg_offset_p
,
2063 struct scatterlist
*meta_sgl
,
2064 unsigned short meta_sg_nents
,
2065 unsigned int *meta_sg_offset_p
)
2067 struct scatterlist
*sg
= sgl
;
2068 struct mlx5_klm
*klms
= mr
->descs
;
2069 unsigned int sg_offset
= sg_offset_p
? *sg_offset_p
: 0;
2070 u32 lkey
= mr
->ibmr
.pd
->local_dma_lkey
;
2073 mr
->ibmr
.iova
= sg_dma_address(sg
) + sg_offset
;
2074 mr
->ibmr
.length
= 0;
2076 for_each_sg(sgl
, sg
, sg_nents
, i
) {
2077 if (unlikely(i
>= mr
->max_descs
))
2079 klms
[i
].va
= cpu_to_be64(sg_dma_address(sg
) + sg_offset
);
2080 klms
[i
].bcount
= cpu_to_be32(sg_dma_len(sg
) - sg_offset
);
2081 klms
[i
].key
= cpu_to_be32(lkey
);
2082 mr
->ibmr
.length
+= sg_dma_len(sg
) - sg_offset
;
2088 *sg_offset_p
= sg_offset
;
2091 mr
->data_length
= mr
->ibmr
.length
;
2093 if (meta_sg_nents
) {
2095 sg_offset
= meta_sg_offset_p
? *meta_sg_offset_p
: 0;
2096 for_each_sg(meta_sgl
, sg
, meta_sg_nents
, j
) {
2097 if (unlikely(i
+ j
>= mr
->max_descs
))
2099 klms
[i
+ j
].va
= cpu_to_be64(sg_dma_address(sg
) +
2101 klms
[i
+ j
].bcount
= cpu_to_be32(sg_dma_len(sg
) -
2103 klms
[i
+ j
].key
= cpu_to_be32(lkey
);
2104 mr
->ibmr
.length
+= sg_dma_len(sg
) - sg_offset
;
2108 if (meta_sg_offset_p
)
2109 *meta_sg_offset_p
= sg_offset
;
2111 mr
->meta_ndescs
= j
;
2112 mr
->meta_length
= mr
->ibmr
.length
- mr
->data_length
;
2118 static int mlx5_set_page(struct ib_mr
*ibmr
, u64 addr
)
2120 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2123 if (unlikely(mr
->ndescs
== mr
->max_descs
))
2127 descs
[mr
->ndescs
++] = cpu_to_be64(addr
| MLX5_EN_RD
| MLX5_EN_WR
);
2132 static int mlx5_set_page_pi(struct ib_mr
*ibmr
, u64 addr
)
2134 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2137 if (unlikely(mr
->ndescs
+ mr
->meta_ndescs
== mr
->max_descs
))
2141 descs
[mr
->ndescs
+ mr
->meta_ndescs
++] =
2142 cpu_to_be64(addr
| MLX5_EN_RD
| MLX5_EN_WR
);
2148 mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr
*ibmr
, struct scatterlist
*data_sg
,
2149 int data_sg_nents
, unsigned int *data_sg_offset
,
2150 struct scatterlist
*meta_sg
, int meta_sg_nents
,
2151 unsigned int *meta_sg_offset
)
2153 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2154 struct mlx5_ib_mr
*pi_mr
= mr
->mtt_mr
;
2158 pi_mr
->meta_ndescs
= 0;
2159 pi_mr
->meta_length
= 0;
2161 ib_dma_sync_single_for_cpu(ibmr
->device
, pi_mr
->desc_map
,
2162 pi_mr
->desc_size
* pi_mr
->max_descs
,
2165 pi_mr
->ibmr
.page_size
= ibmr
->page_size
;
2166 n
= ib_sg_to_pages(&pi_mr
->ibmr
, data_sg
, data_sg_nents
, data_sg_offset
,
2168 if (n
!= data_sg_nents
)
2171 pi_mr
->data_iova
= pi_mr
->ibmr
.iova
;
2172 pi_mr
->data_length
= pi_mr
->ibmr
.length
;
2173 pi_mr
->ibmr
.length
= pi_mr
->data_length
;
2174 ibmr
->length
= pi_mr
->data_length
;
2176 if (meta_sg_nents
) {
2177 u64 page_mask
= ~((u64
)ibmr
->page_size
- 1);
2178 u64 iova
= pi_mr
->data_iova
;
2180 n
+= ib_sg_to_pages(&pi_mr
->ibmr
, meta_sg
, meta_sg_nents
,
2181 meta_sg_offset
, mlx5_set_page_pi
);
2183 pi_mr
->meta_length
= pi_mr
->ibmr
.length
;
2185 * PI address for the HW is the offset of the metadata address
2186 * relative to the first data page address.
2187 * It equals to first data page address + size of data pages +
2188 * metadata offset at the first metadata page
2190 pi_mr
->pi_iova
= (iova
& page_mask
) +
2191 pi_mr
->ndescs
* ibmr
->page_size
+
2192 (pi_mr
->ibmr
.iova
& ~page_mask
);
2194 * In order to use one MTT MR for data and metadata, we register
2195 * also the gaps between the end of the data and the start of
2196 * the metadata (the sig MR will verify that the HW will access
2197 * to right addresses). This mapping is safe because we use
2198 * internal mkey for the registration.
2200 pi_mr
->ibmr
.length
= pi_mr
->pi_iova
+ pi_mr
->meta_length
- iova
;
2201 pi_mr
->ibmr
.iova
= iova
;
2202 ibmr
->length
+= pi_mr
->meta_length
;
2205 ib_dma_sync_single_for_device(ibmr
->device
, pi_mr
->desc_map
,
2206 pi_mr
->desc_size
* pi_mr
->max_descs
,
2213 mlx5_ib_map_klm_mr_sg_pi(struct ib_mr
*ibmr
, struct scatterlist
*data_sg
,
2214 int data_sg_nents
, unsigned int *data_sg_offset
,
2215 struct scatterlist
*meta_sg
, int meta_sg_nents
,
2216 unsigned int *meta_sg_offset
)
2218 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2219 struct mlx5_ib_mr
*pi_mr
= mr
->klm_mr
;
2223 pi_mr
->meta_ndescs
= 0;
2224 pi_mr
->meta_length
= 0;
2226 ib_dma_sync_single_for_cpu(ibmr
->device
, pi_mr
->desc_map
,
2227 pi_mr
->desc_size
* pi_mr
->max_descs
,
2230 n
= mlx5_ib_sg_to_klms(pi_mr
, data_sg
, data_sg_nents
, data_sg_offset
,
2231 meta_sg
, meta_sg_nents
, meta_sg_offset
);
2233 ib_dma_sync_single_for_device(ibmr
->device
, pi_mr
->desc_map
,
2234 pi_mr
->desc_size
* pi_mr
->max_descs
,
2237 /* This is zero-based memory region */
2238 pi_mr
->data_iova
= 0;
2239 pi_mr
->ibmr
.iova
= 0;
2240 pi_mr
->pi_iova
= pi_mr
->data_length
;
2241 ibmr
->length
= pi_mr
->ibmr
.length
;
2246 int mlx5_ib_map_mr_sg_pi(struct ib_mr
*ibmr
, struct scatterlist
*data_sg
,
2247 int data_sg_nents
, unsigned int *data_sg_offset
,
2248 struct scatterlist
*meta_sg
, int meta_sg_nents
,
2249 unsigned int *meta_sg_offset
)
2251 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2252 struct mlx5_ib_mr
*pi_mr
= NULL
;
2255 WARN_ON(ibmr
->type
!= IB_MR_TYPE_INTEGRITY
);
2258 mr
->data_length
= 0;
2260 mr
->meta_ndescs
= 0;
2263 * As a performance optimization, if possible, there is no need to
2264 * perform UMR operation to register the data/metadata buffers.
2265 * First try to map the sg lists to PA descriptors with local_dma_lkey.
2266 * Fallback to UMR only in case of a failure.
2268 n
= mlx5_ib_map_pa_mr_sg_pi(ibmr
, data_sg
, data_sg_nents
,
2269 data_sg_offset
, meta_sg
, meta_sg_nents
,
2271 if (n
== data_sg_nents
+ meta_sg_nents
)
2274 * As a performance optimization, if possible, there is no need to map
2275 * the sg lists to KLM descriptors. First try to map the sg lists to MTT
2276 * descriptors and fallback to KLM only in case of a failure.
2277 * It's more efficient for the HW to work with MTT descriptors
2278 * (especially in high load).
2279 * Use KLM (indirect access) only if it's mandatory.
2282 n
= mlx5_ib_map_mtt_mr_sg_pi(ibmr
, data_sg
, data_sg_nents
,
2283 data_sg_offset
, meta_sg
, meta_sg_nents
,
2285 if (n
== data_sg_nents
+ meta_sg_nents
)
2289 n
= mlx5_ib_map_klm_mr_sg_pi(ibmr
, data_sg
, data_sg_nents
,
2290 data_sg_offset
, meta_sg
, meta_sg_nents
,
2292 if (unlikely(n
!= data_sg_nents
+ meta_sg_nents
))
2296 /* This is zero-based memory region */
2300 ibmr
->sig_attrs
->meta_length
= pi_mr
->meta_length
;
2302 ibmr
->sig_attrs
->meta_length
= mr
->meta_length
;
2307 int mlx5_ib_map_mr_sg(struct ib_mr
*ibmr
, struct scatterlist
*sg
, int sg_nents
,
2308 unsigned int *sg_offset
)
2310 struct mlx5_ib_mr
*mr
= to_mmr(ibmr
);
2315 ib_dma_sync_single_for_cpu(ibmr
->device
, mr
->desc_map
,
2316 mr
->desc_size
* mr
->max_descs
,
2319 if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_KLMS
)
2320 n
= mlx5_ib_sg_to_klms(mr
, sg
, sg_nents
, sg_offset
, NULL
, 0,
2323 n
= ib_sg_to_pages(ibmr
, sg
, sg_nents
, sg_offset
,
2326 ib_dma_sync_single_for_device(ibmr
->device
, mr
->desc_map
,
2327 mr
->desc_size
* mr
->max_descs
,