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Merge back earlier power management tools updates for v5.4.
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mlx5 / mr.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33
34 #include <linux/kref.h>
35 #include <linux/random.h>
36 #include <linux/debugfs.h>
37 #include <linux/export.h>
38 #include <linux/delay.h>
39 #include <rdma/ib_umem.h>
40 #include <rdma/ib_umem_odp.h>
41 #include <rdma/ib_verbs.h>
42 #include "mlx5_ib.h"
43
44 enum {
45 MAX_PENDING_REG_MR = 8,
46 };
47
48 #define MLX5_UMR_ALIGN 2048
49
50 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
51 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
52 static int mr_cache_max_order(struct mlx5_ib_dev *dev);
53 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr);
54
55 static bool umr_can_use_indirect_mkey(struct mlx5_ib_dev *dev)
56 {
57 return !MLX5_CAP_GEN(dev->mdev, umr_indirect_mkey_disabled);
58 }
59
60 static int destroy_mkey(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
61 {
62 int err = mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
63
64 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
65 /* Wait until all page fault handlers using the mr complete. */
66 synchronize_srcu(&dev->mr_srcu);
67
68 return err;
69 }
70
71 static int order2idx(struct mlx5_ib_dev *dev, int order)
72 {
73 struct mlx5_mr_cache *cache = &dev->cache;
74
75 if (order < cache->ent[0].order)
76 return 0;
77 else
78 return order - cache->ent[0].order;
79 }
80
81 static bool use_umr_mtt_update(struct mlx5_ib_mr *mr, u64 start, u64 length)
82 {
83 return ((u64)1 << mr->order) * MLX5_ADAPTER_PAGE_SIZE >=
84 length + (start & (MLX5_ADAPTER_PAGE_SIZE - 1));
85 }
86
87 static void update_odp_mr(struct mlx5_ib_mr *mr)
88 {
89 if (is_odp_mr(mr)) {
90 /*
91 * This barrier prevents the compiler from moving the
92 * setting of umem->odp_data->private to point to our
93 * MR, before reg_umr finished, to ensure that the MR
94 * initialization have finished before starting to
95 * handle invalidations.
96 */
97 smp_wmb();
98 to_ib_umem_odp(mr->umem)->private = mr;
99 /*
100 * Make sure we will see the new
101 * umem->odp_data->private value in the invalidation
102 * routines, before we can get page faults on the
103 * MR. Page faults can happen once we put the MR in
104 * the tree, below this line. Without the barrier,
105 * there can be a fault handling and an invalidation
106 * before umem->odp_data->private == mr is visible to
107 * the invalidation handler.
108 */
109 smp_wmb();
110 }
111 }
112
113 static void reg_mr_callback(int status, struct mlx5_async_work *context)
114 {
115 struct mlx5_ib_mr *mr =
116 container_of(context, struct mlx5_ib_mr, cb_work);
117 struct mlx5_ib_dev *dev = mr->dev;
118 struct mlx5_mr_cache *cache = &dev->cache;
119 int c = order2idx(dev, mr->order);
120 struct mlx5_cache_ent *ent = &cache->ent[c];
121 u8 key;
122 unsigned long flags;
123 struct xarray *mkeys = &dev->mdev->priv.mkey_table;
124 int err;
125
126 spin_lock_irqsave(&ent->lock, flags);
127 ent->pending--;
128 spin_unlock_irqrestore(&ent->lock, flags);
129 if (status) {
130 mlx5_ib_warn(dev, "async reg mr failed. status %d\n", status);
131 kfree(mr);
132 dev->fill_delay = 1;
133 mod_timer(&dev->delay_timer, jiffies + HZ);
134 return;
135 }
136
137 mr->mmkey.type = MLX5_MKEY_MR;
138 spin_lock_irqsave(&dev->mdev->priv.mkey_lock, flags);
139 key = dev->mdev->priv.mkey_key++;
140 spin_unlock_irqrestore(&dev->mdev->priv.mkey_lock, flags);
141 mr->mmkey.key = mlx5_idx_to_mkey(MLX5_GET(create_mkey_out, mr->out, mkey_index)) | key;
142
143 cache->last_add = jiffies;
144
145 spin_lock_irqsave(&ent->lock, flags);
146 list_add_tail(&mr->list, &ent->head);
147 ent->cur++;
148 ent->size++;
149 spin_unlock_irqrestore(&ent->lock, flags);
150
151 xa_lock_irqsave(mkeys, flags);
152 err = xa_err(__xa_store(mkeys, mlx5_base_mkey(mr->mmkey.key),
153 &mr->mmkey, GFP_ATOMIC));
154 xa_unlock_irqrestore(mkeys, flags);
155 if (err)
156 pr_err("Error inserting to mkey tree. 0x%x\n", -err);
157
158 if (!completion_done(&ent->compl))
159 complete(&ent->compl);
160 }
161
162 static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
163 {
164 struct mlx5_mr_cache *cache = &dev->cache;
165 struct mlx5_cache_ent *ent = &cache->ent[c];
166 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
167 struct mlx5_ib_mr *mr;
168 void *mkc;
169 u32 *in;
170 int err = 0;
171 int i;
172
173 in = kzalloc(inlen, GFP_KERNEL);
174 if (!in)
175 return -ENOMEM;
176
177 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
178 for (i = 0; i < num; i++) {
179 if (ent->pending >= MAX_PENDING_REG_MR) {
180 err = -EAGAIN;
181 break;
182 }
183
184 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
185 if (!mr) {
186 err = -ENOMEM;
187 break;
188 }
189 mr->order = ent->order;
190 mr->allocated_from_cache = 1;
191 mr->dev = dev;
192
193 MLX5_SET(mkc, mkc, free, 1);
194 MLX5_SET(mkc, mkc, umr_en, 1);
195 MLX5_SET(mkc, mkc, access_mode_1_0, ent->access_mode & 0x3);
196 MLX5_SET(mkc, mkc, access_mode_4_2,
197 (ent->access_mode >> 2) & 0x7);
198
199 MLX5_SET(mkc, mkc, qpn, 0xffffff);
200 MLX5_SET(mkc, mkc, translations_octword_size, ent->xlt);
201 MLX5_SET(mkc, mkc, log_page_size, ent->page);
202
203 spin_lock_irq(&ent->lock);
204 ent->pending++;
205 spin_unlock_irq(&ent->lock);
206 err = mlx5_core_create_mkey_cb(dev->mdev, &mr->mmkey,
207 &dev->async_ctx, in, inlen,
208 mr->out, sizeof(mr->out),
209 reg_mr_callback, &mr->cb_work);
210 if (err) {
211 spin_lock_irq(&ent->lock);
212 ent->pending--;
213 spin_unlock_irq(&ent->lock);
214 mlx5_ib_warn(dev, "create mkey failed %d\n", err);
215 kfree(mr);
216 break;
217 }
218 }
219
220 kfree(in);
221 return err;
222 }
223
224 static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
225 {
226 struct mlx5_mr_cache *cache = &dev->cache;
227 struct mlx5_cache_ent *ent = &cache->ent[c];
228 struct mlx5_ib_mr *tmp_mr;
229 struct mlx5_ib_mr *mr;
230 LIST_HEAD(del_list);
231 int i;
232
233 for (i = 0; i < num; i++) {
234 spin_lock_irq(&ent->lock);
235 if (list_empty(&ent->head)) {
236 spin_unlock_irq(&ent->lock);
237 break;
238 }
239 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
240 list_move(&mr->list, &del_list);
241 ent->cur--;
242 ent->size--;
243 spin_unlock_irq(&ent->lock);
244 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
245 }
246
247 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
248 synchronize_srcu(&dev->mr_srcu);
249
250 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
251 list_del(&mr->list);
252 kfree(mr);
253 }
254 }
255
256 static ssize_t size_write(struct file *filp, const char __user *buf,
257 size_t count, loff_t *pos)
258 {
259 struct mlx5_cache_ent *ent = filp->private_data;
260 struct mlx5_ib_dev *dev = ent->dev;
261 char lbuf[20] = {0};
262 u32 var;
263 int err;
264 int c;
265
266 count = min(count, sizeof(lbuf) - 1);
267 if (copy_from_user(lbuf, buf, count))
268 return -EFAULT;
269
270 c = order2idx(dev, ent->order);
271
272 if (sscanf(lbuf, "%u", &var) != 1)
273 return -EINVAL;
274
275 if (var < ent->limit)
276 return -EINVAL;
277
278 if (var > ent->size) {
279 do {
280 err = add_keys(dev, c, var - ent->size);
281 if (err && err != -EAGAIN)
282 return err;
283
284 usleep_range(3000, 5000);
285 } while (err);
286 } else if (var < ent->size) {
287 remove_keys(dev, c, ent->size - var);
288 }
289
290 return count;
291 }
292
293 static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
294 loff_t *pos)
295 {
296 struct mlx5_cache_ent *ent = filp->private_data;
297 char lbuf[20];
298 int err;
299
300 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
301 if (err < 0)
302 return err;
303
304 return simple_read_from_buffer(buf, count, pos, lbuf, err);
305 }
306
307 static const struct file_operations size_fops = {
308 .owner = THIS_MODULE,
309 .open = simple_open,
310 .write = size_write,
311 .read = size_read,
312 };
313
314 static ssize_t limit_write(struct file *filp, const char __user *buf,
315 size_t count, loff_t *pos)
316 {
317 struct mlx5_cache_ent *ent = filp->private_data;
318 struct mlx5_ib_dev *dev = ent->dev;
319 char lbuf[20] = {0};
320 u32 var;
321 int err;
322 int c;
323
324 count = min(count, sizeof(lbuf) - 1);
325 if (copy_from_user(lbuf, buf, count))
326 return -EFAULT;
327
328 c = order2idx(dev, ent->order);
329
330 if (sscanf(lbuf, "%u", &var) != 1)
331 return -EINVAL;
332
333 if (var > ent->size)
334 return -EINVAL;
335
336 ent->limit = var;
337
338 if (ent->cur < ent->limit) {
339 err = add_keys(dev, c, 2 * ent->limit - ent->cur);
340 if (err)
341 return err;
342 }
343
344 return count;
345 }
346
347 static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
348 loff_t *pos)
349 {
350 struct mlx5_cache_ent *ent = filp->private_data;
351 char lbuf[20];
352 int err;
353
354 err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
355 if (err < 0)
356 return err;
357
358 return simple_read_from_buffer(buf, count, pos, lbuf, err);
359 }
360
361 static const struct file_operations limit_fops = {
362 .owner = THIS_MODULE,
363 .open = simple_open,
364 .write = limit_write,
365 .read = limit_read,
366 };
367
368 static int someone_adding(struct mlx5_mr_cache *cache)
369 {
370 int i;
371
372 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
373 if (cache->ent[i].cur < cache->ent[i].limit)
374 return 1;
375 }
376
377 return 0;
378 }
379
380 static void __cache_work_func(struct mlx5_cache_ent *ent)
381 {
382 struct mlx5_ib_dev *dev = ent->dev;
383 struct mlx5_mr_cache *cache = &dev->cache;
384 int i = order2idx(dev, ent->order);
385 int err;
386
387 if (cache->stopped)
388 return;
389
390 ent = &dev->cache.ent[i];
391 if (ent->cur < 2 * ent->limit && !dev->fill_delay) {
392 err = add_keys(dev, i, 1);
393 if (ent->cur < 2 * ent->limit) {
394 if (err == -EAGAIN) {
395 mlx5_ib_dbg(dev, "returned eagain, order %d\n",
396 i + 2);
397 queue_delayed_work(cache->wq, &ent->dwork,
398 msecs_to_jiffies(3));
399 } else if (err) {
400 mlx5_ib_warn(dev, "command failed order %d, err %d\n",
401 i + 2, err);
402 queue_delayed_work(cache->wq, &ent->dwork,
403 msecs_to_jiffies(1000));
404 } else {
405 queue_work(cache->wq, &ent->work);
406 }
407 }
408 } else if (ent->cur > 2 * ent->limit) {
409 /*
410 * The remove_keys() logic is performed as garbage collection
411 * task. Such task is intended to be run when no other active
412 * processes are running.
413 *
414 * The need_resched() will return TRUE if there are user tasks
415 * to be activated in near future.
416 *
417 * In such case, we don't execute remove_keys() and postpone
418 * the garbage collection work to try to run in next cycle,
419 * in order to free CPU resources to other tasks.
420 */
421 if (!need_resched() && !someone_adding(cache) &&
422 time_after(jiffies, cache->last_add + 300 * HZ)) {
423 remove_keys(dev, i, 1);
424 if (ent->cur > ent->limit)
425 queue_work(cache->wq, &ent->work);
426 } else {
427 queue_delayed_work(cache->wq, &ent->dwork, 300 * HZ);
428 }
429 }
430 }
431
432 static void delayed_cache_work_func(struct work_struct *work)
433 {
434 struct mlx5_cache_ent *ent;
435
436 ent = container_of(work, struct mlx5_cache_ent, dwork.work);
437 __cache_work_func(ent);
438 }
439
440 static void cache_work_func(struct work_struct *work)
441 {
442 struct mlx5_cache_ent *ent;
443
444 ent = container_of(work, struct mlx5_cache_ent, work);
445 __cache_work_func(ent);
446 }
447
448 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev, int entry)
449 {
450 struct mlx5_mr_cache *cache = &dev->cache;
451 struct mlx5_cache_ent *ent;
452 struct mlx5_ib_mr *mr;
453 int err;
454
455 if (entry < 0 || entry >= MAX_MR_CACHE_ENTRIES) {
456 mlx5_ib_err(dev, "cache entry %d is out of range\n", entry);
457 return NULL;
458 }
459
460 ent = &cache->ent[entry];
461 while (1) {
462 spin_lock_irq(&ent->lock);
463 if (list_empty(&ent->head)) {
464 spin_unlock_irq(&ent->lock);
465
466 err = add_keys(dev, entry, 1);
467 if (err && err != -EAGAIN)
468 return ERR_PTR(err);
469
470 wait_for_completion(&ent->compl);
471 } else {
472 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
473 list);
474 list_del(&mr->list);
475 ent->cur--;
476 spin_unlock_irq(&ent->lock);
477 if (ent->cur < ent->limit)
478 queue_work(cache->wq, &ent->work);
479 return mr;
480 }
481 }
482 }
483
484 static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
485 {
486 struct mlx5_mr_cache *cache = &dev->cache;
487 struct mlx5_ib_mr *mr = NULL;
488 struct mlx5_cache_ent *ent;
489 int last_umr_cache_entry;
490 int c;
491 int i;
492
493 c = order2idx(dev, order);
494 last_umr_cache_entry = order2idx(dev, mr_cache_max_order(dev));
495 if (c < 0 || c > last_umr_cache_entry) {
496 mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
497 return NULL;
498 }
499
500 for (i = c; i <= last_umr_cache_entry; i++) {
501 ent = &cache->ent[i];
502
503 mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
504
505 spin_lock_irq(&ent->lock);
506 if (!list_empty(&ent->head)) {
507 mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
508 list);
509 list_del(&mr->list);
510 ent->cur--;
511 spin_unlock_irq(&ent->lock);
512 if (ent->cur < ent->limit)
513 queue_work(cache->wq, &ent->work);
514 break;
515 }
516 spin_unlock_irq(&ent->lock);
517
518 queue_work(cache->wq, &ent->work);
519 }
520
521 if (!mr)
522 cache->ent[c].miss++;
523
524 return mr;
525 }
526
527 void mlx5_mr_cache_free(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
528 {
529 struct mlx5_mr_cache *cache = &dev->cache;
530 struct mlx5_cache_ent *ent;
531 int shrink = 0;
532 int c;
533
534 if (!mr->allocated_from_cache)
535 return;
536
537 c = order2idx(dev, mr->order);
538 WARN_ON(c < 0 || c >= MAX_MR_CACHE_ENTRIES);
539
540 if (unreg_umr(dev, mr)) {
541 mr->allocated_from_cache = false;
542 destroy_mkey(dev, mr);
543 ent = &cache->ent[c];
544 if (ent->cur < ent->limit)
545 queue_work(cache->wq, &ent->work);
546 return;
547 }
548
549 ent = &cache->ent[c];
550 spin_lock_irq(&ent->lock);
551 list_add_tail(&mr->list, &ent->head);
552 ent->cur++;
553 if (ent->cur > 2 * ent->limit)
554 shrink = 1;
555 spin_unlock_irq(&ent->lock);
556
557 if (shrink)
558 queue_work(cache->wq, &ent->work);
559 }
560
561 static void clean_keys(struct mlx5_ib_dev *dev, int c)
562 {
563 struct mlx5_mr_cache *cache = &dev->cache;
564 struct mlx5_cache_ent *ent = &cache->ent[c];
565 struct mlx5_ib_mr *tmp_mr;
566 struct mlx5_ib_mr *mr;
567 LIST_HEAD(del_list);
568
569 cancel_delayed_work(&ent->dwork);
570 while (1) {
571 spin_lock_irq(&ent->lock);
572 if (list_empty(&ent->head)) {
573 spin_unlock_irq(&ent->lock);
574 break;
575 }
576 mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
577 list_move(&mr->list, &del_list);
578 ent->cur--;
579 ent->size--;
580 spin_unlock_irq(&ent->lock);
581 mlx5_core_destroy_mkey(dev->mdev, &mr->mmkey);
582 }
583
584 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
585 synchronize_srcu(&dev->mr_srcu);
586 #endif
587
588 list_for_each_entry_safe(mr, tmp_mr, &del_list, list) {
589 list_del(&mr->list);
590 kfree(mr);
591 }
592 }
593
594 static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
595 {
596 if (!mlx5_debugfs_root || dev->is_rep)
597 return;
598
599 debugfs_remove_recursive(dev->cache.root);
600 dev->cache.root = NULL;
601 }
602
603 static void mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
604 {
605 struct mlx5_mr_cache *cache = &dev->cache;
606 struct mlx5_cache_ent *ent;
607 struct dentry *dir;
608 int i;
609
610 if (!mlx5_debugfs_root || dev->is_rep)
611 return;
612
613 cache->root = debugfs_create_dir("mr_cache", dev->mdev->priv.dbg_root);
614
615 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
616 ent = &cache->ent[i];
617 sprintf(ent->name, "%d", ent->order);
618 dir = debugfs_create_dir(ent->name, cache->root);
619 debugfs_create_file("size", 0600, dir, ent, &size_fops);
620 debugfs_create_file("limit", 0600, dir, ent, &limit_fops);
621 debugfs_create_u32("cur", 0400, dir, &ent->cur);
622 debugfs_create_u32("miss", 0600, dir, &ent->miss);
623 }
624 }
625
626 static void delay_time_func(struct timer_list *t)
627 {
628 struct mlx5_ib_dev *dev = from_timer(dev, t, delay_timer);
629
630 dev->fill_delay = 0;
631 }
632
633 int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
634 {
635 struct mlx5_mr_cache *cache = &dev->cache;
636 struct mlx5_cache_ent *ent;
637 int i;
638
639 mutex_init(&dev->slow_path_mutex);
640 cache->wq = alloc_ordered_workqueue("mkey_cache", WQ_MEM_RECLAIM);
641 if (!cache->wq) {
642 mlx5_ib_warn(dev, "failed to create work queue\n");
643 return -ENOMEM;
644 }
645
646 mlx5_cmd_init_async_ctx(dev->mdev, &dev->async_ctx);
647 timer_setup(&dev->delay_timer, delay_time_func, 0);
648 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
649 ent = &cache->ent[i];
650 INIT_LIST_HEAD(&ent->head);
651 spin_lock_init(&ent->lock);
652 ent->order = i + 2;
653 ent->dev = dev;
654 ent->limit = 0;
655
656 init_completion(&ent->compl);
657 INIT_WORK(&ent->work, cache_work_func);
658 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
659
660 if (i > MR_CACHE_LAST_STD_ENTRY) {
661 mlx5_odp_init_mr_cache_entry(ent);
662 continue;
663 }
664
665 if (ent->order > mr_cache_max_order(dev))
666 continue;
667
668 ent->page = PAGE_SHIFT;
669 ent->xlt = (1 << ent->order) * sizeof(struct mlx5_mtt) /
670 MLX5_IB_UMR_OCTOWORD;
671 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
672 if ((dev->mdev->profile->mask & MLX5_PROF_MASK_MR_CACHE) &&
673 !dev->is_rep &&
674 mlx5_core_is_pf(dev->mdev))
675 ent->limit = dev->mdev->profile->mr_cache[i].limit;
676 else
677 ent->limit = 0;
678 queue_work(cache->wq, &ent->work);
679 }
680
681 mlx5_mr_cache_debugfs_init(dev);
682
683 return 0;
684 }
685
686 int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
687 {
688 int i;
689
690 if (!dev->cache.wq)
691 return 0;
692
693 dev->cache.stopped = 1;
694 flush_workqueue(dev->cache.wq);
695
696 mlx5_mr_cache_debugfs_cleanup(dev);
697 mlx5_cmd_cleanup_async_ctx(&dev->async_ctx);
698
699 for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
700 clean_keys(dev, i);
701
702 destroy_workqueue(dev->cache.wq);
703 del_timer_sync(&dev->delay_timer);
704
705 return 0;
706 }
707
708 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
709 {
710 struct mlx5_ib_dev *dev = to_mdev(pd->device);
711 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
712 struct mlx5_core_dev *mdev = dev->mdev;
713 struct mlx5_ib_mr *mr;
714 void *mkc;
715 u32 *in;
716 int err;
717
718 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
719 if (!mr)
720 return ERR_PTR(-ENOMEM);
721
722 in = kzalloc(inlen, GFP_KERNEL);
723 if (!in) {
724 err = -ENOMEM;
725 goto err_free;
726 }
727
728 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
729
730 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_PA);
731 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
732 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
733 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
734 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
735 MLX5_SET(mkc, mkc, lr, 1);
736
737 MLX5_SET(mkc, mkc, length64, 1);
738 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
739 MLX5_SET(mkc, mkc, qpn, 0xffffff);
740 MLX5_SET64(mkc, mkc, start_addr, 0);
741
742 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
743 if (err)
744 goto err_in;
745
746 kfree(in);
747 mr->mmkey.type = MLX5_MKEY_MR;
748 mr->ibmr.lkey = mr->mmkey.key;
749 mr->ibmr.rkey = mr->mmkey.key;
750 mr->umem = NULL;
751
752 return &mr->ibmr;
753
754 err_in:
755 kfree(in);
756
757 err_free:
758 kfree(mr);
759
760 return ERR_PTR(err);
761 }
762
763 static int get_octo_len(u64 addr, u64 len, int page_shift)
764 {
765 u64 page_size = 1ULL << page_shift;
766 u64 offset;
767 int npages;
768
769 offset = addr & (page_size - 1);
770 npages = ALIGN(len + offset, page_size) >> page_shift;
771 return (npages + 1) / 2;
772 }
773
774 static int mr_cache_max_order(struct mlx5_ib_dev *dev)
775 {
776 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
777 return MR_CACHE_LAST_STD_ENTRY + 2;
778 return MLX5_MAX_UMR_SHIFT;
779 }
780
781 static int mr_umem_get(struct mlx5_ib_dev *dev, struct ib_udata *udata,
782 u64 start, u64 length, int access_flags,
783 struct ib_umem **umem, int *npages, int *page_shift,
784 int *ncont, int *order)
785 {
786 struct ib_umem *u;
787 int err;
788
789 *umem = NULL;
790
791 u = ib_umem_get(udata, start, length, access_flags, 0);
792 err = PTR_ERR_OR_ZERO(u);
793 if (err) {
794 mlx5_ib_dbg(dev, "umem get failed (%d)\n", err);
795 return err;
796 }
797
798 mlx5_ib_cont_pages(u, start, MLX5_MKEY_PAGE_SHIFT_MASK, npages,
799 page_shift, ncont, order);
800 if (!*npages) {
801 mlx5_ib_warn(dev, "avoid zero region\n");
802 ib_umem_release(u);
803 return -EINVAL;
804 }
805
806 *umem = u;
807
808 mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
809 *npages, *ncont, *order, *page_shift);
810
811 return 0;
812 }
813
814 static void mlx5_ib_umr_done(struct ib_cq *cq, struct ib_wc *wc)
815 {
816 struct mlx5_ib_umr_context *context =
817 container_of(wc->wr_cqe, struct mlx5_ib_umr_context, cqe);
818
819 context->status = wc->status;
820 complete(&context->done);
821 }
822
823 static inline void mlx5_ib_init_umr_context(struct mlx5_ib_umr_context *context)
824 {
825 context->cqe.done = mlx5_ib_umr_done;
826 context->status = -1;
827 init_completion(&context->done);
828 }
829
830 static int mlx5_ib_post_send_wait(struct mlx5_ib_dev *dev,
831 struct mlx5_umr_wr *umrwr)
832 {
833 struct umr_common *umrc = &dev->umrc;
834 const struct ib_send_wr *bad;
835 int err;
836 struct mlx5_ib_umr_context umr_context;
837
838 mlx5_ib_init_umr_context(&umr_context);
839 umrwr->wr.wr_cqe = &umr_context.cqe;
840
841 down(&umrc->sem);
842 err = ib_post_send(umrc->qp, &umrwr->wr, &bad);
843 if (err) {
844 mlx5_ib_warn(dev, "UMR post send failed, err %d\n", err);
845 } else {
846 wait_for_completion(&umr_context.done);
847 if (umr_context.status != IB_WC_SUCCESS) {
848 mlx5_ib_warn(dev, "reg umr failed (%u)\n",
849 umr_context.status);
850 err = -EFAULT;
851 }
852 }
853 up(&umrc->sem);
854 return err;
855 }
856
857 static struct mlx5_ib_mr *alloc_mr_from_cache(
858 struct ib_pd *pd, struct ib_umem *umem,
859 u64 virt_addr, u64 len, int npages,
860 int page_shift, int order, int access_flags)
861 {
862 struct mlx5_ib_dev *dev = to_mdev(pd->device);
863 struct mlx5_ib_mr *mr;
864 int err = 0;
865 int i;
866
867 for (i = 0; i < 1; i++) {
868 mr = alloc_cached_mr(dev, order);
869 if (mr)
870 break;
871
872 err = add_keys(dev, order2idx(dev, order), 1);
873 if (err && err != -EAGAIN) {
874 mlx5_ib_warn(dev, "add_keys failed, err %d\n", err);
875 break;
876 }
877 }
878
879 if (!mr)
880 return ERR_PTR(-EAGAIN);
881
882 mr->ibmr.pd = pd;
883 mr->umem = umem;
884 mr->access_flags = access_flags;
885 mr->desc_size = sizeof(struct mlx5_mtt);
886 mr->mmkey.iova = virt_addr;
887 mr->mmkey.size = len;
888 mr->mmkey.pd = to_mpd(pd)->pdn;
889
890 return mr;
891 }
892
893 static inline int populate_xlt(struct mlx5_ib_mr *mr, int idx, int npages,
894 void *xlt, int page_shift, size_t size,
895 int flags)
896 {
897 struct mlx5_ib_dev *dev = mr->dev;
898 struct ib_umem *umem = mr->umem;
899
900 if (flags & MLX5_IB_UPD_XLT_INDIRECT) {
901 if (!umr_can_use_indirect_mkey(dev))
902 return -EPERM;
903 mlx5_odp_populate_klm(xlt, idx, npages, mr, flags);
904 return npages;
905 }
906
907 npages = min_t(size_t, npages, ib_umem_num_pages(umem) - idx);
908
909 if (!(flags & MLX5_IB_UPD_XLT_ZAP)) {
910 __mlx5_ib_populate_pas(dev, umem, page_shift,
911 idx, npages, xlt,
912 MLX5_IB_MTT_PRESENT);
913 /* Clear padding after the pages
914 * brought from the umem.
915 */
916 memset(xlt + (npages * sizeof(struct mlx5_mtt)), 0,
917 size - npages * sizeof(struct mlx5_mtt));
918 }
919
920 return npages;
921 }
922
923 #define MLX5_MAX_UMR_CHUNK ((1 << (MLX5_MAX_UMR_SHIFT + 4)) - \
924 MLX5_UMR_MTT_ALIGNMENT)
925 #define MLX5_SPARE_UMR_CHUNK 0x10000
926
927 int mlx5_ib_update_xlt(struct mlx5_ib_mr *mr, u64 idx, int npages,
928 int page_shift, int flags)
929 {
930 struct mlx5_ib_dev *dev = mr->dev;
931 struct device *ddev = dev->ib_dev.dev.parent;
932 int size;
933 void *xlt;
934 dma_addr_t dma;
935 struct mlx5_umr_wr wr;
936 struct ib_sge sg;
937 int err = 0;
938 int desc_size = (flags & MLX5_IB_UPD_XLT_INDIRECT)
939 ? sizeof(struct mlx5_klm)
940 : sizeof(struct mlx5_mtt);
941 const int page_align = MLX5_UMR_MTT_ALIGNMENT / desc_size;
942 const int page_mask = page_align - 1;
943 size_t pages_mapped = 0;
944 size_t pages_to_map = 0;
945 size_t pages_iter = 0;
946 gfp_t gfp;
947 bool use_emergency_page = false;
948
949 if ((flags & MLX5_IB_UPD_XLT_INDIRECT) &&
950 !umr_can_use_indirect_mkey(dev))
951 return -EPERM;
952
953 /* UMR copies MTTs in units of MLX5_UMR_MTT_ALIGNMENT bytes,
954 * so we need to align the offset and length accordingly
955 */
956 if (idx & page_mask) {
957 npages += idx & page_mask;
958 idx &= ~page_mask;
959 }
960
961 gfp = flags & MLX5_IB_UPD_XLT_ATOMIC ? GFP_ATOMIC : GFP_KERNEL;
962 gfp |= __GFP_ZERO | __GFP_NOWARN;
963
964 pages_to_map = ALIGN(npages, page_align);
965 size = desc_size * pages_to_map;
966 size = min_t(int, size, MLX5_MAX_UMR_CHUNK);
967
968 xlt = (void *)__get_free_pages(gfp, get_order(size));
969 if (!xlt && size > MLX5_SPARE_UMR_CHUNK) {
970 mlx5_ib_dbg(dev, "Failed to allocate %d bytes of order %d. fallback to spare UMR allocation od %d bytes\n",
971 size, get_order(size), MLX5_SPARE_UMR_CHUNK);
972
973 size = MLX5_SPARE_UMR_CHUNK;
974 xlt = (void *)__get_free_pages(gfp, get_order(size));
975 }
976
977 if (!xlt) {
978 mlx5_ib_warn(dev, "Using XLT emergency buffer\n");
979 xlt = (void *)mlx5_ib_get_xlt_emergency_page();
980 size = PAGE_SIZE;
981 memset(xlt, 0, size);
982 use_emergency_page = true;
983 }
984 pages_iter = size / desc_size;
985 dma = dma_map_single(ddev, xlt, size, DMA_TO_DEVICE);
986 if (dma_mapping_error(ddev, dma)) {
987 mlx5_ib_err(dev, "unable to map DMA during XLT update.\n");
988 err = -ENOMEM;
989 goto free_xlt;
990 }
991
992 sg.addr = dma;
993 sg.lkey = dev->umrc.pd->local_dma_lkey;
994
995 memset(&wr, 0, sizeof(wr));
996 wr.wr.send_flags = MLX5_IB_SEND_UMR_UPDATE_XLT;
997 if (!(flags & MLX5_IB_UPD_XLT_ENABLE))
998 wr.wr.send_flags |= MLX5_IB_SEND_UMR_FAIL_IF_FREE;
999 wr.wr.sg_list = &sg;
1000 wr.wr.num_sge = 1;
1001 wr.wr.opcode = MLX5_IB_WR_UMR;
1002
1003 wr.pd = mr->ibmr.pd;
1004 wr.mkey = mr->mmkey.key;
1005 wr.length = mr->mmkey.size;
1006 wr.virt_addr = mr->mmkey.iova;
1007 wr.access_flags = mr->access_flags;
1008 wr.page_shift = page_shift;
1009
1010 for (pages_mapped = 0;
1011 pages_mapped < pages_to_map && !err;
1012 pages_mapped += pages_iter, idx += pages_iter) {
1013 npages = min_t(int, pages_iter, pages_to_map - pages_mapped);
1014 dma_sync_single_for_cpu(ddev, dma, size, DMA_TO_DEVICE);
1015 npages = populate_xlt(mr, idx, npages, xlt,
1016 page_shift, size, flags);
1017
1018 dma_sync_single_for_device(ddev, dma, size, DMA_TO_DEVICE);
1019
1020 sg.length = ALIGN(npages * desc_size,
1021 MLX5_UMR_MTT_ALIGNMENT);
1022
1023 if (pages_mapped + pages_iter >= pages_to_map) {
1024 if (flags & MLX5_IB_UPD_XLT_ENABLE)
1025 wr.wr.send_flags |=
1026 MLX5_IB_SEND_UMR_ENABLE_MR |
1027 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS |
1028 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1029 if (flags & MLX5_IB_UPD_XLT_PD ||
1030 flags & MLX5_IB_UPD_XLT_ACCESS)
1031 wr.wr.send_flags |=
1032 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1033 if (flags & MLX5_IB_UPD_XLT_ADDR)
1034 wr.wr.send_flags |=
1035 MLX5_IB_SEND_UMR_UPDATE_TRANSLATION;
1036 }
1037
1038 wr.offset = idx * desc_size;
1039 wr.xlt_size = sg.length;
1040
1041 err = mlx5_ib_post_send_wait(dev, &wr);
1042 }
1043 dma_unmap_single(ddev, dma, size, DMA_TO_DEVICE);
1044
1045 free_xlt:
1046 if (use_emergency_page)
1047 mlx5_ib_put_xlt_emergency_page();
1048 else
1049 free_pages((unsigned long)xlt, get_order(size));
1050
1051 return err;
1052 }
1053
1054 /*
1055 * If ibmr is NULL it will be allocated by reg_create.
1056 * Else, the given ibmr will be used.
1057 */
1058 static struct mlx5_ib_mr *reg_create(struct ib_mr *ibmr, struct ib_pd *pd,
1059 u64 virt_addr, u64 length,
1060 struct ib_umem *umem, int npages,
1061 int page_shift, int access_flags,
1062 bool populate)
1063 {
1064 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1065 struct mlx5_ib_mr *mr;
1066 __be64 *pas;
1067 void *mkc;
1068 int inlen;
1069 u32 *in;
1070 int err;
1071 bool pg_cap = !!(MLX5_CAP_GEN(dev->mdev, pg));
1072
1073 mr = ibmr ? to_mmr(ibmr) : kzalloc(sizeof(*mr), GFP_KERNEL);
1074 if (!mr)
1075 return ERR_PTR(-ENOMEM);
1076
1077 mr->ibmr.pd = pd;
1078 mr->access_flags = access_flags;
1079
1080 inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1081 if (populate)
1082 inlen += sizeof(*pas) * roundup(npages, 2);
1083 in = kvzalloc(inlen, GFP_KERNEL);
1084 if (!in) {
1085 err = -ENOMEM;
1086 goto err_1;
1087 }
1088 pas = (__be64 *)MLX5_ADDR_OF(create_mkey_in, in, klm_pas_mtt);
1089 if (populate && !(access_flags & IB_ACCESS_ON_DEMAND))
1090 mlx5_ib_populate_pas(dev, umem, page_shift, pas,
1091 pg_cap ? MLX5_IB_MTT_PRESENT : 0);
1092
1093 /* The pg_access bit allows setting the access flags
1094 * in the page list submitted with the command. */
1095 MLX5_SET(create_mkey_in, in, pg_access, !!(pg_cap));
1096
1097 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1098 MLX5_SET(mkc, mkc, free, !populate);
1099 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
1100 MLX5_SET(mkc, mkc, a, !!(access_flags & IB_ACCESS_REMOTE_ATOMIC));
1101 MLX5_SET(mkc, mkc, rw, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
1102 MLX5_SET(mkc, mkc, rr, !!(access_flags & IB_ACCESS_REMOTE_READ));
1103 MLX5_SET(mkc, mkc, lw, !!(access_flags & IB_ACCESS_LOCAL_WRITE));
1104 MLX5_SET(mkc, mkc, lr, 1);
1105 MLX5_SET(mkc, mkc, umr_en, 1);
1106
1107 MLX5_SET64(mkc, mkc, start_addr, virt_addr);
1108 MLX5_SET64(mkc, mkc, len, length);
1109 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1110 MLX5_SET(mkc, mkc, bsf_octword_size, 0);
1111 MLX5_SET(mkc, mkc, translations_octword_size,
1112 get_octo_len(virt_addr, length, page_shift));
1113 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1114 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1115 if (populate) {
1116 MLX5_SET(create_mkey_in, in, translations_octword_actual_size,
1117 get_octo_len(virt_addr, length, page_shift));
1118 }
1119
1120 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1121 if (err) {
1122 mlx5_ib_warn(dev, "create mkey failed\n");
1123 goto err_2;
1124 }
1125 mr->mmkey.type = MLX5_MKEY_MR;
1126 mr->desc_size = sizeof(struct mlx5_mtt);
1127 mr->dev = dev;
1128 kvfree(in);
1129
1130 mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmkey.key);
1131
1132 return mr;
1133
1134 err_2:
1135 kvfree(in);
1136
1137 err_1:
1138 if (!ibmr)
1139 kfree(mr);
1140
1141 return ERR_PTR(err);
1142 }
1143
1144 static void set_mr_fields(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
1145 int npages, u64 length, int access_flags)
1146 {
1147 mr->npages = npages;
1148 atomic_add(npages, &dev->mdev->priv.reg_pages);
1149 mr->ibmr.lkey = mr->mmkey.key;
1150 mr->ibmr.rkey = mr->mmkey.key;
1151 mr->ibmr.length = length;
1152 mr->access_flags = access_flags;
1153 }
1154
1155 static struct ib_mr *mlx5_ib_get_dm_mr(struct ib_pd *pd, u64 start_addr,
1156 u64 length, int acc, int mode)
1157 {
1158 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1159 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1160 struct mlx5_core_dev *mdev = dev->mdev;
1161 struct mlx5_ib_mr *mr;
1162 void *mkc;
1163 u32 *in;
1164 int err;
1165
1166 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1167 if (!mr)
1168 return ERR_PTR(-ENOMEM);
1169
1170 in = kzalloc(inlen, GFP_KERNEL);
1171 if (!in) {
1172 err = -ENOMEM;
1173 goto err_free;
1174 }
1175
1176 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1177
1178 MLX5_SET(mkc, mkc, access_mode_1_0, mode & 0x3);
1179 MLX5_SET(mkc, mkc, access_mode_4_2, (mode >> 2) & 0x7);
1180 MLX5_SET(mkc, mkc, a, !!(acc & IB_ACCESS_REMOTE_ATOMIC));
1181 MLX5_SET(mkc, mkc, rw, !!(acc & IB_ACCESS_REMOTE_WRITE));
1182 MLX5_SET(mkc, mkc, rr, !!(acc & IB_ACCESS_REMOTE_READ));
1183 MLX5_SET(mkc, mkc, lw, !!(acc & IB_ACCESS_LOCAL_WRITE));
1184 MLX5_SET(mkc, mkc, lr, 1);
1185
1186 MLX5_SET64(mkc, mkc, len, length);
1187 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1188 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1189 MLX5_SET64(mkc, mkc, start_addr, start_addr);
1190
1191 err = mlx5_core_create_mkey(mdev, &mr->mmkey, in, inlen);
1192 if (err)
1193 goto err_in;
1194
1195 kfree(in);
1196
1197 mr->umem = NULL;
1198 set_mr_fields(dev, mr, 0, length, acc);
1199
1200 return &mr->ibmr;
1201
1202 err_in:
1203 kfree(in);
1204
1205 err_free:
1206 kfree(mr);
1207
1208 return ERR_PTR(err);
1209 }
1210
1211 int mlx5_ib_advise_mr(struct ib_pd *pd,
1212 enum ib_uverbs_advise_mr_advice advice,
1213 u32 flags,
1214 struct ib_sge *sg_list,
1215 u32 num_sge,
1216 struct uverbs_attr_bundle *attrs)
1217 {
1218 if (advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH &&
1219 advice != IB_UVERBS_ADVISE_MR_ADVICE_PREFETCH_WRITE)
1220 return -EOPNOTSUPP;
1221
1222 return mlx5_ib_advise_mr_prefetch(pd, advice, flags,
1223 sg_list, num_sge);
1224 }
1225
1226 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1227 struct ib_dm_mr_attr *attr,
1228 struct uverbs_attr_bundle *attrs)
1229 {
1230 struct mlx5_ib_dm *mdm = to_mdm(dm);
1231 struct mlx5_core_dev *dev = to_mdev(dm->device)->mdev;
1232 u64 start_addr = mdm->dev_addr + attr->offset;
1233 int mode;
1234
1235 switch (mdm->type) {
1236 case MLX5_IB_UAPI_DM_TYPE_MEMIC:
1237 if (attr->access_flags & ~MLX5_IB_DM_MEMIC_ALLOWED_ACCESS)
1238 return ERR_PTR(-EINVAL);
1239
1240 mode = MLX5_MKC_ACCESS_MODE_MEMIC;
1241 start_addr -= pci_resource_start(dev->pdev, 0);
1242 break;
1243 case MLX5_IB_UAPI_DM_TYPE_STEERING_SW_ICM:
1244 case MLX5_IB_UAPI_DM_TYPE_HEADER_MODIFY_SW_ICM:
1245 if (attr->access_flags & ~MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS)
1246 return ERR_PTR(-EINVAL);
1247
1248 mode = MLX5_MKC_ACCESS_MODE_SW_ICM;
1249 break;
1250 default:
1251 return ERR_PTR(-EINVAL);
1252 }
1253
1254 return mlx5_ib_get_dm_mr(pd, start_addr, attr->length,
1255 attr->access_flags, mode);
1256 }
1257
1258 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1259 u64 virt_addr, int access_flags,
1260 struct ib_udata *udata)
1261 {
1262 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1263 struct mlx5_ib_mr *mr = NULL;
1264 bool use_umr;
1265 struct ib_umem *umem;
1266 int page_shift;
1267 int npages;
1268 int ncont;
1269 int order;
1270 int err;
1271
1272 if (!IS_ENABLED(CONFIG_INFINIBAND_USER_MEM))
1273 return ERR_PTR(-EOPNOTSUPP);
1274
1275 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1276 start, virt_addr, length, access_flags);
1277
1278 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && !start &&
1279 length == U64_MAX) {
1280 if (!(access_flags & IB_ACCESS_ON_DEMAND) ||
1281 !(dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1282 return ERR_PTR(-EINVAL);
1283
1284 mr = mlx5_ib_alloc_implicit_mr(to_mpd(pd), udata, access_flags);
1285 if (IS_ERR(mr))
1286 return ERR_CAST(mr);
1287 return &mr->ibmr;
1288 }
1289
1290 err = mr_umem_get(dev, udata, start, length, access_flags, &umem,
1291 &npages, &page_shift, &ncont, &order);
1292
1293 if (err < 0)
1294 return ERR_PTR(err);
1295
1296 use_umr = mlx5_ib_can_use_umr(dev, true);
1297
1298 if (order <= mr_cache_max_order(dev) && use_umr) {
1299 mr = alloc_mr_from_cache(pd, umem, virt_addr, length, ncont,
1300 page_shift, order, access_flags);
1301 if (PTR_ERR(mr) == -EAGAIN) {
1302 mlx5_ib_dbg(dev, "cache empty for order %d\n", order);
1303 mr = NULL;
1304 }
1305 } else if (!MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset)) {
1306 if (access_flags & IB_ACCESS_ON_DEMAND) {
1307 err = -EINVAL;
1308 pr_err("Got MR registration for ODP MR > 512MB, not supported for Connect-IB\n");
1309 goto error;
1310 }
1311 use_umr = false;
1312 }
1313
1314 if (!mr) {
1315 mutex_lock(&dev->slow_path_mutex);
1316 mr = reg_create(NULL, pd, virt_addr, length, umem, ncont,
1317 page_shift, access_flags, !use_umr);
1318 mutex_unlock(&dev->slow_path_mutex);
1319 }
1320
1321 if (IS_ERR(mr)) {
1322 err = PTR_ERR(mr);
1323 goto error;
1324 }
1325
1326 mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmkey.key);
1327
1328 mr->umem = umem;
1329 set_mr_fields(dev, mr, npages, length, access_flags);
1330
1331 update_odp_mr(mr);
1332
1333 if (use_umr) {
1334 int update_xlt_flags = MLX5_IB_UPD_XLT_ENABLE;
1335
1336 if (access_flags & IB_ACCESS_ON_DEMAND)
1337 update_xlt_flags |= MLX5_IB_UPD_XLT_ZAP;
1338
1339 err = mlx5_ib_update_xlt(mr, 0, ncont, page_shift,
1340 update_xlt_flags);
1341
1342 if (err) {
1343 dereg_mr(dev, mr);
1344 return ERR_PTR(err);
1345 }
1346 }
1347
1348 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING)) {
1349 mr->live = 1;
1350 atomic_set(&mr->num_pending_prefetch, 0);
1351 }
1352
1353 return &mr->ibmr;
1354 error:
1355 ib_umem_release(umem);
1356 return ERR_PTR(err);
1357 }
1358
1359 static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1360 {
1361 struct mlx5_core_dev *mdev = dev->mdev;
1362 struct mlx5_umr_wr umrwr = {};
1363
1364 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR)
1365 return 0;
1366
1367 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_DISABLE_MR |
1368 MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1369 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1370 umrwr.pd = dev->umrc.pd;
1371 umrwr.mkey = mr->mmkey.key;
1372 umrwr.ignore_free_state = 1;
1373
1374 return mlx5_ib_post_send_wait(dev, &umrwr);
1375 }
1376
1377 static int rereg_umr(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1378 int access_flags, int flags)
1379 {
1380 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1381 struct mlx5_umr_wr umrwr = {};
1382 int err;
1383
1384 umrwr.wr.send_flags = MLX5_IB_SEND_UMR_FAIL_IF_FREE;
1385
1386 umrwr.wr.opcode = MLX5_IB_WR_UMR;
1387 umrwr.mkey = mr->mmkey.key;
1388
1389 if (flags & IB_MR_REREG_PD || flags & IB_MR_REREG_ACCESS) {
1390 umrwr.pd = pd;
1391 umrwr.access_flags = access_flags;
1392 umrwr.wr.send_flags |= MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS;
1393 }
1394
1395 err = mlx5_ib_post_send_wait(dev, &umrwr);
1396
1397 return err;
1398 }
1399
1400 int mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1401 u64 length, u64 virt_addr, int new_access_flags,
1402 struct ib_pd *new_pd, struct ib_udata *udata)
1403 {
1404 struct mlx5_ib_dev *dev = to_mdev(ib_mr->device);
1405 struct mlx5_ib_mr *mr = to_mmr(ib_mr);
1406 struct ib_pd *pd = (flags & IB_MR_REREG_PD) ? new_pd : ib_mr->pd;
1407 int access_flags = flags & IB_MR_REREG_ACCESS ?
1408 new_access_flags :
1409 mr->access_flags;
1410 int page_shift = 0;
1411 int upd_flags = 0;
1412 int npages = 0;
1413 int ncont = 0;
1414 int order = 0;
1415 u64 addr, len;
1416 int err;
1417
1418 mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx, access_flags 0x%x\n",
1419 start, virt_addr, length, access_flags);
1420
1421 atomic_sub(mr->npages, &dev->mdev->priv.reg_pages);
1422
1423 if (!mr->umem)
1424 return -EINVAL;
1425
1426 if (flags & IB_MR_REREG_TRANS) {
1427 addr = virt_addr;
1428 len = length;
1429 } else {
1430 addr = mr->umem->address;
1431 len = mr->umem->length;
1432 }
1433
1434 if (flags != IB_MR_REREG_PD) {
1435 /*
1436 * Replace umem. This needs to be done whether or not UMR is
1437 * used.
1438 */
1439 flags |= IB_MR_REREG_TRANS;
1440 ib_umem_release(mr->umem);
1441 mr->umem = NULL;
1442 err = mr_umem_get(dev, udata, addr, len, access_flags,
1443 &mr->umem, &npages, &page_shift, &ncont,
1444 &order);
1445 if (err)
1446 goto err;
1447 }
1448
1449 if (!mlx5_ib_can_use_umr(dev, true) ||
1450 (flags & IB_MR_REREG_TRANS && !use_umr_mtt_update(mr, addr, len))) {
1451 /*
1452 * UMR can't be used - MKey needs to be replaced.
1453 */
1454 if (mr->allocated_from_cache)
1455 err = unreg_umr(dev, mr);
1456 else
1457 err = destroy_mkey(dev, mr);
1458 if (err)
1459 goto err;
1460
1461 mr = reg_create(ib_mr, pd, addr, len, mr->umem, ncont,
1462 page_shift, access_flags, true);
1463
1464 if (IS_ERR(mr)) {
1465 err = PTR_ERR(mr);
1466 mr = to_mmr(ib_mr);
1467 goto err;
1468 }
1469
1470 mr->allocated_from_cache = 0;
1471 if (IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING))
1472 mr->live = 1;
1473 } else {
1474 /*
1475 * Send a UMR WQE
1476 */
1477 mr->ibmr.pd = pd;
1478 mr->access_flags = access_flags;
1479 mr->mmkey.iova = addr;
1480 mr->mmkey.size = len;
1481 mr->mmkey.pd = to_mpd(pd)->pdn;
1482
1483 if (flags & IB_MR_REREG_TRANS) {
1484 upd_flags = MLX5_IB_UPD_XLT_ADDR;
1485 if (flags & IB_MR_REREG_PD)
1486 upd_flags |= MLX5_IB_UPD_XLT_PD;
1487 if (flags & IB_MR_REREG_ACCESS)
1488 upd_flags |= MLX5_IB_UPD_XLT_ACCESS;
1489 err = mlx5_ib_update_xlt(mr, 0, npages, page_shift,
1490 upd_flags);
1491 } else {
1492 err = rereg_umr(pd, mr, access_flags, flags);
1493 }
1494
1495 if (err)
1496 goto err;
1497 }
1498
1499 set_mr_fields(dev, mr, npages, len, access_flags);
1500
1501 update_odp_mr(mr);
1502 return 0;
1503
1504 err:
1505 ib_umem_release(mr->umem);
1506 mr->umem = NULL;
1507
1508 clean_mr(dev, mr);
1509 return err;
1510 }
1511
1512 static int
1513 mlx5_alloc_priv_descs(struct ib_device *device,
1514 struct mlx5_ib_mr *mr,
1515 int ndescs,
1516 int desc_size)
1517 {
1518 int size = ndescs * desc_size;
1519 int add_size;
1520 int ret;
1521
1522 add_size = max_t(int, MLX5_UMR_ALIGN - ARCH_KMALLOC_MINALIGN, 0);
1523
1524 mr->descs_alloc = kzalloc(size + add_size, GFP_KERNEL);
1525 if (!mr->descs_alloc)
1526 return -ENOMEM;
1527
1528 mr->descs = PTR_ALIGN(mr->descs_alloc, MLX5_UMR_ALIGN);
1529
1530 mr->desc_map = dma_map_single(device->dev.parent, mr->descs,
1531 size, DMA_TO_DEVICE);
1532 if (dma_mapping_error(device->dev.parent, mr->desc_map)) {
1533 ret = -ENOMEM;
1534 goto err;
1535 }
1536
1537 return 0;
1538 err:
1539 kfree(mr->descs_alloc);
1540
1541 return ret;
1542 }
1543
1544 static void
1545 mlx5_free_priv_descs(struct mlx5_ib_mr *mr)
1546 {
1547 if (mr->descs) {
1548 struct ib_device *device = mr->ibmr.device;
1549 int size = mr->max_descs * mr->desc_size;
1550
1551 dma_unmap_single(device->dev.parent, mr->desc_map,
1552 size, DMA_TO_DEVICE);
1553 kfree(mr->descs_alloc);
1554 mr->descs = NULL;
1555 }
1556 }
1557
1558 static void clean_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1559 {
1560 int allocated_from_cache = mr->allocated_from_cache;
1561
1562 if (mr->sig) {
1563 if (mlx5_core_destroy_psv(dev->mdev,
1564 mr->sig->psv_memory.psv_idx))
1565 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1566 mr->sig->psv_memory.psv_idx);
1567 if (mlx5_core_destroy_psv(dev->mdev,
1568 mr->sig->psv_wire.psv_idx))
1569 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1570 mr->sig->psv_wire.psv_idx);
1571 kfree(mr->sig);
1572 mr->sig = NULL;
1573 }
1574
1575 if (!allocated_from_cache) {
1576 destroy_mkey(dev, mr);
1577 mlx5_free_priv_descs(mr);
1578 }
1579 }
1580
1581 static void dereg_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
1582 {
1583 int npages = mr->npages;
1584 struct ib_umem *umem = mr->umem;
1585
1586 if (is_odp_mr(mr)) {
1587 struct ib_umem_odp *umem_odp = to_ib_umem_odp(umem);
1588
1589 /* Prevent new page faults and
1590 * prefetch requests from succeeding
1591 */
1592 mr->live = 0;
1593
1594 /* dequeue pending prefetch requests for the mr */
1595 if (atomic_read(&mr->num_pending_prefetch))
1596 flush_workqueue(system_unbound_wq);
1597 WARN_ON(atomic_read(&mr->num_pending_prefetch));
1598
1599 /* Wait for all running page-fault handlers to finish. */
1600 synchronize_srcu(&dev->mr_srcu);
1601 /* Destroy all page mappings */
1602 if (umem_odp->page_list)
1603 mlx5_ib_invalidate_range(umem_odp,
1604 ib_umem_start(umem_odp),
1605 ib_umem_end(umem_odp));
1606 else
1607 mlx5_ib_free_implicit_mr(mr);
1608 /*
1609 * We kill the umem before the MR for ODP,
1610 * so that there will not be any invalidations in
1611 * flight, looking at the *mr struct.
1612 */
1613 ib_umem_release(umem);
1614 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1615
1616 /* Avoid double-freeing the umem. */
1617 umem = NULL;
1618 }
1619
1620 clean_mr(dev, mr);
1621
1622 /*
1623 * We should unregister the DMA address from the HCA before
1624 * remove the DMA mapping.
1625 */
1626 mlx5_mr_cache_free(dev, mr);
1627 ib_umem_release(umem);
1628 if (umem)
1629 atomic_sub(npages, &dev->mdev->priv.reg_pages);
1630
1631 if (!mr->allocated_from_cache)
1632 kfree(mr);
1633 }
1634
1635 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata)
1636 {
1637 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1638
1639 if (ibmr->type == IB_MR_TYPE_INTEGRITY) {
1640 dereg_mr(to_mdev(mmr->mtt_mr->ibmr.device), mmr->mtt_mr);
1641 dereg_mr(to_mdev(mmr->klm_mr->ibmr.device), mmr->klm_mr);
1642 }
1643
1644 dereg_mr(to_mdev(ibmr->device), mmr);
1645
1646 return 0;
1647 }
1648
1649 static void mlx5_set_umr_free_mkey(struct ib_pd *pd, u32 *in, int ndescs,
1650 int access_mode, int page_shift)
1651 {
1652 void *mkc;
1653
1654 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1655
1656 MLX5_SET(mkc, mkc, free, 1);
1657 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1658 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1659 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1660 MLX5_SET(mkc, mkc, access_mode_1_0, access_mode & 0x3);
1661 MLX5_SET(mkc, mkc, access_mode_4_2, (access_mode >> 2) & 0x7);
1662 MLX5_SET(mkc, mkc, umr_en, 1);
1663 MLX5_SET(mkc, mkc, log_page_size, page_shift);
1664 }
1665
1666 static int _mlx5_alloc_mkey_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1667 int ndescs, int desc_size, int page_shift,
1668 int access_mode, u32 *in, int inlen)
1669 {
1670 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1671 int err;
1672
1673 mr->access_mode = access_mode;
1674 mr->desc_size = desc_size;
1675 mr->max_descs = ndescs;
1676
1677 err = mlx5_alloc_priv_descs(pd->device, mr, ndescs, desc_size);
1678 if (err)
1679 return err;
1680
1681 mlx5_set_umr_free_mkey(pd, in, ndescs, access_mode, page_shift);
1682
1683 err = mlx5_core_create_mkey(dev->mdev, &mr->mmkey, in, inlen);
1684 if (err)
1685 goto err_free_descs;
1686
1687 mr->mmkey.type = MLX5_MKEY_MR;
1688 mr->ibmr.lkey = mr->mmkey.key;
1689 mr->ibmr.rkey = mr->mmkey.key;
1690
1691 return 0;
1692
1693 err_free_descs:
1694 mlx5_free_priv_descs(mr);
1695 return err;
1696 }
1697
1698 static struct mlx5_ib_mr *mlx5_ib_alloc_pi_mr(struct ib_pd *pd,
1699 u32 max_num_sg, u32 max_num_meta_sg,
1700 int desc_size, int access_mode)
1701 {
1702 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1703 int ndescs = ALIGN(max_num_sg + max_num_meta_sg, 4);
1704 int page_shift = 0;
1705 struct mlx5_ib_mr *mr;
1706 u32 *in;
1707 int err;
1708
1709 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1710 if (!mr)
1711 return ERR_PTR(-ENOMEM);
1712
1713 mr->ibmr.pd = pd;
1714 mr->ibmr.device = pd->device;
1715
1716 in = kzalloc(inlen, GFP_KERNEL);
1717 if (!in) {
1718 err = -ENOMEM;
1719 goto err_free;
1720 }
1721
1722 if (access_mode == MLX5_MKC_ACCESS_MODE_MTT)
1723 page_shift = PAGE_SHIFT;
1724
1725 err = _mlx5_alloc_mkey_descs(pd, mr, ndescs, desc_size, page_shift,
1726 access_mode, in, inlen);
1727 if (err)
1728 goto err_free_in;
1729
1730 mr->umem = NULL;
1731 kfree(in);
1732
1733 return mr;
1734
1735 err_free_in:
1736 kfree(in);
1737 err_free:
1738 kfree(mr);
1739 return ERR_PTR(err);
1740 }
1741
1742 static int mlx5_alloc_mem_reg_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1743 int ndescs, u32 *in, int inlen)
1744 {
1745 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_mtt),
1746 PAGE_SHIFT, MLX5_MKC_ACCESS_MODE_MTT, in,
1747 inlen);
1748 }
1749
1750 static int mlx5_alloc_sg_gaps_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1751 int ndescs, u32 *in, int inlen)
1752 {
1753 return _mlx5_alloc_mkey_descs(pd, mr, ndescs, sizeof(struct mlx5_klm),
1754 0, MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
1755 }
1756
1757 static int mlx5_alloc_integrity_descs(struct ib_pd *pd, struct mlx5_ib_mr *mr,
1758 int max_num_sg, int max_num_meta_sg,
1759 u32 *in, int inlen)
1760 {
1761 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1762 u32 psv_index[2];
1763 void *mkc;
1764 int err;
1765
1766 mr->sig = kzalloc(sizeof(*mr->sig), GFP_KERNEL);
1767 if (!mr->sig)
1768 return -ENOMEM;
1769
1770 /* create mem & wire PSVs */
1771 err = mlx5_core_create_psv(dev->mdev, to_mpd(pd)->pdn, 2, psv_index);
1772 if (err)
1773 goto err_free_sig;
1774
1775 mr->sig->psv_memory.psv_idx = psv_index[0];
1776 mr->sig->psv_wire.psv_idx = psv_index[1];
1777
1778 mr->sig->sig_status_checked = true;
1779 mr->sig->sig_err_exists = false;
1780 /* Next UMR, Arm SIGERR */
1781 ++mr->sig->sigerr_count;
1782 mr->klm_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
1783 sizeof(struct mlx5_klm),
1784 MLX5_MKC_ACCESS_MODE_KLMS);
1785 if (IS_ERR(mr->klm_mr)) {
1786 err = PTR_ERR(mr->klm_mr);
1787 goto err_destroy_psv;
1788 }
1789 mr->mtt_mr = mlx5_ib_alloc_pi_mr(pd, max_num_sg, max_num_meta_sg,
1790 sizeof(struct mlx5_mtt),
1791 MLX5_MKC_ACCESS_MODE_MTT);
1792 if (IS_ERR(mr->mtt_mr)) {
1793 err = PTR_ERR(mr->mtt_mr);
1794 goto err_free_klm_mr;
1795 }
1796
1797 /* Set bsf descriptors for mkey */
1798 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1799 MLX5_SET(mkc, mkc, bsf_en, 1);
1800 MLX5_SET(mkc, mkc, bsf_octword_size, MLX5_MKEY_BSF_OCTO_SIZE);
1801
1802 err = _mlx5_alloc_mkey_descs(pd, mr, 4, sizeof(struct mlx5_klm), 0,
1803 MLX5_MKC_ACCESS_MODE_KLMS, in, inlen);
1804 if (err)
1805 goto err_free_mtt_mr;
1806
1807 return 0;
1808
1809 err_free_mtt_mr:
1810 dereg_mr(to_mdev(mr->mtt_mr->ibmr.device), mr->mtt_mr);
1811 mr->mtt_mr = NULL;
1812 err_free_klm_mr:
1813 dereg_mr(to_mdev(mr->klm_mr->ibmr.device), mr->klm_mr);
1814 mr->klm_mr = NULL;
1815 err_destroy_psv:
1816 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_memory.psv_idx))
1817 mlx5_ib_warn(dev, "failed to destroy mem psv %d\n",
1818 mr->sig->psv_memory.psv_idx);
1819 if (mlx5_core_destroy_psv(dev->mdev, mr->sig->psv_wire.psv_idx))
1820 mlx5_ib_warn(dev, "failed to destroy wire psv %d\n",
1821 mr->sig->psv_wire.psv_idx);
1822 err_free_sig:
1823 kfree(mr->sig);
1824
1825 return err;
1826 }
1827
1828 static struct ib_mr *__mlx5_ib_alloc_mr(struct ib_pd *pd,
1829 enum ib_mr_type mr_type, u32 max_num_sg,
1830 u32 max_num_meta_sg)
1831 {
1832 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1833 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1834 int ndescs = ALIGN(max_num_sg, 4);
1835 struct mlx5_ib_mr *mr;
1836 u32 *in;
1837 int err;
1838
1839 mr = kzalloc(sizeof(*mr), GFP_KERNEL);
1840 if (!mr)
1841 return ERR_PTR(-ENOMEM);
1842
1843 in = kzalloc(inlen, GFP_KERNEL);
1844 if (!in) {
1845 err = -ENOMEM;
1846 goto err_free;
1847 }
1848
1849 mr->ibmr.device = pd->device;
1850 mr->umem = NULL;
1851
1852 switch (mr_type) {
1853 case IB_MR_TYPE_MEM_REG:
1854 err = mlx5_alloc_mem_reg_descs(pd, mr, ndescs, in, inlen);
1855 break;
1856 case IB_MR_TYPE_SG_GAPS:
1857 err = mlx5_alloc_sg_gaps_descs(pd, mr, ndescs, in, inlen);
1858 break;
1859 case IB_MR_TYPE_INTEGRITY:
1860 err = mlx5_alloc_integrity_descs(pd, mr, max_num_sg,
1861 max_num_meta_sg, in, inlen);
1862 break;
1863 default:
1864 mlx5_ib_warn(dev, "Invalid mr type %d\n", mr_type);
1865 err = -EINVAL;
1866 }
1867
1868 if (err)
1869 goto err_free_in;
1870
1871 kfree(in);
1872
1873 return &mr->ibmr;
1874
1875 err_free_in:
1876 kfree(in);
1877 err_free:
1878 kfree(mr);
1879 return ERR_PTR(err);
1880 }
1881
1882 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1883 u32 max_num_sg, struct ib_udata *udata)
1884 {
1885 return __mlx5_ib_alloc_mr(pd, mr_type, max_num_sg, 0);
1886 }
1887
1888 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1889 u32 max_num_sg, u32 max_num_meta_sg)
1890 {
1891 return __mlx5_ib_alloc_mr(pd, IB_MR_TYPE_INTEGRITY, max_num_sg,
1892 max_num_meta_sg);
1893 }
1894
1895 struct ib_mw *mlx5_ib_alloc_mw(struct ib_pd *pd, enum ib_mw_type type,
1896 struct ib_udata *udata)
1897 {
1898 struct mlx5_ib_dev *dev = to_mdev(pd->device);
1899 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
1900 struct mlx5_ib_mw *mw = NULL;
1901 u32 *in = NULL;
1902 void *mkc;
1903 int ndescs;
1904 int err;
1905 struct mlx5_ib_alloc_mw req = {};
1906 struct {
1907 __u32 comp_mask;
1908 __u32 response_length;
1909 } resp = {};
1910
1911 err = ib_copy_from_udata(&req, udata, min(udata->inlen, sizeof(req)));
1912 if (err)
1913 return ERR_PTR(err);
1914
1915 if (req.comp_mask || req.reserved1 || req.reserved2)
1916 return ERR_PTR(-EOPNOTSUPP);
1917
1918 if (udata->inlen > sizeof(req) &&
1919 !ib_is_udata_cleared(udata, sizeof(req),
1920 udata->inlen - sizeof(req)))
1921 return ERR_PTR(-EOPNOTSUPP);
1922
1923 ndescs = req.num_klms ? roundup(req.num_klms, 4) : roundup(1, 4);
1924
1925 mw = kzalloc(sizeof(*mw), GFP_KERNEL);
1926 in = kzalloc(inlen, GFP_KERNEL);
1927 if (!mw || !in) {
1928 err = -ENOMEM;
1929 goto free;
1930 }
1931
1932 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
1933
1934 MLX5_SET(mkc, mkc, free, 1);
1935 MLX5_SET(mkc, mkc, translations_octword_size, ndescs);
1936 MLX5_SET(mkc, mkc, pd, to_mpd(pd)->pdn);
1937 MLX5_SET(mkc, mkc, umr_en, 1);
1938 MLX5_SET(mkc, mkc, lr, 1);
1939 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_KLMS);
1940 MLX5_SET(mkc, mkc, en_rinval, !!((type == IB_MW_TYPE_2)));
1941 MLX5_SET(mkc, mkc, qpn, 0xffffff);
1942
1943 err = mlx5_core_create_mkey(dev->mdev, &mw->mmkey, in, inlen);
1944 if (err)
1945 goto free;
1946
1947 mw->mmkey.type = MLX5_MKEY_MW;
1948 mw->ibmw.rkey = mw->mmkey.key;
1949 mw->ndescs = ndescs;
1950
1951 resp.response_length = min(offsetof(typeof(resp), response_length) +
1952 sizeof(resp.response_length), udata->outlen);
1953 if (resp.response_length) {
1954 err = ib_copy_to_udata(udata, &resp, resp.response_length);
1955 if (err) {
1956 mlx5_core_destroy_mkey(dev->mdev, &mw->mmkey);
1957 goto free;
1958 }
1959 }
1960
1961 kfree(in);
1962 return &mw->ibmw;
1963
1964 free:
1965 kfree(mw);
1966 kfree(in);
1967 return ERR_PTR(err);
1968 }
1969
1970 int mlx5_ib_dealloc_mw(struct ib_mw *mw)
1971 {
1972 struct mlx5_ib_mw *mmw = to_mmw(mw);
1973 int err;
1974
1975 err = mlx5_core_destroy_mkey((to_mdev(mw->device))->mdev,
1976 &mmw->mmkey);
1977 if (!err)
1978 kfree(mmw);
1979 return err;
1980 }
1981
1982 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1983 struct ib_mr_status *mr_status)
1984 {
1985 struct mlx5_ib_mr *mmr = to_mmr(ibmr);
1986 int ret = 0;
1987
1988 if (check_mask & ~IB_MR_CHECK_SIG_STATUS) {
1989 pr_err("Invalid status check mask\n");
1990 ret = -EINVAL;
1991 goto done;
1992 }
1993
1994 mr_status->fail_status = 0;
1995 if (check_mask & IB_MR_CHECK_SIG_STATUS) {
1996 if (!mmr->sig) {
1997 ret = -EINVAL;
1998 pr_err("signature status check requested on a non-signature enabled MR\n");
1999 goto done;
2000 }
2001
2002 mmr->sig->sig_status_checked = true;
2003 if (!mmr->sig->sig_err_exists)
2004 goto done;
2005
2006 if (ibmr->lkey == mmr->sig->err_item.key)
2007 memcpy(&mr_status->sig_err, &mmr->sig->err_item,
2008 sizeof(mr_status->sig_err));
2009 else {
2010 mr_status->sig_err.err_type = IB_SIG_BAD_GUARD;
2011 mr_status->sig_err.sig_err_offset = 0;
2012 mr_status->sig_err.key = mmr->sig->err_item.key;
2013 }
2014
2015 mmr->sig->sig_err_exists = false;
2016 mr_status->fail_status |= IB_MR_CHECK_SIG_STATUS;
2017 }
2018
2019 done:
2020 return ret;
2021 }
2022
2023 static int
2024 mlx5_ib_map_pa_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2025 int data_sg_nents, unsigned int *data_sg_offset,
2026 struct scatterlist *meta_sg, int meta_sg_nents,
2027 unsigned int *meta_sg_offset)
2028 {
2029 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2030 unsigned int sg_offset = 0;
2031 int n = 0;
2032
2033 mr->meta_length = 0;
2034 if (data_sg_nents == 1) {
2035 n++;
2036 mr->ndescs = 1;
2037 if (data_sg_offset)
2038 sg_offset = *data_sg_offset;
2039 mr->data_length = sg_dma_len(data_sg) - sg_offset;
2040 mr->data_iova = sg_dma_address(data_sg) + sg_offset;
2041 if (meta_sg_nents == 1) {
2042 n++;
2043 mr->meta_ndescs = 1;
2044 if (meta_sg_offset)
2045 sg_offset = *meta_sg_offset;
2046 else
2047 sg_offset = 0;
2048 mr->meta_length = sg_dma_len(meta_sg) - sg_offset;
2049 mr->pi_iova = sg_dma_address(meta_sg) + sg_offset;
2050 }
2051 ibmr->length = mr->data_length + mr->meta_length;
2052 }
2053
2054 return n;
2055 }
2056
2057 static int
2058 mlx5_ib_sg_to_klms(struct mlx5_ib_mr *mr,
2059 struct scatterlist *sgl,
2060 unsigned short sg_nents,
2061 unsigned int *sg_offset_p,
2062 struct scatterlist *meta_sgl,
2063 unsigned short meta_sg_nents,
2064 unsigned int *meta_sg_offset_p)
2065 {
2066 struct scatterlist *sg = sgl;
2067 struct mlx5_klm *klms = mr->descs;
2068 unsigned int sg_offset = sg_offset_p ? *sg_offset_p : 0;
2069 u32 lkey = mr->ibmr.pd->local_dma_lkey;
2070 int i, j = 0;
2071
2072 mr->ibmr.iova = sg_dma_address(sg) + sg_offset;
2073 mr->ibmr.length = 0;
2074
2075 for_each_sg(sgl, sg, sg_nents, i) {
2076 if (unlikely(i >= mr->max_descs))
2077 break;
2078 klms[i].va = cpu_to_be64(sg_dma_address(sg) + sg_offset);
2079 klms[i].bcount = cpu_to_be32(sg_dma_len(sg) - sg_offset);
2080 klms[i].key = cpu_to_be32(lkey);
2081 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2082
2083 sg_offset = 0;
2084 }
2085
2086 if (sg_offset_p)
2087 *sg_offset_p = sg_offset;
2088
2089 mr->ndescs = i;
2090 mr->data_length = mr->ibmr.length;
2091
2092 if (meta_sg_nents) {
2093 sg = meta_sgl;
2094 sg_offset = meta_sg_offset_p ? *meta_sg_offset_p : 0;
2095 for_each_sg(meta_sgl, sg, meta_sg_nents, j) {
2096 if (unlikely(i + j >= mr->max_descs))
2097 break;
2098 klms[i + j].va = cpu_to_be64(sg_dma_address(sg) +
2099 sg_offset);
2100 klms[i + j].bcount = cpu_to_be32(sg_dma_len(sg) -
2101 sg_offset);
2102 klms[i + j].key = cpu_to_be32(lkey);
2103 mr->ibmr.length += sg_dma_len(sg) - sg_offset;
2104
2105 sg_offset = 0;
2106 }
2107 if (meta_sg_offset_p)
2108 *meta_sg_offset_p = sg_offset;
2109
2110 mr->meta_ndescs = j;
2111 mr->meta_length = mr->ibmr.length - mr->data_length;
2112 }
2113
2114 return i + j;
2115 }
2116
2117 static int mlx5_set_page(struct ib_mr *ibmr, u64 addr)
2118 {
2119 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2120 __be64 *descs;
2121
2122 if (unlikely(mr->ndescs == mr->max_descs))
2123 return -ENOMEM;
2124
2125 descs = mr->descs;
2126 descs[mr->ndescs++] = cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2127
2128 return 0;
2129 }
2130
2131 static int mlx5_set_page_pi(struct ib_mr *ibmr, u64 addr)
2132 {
2133 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2134 __be64 *descs;
2135
2136 if (unlikely(mr->ndescs + mr->meta_ndescs == mr->max_descs))
2137 return -ENOMEM;
2138
2139 descs = mr->descs;
2140 descs[mr->ndescs + mr->meta_ndescs++] =
2141 cpu_to_be64(addr | MLX5_EN_RD | MLX5_EN_WR);
2142
2143 return 0;
2144 }
2145
2146 static int
2147 mlx5_ib_map_mtt_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2148 int data_sg_nents, unsigned int *data_sg_offset,
2149 struct scatterlist *meta_sg, int meta_sg_nents,
2150 unsigned int *meta_sg_offset)
2151 {
2152 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2153 struct mlx5_ib_mr *pi_mr = mr->mtt_mr;
2154 int n;
2155
2156 pi_mr->ndescs = 0;
2157 pi_mr->meta_ndescs = 0;
2158 pi_mr->meta_length = 0;
2159
2160 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2161 pi_mr->desc_size * pi_mr->max_descs,
2162 DMA_TO_DEVICE);
2163
2164 pi_mr->ibmr.page_size = ibmr->page_size;
2165 n = ib_sg_to_pages(&pi_mr->ibmr, data_sg, data_sg_nents, data_sg_offset,
2166 mlx5_set_page);
2167 if (n != data_sg_nents)
2168 return n;
2169
2170 pi_mr->data_iova = pi_mr->ibmr.iova;
2171 pi_mr->data_length = pi_mr->ibmr.length;
2172 pi_mr->ibmr.length = pi_mr->data_length;
2173 ibmr->length = pi_mr->data_length;
2174
2175 if (meta_sg_nents) {
2176 u64 page_mask = ~((u64)ibmr->page_size - 1);
2177 u64 iova = pi_mr->data_iova;
2178
2179 n += ib_sg_to_pages(&pi_mr->ibmr, meta_sg, meta_sg_nents,
2180 meta_sg_offset, mlx5_set_page_pi);
2181
2182 pi_mr->meta_length = pi_mr->ibmr.length;
2183 /*
2184 * PI address for the HW is the offset of the metadata address
2185 * relative to the first data page address.
2186 * It equals to first data page address + size of data pages +
2187 * metadata offset at the first metadata page
2188 */
2189 pi_mr->pi_iova = (iova & page_mask) +
2190 pi_mr->ndescs * ibmr->page_size +
2191 (pi_mr->ibmr.iova & ~page_mask);
2192 /*
2193 * In order to use one MTT MR for data and metadata, we register
2194 * also the gaps between the end of the data and the start of
2195 * the metadata (the sig MR will verify that the HW will access
2196 * to right addresses). This mapping is safe because we use
2197 * internal mkey for the registration.
2198 */
2199 pi_mr->ibmr.length = pi_mr->pi_iova + pi_mr->meta_length - iova;
2200 pi_mr->ibmr.iova = iova;
2201 ibmr->length += pi_mr->meta_length;
2202 }
2203
2204 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2205 pi_mr->desc_size * pi_mr->max_descs,
2206 DMA_TO_DEVICE);
2207
2208 return n;
2209 }
2210
2211 static int
2212 mlx5_ib_map_klm_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2213 int data_sg_nents, unsigned int *data_sg_offset,
2214 struct scatterlist *meta_sg, int meta_sg_nents,
2215 unsigned int *meta_sg_offset)
2216 {
2217 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2218 struct mlx5_ib_mr *pi_mr = mr->klm_mr;
2219 int n;
2220
2221 pi_mr->ndescs = 0;
2222 pi_mr->meta_ndescs = 0;
2223 pi_mr->meta_length = 0;
2224
2225 ib_dma_sync_single_for_cpu(ibmr->device, pi_mr->desc_map,
2226 pi_mr->desc_size * pi_mr->max_descs,
2227 DMA_TO_DEVICE);
2228
2229 n = mlx5_ib_sg_to_klms(pi_mr, data_sg, data_sg_nents, data_sg_offset,
2230 meta_sg, meta_sg_nents, meta_sg_offset);
2231
2232 ib_dma_sync_single_for_device(ibmr->device, pi_mr->desc_map,
2233 pi_mr->desc_size * pi_mr->max_descs,
2234 DMA_TO_DEVICE);
2235
2236 /* This is zero-based memory region */
2237 pi_mr->data_iova = 0;
2238 pi_mr->ibmr.iova = 0;
2239 pi_mr->pi_iova = pi_mr->data_length;
2240 ibmr->length = pi_mr->ibmr.length;
2241
2242 return n;
2243 }
2244
2245 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
2246 int data_sg_nents, unsigned int *data_sg_offset,
2247 struct scatterlist *meta_sg, int meta_sg_nents,
2248 unsigned int *meta_sg_offset)
2249 {
2250 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2251 struct mlx5_ib_mr *pi_mr = NULL;
2252 int n;
2253
2254 WARN_ON(ibmr->type != IB_MR_TYPE_INTEGRITY);
2255
2256 mr->ndescs = 0;
2257 mr->data_length = 0;
2258 mr->data_iova = 0;
2259 mr->meta_ndescs = 0;
2260 mr->pi_iova = 0;
2261 /*
2262 * As a performance optimization, if possible, there is no need to
2263 * perform UMR operation to register the data/metadata buffers.
2264 * First try to map the sg lists to PA descriptors with local_dma_lkey.
2265 * Fallback to UMR only in case of a failure.
2266 */
2267 n = mlx5_ib_map_pa_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2268 data_sg_offset, meta_sg, meta_sg_nents,
2269 meta_sg_offset);
2270 if (n == data_sg_nents + meta_sg_nents)
2271 goto out;
2272 /*
2273 * As a performance optimization, if possible, there is no need to map
2274 * the sg lists to KLM descriptors. First try to map the sg lists to MTT
2275 * descriptors and fallback to KLM only in case of a failure.
2276 * It's more efficient for the HW to work with MTT descriptors
2277 * (especially in high load).
2278 * Use KLM (indirect access) only if it's mandatory.
2279 */
2280 pi_mr = mr->mtt_mr;
2281 n = mlx5_ib_map_mtt_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2282 data_sg_offset, meta_sg, meta_sg_nents,
2283 meta_sg_offset);
2284 if (n == data_sg_nents + meta_sg_nents)
2285 goto out;
2286
2287 pi_mr = mr->klm_mr;
2288 n = mlx5_ib_map_klm_mr_sg_pi(ibmr, data_sg, data_sg_nents,
2289 data_sg_offset, meta_sg, meta_sg_nents,
2290 meta_sg_offset);
2291 if (unlikely(n != data_sg_nents + meta_sg_nents))
2292 return -ENOMEM;
2293
2294 out:
2295 /* This is zero-based memory region */
2296 ibmr->iova = 0;
2297 mr->pi_mr = pi_mr;
2298 if (pi_mr)
2299 ibmr->sig_attrs->meta_length = pi_mr->meta_length;
2300 else
2301 ibmr->sig_attrs->meta_length = mr->meta_length;
2302
2303 return 0;
2304 }
2305
2306 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
2307 unsigned int *sg_offset)
2308 {
2309 struct mlx5_ib_mr *mr = to_mmr(ibmr);
2310 int n;
2311
2312 mr->ndescs = 0;
2313
2314 ib_dma_sync_single_for_cpu(ibmr->device, mr->desc_map,
2315 mr->desc_size * mr->max_descs,
2316 DMA_TO_DEVICE);
2317
2318 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
2319 n = mlx5_ib_sg_to_klms(mr, sg, sg_nents, sg_offset, NULL, 0,
2320 NULL);
2321 else
2322 n = ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset,
2323 mlx5_set_page);
2324
2325 ib_dma_sync_single_for_device(ibmr->device, mr->desc_map,
2326 mr->desc_size * mr->max_descs,
2327 DMA_TO_DEVICE);
2328
2329 return n;
2330 }
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