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[mirror_ubuntu-jammy-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 };
57
58 static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75 struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77 };
78
79 enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
82 };
83
84 struct mlx5_modify_raw_qp_param {
85 u16 operation;
86
87 u32 set_mask; /* raw_qp_set_mask_map */
88 u32 rate_limit;
89 u8 rq_q_ctr_id;
90 };
91
92 static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
96 static int is_qp0(enum ib_qp_type qp_type)
97 {
98 return qp_type == IB_QPT_SMI;
99 }
100
101 static int is_sqp(enum ib_qp_type qp_type)
102 {
103 return is_qp0(qp_type) || is_qp1(qp_type);
104 }
105
106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107 {
108 return mlx5_buf_offset(&qp->buf, offset);
109 }
110
111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112 {
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114 }
115
116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117 {
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119 }
120
121 /**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
141 {
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
147 struct ib_umem *umem = base->ubuffer.umem;
148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191 }
192
193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194 {
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238 }
239
240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242 {
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
260 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
261 qp->rq.max_post = qp->rq.wqe_cnt;
262 } else {
263 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
264 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
265 wqe_size = roundup_pow_of_two(wqe_size);
266 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
267 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
268 qp->rq.wqe_cnt = wq_size / wqe_size;
269 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
270 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
271 wqe_size,
272 MLX5_CAP_GEN(dev->mdev,
273 max_wqe_sz_rq));
274 return -EINVAL;
275 }
276 qp->rq.wqe_shift = ilog2(wqe_size);
277 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
278 qp->rq.max_post = qp->rq.wqe_cnt;
279 }
280 }
281
282 return 0;
283 }
284
285 static int sq_overhead(struct ib_qp_init_attr *attr)
286 {
287 int size = 0;
288
289 switch (attr->qp_type) {
290 case IB_QPT_XRC_INI:
291 size += sizeof(struct mlx5_wqe_xrc_seg);
292 /* fall through */
293 case IB_QPT_RC:
294 size += sizeof(struct mlx5_wqe_ctrl_seg) +
295 max(sizeof(struct mlx5_wqe_atomic_seg) +
296 sizeof(struct mlx5_wqe_raddr_seg),
297 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
298 sizeof(struct mlx5_mkey_seg));
299 break;
300
301 case IB_QPT_XRC_TGT:
302 return 0;
303
304 case IB_QPT_UC:
305 size += sizeof(struct mlx5_wqe_ctrl_seg) +
306 max(sizeof(struct mlx5_wqe_raddr_seg),
307 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
308 sizeof(struct mlx5_mkey_seg));
309 break;
310
311 case IB_QPT_UD:
312 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
313 size += sizeof(struct mlx5_wqe_eth_pad) +
314 sizeof(struct mlx5_wqe_eth_seg);
315 /* fall through */
316 case IB_QPT_SMI:
317 case MLX5_IB_QPT_HW_GSI:
318 size += sizeof(struct mlx5_wqe_ctrl_seg) +
319 sizeof(struct mlx5_wqe_datagram_seg);
320 break;
321
322 case MLX5_IB_QPT_REG_UMR:
323 size += sizeof(struct mlx5_wqe_ctrl_seg) +
324 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
325 sizeof(struct mlx5_mkey_seg);
326 break;
327
328 default:
329 return -EINVAL;
330 }
331
332 return size;
333 }
334
335 static int calc_send_wqe(struct ib_qp_init_attr *attr)
336 {
337 int inl_size = 0;
338 int size;
339
340 size = sq_overhead(attr);
341 if (size < 0)
342 return size;
343
344 if (attr->cap.max_inline_data) {
345 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
346 attr->cap.max_inline_data;
347 }
348
349 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
350 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
351 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
352 return MLX5_SIG_WQE_SIZE;
353 else
354 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
355 }
356
357 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
358 {
359 int max_sge;
360
361 if (attr->qp_type == IB_QPT_RC)
362 max_sge = (min_t(int, wqe_size, 512) -
363 sizeof(struct mlx5_wqe_ctrl_seg) -
364 sizeof(struct mlx5_wqe_raddr_seg)) /
365 sizeof(struct mlx5_wqe_data_seg);
366 else if (attr->qp_type == IB_QPT_XRC_INI)
367 max_sge = (min_t(int, wqe_size, 512) -
368 sizeof(struct mlx5_wqe_ctrl_seg) -
369 sizeof(struct mlx5_wqe_xrc_seg) -
370 sizeof(struct mlx5_wqe_raddr_seg)) /
371 sizeof(struct mlx5_wqe_data_seg);
372 else
373 max_sge = (wqe_size - sq_overhead(attr)) /
374 sizeof(struct mlx5_wqe_data_seg);
375
376 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
377 sizeof(struct mlx5_wqe_data_seg));
378 }
379
380 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
381 struct mlx5_ib_qp *qp)
382 {
383 int wqe_size;
384 int wq_size;
385
386 if (!attr->cap.max_send_wr)
387 return 0;
388
389 wqe_size = calc_send_wqe(attr);
390 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
391 if (wqe_size < 0)
392 return wqe_size;
393
394 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
395 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
396 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
397 return -EINVAL;
398 }
399
400 qp->max_inline_data = wqe_size - sq_overhead(attr) -
401 sizeof(struct mlx5_wqe_inline_seg);
402 attr->cap.max_inline_data = qp->max_inline_data;
403
404 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
405 qp->signature_en = true;
406
407 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
408 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
409 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
410 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
411 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
414 return -ENOMEM;
415 }
416 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
417 qp->sq.max_gs = get_send_sge(attr, wqe_size);
418 if (qp->sq.max_gs < attr->cap.max_send_sge)
419 return -ENOMEM;
420
421 attr->cap.max_send_sge = qp->sq.max_gs;
422 qp->sq.max_post = wq_size / wqe_size;
423 attr->cap.max_send_wr = qp->sq.max_post;
424
425 return wq_size;
426 }
427
428 static int set_user_buf_size(struct mlx5_ib_dev *dev,
429 struct mlx5_ib_qp *qp,
430 struct mlx5_ib_create_qp *ucmd,
431 struct mlx5_ib_qp_base *base,
432 struct ib_qp_init_attr *attr)
433 {
434 int desc_sz = 1 << qp->sq.wqe_shift;
435
436 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
437 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
438 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
439 return -EINVAL;
440 }
441
442 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
443 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
444 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
445 return -EINVAL;
446 }
447
448 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
449
450 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
451 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
452 qp->sq.wqe_cnt,
453 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
454 return -EINVAL;
455 }
456
457 if (attr->qp_type == IB_QPT_RAW_PACKET ||
458 qp->flags & MLX5_IB_QP_UNDERLAY) {
459 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
460 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
461 } else {
462 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
463 (qp->sq.wqe_cnt << 6);
464 }
465
466 return 0;
467 }
468
469 static int qp_has_rq(struct ib_qp_init_attr *attr)
470 {
471 if (attr->qp_type == IB_QPT_XRC_INI ||
472 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
473 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
474 !attr->cap.max_recv_wr)
475 return 0;
476
477 return 1;
478 }
479
480 static int first_med_bfreg(void)
481 {
482 return 1;
483 }
484
485 enum {
486 /* this is the first blue flame register in the array of bfregs assigned
487 * to a processes. Since we do not use it for blue flame but rather
488 * regular 64 bit doorbells, we do not need a lock for maintaiing
489 * "odd/even" order
490 */
491 NUM_NON_BLUE_FLAME_BFREGS = 1,
492 };
493
494 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
495 {
496 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
497 }
498
499 static int num_med_bfreg(struct mlx5_ib_dev *dev,
500 struct mlx5_bfreg_info *bfregi)
501 {
502 int n;
503
504 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
505 NUM_NON_BLUE_FLAME_BFREGS;
506
507 return n >= 0 ? n : 0;
508 }
509
510 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
511 struct mlx5_bfreg_info *bfregi)
512 {
513 int med;
514
515 med = num_med_bfreg(dev, bfregi);
516 return ++med;
517 }
518
519 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
520 struct mlx5_bfreg_info *bfregi)
521 {
522 int i;
523
524 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
525 if (!bfregi->count[i]) {
526 bfregi->count[i]++;
527 return i;
528 }
529 }
530
531 return -ENOMEM;
532 }
533
534 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
535 struct mlx5_bfreg_info *bfregi)
536 {
537 int minidx = first_med_bfreg();
538 int i;
539
540 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
541 if (bfregi->count[i] < bfregi->count[minidx])
542 minidx = i;
543 if (!bfregi->count[minidx])
544 break;
545 }
546
547 bfregi->count[minidx]++;
548 return minidx;
549 }
550
551 static int alloc_bfreg(struct mlx5_ib_dev *dev,
552 struct mlx5_bfreg_info *bfregi,
553 enum mlx5_ib_latency_class lat)
554 {
555 int bfregn = -EINVAL;
556
557 mutex_lock(&bfregi->lock);
558 switch (lat) {
559 case MLX5_IB_LATENCY_CLASS_LOW:
560 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
561 bfregn = 0;
562 bfregi->count[bfregn]++;
563 break;
564
565 case MLX5_IB_LATENCY_CLASS_MEDIUM:
566 if (bfregi->ver < 2)
567 bfregn = -ENOMEM;
568 else
569 bfregn = alloc_med_class_bfreg(dev, bfregi);
570 break;
571
572 case MLX5_IB_LATENCY_CLASS_HIGH:
573 if (bfregi->ver < 2)
574 bfregn = -ENOMEM;
575 else
576 bfregn = alloc_high_class_bfreg(dev, bfregi);
577 break;
578 }
579 mutex_unlock(&bfregi->lock);
580
581 return bfregn;
582 }
583
584 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
585 {
586 mutex_lock(&bfregi->lock);
587 bfregi->count[bfregn]--;
588 mutex_unlock(&bfregi->lock);
589 }
590
591 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
592 {
593 switch (state) {
594 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
595 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
596 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
597 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
598 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
599 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
600 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
601 default: return -1;
602 }
603 }
604
605 static int to_mlx5_st(enum ib_qp_type type)
606 {
607 switch (type) {
608 case IB_QPT_RC: return MLX5_QP_ST_RC;
609 case IB_QPT_UC: return MLX5_QP_ST_UC;
610 case IB_QPT_UD: return MLX5_QP_ST_UD;
611 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
612 case IB_QPT_XRC_INI:
613 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
614 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
615 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
616 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
617 case IB_QPT_RAW_PACKET:
618 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
619 case IB_QPT_MAX:
620 default: return -EINVAL;
621 }
622 }
623
624 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
625 struct mlx5_ib_cq *recv_cq);
626 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
627 struct mlx5_ib_cq *recv_cq);
628
629 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
630 struct mlx5_bfreg_info *bfregi, int bfregn)
631 {
632 int bfregs_per_sys_page;
633 int index_of_sys_page;
634 int offset;
635
636 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
637 MLX5_NON_FP_BFREGS_PER_UAR;
638 index_of_sys_page = bfregn / bfregs_per_sys_page;
639
640 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
641
642 return bfregi->sys_pages[index_of_sys_page] + offset;
643 }
644
645 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
646 struct ib_pd *pd,
647 unsigned long addr, size_t size,
648 struct ib_umem **umem,
649 int *npages, int *page_shift, int *ncont,
650 u32 *offset)
651 {
652 int err;
653
654 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
655 if (IS_ERR(*umem)) {
656 mlx5_ib_dbg(dev, "umem_get failed\n");
657 return PTR_ERR(*umem);
658 }
659
660 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
661
662 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
663 if (err) {
664 mlx5_ib_warn(dev, "bad offset\n");
665 goto err_umem;
666 }
667
668 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
669 addr, size, *npages, *page_shift, *ncont, *offset);
670
671 return 0;
672
673 err_umem:
674 ib_umem_release(*umem);
675 *umem = NULL;
676
677 return err;
678 }
679
680 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
681 struct mlx5_ib_rwq *rwq)
682 {
683 struct mlx5_ib_ucontext *context;
684
685 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
686 atomic_dec(&dev->delay_drop.rqs_cnt);
687
688 context = to_mucontext(pd->uobject->context);
689 mlx5_ib_db_unmap_user(context, &rwq->db);
690 if (rwq->umem)
691 ib_umem_release(rwq->umem);
692 }
693
694 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
695 struct mlx5_ib_rwq *rwq,
696 struct mlx5_ib_create_wq *ucmd)
697 {
698 struct mlx5_ib_ucontext *context;
699 int page_shift = 0;
700 int npages;
701 u32 offset = 0;
702 int ncont = 0;
703 int err;
704
705 if (!ucmd->buf_addr)
706 return -EINVAL;
707
708 context = to_mucontext(pd->uobject->context);
709 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
710 rwq->buf_size, 0, 0);
711 if (IS_ERR(rwq->umem)) {
712 mlx5_ib_dbg(dev, "umem_get failed\n");
713 err = PTR_ERR(rwq->umem);
714 return err;
715 }
716
717 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
718 &ncont, NULL);
719 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
720 &rwq->rq_page_offset);
721 if (err) {
722 mlx5_ib_warn(dev, "bad offset\n");
723 goto err_umem;
724 }
725
726 rwq->rq_num_pas = ncont;
727 rwq->page_shift = page_shift;
728 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
729 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
730
731 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
732 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
733 npages, page_shift, ncont, offset);
734
735 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
736 if (err) {
737 mlx5_ib_dbg(dev, "map failed\n");
738 goto err_umem;
739 }
740
741 rwq->create_type = MLX5_WQ_USER;
742 return 0;
743
744 err_umem:
745 ib_umem_release(rwq->umem);
746 return err;
747 }
748
749 static int adjust_bfregn(struct mlx5_ib_dev *dev,
750 struct mlx5_bfreg_info *bfregi, int bfregn)
751 {
752 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
753 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
754 }
755
756 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
757 struct mlx5_ib_qp *qp, struct ib_udata *udata,
758 struct ib_qp_init_attr *attr,
759 u32 **in,
760 struct mlx5_ib_create_qp_resp *resp, int *inlen,
761 struct mlx5_ib_qp_base *base)
762 {
763 struct mlx5_ib_ucontext *context;
764 struct mlx5_ib_create_qp ucmd;
765 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
766 int page_shift = 0;
767 int uar_index;
768 int npages;
769 u32 offset = 0;
770 int bfregn;
771 int ncont = 0;
772 __be64 *pas;
773 void *qpc;
774 int err;
775
776 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
777 if (err) {
778 mlx5_ib_dbg(dev, "copy failed\n");
779 return err;
780 }
781
782 context = to_mucontext(pd->uobject->context);
783 /*
784 * TBD: should come from the verbs when we have the API
785 */
786 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
787 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
788 bfregn = MLX5_CROSS_CHANNEL_BFREG;
789 else {
790 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
791 if (bfregn < 0) {
792 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
793 mlx5_ib_dbg(dev, "reverting to medium latency\n");
794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
795 if (bfregn < 0) {
796 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
797 mlx5_ib_dbg(dev, "reverting to high latency\n");
798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
799 if (bfregn < 0) {
800 mlx5_ib_warn(dev, "bfreg allocation failed\n");
801 return bfregn;
802 }
803 }
804 }
805 }
806
807 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
808 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
809
810 qp->rq.offset = 0;
811 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
812 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
813
814 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
815 if (err)
816 goto err_bfreg;
817
818 if (ucmd.buf_addr && ubuffer->buf_size) {
819 ubuffer->buf_addr = ucmd.buf_addr;
820 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
821 ubuffer->buf_size,
822 &ubuffer->umem, &npages, &page_shift,
823 &ncont, &offset);
824 if (err)
825 goto err_bfreg;
826 } else {
827 ubuffer->umem = NULL;
828 }
829
830 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
831 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
832 *in = kvzalloc(*inlen, GFP_KERNEL);
833 if (!*in) {
834 err = -ENOMEM;
835 goto err_umem;
836 }
837
838 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
839 if (ubuffer->umem)
840 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
841
842 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
843
844 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
845 MLX5_SET(qpc, qpc, page_offset, offset);
846
847 MLX5_SET(qpc, qpc, uar_page, uar_index);
848 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
849 qp->bfregn = bfregn;
850
851 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
852 if (err) {
853 mlx5_ib_dbg(dev, "map failed\n");
854 goto err_free;
855 }
856
857 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
858 if (err) {
859 mlx5_ib_dbg(dev, "copy failed\n");
860 goto err_unmap;
861 }
862 qp->create_type = MLX5_QP_USER;
863
864 return 0;
865
866 err_unmap:
867 mlx5_ib_db_unmap_user(context, &qp->db);
868
869 err_free:
870 kvfree(*in);
871
872 err_umem:
873 if (ubuffer->umem)
874 ib_umem_release(ubuffer->umem);
875
876 err_bfreg:
877 free_bfreg(dev, &context->bfregi, bfregn);
878 return err;
879 }
880
881 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
882 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
883 {
884 struct mlx5_ib_ucontext *context;
885
886 context = to_mucontext(pd->uobject->context);
887 mlx5_ib_db_unmap_user(context, &qp->db);
888 if (base->ubuffer.umem)
889 ib_umem_release(base->ubuffer.umem);
890 free_bfreg(dev, &context->bfregi, qp->bfregn);
891 }
892
893 static int create_kernel_qp(struct mlx5_ib_dev *dev,
894 struct ib_qp_init_attr *init_attr,
895 struct mlx5_ib_qp *qp,
896 u32 **in, int *inlen,
897 struct mlx5_ib_qp_base *base)
898 {
899 int uar_index;
900 void *qpc;
901 int err;
902
903 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
904 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
905 IB_QP_CREATE_IPOIB_UD_LSO |
906 IB_QP_CREATE_NETIF_QP |
907 mlx5_ib_create_qp_sqpn_qp1()))
908 return -EINVAL;
909
910 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
911 qp->bf.bfreg = &dev->fp_bfreg;
912 else
913 qp->bf.bfreg = &dev->bfreg;
914
915 /* We need to divide by two since each register is comprised of
916 * two buffers of identical size, namely odd and even
917 */
918 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
919 uar_index = qp->bf.bfreg->index;
920
921 err = calc_sq_size(dev, init_attr, qp);
922 if (err < 0) {
923 mlx5_ib_dbg(dev, "err %d\n", err);
924 return err;
925 }
926
927 qp->rq.offset = 0;
928 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
929 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
930
931 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
932 if (err) {
933 mlx5_ib_dbg(dev, "err %d\n", err);
934 return err;
935 }
936
937 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
938 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
939 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
940 *in = kvzalloc(*inlen, GFP_KERNEL);
941 if (!*in) {
942 err = -ENOMEM;
943 goto err_buf;
944 }
945
946 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
947 MLX5_SET(qpc, qpc, uar_page, uar_index);
948 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
949
950 /* Set "fast registration enabled" for all kernel QPs */
951 MLX5_SET(qpc, qpc, fre, 1);
952 MLX5_SET(qpc, qpc, rlky, 1);
953
954 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
955 MLX5_SET(qpc, qpc, deth_sqpn, 1);
956 qp->flags |= MLX5_IB_QP_SQPN_QP1;
957 }
958
959 mlx5_fill_page_array(&qp->buf,
960 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
961
962 err = mlx5_db_alloc(dev->mdev, &qp->db);
963 if (err) {
964 mlx5_ib_dbg(dev, "err %d\n", err);
965 goto err_free;
966 }
967
968 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
969 sizeof(*qp->sq.wrid), GFP_KERNEL);
970 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
971 sizeof(*qp->sq.wr_data), GFP_KERNEL);
972 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
973 sizeof(*qp->rq.wrid), GFP_KERNEL);
974 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
975 sizeof(*qp->sq.w_list), GFP_KERNEL);
976 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
977 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
978
979 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
980 !qp->sq.w_list || !qp->sq.wqe_head) {
981 err = -ENOMEM;
982 goto err_wrid;
983 }
984 qp->create_type = MLX5_QP_KERNEL;
985
986 return 0;
987
988 err_wrid:
989 kvfree(qp->sq.wqe_head);
990 kvfree(qp->sq.w_list);
991 kvfree(qp->sq.wrid);
992 kvfree(qp->sq.wr_data);
993 kvfree(qp->rq.wrid);
994 mlx5_db_free(dev->mdev, &qp->db);
995
996 err_free:
997 kvfree(*in);
998
999 err_buf:
1000 mlx5_buf_free(dev->mdev, &qp->buf);
1001 return err;
1002 }
1003
1004 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1005 {
1006 kvfree(qp->sq.wqe_head);
1007 kvfree(qp->sq.w_list);
1008 kvfree(qp->sq.wrid);
1009 kvfree(qp->sq.wr_data);
1010 kvfree(qp->rq.wrid);
1011 mlx5_db_free(dev->mdev, &qp->db);
1012 mlx5_buf_free(dev->mdev, &qp->buf);
1013 }
1014
1015 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1016 {
1017 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1018 (attr->qp_type == IB_QPT_XRC_INI))
1019 return MLX5_SRQ_RQ;
1020 else if (!qp->has_rq)
1021 return MLX5_ZERO_LEN_RQ;
1022 else
1023 return MLX5_NON_ZERO_RQ;
1024 }
1025
1026 static int is_connected(enum ib_qp_type qp_type)
1027 {
1028 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1029 return 1;
1030
1031 return 0;
1032 }
1033
1034 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1035 struct mlx5_ib_qp *qp,
1036 struct mlx5_ib_sq *sq, u32 tdn)
1037 {
1038 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1039 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1040
1041 MLX5_SET(tisc, tisc, transport_domain, tdn);
1042 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1043 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1044
1045 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1046 }
1047
1048 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1049 struct mlx5_ib_sq *sq)
1050 {
1051 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1052 }
1053
1054 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1055 struct mlx5_ib_sq *sq, void *qpin,
1056 struct ib_pd *pd)
1057 {
1058 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1059 __be64 *pas;
1060 void *in;
1061 void *sqc;
1062 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1063 void *wq;
1064 int inlen;
1065 int err;
1066 int page_shift = 0;
1067 int npages;
1068 int ncont = 0;
1069 u32 offset = 0;
1070
1071 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1072 &sq->ubuffer.umem, &npages, &page_shift,
1073 &ncont, &offset);
1074 if (err)
1075 return err;
1076
1077 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1078 in = kvzalloc(inlen, GFP_KERNEL);
1079 if (!in) {
1080 err = -ENOMEM;
1081 goto err_umem;
1082 }
1083
1084 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1085 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1086 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1087 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1088 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1089 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1090 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1091 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1092 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1093 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1094 MLX5_CAP_ETH(dev->mdev, swp))
1095 MLX5_SET(sqc, sqc, allow_swp, 1);
1096
1097 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1098 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1099 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1100 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1101 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1102 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1103 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1104 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1105 MLX5_SET(wq, wq, page_offset, offset);
1106
1107 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1108 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1109
1110 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1111
1112 kvfree(in);
1113
1114 if (err)
1115 goto err_umem;
1116
1117 return 0;
1118
1119 err_umem:
1120 ib_umem_release(sq->ubuffer.umem);
1121 sq->ubuffer.umem = NULL;
1122
1123 return err;
1124 }
1125
1126 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1127 struct mlx5_ib_sq *sq)
1128 {
1129 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1130 ib_umem_release(sq->ubuffer.umem);
1131 }
1132
1133 static int get_rq_pas_size(void *qpc)
1134 {
1135 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1136 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1137 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1138 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1139 u32 po_quanta = 1 << (log_page_size - 6);
1140 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1141 u32 page_size = 1 << log_page_size;
1142 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1143 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1144
1145 return rq_num_pas * sizeof(u64);
1146 }
1147
1148 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1149 struct mlx5_ib_rq *rq, void *qpin)
1150 {
1151 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1152 __be64 *pas;
1153 __be64 *qp_pas;
1154 void *in;
1155 void *rqc;
1156 void *wq;
1157 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1158 int inlen;
1159 int err;
1160 u32 rq_pas_size = get_rq_pas_size(qpc);
1161
1162 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1163 in = kvzalloc(inlen, GFP_KERNEL);
1164 if (!in)
1165 return -ENOMEM;
1166
1167 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1168 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1169 MLX5_SET(rqc, rqc, vsd, 1);
1170 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1171 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1172 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1173 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1174 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1175
1176 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1177 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1178
1179 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1180 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1181 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1182 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1183 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1184 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1185 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1186 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1187 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1188 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1189
1190 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1191 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1192 memcpy(pas, qp_pas, rq_pas_size);
1193
1194 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1195
1196 kvfree(in);
1197
1198 return err;
1199 }
1200
1201 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1202 struct mlx5_ib_rq *rq)
1203 {
1204 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1205 }
1206
1207 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1208 {
1209 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1210 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1211 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1212 }
1213
1214 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1215 struct mlx5_ib_rq *rq, u32 tdn,
1216 bool tunnel_offload_en)
1217 {
1218 u32 *in;
1219 void *tirc;
1220 int inlen;
1221 int err;
1222
1223 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1224 in = kvzalloc(inlen, GFP_KERNEL);
1225 if (!in)
1226 return -ENOMEM;
1227
1228 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1229 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1230 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1231 MLX5_SET(tirc, tirc, transport_domain, tdn);
1232 if (tunnel_offload_en)
1233 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1234
1235 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1236
1237 kvfree(in);
1238
1239 return err;
1240 }
1241
1242 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1243 struct mlx5_ib_rq *rq)
1244 {
1245 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1246 }
1247
1248 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1249 u32 *in,
1250 struct ib_pd *pd)
1251 {
1252 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1253 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1254 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1255 struct ib_uobject *uobj = pd->uobject;
1256 struct ib_ucontext *ucontext = uobj->context;
1257 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1258 int err;
1259 u32 tdn = mucontext->tdn;
1260
1261 if (qp->sq.wqe_cnt) {
1262 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1263 if (err)
1264 return err;
1265
1266 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1267 if (err)
1268 goto err_destroy_tis;
1269
1270 sq->base.container_mibqp = qp;
1271 sq->base.mqp.event = mlx5_ib_qp_event;
1272 }
1273
1274 if (qp->rq.wqe_cnt) {
1275 rq->base.container_mibqp = qp;
1276
1277 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1278 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1279 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1280 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1281 err = create_raw_packet_qp_rq(dev, rq, in);
1282 if (err)
1283 goto err_destroy_sq;
1284
1285
1286 err = create_raw_packet_qp_tir(dev, rq, tdn,
1287 qp->tunnel_offload_en);
1288 if (err)
1289 goto err_destroy_rq;
1290 }
1291
1292 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1293 rq->base.mqp.qpn;
1294
1295 return 0;
1296
1297 err_destroy_rq:
1298 destroy_raw_packet_qp_rq(dev, rq);
1299 err_destroy_sq:
1300 if (!qp->sq.wqe_cnt)
1301 return err;
1302 destroy_raw_packet_qp_sq(dev, sq);
1303 err_destroy_tis:
1304 destroy_raw_packet_qp_tis(dev, sq);
1305
1306 return err;
1307 }
1308
1309 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1310 struct mlx5_ib_qp *qp)
1311 {
1312 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1313 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1314 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1315
1316 if (qp->rq.wqe_cnt) {
1317 destroy_raw_packet_qp_tir(dev, rq);
1318 destroy_raw_packet_qp_rq(dev, rq);
1319 }
1320
1321 if (qp->sq.wqe_cnt) {
1322 destroy_raw_packet_qp_sq(dev, sq);
1323 destroy_raw_packet_qp_tis(dev, sq);
1324 }
1325 }
1326
1327 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1328 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1329 {
1330 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1331 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1332
1333 sq->sq = &qp->sq;
1334 rq->rq = &qp->rq;
1335 sq->doorbell = &qp->db;
1336 rq->doorbell = &qp->db;
1337 }
1338
1339 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1340 {
1341 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1342 }
1343
1344 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1345 struct ib_pd *pd,
1346 struct ib_qp_init_attr *init_attr,
1347 struct ib_udata *udata)
1348 {
1349 struct ib_uobject *uobj = pd->uobject;
1350 struct ib_ucontext *ucontext = uobj->context;
1351 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1352 struct mlx5_ib_create_qp_resp resp = {};
1353 int inlen;
1354 int err;
1355 u32 *in;
1356 void *tirc;
1357 void *hfso;
1358 u32 selected_fields = 0;
1359 size_t min_resp_len;
1360 u32 tdn = mucontext->tdn;
1361 struct mlx5_ib_create_qp_rss ucmd = {};
1362 size_t required_cmd_sz;
1363
1364 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1365 return -EOPNOTSUPP;
1366
1367 if (init_attr->create_flags || init_attr->send_cq)
1368 return -EINVAL;
1369
1370 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1371 if (udata->outlen < min_resp_len)
1372 return -EINVAL;
1373
1374 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1375 if (udata->inlen < required_cmd_sz) {
1376 mlx5_ib_dbg(dev, "invalid inlen\n");
1377 return -EINVAL;
1378 }
1379
1380 if (udata->inlen > sizeof(ucmd) &&
1381 !ib_is_udata_cleared(udata, sizeof(ucmd),
1382 udata->inlen - sizeof(ucmd))) {
1383 mlx5_ib_dbg(dev, "inlen is not supported\n");
1384 return -EOPNOTSUPP;
1385 }
1386
1387 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1388 mlx5_ib_dbg(dev, "copy failed\n");
1389 return -EFAULT;
1390 }
1391
1392 if (ucmd.comp_mask) {
1393 mlx5_ib_dbg(dev, "invalid comp mask\n");
1394 return -EOPNOTSUPP;
1395 }
1396
1397 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1398 mlx5_ib_dbg(dev, "invalid flags\n");
1399 return -EOPNOTSUPP;
1400 }
1401
1402 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1403 !tunnel_offload_supported(dev->mdev)) {
1404 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1405 return -EOPNOTSUPP;
1406 }
1407
1408 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1409 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1410 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1411 return -EOPNOTSUPP;
1412 }
1413
1414 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1415 if (err) {
1416 mlx5_ib_dbg(dev, "copy failed\n");
1417 return -EINVAL;
1418 }
1419
1420 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1421 in = kvzalloc(inlen, GFP_KERNEL);
1422 if (!in)
1423 return -ENOMEM;
1424
1425 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1426 MLX5_SET(tirc, tirc, disp_type,
1427 MLX5_TIRC_DISP_TYPE_INDIRECT);
1428 MLX5_SET(tirc, tirc, indirect_table,
1429 init_attr->rwq_ind_tbl->ind_tbl_num);
1430 MLX5_SET(tirc, tirc, transport_domain, tdn);
1431
1432 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1433
1434 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1435 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1436
1437 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1438 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1439 else
1440 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1441
1442 switch (ucmd.rx_hash_function) {
1443 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1444 {
1445 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1446 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1447
1448 if (len != ucmd.rx_key_len) {
1449 err = -EINVAL;
1450 goto err;
1451 }
1452
1453 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1454 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1455 memcpy(rss_key, ucmd.rx_hash_key, len);
1456 break;
1457 }
1458 default:
1459 err = -EOPNOTSUPP;
1460 goto err;
1461 }
1462
1463 if (!ucmd.rx_hash_fields_mask) {
1464 /* special case when this TIR serves as steering entry without hashing */
1465 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1466 goto create_tir;
1467 err = -EINVAL;
1468 goto err;
1469 }
1470
1471 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1472 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1473 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1474 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1475 err = -EINVAL;
1476 goto err;
1477 }
1478
1479 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1480 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1481 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1482 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1483 MLX5_L3_PROT_TYPE_IPV4);
1484 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1485 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1486 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1487 MLX5_L3_PROT_TYPE_IPV6);
1488
1489 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1490 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1491 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1492 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1493 err = -EINVAL;
1494 goto err;
1495 }
1496
1497 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1498 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1499 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1500 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1501 MLX5_L4_PROT_TYPE_TCP);
1502 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1503 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1504 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1505 MLX5_L4_PROT_TYPE_UDP);
1506
1507 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1508 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1509 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1510
1511 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1512 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1513 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1514
1515 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1516 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1517 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1518
1519 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1520 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1521 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1522
1523 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1524
1525 create_tir:
1526 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1527
1528 if (err)
1529 goto err;
1530
1531 kvfree(in);
1532 /* qpn is reserved for that QP */
1533 qp->trans_qp.base.mqp.qpn = 0;
1534 qp->flags |= MLX5_IB_QP_RSS;
1535 return 0;
1536
1537 err:
1538 kvfree(in);
1539 return err;
1540 }
1541
1542 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1543 struct ib_qp_init_attr *init_attr,
1544 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1545 {
1546 struct mlx5_ib_resources *devr = &dev->devr;
1547 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1548 struct mlx5_core_dev *mdev = dev->mdev;
1549 struct mlx5_ib_create_qp_resp resp;
1550 struct mlx5_ib_cq *send_cq;
1551 struct mlx5_ib_cq *recv_cq;
1552 unsigned long flags;
1553 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1554 struct mlx5_ib_create_qp ucmd;
1555 struct mlx5_ib_qp_base *base;
1556 void *qpc;
1557 u32 *in;
1558 int err;
1559
1560 mutex_init(&qp->mutex);
1561 spin_lock_init(&qp->sq.lock);
1562 spin_lock_init(&qp->rq.lock);
1563
1564 if (init_attr->rwq_ind_tbl) {
1565 if (!udata)
1566 return -ENOSYS;
1567
1568 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1569 return err;
1570 }
1571
1572 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1573 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1574 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1575 return -EINVAL;
1576 } else {
1577 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1578 }
1579 }
1580
1581 if (init_attr->create_flags &
1582 (IB_QP_CREATE_CROSS_CHANNEL |
1583 IB_QP_CREATE_MANAGED_SEND |
1584 IB_QP_CREATE_MANAGED_RECV)) {
1585 if (!MLX5_CAP_GEN(mdev, cd)) {
1586 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1587 return -EINVAL;
1588 }
1589 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1590 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1591 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1592 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1593 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1594 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1595 }
1596
1597 if (init_attr->qp_type == IB_QPT_UD &&
1598 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1599 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1600 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1601 return -EOPNOTSUPP;
1602 }
1603
1604 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1605 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1606 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1607 return -EOPNOTSUPP;
1608 }
1609 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1610 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1611 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1612 return -EOPNOTSUPP;
1613 }
1614 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1615 }
1616
1617 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1618 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1619
1620 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1621 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1622 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1623 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1624 return -EOPNOTSUPP;
1625 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1626 }
1627
1628 if (pd && pd->uobject) {
1629 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1630 mlx5_ib_dbg(dev, "copy failed\n");
1631 return -EFAULT;
1632 }
1633
1634 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1635 &ucmd, udata->inlen, &uidx);
1636 if (err)
1637 return err;
1638
1639 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1640 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1641 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1642 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1643 !tunnel_offload_supported(mdev)) {
1644 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1645 return -EOPNOTSUPP;
1646 }
1647 qp->tunnel_offload_en = true;
1648 }
1649
1650 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1651 if (init_attr->qp_type != IB_QPT_UD ||
1652 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1653 MLX5_CAP_PORT_TYPE_IB) ||
1654 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1655 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1656 return -EOPNOTSUPP;
1657 }
1658
1659 qp->flags |= MLX5_IB_QP_UNDERLAY;
1660 qp->underlay_qpn = init_attr->source_qpn;
1661 }
1662 } else {
1663 qp->wq_sig = !!wq_signature;
1664 }
1665
1666 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1667 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1668 &qp->raw_packet_qp.rq.base :
1669 &qp->trans_qp.base;
1670
1671 qp->has_rq = qp_has_rq(init_attr);
1672 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1673 qp, (pd && pd->uobject) ? &ucmd : NULL);
1674 if (err) {
1675 mlx5_ib_dbg(dev, "err %d\n", err);
1676 return err;
1677 }
1678
1679 if (pd) {
1680 if (pd->uobject) {
1681 __u32 max_wqes =
1682 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1683 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1684 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1685 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1686 mlx5_ib_dbg(dev, "invalid rq params\n");
1687 return -EINVAL;
1688 }
1689 if (ucmd.sq_wqe_count > max_wqes) {
1690 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1691 ucmd.sq_wqe_count, max_wqes);
1692 return -EINVAL;
1693 }
1694 if (init_attr->create_flags &
1695 mlx5_ib_create_qp_sqpn_qp1()) {
1696 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1697 return -EINVAL;
1698 }
1699 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1700 &resp, &inlen, base);
1701 if (err)
1702 mlx5_ib_dbg(dev, "err %d\n", err);
1703 } else {
1704 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1705 base);
1706 if (err)
1707 mlx5_ib_dbg(dev, "err %d\n", err);
1708 }
1709
1710 if (err)
1711 return err;
1712 } else {
1713 in = kvzalloc(inlen, GFP_KERNEL);
1714 if (!in)
1715 return -ENOMEM;
1716
1717 qp->create_type = MLX5_QP_EMPTY;
1718 }
1719
1720 if (is_sqp(init_attr->qp_type))
1721 qp->port = init_attr->port_num;
1722
1723 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1724
1725 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1726 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1727
1728 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1729 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1730 else
1731 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1732
1733
1734 if (qp->wq_sig)
1735 MLX5_SET(qpc, qpc, wq_signature, 1);
1736
1737 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1738 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1739
1740 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1741 MLX5_SET(qpc, qpc, cd_master, 1);
1742 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1743 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1744 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1745 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1746
1747 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1748 int rcqe_sz;
1749 int scqe_sz;
1750
1751 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1752 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1753
1754 if (rcqe_sz == 128)
1755 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1756 else
1757 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1758
1759 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1760 if (scqe_sz == 128)
1761 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1762 else
1763 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1764 }
1765 }
1766
1767 if (qp->rq.wqe_cnt) {
1768 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1769 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1770 }
1771
1772 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1773
1774 if (qp->sq.wqe_cnt) {
1775 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1776 } else {
1777 MLX5_SET(qpc, qpc, no_sq, 1);
1778 if (init_attr->srq &&
1779 init_attr->srq->srq_type == IB_SRQT_TM)
1780 MLX5_SET(qpc, qpc, offload_type,
1781 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1782 }
1783
1784 /* Set default resources */
1785 switch (init_attr->qp_type) {
1786 case IB_QPT_XRC_TGT:
1787 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1788 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1789 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1790 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1791 break;
1792 case IB_QPT_XRC_INI:
1793 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1794 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1795 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1796 break;
1797 default:
1798 if (init_attr->srq) {
1799 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1800 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1801 } else {
1802 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1803 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1804 }
1805 }
1806
1807 if (init_attr->send_cq)
1808 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1809
1810 if (init_attr->recv_cq)
1811 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1812
1813 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1814
1815 /* 0xffffff means we ask to work with cqe version 0 */
1816 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1817 MLX5_SET(qpc, qpc, user_index, uidx);
1818
1819 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1820 if (init_attr->qp_type == IB_QPT_UD &&
1821 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1822 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1823 qp->flags |= MLX5_IB_QP_LSO;
1824 }
1825
1826 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1827 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1828 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1829 err = -EOPNOTSUPP;
1830 goto err;
1831 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1832 MLX5_SET(qpc, qpc, end_padding_mode,
1833 MLX5_WQ_END_PAD_MODE_ALIGN);
1834 } else {
1835 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1836 }
1837 }
1838
1839 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1840 qp->flags & MLX5_IB_QP_UNDERLAY) {
1841 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1842 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1843 err = create_raw_packet_qp(dev, qp, in, pd);
1844 } else {
1845 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1846 }
1847
1848 if (err) {
1849 mlx5_ib_dbg(dev, "create qp failed\n");
1850 goto err_create;
1851 }
1852
1853 kvfree(in);
1854
1855 base->container_mibqp = qp;
1856 base->mqp.event = mlx5_ib_qp_event;
1857
1858 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1859 &send_cq, &recv_cq);
1860 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1861 mlx5_ib_lock_cqs(send_cq, recv_cq);
1862 /* Maintain device to QPs access, needed for further handling via reset
1863 * flow
1864 */
1865 list_add_tail(&qp->qps_list, &dev->qp_list);
1866 /* Maintain CQ to QPs access, needed for further handling via reset flow
1867 */
1868 if (send_cq)
1869 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1870 if (recv_cq)
1871 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1872 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1873 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1874
1875 return 0;
1876
1877 err_create:
1878 if (qp->create_type == MLX5_QP_USER)
1879 destroy_qp_user(dev, pd, qp, base);
1880 else if (qp->create_type == MLX5_QP_KERNEL)
1881 destroy_qp_kernel(dev, qp);
1882
1883 err:
1884 kvfree(in);
1885 return err;
1886 }
1887
1888 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1889 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1890 {
1891 if (send_cq) {
1892 if (recv_cq) {
1893 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1894 spin_lock(&send_cq->lock);
1895 spin_lock_nested(&recv_cq->lock,
1896 SINGLE_DEPTH_NESTING);
1897 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1898 spin_lock(&send_cq->lock);
1899 __acquire(&recv_cq->lock);
1900 } else {
1901 spin_lock(&recv_cq->lock);
1902 spin_lock_nested(&send_cq->lock,
1903 SINGLE_DEPTH_NESTING);
1904 }
1905 } else {
1906 spin_lock(&send_cq->lock);
1907 __acquire(&recv_cq->lock);
1908 }
1909 } else if (recv_cq) {
1910 spin_lock(&recv_cq->lock);
1911 __acquire(&send_cq->lock);
1912 } else {
1913 __acquire(&send_cq->lock);
1914 __acquire(&recv_cq->lock);
1915 }
1916 }
1917
1918 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1919 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1920 {
1921 if (send_cq) {
1922 if (recv_cq) {
1923 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1924 spin_unlock(&recv_cq->lock);
1925 spin_unlock(&send_cq->lock);
1926 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1927 __release(&recv_cq->lock);
1928 spin_unlock(&send_cq->lock);
1929 } else {
1930 spin_unlock(&send_cq->lock);
1931 spin_unlock(&recv_cq->lock);
1932 }
1933 } else {
1934 __release(&recv_cq->lock);
1935 spin_unlock(&send_cq->lock);
1936 }
1937 } else if (recv_cq) {
1938 __release(&send_cq->lock);
1939 spin_unlock(&recv_cq->lock);
1940 } else {
1941 __release(&recv_cq->lock);
1942 __release(&send_cq->lock);
1943 }
1944 }
1945
1946 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1947 {
1948 return to_mpd(qp->ibqp.pd);
1949 }
1950
1951 static void get_cqs(enum ib_qp_type qp_type,
1952 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1953 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1954 {
1955 switch (qp_type) {
1956 case IB_QPT_XRC_TGT:
1957 *send_cq = NULL;
1958 *recv_cq = NULL;
1959 break;
1960 case MLX5_IB_QPT_REG_UMR:
1961 case IB_QPT_XRC_INI:
1962 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1963 *recv_cq = NULL;
1964 break;
1965
1966 case IB_QPT_SMI:
1967 case MLX5_IB_QPT_HW_GSI:
1968 case IB_QPT_RC:
1969 case IB_QPT_UC:
1970 case IB_QPT_UD:
1971 case IB_QPT_RAW_IPV6:
1972 case IB_QPT_RAW_ETHERTYPE:
1973 case IB_QPT_RAW_PACKET:
1974 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1975 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1976 break;
1977
1978 case IB_QPT_MAX:
1979 default:
1980 *send_cq = NULL;
1981 *recv_cq = NULL;
1982 break;
1983 }
1984 }
1985
1986 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1987 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1988 u8 lag_tx_affinity);
1989
1990 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1991 {
1992 struct mlx5_ib_cq *send_cq, *recv_cq;
1993 struct mlx5_ib_qp_base *base;
1994 unsigned long flags;
1995 int err;
1996
1997 if (qp->ibqp.rwq_ind_tbl) {
1998 destroy_rss_raw_qp_tir(dev, qp);
1999 return;
2000 }
2001
2002 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2003 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2004 &qp->raw_packet_qp.rq.base :
2005 &qp->trans_qp.base;
2006
2007 if (qp->state != IB_QPS_RESET) {
2008 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2009 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2010 err = mlx5_core_qp_modify(dev->mdev,
2011 MLX5_CMD_OP_2RST_QP, 0,
2012 NULL, &base->mqp);
2013 } else {
2014 struct mlx5_modify_raw_qp_param raw_qp_param = {
2015 .operation = MLX5_CMD_OP_2RST_QP
2016 };
2017
2018 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2019 }
2020 if (err)
2021 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2022 base->mqp.qpn);
2023 }
2024
2025 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2026 &send_cq, &recv_cq);
2027
2028 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2029 mlx5_ib_lock_cqs(send_cq, recv_cq);
2030 /* del from lists under both locks above to protect reset flow paths */
2031 list_del(&qp->qps_list);
2032 if (send_cq)
2033 list_del(&qp->cq_send_list);
2034
2035 if (recv_cq)
2036 list_del(&qp->cq_recv_list);
2037
2038 if (qp->create_type == MLX5_QP_KERNEL) {
2039 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2040 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2041 if (send_cq != recv_cq)
2042 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2043 NULL);
2044 }
2045 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2046 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2047
2048 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2049 qp->flags & MLX5_IB_QP_UNDERLAY) {
2050 destroy_raw_packet_qp(dev, qp);
2051 } else {
2052 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2053 if (err)
2054 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2055 base->mqp.qpn);
2056 }
2057
2058 if (qp->create_type == MLX5_QP_KERNEL)
2059 destroy_qp_kernel(dev, qp);
2060 else if (qp->create_type == MLX5_QP_USER)
2061 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2062 }
2063
2064 static const char *ib_qp_type_str(enum ib_qp_type type)
2065 {
2066 switch (type) {
2067 case IB_QPT_SMI:
2068 return "IB_QPT_SMI";
2069 case IB_QPT_GSI:
2070 return "IB_QPT_GSI";
2071 case IB_QPT_RC:
2072 return "IB_QPT_RC";
2073 case IB_QPT_UC:
2074 return "IB_QPT_UC";
2075 case IB_QPT_UD:
2076 return "IB_QPT_UD";
2077 case IB_QPT_RAW_IPV6:
2078 return "IB_QPT_RAW_IPV6";
2079 case IB_QPT_RAW_ETHERTYPE:
2080 return "IB_QPT_RAW_ETHERTYPE";
2081 case IB_QPT_XRC_INI:
2082 return "IB_QPT_XRC_INI";
2083 case IB_QPT_XRC_TGT:
2084 return "IB_QPT_XRC_TGT";
2085 case IB_QPT_RAW_PACKET:
2086 return "IB_QPT_RAW_PACKET";
2087 case MLX5_IB_QPT_REG_UMR:
2088 return "MLX5_IB_QPT_REG_UMR";
2089 case IB_QPT_MAX:
2090 default:
2091 return "Invalid QP type";
2092 }
2093 }
2094
2095 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2096 struct ib_qp_init_attr *init_attr,
2097 struct ib_udata *udata)
2098 {
2099 struct mlx5_ib_dev *dev;
2100 struct mlx5_ib_qp *qp;
2101 u16 xrcdn = 0;
2102 int err;
2103
2104 if (pd) {
2105 dev = to_mdev(pd->device);
2106
2107 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2108 if (!pd->uobject) {
2109 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2110 return ERR_PTR(-EINVAL);
2111 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2112 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2113 return ERR_PTR(-EINVAL);
2114 }
2115 }
2116 } else {
2117 /* being cautious here */
2118 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2119 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2120 pr_warn("%s: no PD for transport %s\n", __func__,
2121 ib_qp_type_str(init_attr->qp_type));
2122 return ERR_PTR(-EINVAL);
2123 }
2124 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2125 }
2126
2127 switch (init_attr->qp_type) {
2128 case IB_QPT_XRC_TGT:
2129 case IB_QPT_XRC_INI:
2130 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2131 mlx5_ib_dbg(dev, "XRC not supported\n");
2132 return ERR_PTR(-ENOSYS);
2133 }
2134 init_attr->recv_cq = NULL;
2135 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2136 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2137 init_attr->send_cq = NULL;
2138 }
2139
2140 /* fall through */
2141 case IB_QPT_RAW_PACKET:
2142 case IB_QPT_RC:
2143 case IB_QPT_UC:
2144 case IB_QPT_UD:
2145 case IB_QPT_SMI:
2146 case MLX5_IB_QPT_HW_GSI:
2147 case MLX5_IB_QPT_REG_UMR:
2148 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2149 if (!qp)
2150 return ERR_PTR(-ENOMEM);
2151
2152 err = create_qp_common(dev, pd, init_attr, udata, qp);
2153 if (err) {
2154 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2155 kfree(qp);
2156 return ERR_PTR(err);
2157 }
2158
2159 if (is_qp0(init_attr->qp_type))
2160 qp->ibqp.qp_num = 0;
2161 else if (is_qp1(init_attr->qp_type))
2162 qp->ibqp.qp_num = 1;
2163 else
2164 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2165
2166 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2167 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2168 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2169 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2170
2171 qp->trans_qp.xrcdn = xrcdn;
2172
2173 break;
2174
2175 case IB_QPT_GSI:
2176 return mlx5_ib_gsi_create_qp(pd, init_attr);
2177
2178 case IB_QPT_RAW_IPV6:
2179 case IB_QPT_RAW_ETHERTYPE:
2180 case IB_QPT_MAX:
2181 default:
2182 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2183 init_attr->qp_type);
2184 /* Don't support raw QPs */
2185 return ERR_PTR(-EINVAL);
2186 }
2187
2188 return &qp->ibqp;
2189 }
2190
2191 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2192 {
2193 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2194 struct mlx5_ib_qp *mqp = to_mqp(qp);
2195
2196 if (unlikely(qp->qp_type == IB_QPT_GSI))
2197 return mlx5_ib_gsi_destroy_qp(qp);
2198
2199 destroy_qp_common(dev, mqp);
2200
2201 kfree(mqp);
2202
2203 return 0;
2204 }
2205
2206 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2207 int attr_mask)
2208 {
2209 u32 hw_access_flags = 0;
2210 u8 dest_rd_atomic;
2211 u32 access_flags;
2212
2213 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2214 dest_rd_atomic = attr->max_dest_rd_atomic;
2215 else
2216 dest_rd_atomic = qp->trans_qp.resp_depth;
2217
2218 if (attr_mask & IB_QP_ACCESS_FLAGS)
2219 access_flags = attr->qp_access_flags;
2220 else
2221 access_flags = qp->trans_qp.atomic_rd_en;
2222
2223 if (!dest_rd_atomic)
2224 access_flags &= IB_ACCESS_REMOTE_WRITE;
2225
2226 if (access_flags & IB_ACCESS_REMOTE_READ)
2227 hw_access_flags |= MLX5_QP_BIT_RRE;
2228 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2229 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2230 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2231 hw_access_flags |= MLX5_QP_BIT_RWE;
2232
2233 return cpu_to_be32(hw_access_flags);
2234 }
2235
2236 enum {
2237 MLX5_PATH_FLAG_FL = 1 << 0,
2238 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2239 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2240 };
2241
2242 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2243 {
2244 if (rate == IB_RATE_PORT_CURRENT) {
2245 return 0;
2246 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2247 return -EINVAL;
2248 } else {
2249 while (rate != IB_RATE_2_5_GBPS &&
2250 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2251 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2252 --rate;
2253 }
2254
2255 return rate + MLX5_STAT_RATE_OFFSET;
2256 }
2257
2258 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2259 struct mlx5_ib_sq *sq, u8 sl)
2260 {
2261 void *in;
2262 void *tisc;
2263 int inlen;
2264 int err;
2265
2266 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2267 in = kvzalloc(inlen, GFP_KERNEL);
2268 if (!in)
2269 return -ENOMEM;
2270
2271 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2272
2273 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2274 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2275
2276 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2277
2278 kvfree(in);
2279
2280 return err;
2281 }
2282
2283 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2284 struct mlx5_ib_sq *sq, u8 tx_affinity)
2285 {
2286 void *in;
2287 void *tisc;
2288 int inlen;
2289 int err;
2290
2291 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2292 in = kvzalloc(inlen, GFP_KERNEL);
2293 if (!in)
2294 return -ENOMEM;
2295
2296 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2297
2298 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2299 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2300
2301 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2302
2303 kvfree(in);
2304
2305 return err;
2306 }
2307
2308 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2309 const struct rdma_ah_attr *ah,
2310 struct mlx5_qp_path *path, u8 port, int attr_mask,
2311 u32 path_flags, const struct ib_qp_attr *attr,
2312 bool alt)
2313 {
2314 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2315 int err;
2316 enum ib_gid_type gid_type;
2317 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2318 u8 sl = rdma_ah_get_sl(ah);
2319
2320 if (attr_mask & IB_QP_PKEY_INDEX)
2321 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2322 attr->pkey_index);
2323
2324 if (ah_flags & IB_AH_GRH) {
2325 if (grh->sgid_index >=
2326 dev->mdev->port_caps[port - 1].gid_table_len) {
2327 pr_err("sgid_index (%u) too large. max is %d\n",
2328 grh->sgid_index,
2329 dev->mdev->port_caps[port - 1].gid_table_len);
2330 return -EINVAL;
2331 }
2332 }
2333
2334 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2335 if (!(ah_flags & IB_AH_GRH))
2336 return -EINVAL;
2337 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2338 &gid_type);
2339 if (err)
2340 return err;
2341 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2342 if (qp->ibqp.qp_type == IB_QPT_RC ||
2343 qp->ibqp.qp_type == IB_QPT_UC ||
2344 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2345 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2346 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2347 grh->sgid_index);
2348 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2349 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2350 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2351 } else {
2352 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2353 path->fl_free_ar |=
2354 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2355 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2356 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2357 if (ah_flags & IB_AH_GRH)
2358 path->grh_mlid |= 1 << 7;
2359 path->dci_cfi_prio_sl = sl & 0xf;
2360 }
2361
2362 if (ah_flags & IB_AH_GRH) {
2363 path->mgid_index = grh->sgid_index;
2364 path->hop_limit = grh->hop_limit;
2365 path->tclass_flowlabel =
2366 cpu_to_be32((grh->traffic_class << 20) |
2367 (grh->flow_label));
2368 memcpy(path->rgid, grh->dgid.raw, 16);
2369 }
2370
2371 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2372 if (err < 0)
2373 return err;
2374 path->static_rate = err;
2375 path->port = port;
2376
2377 if (attr_mask & IB_QP_TIMEOUT)
2378 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2379
2380 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2381 return modify_raw_packet_eth_prio(dev->mdev,
2382 &qp->raw_packet_qp.sq,
2383 sl & 0xf);
2384
2385 return 0;
2386 }
2387
2388 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2389 [MLX5_QP_STATE_INIT] = {
2390 [MLX5_QP_STATE_INIT] = {
2391 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2392 MLX5_QP_OPTPAR_RAE |
2393 MLX5_QP_OPTPAR_RWE |
2394 MLX5_QP_OPTPAR_PKEY_INDEX |
2395 MLX5_QP_OPTPAR_PRI_PORT,
2396 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2397 MLX5_QP_OPTPAR_PKEY_INDEX |
2398 MLX5_QP_OPTPAR_PRI_PORT,
2399 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2400 MLX5_QP_OPTPAR_Q_KEY |
2401 MLX5_QP_OPTPAR_PRI_PORT,
2402 },
2403 [MLX5_QP_STATE_RTR] = {
2404 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2405 MLX5_QP_OPTPAR_RRE |
2406 MLX5_QP_OPTPAR_RAE |
2407 MLX5_QP_OPTPAR_RWE |
2408 MLX5_QP_OPTPAR_PKEY_INDEX,
2409 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2410 MLX5_QP_OPTPAR_RWE |
2411 MLX5_QP_OPTPAR_PKEY_INDEX,
2412 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2413 MLX5_QP_OPTPAR_Q_KEY,
2414 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2415 MLX5_QP_OPTPAR_Q_KEY,
2416 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2417 MLX5_QP_OPTPAR_RRE |
2418 MLX5_QP_OPTPAR_RAE |
2419 MLX5_QP_OPTPAR_RWE |
2420 MLX5_QP_OPTPAR_PKEY_INDEX,
2421 },
2422 },
2423 [MLX5_QP_STATE_RTR] = {
2424 [MLX5_QP_STATE_RTS] = {
2425 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2426 MLX5_QP_OPTPAR_RRE |
2427 MLX5_QP_OPTPAR_RAE |
2428 MLX5_QP_OPTPAR_RWE |
2429 MLX5_QP_OPTPAR_PM_STATE |
2430 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2431 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2432 MLX5_QP_OPTPAR_RWE |
2433 MLX5_QP_OPTPAR_PM_STATE,
2434 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2435 },
2436 },
2437 [MLX5_QP_STATE_RTS] = {
2438 [MLX5_QP_STATE_RTS] = {
2439 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2440 MLX5_QP_OPTPAR_RAE |
2441 MLX5_QP_OPTPAR_RWE |
2442 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2443 MLX5_QP_OPTPAR_PM_STATE |
2444 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2445 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2446 MLX5_QP_OPTPAR_PM_STATE |
2447 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2448 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2449 MLX5_QP_OPTPAR_SRQN |
2450 MLX5_QP_OPTPAR_CQN_RCV,
2451 },
2452 },
2453 [MLX5_QP_STATE_SQER] = {
2454 [MLX5_QP_STATE_RTS] = {
2455 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2456 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2457 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2458 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2459 MLX5_QP_OPTPAR_RWE |
2460 MLX5_QP_OPTPAR_RAE |
2461 MLX5_QP_OPTPAR_RRE,
2462 },
2463 },
2464 };
2465
2466 static int ib_nr_to_mlx5_nr(int ib_mask)
2467 {
2468 switch (ib_mask) {
2469 case IB_QP_STATE:
2470 return 0;
2471 case IB_QP_CUR_STATE:
2472 return 0;
2473 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2474 return 0;
2475 case IB_QP_ACCESS_FLAGS:
2476 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2477 MLX5_QP_OPTPAR_RAE;
2478 case IB_QP_PKEY_INDEX:
2479 return MLX5_QP_OPTPAR_PKEY_INDEX;
2480 case IB_QP_PORT:
2481 return MLX5_QP_OPTPAR_PRI_PORT;
2482 case IB_QP_QKEY:
2483 return MLX5_QP_OPTPAR_Q_KEY;
2484 case IB_QP_AV:
2485 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2486 MLX5_QP_OPTPAR_PRI_PORT;
2487 case IB_QP_PATH_MTU:
2488 return 0;
2489 case IB_QP_TIMEOUT:
2490 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2491 case IB_QP_RETRY_CNT:
2492 return MLX5_QP_OPTPAR_RETRY_COUNT;
2493 case IB_QP_RNR_RETRY:
2494 return MLX5_QP_OPTPAR_RNR_RETRY;
2495 case IB_QP_RQ_PSN:
2496 return 0;
2497 case IB_QP_MAX_QP_RD_ATOMIC:
2498 return MLX5_QP_OPTPAR_SRA_MAX;
2499 case IB_QP_ALT_PATH:
2500 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2501 case IB_QP_MIN_RNR_TIMER:
2502 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2503 case IB_QP_SQ_PSN:
2504 return 0;
2505 case IB_QP_MAX_DEST_RD_ATOMIC:
2506 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2507 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2508 case IB_QP_PATH_MIG_STATE:
2509 return MLX5_QP_OPTPAR_PM_STATE;
2510 case IB_QP_CAP:
2511 return 0;
2512 case IB_QP_DEST_QPN:
2513 return 0;
2514 }
2515 return 0;
2516 }
2517
2518 static int ib_mask_to_mlx5_opt(int ib_mask)
2519 {
2520 int result = 0;
2521 int i;
2522
2523 for (i = 0; i < 8 * sizeof(int); i++) {
2524 if ((1 << i) & ib_mask)
2525 result |= ib_nr_to_mlx5_nr(1 << i);
2526 }
2527
2528 return result;
2529 }
2530
2531 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2532 struct mlx5_ib_rq *rq, int new_state,
2533 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2534 {
2535 void *in;
2536 void *rqc;
2537 int inlen;
2538 int err;
2539
2540 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2541 in = kvzalloc(inlen, GFP_KERNEL);
2542 if (!in)
2543 return -ENOMEM;
2544
2545 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2546
2547 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2548 MLX5_SET(rqc, rqc, state, new_state);
2549
2550 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2551 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2552 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2553 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2554 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2555 } else
2556 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2557 dev->ib_dev.name);
2558 }
2559
2560 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2561 if (err)
2562 goto out;
2563
2564 rq->state = new_state;
2565
2566 out:
2567 kvfree(in);
2568 return err;
2569 }
2570
2571 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2572 struct mlx5_ib_sq *sq,
2573 int new_state,
2574 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2575 {
2576 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2577 u32 old_rate = ibqp->rate_limit;
2578 u32 new_rate = old_rate;
2579 u16 rl_index = 0;
2580 void *in;
2581 void *sqc;
2582 int inlen;
2583 int err;
2584
2585 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2586 in = kvzalloc(inlen, GFP_KERNEL);
2587 if (!in)
2588 return -ENOMEM;
2589
2590 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2591
2592 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2593 MLX5_SET(sqc, sqc, state, new_state);
2594
2595 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2596 if (new_state != MLX5_SQC_STATE_RDY)
2597 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2598 __func__);
2599 else
2600 new_rate = raw_qp_param->rate_limit;
2601 }
2602
2603 if (old_rate != new_rate) {
2604 if (new_rate) {
2605 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2606 if (err) {
2607 pr_err("Failed configuring rate %u: %d\n",
2608 new_rate, err);
2609 goto out;
2610 }
2611 }
2612
2613 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2614 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2615 }
2616
2617 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2618 if (err) {
2619 /* Remove new rate from table if failed */
2620 if (new_rate &&
2621 old_rate != new_rate)
2622 mlx5_rl_remove_rate(dev, new_rate);
2623 goto out;
2624 }
2625
2626 /* Only remove the old rate after new rate was set */
2627 if ((old_rate &&
2628 (old_rate != new_rate)) ||
2629 (new_state != MLX5_SQC_STATE_RDY))
2630 mlx5_rl_remove_rate(dev, old_rate);
2631
2632 ibqp->rate_limit = new_rate;
2633 sq->state = new_state;
2634
2635 out:
2636 kvfree(in);
2637 return err;
2638 }
2639
2640 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2641 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2642 u8 tx_affinity)
2643 {
2644 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2645 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2646 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2647 int modify_rq = !!qp->rq.wqe_cnt;
2648 int modify_sq = !!qp->sq.wqe_cnt;
2649 int rq_state;
2650 int sq_state;
2651 int err;
2652
2653 switch (raw_qp_param->operation) {
2654 case MLX5_CMD_OP_RST2INIT_QP:
2655 rq_state = MLX5_RQC_STATE_RDY;
2656 sq_state = MLX5_SQC_STATE_RDY;
2657 break;
2658 case MLX5_CMD_OP_2ERR_QP:
2659 rq_state = MLX5_RQC_STATE_ERR;
2660 sq_state = MLX5_SQC_STATE_ERR;
2661 break;
2662 case MLX5_CMD_OP_2RST_QP:
2663 rq_state = MLX5_RQC_STATE_RST;
2664 sq_state = MLX5_SQC_STATE_RST;
2665 break;
2666 case MLX5_CMD_OP_RTR2RTS_QP:
2667 case MLX5_CMD_OP_RTS2RTS_QP:
2668 if (raw_qp_param->set_mask ==
2669 MLX5_RAW_QP_RATE_LIMIT) {
2670 modify_rq = 0;
2671 sq_state = sq->state;
2672 } else {
2673 return raw_qp_param->set_mask ? -EINVAL : 0;
2674 }
2675 break;
2676 case MLX5_CMD_OP_INIT2INIT_QP:
2677 case MLX5_CMD_OP_INIT2RTR_QP:
2678 if (raw_qp_param->set_mask)
2679 return -EINVAL;
2680 else
2681 return 0;
2682 default:
2683 WARN_ON(1);
2684 return -EINVAL;
2685 }
2686
2687 if (modify_rq) {
2688 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2689 if (err)
2690 return err;
2691 }
2692
2693 if (modify_sq) {
2694 if (tx_affinity) {
2695 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2696 tx_affinity);
2697 if (err)
2698 return err;
2699 }
2700
2701 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2702 }
2703
2704 return 0;
2705 }
2706
2707 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2708 const struct ib_qp_attr *attr, int attr_mask,
2709 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2710 {
2711 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2712 [MLX5_QP_STATE_RST] = {
2713 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2714 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2715 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2716 },
2717 [MLX5_QP_STATE_INIT] = {
2718 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2719 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2720 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2721 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2722 },
2723 [MLX5_QP_STATE_RTR] = {
2724 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2725 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2726 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2727 },
2728 [MLX5_QP_STATE_RTS] = {
2729 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2730 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2731 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2732 },
2733 [MLX5_QP_STATE_SQD] = {
2734 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2735 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2736 },
2737 [MLX5_QP_STATE_SQER] = {
2738 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2739 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2740 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2741 },
2742 [MLX5_QP_STATE_ERR] = {
2743 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2744 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2745 }
2746 };
2747
2748 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2749 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2750 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2751 struct mlx5_ib_cq *send_cq, *recv_cq;
2752 struct mlx5_qp_context *context;
2753 struct mlx5_ib_pd *pd;
2754 struct mlx5_ib_port *mibport = NULL;
2755 enum mlx5_qp_state mlx5_cur, mlx5_new;
2756 enum mlx5_qp_optpar optpar;
2757 int mlx5_st;
2758 int err;
2759 u16 op;
2760 u8 tx_affinity = 0;
2761
2762 context = kzalloc(sizeof(*context), GFP_KERNEL);
2763 if (!context)
2764 return -ENOMEM;
2765
2766 err = to_mlx5_st(ibqp->qp_type);
2767 if (err < 0) {
2768 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2769 goto out;
2770 }
2771
2772 context->flags = cpu_to_be32(err << 16);
2773
2774 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2775 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2776 } else {
2777 switch (attr->path_mig_state) {
2778 case IB_MIG_MIGRATED:
2779 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2780 break;
2781 case IB_MIG_REARM:
2782 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2783 break;
2784 case IB_MIG_ARMED:
2785 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2786 break;
2787 }
2788 }
2789
2790 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2791 if ((ibqp->qp_type == IB_QPT_RC) ||
2792 (ibqp->qp_type == IB_QPT_UD &&
2793 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2794 (ibqp->qp_type == IB_QPT_UC) ||
2795 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2796 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2797 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2798 if (mlx5_lag_is_active(dev->mdev)) {
2799 tx_affinity = (unsigned int)atomic_add_return(1,
2800 &dev->roce.next_port) %
2801 MLX5_MAX_PORTS + 1;
2802 context->flags |= cpu_to_be32(tx_affinity << 24);
2803 }
2804 }
2805 }
2806
2807 if (is_sqp(ibqp->qp_type)) {
2808 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2809 } else if ((ibqp->qp_type == IB_QPT_UD &&
2810 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2811 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2812 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2813 } else if (attr_mask & IB_QP_PATH_MTU) {
2814 if (attr->path_mtu < IB_MTU_256 ||
2815 attr->path_mtu > IB_MTU_4096) {
2816 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2817 err = -EINVAL;
2818 goto out;
2819 }
2820 context->mtu_msgmax = (attr->path_mtu << 5) |
2821 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2822 }
2823
2824 if (attr_mask & IB_QP_DEST_QPN)
2825 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2826
2827 if (attr_mask & IB_QP_PKEY_INDEX)
2828 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2829
2830 /* todo implement counter_index functionality */
2831
2832 if (is_sqp(ibqp->qp_type))
2833 context->pri_path.port = qp->port;
2834
2835 if (attr_mask & IB_QP_PORT)
2836 context->pri_path.port = attr->port_num;
2837
2838 if (attr_mask & IB_QP_AV) {
2839 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2840 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2841 attr_mask, 0, attr, false);
2842 if (err)
2843 goto out;
2844 }
2845
2846 if (attr_mask & IB_QP_TIMEOUT)
2847 context->pri_path.ackto_lt |= attr->timeout << 3;
2848
2849 if (attr_mask & IB_QP_ALT_PATH) {
2850 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2851 &context->alt_path,
2852 attr->alt_port_num,
2853 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2854 0, attr, true);
2855 if (err)
2856 goto out;
2857 }
2858
2859 pd = get_pd(qp);
2860 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2861 &send_cq, &recv_cq);
2862
2863 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2864 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2865 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2866 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2867
2868 if (attr_mask & IB_QP_RNR_RETRY)
2869 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2870
2871 if (attr_mask & IB_QP_RETRY_CNT)
2872 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2873
2874 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2875 if (attr->max_rd_atomic)
2876 context->params1 |=
2877 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2878 }
2879
2880 if (attr_mask & IB_QP_SQ_PSN)
2881 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2882
2883 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2884 if (attr->max_dest_rd_atomic)
2885 context->params2 |=
2886 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2887 }
2888
2889 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2890 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2891
2892 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2893 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2894
2895 if (attr_mask & IB_QP_RQ_PSN)
2896 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2897
2898 if (attr_mask & IB_QP_QKEY)
2899 context->qkey = cpu_to_be32(attr->qkey);
2900
2901 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2902 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2903
2904 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2905 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2906 qp->port) - 1;
2907
2908 /* Underlay port should be used - index 0 function per port */
2909 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2910 port_num = 0;
2911
2912 mibport = &dev->port[port_num];
2913 context->qp_counter_set_usr_page |=
2914 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2915 }
2916
2917 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2918 context->sq_crq_size |= cpu_to_be16(1 << 4);
2919
2920 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2921 context->deth_sqpn = cpu_to_be32(1);
2922
2923 mlx5_cur = to_mlx5_state(cur_state);
2924 mlx5_new = to_mlx5_state(new_state);
2925 mlx5_st = to_mlx5_st(ibqp->qp_type);
2926 if (mlx5_st < 0)
2927 goto out;
2928
2929 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2930 !optab[mlx5_cur][mlx5_new])
2931 goto out;
2932
2933 op = optab[mlx5_cur][mlx5_new];
2934 optpar = ib_mask_to_mlx5_opt(attr_mask);
2935 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2936
2937 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2938 qp->flags & MLX5_IB_QP_UNDERLAY) {
2939 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2940
2941 raw_qp_param.operation = op;
2942 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2943 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2944 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2945 }
2946
2947 if (attr_mask & IB_QP_RATE_LIMIT) {
2948 raw_qp_param.rate_limit = attr->rate_limit;
2949 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2950 }
2951
2952 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2953 } else {
2954 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2955 &base->mqp);
2956 }
2957
2958 if (err)
2959 goto out;
2960
2961 qp->state = new_state;
2962
2963 if (attr_mask & IB_QP_ACCESS_FLAGS)
2964 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2965 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2966 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2967 if (attr_mask & IB_QP_PORT)
2968 qp->port = attr->port_num;
2969 if (attr_mask & IB_QP_ALT_PATH)
2970 qp->trans_qp.alt_port = attr->alt_port_num;
2971
2972 /*
2973 * If we moved a kernel QP to RESET, clean up all old CQ
2974 * entries and reinitialize the QP.
2975 */
2976 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2977 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2978 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2979 if (send_cq != recv_cq)
2980 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2981
2982 qp->rq.head = 0;
2983 qp->rq.tail = 0;
2984 qp->sq.head = 0;
2985 qp->sq.tail = 0;
2986 qp->sq.cur_post = 0;
2987 qp->sq.last_poll = 0;
2988 qp->db.db[MLX5_RCV_DBR] = 0;
2989 qp->db.db[MLX5_SND_DBR] = 0;
2990 }
2991
2992 out:
2993 kfree(context);
2994 return err;
2995 }
2996
2997 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2998 int attr_mask, struct ib_udata *udata)
2999 {
3000 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3001 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3002 enum ib_qp_type qp_type;
3003 enum ib_qp_state cur_state, new_state;
3004 int err = -EINVAL;
3005 int port;
3006 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3007
3008 if (ibqp->rwq_ind_tbl)
3009 return -ENOSYS;
3010
3011 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3012 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3013
3014 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3015 IB_QPT_GSI : ibqp->qp_type;
3016
3017 mutex_lock(&qp->mutex);
3018
3019 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3020 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3021
3022 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3023 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3024 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3025 }
3026
3027 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3028 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3029 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3030 attr_mask);
3031 goto out;
3032 }
3033 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3034 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3035 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3036 cur_state, new_state, ibqp->qp_type, attr_mask);
3037 goto out;
3038 }
3039
3040 if ((attr_mask & IB_QP_PORT) &&
3041 (attr->port_num == 0 ||
3042 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3043 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3044 attr->port_num, dev->num_ports);
3045 goto out;
3046 }
3047
3048 if (attr_mask & IB_QP_PKEY_INDEX) {
3049 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3050 if (attr->pkey_index >=
3051 dev->mdev->port_caps[port - 1].pkey_table_len) {
3052 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3053 attr->pkey_index);
3054 goto out;
3055 }
3056 }
3057
3058 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3059 attr->max_rd_atomic >
3060 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3061 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3062 attr->max_rd_atomic);
3063 goto out;
3064 }
3065
3066 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3067 attr->max_dest_rd_atomic >
3068 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3069 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3070 attr->max_dest_rd_atomic);
3071 goto out;
3072 }
3073
3074 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3075 err = 0;
3076 goto out;
3077 }
3078
3079 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3080
3081 out:
3082 mutex_unlock(&qp->mutex);
3083 return err;
3084 }
3085
3086 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3087 {
3088 struct mlx5_ib_cq *cq;
3089 unsigned cur;
3090
3091 cur = wq->head - wq->tail;
3092 if (likely(cur + nreq < wq->max_post))
3093 return 0;
3094
3095 cq = to_mcq(ib_cq);
3096 spin_lock(&cq->lock);
3097 cur = wq->head - wq->tail;
3098 spin_unlock(&cq->lock);
3099
3100 return cur + nreq >= wq->max_post;
3101 }
3102
3103 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3104 u64 remote_addr, u32 rkey)
3105 {
3106 rseg->raddr = cpu_to_be64(remote_addr);
3107 rseg->rkey = cpu_to_be32(rkey);
3108 rseg->reserved = 0;
3109 }
3110
3111 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3112 struct ib_send_wr *wr, void *qend,
3113 struct mlx5_ib_qp *qp, int *size)
3114 {
3115 void *seg = eseg;
3116
3117 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3118
3119 if (wr->send_flags & IB_SEND_IP_CSUM)
3120 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3121 MLX5_ETH_WQE_L4_CSUM;
3122
3123 seg += sizeof(struct mlx5_wqe_eth_seg);
3124 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3125
3126 if (wr->opcode == IB_WR_LSO) {
3127 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3128 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3129 u64 left, leftlen, copysz;
3130 void *pdata = ud_wr->header;
3131
3132 left = ud_wr->hlen;
3133 eseg->mss = cpu_to_be16(ud_wr->mss);
3134 eseg->inline_hdr.sz = cpu_to_be16(left);
3135
3136 /*
3137 * check if there is space till the end of queue, if yes,
3138 * copy all in one shot, otherwise copy till the end of queue,
3139 * rollback and than the copy the left
3140 */
3141 leftlen = qend - (void *)eseg->inline_hdr.start;
3142 copysz = min_t(u64, leftlen, left);
3143
3144 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3145
3146 if (likely(copysz > size_of_inl_hdr_start)) {
3147 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3148 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3149 }
3150
3151 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3152 seg = mlx5_get_send_wqe(qp, 0);
3153 left -= copysz;
3154 pdata += copysz;
3155 memcpy(seg, pdata, left);
3156 seg += ALIGN(left, 16);
3157 *size += ALIGN(left, 16) / 16;
3158 }
3159 }
3160
3161 return seg;
3162 }
3163
3164 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3165 struct ib_send_wr *wr)
3166 {
3167 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3168 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3169 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3170 }
3171
3172 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3173 {
3174 dseg->byte_count = cpu_to_be32(sg->length);
3175 dseg->lkey = cpu_to_be32(sg->lkey);
3176 dseg->addr = cpu_to_be64(sg->addr);
3177 }
3178
3179 static u64 get_xlt_octo(u64 bytes)
3180 {
3181 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3182 MLX5_IB_UMR_OCTOWORD;
3183 }
3184
3185 static __be64 frwr_mkey_mask(void)
3186 {
3187 u64 result;
3188
3189 result = MLX5_MKEY_MASK_LEN |
3190 MLX5_MKEY_MASK_PAGE_SIZE |
3191 MLX5_MKEY_MASK_START_ADDR |
3192 MLX5_MKEY_MASK_EN_RINVAL |
3193 MLX5_MKEY_MASK_KEY |
3194 MLX5_MKEY_MASK_LR |
3195 MLX5_MKEY_MASK_LW |
3196 MLX5_MKEY_MASK_RR |
3197 MLX5_MKEY_MASK_RW |
3198 MLX5_MKEY_MASK_A |
3199 MLX5_MKEY_MASK_SMALL_FENCE |
3200 MLX5_MKEY_MASK_FREE;
3201
3202 return cpu_to_be64(result);
3203 }
3204
3205 static __be64 sig_mkey_mask(void)
3206 {
3207 u64 result;
3208
3209 result = MLX5_MKEY_MASK_LEN |
3210 MLX5_MKEY_MASK_PAGE_SIZE |
3211 MLX5_MKEY_MASK_START_ADDR |
3212 MLX5_MKEY_MASK_EN_SIGERR |
3213 MLX5_MKEY_MASK_EN_RINVAL |
3214 MLX5_MKEY_MASK_KEY |
3215 MLX5_MKEY_MASK_LR |
3216 MLX5_MKEY_MASK_LW |
3217 MLX5_MKEY_MASK_RR |
3218 MLX5_MKEY_MASK_RW |
3219 MLX5_MKEY_MASK_SMALL_FENCE |
3220 MLX5_MKEY_MASK_FREE |
3221 MLX5_MKEY_MASK_BSF_EN;
3222
3223 return cpu_to_be64(result);
3224 }
3225
3226 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3227 struct mlx5_ib_mr *mr)
3228 {
3229 int size = mr->ndescs * mr->desc_size;
3230
3231 memset(umr, 0, sizeof(*umr));
3232
3233 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3234 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3235 umr->mkey_mask = frwr_mkey_mask();
3236 }
3237
3238 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3239 {
3240 memset(umr, 0, sizeof(*umr));
3241 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3242 umr->flags = MLX5_UMR_INLINE;
3243 }
3244
3245 static __be64 get_umr_enable_mr_mask(void)
3246 {
3247 u64 result;
3248
3249 result = MLX5_MKEY_MASK_KEY |
3250 MLX5_MKEY_MASK_FREE;
3251
3252 return cpu_to_be64(result);
3253 }
3254
3255 static __be64 get_umr_disable_mr_mask(void)
3256 {
3257 u64 result;
3258
3259 result = MLX5_MKEY_MASK_FREE;
3260
3261 return cpu_to_be64(result);
3262 }
3263
3264 static __be64 get_umr_update_translation_mask(void)
3265 {
3266 u64 result;
3267
3268 result = MLX5_MKEY_MASK_LEN |
3269 MLX5_MKEY_MASK_PAGE_SIZE |
3270 MLX5_MKEY_MASK_START_ADDR;
3271
3272 return cpu_to_be64(result);
3273 }
3274
3275 static __be64 get_umr_update_access_mask(int atomic)
3276 {
3277 u64 result;
3278
3279 result = MLX5_MKEY_MASK_LR |
3280 MLX5_MKEY_MASK_LW |
3281 MLX5_MKEY_MASK_RR |
3282 MLX5_MKEY_MASK_RW;
3283
3284 if (atomic)
3285 result |= MLX5_MKEY_MASK_A;
3286
3287 return cpu_to_be64(result);
3288 }
3289
3290 static __be64 get_umr_update_pd_mask(void)
3291 {
3292 u64 result;
3293
3294 result = MLX5_MKEY_MASK_PD;
3295
3296 return cpu_to_be64(result);
3297 }
3298
3299 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3300 struct ib_send_wr *wr, int atomic)
3301 {
3302 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3303
3304 memset(umr, 0, sizeof(*umr));
3305
3306 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3307 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3308 else
3309 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3310
3311 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3312 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3313 u64 offset = get_xlt_octo(umrwr->offset);
3314
3315 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3316 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3317 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3318 }
3319 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3320 umr->mkey_mask |= get_umr_update_translation_mask();
3321 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3322 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3323 umr->mkey_mask |= get_umr_update_pd_mask();
3324 }
3325 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3326 umr->mkey_mask |= get_umr_enable_mr_mask();
3327 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3328 umr->mkey_mask |= get_umr_disable_mr_mask();
3329
3330 if (!wr->num_sge)
3331 umr->flags |= MLX5_UMR_INLINE;
3332 }
3333
3334 static u8 get_umr_flags(int acc)
3335 {
3336 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3337 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3338 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3339 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3340 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3341 }
3342
3343 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3344 struct mlx5_ib_mr *mr,
3345 u32 key, int access)
3346 {
3347 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3348
3349 memset(seg, 0, sizeof(*seg));
3350
3351 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3352 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3353 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3354 /* KLMs take twice the size of MTTs */
3355 ndescs *= 2;
3356
3357 seg->flags = get_umr_flags(access) | mr->access_mode;
3358 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3359 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3360 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3361 seg->len = cpu_to_be64(mr->ibmr.length);
3362 seg->xlt_oct_size = cpu_to_be32(ndescs);
3363 }
3364
3365 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3366 {
3367 memset(seg, 0, sizeof(*seg));
3368 seg->status = MLX5_MKEY_STATUS_FREE;
3369 }
3370
3371 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3372 {
3373 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3374
3375 memset(seg, 0, sizeof(*seg));
3376 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3377 seg->status = MLX5_MKEY_STATUS_FREE;
3378
3379 seg->flags = convert_access(umrwr->access_flags);
3380 if (umrwr->pd)
3381 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3382 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3383 !umrwr->length)
3384 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3385
3386 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3387 seg->len = cpu_to_be64(umrwr->length);
3388 seg->log2_page_size = umrwr->page_shift;
3389 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3390 mlx5_mkey_variant(umrwr->mkey));
3391 }
3392
3393 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3394 struct mlx5_ib_mr *mr,
3395 struct mlx5_ib_pd *pd)
3396 {
3397 int bcount = mr->desc_size * mr->ndescs;
3398
3399 dseg->addr = cpu_to_be64(mr->desc_map);
3400 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3401 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3402 }
3403
3404 static __be32 send_ieth(struct ib_send_wr *wr)
3405 {
3406 switch (wr->opcode) {
3407 case IB_WR_SEND_WITH_IMM:
3408 case IB_WR_RDMA_WRITE_WITH_IMM:
3409 return wr->ex.imm_data;
3410
3411 case IB_WR_SEND_WITH_INV:
3412 return cpu_to_be32(wr->ex.invalidate_rkey);
3413
3414 default:
3415 return 0;
3416 }
3417 }
3418
3419 static u8 calc_sig(void *wqe, int size)
3420 {
3421 u8 *p = wqe;
3422 u8 res = 0;
3423 int i;
3424
3425 for (i = 0; i < size; i++)
3426 res ^= p[i];
3427
3428 return ~res;
3429 }
3430
3431 static u8 wq_sig(void *wqe)
3432 {
3433 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3434 }
3435
3436 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3437 void *wqe, int *sz)
3438 {
3439 struct mlx5_wqe_inline_seg *seg;
3440 void *qend = qp->sq.qend;
3441 void *addr;
3442 int inl = 0;
3443 int copy;
3444 int len;
3445 int i;
3446
3447 seg = wqe;
3448 wqe += sizeof(*seg);
3449 for (i = 0; i < wr->num_sge; i++) {
3450 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3451 len = wr->sg_list[i].length;
3452 inl += len;
3453
3454 if (unlikely(inl > qp->max_inline_data))
3455 return -ENOMEM;
3456
3457 if (unlikely(wqe + len > qend)) {
3458 copy = qend - wqe;
3459 memcpy(wqe, addr, copy);
3460 addr += copy;
3461 len -= copy;
3462 wqe = mlx5_get_send_wqe(qp, 0);
3463 }
3464 memcpy(wqe, addr, len);
3465 wqe += len;
3466 }
3467
3468 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3469
3470 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3471
3472 return 0;
3473 }
3474
3475 static u16 prot_field_size(enum ib_signature_type type)
3476 {
3477 switch (type) {
3478 case IB_SIG_TYPE_T10_DIF:
3479 return MLX5_DIF_SIZE;
3480 default:
3481 return 0;
3482 }
3483 }
3484
3485 static u8 bs_selector(int block_size)
3486 {
3487 switch (block_size) {
3488 case 512: return 0x1;
3489 case 520: return 0x2;
3490 case 4096: return 0x3;
3491 case 4160: return 0x4;
3492 case 1073741824: return 0x5;
3493 default: return 0;
3494 }
3495 }
3496
3497 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3498 struct mlx5_bsf_inl *inl)
3499 {
3500 /* Valid inline section and allow BSF refresh */
3501 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3502 MLX5_BSF_REFRESH_DIF);
3503 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3504 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3505 /* repeating block */
3506 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3507 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3508 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3509
3510 if (domain->sig.dif.ref_remap)
3511 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3512
3513 if (domain->sig.dif.app_escape) {
3514 if (domain->sig.dif.ref_escape)
3515 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3516 else
3517 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3518 }
3519
3520 inl->dif_app_bitmask_check =
3521 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3522 }
3523
3524 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3525 struct ib_sig_attrs *sig_attrs,
3526 struct mlx5_bsf *bsf, u32 data_size)
3527 {
3528 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3529 struct mlx5_bsf_basic *basic = &bsf->basic;
3530 struct ib_sig_domain *mem = &sig_attrs->mem;
3531 struct ib_sig_domain *wire = &sig_attrs->wire;
3532
3533 memset(bsf, 0, sizeof(*bsf));
3534
3535 /* Basic + Extended + Inline */
3536 basic->bsf_size_sbs = 1 << 7;
3537 /* Input domain check byte mask */
3538 basic->check_byte_mask = sig_attrs->check_mask;
3539 basic->raw_data_size = cpu_to_be32(data_size);
3540
3541 /* Memory domain */
3542 switch (sig_attrs->mem.sig_type) {
3543 case IB_SIG_TYPE_NONE:
3544 break;
3545 case IB_SIG_TYPE_T10_DIF:
3546 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3547 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3548 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3549 break;
3550 default:
3551 return -EINVAL;
3552 }
3553
3554 /* Wire domain */
3555 switch (sig_attrs->wire.sig_type) {
3556 case IB_SIG_TYPE_NONE:
3557 break;
3558 case IB_SIG_TYPE_T10_DIF:
3559 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3560 mem->sig_type == wire->sig_type) {
3561 /* Same block structure */
3562 basic->bsf_size_sbs |= 1 << 4;
3563 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3564 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3565 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3566 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3567 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3568 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3569 } else
3570 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3571
3572 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3573 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3574 break;
3575 default:
3576 return -EINVAL;
3577 }
3578
3579 return 0;
3580 }
3581
3582 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3583 struct mlx5_ib_qp *qp, void **seg, int *size)
3584 {
3585 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3586 struct ib_mr *sig_mr = wr->sig_mr;
3587 struct mlx5_bsf *bsf;
3588 u32 data_len = wr->wr.sg_list->length;
3589 u32 data_key = wr->wr.sg_list->lkey;
3590 u64 data_va = wr->wr.sg_list->addr;
3591 int ret;
3592 int wqe_size;
3593
3594 if (!wr->prot ||
3595 (data_key == wr->prot->lkey &&
3596 data_va == wr->prot->addr &&
3597 data_len == wr->prot->length)) {
3598 /**
3599 * Source domain doesn't contain signature information
3600 * or data and protection are interleaved in memory.
3601 * So need construct:
3602 * ------------------
3603 * | data_klm |
3604 * ------------------
3605 * | BSF |
3606 * ------------------
3607 **/
3608 struct mlx5_klm *data_klm = *seg;
3609
3610 data_klm->bcount = cpu_to_be32(data_len);
3611 data_klm->key = cpu_to_be32(data_key);
3612 data_klm->va = cpu_to_be64(data_va);
3613 wqe_size = ALIGN(sizeof(*data_klm), 64);
3614 } else {
3615 /**
3616 * Source domain contains signature information
3617 * So need construct a strided block format:
3618 * ---------------------------
3619 * | stride_block_ctrl |
3620 * ---------------------------
3621 * | data_klm |
3622 * ---------------------------
3623 * | prot_klm |
3624 * ---------------------------
3625 * | BSF |
3626 * ---------------------------
3627 **/
3628 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3629 struct mlx5_stride_block_entry *data_sentry;
3630 struct mlx5_stride_block_entry *prot_sentry;
3631 u32 prot_key = wr->prot->lkey;
3632 u64 prot_va = wr->prot->addr;
3633 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3634 int prot_size;
3635
3636 sblock_ctrl = *seg;
3637 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3638 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3639
3640 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3641 if (!prot_size) {
3642 pr_err("Bad block size given: %u\n", block_size);
3643 return -EINVAL;
3644 }
3645 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3646 prot_size);
3647 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3648 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3649 sblock_ctrl->num_entries = cpu_to_be16(2);
3650
3651 data_sentry->bcount = cpu_to_be16(block_size);
3652 data_sentry->key = cpu_to_be32(data_key);
3653 data_sentry->va = cpu_to_be64(data_va);
3654 data_sentry->stride = cpu_to_be16(block_size);
3655
3656 prot_sentry->bcount = cpu_to_be16(prot_size);
3657 prot_sentry->key = cpu_to_be32(prot_key);
3658 prot_sentry->va = cpu_to_be64(prot_va);
3659 prot_sentry->stride = cpu_to_be16(prot_size);
3660
3661 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3662 sizeof(*prot_sentry), 64);
3663 }
3664
3665 *seg += wqe_size;
3666 *size += wqe_size / 16;
3667 if (unlikely((*seg == qp->sq.qend)))
3668 *seg = mlx5_get_send_wqe(qp, 0);
3669
3670 bsf = *seg;
3671 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3672 if (ret)
3673 return -EINVAL;
3674
3675 *seg += sizeof(*bsf);
3676 *size += sizeof(*bsf) / 16;
3677 if (unlikely((*seg == qp->sq.qend)))
3678 *seg = mlx5_get_send_wqe(qp, 0);
3679
3680 return 0;
3681 }
3682
3683 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3684 struct ib_sig_handover_wr *wr, u32 size,
3685 u32 length, u32 pdn)
3686 {
3687 struct ib_mr *sig_mr = wr->sig_mr;
3688 u32 sig_key = sig_mr->rkey;
3689 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3690
3691 memset(seg, 0, sizeof(*seg));
3692
3693 seg->flags = get_umr_flags(wr->access_flags) |
3694 MLX5_MKC_ACCESS_MODE_KLMS;
3695 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3696 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3697 MLX5_MKEY_BSF_EN | pdn);
3698 seg->len = cpu_to_be64(length);
3699 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3700 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3701 }
3702
3703 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3704 u32 size)
3705 {
3706 memset(umr, 0, sizeof(*umr));
3707
3708 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3709 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3710 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3711 umr->mkey_mask = sig_mkey_mask();
3712 }
3713
3714
3715 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3716 void **seg, int *size)
3717 {
3718 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3719 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3720 u32 pdn = get_pd(qp)->pdn;
3721 u32 xlt_size;
3722 int region_len, ret;
3723
3724 if (unlikely(wr->wr.num_sge != 1) ||
3725 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3726 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3727 unlikely(!sig_mr->sig->sig_status_checked))
3728 return -EINVAL;
3729
3730 /* length of the protected region, data + protection */
3731 region_len = wr->wr.sg_list->length;
3732 if (wr->prot &&
3733 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3734 wr->prot->addr != wr->wr.sg_list->addr ||
3735 wr->prot->length != wr->wr.sg_list->length))
3736 region_len += wr->prot->length;
3737
3738 /**
3739 * KLM octoword size - if protection was provided
3740 * then we use strided block format (3 octowords),
3741 * else we use single KLM (1 octoword)
3742 **/
3743 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3744
3745 set_sig_umr_segment(*seg, xlt_size);
3746 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3747 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3748 if (unlikely((*seg == qp->sq.qend)))
3749 *seg = mlx5_get_send_wqe(qp, 0);
3750
3751 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3752 *seg += sizeof(struct mlx5_mkey_seg);
3753 *size += sizeof(struct mlx5_mkey_seg) / 16;
3754 if (unlikely((*seg == qp->sq.qend)))
3755 *seg = mlx5_get_send_wqe(qp, 0);
3756
3757 ret = set_sig_data_segment(wr, qp, seg, size);
3758 if (ret)
3759 return ret;
3760
3761 sig_mr->sig->sig_status_checked = false;
3762 return 0;
3763 }
3764
3765 static int set_psv_wr(struct ib_sig_domain *domain,
3766 u32 psv_idx, void **seg, int *size)
3767 {
3768 struct mlx5_seg_set_psv *psv_seg = *seg;
3769
3770 memset(psv_seg, 0, sizeof(*psv_seg));
3771 psv_seg->psv_num = cpu_to_be32(psv_idx);
3772 switch (domain->sig_type) {
3773 case IB_SIG_TYPE_NONE:
3774 break;
3775 case IB_SIG_TYPE_T10_DIF:
3776 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3777 domain->sig.dif.app_tag);
3778 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3779 break;
3780 default:
3781 pr_err("Bad signature type (%d) is given.\n",
3782 domain->sig_type);
3783 return -EINVAL;
3784 }
3785
3786 *seg += sizeof(*psv_seg);
3787 *size += sizeof(*psv_seg) / 16;
3788
3789 return 0;
3790 }
3791
3792 static int set_reg_wr(struct mlx5_ib_qp *qp,
3793 struct ib_reg_wr *wr,
3794 void **seg, int *size)
3795 {
3796 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3797 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3798
3799 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3800 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3801 "Invalid IB_SEND_INLINE send flag\n");
3802 return -EINVAL;
3803 }
3804
3805 set_reg_umr_seg(*seg, mr);
3806 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3807 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3808 if (unlikely((*seg == qp->sq.qend)))
3809 *seg = mlx5_get_send_wqe(qp, 0);
3810
3811 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3812 *seg += sizeof(struct mlx5_mkey_seg);
3813 *size += sizeof(struct mlx5_mkey_seg) / 16;
3814 if (unlikely((*seg == qp->sq.qend)))
3815 *seg = mlx5_get_send_wqe(qp, 0);
3816
3817 set_reg_data_seg(*seg, mr, pd);
3818 *seg += sizeof(struct mlx5_wqe_data_seg);
3819 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3820
3821 return 0;
3822 }
3823
3824 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3825 {
3826 set_linv_umr_seg(*seg);
3827 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3828 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3829 if (unlikely((*seg == qp->sq.qend)))
3830 *seg = mlx5_get_send_wqe(qp, 0);
3831 set_linv_mkey_seg(*seg);
3832 *seg += sizeof(struct mlx5_mkey_seg);
3833 *size += sizeof(struct mlx5_mkey_seg) / 16;
3834 if (unlikely((*seg == qp->sq.qend)))
3835 *seg = mlx5_get_send_wqe(qp, 0);
3836 }
3837
3838 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3839 {
3840 __be32 *p = NULL;
3841 int tidx = idx;
3842 int i, j;
3843
3844 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3845 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3846 if ((i & 0xf) == 0) {
3847 void *buf = mlx5_get_send_wqe(qp, tidx);
3848 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3849 p = buf;
3850 j = 0;
3851 }
3852 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3853 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3854 be32_to_cpu(p[j + 3]));
3855 }
3856 }
3857
3858 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3859 struct mlx5_wqe_ctrl_seg **ctrl,
3860 struct ib_send_wr *wr, unsigned *idx,
3861 int *size, int nreq)
3862 {
3863 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3864 return -ENOMEM;
3865
3866 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3867 *seg = mlx5_get_send_wqe(qp, *idx);
3868 *ctrl = *seg;
3869 *(uint32_t *)(*seg + 8) = 0;
3870 (*ctrl)->imm = send_ieth(wr);
3871 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3872 (wr->send_flags & IB_SEND_SIGNALED ?
3873 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3874 (wr->send_flags & IB_SEND_SOLICITED ?
3875 MLX5_WQE_CTRL_SOLICITED : 0);
3876
3877 *seg += sizeof(**ctrl);
3878 *size = sizeof(**ctrl) / 16;
3879
3880 return 0;
3881 }
3882
3883 static void finish_wqe(struct mlx5_ib_qp *qp,
3884 struct mlx5_wqe_ctrl_seg *ctrl,
3885 u8 size, unsigned idx, u64 wr_id,
3886 int nreq, u8 fence, u32 mlx5_opcode)
3887 {
3888 u8 opmod = 0;
3889
3890 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3891 mlx5_opcode | ((u32)opmod << 24));
3892 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3893 ctrl->fm_ce_se |= fence;
3894 if (unlikely(qp->wq_sig))
3895 ctrl->signature = wq_sig(ctrl);
3896
3897 qp->sq.wrid[idx] = wr_id;
3898 qp->sq.w_list[idx].opcode = mlx5_opcode;
3899 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3900 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3901 qp->sq.w_list[idx].next = qp->sq.cur_post;
3902 }
3903
3904
3905 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3906 struct ib_send_wr **bad_wr)
3907 {
3908 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3909 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3910 struct mlx5_core_dev *mdev = dev->mdev;
3911 struct mlx5_ib_qp *qp;
3912 struct mlx5_ib_mr *mr;
3913 struct mlx5_wqe_data_seg *dpseg;
3914 struct mlx5_wqe_xrc_seg *xrc;
3915 struct mlx5_bf *bf;
3916 int uninitialized_var(size);
3917 void *qend;
3918 unsigned long flags;
3919 unsigned idx;
3920 int err = 0;
3921 int num_sge;
3922 void *seg;
3923 int nreq;
3924 int i;
3925 u8 next_fence = 0;
3926 u8 fence;
3927
3928 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3929 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3930
3931 qp = to_mqp(ibqp);
3932 bf = &qp->bf;
3933 qend = qp->sq.qend;
3934
3935 spin_lock_irqsave(&qp->sq.lock, flags);
3936
3937 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3938 err = -EIO;
3939 *bad_wr = wr;
3940 nreq = 0;
3941 goto out;
3942 }
3943
3944 for (nreq = 0; wr; nreq++, wr = wr->next) {
3945 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3946 mlx5_ib_warn(dev, "\n");
3947 err = -EINVAL;
3948 *bad_wr = wr;
3949 goto out;
3950 }
3951
3952 num_sge = wr->num_sge;
3953 if (unlikely(num_sge > qp->sq.max_gs)) {
3954 mlx5_ib_warn(dev, "\n");
3955 err = -EINVAL;
3956 *bad_wr = wr;
3957 goto out;
3958 }
3959
3960 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3961 if (err) {
3962 mlx5_ib_warn(dev, "\n");
3963 err = -ENOMEM;
3964 *bad_wr = wr;
3965 goto out;
3966 }
3967
3968 if (wr->opcode == IB_WR_LOCAL_INV ||
3969 wr->opcode == IB_WR_REG_MR) {
3970 fence = dev->umr_fence;
3971 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3972 } else if (wr->send_flags & IB_SEND_FENCE) {
3973 if (qp->next_fence)
3974 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3975 else
3976 fence = MLX5_FENCE_MODE_FENCE;
3977 } else {
3978 fence = qp->next_fence;
3979 }
3980
3981 switch (ibqp->qp_type) {
3982 case IB_QPT_XRC_INI:
3983 xrc = seg;
3984 seg += sizeof(*xrc);
3985 size += sizeof(*xrc) / 16;
3986 /* fall through */
3987 case IB_QPT_RC:
3988 switch (wr->opcode) {
3989 case IB_WR_RDMA_READ:
3990 case IB_WR_RDMA_WRITE:
3991 case IB_WR_RDMA_WRITE_WITH_IMM:
3992 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3993 rdma_wr(wr)->rkey);
3994 seg += sizeof(struct mlx5_wqe_raddr_seg);
3995 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3996 break;
3997
3998 case IB_WR_ATOMIC_CMP_AND_SWP:
3999 case IB_WR_ATOMIC_FETCH_AND_ADD:
4000 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4001 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4002 err = -ENOSYS;
4003 *bad_wr = wr;
4004 goto out;
4005
4006 case IB_WR_LOCAL_INV:
4007 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4008 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4009 set_linv_wr(qp, &seg, &size);
4010 num_sge = 0;
4011 break;
4012
4013 case IB_WR_REG_MR:
4014 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4015 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4016 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4017 if (err) {
4018 *bad_wr = wr;
4019 goto out;
4020 }
4021 num_sge = 0;
4022 break;
4023
4024 case IB_WR_REG_SIG_MR:
4025 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4026 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4027
4028 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4029 err = set_sig_umr_wr(wr, qp, &seg, &size);
4030 if (err) {
4031 mlx5_ib_warn(dev, "\n");
4032 *bad_wr = wr;
4033 goto out;
4034 }
4035
4036 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4037 fence, MLX5_OPCODE_UMR);
4038 /*
4039 * SET_PSV WQEs are not signaled and solicited
4040 * on error
4041 */
4042 wr->send_flags &= ~IB_SEND_SIGNALED;
4043 wr->send_flags |= IB_SEND_SOLICITED;
4044 err = begin_wqe(qp, &seg, &ctrl, wr,
4045 &idx, &size, nreq);
4046 if (err) {
4047 mlx5_ib_warn(dev, "\n");
4048 err = -ENOMEM;
4049 *bad_wr = wr;
4050 goto out;
4051 }
4052
4053 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4054 mr->sig->psv_memory.psv_idx, &seg,
4055 &size);
4056 if (err) {
4057 mlx5_ib_warn(dev, "\n");
4058 *bad_wr = wr;
4059 goto out;
4060 }
4061
4062 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4063 fence, MLX5_OPCODE_SET_PSV);
4064 err = begin_wqe(qp, &seg, &ctrl, wr,
4065 &idx, &size, nreq);
4066 if (err) {
4067 mlx5_ib_warn(dev, "\n");
4068 err = -ENOMEM;
4069 *bad_wr = wr;
4070 goto out;
4071 }
4072
4073 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4074 mr->sig->psv_wire.psv_idx, &seg,
4075 &size);
4076 if (err) {
4077 mlx5_ib_warn(dev, "\n");
4078 *bad_wr = wr;
4079 goto out;
4080 }
4081
4082 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4083 fence, MLX5_OPCODE_SET_PSV);
4084 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4085 num_sge = 0;
4086 goto skip_psv;
4087
4088 default:
4089 break;
4090 }
4091 break;
4092
4093 case IB_QPT_UC:
4094 switch (wr->opcode) {
4095 case IB_WR_RDMA_WRITE:
4096 case IB_WR_RDMA_WRITE_WITH_IMM:
4097 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4098 rdma_wr(wr)->rkey);
4099 seg += sizeof(struct mlx5_wqe_raddr_seg);
4100 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4101 break;
4102
4103 default:
4104 break;
4105 }
4106 break;
4107
4108 case IB_QPT_SMI:
4109 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4110 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4111 err = -EPERM;
4112 *bad_wr = wr;
4113 goto out;
4114 }
4115 /* fall through */
4116 case MLX5_IB_QPT_HW_GSI:
4117 set_datagram_seg(seg, wr);
4118 seg += sizeof(struct mlx5_wqe_datagram_seg);
4119 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4120 if (unlikely((seg == qend)))
4121 seg = mlx5_get_send_wqe(qp, 0);
4122 break;
4123 case IB_QPT_UD:
4124 set_datagram_seg(seg, wr);
4125 seg += sizeof(struct mlx5_wqe_datagram_seg);
4126 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4127
4128 if (unlikely((seg == qend)))
4129 seg = mlx5_get_send_wqe(qp, 0);
4130
4131 /* handle qp that supports ud offload */
4132 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4133 struct mlx5_wqe_eth_pad *pad;
4134
4135 pad = seg;
4136 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4137 seg += sizeof(struct mlx5_wqe_eth_pad);
4138 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4139
4140 seg = set_eth_seg(seg, wr, qend, qp, &size);
4141
4142 if (unlikely((seg == qend)))
4143 seg = mlx5_get_send_wqe(qp, 0);
4144 }
4145 break;
4146 case MLX5_IB_QPT_REG_UMR:
4147 if (wr->opcode != MLX5_IB_WR_UMR) {
4148 err = -EINVAL;
4149 mlx5_ib_warn(dev, "bad opcode\n");
4150 goto out;
4151 }
4152 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4153 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4154 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4155 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4156 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4157 if (unlikely((seg == qend)))
4158 seg = mlx5_get_send_wqe(qp, 0);
4159 set_reg_mkey_segment(seg, wr);
4160 seg += sizeof(struct mlx5_mkey_seg);
4161 size += sizeof(struct mlx5_mkey_seg) / 16;
4162 if (unlikely((seg == qend)))
4163 seg = mlx5_get_send_wqe(qp, 0);
4164 break;
4165
4166 default:
4167 break;
4168 }
4169
4170 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4171 int uninitialized_var(sz);
4172
4173 err = set_data_inl_seg(qp, wr, seg, &sz);
4174 if (unlikely(err)) {
4175 mlx5_ib_warn(dev, "\n");
4176 *bad_wr = wr;
4177 goto out;
4178 }
4179 size += sz;
4180 } else {
4181 dpseg = seg;
4182 for (i = 0; i < num_sge; i++) {
4183 if (unlikely(dpseg == qend)) {
4184 seg = mlx5_get_send_wqe(qp, 0);
4185 dpseg = seg;
4186 }
4187 if (likely(wr->sg_list[i].length)) {
4188 set_data_ptr_seg(dpseg, wr->sg_list + i);
4189 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4190 dpseg++;
4191 }
4192 }
4193 }
4194
4195 qp->next_fence = next_fence;
4196 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4197 mlx5_ib_opcode[wr->opcode]);
4198 skip_psv:
4199 if (0)
4200 dump_wqe(qp, idx, size);
4201 }
4202
4203 out:
4204 if (likely(nreq)) {
4205 qp->sq.head += nreq;
4206
4207 /* Make sure that descriptors are written before
4208 * updating doorbell record and ringing the doorbell
4209 */
4210 wmb();
4211
4212 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4213
4214 /* Make sure doorbell record is visible to the HCA before
4215 * we hit doorbell */
4216 wmb();
4217
4218 /* currently we support only regular doorbells */
4219 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4220 /* Make sure doorbells don't leak out of SQ spinlock
4221 * and reach the HCA out of order.
4222 */
4223 mmiowb();
4224 bf->offset ^= bf->buf_size;
4225 }
4226
4227 spin_unlock_irqrestore(&qp->sq.lock, flags);
4228
4229 return err;
4230 }
4231
4232 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4233 {
4234 sig->signature = calc_sig(sig, size);
4235 }
4236
4237 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4238 struct ib_recv_wr **bad_wr)
4239 {
4240 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4241 struct mlx5_wqe_data_seg *scat;
4242 struct mlx5_rwqe_sig *sig;
4243 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4244 struct mlx5_core_dev *mdev = dev->mdev;
4245 unsigned long flags;
4246 int err = 0;
4247 int nreq;
4248 int ind;
4249 int i;
4250
4251 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4252 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4253
4254 spin_lock_irqsave(&qp->rq.lock, flags);
4255
4256 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4257 err = -EIO;
4258 *bad_wr = wr;
4259 nreq = 0;
4260 goto out;
4261 }
4262
4263 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4264
4265 for (nreq = 0; wr; nreq++, wr = wr->next) {
4266 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4267 err = -ENOMEM;
4268 *bad_wr = wr;
4269 goto out;
4270 }
4271
4272 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4273 err = -EINVAL;
4274 *bad_wr = wr;
4275 goto out;
4276 }
4277
4278 scat = get_recv_wqe(qp, ind);
4279 if (qp->wq_sig)
4280 scat++;
4281
4282 for (i = 0; i < wr->num_sge; i++)
4283 set_data_ptr_seg(scat + i, wr->sg_list + i);
4284
4285 if (i < qp->rq.max_gs) {
4286 scat[i].byte_count = 0;
4287 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4288 scat[i].addr = 0;
4289 }
4290
4291 if (qp->wq_sig) {
4292 sig = (struct mlx5_rwqe_sig *)scat;
4293 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4294 }
4295
4296 qp->rq.wrid[ind] = wr->wr_id;
4297
4298 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4299 }
4300
4301 out:
4302 if (likely(nreq)) {
4303 qp->rq.head += nreq;
4304
4305 /* Make sure that descriptors are written before
4306 * doorbell record.
4307 */
4308 wmb();
4309
4310 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4311 }
4312
4313 spin_unlock_irqrestore(&qp->rq.lock, flags);
4314
4315 return err;
4316 }
4317
4318 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4319 {
4320 switch (mlx5_state) {
4321 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4322 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4323 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4324 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4325 case MLX5_QP_STATE_SQ_DRAINING:
4326 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4327 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4328 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4329 default: return -1;
4330 }
4331 }
4332
4333 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4334 {
4335 switch (mlx5_mig_state) {
4336 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4337 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4338 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4339 default: return -1;
4340 }
4341 }
4342
4343 static int to_ib_qp_access_flags(int mlx5_flags)
4344 {
4345 int ib_flags = 0;
4346
4347 if (mlx5_flags & MLX5_QP_BIT_RRE)
4348 ib_flags |= IB_ACCESS_REMOTE_READ;
4349 if (mlx5_flags & MLX5_QP_BIT_RWE)
4350 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4351 if (mlx5_flags & MLX5_QP_BIT_RAE)
4352 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4353
4354 return ib_flags;
4355 }
4356
4357 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4358 struct rdma_ah_attr *ah_attr,
4359 struct mlx5_qp_path *path)
4360 {
4361 struct mlx5_core_dev *dev = ibdev->mdev;
4362
4363 memset(ah_attr, 0, sizeof(*ah_attr));
4364
4365 if (!path->port || path->port > MLX5_CAP_GEN(dev, num_ports))
4366 return;
4367
4368 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4369
4370 rdma_ah_set_port_num(ah_attr, path->port);
4371 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4372
4373 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4374 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4375 rdma_ah_set_static_rate(ah_attr,
4376 path->static_rate ? path->static_rate - 5 : 0);
4377 if (path->grh_mlid & (1 << 7)) {
4378 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4379
4380 rdma_ah_set_grh(ah_attr, NULL,
4381 tc_fl & 0xfffff,
4382 path->mgid_index,
4383 path->hop_limit,
4384 (tc_fl >> 20) & 0xff);
4385 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4386 }
4387 }
4388
4389 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4390 struct mlx5_ib_sq *sq,
4391 u8 *sq_state)
4392 {
4393 void *out;
4394 void *sqc;
4395 int inlen;
4396 int err;
4397
4398 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4399 out = kvzalloc(inlen, GFP_KERNEL);
4400 if (!out)
4401 return -ENOMEM;
4402
4403 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4404 if (err)
4405 goto out;
4406
4407 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4408 *sq_state = MLX5_GET(sqc, sqc, state);
4409 sq->state = *sq_state;
4410
4411 out:
4412 kvfree(out);
4413 return err;
4414 }
4415
4416 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4417 struct mlx5_ib_rq *rq,
4418 u8 *rq_state)
4419 {
4420 void *out;
4421 void *rqc;
4422 int inlen;
4423 int err;
4424
4425 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4426 out = kvzalloc(inlen, GFP_KERNEL);
4427 if (!out)
4428 return -ENOMEM;
4429
4430 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4431 if (err)
4432 goto out;
4433
4434 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4435 *rq_state = MLX5_GET(rqc, rqc, state);
4436 rq->state = *rq_state;
4437
4438 out:
4439 kvfree(out);
4440 return err;
4441 }
4442
4443 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4444 struct mlx5_ib_qp *qp, u8 *qp_state)
4445 {
4446 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4447 [MLX5_RQC_STATE_RST] = {
4448 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4449 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4450 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4451 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4452 },
4453 [MLX5_RQC_STATE_RDY] = {
4454 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4455 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4456 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4457 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4458 },
4459 [MLX5_RQC_STATE_ERR] = {
4460 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4461 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4462 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4463 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4464 },
4465 [MLX5_RQ_STATE_NA] = {
4466 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4467 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4468 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4469 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4470 },
4471 };
4472
4473 *qp_state = sqrq_trans[rq_state][sq_state];
4474
4475 if (*qp_state == MLX5_QP_STATE_BAD) {
4476 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4477 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4478 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4479 return -EINVAL;
4480 }
4481
4482 if (*qp_state == MLX5_QP_STATE)
4483 *qp_state = qp->state;
4484
4485 return 0;
4486 }
4487
4488 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4489 struct mlx5_ib_qp *qp,
4490 u8 *raw_packet_qp_state)
4491 {
4492 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4493 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4494 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4495 int err;
4496 u8 sq_state = MLX5_SQ_STATE_NA;
4497 u8 rq_state = MLX5_RQ_STATE_NA;
4498
4499 if (qp->sq.wqe_cnt) {
4500 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4501 if (err)
4502 return err;
4503 }
4504
4505 if (qp->rq.wqe_cnt) {
4506 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4507 if (err)
4508 return err;
4509 }
4510
4511 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4512 raw_packet_qp_state);
4513 }
4514
4515 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4516 struct ib_qp_attr *qp_attr)
4517 {
4518 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4519 struct mlx5_qp_context *context;
4520 int mlx5_state;
4521 u32 *outb;
4522 int err = 0;
4523
4524 outb = kzalloc(outlen, GFP_KERNEL);
4525 if (!outb)
4526 return -ENOMEM;
4527
4528 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4529 outlen);
4530 if (err)
4531 goto out;
4532
4533 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4534 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4535
4536 mlx5_state = be32_to_cpu(context->flags) >> 28;
4537
4538 qp->state = to_ib_qp_state(mlx5_state);
4539 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4540 qp_attr->path_mig_state =
4541 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4542 qp_attr->qkey = be32_to_cpu(context->qkey);
4543 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4544 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4545 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4546 qp_attr->qp_access_flags =
4547 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4548
4549 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4550 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4551 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4552 qp_attr->alt_pkey_index =
4553 be16_to_cpu(context->alt_path.pkey_index);
4554 qp_attr->alt_port_num =
4555 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4556 }
4557
4558 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4559 qp_attr->port_num = context->pri_path.port;
4560
4561 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4562 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4563
4564 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4565
4566 qp_attr->max_dest_rd_atomic =
4567 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4568 qp_attr->min_rnr_timer =
4569 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4570 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4571 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4572 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4573 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4574
4575 out:
4576 kfree(outb);
4577 return err;
4578 }
4579
4580 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4581 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4582 {
4583 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4584 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4585 int err = 0;
4586 u8 raw_packet_qp_state;
4587
4588 if (ibqp->rwq_ind_tbl)
4589 return -ENOSYS;
4590
4591 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4592 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4593 qp_init_attr);
4594
4595 /* Not all of output fields are applicable, make sure to zero them */
4596 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4597 memset(qp_attr, 0, sizeof(*qp_attr));
4598
4599 mutex_lock(&qp->mutex);
4600
4601 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4602 qp->flags & MLX5_IB_QP_UNDERLAY) {
4603 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4604 if (err)
4605 goto out;
4606 qp->state = raw_packet_qp_state;
4607 qp_attr->port_num = 1;
4608 } else {
4609 err = query_qp_attr(dev, qp, qp_attr);
4610 if (err)
4611 goto out;
4612 }
4613
4614 qp_attr->qp_state = qp->state;
4615 qp_attr->cur_qp_state = qp_attr->qp_state;
4616 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4617 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4618
4619 if (!ibqp->uobject) {
4620 qp_attr->cap.max_send_wr = qp->sq.max_post;
4621 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4622 qp_init_attr->qp_context = ibqp->qp_context;
4623 } else {
4624 qp_attr->cap.max_send_wr = 0;
4625 qp_attr->cap.max_send_sge = 0;
4626 }
4627
4628 qp_init_attr->qp_type = ibqp->qp_type;
4629 qp_init_attr->recv_cq = ibqp->recv_cq;
4630 qp_init_attr->send_cq = ibqp->send_cq;
4631 qp_init_attr->srq = ibqp->srq;
4632 qp_attr->cap.max_inline_data = qp->max_inline_data;
4633
4634 qp_init_attr->cap = qp_attr->cap;
4635
4636 qp_init_attr->create_flags = 0;
4637 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4638 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4639
4640 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4641 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4642 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4643 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4644 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4645 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4646 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4647 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4648
4649 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4650 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4651
4652 out:
4653 mutex_unlock(&qp->mutex);
4654 return err;
4655 }
4656
4657 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4658 struct ib_ucontext *context,
4659 struct ib_udata *udata)
4660 {
4661 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4662 struct mlx5_ib_xrcd *xrcd;
4663 int err;
4664
4665 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4666 return ERR_PTR(-ENOSYS);
4667
4668 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4669 if (!xrcd)
4670 return ERR_PTR(-ENOMEM);
4671
4672 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4673 if (err) {
4674 kfree(xrcd);
4675 return ERR_PTR(-ENOMEM);
4676 }
4677
4678 return &xrcd->ibxrcd;
4679 }
4680
4681 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4682 {
4683 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4684 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4685 int err;
4686
4687 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4688 if (err) {
4689 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4690 return err;
4691 }
4692
4693 kfree(xrcd);
4694
4695 return 0;
4696 }
4697
4698 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4699 {
4700 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4701 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4702 struct ib_event event;
4703
4704 if (rwq->ibwq.event_handler) {
4705 event.device = rwq->ibwq.device;
4706 event.element.wq = &rwq->ibwq;
4707 switch (type) {
4708 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4709 event.event = IB_EVENT_WQ_FATAL;
4710 break;
4711 default:
4712 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4713 return;
4714 }
4715
4716 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4717 }
4718 }
4719
4720 static int set_delay_drop(struct mlx5_ib_dev *dev)
4721 {
4722 int err = 0;
4723
4724 mutex_lock(&dev->delay_drop.lock);
4725 if (dev->delay_drop.activate)
4726 goto out;
4727
4728 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4729 if (err)
4730 goto out;
4731
4732 dev->delay_drop.activate = true;
4733 out:
4734 mutex_unlock(&dev->delay_drop.lock);
4735
4736 if (!err)
4737 atomic_inc(&dev->delay_drop.rqs_cnt);
4738 return err;
4739 }
4740
4741 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4742 struct ib_wq_init_attr *init_attr)
4743 {
4744 struct mlx5_ib_dev *dev;
4745 int has_net_offloads;
4746 __be64 *rq_pas0;
4747 void *in;
4748 void *rqc;
4749 void *wq;
4750 int inlen;
4751 int err;
4752
4753 dev = to_mdev(pd->device);
4754
4755 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4756 in = kvzalloc(inlen, GFP_KERNEL);
4757 if (!in)
4758 return -ENOMEM;
4759
4760 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4761 MLX5_SET(rqc, rqc, mem_rq_type,
4762 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4763 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4764 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4765 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4766 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4767 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4768 MLX5_SET(wq, wq, wq_type,
4769 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4770 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4771 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4772 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4773 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4774 err = -EOPNOTSUPP;
4775 goto out;
4776 } else {
4777 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4778 }
4779 }
4780 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4781 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4782 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4783 MLX5_SET(wq, wq, log_wqe_stride_size,
4784 rwq->single_stride_log_num_of_bytes -
4785 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4786 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
4787 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4788 }
4789 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4790 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4791 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4792 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4793 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4794 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4795 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4796 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4797 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4798 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4799 err = -EOPNOTSUPP;
4800 goto out;
4801 }
4802 } else {
4803 MLX5_SET(rqc, rqc, vsd, 1);
4804 }
4805 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4806 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4807 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4808 err = -EOPNOTSUPP;
4809 goto out;
4810 }
4811 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4812 }
4813 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4814 if (!(dev->ib_dev.attrs.raw_packet_caps &
4815 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4816 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4817 err = -EOPNOTSUPP;
4818 goto out;
4819 }
4820 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4821 }
4822 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4823 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4824 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4825 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4826 err = set_delay_drop(dev);
4827 if (err) {
4828 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4829 err);
4830 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4831 } else {
4832 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4833 }
4834 }
4835 out:
4836 kvfree(in);
4837 return err;
4838 }
4839
4840 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4841 struct ib_wq_init_attr *wq_init_attr,
4842 struct mlx5_ib_create_wq *ucmd,
4843 struct mlx5_ib_rwq *rwq)
4844 {
4845 /* Sanity check RQ size before proceeding */
4846 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4847 return -EINVAL;
4848
4849 if (!ucmd->rq_wqe_count)
4850 return -EINVAL;
4851
4852 rwq->wqe_count = ucmd->rq_wqe_count;
4853 rwq->wqe_shift = ucmd->rq_wqe_shift;
4854 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4855 rwq->log_rq_stride = rwq->wqe_shift;
4856 rwq->log_rq_size = ilog2(rwq->wqe_count);
4857 return 0;
4858 }
4859
4860 static int prepare_user_rq(struct ib_pd *pd,
4861 struct ib_wq_init_attr *init_attr,
4862 struct ib_udata *udata,
4863 struct mlx5_ib_rwq *rwq)
4864 {
4865 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4866 struct mlx5_ib_create_wq ucmd = {};
4867 int err;
4868 size_t required_cmd_sz;
4869
4870 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4871 + sizeof(ucmd.single_stride_log_num_of_bytes);
4872 if (udata->inlen < required_cmd_sz) {
4873 mlx5_ib_dbg(dev, "invalid inlen\n");
4874 return -EINVAL;
4875 }
4876
4877 if (udata->inlen > sizeof(ucmd) &&
4878 !ib_is_udata_cleared(udata, sizeof(ucmd),
4879 udata->inlen - sizeof(ucmd))) {
4880 mlx5_ib_dbg(dev, "inlen is not supported\n");
4881 return -EOPNOTSUPP;
4882 }
4883
4884 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4885 mlx5_ib_dbg(dev, "copy failed\n");
4886 return -EFAULT;
4887 }
4888
4889 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4890 mlx5_ib_dbg(dev, "invalid comp mask\n");
4891 return -EOPNOTSUPP;
4892 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4893 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4894 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4895 return -EOPNOTSUPP;
4896 }
4897 if ((ucmd.single_stride_log_num_of_bytes <
4898 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4899 (ucmd.single_stride_log_num_of_bytes >
4900 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4901 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4902 ucmd.single_stride_log_num_of_bytes,
4903 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4904 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4905 return -EINVAL;
4906 }
4907 if ((ucmd.single_wqe_log_num_of_strides >
4908 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4909 (ucmd.single_wqe_log_num_of_strides <
4910 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
4911 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
4912 ucmd.single_wqe_log_num_of_strides,
4913 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4914 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4915 return -EINVAL;
4916 }
4917 rwq->single_stride_log_num_of_bytes =
4918 ucmd.single_stride_log_num_of_bytes;
4919 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4920 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4921 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4922 }
4923
4924 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4925 if (err) {
4926 mlx5_ib_dbg(dev, "err %d\n", err);
4927 return err;
4928 }
4929
4930 err = create_user_rq(dev, pd, rwq, &ucmd);
4931 if (err) {
4932 mlx5_ib_dbg(dev, "err %d\n", err);
4933 if (err)
4934 return err;
4935 }
4936
4937 rwq->user_index = ucmd.user_index;
4938 return 0;
4939 }
4940
4941 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4942 struct ib_wq_init_attr *init_attr,
4943 struct ib_udata *udata)
4944 {
4945 struct mlx5_ib_dev *dev;
4946 struct mlx5_ib_rwq *rwq;
4947 struct mlx5_ib_create_wq_resp resp = {};
4948 size_t min_resp_len;
4949 int err;
4950
4951 if (!udata)
4952 return ERR_PTR(-ENOSYS);
4953
4954 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4955 if (udata->outlen && udata->outlen < min_resp_len)
4956 return ERR_PTR(-EINVAL);
4957
4958 dev = to_mdev(pd->device);
4959 switch (init_attr->wq_type) {
4960 case IB_WQT_RQ:
4961 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4962 if (!rwq)
4963 return ERR_PTR(-ENOMEM);
4964 err = prepare_user_rq(pd, init_attr, udata, rwq);
4965 if (err)
4966 goto err;
4967 err = create_rq(rwq, pd, init_attr);
4968 if (err)
4969 goto err_user_rq;
4970 break;
4971 default:
4972 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4973 init_attr->wq_type);
4974 return ERR_PTR(-EINVAL);
4975 }
4976
4977 rwq->ibwq.wq_num = rwq->core_qp.qpn;
4978 rwq->ibwq.state = IB_WQS_RESET;
4979 if (udata->outlen) {
4980 resp.response_length = offsetof(typeof(resp), response_length) +
4981 sizeof(resp.response_length);
4982 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4983 if (err)
4984 goto err_copy;
4985 }
4986
4987 rwq->core_qp.event = mlx5_ib_wq_event;
4988 rwq->ibwq.event_handler = init_attr->event_handler;
4989 return &rwq->ibwq;
4990
4991 err_copy:
4992 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4993 err_user_rq:
4994 destroy_user_rq(dev, pd, rwq);
4995 err:
4996 kfree(rwq);
4997 return ERR_PTR(err);
4998 }
4999
5000 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5001 {
5002 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5003 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5004
5005 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5006 destroy_user_rq(dev, wq->pd, rwq);
5007 kfree(rwq);
5008
5009 return 0;
5010 }
5011
5012 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5013 struct ib_rwq_ind_table_init_attr *init_attr,
5014 struct ib_udata *udata)
5015 {
5016 struct mlx5_ib_dev *dev = to_mdev(device);
5017 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5018 int sz = 1 << init_attr->log_ind_tbl_size;
5019 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5020 size_t min_resp_len;
5021 int inlen;
5022 int err;
5023 int i;
5024 u32 *in;
5025 void *rqtc;
5026
5027 if (udata->inlen > 0 &&
5028 !ib_is_udata_cleared(udata, 0,
5029 udata->inlen))
5030 return ERR_PTR(-EOPNOTSUPP);
5031
5032 if (init_attr->log_ind_tbl_size >
5033 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5034 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5035 init_attr->log_ind_tbl_size,
5036 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5037 return ERR_PTR(-EINVAL);
5038 }
5039
5040 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5041 if (udata->outlen && udata->outlen < min_resp_len)
5042 return ERR_PTR(-EINVAL);
5043
5044 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5045 if (!rwq_ind_tbl)
5046 return ERR_PTR(-ENOMEM);
5047
5048 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5049 in = kvzalloc(inlen, GFP_KERNEL);
5050 if (!in) {
5051 err = -ENOMEM;
5052 goto err;
5053 }
5054
5055 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5056
5057 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5058 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5059
5060 for (i = 0; i < sz; i++)
5061 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5062
5063 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5064 kvfree(in);
5065
5066 if (err)
5067 goto err;
5068
5069 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5070 if (udata->outlen) {
5071 resp.response_length = offsetof(typeof(resp), response_length) +
5072 sizeof(resp.response_length);
5073 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5074 if (err)
5075 goto err_copy;
5076 }
5077
5078 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5079
5080 err_copy:
5081 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5082 err:
5083 kfree(rwq_ind_tbl);
5084 return ERR_PTR(err);
5085 }
5086
5087 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5088 {
5089 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5090 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5091
5092 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5093
5094 kfree(rwq_ind_tbl);
5095 return 0;
5096 }
5097
5098 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5099 u32 wq_attr_mask, struct ib_udata *udata)
5100 {
5101 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5102 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5103 struct mlx5_ib_modify_wq ucmd = {};
5104 size_t required_cmd_sz;
5105 int curr_wq_state;
5106 int wq_state;
5107 int inlen;
5108 int err;
5109 void *rqc;
5110 void *in;
5111
5112 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5113 if (udata->inlen < required_cmd_sz)
5114 return -EINVAL;
5115
5116 if (udata->inlen > sizeof(ucmd) &&
5117 !ib_is_udata_cleared(udata, sizeof(ucmd),
5118 udata->inlen - sizeof(ucmd)))
5119 return -EOPNOTSUPP;
5120
5121 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5122 return -EFAULT;
5123
5124 if (ucmd.comp_mask || ucmd.reserved)
5125 return -EOPNOTSUPP;
5126
5127 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5128 in = kvzalloc(inlen, GFP_KERNEL);
5129 if (!in)
5130 return -ENOMEM;
5131
5132 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5133
5134 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5135 wq_attr->curr_wq_state : wq->state;
5136 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5137 wq_attr->wq_state : curr_wq_state;
5138 if (curr_wq_state == IB_WQS_ERR)
5139 curr_wq_state = MLX5_RQC_STATE_ERR;
5140 if (wq_state == IB_WQS_ERR)
5141 wq_state = MLX5_RQC_STATE_ERR;
5142 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5143 MLX5_SET(rqc, rqc, state, wq_state);
5144
5145 if (wq_attr_mask & IB_WQ_FLAGS) {
5146 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5147 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5148 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5149 mlx5_ib_dbg(dev, "VLAN offloads are not "
5150 "supported\n");
5151 err = -EOPNOTSUPP;
5152 goto out;
5153 }
5154 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5155 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5156 MLX5_SET(rqc, rqc, vsd,
5157 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5158 }
5159
5160 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5161 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5162 err = -EOPNOTSUPP;
5163 goto out;
5164 }
5165 }
5166
5167 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5168 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5169 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5170 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5171 MLX5_SET(rqc, rqc, counter_set_id,
5172 dev->port->cnts.set_id);
5173 } else
5174 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5175 dev->ib_dev.name);
5176 }
5177
5178 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5179 if (!err)
5180 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5181
5182 out:
5183 kvfree(in);
5184 return err;
5185 }
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