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[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38 #include "user.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57 };
58
59 static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
61 [IB_WR_LSO] = MLX5_OPCODE_LSO,
62 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
63 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
64 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
65 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
66 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
67 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
68 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
69 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
70 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
73 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
74 };
75
76 struct mlx5_wqe_eth_pad {
77 u8 rsvd0[16];
78 };
79
80 static void get_cqs(enum ib_qp_type qp_type,
81 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
82 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
83
84 static int is_qp0(enum ib_qp_type qp_type)
85 {
86 return qp_type == IB_QPT_SMI;
87 }
88
89 static int is_sqp(enum ib_qp_type qp_type)
90 {
91 return is_qp0(qp_type) || is_qp1(qp_type);
92 }
93
94 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
95 {
96 return mlx5_buf_offset(&qp->buf, offset);
97 }
98
99 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
100 {
101 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
102 }
103
104 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
105 {
106 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
107 }
108
109 /**
110 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
111 *
112 * @qp: QP to copy from.
113 * @send: copy from the send queue when non-zero, use the receive queue
114 * otherwise.
115 * @wqe_index: index to start copying from. For send work queues, the
116 * wqe_index is in units of MLX5_SEND_WQE_BB.
117 * For receive work queue, it is the number of work queue
118 * element in the queue.
119 * @buffer: destination buffer.
120 * @length: maximum number of bytes to copy.
121 *
122 * Copies at least a single WQE, but may copy more data.
123 *
124 * Return: the number of bytes copied, or an error code.
125 */
126 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
127 void *buffer, u32 length,
128 struct mlx5_ib_qp_base *base)
129 {
130 struct ib_device *ibdev = qp->ibqp.device;
131 struct mlx5_ib_dev *dev = to_mdev(ibdev);
132 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
133 size_t offset;
134 size_t wq_end;
135 struct ib_umem *umem = base->ubuffer.umem;
136 u32 first_copy_length;
137 int wqe_length;
138 int ret;
139
140 if (wq->wqe_cnt == 0) {
141 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
142 qp->ibqp.qp_type);
143 return -EINVAL;
144 }
145
146 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
147 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
148
149 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
150 return -EINVAL;
151
152 if (offset > umem->length ||
153 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
154 return -EINVAL;
155
156 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
157 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
158 if (ret)
159 return ret;
160
161 if (send) {
162 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
163 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
164
165 wqe_length = ds * MLX5_WQE_DS_UNITS;
166 } else {
167 wqe_length = 1 << wq->wqe_shift;
168 }
169
170 if (wqe_length <= first_copy_length)
171 return first_copy_length;
172
173 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
174 wqe_length - first_copy_length);
175 if (ret)
176 return ret;
177
178 return wqe_length;
179 }
180
181 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
182 {
183 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
184 struct ib_event event;
185
186 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
187 /* This event is only valid for trans_qps */
188 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
189 }
190
191 if (ibqp->event_handler) {
192 event.device = ibqp->device;
193 event.element.qp = ibqp;
194 switch (type) {
195 case MLX5_EVENT_TYPE_PATH_MIG:
196 event.event = IB_EVENT_PATH_MIG;
197 break;
198 case MLX5_EVENT_TYPE_COMM_EST:
199 event.event = IB_EVENT_COMM_EST;
200 break;
201 case MLX5_EVENT_TYPE_SQ_DRAINED:
202 event.event = IB_EVENT_SQ_DRAINED;
203 break;
204 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
205 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
206 break;
207 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
208 event.event = IB_EVENT_QP_FATAL;
209 break;
210 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
211 event.event = IB_EVENT_PATH_MIG_ERR;
212 break;
213 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
214 event.event = IB_EVENT_QP_REQ_ERR;
215 break;
216 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
217 event.event = IB_EVENT_QP_ACCESS_ERR;
218 break;
219 default:
220 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
221 return;
222 }
223
224 ibqp->event_handler(&event, ibqp->qp_context);
225 }
226 }
227
228 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
229 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
230 {
231 int wqe_size;
232 int wq_size;
233
234 /* Sanity check RQ size before proceeding */
235 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
236 return -EINVAL;
237
238 if (!has_rq) {
239 qp->rq.max_gs = 0;
240 qp->rq.wqe_cnt = 0;
241 qp->rq.wqe_shift = 0;
242 cap->max_recv_wr = 0;
243 cap->max_recv_sge = 0;
244 } else {
245 if (ucmd) {
246 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
247 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
248 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
249 qp->rq.max_post = qp->rq.wqe_cnt;
250 } else {
251 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
252 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
253 wqe_size = roundup_pow_of_two(wqe_size);
254 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
255 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
256 qp->rq.wqe_cnt = wq_size / wqe_size;
257 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
258 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
259 wqe_size,
260 MLX5_CAP_GEN(dev->mdev,
261 max_wqe_sz_rq));
262 return -EINVAL;
263 }
264 qp->rq.wqe_shift = ilog2(wqe_size);
265 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
266 qp->rq.max_post = qp->rq.wqe_cnt;
267 }
268 }
269
270 return 0;
271 }
272
273 static int sq_overhead(struct ib_qp_init_attr *attr)
274 {
275 int size = 0;
276
277 switch (attr->qp_type) {
278 case IB_QPT_XRC_INI:
279 size += sizeof(struct mlx5_wqe_xrc_seg);
280 /* fall through */
281 case IB_QPT_RC:
282 size += sizeof(struct mlx5_wqe_ctrl_seg) +
283 max(sizeof(struct mlx5_wqe_atomic_seg) +
284 sizeof(struct mlx5_wqe_raddr_seg),
285 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
286 sizeof(struct mlx5_mkey_seg));
287 break;
288
289 case IB_QPT_XRC_TGT:
290 return 0;
291
292 case IB_QPT_UC:
293 size += sizeof(struct mlx5_wqe_ctrl_seg) +
294 max(sizeof(struct mlx5_wqe_raddr_seg),
295 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
296 sizeof(struct mlx5_mkey_seg));
297 break;
298
299 case IB_QPT_UD:
300 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
301 size += sizeof(struct mlx5_wqe_eth_pad) +
302 sizeof(struct mlx5_wqe_eth_seg);
303 /* fall through */
304 case IB_QPT_SMI:
305 case MLX5_IB_QPT_HW_GSI:
306 size += sizeof(struct mlx5_wqe_ctrl_seg) +
307 sizeof(struct mlx5_wqe_datagram_seg);
308 break;
309
310 case MLX5_IB_QPT_REG_UMR:
311 size += sizeof(struct mlx5_wqe_ctrl_seg) +
312 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
313 sizeof(struct mlx5_mkey_seg);
314 break;
315
316 default:
317 return -EINVAL;
318 }
319
320 return size;
321 }
322
323 static int calc_send_wqe(struct ib_qp_init_attr *attr)
324 {
325 int inl_size = 0;
326 int size;
327
328 size = sq_overhead(attr);
329 if (size < 0)
330 return size;
331
332 if (attr->cap.max_inline_data) {
333 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
334 attr->cap.max_inline_data;
335 }
336
337 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
338 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
339 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
340 return MLX5_SIG_WQE_SIZE;
341 else
342 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
343 }
344
345 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
346 struct mlx5_ib_qp *qp)
347 {
348 int wqe_size;
349 int wq_size;
350
351 if (!attr->cap.max_send_wr)
352 return 0;
353
354 wqe_size = calc_send_wqe(attr);
355 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
356 if (wqe_size < 0)
357 return wqe_size;
358
359 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
360 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
361 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
362 return -EINVAL;
363 }
364
365 qp->max_inline_data = wqe_size - sq_overhead(attr) -
366 sizeof(struct mlx5_wqe_inline_seg);
367 attr->cap.max_inline_data = qp->max_inline_data;
368
369 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
370 qp->signature_en = true;
371
372 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
373 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
374 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
375 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
376 qp->sq.wqe_cnt,
377 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
378 return -ENOMEM;
379 }
380 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
381 qp->sq.max_gs = attr->cap.max_send_sge;
382 qp->sq.max_post = wq_size / wqe_size;
383 attr->cap.max_send_wr = qp->sq.max_post;
384
385 return wq_size;
386 }
387
388 static int set_user_buf_size(struct mlx5_ib_dev *dev,
389 struct mlx5_ib_qp *qp,
390 struct mlx5_ib_create_qp *ucmd,
391 struct mlx5_ib_qp_base *base,
392 struct ib_qp_init_attr *attr)
393 {
394 int desc_sz = 1 << qp->sq.wqe_shift;
395
396 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
397 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
398 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
399 return -EINVAL;
400 }
401
402 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
403 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
404 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
405 return -EINVAL;
406 }
407
408 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
409
410 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
411 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
412 qp->sq.wqe_cnt,
413 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
414 return -EINVAL;
415 }
416
417 if (attr->qp_type == IB_QPT_RAW_PACKET) {
418 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
419 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
420 } else {
421 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
422 (qp->sq.wqe_cnt << 6);
423 }
424
425 return 0;
426 }
427
428 static int qp_has_rq(struct ib_qp_init_attr *attr)
429 {
430 if (attr->qp_type == IB_QPT_XRC_INI ||
431 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
432 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
433 !attr->cap.max_recv_wr)
434 return 0;
435
436 return 1;
437 }
438
439 static int first_med_uuar(void)
440 {
441 return 1;
442 }
443
444 static int next_uuar(int n)
445 {
446 n++;
447
448 while (((n % 4) & 2))
449 n++;
450
451 return n;
452 }
453
454 static int num_med_uuar(struct mlx5_uuar_info *uuari)
455 {
456 int n;
457
458 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
459 uuari->num_low_latency_uuars - 1;
460
461 return n >= 0 ? n : 0;
462 }
463
464 static int max_uuari(struct mlx5_uuar_info *uuari)
465 {
466 return uuari->num_uars * 4;
467 }
468
469 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
470 {
471 int med;
472 int i;
473 int t;
474
475 med = num_med_uuar(uuari);
476 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
477 t++;
478 if (t == med)
479 return next_uuar(i);
480 }
481
482 return 0;
483 }
484
485 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
486 {
487 int i;
488
489 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
490 if (!test_bit(i, uuari->bitmap)) {
491 set_bit(i, uuari->bitmap);
492 uuari->count[i]++;
493 return i;
494 }
495 }
496
497 return -ENOMEM;
498 }
499
500 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
501 {
502 int minidx = first_med_uuar();
503 int i;
504
505 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
506 if (uuari->count[i] < uuari->count[minidx])
507 minidx = i;
508 }
509
510 uuari->count[minidx]++;
511 return minidx;
512 }
513
514 static int alloc_uuar(struct mlx5_uuar_info *uuari,
515 enum mlx5_ib_latency_class lat)
516 {
517 int uuarn = -EINVAL;
518
519 mutex_lock(&uuari->lock);
520 switch (lat) {
521 case MLX5_IB_LATENCY_CLASS_LOW:
522 uuarn = 0;
523 uuari->count[uuarn]++;
524 break;
525
526 case MLX5_IB_LATENCY_CLASS_MEDIUM:
527 if (uuari->ver < 2)
528 uuarn = -ENOMEM;
529 else
530 uuarn = alloc_med_class_uuar(uuari);
531 break;
532
533 case MLX5_IB_LATENCY_CLASS_HIGH:
534 if (uuari->ver < 2)
535 uuarn = -ENOMEM;
536 else
537 uuarn = alloc_high_class_uuar(uuari);
538 break;
539
540 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
541 uuarn = 2;
542 break;
543 }
544 mutex_unlock(&uuari->lock);
545
546 return uuarn;
547 }
548
549 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
550 {
551 clear_bit(uuarn, uuari->bitmap);
552 --uuari->count[uuarn];
553 }
554
555 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
556 {
557 clear_bit(uuarn, uuari->bitmap);
558 --uuari->count[uuarn];
559 }
560
561 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
562 {
563 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
564 int high_uuar = nuuars - uuari->num_low_latency_uuars;
565
566 mutex_lock(&uuari->lock);
567 if (uuarn == 0) {
568 --uuari->count[uuarn];
569 goto out;
570 }
571
572 if (uuarn < high_uuar) {
573 free_med_class_uuar(uuari, uuarn);
574 goto out;
575 }
576
577 free_high_class_uuar(uuari, uuarn);
578
579 out:
580 mutex_unlock(&uuari->lock);
581 }
582
583 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
584 {
585 switch (state) {
586 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
587 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
588 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
589 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
590 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
591 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
592 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
593 default: return -1;
594 }
595 }
596
597 static int to_mlx5_st(enum ib_qp_type type)
598 {
599 switch (type) {
600 case IB_QPT_RC: return MLX5_QP_ST_RC;
601 case IB_QPT_UC: return MLX5_QP_ST_UC;
602 case IB_QPT_UD: return MLX5_QP_ST_UD;
603 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
604 case IB_QPT_XRC_INI:
605 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
606 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
607 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
608 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
609 case IB_QPT_RAW_PACKET:
610 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
611 case IB_QPT_MAX:
612 default: return -EINVAL;
613 }
614 }
615
616 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
617 struct mlx5_ib_cq *recv_cq);
618 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
619 struct mlx5_ib_cq *recv_cq);
620
621 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
622 {
623 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
624 }
625
626 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
627 struct ib_pd *pd,
628 unsigned long addr, size_t size,
629 struct ib_umem **umem,
630 int *npages, int *page_shift, int *ncont,
631 u32 *offset)
632 {
633 int err;
634
635 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
636 if (IS_ERR(*umem)) {
637 mlx5_ib_dbg(dev, "umem_get failed\n");
638 return PTR_ERR(*umem);
639 }
640
641 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
642
643 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
644 if (err) {
645 mlx5_ib_warn(dev, "bad offset\n");
646 goto err_umem;
647 }
648
649 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
650 addr, size, *npages, *page_shift, *ncont, *offset);
651
652 return 0;
653
654 err_umem:
655 ib_umem_release(*umem);
656 *umem = NULL;
657
658 return err;
659 }
660
661 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
662 {
663 struct mlx5_ib_ucontext *context;
664
665 context = to_mucontext(pd->uobject->context);
666 mlx5_ib_db_unmap_user(context, &rwq->db);
667 if (rwq->umem)
668 ib_umem_release(rwq->umem);
669 }
670
671 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
672 struct mlx5_ib_rwq *rwq,
673 struct mlx5_ib_create_wq *ucmd)
674 {
675 struct mlx5_ib_ucontext *context;
676 int page_shift = 0;
677 int npages;
678 u32 offset = 0;
679 int ncont = 0;
680 int err;
681
682 if (!ucmd->buf_addr)
683 return -EINVAL;
684
685 context = to_mucontext(pd->uobject->context);
686 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
687 rwq->buf_size, 0, 0);
688 if (IS_ERR(rwq->umem)) {
689 mlx5_ib_dbg(dev, "umem_get failed\n");
690 err = PTR_ERR(rwq->umem);
691 return err;
692 }
693
694 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
695 &ncont, NULL);
696 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
697 &rwq->rq_page_offset);
698 if (err) {
699 mlx5_ib_warn(dev, "bad offset\n");
700 goto err_umem;
701 }
702
703 rwq->rq_num_pas = ncont;
704 rwq->page_shift = page_shift;
705 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
706 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
707
708 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
709 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
710 npages, page_shift, ncont, offset);
711
712 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
713 if (err) {
714 mlx5_ib_dbg(dev, "map failed\n");
715 goto err_umem;
716 }
717
718 rwq->create_type = MLX5_WQ_USER;
719 return 0;
720
721 err_umem:
722 ib_umem_release(rwq->umem);
723 return err;
724 }
725
726 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
727 struct mlx5_ib_qp *qp, struct ib_udata *udata,
728 struct ib_qp_init_attr *attr,
729 u32 **in,
730 struct mlx5_ib_create_qp_resp *resp, int *inlen,
731 struct mlx5_ib_qp_base *base)
732 {
733 struct mlx5_ib_ucontext *context;
734 struct mlx5_ib_create_qp ucmd;
735 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
736 int page_shift = 0;
737 int uar_index;
738 int npages;
739 u32 offset = 0;
740 int uuarn;
741 int ncont = 0;
742 __be64 *pas;
743 void *qpc;
744 int err;
745
746 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
747 if (err) {
748 mlx5_ib_dbg(dev, "copy failed\n");
749 return err;
750 }
751
752 context = to_mucontext(pd->uobject->context);
753 /*
754 * TBD: should come from the verbs when we have the API
755 */
756 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
757 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
758 uuarn = MLX5_CROSS_CHANNEL_UUAR;
759 else {
760 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
761 if (uuarn < 0) {
762 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
763 mlx5_ib_dbg(dev, "reverting to medium latency\n");
764 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
765 if (uuarn < 0) {
766 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
767 mlx5_ib_dbg(dev, "reverting to high latency\n");
768 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
769 if (uuarn < 0) {
770 mlx5_ib_warn(dev, "uuar allocation failed\n");
771 return uuarn;
772 }
773 }
774 }
775 }
776
777 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
778 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
779
780 qp->rq.offset = 0;
781 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
782 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
783
784 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
785 if (err)
786 goto err_uuar;
787
788 if (ucmd.buf_addr && ubuffer->buf_size) {
789 ubuffer->buf_addr = ucmd.buf_addr;
790 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
791 ubuffer->buf_size,
792 &ubuffer->umem, &npages, &page_shift,
793 &ncont, &offset);
794 if (err)
795 goto err_uuar;
796 } else {
797 ubuffer->umem = NULL;
798 }
799
800 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
801 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
802 *in = mlx5_vzalloc(*inlen);
803 if (!*in) {
804 err = -ENOMEM;
805 goto err_umem;
806 }
807
808 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
809 if (ubuffer->umem)
810 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
811
812 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
813
814 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
815 MLX5_SET(qpc, qpc, page_offset, offset);
816
817 MLX5_SET(qpc, qpc, uar_page, uar_index);
818 resp->uuar_index = uuarn;
819 qp->uuarn = uuarn;
820
821 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
822 if (err) {
823 mlx5_ib_dbg(dev, "map failed\n");
824 goto err_free;
825 }
826
827 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
828 if (err) {
829 mlx5_ib_dbg(dev, "copy failed\n");
830 goto err_unmap;
831 }
832 qp->create_type = MLX5_QP_USER;
833
834 return 0;
835
836 err_unmap:
837 mlx5_ib_db_unmap_user(context, &qp->db);
838
839 err_free:
840 kvfree(*in);
841
842 err_umem:
843 if (ubuffer->umem)
844 ib_umem_release(ubuffer->umem);
845
846 err_uuar:
847 free_uuar(&context->uuari, uuarn);
848 return err;
849 }
850
851 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
852 struct mlx5_ib_qp_base *base)
853 {
854 struct mlx5_ib_ucontext *context;
855
856 context = to_mucontext(pd->uobject->context);
857 mlx5_ib_db_unmap_user(context, &qp->db);
858 if (base->ubuffer.umem)
859 ib_umem_release(base->ubuffer.umem);
860 free_uuar(&context->uuari, qp->uuarn);
861 }
862
863 static int create_kernel_qp(struct mlx5_ib_dev *dev,
864 struct ib_qp_init_attr *init_attr,
865 struct mlx5_ib_qp *qp,
866 u32 **in, int *inlen,
867 struct mlx5_ib_qp_base *base)
868 {
869 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
870 struct mlx5_uuar_info *uuari;
871 int uar_index;
872 void *qpc;
873 int uuarn;
874 int err;
875
876 uuari = &dev->mdev->priv.uuari;
877 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
878 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
879 IB_QP_CREATE_IPOIB_UD_LSO |
880 mlx5_ib_create_qp_sqpn_qp1()))
881 return -EINVAL;
882
883 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
884 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
885
886 uuarn = alloc_uuar(uuari, lc);
887 if (uuarn < 0) {
888 mlx5_ib_dbg(dev, "\n");
889 return -ENOMEM;
890 }
891
892 qp->bf = &uuari->bfs[uuarn];
893 uar_index = qp->bf->uar->index;
894
895 err = calc_sq_size(dev, init_attr, qp);
896 if (err < 0) {
897 mlx5_ib_dbg(dev, "err %d\n", err);
898 goto err_uuar;
899 }
900
901 qp->rq.offset = 0;
902 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
903 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
904
905 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
906 if (err) {
907 mlx5_ib_dbg(dev, "err %d\n", err);
908 goto err_uuar;
909 }
910
911 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
912 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
913 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
914 *in = mlx5_vzalloc(*inlen);
915 if (!*in) {
916 err = -ENOMEM;
917 goto err_buf;
918 }
919
920 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
921 MLX5_SET(qpc, qpc, uar_page, uar_index);
922 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
923
924 /* Set "fast registration enabled" for all kernel QPs */
925 MLX5_SET(qpc, qpc, fre, 1);
926 MLX5_SET(qpc, qpc, rlky, 1);
927
928 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
929 MLX5_SET(qpc, qpc, deth_sqpn, 1);
930 qp->flags |= MLX5_IB_QP_SQPN_QP1;
931 }
932
933 mlx5_fill_page_array(&qp->buf,
934 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
935
936 err = mlx5_db_alloc(dev->mdev, &qp->db);
937 if (err) {
938 mlx5_ib_dbg(dev, "err %d\n", err);
939 goto err_free;
940 }
941
942 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
943 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
944 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
945 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
946 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
947
948 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
949 !qp->sq.w_list || !qp->sq.wqe_head) {
950 err = -ENOMEM;
951 goto err_wrid;
952 }
953 qp->create_type = MLX5_QP_KERNEL;
954
955 return 0;
956
957 err_wrid:
958 mlx5_db_free(dev->mdev, &qp->db);
959 kfree(qp->sq.wqe_head);
960 kfree(qp->sq.w_list);
961 kfree(qp->sq.wrid);
962 kfree(qp->sq.wr_data);
963 kfree(qp->rq.wrid);
964
965 err_free:
966 kvfree(*in);
967
968 err_buf:
969 mlx5_buf_free(dev->mdev, &qp->buf);
970
971 err_uuar:
972 free_uuar(&dev->mdev->priv.uuari, uuarn);
973 return err;
974 }
975
976 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
977 {
978 mlx5_db_free(dev->mdev, &qp->db);
979 kfree(qp->sq.wqe_head);
980 kfree(qp->sq.w_list);
981 kfree(qp->sq.wrid);
982 kfree(qp->sq.wr_data);
983 kfree(qp->rq.wrid);
984 mlx5_buf_free(dev->mdev, &qp->buf);
985 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
986 }
987
988 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
989 {
990 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
991 (attr->qp_type == IB_QPT_XRC_INI))
992 return MLX5_SRQ_RQ;
993 else if (!qp->has_rq)
994 return MLX5_ZERO_LEN_RQ;
995 else
996 return MLX5_NON_ZERO_RQ;
997 }
998
999 static int is_connected(enum ib_qp_type qp_type)
1000 {
1001 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1002 return 1;
1003
1004 return 0;
1005 }
1006
1007 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1008 struct mlx5_ib_sq *sq, u32 tdn)
1009 {
1010 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
1011 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1012
1013 memset(in, 0, sizeof(in));
1014
1015 MLX5_SET(tisc, tisc, transport_domain, tdn);
1016
1017 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1018 }
1019
1020 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1021 struct mlx5_ib_sq *sq)
1022 {
1023 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1024 }
1025
1026 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1027 struct mlx5_ib_sq *sq, void *qpin,
1028 struct ib_pd *pd)
1029 {
1030 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1031 __be64 *pas;
1032 void *in;
1033 void *sqc;
1034 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1035 void *wq;
1036 int inlen;
1037 int err;
1038 int page_shift = 0;
1039 int npages;
1040 int ncont = 0;
1041 u32 offset = 0;
1042
1043 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1044 &sq->ubuffer.umem, &npages, &page_shift,
1045 &ncont, &offset);
1046 if (err)
1047 return err;
1048
1049 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1050 in = mlx5_vzalloc(inlen);
1051 if (!in) {
1052 err = -ENOMEM;
1053 goto err_umem;
1054 }
1055
1056 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1057 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1058 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1059 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1060 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1061 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1062 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1063
1064 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1065 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1066 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1067 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1068 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1069 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1070 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1071 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1072 MLX5_SET(wq, wq, page_offset, offset);
1073
1074 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1075 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1076
1077 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1078
1079 kvfree(in);
1080
1081 if (err)
1082 goto err_umem;
1083
1084 return 0;
1085
1086 err_umem:
1087 ib_umem_release(sq->ubuffer.umem);
1088 sq->ubuffer.umem = NULL;
1089
1090 return err;
1091 }
1092
1093 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1094 struct mlx5_ib_sq *sq)
1095 {
1096 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1097 ib_umem_release(sq->ubuffer.umem);
1098 }
1099
1100 static int get_rq_pas_size(void *qpc)
1101 {
1102 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1103 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1104 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1105 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1106 u32 po_quanta = 1 << (log_page_size - 6);
1107 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1108 u32 page_size = 1 << log_page_size;
1109 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1110 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1111
1112 return rq_num_pas * sizeof(u64);
1113 }
1114
1115 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1116 struct mlx5_ib_rq *rq, void *qpin)
1117 {
1118 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1119 __be64 *pas;
1120 __be64 *qp_pas;
1121 void *in;
1122 void *rqc;
1123 void *wq;
1124 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1125 int inlen;
1126 int err;
1127 u32 rq_pas_size = get_rq_pas_size(qpc);
1128
1129 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1130 in = mlx5_vzalloc(inlen);
1131 if (!in)
1132 return -ENOMEM;
1133
1134 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1135 MLX5_SET(rqc, rqc, vsd, 1);
1136 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1137 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1138 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1139 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1140 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1141
1142 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1143 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1144
1145 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1146 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1147 MLX5_SET(wq, wq, end_padding_mode,
1148 MLX5_GET(qpc, qpc, end_padding_mode));
1149 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1150 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1151 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1152 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1153 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1154 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1155
1156 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1157 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1158 memcpy(pas, qp_pas, rq_pas_size);
1159
1160 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1161
1162 kvfree(in);
1163
1164 return err;
1165 }
1166
1167 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1168 struct mlx5_ib_rq *rq)
1169 {
1170 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1171 }
1172
1173 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1174 struct mlx5_ib_rq *rq, u32 tdn)
1175 {
1176 u32 *in;
1177 void *tirc;
1178 int inlen;
1179 int err;
1180
1181 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1182 in = mlx5_vzalloc(inlen);
1183 if (!in)
1184 return -ENOMEM;
1185
1186 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1187 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1188 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1189 MLX5_SET(tirc, tirc, transport_domain, tdn);
1190
1191 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1192
1193 kvfree(in);
1194
1195 return err;
1196 }
1197
1198 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1199 struct mlx5_ib_rq *rq)
1200 {
1201 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1202 }
1203
1204 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1205 u32 *in,
1206 struct ib_pd *pd)
1207 {
1208 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1209 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1210 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1211 struct ib_uobject *uobj = pd->uobject;
1212 struct ib_ucontext *ucontext = uobj->context;
1213 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1214 int err;
1215 u32 tdn = mucontext->tdn;
1216
1217 if (qp->sq.wqe_cnt) {
1218 err = create_raw_packet_qp_tis(dev, sq, tdn);
1219 if (err)
1220 return err;
1221
1222 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1223 if (err)
1224 goto err_destroy_tis;
1225
1226 sq->base.container_mibqp = qp;
1227 }
1228
1229 if (qp->rq.wqe_cnt) {
1230 rq->base.container_mibqp = qp;
1231
1232 err = create_raw_packet_qp_rq(dev, rq, in);
1233 if (err)
1234 goto err_destroy_sq;
1235
1236
1237 err = create_raw_packet_qp_tir(dev, rq, tdn);
1238 if (err)
1239 goto err_destroy_rq;
1240 }
1241
1242 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1243 rq->base.mqp.qpn;
1244
1245 return 0;
1246
1247 err_destroy_rq:
1248 destroy_raw_packet_qp_rq(dev, rq);
1249 err_destroy_sq:
1250 if (!qp->sq.wqe_cnt)
1251 return err;
1252 destroy_raw_packet_qp_sq(dev, sq);
1253 err_destroy_tis:
1254 destroy_raw_packet_qp_tis(dev, sq);
1255
1256 return err;
1257 }
1258
1259 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1260 struct mlx5_ib_qp *qp)
1261 {
1262 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1263 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1264 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1265
1266 if (qp->rq.wqe_cnt) {
1267 destroy_raw_packet_qp_tir(dev, rq);
1268 destroy_raw_packet_qp_rq(dev, rq);
1269 }
1270
1271 if (qp->sq.wqe_cnt) {
1272 destroy_raw_packet_qp_sq(dev, sq);
1273 destroy_raw_packet_qp_tis(dev, sq);
1274 }
1275 }
1276
1277 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1278 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1279 {
1280 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1281 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1282
1283 sq->sq = &qp->sq;
1284 rq->rq = &qp->rq;
1285 sq->doorbell = &qp->db;
1286 rq->doorbell = &qp->db;
1287 }
1288
1289 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1290 {
1291 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1292 }
1293
1294 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1295 struct ib_pd *pd,
1296 struct ib_qp_init_attr *init_attr,
1297 struct ib_udata *udata)
1298 {
1299 struct ib_uobject *uobj = pd->uobject;
1300 struct ib_ucontext *ucontext = uobj->context;
1301 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1302 struct mlx5_ib_create_qp_resp resp = {};
1303 int inlen;
1304 int err;
1305 u32 *in;
1306 void *tirc;
1307 void *hfso;
1308 u32 selected_fields = 0;
1309 size_t min_resp_len;
1310 u32 tdn = mucontext->tdn;
1311 struct mlx5_ib_create_qp_rss ucmd = {};
1312 size_t required_cmd_sz;
1313
1314 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1315 return -EOPNOTSUPP;
1316
1317 if (init_attr->create_flags || init_attr->send_cq)
1318 return -EINVAL;
1319
1320 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1321 if (udata->outlen < min_resp_len)
1322 return -EINVAL;
1323
1324 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1325 if (udata->inlen < required_cmd_sz) {
1326 mlx5_ib_dbg(dev, "invalid inlen\n");
1327 return -EINVAL;
1328 }
1329
1330 if (udata->inlen > sizeof(ucmd) &&
1331 !ib_is_udata_cleared(udata, sizeof(ucmd),
1332 udata->inlen - sizeof(ucmd))) {
1333 mlx5_ib_dbg(dev, "inlen is not supported\n");
1334 return -EOPNOTSUPP;
1335 }
1336
1337 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1338 mlx5_ib_dbg(dev, "copy failed\n");
1339 return -EFAULT;
1340 }
1341
1342 if (ucmd.comp_mask) {
1343 mlx5_ib_dbg(dev, "invalid comp mask\n");
1344 return -EOPNOTSUPP;
1345 }
1346
1347 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1348 mlx5_ib_dbg(dev, "invalid reserved\n");
1349 return -EOPNOTSUPP;
1350 }
1351
1352 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1353 if (err) {
1354 mlx5_ib_dbg(dev, "copy failed\n");
1355 return -EINVAL;
1356 }
1357
1358 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1359 in = mlx5_vzalloc(inlen);
1360 if (!in)
1361 return -ENOMEM;
1362
1363 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1364 MLX5_SET(tirc, tirc, disp_type,
1365 MLX5_TIRC_DISP_TYPE_INDIRECT);
1366 MLX5_SET(tirc, tirc, indirect_table,
1367 init_attr->rwq_ind_tbl->ind_tbl_num);
1368 MLX5_SET(tirc, tirc, transport_domain, tdn);
1369
1370 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1371 switch (ucmd.rx_hash_function) {
1372 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1373 {
1374 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1375 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1376
1377 if (len != ucmd.rx_key_len) {
1378 err = -EINVAL;
1379 goto err;
1380 }
1381
1382 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1383 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1384 memcpy(rss_key, ucmd.rx_hash_key, len);
1385 break;
1386 }
1387 default:
1388 err = -EOPNOTSUPP;
1389 goto err;
1390 }
1391
1392 if (!ucmd.rx_hash_fields_mask) {
1393 /* special case when this TIR serves as steering entry without hashing */
1394 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1395 goto create_tir;
1396 err = -EINVAL;
1397 goto err;
1398 }
1399
1400 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1401 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1402 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1403 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1404 err = -EINVAL;
1405 goto err;
1406 }
1407
1408 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1409 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1410 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1411 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1412 MLX5_L3_PROT_TYPE_IPV4);
1413 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1414 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1415 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1416 MLX5_L3_PROT_TYPE_IPV6);
1417
1418 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1419 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1420 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1421 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1422 err = -EINVAL;
1423 goto err;
1424 }
1425
1426 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1427 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1428 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1429 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1430 MLX5_L4_PROT_TYPE_TCP);
1431 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1432 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1433 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1434 MLX5_L4_PROT_TYPE_UDP);
1435
1436 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1437 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1438 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1439
1440 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1441 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1442 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1443
1444 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1445 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1446 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1447
1448 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1449 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1450 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1451
1452 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1453
1454 create_tir:
1455 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1456
1457 if (err)
1458 goto err;
1459
1460 kvfree(in);
1461 /* qpn is reserved for that QP */
1462 qp->trans_qp.base.mqp.qpn = 0;
1463 return 0;
1464
1465 err:
1466 kvfree(in);
1467 return err;
1468 }
1469
1470 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1471 struct ib_qp_init_attr *init_attr,
1472 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1473 {
1474 struct mlx5_ib_resources *devr = &dev->devr;
1475 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1476 struct mlx5_core_dev *mdev = dev->mdev;
1477 struct mlx5_ib_create_qp_resp resp;
1478 struct mlx5_ib_cq *send_cq;
1479 struct mlx5_ib_cq *recv_cq;
1480 unsigned long flags;
1481 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1482 struct mlx5_ib_create_qp ucmd;
1483 struct mlx5_ib_qp_base *base;
1484 void *qpc;
1485 u32 *in;
1486 int err;
1487
1488 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1489 &qp->raw_packet_qp.rq.base :
1490 &qp->trans_qp.base;
1491
1492 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1493 mlx5_ib_odp_create_qp(qp);
1494
1495 mutex_init(&qp->mutex);
1496 spin_lock_init(&qp->sq.lock);
1497 spin_lock_init(&qp->rq.lock);
1498
1499 if (init_attr->rwq_ind_tbl) {
1500 if (!udata)
1501 return -ENOSYS;
1502
1503 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1504 return err;
1505 }
1506
1507 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1508 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1509 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1510 return -EINVAL;
1511 } else {
1512 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1513 }
1514 }
1515
1516 if (init_attr->create_flags &
1517 (IB_QP_CREATE_CROSS_CHANNEL |
1518 IB_QP_CREATE_MANAGED_SEND |
1519 IB_QP_CREATE_MANAGED_RECV)) {
1520 if (!MLX5_CAP_GEN(mdev, cd)) {
1521 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1522 return -EINVAL;
1523 }
1524 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1525 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1526 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1527 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1528 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1529 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1530 }
1531
1532 if (init_attr->qp_type == IB_QPT_UD &&
1533 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1534 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1535 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1536 return -EOPNOTSUPP;
1537 }
1538
1539 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1540 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1541 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1542 return -EOPNOTSUPP;
1543 }
1544 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1545 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1546 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1547 return -EOPNOTSUPP;
1548 }
1549 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1550 }
1551
1552 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1553 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1554
1555 if (pd && pd->uobject) {
1556 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1557 mlx5_ib_dbg(dev, "copy failed\n");
1558 return -EFAULT;
1559 }
1560
1561 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1562 &ucmd, udata->inlen, &uidx);
1563 if (err)
1564 return err;
1565
1566 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1567 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1568 } else {
1569 qp->wq_sig = !!wq_signature;
1570 }
1571
1572 qp->has_rq = qp_has_rq(init_attr);
1573 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1574 qp, (pd && pd->uobject) ? &ucmd : NULL);
1575 if (err) {
1576 mlx5_ib_dbg(dev, "err %d\n", err);
1577 return err;
1578 }
1579
1580 if (pd) {
1581 if (pd->uobject) {
1582 __u32 max_wqes =
1583 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1584 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1585 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1586 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1587 mlx5_ib_dbg(dev, "invalid rq params\n");
1588 return -EINVAL;
1589 }
1590 if (ucmd.sq_wqe_count > max_wqes) {
1591 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1592 ucmd.sq_wqe_count, max_wqes);
1593 return -EINVAL;
1594 }
1595 if (init_attr->create_flags &
1596 mlx5_ib_create_qp_sqpn_qp1()) {
1597 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1598 return -EINVAL;
1599 }
1600 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1601 &resp, &inlen, base);
1602 if (err)
1603 mlx5_ib_dbg(dev, "err %d\n", err);
1604 } else {
1605 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1606 base);
1607 if (err)
1608 mlx5_ib_dbg(dev, "err %d\n", err);
1609 }
1610
1611 if (err)
1612 return err;
1613 } else {
1614 in = mlx5_vzalloc(inlen);
1615 if (!in)
1616 return -ENOMEM;
1617
1618 qp->create_type = MLX5_QP_EMPTY;
1619 }
1620
1621 if (is_sqp(init_attr->qp_type))
1622 qp->port = init_attr->port_num;
1623
1624 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1625
1626 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1627 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1628
1629 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1630 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1631 else
1632 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1633
1634
1635 if (qp->wq_sig)
1636 MLX5_SET(qpc, qpc, wq_signature, 1);
1637
1638 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1639 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1640
1641 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1642 MLX5_SET(qpc, qpc, cd_master, 1);
1643 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1644 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1645 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1646 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1647
1648 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1649 int rcqe_sz;
1650 int scqe_sz;
1651
1652 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1653 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1654
1655 if (rcqe_sz == 128)
1656 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1657 else
1658 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1659
1660 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1661 if (scqe_sz == 128)
1662 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1663 else
1664 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1665 }
1666 }
1667
1668 if (qp->rq.wqe_cnt) {
1669 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1670 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1671 }
1672
1673 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1674
1675 if (qp->sq.wqe_cnt)
1676 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1677 else
1678 MLX5_SET(qpc, qpc, no_sq, 1);
1679
1680 /* Set default resources */
1681 switch (init_attr->qp_type) {
1682 case IB_QPT_XRC_TGT:
1683 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1684 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1685 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1686 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1687 break;
1688 case IB_QPT_XRC_INI:
1689 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1690 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1691 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1692 break;
1693 default:
1694 if (init_attr->srq) {
1695 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1696 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1697 } else {
1698 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1699 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1700 }
1701 }
1702
1703 if (init_attr->send_cq)
1704 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1705
1706 if (init_attr->recv_cq)
1707 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1708
1709 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1710
1711 /* 0xffffff means we ask to work with cqe version 0 */
1712 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1713 MLX5_SET(qpc, qpc, user_index, uidx);
1714
1715 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1716 if (init_attr->qp_type == IB_QPT_UD &&
1717 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1718 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1719 qp->flags |= MLX5_IB_QP_LSO;
1720 }
1721
1722 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1723 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1724 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1725 err = create_raw_packet_qp(dev, qp, in, pd);
1726 } else {
1727 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1728 }
1729
1730 if (err) {
1731 mlx5_ib_dbg(dev, "create qp failed\n");
1732 goto err_create;
1733 }
1734
1735 kvfree(in);
1736
1737 base->container_mibqp = qp;
1738 base->mqp.event = mlx5_ib_qp_event;
1739
1740 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1741 &send_cq, &recv_cq);
1742 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1743 mlx5_ib_lock_cqs(send_cq, recv_cq);
1744 /* Maintain device to QPs access, needed for further handling via reset
1745 * flow
1746 */
1747 list_add_tail(&qp->qps_list, &dev->qp_list);
1748 /* Maintain CQ to QPs access, needed for further handling via reset flow
1749 */
1750 if (send_cq)
1751 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1752 if (recv_cq)
1753 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1754 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1755 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1756
1757 return 0;
1758
1759 err_create:
1760 if (qp->create_type == MLX5_QP_USER)
1761 destroy_qp_user(pd, qp, base);
1762 else if (qp->create_type == MLX5_QP_KERNEL)
1763 destroy_qp_kernel(dev, qp);
1764
1765 kvfree(in);
1766 return err;
1767 }
1768
1769 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1770 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1771 {
1772 if (send_cq) {
1773 if (recv_cq) {
1774 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1775 spin_lock(&send_cq->lock);
1776 spin_lock_nested(&recv_cq->lock,
1777 SINGLE_DEPTH_NESTING);
1778 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1779 spin_lock(&send_cq->lock);
1780 __acquire(&recv_cq->lock);
1781 } else {
1782 spin_lock(&recv_cq->lock);
1783 spin_lock_nested(&send_cq->lock,
1784 SINGLE_DEPTH_NESTING);
1785 }
1786 } else {
1787 spin_lock(&send_cq->lock);
1788 __acquire(&recv_cq->lock);
1789 }
1790 } else if (recv_cq) {
1791 spin_lock(&recv_cq->lock);
1792 __acquire(&send_cq->lock);
1793 } else {
1794 __acquire(&send_cq->lock);
1795 __acquire(&recv_cq->lock);
1796 }
1797 }
1798
1799 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1800 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1801 {
1802 if (send_cq) {
1803 if (recv_cq) {
1804 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1805 spin_unlock(&recv_cq->lock);
1806 spin_unlock(&send_cq->lock);
1807 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1808 __release(&recv_cq->lock);
1809 spin_unlock(&send_cq->lock);
1810 } else {
1811 spin_unlock(&send_cq->lock);
1812 spin_unlock(&recv_cq->lock);
1813 }
1814 } else {
1815 __release(&recv_cq->lock);
1816 spin_unlock(&send_cq->lock);
1817 }
1818 } else if (recv_cq) {
1819 __release(&send_cq->lock);
1820 spin_unlock(&recv_cq->lock);
1821 } else {
1822 __release(&recv_cq->lock);
1823 __release(&send_cq->lock);
1824 }
1825 }
1826
1827 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1828 {
1829 return to_mpd(qp->ibqp.pd);
1830 }
1831
1832 static void get_cqs(enum ib_qp_type qp_type,
1833 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1834 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1835 {
1836 switch (qp_type) {
1837 case IB_QPT_XRC_TGT:
1838 *send_cq = NULL;
1839 *recv_cq = NULL;
1840 break;
1841 case MLX5_IB_QPT_REG_UMR:
1842 case IB_QPT_XRC_INI:
1843 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1844 *recv_cq = NULL;
1845 break;
1846
1847 case IB_QPT_SMI:
1848 case MLX5_IB_QPT_HW_GSI:
1849 case IB_QPT_RC:
1850 case IB_QPT_UC:
1851 case IB_QPT_UD:
1852 case IB_QPT_RAW_IPV6:
1853 case IB_QPT_RAW_ETHERTYPE:
1854 case IB_QPT_RAW_PACKET:
1855 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1856 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1857 break;
1858
1859 case IB_QPT_MAX:
1860 default:
1861 *send_cq = NULL;
1862 *recv_cq = NULL;
1863 break;
1864 }
1865 }
1866
1867 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1868 u16 operation);
1869
1870 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1871 {
1872 struct mlx5_ib_cq *send_cq, *recv_cq;
1873 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1874 struct mlx5_modify_qp_mbox_in *in;
1875 unsigned long flags;
1876 int err;
1877
1878 if (qp->ibqp.rwq_ind_tbl) {
1879 destroy_rss_raw_qp_tir(dev, qp);
1880 return;
1881 }
1882
1883 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1884 &qp->raw_packet_qp.rq.base :
1885 &qp->trans_qp.base;
1886
1887 in = kzalloc(sizeof(*in), GFP_KERNEL);
1888 if (!in)
1889 return;
1890
1891 if (qp->state != IB_QPS_RESET) {
1892 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1893 mlx5_ib_qp_disable_pagefaults(qp);
1894 err = mlx5_core_qp_modify(dev->mdev,
1895 MLX5_CMD_OP_2RST_QP, in, 0,
1896 &base->mqp);
1897 } else {
1898 err = modify_raw_packet_qp(dev, qp,
1899 MLX5_CMD_OP_2RST_QP);
1900 }
1901 if (err)
1902 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1903 base->mqp.qpn);
1904 }
1905
1906 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1907 &send_cq, &recv_cq);
1908
1909 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1910 mlx5_ib_lock_cqs(send_cq, recv_cq);
1911 /* del from lists under both locks above to protect reset flow paths */
1912 list_del(&qp->qps_list);
1913 if (send_cq)
1914 list_del(&qp->cq_send_list);
1915
1916 if (recv_cq)
1917 list_del(&qp->cq_recv_list);
1918
1919 if (qp->create_type == MLX5_QP_KERNEL) {
1920 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1921 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1922 if (send_cq != recv_cq)
1923 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1924 NULL);
1925 }
1926 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1927 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1928
1929 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1930 destroy_raw_packet_qp(dev, qp);
1931 } else {
1932 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1933 if (err)
1934 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1935 base->mqp.qpn);
1936 }
1937
1938 kfree(in);
1939
1940 if (qp->create_type == MLX5_QP_KERNEL)
1941 destroy_qp_kernel(dev, qp);
1942 else if (qp->create_type == MLX5_QP_USER)
1943 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1944 }
1945
1946 static const char *ib_qp_type_str(enum ib_qp_type type)
1947 {
1948 switch (type) {
1949 case IB_QPT_SMI:
1950 return "IB_QPT_SMI";
1951 case IB_QPT_GSI:
1952 return "IB_QPT_GSI";
1953 case IB_QPT_RC:
1954 return "IB_QPT_RC";
1955 case IB_QPT_UC:
1956 return "IB_QPT_UC";
1957 case IB_QPT_UD:
1958 return "IB_QPT_UD";
1959 case IB_QPT_RAW_IPV6:
1960 return "IB_QPT_RAW_IPV6";
1961 case IB_QPT_RAW_ETHERTYPE:
1962 return "IB_QPT_RAW_ETHERTYPE";
1963 case IB_QPT_XRC_INI:
1964 return "IB_QPT_XRC_INI";
1965 case IB_QPT_XRC_TGT:
1966 return "IB_QPT_XRC_TGT";
1967 case IB_QPT_RAW_PACKET:
1968 return "IB_QPT_RAW_PACKET";
1969 case MLX5_IB_QPT_REG_UMR:
1970 return "MLX5_IB_QPT_REG_UMR";
1971 case IB_QPT_MAX:
1972 default:
1973 return "Invalid QP type";
1974 }
1975 }
1976
1977 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1978 struct ib_qp_init_attr *init_attr,
1979 struct ib_udata *udata)
1980 {
1981 struct mlx5_ib_dev *dev;
1982 struct mlx5_ib_qp *qp;
1983 u16 xrcdn = 0;
1984 int err;
1985
1986 if (pd) {
1987 dev = to_mdev(pd->device);
1988
1989 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1990 if (!pd->uobject) {
1991 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1992 return ERR_PTR(-EINVAL);
1993 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1994 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1995 return ERR_PTR(-EINVAL);
1996 }
1997 }
1998 } else {
1999 /* being cautious here */
2000 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2001 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2002 pr_warn("%s: no PD for transport %s\n", __func__,
2003 ib_qp_type_str(init_attr->qp_type));
2004 return ERR_PTR(-EINVAL);
2005 }
2006 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2007 }
2008
2009 switch (init_attr->qp_type) {
2010 case IB_QPT_XRC_TGT:
2011 case IB_QPT_XRC_INI:
2012 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2013 mlx5_ib_dbg(dev, "XRC not supported\n");
2014 return ERR_PTR(-ENOSYS);
2015 }
2016 init_attr->recv_cq = NULL;
2017 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2018 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2019 init_attr->send_cq = NULL;
2020 }
2021
2022 /* fall through */
2023 case IB_QPT_RAW_PACKET:
2024 case IB_QPT_RC:
2025 case IB_QPT_UC:
2026 case IB_QPT_UD:
2027 case IB_QPT_SMI:
2028 case MLX5_IB_QPT_HW_GSI:
2029 case MLX5_IB_QPT_REG_UMR:
2030 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2031 if (!qp)
2032 return ERR_PTR(-ENOMEM);
2033
2034 err = create_qp_common(dev, pd, init_attr, udata, qp);
2035 if (err) {
2036 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2037 kfree(qp);
2038 return ERR_PTR(err);
2039 }
2040
2041 if (is_qp0(init_attr->qp_type))
2042 qp->ibqp.qp_num = 0;
2043 else if (is_qp1(init_attr->qp_type))
2044 qp->ibqp.qp_num = 1;
2045 else
2046 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2047
2048 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2049 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2050 to_mcq(init_attr->recv_cq)->mcq.cqn,
2051 to_mcq(init_attr->send_cq)->mcq.cqn);
2052
2053 qp->trans_qp.xrcdn = xrcdn;
2054
2055 break;
2056
2057 case IB_QPT_GSI:
2058 return mlx5_ib_gsi_create_qp(pd, init_attr);
2059
2060 case IB_QPT_RAW_IPV6:
2061 case IB_QPT_RAW_ETHERTYPE:
2062 case IB_QPT_MAX:
2063 default:
2064 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2065 init_attr->qp_type);
2066 /* Don't support raw QPs */
2067 return ERR_PTR(-EINVAL);
2068 }
2069
2070 return &qp->ibqp;
2071 }
2072
2073 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2074 {
2075 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2076 struct mlx5_ib_qp *mqp = to_mqp(qp);
2077
2078 if (unlikely(qp->qp_type == IB_QPT_GSI))
2079 return mlx5_ib_gsi_destroy_qp(qp);
2080
2081 destroy_qp_common(dev, mqp);
2082
2083 kfree(mqp);
2084
2085 return 0;
2086 }
2087
2088 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2089 int attr_mask)
2090 {
2091 u32 hw_access_flags = 0;
2092 u8 dest_rd_atomic;
2093 u32 access_flags;
2094
2095 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2096 dest_rd_atomic = attr->max_dest_rd_atomic;
2097 else
2098 dest_rd_atomic = qp->trans_qp.resp_depth;
2099
2100 if (attr_mask & IB_QP_ACCESS_FLAGS)
2101 access_flags = attr->qp_access_flags;
2102 else
2103 access_flags = qp->trans_qp.atomic_rd_en;
2104
2105 if (!dest_rd_atomic)
2106 access_flags &= IB_ACCESS_REMOTE_WRITE;
2107
2108 if (access_flags & IB_ACCESS_REMOTE_READ)
2109 hw_access_flags |= MLX5_QP_BIT_RRE;
2110 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2111 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2112 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2113 hw_access_flags |= MLX5_QP_BIT_RWE;
2114
2115 return cpu_to_be32(hw_access_flags);
2116 }
2117
2118 enum {
2119 MLX5_PATH_FLAG_FL = 1 << 0,
2120 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2121 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2122 };
2123
2124 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2125 {
2126 if (rate == IB_RATE_PORT_CURRENT) {
2127 return 0;
2128 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2129 return -EINVAL;
2130 } else {
2131 while (rate != IB_RATE_2_5_GBPS &&
2132 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2133 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2134 --rate;
2135 }
2136
2137 return rate + MLX5_STAT_RATE_OFFSET;
2138 }
2139
2140 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2141 struct mlx5_ib_sq *sq, u8 sl)
2142 {
2143 void *in;
2144 void *tisc;
2145 int inlen;
2146 int err;
2147
2148 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2149 in = mlx5_vzalloc(inlen);
2150 if (!in)
2151 return -ENOMEM;
2152
2153 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2154
2155 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2156 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2157
2158 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2159
2160 kvfree(in);
2161
2162 return err;
2163 }
2164
2165 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2166 const struct ib_ah_attr *ah,
2167 struct mlx5_qp_path *path, u8 port, int attr_mask,
2168 u32 path_flags, const struct ib_qp_attr *attr,
2169 bool alt)
2170 {
2171 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2172 int err;
2173
2174 if (attr_mask & IB_QP_PKEY_INDEX)
2175 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2176 attr->pkey_index);
2177
2178 if (ah->ah_flags & IB_AH_GRH) {
2179 if (ah->grh.sgid_index >=
2180 dev->mdev->port_caps[port - 1].gid_table_len) {
2181 pr_err("sgid_index (%u) too large. max is %d\n",
2182 ah->grh.sgid_index,
2183 dev->mdev->port_caps[port - 1].gid_table_len);
2184 return -EINVAL;
2185 }
2186 }
2187
2188 if (ll == IB_LINK_LAYER_ETHERNET) {
2189 if (!(ah->ah_flags & IB_AH_GRH))
2190 return -EINVAL;
2191 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2192 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2193 ah->grh.sgid_index);
2194 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2195 } else {
2196 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2197 path->fl_free_ar |=
2198 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2199 path->rlid = cpu_to_be16(ah->dlid);
2200 path->grh_mlid = ah->src_path_bits & 0x7f;
2201 if (ah->ah_flags & IB_AH_GRH)
2202 path->grh_mlid |= 1 << 7;
2203 path->dci_cfi_prio_sl = ah->sl & 0xf;
2204 }
2205
2206 if (ah->ah_flags & IB_AH_GRH) {
2207 path->mgid_index = ah->grh.sgid_index;
2208 path->hop_limit = ah->grh.hop_limit;
2209 path->tclass_flowlabel =
2210 cpu_to_be32((ah->grh.traffic_class << 20) |
2211 (ah->grh.flow_label));
2212 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2213 }
2214
2215 err = ib_rate_to_mlx5(dev, ah->static_rate);
2216 if (err < 0)
2217 return err;
2218 path->static_rate = err;
2219 path->port = port;
2220
2221 if (attr_mask & IB_QP_TIMEOUT)
2222 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2223
2224 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2225 return modify_raw_packet_eth_prio(dev->mdev,
2226 &qp->raw_packet_qp.sq,
2227 ah->sl & 0xf);
2228
2229 return 0;
2230 }
2231
2232 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2233 [MLX5_QP_STATE_INIT] = {
2234 [MLX5_QP_STATE_INIT] = {
2235 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2236 MLX5_QP_OPTPAR_RAE |
2237 MLX5_QP_OPTPAR_RWE |
2238 MLX5_QP_OPTPAR_PKEY_INDEX |
2239 MLX5_QP_OPTPAR_PRI_PORT,
2240 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2241 MLX5_QP_OPTPAR_PKEY_INDEX |
2242 MLX5_QP_OPTPAR_PRI_PORT,
2243 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2244 MLX5_QP_OPTPAR_Q_KEY |
2245 MLX5_QP_OPTPAR_PRI_PORT,
2246 },
2247 [MLX5_QP_STATE_RTR] = {
2248 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2249 MLX5_QP_OPTPAR_RRE |
2250 MLX5_QP_OPTPAR_RAE |
2251 MLX5_QP_OPTPAR_RWE |
2252 MLX5_QP_OPTPAR_PKEY_INDEX,
2253 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2254 MLX5_QP_OPTPAR_RWE |
2255 MLX5_QP_OPTPAR_PKEY_INDEX,
2256 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2257 MLX5_QP_OPTPAR_Q_KEY,
2258 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2259 MLX5_QP_OPTPAR_Q_KEY,
2260 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2261 MLX5_QP_OPTPAR_RRE |
2262 MLX5_QP_OPTPAR_RAE |
2263 MLX5_QP_OPTPAR_RWE |
2264 MLX5_QP_OPTPAR_PKEY_INDEX,
2265 },
2266 },
2267 [MLX5_QP_STATE_RTR] = {
2268 [MLX5_QP_STATE_RTS] = {
2269 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2270 MLX5_QP_OPTPAR_RRE |
2271 MLX5_QP_OPTPAR_RAE |
2272 MLX5_QP_OPTPAR_RWE |
2273 MLX5_QP_OPTPAR_PM_STATE |
2274 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2275 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2276 MLX5_QP_OPTPAR_RWE |
2277 MLX5_QP_OPTPAR_PM_STATE,
2278 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2279 },
2280 },
2281 [MLX5_QP_STATE_RTS] = {
2282 [MLX5_QP_STATE_RTS] = {
2283 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2284 MLX5_QP_OPTPAR_RAE |
2285 MLX5_QP_OPTPAR_RWE |
2286 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2287 MLX5_QP_OPTPAR_PM_STATE |
2288 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2289 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2290 MLX5_QP_OPTPAR_PM_STATE |
2291 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2292 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2293 MLX5_QP_OPTPAR_SRQN |
2294 MLX5_QP_OPTPAR_CQN_RCV,
2295 },
2296 },
2297 [MLX5_QP_STATE_SQER] = {
2298 [MLX5_QP_STATE_RTS] = {
2299 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2300 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2301 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2302 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2303 MLX5_QP_OPTPAR_RWE |
2304 MLX5_QP_OPTPAR_RAE |
2305 MLX5_QP_OPTPAR_RRE,
2306 },
2307 },
2308 };
2309
2310 static int ib_nr_to_mlx5_nr(int ib_mask)
2311 {
2312 switch (ib_mask) {
2313 case IB_QP_STATE:
2314 return 0;
2315 case IB_QP_CUR_STATE:
2316 return 0;
2317 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2318 return 0;
2319 case IB_QP_ACCESS_FLAGS:
2320 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2321 MLX5_QP_OPTPAR_RAE;
2322 case IB_QP_PKEY_INDEX:
2323 return MLX5_QP_OPTPAR_PKEY_INDEX;
2324 case IB_QP_PORT:
2325 return MLX5_QP_OPTPAR_PRI_PORT;
2326 case IB_QP_QKEY:
2327 return MLX5_QP_OPTPAR_Q_KEY;
2328 case IB_QP_AV:
2329 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2330 MLX5_QP_OPTPAR_PRI_PORT;
2331 case IB_QP_PATH_MTU:
2332 return 0;
2333 case IB_QP_TIMEOUT:
2334 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2335 case IB_QP_RETRY_CNT:
2336 return MLX5_QP_OPTPAR_RETRY_COUNT;
2337 case IB_QP_RNR_RETRY:
2338 return MLX5_QP_OPTPAR_RNR_RETRY;
2339 case IB_QP_RQ_PSN:
2340 return 0;
2341 case IB_QP_MAX_QP_RD_ATOMIC:
2342 return MLX5_QP_OPTPAR_SRA_MAX;
2343 case IB_QP_ALT_PATH:
2344 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2345 case IB_QP_MIN_RNR_TIMER:
2346 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2347 case IB_QP_SQ_PSN:
2348 return 0;
2349 case IB_QP_MAX_DEST_RD_ATOMIC:
2350 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2351 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2352 case IB_QP_PATH_MIG_STATE:
2353 return MLX5_QP_OPTPAR_PM_STATE;
2354 case IB_QP_CAP:
2355 return 0;
2356 case IB_QP_DEST_QPN:
2357 return 0;
2358 }
2359 return 0;
2360 }
2361
2362 static int ib_mask_to_mlx5_opt(int ib_mask)
2363 {
2364 int result = 0;
2365 int i;
2366
2367 for (i = 0; i < 8 * sizeof(int); i++) {
2368 if ((1 << i) & ib_mask)
2369 result |= ib_nr_to_mlx5_nr(1 << i);
2370 }
2371
2372 return result;
2373 }
2374
2375 static int modify_raw_packet_qp_rq(struct mlx5_core_dev *dev,
2376 struct mlx5_ib_rq *rq, int new_state)
2377 {
2378 void *in;
2379 void *rqc;
2380 int inlen;
2381 int err;
2382
2383 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2384 in = mlx5_vzalloc(inlen);
2385 if (!in)
2386 return -ENOMEM;
2387
2388 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2389
2390 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2391 MLX5_SET(rqc, rqc, state, new_state);
2392
2393 err = mlx5_core_modify_rq(dev, rq->base.mqp.qpn, in, inlen);
2394 if (err)
2395 goto out;
2396
2397 rq->state = new_state;
2398
2399 out:
2400 kvfree(in);
2401 return err;
2402 }
2403
2404 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2405 struct mlx5_ib_sq *sq, int new_state)
2406 {
2407 void *in;
2408 void *sqc;
2409 int inlen;
2410 int err;
2411
2412 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2413 in = mlx5_vzalloc(inlen);
2414 if (!in)
2415 return -ENOMEM;
2416
2417 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2418
2419 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2420 MLX5_SET(sqc, sqc, state, new_state);
2421
2422 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2423 if (err)
2424 goto out;
2425
2426 sq->state = new_state;
2427
2428 out:
2429 kvfree(in);
2430 return err;
2431 }
2432
2433 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2434 u16 operation)
2435 {
2436 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2437 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2438 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2439 int rq_state;
2440 int sq_state;
2441 int err;
2442
2443 switch (operation) {
2444 case MLX5_CMD_OP_RST2INIT_QP:
2445 rq_state = MLX5_RQC_STATE_RDY;
2446 sq_state = MLX5_SQC_STATE_RDY;
2447 break;
2448 case MLX5_CMD_OP_2ERR_QP:
2449 rq_state = MLX5_RQC_STATE_ERR;
2450 sq_state = MLX5_SQC_STATE_ERR;
2451 break;
2452 case MLX5_CMD_OP_2RST_QP:
2453 rq_state = MLX5_RQC_STATE_RST;
2454 sq_state = MLX5_SQC_STATE_RST;
2455 break;
2456 case MLX5_CMD_OP_INIT2INIT_QP:
2457 case MLX5_CMD_OP_INIT2RTR_QP:
2458 case MLX5_CMD_OP_RTR2RTS_QP:
2459 case MLX5_CMD_OP_RTS2RTS_QP:
2460 /* Nothing to do here... */
2461 return 0;
2462 default:
2463 WARN_ON(1);
2464 return -EINVAL;
2465 }
2466
2467 if (qp->rq.wqe_cnt) {
2468 err = modify_raw_packet_qp_rq(dev->mdev, rq, rq_state);
2469 if (err)
2470 return err;
2471 }
2472
2473 if (qp->sq.wqe_cnt)
2474 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2475
2476 return 0;
2477 }
2478
2479 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2480 const struct ib_qp_attr *attr, int attr_mask,
2481 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2482 {
2483 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2484 [MLX5_QP_STATE_RST] = {
2485 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2486 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2487 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2488 },
2489 [MLX5_QP_STATE_INIT] = {
2490 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2491 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2492 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2493 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2494 },
2495 [MLX5_QP_STATE_RTR] = {
2496 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2497 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2498 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2499 },
2500 [MLX5_QP_STATE_RTS] = {
2501 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2502 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2503 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2504 },
2505 [MLX5_QP_STATE_SQD] = {
2506 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2507 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2508 },
2509 [MLX5_QP_STATE_SQER] = {
2510 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2511 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2512 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2513 },
2514 [MLX5_QP_STATE_ERR] = {
2515 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2516 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2517 }
2518 };
2519
2520 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2521 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2522 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2523 struct mlx5_ib_cq *send_cq, *recv_cq;
2524 struct mlx5_qp_context *context;
2525 struct mlx5_modify_qp_mbox_in *in;
2526 struct mlx5_ib_pd *pd;
2527 enum mlx5_qp_state mlx5_cur, mlx5_new;
2528 enum mlx5_qp_optpar optpar;
2529 int sqd_event;
2530 int mlx5_st;
2531 int err;
2532 u16 op;
2533
2534 in = kzalloc(sizeof(*in), GFP_KERNEL);
2535 if (!in)
2536 return -ENOMEM;
2537
2538 context = &in->ctx;
2539 err = to_mlx5_st(ibqp->qp_type);
2540 if (err < 0) {
2541 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2542 goto out;
2543 }
2544
2545 context->flags = cpu_to_be32(err << 16);
2546
2547 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2548 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2549 } else {
2550 switch (attr->path_mig_state) {
2551 case IB_MIG_MIGRATED:
2552 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2553 break;
2554 case IB_MIG_REARM:
2555 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2556 break;
2557 case IB_MIG_ARMED:
2558 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2559 break;
2560 }
2561 }
2562
2563 if (is_sqp(ibqp->qp_type)) {
2564 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2565 } else if (ibqp->qp_type == IB_QPT_UD ||
2566 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2567 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2568 } else if (attr_mask & IB_QP_PATH_MTU) {
2569 if (attr->path_mtu < IB_MTU_256 ||
2570 attr->path_mtu > IB_MTU_4096) {
2571 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2572 err = -EINVAL;
2573 goto out;
2574 }
2575 context->mtu_msgmax = (attr->path_mtu << 5) |
2576 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2577 }
2578
2579 if (attr_mask & IB_QP_DEST_QPN)
2580 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2581
2582 if (attr_mask & IB_QP_PKEY_INDEX)
2583 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2584
2585 /* todo implement counter_index functionality */
2586
2587 if (is_sqp(ibqp->qp_type))
2588 context->pri_path.port = qp->port;
2589
2590 if (attr_mask & IB_QP_PORT)
2591 context->pri_path.port = attr->port_num;
2592
2593 if (attr_mask & IB_QP_AV) {
2594 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2595 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2596 attr_mask, 0, attr, false);
2597 if (err)
2598 goto out;
2599 }
2600
2601 if (attr_mask & IB_QP_TIMEOUT)
2602 context->pri_path.ackto_lt |= attr->timeout << 3;
2603
2604 if (attr_mask & IB_QP_ALT_PATH) {
2605 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2606 &context->alt_path,
2607 attr->alt_port_num,
2608 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2609 0, attr, true);
2610 if (err)
2611 goto out;
2612 }
2613
2614 pd = get_pd(qp);
2615 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2616 &send_cq, &recv_cq);
2617
2618 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2619 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2620 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2621 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2622
2623 if (attr_mask & IB_QP_RNR_RETRY)
2624 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2625
2626 if (attr_mask & IB_QP_RETRY_CNT)
2627 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2628
2629 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2630 if (attr->max_rd_atomic)
2631 context->params1 |=
2632 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2633 }
2634
2635 if (attr_mask & IB_QP_SQ_PSN)
2636 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2637
2638 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2639 if (attr->max_dest_rd_atomic)
2640 context->params2 |=
2641 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2642 }
2643
2644 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2645 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2646
2647 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2648 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2649
2650 if (attr_mask & IB_QP_RQ_PSN)
2651 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2652
2653 if (attr_mask & IB_QP_QKEY)
2654 context->qkey = cpu_to_be32(attr->qkey);
2655
2656 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2657 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2658
2659 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2660 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2661 sqd_event = 1;
2662 else
2663 sqd_event = 0;
2664
2665 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2666 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2667 qp->port) - 1;
2668 struct mlx5_ib_port *mibport = &dev->port[port_num];
2669
2670 context->qp_counter_set_usr_page |=
2671 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2672 }
2673
2674 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2675 context->sq_crq_size |= cpu_to_be16(1 << 4);
2676
2677 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2678 context->deth_sqpn = cpu_to_be32(1);
2679
2680 mlx5_cur = to_mlx5_state(cur_state);
2681 mlx5_new = to_mlx5_state(new_state);
2682 mlx5_st = to_mlx5_st(ibqp->qp_type);
2683 if (mlx5_st < 0)
2684 goto out;
2685
2686 /* If moving to a reset or error state, we must disable page faults on
2687 * this QP and flush all current page faults. Otherwise a stale page
2688 * fault may attempt to work on this QP after it is reset and moved
2689 * again to RTS, and may cause the driver and the device to get out of
2690 * sync. */
2691 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2692 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2693 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2694 mlx5_ib_qp_disable_pagefaults(qp);
2695
2696 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2697 !optab[mlx5_cur][mlx5_new])
2698 goto out;
2699
2700 op = optab[mlx5_cur][mlx5_new];
2701 optpar = ib_mask_to_mlx5_opt(attr_mask);
2702 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2703 in->optparam = cpu_to_be32(optpar);
2704
2705 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET)
2706 err = modify_raw_packet_qp(dev, qp, op);
2707 else
2708 err = mlx5_core_qp_modify(dev->mdev, op, in, sqd_event,
2709 &base->mqp);
2710 if (err)
2711 goto out;
2712
2713 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2714 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2715 mlx5_ib_qp_enable_pagefaults(qp);
2716
2717 qp->state = new_state;
2718
2719 if (attr_mask & IB_QP_ACCESS_FLAGS)
2720 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2721 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2722 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2723 if (attr_mask & IB_QP_PORT)
2724 qp->port = attr->port_num;
2725 if (attr_mask & IB_QP_ALT_PATH)
2726 qp->trans_qp.alt_port = attr->alt_port_num;
2727
2728 /*
2729 * If we moved a kernel QP to RESET, clean up all old CQ
2730 * entries and reinitialize the QP.
2731 */
2732 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2733 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2734 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2735 if (send_cq != recv_cq)
2736 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2737
2738 qp->rq.head = 0;
2739 qp->rq.tail = 0;
2740 qp->sq.head = 0;
2741 qp->sq.tail = 0;
2742 qp->sq.cur_post = 0;
2743 qp->sq.last_poll = 0;
2744 qp->db.db[MLX5_RCV_DBR] = 0;
2745 qp->db.db[MLX5_SND_DBR] = 0;
2746 }
2747
2748 out:
2749 kfree(in);
2750 return err;
2751 }
2752
2753 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2754 int attr_mask, struct ib_udata *udata)
2755 {
2756 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2757 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2758 enum ib_qp_type qp_type;
2759 enum ib_qp_state cur_state, new_state;
2760 int err = -EINVAL;
2761 int port;
2762 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2763
2764 if (ibqp->rwq_ind_tbl)
2765 return -ENOSYS;
2766
2767 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2768 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2769
2770 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2771 IB_QPT_GSI : ibqp->qp_type;
2772
2773 mutex_lock(&qp->mutex);
2774
2775 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2776 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2777
2778 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2779 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2780 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2781 }
2782
2783 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2784 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2785 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2786 cur_state, new_state, ibqp->qp_type, attr_mask);
2787 goto out;
2788 }
2789
2790 if ((attr_mask & IB_QP_PORT) &&
2791 (attr->port_num == 0 ||
2792 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2793 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2794 attr->port_num, dev->num_ports);
2795 goto out;
2796 }
2797
2798 if (attr_mask & IB_QP_PKEY_INDEX) {
2799 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2800 if (attr->pkey_index >=
2801 dev->mdev->port_caps[port - 1].pkey_table_len) {
2802 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2803 attr->pkey_index);
2804 goto out;
2805 }
2806 }
2807
2808 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2809 attr->max_rd_atomic >
2810 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2811 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2812 attr->max_rd_atomic);
2813 goto out;
2814 }
2815
2816 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2817 attr->max_dest_rd_atomic >
2818 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2819 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2820 attr->max_dest_rd_atomic);
2821 goto out;
2822 }
2823
2824 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2825 err = 0;
2826 goto out;
2827 }
2828
2829 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2830
2831 out:
2832 mutex_unlock(&qp->mutex);
2833 return err;
2834 }
2835
2836 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2837 {
2838 struct mlx5_ib_cq *cq;
2839 unsigned cur;
2840
2841 cur = wq->head - wq->tail;
2842 if (likely(cur + nreq < wq->max_post))
2843 return 0;
2844
2845 cq = to_mcq(ib_cq);
2846 spin_lock(&cq->lock);
2847 cur = wq->head - wq->tail;
2848 spin_unlock(&cq->lock);
2849
2850 return cur + nreq >= wq->max_post;
2851 }
2852
2853 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2854 u64 remote_addr, u32 rkey)
2855 {
2856 rseg->raddr = cpu_to_be64(remote_addr);
2857 rseg->rkey = cpu_to_be32(rkey);
2858 rseg->reserved = 0;
2859 }
2860
2861 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2862 struct ib_send_wr *wr, void *qend,
2863 struct mlx5_ib_qp *qp, int *size)
2864 {
2865 void *seg = eseg;
2866
2867 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2868
2869 if (wr->send_flags & IB_SEND_IP_CSUM)
2870 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2871 MLX5_ETH_WQE_L4_CSUM;
2872
2873 seg += sizeof(struct mlx5_wqe_eth_seg);
2874 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2875
2876 if (wr->opcode == IB_WR_LSO) {
2877 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2878 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2879 u64 left, leftlen, copysz;
2880 void *pdata = ud_wr->header;
2881
2882 left = ud_wr->hlen;
2883 eseg->mss = cpu_to_be16(ud_wr->mss);
2884 eseg->inline_hdr_sz = cpu_to_be16(left);
2885
2886 /*
2887 * check if there is space till the end of queue, if yes,
2888 * copy all in one shot, otherwise copy till the end of queue,
2889 * rollback and than the copy the left
2890 */
2891 leftlen = qend - (void *)eseg->inline_hdr_start;
2892 copysz = min_t(u64, leftlen, left);
2893
2894 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2895
2896 if (likely(copysz > size_of_inl_hdr_start)) {
2897 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2898 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2899 }
2900
2901 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2902 seg = mlx5_get_send_wqe(qp, 0);
2903 left -= copysz;
2904 pdata += copysz;
2905 memcpy(seg, pdata, left);
2906 seg += ALIGN(left, 16);
2907 *size += ALIGN(left, 16) / 16;
2908 }
2909 }
2910
2911 return seg;
2912 }
2913
2914 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2915 struct ib_send_wr *wr)
2916 {
2917 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2918 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2919 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2920 }
2921
2922 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2923 {
2924 dseg->byte_count = cpu_to_be32(sg->length);
2925 dseg->lkey = cpu_to_be32(sg->lkey);
2926 dseg->addr = cpu_to_be64(sg->addr);
2927 }
2928
2929 static __be16 get_klm_octo(int npages)
2930 {
2931 return cpu_to_be16(ALIGN(npages, 8) / 2);
2932 }
2933
2934 static __be64 frwr_mkey_mask(void)
2935 {
2936 u64 result;
2937
2938 result = MLX5_MKEY_MASK_LEN |
2939 MLX5_MKEY_MASK_PAGE_SIZE |
2940 MLX5_MKEY_MASK_START_ADDR |
2941 MLX5_MKEY_MASK_EN_RINVAL |
2942 MLX5_MKEY_MASK_KEY |
2943 MLX5_MKEY_MASK_LR |
2944 MLX5_MKEY_MASK_LW |
2945 MLX5_MKEY_MASK_RR |
2946 MLX5_MKEY_MASK_RW |
2947 MLX5_MKEY_MASK_A |
2948 MLX5_MKEY_MASK_SMALL_FENCE |
2949 MLX5_MKEY_MASK_FREE;
2950
2951 return cpu_to_be64(result);
2952 }
2953
2954 static __be64 sig_mkey_mask(void)
2955 {
2956 u64 result;
2957
2958 result = MLX5_MKEY_MASK_LEN |
2959 MLX5_MKEY_MASK_PAGE_SIZE |
2960 MLX5_MKEY_MASK_START_ADDR |
2961 MLX5_MKEY_MASK_EN_SIGERR |
2962 MLX5_MKEY_MASK_EN_RINVAL |
2963 MLX5_MKEY_MASK_KEY |
2964 MLX5_MKEY_MASK_LR |
2965 MLX5_MKEY_MASK_LW |
2966 MLX5_MKEY_MASK_RR |
2967 MLX5_MKEY_MASK_RW |
2968 MLX5_MKEY_MASK_SMALL_FENCE |
2969 MLX5_MKEY_MASK_FREE |
2970 MLX5_MKEY_MASK_BSF_EN;
2971
2972 return cpu_to_be64(result);
2973 }
2974
2975 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2976 struct mlx5_ib_mr *mr)
2977 {
2978 int ndescs = mr->ndescs;
2979
2980 memset(umr, 0, sizeof(*umr));
2981
2982 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
2983 /* KLMs take twice the size of MTTs */
2984 ndescs *= 2;
2985
2986 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2987 umr->klm_octowords = get_klm_octo(ndescs);
2988 umr->mkey_mask = frwr_mkey_mask();
2989 }
2990
2991 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2992 {
2993 memset(umr, 0, sizeof(*umr));
2994 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2995 umr->flags = 1 << 7;
2996 }
2997
2998 static __be64 get_umr_reg_mr_mask(void)
2999 {
3000 u64 result;
3001
3002 result = MLX5_MKEY_MASK_LEN |
3003 MLX5_MKEY_MASK_PAGE_SIZE |
3004 MLX5_MKEY_MASK_START_ADDR |
3005 MLX5_MKEY_MASK_PD |
3006 MLX5_MKEY_MASK_LR |
3007 MLX5_MKEY_MASK_LW |
3008 MLX5_MKEY_MASK_KEY |
3009 MLX5_MKEY_MASK_RR |
3010 MLX5_MKEY_MASK_RW |
3011 MLX5_MKEY_MASK_A |
3012 MLX5_MKEY_MASK_FREE;
3013
3014 return cpu_to_be64(result);
3015 }
3016
3017 static __be64 get_umr_unreg_mr_mask(void)
3018 {
3019 u64 result;
3020
3021 result = MLX5_MKEY_MASK_FREE;
3022
3023 return cpu_to_be64(result);
3024 }
3025
3026 static __be64 get_umr_update_mtt_mask(void)
3027 {
3028 u64 result;
3029
3030 result = MLX5_MKEY_MASK_FREE;
3031
3032 return cpu_to_be64(result);
3033 }
3034
3035 static __be64 get_umr_update_translation_mask(void)
3036 {
3037 u64 result;
3038
3039 result = MLX5_MKEY_MASK_LEN |
3040 MLX5_MKEY_MASK_PAGE_SIZE |
3041 MLX5_MKEY_MASK_START_ADDR |
3042 MLX5_MKEY_MASK_KEY |
3043 MLX5_MKEY_MASK_FREE;
3044
3045 return cpu_to_be64(result);
3046 }
3047
3048 static __be64 get_umr_update_access_mask(void)
3049 {
3050 u64 result;
3051
3052 result = MLX5_MKEY_MASK_LW |
3053 MLX5_MKEY_MASK_RR |
3054 MLX5_MKEY_MASK_RW |
3055 MLX5_MKEY_MASK_A |
3056 MLX5_MKEY_MASK_KEY |
3057 MLX5_MKEY_MASK_FREE;
3058
3059 return cpu_to_be64(result);
3060 }
3061
3062 static __be64 get_umr_update_pd_mask(void)
3063 {
3064 u64 result;
3065
3066 result = MLX5_MKEY_MASK_PD |
3067 MLX5_MKEY_MASK_KEY |
3068 MLX5_MKEY_MASK_FREE;
3069
3070 return cpu_to_be64(result);
3071 }
3072
3073 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3074 struct ib_send_wr *wr)
3075 {
3076 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3077
3078 memset(umr, 0, sizeof(*umr));
3079
3080 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3081 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3082 else
3083 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3084
3085 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3086 umr->klm_octowords = get_klm_octo(umrwr->npages);
3087 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3088 umr->mkey_mask = get_umr_update_mtt_mask();
3089 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3090 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3091 }
3092 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3093 umr->mkey_mask |= get_umr_update_translation_mask();
3094 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3095 umr->mkey_mask |= get_umr_update_access_mask();
3096 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3097 umr->mkey_mask |= get_umr_update_pd_mask();
3098 if (!umr->mkey_mask)
3099 umr->mkey_mask = get_umr_reg_mr_mask();
3100 } else {
3101 umr->mkey_mask = get_umr_unreg_mr_mask();
3102 }
3103
3104 if (!wr->num_sge)
3105 umr->flags |= MLX5_UMR_INLINE;
3106 }
3107
3108 static u8 get_umr_flags(int acc)
3109 {
3110 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3111 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3112 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3113 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3114 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3115 }
3116
3117 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3118 struct mlx5_ib_mr *mr,
3119 u32 key, int access)
3120 {
3121 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3122
3123 memset(seg, 0, sizeof(*seg));
3124
3125 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3126 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3127 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3128 /* KLMs take twice the size of MTTs */
3129 ndescs *= 2;
3130
3131 seg->flags = get_umr_flags(access) | mr->access_mode;
3132 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3133 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3134 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3135 seg->len = cpu_to_be64(mr->ibmr.length);
3136 seg->xlt_oct_size = cpu_to_be32(ndescs);
3137 }
3138
3139 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3140 {
3141 memset(seg, 0, sizeof(*seg));
3142 seg->status = MLX5_MKEY_STATUS_FREE;
3143 }
3144
3145 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3146 {
3147 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3148
3149 memset(seg, 0, sizeof(*seg));
3150 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3151 seg->status = MLX5_MKEY_STATUS_FREE;
3152 return;
3153 }
3154
3155 seg->flags = convert_access(umrwr->access_flags);
3156 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3157 if (umrwr->pd)
3158 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3159 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3160 }
3161 seg->len = cpu_to_be64(umrwr->length);
3162 seg->log2_page_size = umrwr->page_shift;
3163 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3164 mlx5_mkey_variant(umrwr->mkey));
3165 }
3166
3167 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3168 struct mlx5_ib_mr *mr,
3169 struct mlx5_ib_pd *pd)
3170 {
3171 int bcount = mr->desc_size * mr->ndescs;
3172
3173 dseg->addr = cpu_to_be64(mr->desc_map);
3174 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3175 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3176 }
3177
3178 static __be32 send_ieth(struct ib_send_wr *wr)
3179 {
3180 switch (wr->opcode) {
3181 case IB_WR_SEND_WITH_IMM:
3182 case IB_WR_RDMA_WRITE_WITH_IMM:
3183 return wr->ex.imm_data;
3184
3185 case IB_WR_SEND_WITH_INV:
3186 return cpu_to_be32(wr->ex.invalidate_rkey);
3187
3188 default:
3189 return 0;
3190 }
3191 }
3192
3193 static u8 calc_sig(void *wqe, int size)
3194 {
3195 u8 *p = wqe;
3196 u8 res = 0;
3197 int i;
3198
3199 for (i = 0; i < size; i++)
3200 res ^= p[i];
3201
3202 return ~res;
3203 }
3204
3205 static u8 wq_sig(void *wqe)
3206 {
3207 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3208 }
3209
3210 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3211 void *wqe, int *sz)
3212 {
3213 struct mlx5_wqe_inline_seg *seg;
3214 void *qend = qp->sq.qend;
3215 void *addr;
3216 int inl = 0;
3217 int copy;
3218 int len;
3219 int i;
3220
3221 seg = wqe;
3222 wqe += sizeof(*seg);
3223 for (i = 0; i < wr->num_sge; i++) {
3224 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3225 len = wr->sg_list[i].length;
3226 inl += len;
3227
3228 if (unlikely(inl > qp->max_inline_data))
3229 return -ENOMEM;
3230
3231 if (unlikely(wqe + len > qend)) {
3232 copy = qend - wqe;
3233 memcpy(wqe, addr, copy);
3234 addr += copy;
3235 len -= copy;
3236 wqe = mlx5_get_send_wqe(qp, 0);
3237 }
3238 memcpy(wqe, addr, len);
3239 wqe += len;
3240 }
3241
3242 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3243
3244 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3245
3246 return 0;
3247 }
3248
3249 static u16 prot_field_size(enum ib_signature_type type)
3250 {
3251 switch (type) {
3252 case IB_SIG_TYPE_T10_DIF:
3253 return MLX5_DIF_SIZE;
3254 default:
3255 return 0;
3256 }
3257 }
3258
3259 static u8 bs_selector(int block_size)
3260 {
3261 switch (block_size) {
3262 case 512: return 0x1;
3263 case 520: return 0x2;
3264 case 4096: return 0x3;
3265 case 4160: return 0x4;
3266 case 1073741824: return 0x5;
3267 default: return 0;
3268 }
3269 }
3270
3271 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3272 struct mlx5_bsf_inl *inl)
3273 {
3274 /* Valid inline section and allow BSF refresh */
3275 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3276 MLX5_BSF_REFRESH_DIF);
3277 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3278 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3279 /* repeating block */
3280 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3281 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3282 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3283
3284 if (domain->sig.dif.ref_remap)
3285 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3286
3287 if (domain->sig.dif.app_escape) {
3288 if (domain->sig.dif.ref_escape)
3289 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3290 else
3291 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3292 }
3293
3294 inl->dif_app_bitmask_check =
3295 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3296 }
3297
3298 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3299 struct ib_sig_attrs *sig_attrs,
3300 struct mlx5_bsf *bsf, u32 data_size)
3301 {
3302 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3303 struct mlx5_bsf_basic *basic = &bsf->basic;
3304 struct ib_sig_domain *mem = &sig_attrs->mem;
3305 struct ib_sig_domain *wire = &sig_attrs->wire;
3306
3307 memset(bsf, 0, sizeof(*bsf));
3308
3309 /* Basic + Extended + Inline */
3310 basic->bsf_size_sbs = 1 << 7;
3311 /* Input domain check byte mask */
3312 basic->check_byte_mask = sig_attrs->check_mask;
3313 basic->raw_data_size = cpu_to_be32(data_size);
3314
3315 /* Memory domain */
3316 switch (sig_attrs->mem.sig_type) {
3317 case IB_SIG_TYPE_NONE:
3318 break;
3319 case IB_SIG_TYPE_T10_DIF:
3320 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3321 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3322 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3323 break;
3324 default:
3325 return -EINVAL;
3326 }
3327
3328 /* Wire domain */
3329 switch (sig_attrs->wire.sig_type) {
3330 case IB_SIG_TYPE_NONE:
3331 break;
3332 case IB_SIG_TYPE_T10_DIF:
3333 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3334 mem->sig_type == wire->sig_type) {
3335 /* Same block structure */
3336 basic->bsf_size_sbs |= 1 << 4;
3337 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3338 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3339 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3340 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3341 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3342 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3343 } else
3344 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3345
3346 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3347 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3348 break;
3349 default:
3350 return -EINVAL;
3351 }
3352
3353 return 0;
3354 }
3355
3356 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3357 struct mlx5_ib_qp *qp, void **seg, int *size)
3358 {
3359 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3360 struct ib_mr *sig_mr = wr->sig_mr;
3361 struct mlx5_bsf *bsf;
3362 u32 data_len = wr->wr.sg_list->length;
3363 u32 data_key = wr->wr.sg_list->lkey;
3364 u64 data_va = wr->wr.sg_list->addr;
3365 int ret;
3366 int wqe_size;
3367
3368 if (!wr->prot ||
3369 (data_key == wr->prot->lkey &&
3370 data_va == wr->prot->addr &&
3371 data_len == wr->prot->length)) {
3372 /**
3373 * Source domain doesn't contain signature information
3374 * or data and protection are interleaved in memory.
3375 * So need construct:
3376 * ------------------
3377 * | data_klm |
3378 * ------------------
3379 * | BSF |
3380 * ------------------
3381 **/
3382 struct mlx5_klm *data_klm = *seg;
3383
3384 data_klm->bcount = cpu_to_be32(data_len);
3385 data_klm->key = cpu_to_be32(data_key);
3386 data_klm->va = cpu_to_be64(data_va);
3387 wqe_size = ALIGN(sizeof(*data_klm), 64);
3388 } else {
3389 /**
3390 * Source domain contains signature information
3391 * So need construct a strided block format:
3392 * ---------------------------
3393 * | stride_block_ctrl |
3394 * ---------------------------
3395 * | data_klm |
3396 * ---------------------------
3397 * | prot_klm |
3398 * ---------------------------
3399 * | BSF |
3400 * ---------------------------
3401 **/
3402 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3403 struct mlx5_stride_block_entry *data_sentry;
3404 struct mlx5_stride_block_entry *prot_sentry;
3405 u32 prot_key = wr->prot->lkey;
3406 u64 prot_va = wr->prot->addr;
3407 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3408 int prot_size;
3409
3410 sblock_ctrl = *seg;
3411 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3412 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3413
3414 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3415 if (!prot_size) {
3416 pr_err("Bad block size given: %u\n", block_size);
3417 return -EINVAL;
3418 }
3419 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3420 prot_size);
3421 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3422 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3423 sblock_ctrl->num_entries = cpu_to_be16(2);
3424
3425 data_sentry->bcount = cpu_to_be16(block_size);
3426 data_sentry->key = cpu_to_be32(data_key);
3427 data_sentry->va = cpu_to_be64(data_va);
3428 data_sentry->stride = cpu_to_be16(block_size);
3429
3430 prot_sentry->bcount = cpu_to_be16(prot_size);
3431 prot_sentry->key = cpu_to_be32(prot_key);
3432 prot_sentry->va = cpu_to_be64(prot_va);
3433 prot_sentry->stride = cpu_to_be16(prot_size);
3434
3435 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3436 sizeof(*prot_sentry), 64);
3437 }
3438
3439 *seg += wqe_size;
3440 *size += wqe_size / 16;
3441 if (unlikely((*seg == qp->sq.qend)))
3442 *seg = mlx5_get_send_wqe(qp, 0);
3443
3444 bsf = *seg;
3445 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3446 if (ret)
3447 return -EINVAL;
3448
3449 *seg += sizeof(*bsf);
3450 *size += sizeof(*bsf) / 16;
3451 if (unlikely((*seg == qp->sq.qend)))
3452 *seg = mlx5_get_send_wqe(qp, 0);
3453
3454 return 0;
3455 }
3456
3457 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3458 struct ib_sig_handover_wr *wr, u32 nelements,
3459 u32 length, u32 pdn)
3460 {
3461 struct ib_mr *sig_mr = wr->sig_mr;
3462 u32 sig_key = sig_mr->rkey;
3463 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3464
3465 memset(seg, 0, sizeof(*seg));
3466
3467 seg->flags = get_umr_flags(wr->access_flags) |
3468 MLX5_MKC_ACCESS_MODE_KLMS;
3469 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3470 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3471 MLX5_MKEY_BSF_EN | pdn);
3472 seg->len = cpu_to_be64(length);
3473 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3474 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3475 }
3476
3477 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3478 u32 nelements)
3479 {
3480 memset(umr, 0, sizeof(*umr));
3481
3482 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3483 umr->klm_octowords = get_klm_octo(nelements);
3484 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3485 umr->mkey_mask = sig_mkey_mask();
3486 }
3487
3488
3489 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3490 void **seg, int *size)
3491 {
3492 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3493 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3494 u32 pdn = get_pd(qp)->pdn;
3495 u32 klm_oct_size;
3496 int region_len, ret;
3497
3498 if (unlikely(wr->wr.num_sge != 1) ||
3499 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3500 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3501 unlikely(!sig_mr->sig->sig_status_checked))
3502 return -EINVAL;
3503
3504 /* length of the protected region, data + protection */
3505 region_len = wr->wr.sg_list->length;
3506 if (wr->prot &&
3507 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3508 wr->prot->addr != wr->wr.sg_list->addr ||
3509 wr->prot->length != wr->wr.sg_list->length))
3510 region_len += wr->prot->length;
3511
3512 /**
3513 * KLM octoword size - if protection was provided
3514 * then we use strided block format (3 octowords),
3515 * else we use single KLM (1 octoword)
3516 **/
3517 klm_oct_size = wr->prot ? 3 : 1;
3518
3519 set_sig_umr_segment(*seg, klm_oct_size);
3520 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3521 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3522 if (unlikely((*seg == qp->sq.qend)))
3523 *seg = mlx5_get_send_wqe(qp, 0);
3524
3525 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3526 *seg += sizeof(struct mlx5_mkey_seg);
3527 *size += sizeof(struct mlx5_mkey_seg) / 16;
3528 if (unlikely((*seg == qp->sq.qend)))
3529 *seg = mlx5_get_send_wqe(qp, 0);
3530
3531 ret = set_sig_data_segment(wr, qp, seg, size);
3532 if (ret)
3533 return ret;
3534
3535 sig_mr->sig->sig_status_checked = false;
3536 return 0;
3537 }
3538
3539 static int set_psv_wr(struct ib_sig_domain *domain,
3540 u32 psv_idx, void **seg, int *size)
3541 {
3542 struct mlx5_seg_set_psv *psv_seg = *seg;
3543
3544 memset(psv_seg, 0, sizeof(*psv_seg));
3545 psv_seg->psv_num = cpu_to_be32(psv_idx);
3546 switch (domain->sig_type) {
3547 case IB_SIG_TYPE_NONE:
3548 break;
3549 case IB_SIG_TYPE_T10_DIF:
3550 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3551 domain->sig.dif.app_tag);
3552 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3553 break;
3554 default:
3555 pr_err("Bad signature type given.\n");
3556 return 1;
3557 }
3558
3559 *seg += sizeof(*psv_seg);
3560 *size += sizeof(*psv_seg) / 16;
3561
3562 return 0;
3563 }
3564
3565 static int set_reg_wr(struct mlx5_ib_qp *qp,
3566 struct ib_reg_wr *wr,
3567 void **seg, int *size)
3568 {
3569 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3570 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3571
3572 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3573 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3574 "Invalid IB_SEND_INLINE send flag\n");
3575 return -EINVAL;
3576 }
3577
3578 set_reg_umr_seg(*seg, mr);
3579 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3580 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3581 if (unlikely((*seg == qp->sq.qend)))
3582 *seg = mlx5_get_send_wqe(qp, 0);
3583
3584 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3585 *seg += sizeof(struct mlx5_mkey_seg);
3586 *size += sizeof(struct mlx5_mkey_seg) / 16;
3587 if (unlikely((*seg == qp->sq.qend)))
3588 *seg = mlx5_get_send_wqe(qp, 0);
3589
3590 set_reg_data_seg(*seg, mr, pd);
3591 *seg += sizeof(struct mlx5_wqe_data_seg);
3592 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3593
3594 return 0;
3595 }
3596
3597 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3598 {
3599 set_linv_umr_seg(*seg);
3600 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3601 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3602 if (unlikely((*seg == qp->sq.qend)))
3603 *seg = mlx5_get_send_wqe(qp, 0);
3604 set_linv_mkey_seg(*seg);
3605 *seg += sizeof(struct mlx5_mkey_seg);
3606 *size += sizeof(struct mlx5_mkey_seg) / 16;
3607 if (unlikely((*seg == qp->sq.qend)))
3608 *seg = mlx5_get_send_wqe(qp, 0);
3609 }
3610
3611 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3612 {
3613 __be32 *p = NULL;
3614 int tidx = idx;
3615 int i, j;
3616
3617 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3618 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3619 if ((i & 0xf) == 0) {
3620 void *buf = mlx5_get_send_wqe(qp, tidx);
3621 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3622 p = buf;
3623 j = 0;
3624 }
3625 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3626 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3627 be32_to_cpu(p[j + 3]));
3628 }
3629 }
3630
3631 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3632 unsigned bytecnt, struct mlx5_ib_qp *qp)
3633 {
3634 while (bytecnt > 0) {
3635 __iowrite64_copy(dst++, src++, 8);
3636 __iowrite64_copy(dst++, src++, 8);
3637 __iowrite64_copy(dst++, src++, 8);
3638 __iowrite64_copy(dst++, src++, 8);
3639 __iowrite64_copy(dst++, src++, 8);
3640 __iowrite64_copy(dst++, src++, 8);
3641 __iowrite64_copy(dst++, src++, 8);
3642 __iowrite64_copy(dst++, src++, 8);
3643 bytecnt -= 64;
3644 if (unlikely(src == qp->sq.qend))
3645 src = mlx5_get_send_wqe(qp, 0);
3646 }
3647 }
3648
3649 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3650 {
3651 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3652 wr->send_flags & IB_SEND_FENCE))
3653 return MLX5_FENCE_MODE_STRONG_ORDERING;
3654
3655 if (unlikely(fence)) {
3656 if (wr->send_flags & IB_SEND_FENCE)
3657 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3658 else
3659 return fence;
3660 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3661 return MLX5_FENCE_MODE_FENCE;
3662 }
3663
3664 return 0;
3665 }
3666
3667 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3668 struct mlx5_wqe_ctrl_seg **ctrl,
3669 struct ib_send_wr *wr, unsigned *idx,
3670 int *size, int nreq)
3671 {
3672 int err = 0;
3673
3674 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
3675 err = -ENOMEM;
3676 return err;
3677 }
3678
3679 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3680 *seg = mlx5_get_send_wqe(qp, *idx);
3681 *ctrl = *seg;
3682 *(uint32_t *)(*seg + 8) = 0;
3683 (*ctrl)->imm = send_ieth(wr);
3684 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3685 (wr->send_flags & IB_SEND_SIGNALED ?
3686 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3687 (wr->send_flags & IB_SEND_SOLICITED ?
3688 MLX5_WQE_CTRL_SOLICITED : 0);
3689
3690 *seg += sizeof(**ctrl);
3691 *size = sizeof(**ctrl) / 16;
3692
3693 return err;
3694 }
3695
3696 static void finish_wqe(struct mlx5_ib_qp *qp,
3697 struct mlx5_wqe_ctrl_seg *ctrl,
3698 u8 size, unsigned idx, u64 wr_id,
3699 int nreq, u8 fence, u8 next_fence,
3700 u32 mlx5_opcode)
3701 {
3702 u8 opmod = 0;
3703
3704 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3705 mlx5_opcode | ((u32)opmod << 24));
3706 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3707 ctrl->fm_ce_se |= fence;
3708 qp->fm_cache = next_fence;
3709 if (unlikely(qp->wq_sig))
3710 ctrl->signature = wq_sig(ctrl);
3711
3712 qp->sq.wrid[idx] = wr_id;
3713 qp->sq.w_list[idx].opcode = mlx5_opcode;
3714 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3715 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3716 qp->sq.w_list[idx].next = qp->sq.cur_post;
3717 }
3718
3719
3720 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3721 struct ib_send_wr **bad_wr)
3722 {
3723 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3724 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3725 struct mlx5_core_dev *mdev = dev->mdev;
3726 struct mlx5_ib_qp *qp;
3727 struct mlx5_ib_mr *mr;
3728 struct mlx5_wqe_data_seg *dpseg;
3729 struct mlx5_wqe_xrc_seg *xrc;
3730 struct mlx5_bf *bf;
3731 int uninitialized_var(size);
3732 void *qend;
3733 unsigned long flags;
3734 unsigned idx;
3735 int err = 0;
3736 int inl = 0;
3737 int num_sge;
3738 void *seg;
3739 int nreq;
3740 int i;
3741 u8 next_fence = 0;
3742 u8 fence;
3743
3744 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3745 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3746
3747 qp = to_mqp(ibqp);
3748 bf = qp->bf;
3749 qend = qp->sq.qend;
3750
3751 spin_lock_irqsave(&qp->sq.lock, flags);
3752
3753 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3754 err = -EIO;
3755 *bad_wr = wr;
3756 nreq = 0;
3757 goto out;
3758 }
3759
3760 for (nreq = 0; wr; nreq++, wr = wr->next) {
3761 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3762 mlx5_ib_warn(dev, "\n");
3763 err = -EINVAL;
3764 *bad_wr = wr;
3765 goto out;
3766 }
3767
3768 fence = qp->fm_cache;
3769 num_sge = wr->num_sge;
3770 if (unlikely(num_sge > qp->sq.max_gs)) {
3771 mlx5_ib_warn(dev, "\n");
3772 err = -ENOMEM;
3773 *bad_wr = wr;
3774 goto out;
3775 }
3776
3777 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3778 if (err) {
3779 mlx5_ib_warn(dev, "\n");
3780 err = -ENOMEM;
3781 *bad_wr = wr;
3782 goto out;
3783 }
3784
3785 switch (ibqp->qp_type) {
3786 case IB_QPT_XRC_INI:
3787 xrc = seg;
3788 seg += sizeof(*xrc);
3789 size += sizeof(*xrc) / 16;
3790 /* fall through */
3791 case IB_QPT_RC:
3792 switch (wr->opcode) {
3793 case IB_WR_RDMA_READ:
3794 case IB_WR_RDMA_WRITE:
3795 case IB_WR_RDMA_WRITE_WITH_IMM:
3796 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3797 rdma_wr(wr)->rkey);
3798 seg += sizeof(struct mlx5_wqe_raddr_seg);
3799 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3800 break;
3801
3802 case IB_WR_ATOMIC_CMP_AND_SWP:
3803 case IB_WR_ATOMIC_FETCH_AND_ADD:
3804 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3805 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3806 err = -ENOSYS;
3807 *bad_wr = wr;
3808 goto out;
3809
3810 case IB_WR_LOCAL_INV:
3811 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3812 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3813 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3814 set_linv_wr(qp, &seg, &size);
3815 num_sge = 0;
3816 break;
3817
3818 case IB_WR_REG_MR:
3819 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3820 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3821 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3822 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3823 if (err) {
3824 *bad_wr = wr;
3825 goto out;
3826 }
3827 num_sge = 0;
3828 break;
3829
3830 case IB_WR_REG_SIG_MR:
3831 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3832 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3833
3834 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3835 err = set_sig_umr_wr(wr, qp, &seg, &size);
3836 if (err) {
3837 mlx5_ib_warn(dev, "\n");
3838 *bad_wr = wr;
3839 goto out;
3840 }
3841
3842 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3843 nreq, get_fence(fence, wr),
3844 next_fence, MLX5_OPCODE_UMR);
3845 /*
3846 * SET_PSV WQEs are not signaled and solicited
3847 * on error
3848 */
3849 wr->send_flags &= ~IB_SEND_SIGNALED;
3850 wr->send_flags |= IB_SEND_SOLICITED;
3851 err = begin_wqe(qp, &seg, &ctrl, wr,
3852 &idx, &size, nreq);
3853 if (err) {
3854 mlx5_ib_warn(dev, "\n");
3855 err = -ENOMEM;
3856 *bad_wr = wr;
3857 goto out;
3858 }
3859
3860 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3861 mr->sig->psv_memory.psv_idx, &seg,
3862 &size);
3863 if (err) {
3864 mlx5_ib_warn(dev, "\n");
3865 *bad_wr = wr;
3866 goto out;
3867 }
3868
3869 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3870 nreq, get_fence(fence, wr),
3871 next_fence, MLX5_OPCODE_SET_PSV);
3872 err = begin_wqe(qp, &seg, &ctrl, wr,
3873 &idx, &size, nreq);
3874 if (err) {
3875 mlx5_ib_warn(dev, "\n");
3876 err = -ENOMEM;
3877 *bad_wr = wr;
3878 goto out;
3879 }
3880
3881 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3882 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3883 mr->sig->psv_wire.psv_idx, &seg,
3884 &size);
3885 if (err) {
3886 mlx5_ib_warn(dev, "\n");
3887 *bad_wr = wr;
3888 goto out;
3889 }
3890
3891 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3892 nreq, get_fence(fence, wr),
3893 next_fence, MLX5_OPCODE_SET_PSV);
3894 num_sge = 0;
3895 goto skip_psv;
3896
3897 default:
3898 break;
3899 }
3900 break;
3901
3902 case IB_QPT_UC:
3903 switch (wr->opcode) {
3904 case IB_WR_RDMA_WRITE:
3905 case IB_WR_RDMA_WRITE_WITH_IMM:
3906 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3907 rdma_wr(wr)->rkey);
3908 seg += sizeof(struct mlx5_wqe_raddr_seg);
3909 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3910 break;
3911
3912 default:
3913 break;
3914 }
3915 break;
3916
3917 case IB_QPT_SMI:
3918 case MLX5_IB_QPT_HW_GSI:
3919 set_datagram_seg(seg, wr);
3920 seg += sizeof(struct mlx5_wqe_datagram_seg);
3921 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3922 if (unlikely((seg == qend)))
3923 seg = mlx5_get_send_wqe(qp, 0);
3924 break;
3925 case IB_QPT_UD:
3926 set_datagram_seg(seg, wr);
3927 seg += sizeof(struct mlx5_wqe_datagram_seg);
3928 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3929
3930 if (unlikely((seg == qend)))
3931 seg = mlx5_get_send_wqe(qp, 0);
3932
3933 /* handle qp that supports ud offload */
3934 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
3935 struct mlx5_wqe_eth_pad *pad;
3936
3937 pad = seg;
3938 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
3939 seg += sizeof(struct mlx5_wqe_eth_pad);
3940 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
3941
3942 seg = set_eth_seg(seg, wr, qend, qp, &size);
3943
3944 if (unlikely((seg == qend)))
3945 seg = mlx5_get_send_wqe(qp, 0);
3946 }
3947 break;
3948 case MLX5_IB_QPT_REG_UMR:
3949 if (wr->opcode != MLX5_IB_WR_UMR) {
3950 err = -EINVAL;
3951 mlx5_ib_warn(dev, "bad opcode\n");
3952 goto out;
3953 }
3954 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3955 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3956 set_reg_umr_segment(seg, wr);
3957 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3958 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3959 if (unlikely((seg == qend)))
3960 seg = mlx5_get_send_wqe(qp, 0);
3961 set_reg_mkey_segment(seg, wr);
3962 seg += sizeof(struct mlx5_mkey_seg);
3963 size += sizeof(struct mlx5_mkey_seg) / 16;
3964 if (unlikely((seg == qend)))
3965 seg = mlx5_get_send_wqe(qp, 0);
3966 break;
3967
3968 default:
3969 break;
3970 }
3971
3972 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3973 int uninitialized_var(sz);
3974
3975 err = set_data_inl_seg(qp, wr, seg, &sz);
3976 if (unlikely(err)) {
3977 mlx5_ib_warn(dev, "\n");
3978 *bad_wr = wr;
3979 goto out;
3980 }
3981 inl = 1;
3982 size += sz;
3983 } else {
3984 dpseg = seg;
3985 for (i = 0; i < num_sge; i++) {
3986 if (unlikely(dpseg == qend)) {
3987 seg = mlx5_get_send_wqe(qp, 0);
3988 dpseg = seg;
3989 }
3990 if (likely(wr->sg_list[i].length)) {
3991 set_data_ptr_seg(dpseg, wr->sg_list + i);
3992 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3993 dpseg++;
3994 }
3995 }
3996 }
3997
3998 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3999 get_fence(fence, wr), next_fence,
4000 mlx5_ib_opcode[wr->opcode]);
4001 skip_psv:
4002 if (0)
4003 dump_wqe(qp, idx, size);
4004 }
4005
4006 out:
4007 if (likely(nreq)) {
4008 qp->sq.head += nreq;
4009
4010 /* Make sure that descriptors are written before
4011 * updating doorbell record and ringing the doorbell
4012 */
4013 wmb();
4014
4015 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4016
4017 /* Make sure doorbell record is visible to the HCA before
4018 * we hit doorbell */
4019 wmb();
4020
4021 if (bf->need_lock)
4022 spin_lock(&bf->lock);
4023 else
4024 __acquire(&bf->lock);
4025
4026 /* TBD enable WC */
4027 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4028 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4029 /* wc_wmb(); */
4030 } else {
4031 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4032 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4033 /* Make sure doorbells don't leak out of SQ spinlock
4034 * and reach the HCA out of order.
4035 */
4036 mmiowb();
4037 }
4038 bf->offset ^= bf->buf_size;
4039 if (bf->need_lock)
4040 spin_unlock(&bf->lock);
4041 else
4042 __release(&bf->lock);
4043 }
4044
4045 spin_unlock_irqrestore(&qp->sq.lock, flags);
4046
4047 return err;
4048 }
4049
4050 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4051 {
4052 sig->signature = calc_sig(sig, size);
4053 }
4054
4055 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4056 struct ib_recv_wr **bad_wr)
4057 {
4058 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4059 struct mlx5_wqe_data_seg *scat;
4060 struct mlx5_rwqe_sig *sig;
4061 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4062 struct mlx5_core_dev *mdev = dev->mdev;
4063 unsigned long flags;
4064 int err = 0;
4065 int nreq;
4066 int ind;
4067 int i;
4068
4069 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4070 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4071
4072 spin_lock_irqsave(&qp->rq.lock, flags);
4073
4074 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4075 err = -EIO;
4076 *bad_wr = wr;
4077 nreq = 0;
4078 goto out;
4079 }
4080
4081 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4082
4083 for (nreq = 0; wr; nreq++, wr = wr->next) {
4084 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4085 err = -ENOMEM;
4086 *bad_wr = wr;
4087 goto out;
4088 }
4089
4090 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4091 err = -EINVAL;
4092 *bad_wr = wr;
4093 goto out;
4094 }
4095
4096 scat = get_recv_wqe(qp, ind);
4097 if (qp->wq_sig)
4098 scat++;
4099
4100 for (i = 0; i < wr->num_sge; i++)
4101 set_data_ptr_seg(scat + i, wr->sg_list + i);
4102
4103 if (i < qp->rq.max_gs) {
4104 scat[i].byte_count = 0;
4105 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4106 scat[i].addr = 0;
4107 }
4108
4109 if (qp->wq_sig) {
4110 sig = (struct mlx5_rwqe_sig *)scat;
4111 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4112 }
4113
4114 qp->rq.wrid[ind] = wr->wr_id;
4115
4116 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4117 }
4118
4119 out:
4120 if (likely(nreq)) {
4121 qp->rq.head += nreq;
4122
4123 /* Make sure that descriptors are written before
4124 * doorbell record.
4125 */
4126 wmb();
4127
4128 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4129 }
4130
4131 spin_unlock_irqrestore(&qp->rq.lock, flags);
4132
4133 return err;
4134 }
4135
4136 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4137 {
4138 switch (mlx5_state) {
4139 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4140 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4141 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4142 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4143 case MLX5_QP_STATE_SQ_DRAINING:
4144 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4145 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4146 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4147 default: return -1;
4148 }
4149 }
4150
4151 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4152 {
4153 switch (mlx5_mig_state) {
4154 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4155 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4156 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4157 default: return -1;
4158 }
4159 }
4160
4161 static int to_ib_qp_access_flags(int mlx5_flags)
4162 {
4163 int ib_flags = 0;
4164
4165 if (mlx5_flags & MLX5_QP_BIT_RRE)
4166 ib_flags |= IB_ACCESS_REMOTE_READ;
4167 if (mlx5_flags & MLX5_QP_BIT_RWE)
4168 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4169 if (mlx5_flags & MLX5_QP_BIT_RAE)
4170 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4171
4172 return ib_flags;
4173 }
4174
4175 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4176 struct mlx5_qp_path *path)
4177 {
4178 struct mlx5_core_dev *dev = ibdev->mdev;
4179
4180 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4181 ib_ah_attr->port_num = path->port;
4182
4183 if (ib_ah_attr->port_num == 0 ||
4184 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4185 return;
4186
4187 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4188
4189 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4190 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4191 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4192 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4193 if (ib_ah_attr->ah_flags) {
4194 ib_ah_attr->grh.sgid_index = path->mgid_index;
4195 ib_ah_attr->grh.hop_limit = path->hop_limit;
4196 ib_ah_attr->grh.traffic_class =
4197 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4198 ib_ah_attr->grh.flow_label =
4199 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4200 memcpy(ib_ah_attr->grh.dgid.raw,
4201 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4202 }
4203 }
4204
4205 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4206 struct mlx5_ib_sq *sq,
4207 u8 *sq_state)
4208 {
4209 void *out;
4210 void *sqc;
4211 int inlen;
4212 int err;
4213
4214 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4215 out = mlx5_vzalloc(inlen);
4216 if (!out)
4217 return -ENOMEM;
4218
4219 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4220 if (err)
4221 goto out;
4222
4223 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4224 *sq_state = MLX5_GET(sqc, sqc, state);
4225 sq->state = *sq_state;
4226
4227 out:
4228 kvfree(out);
4229 return err;
4230 }
4231
4232 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4233 struct mlx5_ib_rq *rq,
4234 u8 *rq_state)
4235 {
4236 void *out;
4237 void *rqc;
4238 int inlen;
4239 int err;
4240
4241 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4242 out = mlx5_vzalloc(inlen);
4243 if (!out)
4244 return -ENOMEM;
4245
4246 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4247 if (err)
4248 goto out;
4249
4250 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4251 *rq_state = MLX5_GET(rqc, rqc, state);
4252 rq->state = *rq_state;
4253
4254 out:
4255 kvfree(out);
4256 return err;
4257 }
4258
4259 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4260 struct mlx5_ib_qp *qp, u8 *qp_state)
4261 {
4262 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4263 [MLX5_RQC_STATE_RST] = {
4264 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4265 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4266 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4267 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4268 },
4269 [MLX5_RQC_STATE_RDY] = {
4270 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4271 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4272 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4273 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4274 },
4275 [MLX5_RQC_STATE_ERR] = {
4276 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4277 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4278 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4279 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4280 },
4281 [MLX5_RQ_STATE_NA] = {
4282 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4283 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4284 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4285 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4286 },
4287 };
4288
4289 *qp_state = sqrq_trans[rq_state][sq_state];
4290
4291 if (*qp_state == MLX5_QP_STATE_BAD) {
4292 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4293 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4294 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4295 return -EINVAL;
4296 }
4297
4298 if (*qp_state == MLX5_QP_STATE)
4299 *qp_state = qp->state;
4300
4301 return 0;
4302 }
4303
4304 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4305 struct mlx5_ib_qp *qp,
4306 u8 *raw_packet_qp_state)
4307 {
4308 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4309 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4310 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4311 int err;
4312 u8 sq_state = MLX5_SQ_STATE_NA;
4313 u8 rq_state = MLX5_RQ_STATE_NA;
4314
4315 if (qp->sq.wqe_cnt) {
4316 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4317 if (err)
4318 return err;
4319 }
4320
4321 if (qp->rq.wqe_cnt) {
4322 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4323 if (err)
4324 return err;
4325 }
4326
4327 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4328 raw_packet_qp_state);
4329 }
4330
4331 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4332 struct ib_qp_attr *qp_attr)
4333 {
4334 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4335 struct mlx5_qp_context *context;
4336 int mlx5_state;
4337 u32 *outb;
4338 int err = 0;
4339
4340 outb = kzalloc(outlen, GFP_KERNEL);
4341 if (!outb)
4342 return -ENOMEM;
4343
4344 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4345 outlen);
4346 if (err)
4347 goto out;
4348
4349 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4350 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4351
4352 mlx5_state = be32_to_cpu(context->flags) >> 28;
4353
4354 qp->state = to_ib_qp_state(mlx5_state);
4355 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4356 qp_attr->path_mig_state =
4357 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4358 qp_attr->qkey = be32_to_cpu(context->qkey);
4359 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4360 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4361 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4362 qp_attr->qp_access_flags =
4363 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4364
4365 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4366 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4367 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4368 qp_attr->alt_pkey_index =
4369 be16_to_cpu(context->alt_path.pkey_index);
4370 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4371 }
4372
4373 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4374 qp_attr->port_num = context->pri_path.port;
4375
4376 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4377 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4378
4379 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4380
4381 qp_attr->max_dest_rd_atomic =
4382 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4383 qp_attr->min_rnr_timer =
4384 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4385 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4386 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4387 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4388 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4389
4390 out:
4391 kfree(outb);
4392 return err;
4393 }
4394
4395 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4396 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4397 {
4398 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4399 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4400 int err = 0;
4401 u8 raw_packet_qp_state;
4402
4403 if (ibqp->rwq_ind_tbl)
4404 return -ENOSYS;
4405
4406 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4407 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4408 qp_init_attr);
4409
4410 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4411 /*
4412 * Wait for any outstanding page faults, in case the user frees memory
4413 * based upon this query's result.
4414 */
4415 flush_workqueue(mlx5_ib_page_fault_wq);
4416 #endif
4417
4418 mutex_lock(&qp->mutex);
4419
4420 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4421 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4422 if (err)
4423 goto out;
4424 qp->state = raw_packet_qp_state;
4425 qp_attr->port_num = 1;
4426 } else {
4427 err = query_qp_attr(dev, qp, qp_attr);
4428 if (err)
4429 goto out;
4430 }
4431
4432 qp_attr->qp_state = qp->state;
4433 qp_attr->cur_qp_state = qp_attr->qp_state;
4434 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4435 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4436
4437 if (!ibqp->uobject) {
4438 qp_attr->cap.max_send_wr = qp->sq.max_post;
4439 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4440 qp_init_attr->qp_context = ibqp->qp_context;
4441 } else {
4442 qp_attr->cap.max_send_wr = 0;
4443 qp_attr->cap.max_send_sge = 0;
4444 }
4445
4446 qp_init_attr->qp_type = ibqp->qp_type;
4447 qp_init_attr->recv_cq = ibqp->recv_cq;
4448 qp_init_attr->send_cq = ibqp->send_cq;
4449 qp_init_attr->srq = ibqp->srq;
4450 qp_attr->cap.max_inline_data = qp->max_inline_data;
4451
4452 qp_init_attr->cap = qp_attr->cap;
4453
4454 qp_init_attr->create_flags = 0;
4455 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4456 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4457
4458 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4459 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4460 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4461 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4462 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4463 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4464 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4465 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4466
4467 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4468 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4469
4470 out:
4471 mutex_unlock(&qp->mutex);
4472 return err;
4473 }
4474
4475 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4476 struct ib_ucontext *context,
4477 struct ib_udata *udata)
4478 {
4479 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4480 struct mlx5_ib_xrcd *xrcd;
4481 int err;
4482
4483 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4484 return ERR_PTR(-ENOSYS);
4485
4486 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4487 if (!xrcd)
4488 return ERR_PTR(-ENOMEM);
4489
4490 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4491 if (err) {
4492 kfree(xrcd);
4493 return ERR_PTR(-ENOMEM);
4494 }
4495
4496 return &xrcd->ibxrcd;
4497 }
4498
4499 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4500 {
4501 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4502 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4503 int err;
4504
4505 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4506 if (err) {
4507 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4508 return err;
4509 }
4510
4511 kfree(xrcd);
4512
4513 return 0;
4514 }
4515
4516 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4517 struct ib_wq_init_attr *init_attr)
4518 {
4519 struct mlx5_ib_dev *dev;
4520 __be64 *rq_pas0;
4521 void *in;
4522 void *rqc;
4523 void *wq;
4524 int inlen;
4525 int err;
4526
4527 dev = to_mdev(pd->device);
4528
4529 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4530 in = mlx5_vzalloc(inlen);
4531 if (!in)
4532 return -ENOMEM;
4533
4534 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4535 MLX5_SET(rqc, rqc, mem_rq_type,
4536 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4537 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4538 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4539 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4540 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4541 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4542 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4543 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4544 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4545 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4546 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4547 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4548 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4549 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4550 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4551 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4552 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4553 err = mlx5_core_create_rq(dev->mdev, in, inlen, &rwq->rqn);
4554 kvfree(in);
4555 return err;
4556 }
4557
4558 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4559 struct ib_wq_init_attr *wq_init_attr,
4560 struct mlx5_ib_create_wq *ucmd,
4561 struct mlx5_ib_rwq *rwq)
4562 {
4563 /* Sanity check RQ size before proceeding */
4564 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4565 return -EINVAL;
4566
4567 if (!ucmd->rq_wqe_count)
4568 return -EINVAL;
4569
4570 rwq->wqe_count = ucmd->rq_wqe_count;
4571 rwq->wqe_shift = ucmd->rq_wqe_shift;
4572 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4573 rwq->log_rq_stride = rwq->wqe_shift;
4574 rwq->log_rq_size = ilog2(rwq->wqe_count);
4575 return 0;
4576 }
4577
4578 static int prepare_user_rq(struct ib_pd *pd,
4579 struct ib_wq_init_attr *init_attr,
4580 struct ib_udata *udata,
4581 struct mlx5_ib_rwq *rwq)
4582 {
4583 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4584 struct mlx5_ib_create_wq ucmd = {};
4585 int err;
4586 size_t required_cmd_sz;
4587
4588 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4589 if (udata->inlen < required_cmd_sz) {
4590 mlx5_ib_dbg(dev, "invalid inlen\n");
4591 return -EINVAL;
4592 }
4593
4594 if (udata->inlen > sizeof(ucmd) &&
4595 !ib_is_udata_cleared(udata, sizeof(ucmd),
4596 udata->inlen - sizeof(ucmd))) {
4597 mlx5_ib_dbg(dev, "inlen is not supported\n");
4598 return -EOPNOTSUPP;
4599 }
4600
4601 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4602 mlx5_ib_dbg(dev, "copy failed\n");
4603 return -EFAULT;
4604 }
4605
4606 if (ucmd.comp_mask) {
4607 mlx5_ib_dbg(dev, "invalid comp mask\n");
4608 return -EOPNOTSUPP;
4609 }
4610
4611 if (ucmd.reserved) {
4612 mlx5_ib_dbg(dev, "invalid reserved\n");
4613 return -EOPNOTSUPP;
4614 }
4615
4616 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4617 if (err) {
4618 mlx5_ib_dbg(dev, "err %d\n", err);
4619 return err;
4620 }
4621
4622 err = create_user_rq(dev, pd, rwq, &ucmd);
4623 if (err) {
4624 mlx5_ib_dbg(dev, "err %d\n", err);
4625 if (err)
4626 return err;
4627 }
4628
4629 rwq->user_index = ucmd.user_index;
4630 return 0;
4631 }
4632
4633 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4634 struct ib_wq_init_attr *init_attr,
4635 struct ib_udata *udata)
4636 {
4637 struct mlx5_ib_dev *dev;
4638 struct mlx5_ib_rwq *rwq;
4639 struct mlx5_ib_create_wq_resp resp = {};
4640 size_t min_resp_len;
4641 int err;
4642
4643 if (!udata)
4644 return ERR_PTR(-ENOSYS);
4645
4646 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4647 if (udata->outlen && udata->outlen < min_resp_len)
4648 return ERR_PTR(-EINVAL);
4649
4650 dev = to_mdev(pd->device);
4651 switch (init_attr->wq_type) {
4652 case IB_WQT_RQ:
4653 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4654 if (!rwq)
4655 return ERR_PTR(-ENOMEM);
4656 err = prepare_user_rq(pd, init_attr, udata, rwq);
4657 if (err)
4658 goto err;
4659 err = create_rq(rwq, pd, init_attr);
4660 if (err)
4661 goto err_user_rq;
4662 break;
4663 default:
4664 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4665 init_attr->wq_type);
4666 return ERR_PTR(-EINVAL);
4667 }
4668
4669 rwq->ibwq.wq_num = rwq->rqn;
4670 rwq->ibwq.state = IB_WQS_RESET;
4671 if (udata->outlen) {
4672 resp.response_length = offsetof(typeof(resp), response_length) +
4673 sizeof(resp.response_length);
4674 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4675 if (err)
4676 goto err_copy;
4677 }
4678
4679 return &rwq->ibwq;
4680
4681 err_copy:
4682 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4683 err_user_rq:
4684 destroy_user_rq(pd, rwq);
4685 err:
4686 kfree(rwq);
4687 return ERR_PTR(err);
4688 }
4689
4690 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4691 {
4692 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4693 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4694
4695 mlx5_core_destroy_rq(dev->mdev, rwq->rqn);
4696 destroy_user_rq(wq->pd, rwq);
4697 kfree(rwq);
4698
4699 return 0;
4700 }
4701
4702 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4703 struct ib_rwq_ind_table_init_attr *init_attr,
4704 struct ib_udata *udata)
4705 {
4706 struct mlx5_ib_dev *dev = to_mdev(device);
4707 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4708 int sz = 1 << init_attr->log_ind_tbl_size;
4709 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4710 size_t min_resp_len;
4711 int inlen;
4712 int err;
4713 int i;
4714 u32 *in;
4715 void *rqtc;
4716
4717 if (udata->inlen > 0 &&
4718 !ib_is_udata_cleared(udata, 0,
4719 udata->inlen))
4720 return ERR_PTR(-EOPNOTSUPP);
4721
4722 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4723 if (udata->outlen && udata->outlen < min_resp_len)
4724 return ERR_PTR(-EINVAL);
4725
4726 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4727 if (!rwq_ind_tbl)
4728 return ERR_PTR(-ENOMEM);
4729
4730 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4731 in = mlx5_vzalloc(inlen);
4732 if (!in) {
4733 err = -ENOMEM;
4734 goto err;
4735 }
4736
4737 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4738
4739 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4740 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4741
4742 for (i = 0; i < sz; i++)
4743 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4744
4745 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4746 kvfree(in);
4747
4748 if (err)
4749 goto err;
4750
4751 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4752 if (udata->outlen) {
4753 resp.response_length = offsetof(typeof(resp), response_length) +
4754 sizeof(resp.response_length);
4755 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4756 if (err)
4757 goto err_copy;
4758 }
4759
4760 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4761
4762 err_copy:
4763 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4764 err:
4765 kfree(rwq_ind_tbl);
4766 return ERR_PTR(err);
4767 }
4768
4769 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4770 {
4771 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4772 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4773
4774 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4775
4776 kfree(rwq_ind_tbl);
4777 return 0;
4778 }
4779
4780 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4781 u32 wq_attr_mask, struct ib_udata *udata)
4782 {
4783 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4784 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4785 struct mlx5_ib_modify_wq ucmd = {};
4786 size_t required_cmd_sz;
4787 int curr_wq_state;
4788 int wq_state;
4789 int inlen;
4790 int err;
4791 void *rqc;
4792 void *in;
4793
4794 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4795 if (udata->inlen < required_cmd_sz)
4796 return -EINVAL;
4797
4798 if (udata->inlen > sizeof(ucmd) &&
4799 !ib_is_udata_cleared(udata, sizeof(ucmd),
4800 udata->inlen - sizeof(ucmd)))
4801 return -EOPNOTSUPP;
4802
4803 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4804 return -EFAULT;
4805
4806 if (ucmd.comp_mask || ucmd.reserved)
4807 return -EOPNOTSUPP;
4808
4809 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4810 in = mlx5_vzalloc(inlen);
4811 if (!in)
4812 return -ENOMEM;
4813
4814 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4815
4816 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4817 wq_attr->curr_wq_state : wq->state;
4818 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4819 wq_attr->wq_state : curr_wq_state;
4820 if (curr_wq_state == IB_WQS_ERR)
4821 curr_wq_state = MLX5_RQC_STATE_ERR;
4822 if (wq_state == IB_WQS_ERR)
4823 wq_state = MLX5_RQC_STATE_ERR;
4824 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4825 MLX5_SET(rqc, rqc, state, wq_state);
4826
4827 err = mlx5_core_modify_rq(dev->mdev, rwq->rqn, in, inlen);
4828 kvfree(in);
4829 if (!err)
4830 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4831
4832 return err;
4833 }
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