]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/infiniband/hw/mlx5/qp.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:


df72056c2055626188be7297d2cc1a2b0d2ebbab
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
38 #include "mlx5_ib.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 };
57
58 static const u32 mlx5_ib_opcode[] = {
59 [IB_WR_SEND] = MLX5_OPCODE_SEND,
60 [IB_WR_LSO] = MLX5_OPCODE_LSO,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75 struct mlx5_wqe_eth_pad {
76 u8 rsvd0[16];
77 };
78
79 enum raw_qp_set_mask_map {
80 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
81 MLX5_RAW_QP_RATE_LIMIT = 1UL << 1,
82 };
83
84 struct mlx5_modify_raw_qp_param {
85 u16 operation;
86
87 u32 set_mask; /* raw_qp_set_mask_map */
88 u32 rate_limit;
89 u8 rq_q_ctr_id;
90 };
91
92 static void get_cqs(enum ib_qp_type qp_type,
93 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
94 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
95
96 static int is_qp0(enum ib_qp_type qp_type)
97 {
98 return qp_type == IB_QPT_SMI;
99 }
100
101 static int is_sqp(enum ib_qp_type qp_type)
102 {
103 return is_qp0(qp_type) || is_qp1(qp_type);
104 }
105
106 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
107 {
108 return mlx5_buf_offset(&qp->buf, offset);
109 }
110
111 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
112 {
113 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
114 }
115
116 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
117 {
118 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
119 }
120
121 /**
122 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
123 *
124 * @qp: QP to copy from.
125 * @send: copy from the send queue when non-zero, use the receive queue
126 * otherwise.
127 * @wqe_index: index to start copying from. For send work queues, the
128 * wqe_index is in units of MLX5_SEND_WQE_BB.
129 * For receive work queue, it is the number of work queue
130 * element in the queue.
131 * @buffer: destination buffer.
132 * @length: maximum number of bytes to copy.
133 *
134 * Copies at least a single WQE, but may copy more data.
135 *
136 * Return: the number of bytes copied, or an error code.
137 */
138 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
139 void *buffer, u32 length,
140 struct mlx5_ib_qp_base *base)
141 {
142 struct ib_device *ibdev = qp->ibqp.device;
143 struct mlx5_ib_dev *dev = to_mdev(ibdev);
144 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
145 size_t offset;
146 size_t wq_end;
147 struct ib_umem *umem = base->ubuffer.umem;
148 u32 first_copy_length;
149 int wqe_length;
150 int ret;
151
152 if (wq->wqe_cnt == 0) {
153 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
154 qp->ibqp.qp_type);
155 return -EINVAL;
156 }
157
158 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
159 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
160
161 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
162 return -EINVAL;
163
164 if (offset > umem->length ||
165 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
166 return -EINVAL;
167
168 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
169 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
170 if (ret)
171 return ret;
172
173 if (send) {
174 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
175 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
176
177 wqe_length = ds * MLX5_WQE_DS_UNITS;
178 } else {
179 wqe_length = 1 << wq->wqe_shift;
180 }
181
182 if (wqe_length <= first_copy_length)
183 return first_copy_length;
184
185 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
186 wqe_length - first_copy_length);
187 if (ret)
188 return ret;
189
190 return wqe_length;
191 }
192
193 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
194 {
195 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
196 struct ib_event event;
197
198 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
199 /* This event is only valid for trans_qps */
200 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
201 }
202
203 if (ibqp->event_handler) {
204 event.device = ibqp->device;
205 event.element.qp = ibqp;
206 switch (type) {
207 case MLX5_EVENT_TYPE_PATH_MIG:
208 event.event = IB_EVENT_PATH_MIG;
209 break;
210 case MLX5_EVENT_TYPE_COMM_EST:
211 event.event = IB_EVENT_COMM_EST;
212 break;
213 case MLX5_EVENT_TYPE_SQ_DRAINED:
214 event.event = IB_EVENT_SQ_DRAINED;
215 break;
216 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
217 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
218 break;
219 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
220 event.event = IB_EVENT_QP_FATAL;
221 break;
222 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
223 event.event = IB_EVENT_PATH_MIG_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
226 event.event = IB_EVENT_QP_REQ_ERR;
227 break;
228 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
229 event.event = IB_EVENT_QP_ACCESS_ERR;
230 break;
231 default:
232 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
233 return;
234 }
235
236 ibqp->event_handler(&event, ibqp->qp_context);
237 }
238 }
239
240 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
241 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
242 {
243 int wqe_size;
244 int wq_size;
245
246 /* Sanity check RQ size before proceeding */
247 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
248 return -EINVAL;
249
250 if (!has_rq) {
251 qp->rq.max_gs = 0;
252 qp->rq.wqe_cnt = 0;
253 qp->rq.wqe_shift = 0;
254 cap->max_recv_wr = 0;
255 cap->max_recv_sge = 0;
256 } else {
257 if (ucmd) {
258 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
259 if (ucmd->rq_wqe_shift > BITS_PER_BYTE * sizeof(ucmd->rq_wqe_shift))
260 return -EINVAL;
261 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
262 if ((1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) < qp->wq_sig)
263 return -EINVAL;
264 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
265 qp->rq.max_post = qp->rq.wqe_cnt;
266 } else {
267 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
268 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
269 wqe_size = roundup_pow_of_two(wqe_size);
270 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
271 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
272 qp->rq.wqe_cnt = wq_size / wqe_size;
273 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
274 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
275 wqe_size,
276 MLX5_CAP_GEN(dev->mdev,
277 max_wqe_sz_rq));
278 return -EINVAL;
279 }
280 qp->rq.wqe_shift = ilog2(wqe_size);
281 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
282 qp->rq.max_post = qp->rq.wqe_cnt;
283 }
284 }
285
286 return 0;
287 }
288
289 static int sq_overhead(struct ib_qp_init_attr *attr)
290 {
291 int size = 0;
292
293 switch (attr->qp_type) {
294 case IB_QPT_XRC_INI:
295 size += sizeof(struct mlx5_wqe_xrc_seg);
296 /* fall through */
297 case IB_QPT_RC:
298 size += sizeof(struct mlx5_wqe_ctrl_seg) +
299 max(sizeof(struct mlx5_wqe_atomic_seg) +
300 sizeof(struct mlx5_wqe_raddr_seg),
301 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
302 sizeof(struct mlx5_mkey_seg));
303 break;
304
305 case IB_QPT_XRC_TGT:
306 return 0;
307
308 case IB_QPT_UC:
309 size += sizeof(struct mlx5_wqe_ctrl_seg) +
310 max(sizeof(struct mlx5_wqe_raddr_seg),
311 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
312 sizeof(struct mlx5_mkey_seg));
313 break;
314
315 case IB_QPT_UD:
316 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
317 size += sizeof(struct mlx5_wqe_eth_pad) +
318 sizeof(struct mlx5_wqe_eth_seg);
319 /* fall through */
320 case IB_QPT_SMI:
321 case MLX5_IB_QPT_HW_GSI:
322 size += sizeof(struct mlx5_wqe_ctrl_seg) +
323 sizeof(struct mlx5_wqe_datagram_seg);
324 break;
325
326 case MLX5_IB_QPT_REG_UMR:
327 size += sizeof(struct mlx5_wqe_ctrl_seg) +
328 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
329 sizeof(struct mlx5_mkey_seg);
330 break;
331
332 default:
333 return -EINVAL;
334 }
335
336 return size;
337 }
338
339 static int calc_send_wqe(struct ib_qp_init_attr *attr)
340 {
341 int inl_size = 0;
342 int size;
343
344 size = sq_overhead(attr);
345 if (size < 0)
346 return size;
347
348 if (attr->cap.max_inline_data) {
349 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
350 attr->cap.max_inline_data;
351 }
352
353 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
354 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
355 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
356 return MLX5_SIG_WQE_SIZE;
357 else
358 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
359 }
360
361 static int get_send_sge(struct ib_qp_init_attr *attr, int wqe_size)
362 {
363 int max_sge;
364
365 if (attr->qp_type == IB_QPT_RC)
366 max_sge = (min_t(int, wqe_size, 512) -
367 sizeof(struct mlx5_wqe_ctrl_seg) -
368 sizeof(struct mlx5_wqe_raddr_seg)) /
369 sizeof(struct mlx5_wqe_data_seg);
370 else if (attr->qp_type == IB_QPT_XRC_INI)
371 max_sge = (min_t(int, wqe_size, 512) -
372 sizeof(struct mlx5_wqe_ctrl_seg) -
373 sizeof(struct mlx5_wqe_xrc_seg) -
374 sizeof(struct mlx5_wqe_raddr_seg)) /
375 sizeof(struct mlx5_wqe_data_seg);
376 else
377 max_sge = (wqe_size - sq_overhead(attr)) /
378 sizeof(struct mlx5_wqe_data_seg);
379
380 return min_t(int, max_sge, wqe_size - sq_overhead(attr) /
381 sizeof(struct mlx5_wqe_data_seg));
382 }
383
384 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
385 struct mlx5_ib_qp *qp)
386 {
387 int wqe_size;
388 int wq_size;
389
390 if (!attr->cap.max_send_wr)
391 return 0;
392
393 wqe_size = calc_send_wqe(attr);
394 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
395 if (wqe_size < 0)
396 return wqe_size;
397
398 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
399 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
400 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
401 return -EINVAL;
402 }
403
404 qp->max_inline_data = wqe_size - sq_overhead(attr) -
405 sizeof(struct mlx5_wqe_inline_seg);
406 attr->cap.max_inline_data = qp->max_inline_data;
407
408 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
409 qp->signature_en = true;
410
411 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
412 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
413 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
414 mlx5_ib_dbg(dev, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
415 attr->cap.max_send_wr, wqe_size, MLX5_SEND_WQE_BB,
416 qp->sq.wqe_cnt,
417 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
418 return -ENOMEM;
419 }
420 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
421 qp->sq.max_gs = get_send_sge(attr, wqe_size);
422 if (qp->sq.max_gs < attr->cap.max_send_sge)
423 return -ENOMEM;
424
425 attr->cap.max_send_sge = qp->sq.max_gs;
426 qp->sq.max_post = wq_size / wqe_size;
427 attr->cap.max_send_wr = qp->sq.max_post;
428
429 return wq_size;
430 }
431
432 static int set_user_buf_size(struct mlx5_ib_dev *dev,
433 struct mlx5_ib_qp *qp,
434 struct mlx5_ib_create_qp *ucmd,
435 struct mlx5_ib_qp_base *base,
436 struct ib_qp_init_attr *attr)
437 {
438 int desc_sz = 1 << qp->sq.wqe_shift;
439
440 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
441 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
442 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
443 return -EINVAL;
444 }
445
446 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
447 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
448 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
449 return -EINVAL;
450 }
451
452 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
453
454 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
455 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
456 qp->sq.wqe_cnt,
457 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
458 return -EINVAL;
459 }
460
461 if (attr->qp_type == IB_QPT_RAW_PACKET ||
462 qp->flags & MLX5_IB_QP_UNDERLAY) {
463 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
464 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
465 } else {
466 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
467 (qp->sq.wqe_cnt << 6);
468 }
469
470 return 0;
471 }
472
473 static int qp_has_rq(struct ib_qp_init_attr *attr)
474 {
475 if (attr->qp_type == IB_QPT_XRC_INI ||
476 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
477 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
478 !attr->cap.max_recv_wr)
479 return 0;
480
481 return 1;
482 }
483
484 static int first_med_bfreg(void)
485 {
486 return 1;
487 }
488
489 enum {
490 /* this is the first blue flame register in the array of bfregs assigned
491 * to a processes. Since we do not use it for blue flame but rather
492 * regular 64 bit doorbells, we do not need a lock for maintaiing
493 * "odd/even" order
494 */
495 NUM_NON_BLUE_FLAME_BFREGS = 1,
496 };
497
498 static int max_bfregs(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi)
499 {
500 return get_num_uars(dev, bfregi) * MLX5_NON_FP_BFREGS_PER_UAR;
501 }
502
503 static int num_med_bfreg(struct mlx5_ib_dev *dev,
504 struct mlx5_bfreg_info *bfregi)
505 {
506 int n;
507
508 n = max_bfregs(dev, bfregi) - bfregi->num_low_latency_bfregs -
509 NUM_NON_BLUE_FLAME_BFREGS;
510
511 return n >= 0 ? n : 0;
512 }
513
514 static int first_hi_bfreg(struct mlx5_ib_dev *dev,
515 struct mlx5_bfreg_info *bfregi)
516 {
517 int med;
518
519 med = num_med_bfreg(dev, bfregi);
520 return ++med;
521 }
522
523 static int alloc_high_class_bfreg(struct mlx5_ib_dev *dev,
524 struct mlx5_bfreg_info *bfregi)
525 {
526 int i;
527
528 for (i = first_hi_bfreg(dev, bfregi); i < max_bfregs(dev, bfregi); i++) {
529 if (!bfregi->count[i]) {
530 bfregi->count[i]++;
531 return i;
532 }
533 }
534
535 return -ENOMEM;
536 }
537
538 static int alloc_med_class_bfreg(struct mlx5_ib_dev *dev,
539 struct mlx5_bfreg_info *bfregi)
540 {
541 int minidx = first_med_bfreg();
542 int i;
543
544 for (i = first_med_bfreg(); i < first_hi_bfreg(dev, bfregi); i++) {
545 if (bfregi->count[i] < bfregi->count[minidx])
546 minidx = i;
547 if (!bfregi->count[minidx])
548 break;
549 }
550
551 bfregi->count[minidx]++;
552 return minidx;
553 }
554
555 static int alloc_bfreg(struct mlx5_ib_dev *dev,
556 struct mlx5_bfreg_info *bfregi,
557 enum mlx5_ib_latency_class lat)
558 {
559 int bfregn = -EINVAL;
560
561 mutex_lock(&bfregi->lock);
562 switch (lat) {
563 case MLX5_IB_LATENCY_CLASS_LOW:
564 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS != 1);
565 bfregn = 0;
566 bfregi->count[bfregn]++;
567 break;
568
569 case MLX5_IB_LATENCY_CLASS_MEDIUM:
570 if (bfregi->ver < 2)
571 bfregn = -ENOMEM;
572 else
573 bfregn = alloc_med_class_bfreg(dev, bfregi);
574 break;
575
576 case MLX5_IB_LATENCY_CLASS_HIGH:
577 if (bfregi->ver < 2)
578 bfregn = -ENOMEM;
579 else
580 bfregn = alloc_high_class_bfreg(dev, bfregi);
581 break;
582 }
583 mutex_unlock(&bfregi->lock);
584
585 return bfregn;
586 }
587
588 static void free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi, int bfregn)
589 {
590 mutex_lock(&bfregi->lock);
591 bfregi->count[bfregn]--;
592 mutex_unlock(&bfregi->lock);
593 }
594
595 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
596 {
597 switch (state) {
598 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
599 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
600 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
601 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
602 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
603 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
604 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
605 default: return -1;
606 }
607 }
608
609 static int to_mlx5_st(enum ib_qp_type type)
610 {
611 switch (type) {
612 case IB_QPT_RC: return MLX5_QP_ST_RC;
613 case IB_QPT_UC: return MLX5_QP_ST_UC;
614 case IB_QPT_UD: return MLX5_QP_ST_UD;
615 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
616 case IB_QPT_XRC_INI:
617 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
618 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
619 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
620 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
621 case IB_QPT_RAW_PACKET:
622 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
623 case IB_QPT_MAX:
624 default: return -EINVAL;
625 }
626 }
627
628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
629 struct mlx5_ib_cq *recv_cq);
630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
631 struct mlx5_ib_cq *recv_cq);
632
633 static int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
634 struct mlx5_bfreg_info *bfregi, int bfregn)
635 {
636 int bfregs_per_sys_page;
637 int index_of_sys_page;
638 int offset;
639
640 bfregs_per_sys_page = get_uars_per_sys_page(dev, bfregi->lib_uar_4k) *
641 MLX5_NON_FP_BFREGS_PER_UAR;
642 index_of_sys_page = bfregn / bfregs_per_sys_page;
643
644 offset = bfregn % bfregs_per_sys_page / MLX5_NON_FP_BFREGS_PER_UAR;
645
646 return bfregi->sys_pages[index_of_sys_page] + offset;
647 }
648
649 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
650 struct ib_pd *pd,
651 unsigned long addr, size_t size,
652 struct ib_umem **umem,
653 int *npages, int *page_shift, int *ncont,
654 u32 *offset)
655 {
656 int err;
657
658 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
659 if (IS_ERR(*umem)) {
660 mlx5_ib_dbg(dev, "umem_get failed\n");
661 return PTR_ERR(*umem);
662 }
663
664 mlx5_ib_cont_pages(*umem, addr, 0, npages, page_shift, ncont, NULL);
665
666 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
667 if (err) {
668 mlx5_ib_warn(dev, "bad offset\n");
669 goto err_umem;
670 }
671
672 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
673 addr, size, *npages, *page_shift, *ncont, *offset);
674
675 return 0;
676
677 err_umem:
678 ib_umem_release(*umem);
679 *umem = NULL;
680
681 return err;
682 }
683
684 static void destroy_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
685 struct mlx5_ib_rwq *rwq)
686 {
687 struct mlx5_ib_ucontext *context;
688
689 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_DELAY_DROP)
690 atomic_dec(&dev->delay_drop.rqs_cnt);
691
692 context = to_mucontext(pd->uobject->context);
693 mlx5_ib_db_unmap_user(context, &rwq->db);
694 if (rwq->umem)
695 ib_umem_release(rwq->umem);
696 }
697
698 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
699 struct mlx5_ib_rwq *rwq,
700 struct mlx5_ib_create_wq *ucmd)
701 {
702 struct mlx5_ib_ucontext *context;
703 int page_shift = 0;
704 int npages;
705 u32 offset = 0;
706 int ncont = 0;
707 int err;
708
709 if (!ucmd->buf_addr)
710 return -EINVAL;
711
712 context = to_mucontext(pd->uobject->context);
713 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
714 rwq->buf_size, 0, 0);
715 if (IS_ERR(rwq->umem)) {
716 mlx5_ib_dbg(dev, "umem_get failed\n");
717 err = PTR_ERR(rwq->umem);
718 return err;
719 }
720
721 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, 0, &npages, &page_shift,
722 &ncont, NULL);
723 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
724 &rwq->rq_page_offset);
725 if (err) {
726 mlx5_ib_warn(dev, "bad offset\n");
727 goto err_umem;
728 }
729
730 rwq->rq_num_pas = ncont;
731 rwq->page_shift = page_shift;
732 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
733 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
734
735 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
736 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
737 npages, page_shift, ncont, offset);
738
739 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
740 if (err) {
741 mlx5_ib_dbg(dev, "map failed\n");
742 goto err_umem;
743 }
744
745 rwq->create_type = MLX5_WQ_USER;
746 return 0;
747
748 err_umem:
749 ib_umem_release(rwq->umem);
750 return err;
751 }
752
753 static int adjust_bfregn(struct mlx5_ib_dev *dev,
754 struct mlx5_bfreg_info *bfregi, int bfregn)
755 {
756 return bfregn / MLX5_NON_FP_BFREGS_PER_UAR * MLX5_BFREGS_PER_UAR +
757 bfregn % MLX5_NON_FP_BFREGS_PER_UAR;
758 }
759
760 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
761 struct mlx5_ib_qp *qp, struct ib_udata *udata,
762 struct ib_qp_init_attr *attr,
763 u32 **in,
764 struct mlx5_ib_create_qp_resp *resp, int *inlen,
765 struct mlx5_ib_qp_base *base)
766 {
767 struct mlx5_ib_ucontext *context;
768 struct mlx5_ib_create_qp ucmd;
769 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
770 int page_shift = 0;
771 int uar_index;
772 int npages;
773 u32 offset = 0;
774 int bfregn;
775 int ncont = 0;
776 __be64 *pas;
777 void *qpc;
778 int err;
779
780 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
781 if (err) {
782 mlx5_ib_dbg(dev, "copy failed\n");
783 return err;
784 }
785
786 context = to_mucontext(pd->uobject->context);
787 /*
788 * TBD: should come from the verbs when we have the API
789 */
790 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
791 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
792 bfregn = MLX5_CROSS_CHANNEL_BFREG;
793 else {
794 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_HIGH);
795 if (bfregn < 0) {
796 mlx5_ib_dbg(dev, "failed to allocate low latency BFREG\n");
797 mlx5_ib_dbg(dev, "reverting to medium latency\n");
798 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_MEDIUM);
799 if (bfregn < 0) {
800 mlx5_ib_dbg(dev, "failed to allocate medium latency BFREG\n");
801 mlx5_ib_dbg(dev, "reverting to high latency\n");
802 bfregn = alloc_bfreg(dev, &context->bfregi, MLX5_IB_LATENCY_CLASS_LOW);
803 if (bfregn < 0) {
804 mlx5_ib_warn(dev, "bfreg allocation failed\n");
805 return bfregn;
806 }
807 }
808 }
809 }
810
811 uar_index = bfregn_to_uar_index(dev, &context->bfregi, bfregn);
812 mlx5_ib_dbg(dev, "bfregn 0x%x, uar_index 0x%x\n", bfregn, uar_index);
813
814 qp->rq.offset = 0;
815 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
816 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
817
818 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
819 if (err)
820 goto err_bfreg;
821
822 if (ucmd.buf_addr && ubuffer->buf_size) {
823 ubuffer->buf_addr = ucmd.buf_addr;
824 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
825 ubuffer->buf_size,
826 &ubuffer->umem, &npages, &page_shift,
827 &ncont, &offset);
828 if (err)
829 goto err_bfreg;
830 } else {
831 ubuffer->umem = NULL;
832 }
833
834 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
835 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
836 *in = kvzalloc(*inlen, GFP_KERNEL);
837 if (!*in) {
838 err = -ENOMEM;
839 goto err_umem;
840 }
841
842 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
843 if (ubuffer->umem)
844 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
845
846 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
847
848 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
849 MLX5_SET(qpc, qpc, page_offset, offset);
850
851 MLX5_SET(qpc, qpc, uar_page, uar_index);
852 resp->bfreg_index = adjust_bfregn(dev, &context->bfregi, bfregn);
853 qp->bfregn = bfregn;
854
855 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
856 if (err) {
857 mlx5_ib_dbg(dev, "map failed\n");
858 goto err_free;
859 }
860
861 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
862 if (err) {
863 mlx5_ib_dbg(dev, "copy failed\n");
864 goto err_unmap;
865 }
866 qp->create_type = MLX5_QP_USER;
867
868 return 0;
869
870 err_unmap:
871 mlx5_ib_db_unmap_user(context, &qp->db);
872
873 err_free:
874 kvfree(*in);
875
876 err_umem:
877 if (ubuffer->umem)
878 ib_umem_release(ubuffer->umem);
879
880 err_bfreg:
881 free_bfreg(dev, &context->bfregi, bfregn);
882 return err;
883 }
884
885 static void destroy_qp_user(struct mlx5_ib_dev *dev, struct ib_pd *pd,
886 struct mlx5_ib_qp *qp, struct mlx5_ib_qp_base *base)
887 {
888 struct mlx5_ib_ucontext *context;
889
890 context = to_mucontext(pd->uobject->context);
891 mlx5_ib_db_unmap_user(context, &qp->db);
892 if (base->ubuffer.umem)
893 ib_umem_release(base->ubuffer.umem);
894 free_bfreg(dev, &context->bfregi, qp->bfregn);
895 }
896
897 static int create_kernel_qp(struct mlx5_ib_dev *dev,
898 struct ib_qp_init_attr *init_attr,
899 struct mlx5_ib_qp *qp,
900 u32 **in, int *inlen,
901 struct mlx5_ib_qp_base *base)
902 {
903 int uar_index;
904 void *qpc;
905 int err;
906
907 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
908 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
909 IB_QP_CREATE_IPOIB_UD_LSO |
910 IB_QP_CREATE_NETIF_QP |
911 mlx5_ib_create_qp_sqpn_qp1()))
912 return -EINVAL;
913
914 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
915 qp->bf.bfreg = &dev->fp_bfreg;
916 else
917 qp->bf.bfreg = &dev->bfreg;
918
919 /* We need to divide by two since each register is comprised of
920 * two buffers of identical size, namely odd and even
921 */
922 qp->bf.buf_size = (1 << MLX5_CAP_GEN(dev->mdev, log_bf_reg_size)) / 2;
923 uar_index = qp->bf.bfreg->index;
924
925 err = calc_sq_size(dev, init_attr, qp);
926 if (err < 0) {
927 mlx5_ib_dbg(dev, "err %d\n", err);
928 return err;
929 }
930
931 qp->rq.offset = 0;
932 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
933 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
934
935 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
936 if (err) {
937 mlx5_ib_dbg(dev, "err %d\n", err);
938 return err;
939 }
940
941 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
942 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
943 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
944 *in = kvzalloc(*inlen, GFP_KERNEL);
945 if (!*in) {
946 err = -ENOMEM;
947 goto err_buf;
948 }
949
950 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
951 MLX5_SET(qpc, qpc, uar_page, uar_index);
952 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
953
954 /* Set "fast registration enabled" for all kernel QPs */
955 MLX5_SET(qpc, qpc, fre, 1);
956 MLX5_SET(qpc, qpc, rlky, 1);
957
958 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
959 MLX5_SET(qpc, qpc, deth_sqpn, 1);
960 qp->flags |= MLX5_IB_QP_SQPN_QP1;
961 }
962
963 mlx5_fill_page_array(&qp->buf,
964 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
965
966 err = mlx5_db_alloc(dev->mdev, &qp->db);
967 if (err) {
968 mlx5_ib_dbg(dev, "err %d\n", err);
969 goto err_free;
970 }
971
972 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
973 sizeof(*qp->sq.wrid), GFP_KERNEL);
974 qp->sq.wr_data = kvmalloc_array(qp->sq.wqe_cnt,
975 sizeof(*qp->sq.wr_data), GFP_KERNEL);
976 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
977 sizeof(*qp->rq.wrid), GFP_KERNEL);
978 qp->sq.w_list = kvmalloc_array(qp->sq.wqe_cnt,
979 sizeof(*qp->sq.w_list), GFP_KERNEL);
980 qp->sq.wqe_head = kvmalloc_array(qp->sq.wqe_cnt,
981 sizeof(*qp->sq.wqe_head), GFP_KERNEL);
982
983 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
984 !qp->sq.w_list || !qp->sq.wqe_head) {
985 err = -ENOMEM;
986 goto err_wrid;
987 }
988 qp->create_type = MLX5_QP_KERNEL;
989
990 return 0;
991
992 err_wrid:
993 kvfree(qp->sq.wqe_head);
994 kvfree(qp->sq.w_list);
995 kvfree(qp->sq.wrid);
996 kvfree(qp->sq.wr_data);
997 kvfree(qp->rq.wrid);
998 mlx5_db_free(dev->mdev, &qp->db);
999
1000 err_free:
1001 kvfree(*in);
1002
1003 err_buf:
1004 mlx5_buf_free(dev->mdev, &qp->buf);
1005 return err;
1006 }
1007
1008 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1009 {
1010 kvfree(qp->sq.wqe_head);
1011 kvfree(qp->sq.w_list);
1012 kvfree(qp->sq.wrid);
1013 kvfree(qp->sq.wr_data);
1014 kvfree(qp->rq.wrid);
1015 mlx5_db_free(dev->mdev, &qp->db);
1016 mlx5_buf_free(dev->mdev, &qp->buf);
1017 }
1018
1019 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
1020 {
1021 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1022 (attr->qp_type == IB_QPT_XRC_INI))
1023 return MLX5_SRQ_RQ;
1024 else if (!qp->has_rq)
1025 return MLX5_ZERO_LEN_RQ;
1026 else
1027 return MLX5_NON_ZERO_RQ;
1028 }
1029
1030 static int is_connected(enum ib_qp_type qp_type)
1031 {
1032 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1033 return 1;
1034
1035 return 0;
1036 }
1037
1038 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1039 struct mlx5_ib_qp *qp,
1040 struct mlx5_ib_sq *sq, u32 tdn)
1041 {
1042 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1043 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1044
1045 MLX5_SET(tisc, tisc, transport_domain, tdn);
1046 if (qp->flags & MLX5_IB_QP_UNDERLAY)
1047 MLX5_SET(tisc, tisc, underlay_qpn, qp->underlay_qpn);
1048
1049 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1050 }
1051
1052 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1053 struct mlx5_ib_sq *sq)
1054 {
1055 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1056 }
1057
1058 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1059 struct mlx5_ib_sq *sq, void *qpin,
1060 struct ib_pd *pd)
1061 {
1062 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1063 __be64 *pas;
1064 void *in;
1065 void *sqc;
1066 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1067 void *wq;
1068 int inlen;
1069 int err;
1070 int page_shift = 0;
1071 int npages;
1072 int ncont = 0;
1073 u32 offset = 0;
1074
1075 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1076 &sq->ubuffer.umem, &npages, &page_shift,
1077 &ncont, &offset);
1078 if (err)
1079 return err;
1080
1081 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1082 in = kvzalloc(inlen, GFP_KERNEL);
1083 if (!in) {
1084 err = -ENOMEM;
1085 goto err_umem;
1086 }
1087
1088 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1089 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1090 if (MLX5_CAP_ETH(dev->mdev, multi_pkt_send_wqe))
1091 MLX5_SET(sqc, sqc, allow_multi_pkt_send_wqe, 1);
1092 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1093 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1094 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1095 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1096 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1097 if (MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1098 MLX5_CAP_ETH(dev->mdev, swp))
1099 MLX5_SET(sqc, sqc, allow_swp, 1);
1100
1101 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1102 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1103 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1104 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1105 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1106 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1107 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1108 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1109 MLX5_SET(wq, wq, page_offset, offset);
1110
1111 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1112 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1113
1114 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1115
1116 kvfree(in);
1117
1118 if (err)
1119 goto err_umem;
1120
1121 return 0;
1122
1123 err_umem:
1124 ib_umem_release(sq->ubuffer.umem);
1125 sq->ubuffer.umem = NULL;
1126
1127 return err;
1128 }
1129
1130 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1131 struct mlx5_ib_sq *sq)
1132 {
1133 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1134 ib_umem_release(sq->ubuffer.umem);
1135 }
1136
1137 static size_t get_rq_pas_size(void *qpc)
1138 {
1139 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1140 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1141 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1142 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1143 u32 po_quanta = 1 << (log_page_size - 6);
1144 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1145 u32 page_size = 1 << log_page_size;
1146 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1147 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1148
1149 return rq_num_pas * sizeof(u64);
1150 }
1151
1152 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1153 struct mlx5_ib_rq *rq, void *qpin,
1154 size_t qpinlen)
1155 {
1156 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1157 __be64 *pas;
1158 __be64 *qp_pas;
1159 void *in;
1160 void *rqc;
1161 void *wq;
1162 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1163 size_t rq_pas_size = get_rq_pas_size(qpc);
1164 size_t inlen;
1165 int err;
1166
1167 if (qpinlen < rq_pas_size + MLX5_BYTE_OFF(create_qp_in, pas))
1168 return -EINVAL;
1169
1170 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1171 in = kvzalloc(inlen, GFP_KERNEL);
1172 if (!in)
1173 return -ENOMEM;
1174
1175 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1176 if (!(rq->flags & MLX5_IB_RQ_CVLAN_STRIPPING))
1177 MLX5_SET(rqc, rqc, vsd, 1);
1178 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1179 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1180 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1181 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1182 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1183
1184 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1185 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1186
1187 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1188 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1189 if (rq->flags & MLX5_IB_RQ_PCI_WRITE_END_PADDING)
1190 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1191 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1192 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1193 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1194 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1195 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1196 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1197
1198 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1199 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1200 memcpy(pas, qp_pas, rq_pas_size);
1201
1202 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1203
1204 kvfree(in);
1205
1206 return err;
1207 }
1208
1209 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1210 struct mlx5_ib_rq *rq)
1211 {
1212 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1213 }
1214
1215 static bool tunnel_offload_supported(struct mlx5_core_dev *dev)
1216 {
1217 return (MLX5_CAP_ETH(dev, tunnel_stateless_vxlan) ||
1218 MLX5_CAP_ETH(dev, tunnel_stateless_gre) ||
1219 MLX5_CAP_ETH(dev, tunnel_stateless_geneve_rx));
1220 }
1221
1222 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1223 struct mlx5_ib_rq *rq, u32 tdn,
1224 bool tunnel_offload_en)
1225 {
1226 u32 *in;
1227 void *tirc;
1228 int inlen;
1229 int err;
1230
1231 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1232 in = kvzalloc(inlen, GFP_KERNEL);
1233 if (!in)
1234 return -ENOMEM;
1235
1236 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1237 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1238 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1239 MLX5_SET(tirc, tirc, transport_domain, tdn);
1240 if (tunnel_offload_en)
1241 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1242
1243 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1244
1245 kvfree(in);
1246
1247 return err;
1248 }
1249
1250 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1251 struct mlx5_ib_rq *rq)
1252 {
1253 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1254 }
1255
1256 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1257 u32 *in, size_t inlen,
1258 struct ib_pd *pd)
1259 {
1260 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1261 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1262 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1263 struct ib_uobject *uobj = pd->uobject;
1264 struct ib_ucontext *ucontext = uobj->context;
1265 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1266 int err;
1267 u32 tdn = mucontext->tdn;
1268
1269 if (qp->sq.wqe_cnt) {
1270 err = create_raw_packet_qp_tis(dev, qp, sq, tdn);
1271 if (err)
1272 return err;
1273
1274 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1275 if (err)
1276 goto err_destroy_tis;
1277
1278 sq->base.container_mibqp = qp;
1279 sq->base.mqp.event = mlx5_ib_qp_event;
1280 }
1281
1282 if (qp->rq.wqe_cnt) {
1283 rq->base.container_mibqp = qp;
1284
1285 if (qp->flags & MLX5_IB_QP_CVLAN_STRIPPING)
1286 rq->flags |= MLX5_IB_RQ_CVLAN_STRIPPING;
1287 if (qp->flags & MLX5_IB_QP_PCI_WRITE_END_PADDING)
1288 rq->flags |= MLX5_IB_RQ_PCI_WRITE_END_PADDING;
1289 err = create_raw_packet_qp_rq(dev, rq, in, inlen);
1290 if (err)
1291 goto err_destroy_sq;
1292
1293
1294 err = create_raw_packet_qp_tir(dev, rq, tdn,
1295 qp->tunnel_offload_en);
1296 if (err)
1297 goto err_destroy_rq;
1298 }
1299
1300 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1301 rq->base.mqp.qpn;
1302
1303 return 0;
1304
1305 err_destroy_rq:
1306 destroy_raw_packet_qp_rq(dev, rq);
1307 err_destroy_sq:
1308 if (!qp->sq.wqe_cnt)
1309 return err;
1310 destroy_raw_packet_qp_sq(dev, sq);
1311 err_destroy_tis:
1312 destroy_raw_packet_qp_tis(dev, sq);
1313
1314 return err;
1315 }
1316
1317 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1318 struct mlx5_ib_qp *qp)
1319 {
1320 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1321 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1322 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1323
1324 if (qp->rq.wqe_cnt) {
1325 destroy_raw_packet_qp_tir(dev, rq);
1326 destroy_raw_packet_qp_rq(dev, rq);
1327 }
1328
1329 if (qp->sq.wqe_cnt) {
1330 destroy_raw_packet_qp_sq(dev, sq);
1331 destroy_raw_packet_qp_tis(dev, sq);
1332 }
1333 }
1334
1335 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1336 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1337 {
1338 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1339 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1340
1341 sq->sq = &qp->sq;
1342 rq->rq = &qp->rq;
1343 sq->doorbell = &qp->db;
1344 rq->doorbell = &qp->db;
1345 }
1346
1347 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1348 {
1349 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1350 }
1351
1352 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1353 struct ib_pd *pd,
1354 struct ib_qp_init_attr *init_attr,
1355 struct ib_udata *udata)
1356 {
1357 struct ib_uobject *uobj = pd->uobject;
1358 struct ib_ucontext *ucontext = uobj->context;
1359 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1360 struct mlx5_ib_create_qp_resp resp = {};
1361 int inlen;
1362 int err;
1363 u32 *in;
1364 void *tirc;
1365 void *hfso;
1366 u32 selected_fields = 0;
1367 size_t min_resp_len;
1368 u32 tdn = mucontext->tdn;
1369 struct mlx5_ib_create_qp_rss ucmd = {};
1370 size_t required_cmd_sz;
1371
1372 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1373 return -EOPNOTSUPP;
1374
1375 if (init_attr->create_flags || init_attr->send_cq)
1376 return -EINVAL;
1377
1378 min_resp_len = offsetof(typeof(resp), bfreg_index) + sizeof(resp.bfreg_index);
1379 if (udata->outlen < min_resp_len)
1380 return -EINVAL;
1381
1382 required_cmd_sz = offsetof(typeof(ucmd), flags) + sizeof(ucmd.flags);
1383 if (udata->inlen < required_cmd_sz) {
1384 mlx5_ib_dbg(dev, "invalid inlen\n");
1385 return -EINVAL;
1386 }
1387
1388 if (udata->inlen > sizeof(ucmd) &&
1389 !ib_is_udata_cleared(udata, sizeof(ucmd),
1390 udata->inlen - sizeof(ucmd))) {
1391 mlx5_ib_dbg(dev, "inlen is not supported\n");
1392 return -EOPNOTSUPP;
1393 }
1394
1395 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1396 mlx5_ib_dbg(dev, "copy failed\n");
1397 return -EFAULT;
1398 }
1399
1400 if (ucmd.comp_mask) {
1401 mlx5_ib_dbg(dev, "invalid comp mask\n");
1402 return -EOPNOTSUPP;
1403 }
1404
1405 if (ucmd.flags & ~MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1406 mlx5_ib_dbg(dev, "invalid flags\n");
1407 return -EOPNOTSUPP;
1408 }
1409
1410 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS &&
1411 !tunnel_offload_supported(dev->mdev)) {
1412 mlx5_ib_dbg(dev, "tunnel offloads isn't supported\n");
1413 return -EOPNOTSUPP;
1414 }
1415
1416 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER &&
1417 !(ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)) {
1418 mlx5_ib_dbg(dev, "Tunnel offloads must be set for inner RSS\n");
1419 return -EOPNOTSUPP;
1420 }
1421
1422 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1423 if (err) {
1424 mlx5_ib_dbg(dev, "copy failed\n");
1425 return -EINVAL;
1426 }
1427
1428 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1429 in = kvzalloc(inlen, GFP_KERNEL);
1430 if (!in)
1431 return -ENOMEM;
1432
1433 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1434 MLX5_SET(tirc, tirc, disp_type,
1435 MLX5_TIRC_DISP_TYPE_INDIRECT);
1436 MLX5_SET(tirc, tirc, indirect_table,
1437 init_attr->rwq_ind_tbl->ind_tbl_num);
1438 MLX5_SET(tirc, tirc, transport_domain, tdn);
1439
1440 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1441
1442 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS)
1443 MLX5_SET(tirc, tirc, tunneled_offload_en, 1);
1444
1445 if (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_INNER)
1446 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner);
1447 else
1448 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1449
1450 switch (ucmd.rx_hash_function) {
1451 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1452 {
1453 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1454 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1455
1456 if (len != ucmd.rx_key_len) {
1457 err = -EINVAL;
1458 goto err;
1459 }
1460
1461 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1462 memcpy(rss_key, ucmd.rx_hash_key, len);
1463 break;
1464 }
1465 default:
1466 err = -EOPNOTSUPP;
1467 goto err;
1468 }
1469
1470 if (!ucmd.rx_hash_fields_mask) {
1471 /* special case when this TIR serves as steering entry without hashing */
1472 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1473 goto create_tir;
1474 err = -EINVAL;
1475 goto err;
1476 }
1477
1478 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1479 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1480 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1481 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1482 err = -EINVAL;
1483 goto err;
1484 }
1485
1486 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1487 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1488 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1489 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1490 MLX5_L3_PROT_TYPE_IPV4);
1491 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1492 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1493 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1494 MLX5_L3_PROT_TYPE_IPV6);
1495
1496 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1497 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1498 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1499 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1500 err = -EINVAL;
1501 goto err;
1502 }
1503
1504 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1505 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1506 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1507 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1508 MLX5_L4_PROT_TYPE_TCP);
1509 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1510 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1511 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1512 MLX5_L4_PROT_TYPE_UDP);
1513
1514 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1515 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1516 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1517
1518 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1519 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1520 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1521
1522 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1523 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1524 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1525
1526 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1527 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1528 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1529
1530 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1531
1532 create_tir:
1533 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1534
1535 if (err)
1536 goto err;
1537
1538 kvfree(in);
1539 /* qpn is reserved for that QP */
1540 qp->trans_qp.base.mqp.qpn = 0;
1541 qp->flags |= MLX5_IB_QP_RSS;
1542 return 0;
1543
1544 err:
1545 kvfree(in);
1546 return err;
1547 }
1548
1549 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1550 struct ib_qp_init_attr *init_attr,
1551 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1552 {
1553 struct mlx5_ib_resources *devr = &dev->devr;
1554 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1555 struct mlx5_core_dev *mdev = dev->mdev;
1556 struct mlx5_ib_create_qp_resp resp = {};
1557 struct mlx5_ib_cq *send_cq;
1558 struct mlx5_ib_cq *recv_cq;
1559 unsigned long flags;
1560 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1561 struct mlx5_ib_create_qp ucmd;
1562 struct mlx5_ib_qp_base *base;
1563 int mlx5_st;
1564 void *qpc;
1565 u32 *in;
1566 int err;
1567
1568 mutex_init(&qp->mutex);
1569 spin_lock_init(&qp->sq.lock);
1570 spin_lock_init(&qp->rq.lock);
1571
1572 mlx5_st = to_mlx5_st(init_attr->qp_type);
1573 if (mlx5_st < 0)
1574 return -EINVAL;
1575
1576 if (init_attr->rwq_ind_tbl) {
1577 if (!udata)
1578 return -ENOSYS;
1579
1580 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1581 return err;
1582 }
1583
1584 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1585 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1586 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1587 return -EINVAL;
1588 } else {
1589 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1590 }
1591 }
1592
1593 if (init_attr->create_flags &
1594 (IB_QP_CREATE_CROSS_CHANNEL |
1595 IB_QP_CREATE_MANAGED_SEND |
1596 IB_QP_CREATE_MANAGED_RECV)) {
1597 if (!MLX5_CAP_GEN(mdev, cd)) {
1598 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1599 return -EINVAL;
1600 }
1601 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1602 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1603 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1604 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1605 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1606 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1607 }
1608
1609 if (init_attr->qp_type == IB_QPT_UD &&
1610 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1611 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1612 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1613 return -EOPNOTSUPP;
1614 }
1615
1616 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1617 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1618 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1619 return -EOPNOTSUPP;
1620 }
1621 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1622 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1623 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1624 return -EOPNOTSUPP;
1625 }
1626 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1627 }
1628
1629 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1630 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1631
1632 if (init_attr->create_flags & IB_QP_CREATE_CVLAN_STRIPPING) {
1633 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
1634 MLX5_CAP_ETH(dev->mdev, vlan_cap)) ||
1635 (init_attr->qp_type != IB_QPT_RAW_PACKET))
1636 return -EOPNOTSUPP;
1637 qp->flags |= MLX5_IB_QP_CVLAN_STRIPPING;
1638 }
1639
1640 if (pd && pd->uobject) {
1641 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1642 mlx5_ib_dbg(dev, "copy failed\n");
1643 return -EFAULT;
1644 }
1645
1646 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1647 &ucmd, udata->inlen, &uidx);
1648 if (err)
1649 return err;
1650
1651 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1652 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1653 if (ucmd.flags & MLX5_QP_FLAG_TUNNEL_OFFLOADS) {
1654 if (init_attr->qp_type != IB_QPT_RAW_PACKET ||
1655 !tunnel_offload_supported(mdev)) {
1656 mlx5_ib_dbg(dev, "Tunnel offload isn't supported\n");
1657 return -EOPNOTSUPP;
1658 }
1659 qp->tunnel_offload_en = true;
1660 }
1661
1662 if (init_attr->create_flags & IB_QP_CREATE_SOURCE_QPN) {
1663 if (init_attr->qp_type != IB_QPT_UD ||
1664 (MLX5_CAP_GEN(dev->mdev, port_type) !=
1665 MLX5_CAP_PORT_TYPE_IB) ||
1666 !mlx5_get_flow_namespace(dev->mdev, MLX5_FLOW_NAMESPACE_BYPASS)) {
1667 mlx5_ib_dbg(dev, "Source QP option isn't supported\n");
1668 return -EOPNOTSUPP;
1669 }
1670
1671 qp->flags |= MLX5_IB_QP_UNDERLAY;
1672 qp->underlay_qpn = init_attr->source_qpn;
1673 }
1674 } else {
1675 qp->wq_sig = !!wq_signature;
1676 }
1677
1678 base = (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1679 qp->flags & MLX5_IB_QP_UNDERLAY) ?
1680 &qp->raw_packet_qp.rq.base :
1681 &qp->trans_qp.base;
1682
1683 qp->has_rq = qp_has_rq(init_attr);
1684 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1685 qp, (pd && pd->uobject) ? &ucmd : NULL);
1686 if (err) {
1687 mlx5_ib_dbg(dev, "err %d\n", err);
1688 return err;
1689 }
1690
1691 if (pd) {
1692 if (pd->uobject) {
1693 __u32 max_wqes =
1694 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1695 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1696 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1697 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1698 mlx5_ib_dbg(dev, "invalid rq params\n");
1699 return -EINVAL;
1700 }
1701 if (ucmd.sq_wqe_count > max_wqes) {
1702 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1703 ucmd.sq_wqe_count, max_wqes);
1704 return -EINVAL;
1705 }
1706 if (init_attr->create_flags &
1707 mlx5_ib_create_qp_sqpn_qp1()) {
1708 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1709 return -EINVAL;
1710 }
1711 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1712 &resp, &inlen, base);
1713 if (err)
1714 mlx5_ib_dbg(dev, "err %d\n", err);
1715 } else {
1716 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1717 base);
1718 if (err)
1719 mlx5_ib_dbg(dev, "err %d\n", err);
1720 }
1721
1722 if (err)
1723 return err;
1724 } else {
1725 in = kvzalloc(inlen, GFP_KERNEL);
1726 if (!in)
1727 return -ENOMEM;
1728
1729 qp->create_type = MLX5_QP_EMPTY;
1730 }
1731
1732 if (is_sqp(init_attr->qp_type))
1733 qp->port = init_attr->port_num;
1734
1735 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1736
1737 MLX5_SET(qpc, qpc, st, mlx5_st);
1738 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1739
1740 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1741 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1742 else
1743 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1744
1745
1746 if (qp->wq_sig)
1747 MLX5_SET(qpc, qpc, wq_signature, 1);
1748
1749 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1750 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1751
1752 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1753 MLX5_SET(qpc, qpc, cd_master, 1);
1754 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1755 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1756 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1757 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1758
1759 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1760 int rcqe_sz;
1761 int scqe_sz;
1762
1763 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1764 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1765
1766 if (rcqe_sz == 128)
1767 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1768 else
1769 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1770
1771 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1772 if (scqe_sz == 128)
1773 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1774 else
1775 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1776 }
1777 }
1778
1779 if (qp->rq.wqe_cnt) {
1780 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1781 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1782 }
1783
1784 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1785
1786 if (qp->sq.wqe_cnt) {
1787 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1788 } else {
1789 MLX5_SET(qpc, qpc, no_sq, 1);
1790 if (init_attr->srq &&
1791 init_attr->srq->srq_type == IB_SRQT_TM)
1792 MLX5_SET(qpc, qpc, offload_type,
1793 MLX5_QPC_OFFLOAD_TYPE_RNDV);
1794 }
1795
1796 /* Set default resources */
1797 switch (init_attr->qp_type) {
1798 case IB_QPT_XRC_TGT:
1799 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1800 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1801 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1802 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1803 break;
1804 case IB_QPT_XRC_INI:
1805 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1806 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1807 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1808 break;
1809 default:
1810 if (init_attr->srq) {
1811 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1812 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1813 } else {
1814 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1815 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1816 }
1817 }
1818
1819 if (init_attr->send_cq)
1820 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1821
1822 if (init_attr->recv_cq)
1823 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1824
1825 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1826
1827 /* 0xffffff means we ask to work with cqe version 0 */
1828 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1829 MLX5_SET(qpc, qpc, user_index, uidx);
1830
1831 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1832 if (init_attr->qp_type == IB_QPT_UD &&
1833 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1834 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1835 qp->flags |= MLX5_IB_QP_LSO;
1836 }
1837
1838 if (init_attr->create_flags & IB_QP_CREATE_PCI_WRITE_END_PADDING) {
1839 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
1840 mlx5_ib_dbg(dev, "scatter end padding is not supported\n");
1841 err = -EOPNOTSUPP;
1842 goto err;
1843 } else if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1844 MLX5_SET(qpc, qpc, end_padding_mode,
1845 MLX5_WQ_END_PAD_MODE_ALIGN);
1846 } else {
1847 qp->flags |= MLX5_IB_QP_PCI_WRITE_END_PADDING;
1848 }
1849 }
1850
1851 if (inlen < 0) {
1852 err = -EINVAL;
1853 goto err;
1854 }
1855
1856 if (init_attr->qp_type == IB_QPT_RAW_PACKET ||
1857 qp->flags & MLX5_IB_QP_UNDERLAY) {
1858 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1859 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1860 err = create_raw_packet_qp(dev, qp, in, inlen, pd);
1861 } else {
1862 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1863 }
1864
1865 if (err) {
1866 mlx5_ib_dbg(dev, "create qp failed\n");
1867 goto err_create;
1868 }
1869
1870 kvfree(in);
1871
1872 base->container_mibqp = qp;
1873 base->mqp.event = mlx5_ib_qp_event;
1874
1875 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1876 &send_cq, &recv_cq);
1877 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1878 mlx5_ib_lock_cqs(send_cq, recv_cq);
1879 /* Maintain device to QPs access, needed for further handling via reset
1880 * flow
1881 */
1882 list_add_tail(&qp->qps_list, &dev->qp_list);
1883 /* Maintain CQ to QPs access, needed for further handling via reset flow
1884 */
1885 if (send_cq)
1886 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1887 if (recv_cq)
1888 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1889 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1890 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1891
1892 return 0;
1893
1894 err_create:
1895 if (qp->create_type == MLX5_QP_USER)
1896 destroy_qp_user(dev, pd, qp, base);
1897 else if (qp->create_type == MLX5_QP_KERNEL)
1898 destroy_qp_kernel(dev, qp);
1899
1900 err:
1901 kvfree(in);
1902 return err;
1903 }
1904
1905 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1906 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1907 {
1908 if (send_cq) {
1909 if (recv_cq) {
1910 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1911 spin_lock(&send_cq->lock);
1912 spin_lock_nested(&recv_cq->lock,
1913 SINGLE_DEPTH_NESTING);
1914 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1915 spin_lock(&send_cq->lock);
1916 __acquire(&recv_cq->lock);
1917 } else {
1918 spin_lock(&recv_cq->lock);
1919 spin_lock_nested(&send_cq->lock,
1920 SINGLE_DEPTH_NESTING);
1921 }
1922 } else {
1923 spin_lock(&send_cq->lock);
1924 __acquire(&recv_cq->lock);
1925 }
1926 } else if (recv_cq) {
1927 spin_lock(&recv_cq->lock);
1928 __acquire(&send_cq->lock);
1929 } else {
1930 __acquire(&send_cq->lock);
1931 __acquire(&recv_cq->lock);
1932 }
1933 }
1934
1935 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1936 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1937 {
1938 if (send_cq) {
1939 if (recv_cq) {
1940 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1941 spin_unlock(&recv_cq->lock);
1942 spin_unlock(&send_cq->lock);
1943 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1944 __release(&recv_cq->lock);
1945 spin_unlock(&send_cq->lock);
1946 } else {
1947 spin_unlock(&send_cq->lock);
1948 spin_unlock(&recv_cq->lock);
1949 }
1950 } else {
1951 __release(&recv_cq->lock);
1952 spin_unlock(&send_cq->lock);
1953 }
1954 } else if (recv_cq) {
1955 __release(&send_cq->lock);
1956 spin_unlock(&recv_cq->lock);
1957 } else {
1958 __release(&recv_cq->lock);
1959 __release(&send_cq->lock);
1960 }
1961 }
1962
1963 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1964 {
1965 return to_mpd(qp->ibqp.pd);
1966 }
1967
1968 static void get_cqs(enum ib_qp_type qp_type,
1969 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1970 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1971 {
1972 switch (qp_type) {
1973 case IB_QPT_XRC_TGT:
1974 *send_cq = NULL;
1975 *recv_cq = NULL;
1976 break;
1977 case MLX5_IB_QPT_REG_UMR:
1978 case IB_QPT_XRC_INI:
1979 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1980 *recv_cq = NULL;
1981 break;
1982
1983 case IB_QPT_SMI:
1984 case MLX5_IB_QPT_HW_GSI:
1985 case IB_QPT_RC:
1986 case IB_QPT_UC:
1987 case IB_QPT_UD:
1988 case IB_QPT_RAW_IPV6:
1989 case IB_QPT_RAW_ETHERTYPE:
1990 case IB_QPT_RAW_PACKET:
1991 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1992 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1993 break;
1994
1995 case IB_QPT_MAX:
1996 default:
1997 *send_cq = NULL;
1998 *recv_cq = NULL;
1999 break;
2000 }
2001 }
2002
2003 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2004 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2005 u8 lag_tx_affinity);
2006
2007 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
2008 {
2009 struct mlx5_ib_cq *send_cq, *recv_cq;
2010 struct mlx5_ib_qp_base *base;
2011 unsigned long flags;
2012 int err;
2013
2014 if (qp->ibqp.rwq_ind_tbl) {
2015 destroy_rss_raw_qp_tir(dev, qp);
2016 return;
2017 }
2018
2019 base = (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2020 qp->flags & MLX5_IB_QP_UNDERLAY) ?
2021 &qp->raw_packet_qp.rq.base :
2022 &qp->trans_qp.base;
2023
2024 if (qp->state != IB_QPS_RESET) {
2025 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET &&
2026 !(qp->flags & MLX5_IB_QP_UNDERLAY)) {
2027 err = mlx5_core_qp_modify(dev->mdev,
2028 MLX5_CMD_OP_2RST_QP, 0,
2029 NULL, &base->mqp);
2030 } else {
2031 struct mlx5_modify_raw_qp_param raw_qp_param = {
2032 .operation = MLX5_CMD_OP_2RST_QP
2033 };
2034
2035 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
2036 }
2037 if (err)
2038 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2039 base->mqp.qpn);
2040 }
2041
2042 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2043 &send_cq, &recv_cq);
2044
2045 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
2046 mlx5_ib_lock_cqs(send_cq, recv_cq);
2047 /* del from lists under both locks above to protect reset flow paths */
2048 list_del(&qp->qps_list);
2049 if (send_cq)
2050 list_del(&qp->cq_send_list);
2051
2052 if (recv_cq)
2053 list_del(&qp->cq_recv_list);
2054
2055 if (qp->create_type == MLX5_QP_KERNEL) {
2056 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2057 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
2058 if (send_cq != recv_cq)
2059 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
2060 NULL);
2061 }
2062 mlx5_ib_unlock_cqs(send_cq, recv_cq);
2063 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
2064
2065 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2066 qp->flags & MLX5_IB_QP_UNDERLAY) {
2067 destroy_raw_packet_qp(dev, qp);
2068 } else {
2069 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
2070 if (err)
2071 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
2072 base->mqp.qpn);
2073 }
2074
2075 if (qp->create_type == MLX5_QP_KERNEL)
2076 destroy_qp_kernel(dev, qp);
2077 else if (qp->create_type == MLX5_QP_USER)
2078 destroy_qp_user(dev, &get_pd(qp)->ibpd, qp, base);
2079 }
2080
2081 static const char *ib_qp_type_str(enum ib_qp_type type)
2082 {
2083 switch (type) {
2084 case IB_QPT_SMI:
2085 return "IB_QPT_SMI";
2086 case IB_QPT_GSI:
2087 return "IB_QPT_GSI";
2088 case IB_QPT_RC:
2089 return "IB_QPT_RC";
2090 case IB_QPT_UC:
2091 return "IB_QPT_UC";
2092 case IB_QPT_UD:
2093 return "IB_QPT_UD";
2094 case IB_QPT_RAW_IPV6:
2095 return "IB_QPT_RAW_IPV6";
2096 case IB_QPT_RAW_ETHERTYPE:
2097 return "IB_QPT_RAW_ETHERTYPE";
2098 case IB_QPT_XRC_INI:
2099 return "IB_QPT_XRC_INI";
2100 case IB_QPT_XRC_TGT:
2101 return "IB_QPT_XRC_TGT";
2102 case IB_QPT_RAW_PACKET:
2103 return "IB_QPT_RAW_PACKET";
2104 case MLX5_IB_QPT_REG_UMR:
2105 return "MLX5_IB_QPT_REG_UMR";
2106 case IB_QPT_MAX:
2107 default:
2108 return "Invalid QP type";
2109 }
2110 }
2111
2112 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
2113 struct ib_qp_init_attr *init_attr,
2114 struct ib_udata *udata)
2115 {
2116 struct mlx5_ib_dev *dev;
2117 struct mlx5_ib_qp *qp;
2118 u16 xrcdn = 0;
2119 int err;
2120
2121 if (pd) {
2122 dev = to_mdev(pd->device);
2123
2124 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
2125 if (!pd->uobject) {
2126 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
2127 return ERR_PTR(-EINVAL);
2128 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
2129 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
2130 return ERR_PTR(-EINVAL);
2131 }
2132 }
2133 } else {
2134 /* being cautious here */
2135 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2136 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2137 pr_warn("%s: no PD for transport %s\n", __func__,
2138 ib_qp_type_str(init_attr->qp_type));
2139 return ERR_PTR(-EINVAL);
2140 }
2141 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2142 }
2143
2144 switch (init_attr->qp_type) {
2145 case IB_QPT_XRC_TGT:
2146 case IB_QPT_XRC_INI:
2147 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2148 mlx5_ib_dbg(dev, "XRC not supported\n");
2149 return ERR_PTR(-ENOSYS);
2150 }
2151 init_attr->recv_cq = NULL;
2152 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2153 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2154 init_attr->send_cq = NULL;
2155 }
2156
2157 /* fall through */
2158 case IB_QPT_RAW_PACKET:
2159 case IB_QPT_RC:
2160 case IB_QPT_UC:
2161 case IB_QPT_UD:
2162 case IB_QPT_SMI:
2163 case MLX5_IB_QPT_HW_GSI:
2164 case MLX5_IB_QPT_REG_UMR:
2165 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2166 if (!qp)
2167 return ERR_PTR(-ENOMEM);
2168
2169 err = create_qp_common(dev, pd, init_attr, udata, qp);
2170 if (err) {
2171 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2172 kfree(qp);
2173 return ERR_PTR(err);
2174 }
2175
2176 if (is_qp0(init_attr->qp_type))
2177 qp->ibqp.qp_num = 0;
2178 else if (is_qp1(init_attr->qp_type))
2179 qp->ibqp.qp_num = 1;
2180 else
2181 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2182
2183 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2184 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2185 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2186 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2187
2188 qp->trans_qp.xrcdn = xrcdn;
2189
2190 break;
2191
2192 case IB_QPT_GSI:
2193 return mlx5_ib_gsi_create_qp(pd, init_attr);
2194
2195 case IB_QPT_RAW_IPV6:
2196 case IB_QPT_RAW_ETHERTYPE:
2197 case IB_QPT_MAX:
2198 default:
2199 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2200 init_attr->qp_type);
2201 /* Don't support raw QPs */
2202 return ERR_PTR(-EINVAL);
2203 }
2204
2205 return &qp->ibqp;
2206 }
2207
2208 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2209 {
2210 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2211 struct mlx5_ib_qp *mqp = to_mqp(qp);
2212
2213 if (unlikely(qp->qp_type == IB_QPT_GSI))
2214 return mlx5_ib_gsi_destroy_qp(qp);
2215
2216 destroy_qp_common(dev, mqp);
2217
2218 kfree(mqp);
2219
2220 return 0;
2221 }
2222
2223 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2224 int attr_mask)
2225 {
2226 u32 hw_access_flags = 0;
2227 u8 dest_rd_atomic;
2228 u32 access_flags;
2229
2230 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2231 dest_rd_atomic = attr->max_dest_rd_atomic;
2232 else
2233 dest_rd_atomic = qp->trans_qp.resp_depth;
2234
2235 if (attr_mask & IB_QP_ACCESS_FLAGS)
2236 access_flags = attr->qp_access_flags;
2237 else
2238 access_flags = qp->trans_qp.atomic_rd_en;
2239
2240 if (!dest_rd_atomic)
2241 access_flags &= IB_ACCESS_REMOTE_WRITE;
2242
2243 if (access_flags & IB_ACCESS_REMOTE_READ)
2244 hw_access_flags |= MLX5_QP_BIT_RRE;
2245 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2246 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2247 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2248 hw_access_flags |= MLX5_QP_BIT_RWE;
2249
2250 return cpu_to_be32(hw_access_flags);
2251 }
2252
2253 enum {
2254 MLX5_PATH_FLAG_FL = 1 << 0,
2255 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2256 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2257 };
2258
2259 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2260 {
2261 if (rate == IB_RATE_PORT_CURRENT)
2262 return 0;
2263
2264 if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS)
2265 return -EINVAL;
2266
2267 while (rate != IB_RATE_PORT_CURRENT &&
2268 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2269 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2270 --rate;
2271
2272 return rate ? rate + MLX5_STAT_RATE_OFFSET : rate;
2273 }
2274
2275 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2276 struct mlx5_ib_sq *sq, u8 sl)
2277 {
2278 void *in;
2279 void *tisc;
2280 int inlen;
2281 int err;
2282
2283 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2284 in = kvzalloc(inlen, GFP_KERNEL);
2285 if (!in)
2286 return -ENOMEM;
2287
2288 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2289
2290 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2291 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2292
2293 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2294
2295 kvfree(in);
2296
2297 return err;
2298 }
2299
2300 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2301 struct mlx5_ib_sq *sq, u8 tx_affinity)
2302 {
2303 void *in;
2304 void *tisc;
2305 int inlen;
2306 int err;
2307
2308 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2309 in = kvzalloc(inlen, GFP_KERNEL);
2310 if (!in)
2311 return -ENOMEM;
2312
2313 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2314
2315 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2316 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2317
2318 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2319
2320 kvfree(in);
2321
2322 return err;
2323 }
2324
2325 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2326 const struct rdma_ah_attr *ah,
2327 struct mlx5_qp_path *path, u8 port, int attr_mask,
2328 u32 path_flags, const struct ib_qp_attr *attr,
2329 bool alt)
2330 {
2331 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
2332 int err;
2333 enum ib_gid_type gid_type;
2334 u8 ah_flags = rdma_ah_get_ah_flags(ah);
2335 u8 sl = rdma_ah_get_sl(ah);
2336
2337 if (attr_mask & IB_QP_PKEY_INDEX)
2338 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2339 attr->pkey_index);
2340
2341 if (ah_flags & IB_AH_GRH) {
2342 if (grh->sgid_index >=
2343 dev->mdev->port_caps[port - 1].gid_table_len) {
2344 pr_err("sgid_index (%u) too large. max is %d\n",
2345 grh->sgid_index,
2346 dev->mdev->port_caps[port - 1].gid_table_len);
2347 return -EINVAL;
2348 }
2349 }
2350
2351 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
2352 if (!(ah_flags & IB_AH_GRH))
2353 return -EINVAL;
2354 err = mlx5_get_roce_gid_type(dev, port, grh->sgid_index,
2355 &gid_type);
2356 if (err)
2357 return err;
2358 memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
2359 if (qp->ibqp.qp_type == IB_QPT_RC ||
2360 qp->ibqp.qp_type == IB_QPT_UC ||
2361 qp->ibqp.qp_type == IB_QPT_XRC_INI ||
2362 qp->ibqp.qp_type == IB_QPT_XRC_TGT)
2363 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2364 grh->sgid_index);
2365 path->dci_cfi_prio_sl = (sl & 0x7) << 4;
2366 if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
2367 path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
2368 } else {
2369 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2370 path->fl_free_ar |=
2371 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2372 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
2373 path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
2374 if (ah_flags & IB_AH_GRH)
2375 path->grh_mlid |= 1 << 7;
2376 path->dci_cfi_prio_sl = sl & 0xf;
2377 }
2378
2379 if (ah_flags & IB_AH_GRH) {
2380 path->mgid_index = grh->sgid_index;
2381 path->hop_limit = grh->hop_limit;
2382 path->tclass_flowlabel =
2383 cpu_to_be32((grh->traffic_class << 20) |
2384 (grh->flow_label));
2385 memcpy(path->rgid, grh->dgid.raw, 16);
2386 }
2387
2388 err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
2389 if (err < 0)
2390 return err;
2391 path->static_rate = err;
2392 path->port = port;
2393
2394 if (attr_mask & IB_QP_TIMEOUT)
2395 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2396
2397 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2398 return modify_raw_packet_eth_prio(dev->mdev,
2399 &qp->raw_packet_qp.sq,
2400 sl & 0xf);
2401
2402 return 0;
2403 }
2404
2405 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2406 [MLX5_QP_STATE_INIT] = {
2407 [MLX5_QP_STATE_INIT] = {
2408 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2409 MLX5_QP_OPTPAR_RAE |
2410 MLX5_QP_OPTPAR_RWE |
2411 MLX5_QP_OPTPAR_PKEY_INDEX |
2412 MLX5_QP_OPTPAR_PRI_PORT,
2413 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2414 MLX5_QP_OPTPAR_PKEY_INDEX |
2415 MLX5_QP_OPTPAR_PRI_PORT,
2416 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2417 MLX5_QP_OPTPAR_Q_KEY |
2418 MLX5_QP_OPTPAR_PRI_PORT,
2419 },
2420 [MLX5_QP_STATE_RTR] = {
2421 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2422 MLX5_QP_OPTPAR_RRE |
2423 MLX5_QP_OPTPAR_RAE |
2424 MLX5_QP_OPTPAR_RWE |
2425 MLX5_QP_OPTPAR_PKEY_INDEX,
2426 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2427 MLX5_QP_OPTPAR_RWE |
2428 MLX5_QP_OPTPAR_PKEY_INDEX,
2429 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2430 MLX5_QP_OPTPAR_Q_KEY,
2431 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2432 MLX5_QP_OPTPAR_Q_KEY,
2433 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2434 MLX5_QP_OPTPAR_RRE |
2435 MLX5_QP_OPTPAR_RAE |
2436 MLX5_QP_OPTPAR_RWE |
2437 MLX5_QP_OPTPAR_PKEY_INDEX,
2438 },
2439 },
2440 [MLX5_QP_STATE_RTR] = {
2441 [MLX5_QP_STATE_RTS] = {
2442 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2443 MLX5_QP_OPTPAR_RRE |
2444 MLX5_QP_OPTPAR_RAE |
2445 MLX5_QP_OPTPAR_RWE |
2446 MLX5_QP_OPTPAR_PM_STATE |
2447 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2448 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2449 MLX5_QP_OPTPAR_RWE |
2450 MLX5_QP_OPTPAR_PM_STATE,
2451 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2452 },
2453 },
2454 [MLX5_QP_STATE_RTS] = {
2455 [MLX5_QP_STATE_RTS] = {
2456 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2457 MLX5_QP_OPTPAR_RAE |
2458 MLX5_QP_OPTPAR_RWE |
2459 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2460 MLX5_QP_OPTPAR_PM_STATE |
2461 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2462 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2463 MLX5_QP_OPTPAR_PM_STATE |
2464 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2465 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2466 MLX5_QP_OPTPAR_SRQN |
2467 MLX5_QP_OPTPAR_CQN_RCV,
2468 },
2469 },
2470 [MLX5_QP_STATE_SQER] = {
2471 [MLX5_QP_STATE_RTS] = {
2472 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2473 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2474 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2475 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2476 MLX5_QP_OPTPAR_RWE |
2477 MLX5_QP_OPTPAR_RAE |
2478 MLX5_QP_OPTPAR_RRE,
2479 },
2480 },
2481 };
2482
2483 static int ib_nr_to_mlx5_nr(int ib_mask)
2484 {
2485 switch (ib_mask) {
2486 case IB_QP_STATE:
2487 return 0;
2488 case IB_QP_CUR_STATE:
2489 return 0;
2490 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2491 return 0;
2492 case IB_QP_ACCESS_FLAGS:
2493 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2494 MLX5_QP_OPTPAR_RAE;
2495 case IB_QP_PKEY_INDEX:
2496 return MLX5_QP_OPTPAR_PKEY_INDEX;
2497 case IB_QP_PORT:
2498 return MLX5_QP_OPTPAR_PRI_PORT;
2499 case IB_QP_QKEY:
2500 return MLX5_QP_OPTPAR_Q_KEY;
2501 case IB_QP_AV:
2502 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2503 MLX5_QP_OPTPAR_PRI_PORT;
2504 case IB_QP_PATH_MTU:
2505 return 0;
2506 case IB_QP_TIMEOUT:
2507 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2508 case IB_QP_RETRY_CNT:
2509 return MLX5_QP_OPTPAR_RETRY_COUNT;
2510 case IB_QP_RNR_RETRY:
2511 return MLX5_QP_OPTPAR_RNR_RETRY;
2512 case IB_QP_RQ_PSN:
2513 return 0;
2514 case IB_QP_MAX_QP_RD_ATOMIC:
2515 return MLX5_QP_OPTPAR_SRA_MAX;
2516 case IB_QP_ALT_PATH:
2517 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2518 case IB_QP_MIN_RNR_TIMER:
2519 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2520 case IB_QP_SQ_PSN:
2521 return 0;
2522 case IB_QP_MAX_DEST_RD_ATOMIC:
2523 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2524 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2525 case IB_QP_PATH_MIG_STATE:
2526 return MLX5_QP_OPTPAR_PM_STATE;
2527 case IB_QP_CAP:
2528 return 0;
2529 case IB_QP_DEST_QPN:
2530 return 0;
2531 }
2532 return 0;
2533 }
2534
2535 static int ib_mask_to_mlx5_opt(int ib_mask)
2536 {
2537 int result = 0;
2538 int i;
2539
2540 for (i = 0; i < 8 * sizeof(int); i++) {
2541 if ((1 << i) & ib_mask)
2542 result |= ib_nr_to_mlx5_nr(1 << i);
2543 }
2544
2545 return result;
2546 }
2547
2548 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2549 struct mlx5_ib_rq *rq, int new_state,
2550 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2551 {
2552 void *in;
2553 void *rqc;
2554 int inlen;
2555 int err;
2556
2557 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2558 in = kvzalloc(inlen, GFP_KERNEL);
2559 if (!in)
2560 return -ENOMEM;
2561
2562 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2563
2564 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2565 MLX5_SET(rqc, rqc, state, new_state);
2566
2567 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2568 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2569 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2570 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
2571 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2572 } else
2573 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2574 dev->ib_dev.name);
2575 }
2576
2577 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2578 if (err)
2579 goto out;
2580
2581 rq->state = new_state;
2582
2583 out:
2584 kvfree(in);
2585 return err;
2586 }
2587
2588 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2589 struct mlx5_ib_sq *sq,
2590 int new_state,
2591 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2592 {
2593 struct mlx5_ib_qp *ibqp = sq->base.container_mibqp;
2594 u32 old_rate = ibqp->rate_limit;
2595 u32 new_rate = old_rate;
2596 u16 rl_index = 0;
2597 void *in;
2598 void *sqc;
2599 int inlen;
2600 int err;
2601
2602 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2603 in = kvzalloc(inlen, GFP_KERNEL);
2604 if (!in)
2605 return -ENOMEM;
2606
2607 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2608
2609 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2610 MLX5_SET(sqc, sqc, state, new_state);
2611
2612 if (raw_qp_param->set_mask & MLX5_RAW_QP_RATE_LIMIT) {
2613 if (new_state != MLX5_SQC_STATE_RDY)
2614 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2615 __func__);
2616 else
2617 new_rate = raw_qp_param->rate_limit;
2618 }
2619
2620 if (old_rate != new_rate) {
2621 if (new_rate) {
2622 err = mlx5_rl_add_rate(dev, new_rate, &rl_index);
2623 if (err) {
2624 pr_err("Failed configuring rate %u: %d\n",
2625 new_rate, err);
2626 goto out;
2627 }
2628 }
2629
2630 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
2631 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, rl_index);
2632 }
2633
2634 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2635 if (err) {
2636 /* Remove new rate from table if failed */
2637 if (new_rate &&
2638 old_rate != new_rate)
2639 mlx5_rl_remove_rate(dev, new_rate);
2640 goto out;
2641 }
2642
2643 /* Only remove the old rate after new rate was set */
2644 if ((old_rate &&
2645 (old_rate != new_rate)) ||
2646 (new_state != MLX5_SQC_STATE_RDY))
2647 mlx5_rl_remove_rate(dev, old_rate);
2648
2649 ibqp->rate_limit = new_rate;
2650 sq->state = new_state;
2651
2652 out:
2653 kvfree(in);
2654 return err;
2655 }
2656
2657 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2658 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2659 u8 tx_affinity)
2660 {
2661 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2662 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2663 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2664 int modify_rq = !!qp->rq.wqe_cnt;
2665 int modify_sq = !!qp->sq.wqe_cnt;
2666 int rq_state;
2667 int sq_state;
2668 int err;
2669
2670 switch (raw_qp_param->operation) {
2671 case MLX5_CMD_OP_RST2INIT_QP:
2672 rq_state = MLX5_RQC_STATE_RDY;
2673 sq_state = MLX5_SQC_STATE_RDY;
2674 break;
2675 case MLX5_CMD_OP_2ERR_QP:
2676 rq_state = MLX5_RQC_STATE_ERR;
2677 sq_state = MLX5_SQC_STATE_ERR;
2678 break;
2679 case MLX5_CMD_OP_2RST_QP:
2680 rq_state = MLX5_RQC_STATE_RST;
2681 sq_state = MLX5_SQC_STATE_RST;
2682 break;
2683 case MLX5_CMD_OP_RTR2RTS_QP:
2684 case MLX5_CMD_OP_RTS2RTS_QP:
2685 if (raw_qp_param->set_mask ==
2686 MLX5_RAW_QP_RATE_LIMIT) {
2687 modify_rq = 0;
2688 sq_state = sq->state;
2689 } else {
2690 return raw_qp_param->set_mask ? -EINVAL : 0;
2691 }
2692 break;
2693 case MLX5_CMD_OP_INIT2INIT_QP:
2694 case MLX5_CMD_OP_INIT2RTR_QP:
2695 if (raw_qp_param->set_mask)
2696 return -EINVAL;
2697 else
2698 return 0;
2699 default:
2700 WARN_ON(1);
2701 return -EINVAL;
2702 }
2703
2704 if (modify_rq) {
2705 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2706 if (err)
2707 return err;
2708 }
2709
2710 if (modify_sq) {
2711 if (tx_affinity) {
2712 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2713 tx_affinity);
2714 if (err)
2715 return err;
2716 }
2717
2718 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state, raw_qp_param);
2719 }
2720
2721 return 0;
2722 }
2723
2724 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2725 const struct ib_qp_attr *attr, int attr_mask,
2726 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2727 {
2728 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2729 [MLX5_QP_STATE_RST] = {
2730 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2731 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2732 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2733 },
2734 [MLX5_QP_STATE_INIT] = {
2735 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2736 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2737 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2738 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2739 },
2740 [MLX5_QP_STATE_RTR] = {
2741 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2742 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2743 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2744 },
2745 [MLX5_QP_STATE_RTS] = {
2746 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2747 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2748 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2749 },
2750 [MLX5_QP_STATE_SQD] = {
2751 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2752 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2753 },
2754 [MLX5_QP_STATE_SQER] = {
2755 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2756 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2757 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2758 },
2759 [MLX5_QP_STATE_ERR] = {
2760 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2761 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2762 }
2763 };
2764
2765 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2766 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2767 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2768 struct mlx5_ib_cq *send_cq, *recv_cq;
2769 struct mlx5_qp_context *context;
2770 struct mlx5_ib_pd *pd;
2771 struct mlx5_ib_port *mibport = NULL;
2772 enum mlx5_qp_state mlx5_cur, mlx5_new;
2773 enum mlx5_qp_optpar optpar;
2774 int mlx5_st;
2775 int err;
2776 u16 op;
2777 u8 tx_affinity = 0;
2778
2779 context = kzalloc(sizeof(*context), GFP_KERNEL);
2780 if (!context)
2781 return -ENOMEM;
2782
2783 err = to_mlx5_st(ibqp->qp_type);
2784 if (err < 0) {
2785 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2786 goto out;
2787 }
2788
2789 context->flags = cpu_to_be32(err << 16);
2790
2791 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2792 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2793 } else {
2794 switch (attr->path_mig_state) {
2795 case IB_MIG_MIGRATED:
2796 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2797 break;
2798 case IB_MIG_REARM:
2799 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2800 break;
2801 case IB_MIG_ARMED:
2802 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2803 break;
2804 }
2805 }
2806
2807 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2808 if ((ibqp->qp_type == IB_QPT_RC) ||
2809 (ibqp->qp_type == IB_QPT_UD &&
2810 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2811 (ibqp->qp_type == IB_QPT_UC) ||
2812 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2813 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2814 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2815 if (mlx5_lag_is_active(dev->mdev)) {
2816 tx_affinity = (unsigned int)atomic_add_return(1,
2817 &dev->roce.next_port) %
2818 MLX5_MAX_PORTS + 1;
2819 context->flags |= cpu_to_be32(tx_affinity << 24);
2820 }
2821 }
2822 }
2823
2824 if (is_sqp(ibqp->qp_type)) {
2825 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2826 } else if ((ibqp->qp_type == IB_QPT_UD &&
2827 !(qp->flags & MLX5_IB_QP_UNDERLAY)) ||
2828 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2829 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2830 } else if (attr_mask & IB_QP_PATH_MTU) {
2831 if (attr->path_mtu < IB_MTU_256 ||
2832 attr->path_mtu > IB_MTU_4096) {
2833 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2834 err = -EINVAL;
2835 goto out;
2836 }
2837 context->mtu_msgmax = (attr->path_mtu << 5) |
2838 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2839 }
2840
2841 if (attr_mask & IB_QP_DEST_QPN)
2842 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2843
2844 if (attr_mask & IB_QP_PKEY_INDEX)
2845 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2846
2847 /* todo implement counter_index functionality */
2848
2849 if (is_sqp(ibqp->qp_type))
2850 context->pri_path.port = qp->port;
2851
2852 if (attr_mask & IB_QP_PORT)
2853 context->pri_path.port = attr->port_num;
2854
2855 if (attr_mask & IB_QP_AV) {
2856 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2857 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2858 attr_mask, 0, attr, false);
2859 if (err)
2860 goto out;
2861 }
2862
2863 if (attr_mask & IB_QP_TIMEOUT)
2864 context->pri_path.ackto_lt |= attr->timeout << 3;
2865
2866 if (attr_mask & IB_QP_ALT_PATH) {
2867 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2868 &context->alt_path,
2869 attr->alt_port_num,
2870 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2871 0, attr, true);
2872 if (err)
2873 goto out;
2874 }
2875
2876 pd = get_pd(qp);
2877 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2878 &send_cq, &recv_cq);
2879
2880 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2881 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2882 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2883 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2884
2885 if (attr_mask & IB_QP_RNR_RETRY)
2886 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2887
2888 if (attr_mask & IB_QP_RETRY_CNT)
2889 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2890
2891 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2892 if (attr->max_rd_atomic)
2893 context->params1 |=
2894 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2895 }
2896
2897 if (attr_mask & IB_QP_SQ_PSN)
2898 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2899
2900 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2901 if (attr->max_dest_rd_atomic)
2902 context->params2 |=
2903 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2904 }
2905
2906 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2907 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2908
2909 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2910 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2911
2912 if (attr_mask & IB_QP_RQ_PSN)
2913 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2914
2915 if (attr_mask & IB_QP_QKEY)
2916 context->qkey = cpu_to_be32(attr->qkey);
2917
2918 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2919 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2920
2921 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2922 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2923 qp->port) - 1;
2924
2925 /* Underlay port should be used - index 0 function per port */
2926 if (qp->flags & MLX5_IB_QP_UNDERLAY)
2927 port_num = 0;
2928
2929 mibport = &dev->port[port_num];
2930 context->qp_counter_set_usr_page |=
2931 cpu_to_be32((u32)(mibport->cnts.set_id) << 24);
2932 }
2933
2934 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2935 context->sq_crq_size |= cpu_to_be16(1 << 4);
2936
2937 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2938 context->deth_sqpn = cpu_to_be32(1);
2939
2940 mlx5_cur = to_mlx5_state(cur_state);
2941 mlx5_new = to_mlx5_state(new_state);
2942 mlx5_st = to_mlx5_st(ibqp->qp_type);
2943 if (mlx5_st < 0)
2944 goto out;
2945
2946 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2947 !optab[mlx5_cur][mlx5_new]) {
2948 err = -EINVAL;
2949 goto out;
2950 }
2951
2952 op = optab[mlx5_cur][mlx5_new];
2953 optpar = ib_mask_to_mlx5_opt(attr_mask);
2954 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2955
2956 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
2957 qp->flags & MLX5_IB_QP_UNDERLAY) {
2958 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2959
2960 raw_qp_param.operation = op;
2961 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2962 raw_qp_param.rq_q_ctr_id = mibport->cnts.set_id;
2963 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2964 }
2965
2966 if (attr_mask & IB_QP_RATE_LIMIT) {
2967 raw_qp_param.rate_limit = attr->rate_limit;
2968 raw_qp_param.set_mask |= MLX5_RAW_QP_RATE_LIMIT;
2969 }
2970
2971 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2972 } else {
2973 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2974 &base->mqp);
2975 }
2976
2977 if (err)
2978 goto out;
2979
2980 qp->state = new_state;
2981
2982 if (attr_mask & IB_QP_ACCESS_FLAGS)
2983 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2984 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2985 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2986 if (attr_mask & IB_QP_PORT)
2987 qp->port = attr->port_num;
2988 if (attr_mask & IB_QP_ALT_PATH)
2989 qp->trans_qp.alt_port = attr->alt_port_num;
2990
2991 /*
2992 * If we moved a kernel QP to RESET, clean up all old CQ
2993 * entries and reinitialize the QP.
2994 */
2995 if (new_state == IB_QPS_RESET &&
2996 !ibqp->uobject && ibqp->qp_type != IB_QPT_XRC_TGT) {
2997 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2998 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2999 if (send_cq != recv_cq)
3000 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
3001
3002 qp->rq.head = 0;
3003 qp->rq.tail = 0;
3004 qp->sq.head = 0;
3005 qp->sq.tail = 0;
3006 qp->sq.cur_post = 0;
3007 qp->sq.last_poll = 0;
3008 qp->db.db[MLX5_RCV_DBR] = 0;
3009 qp->db.db[MLX5_SND_DBR] = 0;
3010 }
3011
3012 out:
3013 kfree(context);
3014 return err;
3015 }
3016
3017 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
3018 int attr_mask, struct ib_udata *udata)
3019 {
3020 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3021 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3022 enum ib_qp_type qp_type;
3023 enum ib_qp_state cur_state, new_state;
3024 int err = -EINVAL;
3025 int port;
3026 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
3027
3028 if (ibqp->rwq_ind_tbl)
3029 return -ENOSYS;
3030
3031 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3032 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
3033
3034 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
3035 IB_QPT_GSI : ibqp->qp_type;
3036
3037 mutex_lock(&qp->mutex);
3038
3039 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
3040 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
3041
3042 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
3043 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3044 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
3045 }
3046
3047 if (qp->flags & MLX5_IB_QP_UNDERLAY) {
3048 if (attr_mask & ~(IB_QP_STATE | IB_QP_CUR_STATE)) {
3049 mlx5_ib_dbg(dev, "invalid attr_mask 0x%x when underlay QP is used\n",
3050 attr_mask);
3051 goto out;
3052 }
3053 } else if (qp_type != MLX5_IB_QPT_REG_UMR &&
3054 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
3055 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3056 cur_state, new_state, ibqp->qp_type, attr_mask);
3057 goto out;
3058 }
3059
3060 if ((attr_mask & IB_QP_PORT) &&
3061 (attr->port_num == 0 ||
3062 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
3063 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
3064 attr->port_num, dev->num_ports);
3065 goto out;
3066 }
3067
3068 if (attr_mask & IB_QP_PKEY_INDEX) {
3069 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
3070 if (attr->pkey_index >=
3071 dev->mdev->port_caps[port - 1].pkey_table_len) {
3072 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
3073 attr->pkey_index);
3074 goto out;
3075 }
3076 }
3077
3078 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
3079 attr->max_rd_atomic >
3080 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
3081 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
3082 attr->max_rd_atomic);
3083 goto out;
3084 }
3085
3086 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
3087 attr->max_dest_rd_atomic >
3088 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
3089 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
3090 attr->max_dest_rd_atomic);
3091 goto out;
3092 }
3093
3094 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
3095 err = 0;
3096 goto out;
3097 }
3098
3099 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
3100
3101 out:
3102 mutex_unlock(&qp->mutex);
3103 return err;
3104 }
3105
3106 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3107 {
3108 struct mlx5_ib_cq *cq;
3109 unsigned cur;
3110
3111 cur = wq->head - wq->tail;
3112 if (likely(cur + nreq < wq->max_post))
3113 return 0;
3114
3115 cq = to_mcq(ib_cq);
3116 spin_lock(&cq->lock);
3117 cur = wq->head - wq->tail;
3118 spin_unlock(&cq->lock);
3119
3120 return cur + nreq >= wq->max_post;
3121 }
3122
3123 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
3124 u64 remote_addr, u32 rkey)
3125 {
3126 rseg->raddr = cpu_to_be64(remote_addr);
3127 rseg->rkey = cpu_to_be32(rkey);
3128 rseg->reserved = 0;
3129 }
3130
3131 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
3132 struct ib_send_wr *wr, void *qend,
3133 struct mlx5_ib_qp *qp, int *size)
3134 {
3135 void *seg = eseg;
3136
3137 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
3138
3139 if (wr->send_flags & IB_SEND_IP_CSUM)
3140 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
3141 MLX5_ETH_WQE_L4_CSUM;
3142
3143 seg += sizeof(struct mlx5_wqe_eth_seg);
3144 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
3145
3146 if (wr->opcode == IB_WR_LSO) {
3147 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
3148 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr.start);
3149 u64 left, leftlen, copysz;
3150 void *pdata = ud_wr->header;
3151
3152 left = ud_wr->hlen;
3153 eseg->mss = cpu_to_be16(ud_wr->mss);
3154 eseg->inline_hdr.sz = cpu_to_be16(left);
3155
3156 /*
3157 * check if there is space till the end of queue, if yes,
3158 * copy all in one shot, otherwise copy till the end of queue,
3159 * rollback and than the copy the left
3160 */
3161 leftlen = qend - (void *)eseg->inline_hdr.start;
3162 copysz = min_t(u64, leftlen, left);
3163
3164 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
3165
3166 if (likely(copysz > size_of_inl_hdr_start)) {
3167 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
3168 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
3169 }
3170
3171 if (unlikely(copysz < left)) { /* the last wqe in the queue */
3172 seg = mlx5_get_send_wqe(qp, 0);
3173 left -= copysz;
3174 pdata += copysz;
3175 memcpy(seg, pdata, left);
3176 seg += ALIGN(left, 16);
3177 *size += ALIGN(left, 16) / 16;
3178 }
3179 }
3180
3181 return seg;
3182 }
3183
3184 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
3185 struct ib_send_wr *wr)
3186 {
3187 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
3188 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
3189 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
3190 }
3191
3192 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
3193 {
3194 dseg->byte_count = cpu_to_be32(sg->length);
3195 dseg->lkey = cpu_to_be32(sg->lkey);
3196 dseg->addr = cpu_to_be64(sg->addr);
3197 }
3198
3199 static u64 get_xlt_octo(u64 bytes)
3200 {
3201 return ALIGN(bytes, MLX5_IB_UMR_XLT_ALIGNMENT) /
3202 MLX5_IB_UMR_OCTOWORD;
3203 }
3204
3205 static __be64 frwr_mkey_mask(void)
3206 {
3207 u64 result;
3208
3209 result = MLX5_MKEY_MASK_LEN |
3210 MLX5_MKEY_MASK_PAGE_SIZE |
3211 MLX5_MKEY_MASK_START_ADDR |
3212 MLX5_MKEY_MASK_EN_RINVAL |
3213 MLX5_MKEY_MASK_KEY |
3214 MLX5_MKEY_MASK_LR |
3215 MLX5_MKEY_MASK_LW |
3216 MLX5_MKEY_MASK_RR |
3217 MLX5_MKEY_MASK_RW |
3218 MLX5_MKEY_MASK_A |
3219 MLX5_MKEY_MASK_SMALL_FENCE |
3220 MLX5_MKEY_MASK_FREE;
3221
3222 return cpu_to_be64(result);
3223 }
3224
3225 static __be64 sig_mkey_mask(void)
3226 {
3227 u64 result;
3228
3229 result = MLX5_MKEY_MASK_LEN |
3230 MLX5_MKEY_MASK_PAGE_SIZE |
3231 MLX5_MKEY_MASK_START_ADDR |
3232 MLX5_MKEY_MASK_EN_SIGERR |
3233 MLX5_MKEY_MASK_EN_RINVAL |
3234 MLX5_MKEY_MASK_KEY |
3235 MLX5_MKEY_MASK_LR |
3236 MLX5_MKEY_MASK_LW |
3237 MLX5_MKEY_MASK_RR |
3238 MLX5_MKEY_MASK_RW |
3239 MLX5_MKEY_MASK_SMALL_FENCE |
3240 MLX5_MKEY_MASK_FREE |
3241 MLX5_MKEY_MASK_BSF_EN;
3242
3243 return cpu_to_be64(result);
3244 }
3245
3246 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3247 struct mlx5_ib_mr *mr)
3248 {
3249 int size = mr->ndescs * mr->desc_size;
3250
3251 memset(umr, 0, sizeof(*umr));
3252
3253 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3254 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3255 umr->mkey_mask = frwr_mkey_mask();
3256 }
3257
3258 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3259 {
3260 memset(umr, 0, sizeof(*umr));
3261 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3262 umr->flags = MLX5_UMR_INLINE;
3263 }
3264
3265 static __be64 get_umr_enable_mr_mask(void)
3266 {
3267 u64 result;
3268
3269 result = MLX5_MKEY_MASK_KEY |
3270 MLX5_MKEY_MASK_FREE;
3271
3272 return cpu_to_be64(result);
3273 }
3274
3275 static __be64 get_umr_disable_mr_mask(void)
3276 {
3277 u64 result;
3278
3279 result = MLX5_MKEY_MASK_FREE;
3280
3281 return cpu_to_be64(result);
3282 }
3283
3284 static __be64 get_umr_update_translation_mask(void)
3285 {
3286 u64 result;
3287
3288 result = MLX5_MKEY_MASK_LEN |
3289 MLX5_MKEY_MASK_PAGE_SIZE |
3290 MLX5_MKEY_MASK_START_ADDR;
3291
3292 return cpu_to_be64(result);
3293 }
3294
3295 static __be64 get_umr_update_access_mask(int atomic)
3296 {
3297 u64 result;
3298
3299 result = MLX5_MKEY_MASK_LR |
3300 MLX5_MKEY_MASK_LW |
3301 MLX5_MKEY_MASK_RR |
3302 MLX5_MKEY_MASK_RW;
3303
3304 if (atomic)
3305 result |= MLX5_MKEY_MASK_A;
3306
3307 return cpu_to_be64(result);
3308 }
3309
3310 static __be64 get_umr_update_pd_mask(void)
3311 {
3312 u64 result;
3313
3314 result = MLX5_MKEY_MASK_PD;
3315
3316 return cpu_to_be64(result);
3317 }
3318
3319 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3320 struct ib_send_wr *wr, int atomic)
3321 {
3322 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3323
3324 memset(umr, 0, sizeof(*umr));
3325
3326 if (!umrwr->ignore_free_state) {
3327 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3328 /* fail if free */
3329 umr->flags = MLX5_UMR_CHECK_FREE;
3330 else
3331 /* fail if not free */
3332 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3333 }
3334
3335 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(umrwr->xlt_size));
3336 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_XLT) {
3337 u64 offset = get_xlt_octo(umrwr->offset);
3338
3339 umr->xlt_offset = cpu_to_be16(offset & 0xffff);
3340 umr->xlt_offset_47_16 = cpu_to_be32(offset >> 16);
3341 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3342 }
3343 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3344 umr->mkey_mask |= get_umr_update_translation_mask();
3345 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS) {
3346 umr->mkey_mask |= get_umr_update_access_mask(atomic);
3347 umr->mkey_mask |= get_umr_update_pd_mask();
3348 }
3349 if (wr->send_flags & MLX5_IB_SEND_UMR_ENABLE_MR)
3350 umr->mkey_mask |= get_umr_enable_mr_mask();
3351 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3352 umr->mkey_mask |= get_umr_disable_mr_mask();
3353
3354 if (!wr->num_sge)
3355 umr->flags |= MLX5_UMR_INLINE;
3356 }
3357
3358 static u8 get_umr_flags(int acc)
3359 {
3360 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3361 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3362 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3363 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3364 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3365 }
3366
3367 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3368 struct mlx5_ib_mr *mr,
3369 u32 key, int access)
3370 {
3371 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3372
3373 memset(seg, 0, sizeof(*seg));
3374
3375 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3376 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3377 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3378 /* KLMs take twice the size of MTTs */
3379 ndescs *= 2;
3380
3381 seg->flags = get_umr_flags(access) | mr->access_mode;
3382 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3383 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3384 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3385 seg->len = cpu_to_be64(mr->ibmr.length);
3386 seg->xlt_oct_size = cpu_to_be32(ndescs);
3387 }
3388
3389 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3390 {
3391 memset(seg, 0, sizeof(*seg));
3392 seg->status = MLX5_MKEY_STATUS_FREE;
3393 }
3394
3395 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3396 {
3397 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3398
3399 memset(seg, 0, sizeof(*seg));
3400 if (wr->send_flags & MLX5_IB_SEND_UMR_DISABLE_MR)
3401 seg->status = MLX5_MKEY_STATUS_FREE;
3402
3403 seg->flags = convert_access(umrwr->access_flags);
3404 if (umrwr->pd)
3405 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3406 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION &&
3407 !umrwr->length)
3408 seg->flags_pd |= cpu_to_be32(MLX5_MKEY_LEN64);
3409
3410 seg->start_addr = cpu_to_be64(umrwr->virt_addr);
3411 seg->len = cpu_to_be64(umrwr->length);
3412 seg->log2_page_size = umrwr->page_shift;
3413 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3414 mlx5_mkey_variant(umrwr->mkey));
3415 }
3416
3417 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3418 struct mlx5_ib_mr *mr,
3419 struct mlx5_ib_pd *pd)
3420 {
3421 int bcount = mr->desc_size * mr->ndescs;
3422
3423 dseg->addr = cpu_to_be64(mr->desc_map);
3424 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3425 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3426 }
3427
3428 static __be32 send_ieth(struct ib_send_wr *wr)
3429 {
3430 switch (wr->opcode) {
3431 case IB_WR_SEND_WITH_IMM:
3432 case IB_WR_RDMA_WRITE_WITH_IMM:
3433 return wr->ex.imm_data;
3434
3435 case IB_WR_SEND_WITH_INV:
3436 return cpu_to_be32(wr->ex.invalidate_rkey);
3437
3438 default:
3439 return 0;
3440 }
3441 }
3442
3443 static u8 calc_sig(void *wqe, int size)
3444 {
3445 u8 *p = wqe;
3446 u8 res = 0;
3447 int i;
3448
3449 for (i = 0; i < size; i++)
3450 res ^= p[i];
3451
3452 return ~res;
3453 }
3454
3455 static u8 wq_sig(void *wqe)
3456 {
3457 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3458 }
3459
3460 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3461 void *wqe, int *sz)
3462 {
3463 struct mlx5_wqe_inline_seg *seg;
3464 void *qend = qp->sq.qend;
3465 void *addr;
3466 int inl = 0;
3467 int copy;
3468 int len;
3469 int i;
3470
3471 seg = wqe;
3472 wqe += sizeof(*seg);
3473 for (i = 0; i < wr->num_sge; i++) {
3474 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3475 len = wr->sg_list[i].length;
3476 inl += len;
3477
3478 if (unlikely(inl > qp->max_inline_data))
3479 return -ENOMEM;
3480
3481 if (unlikely(wqe + len > qend)) {
3482 copy = qend - wqe;
3483 memcpy(wqe, addr, copy);
3484 addr += copy;
3485 len -= copy;
3486 wqe = mlx5_get_send_wqe(qp, 0);
3487 }
3488 memcpy(wqe, addr, len);
3489 wqe += len;
3490 }
3491
3492 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3493
3494 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3495
3496 return 0;
3497 }
3498
3499 static u16 prot_field_size(enum ib_signature_type type)
3500 {
3501 switch (type) {
3502 case IB_SIG_TYPE_T10_DIF:
3503 return MLX5_DIF_SIZE;
3504 default:
3505 return 0;
3506 }
3507 }
3508
3509 static u8 bs_selector(int block_size)
3510 {
3511 switch (block_size) {
3512 case 512: return 0x1;
3513 case 520: return 0x2;
3514 case 4096: return 0x3;
3515 case 4160: return 0x4;
3516 case 1073741824: return 0x5;
3517 default: return 0;
3518 }
3519 }
3520
3521 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3522 struct mlx5_bsf_inl *inl)
3523 {
3524 /* Valid inline section and allow BSF refresh */
3525 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3526 MLX5_BSF_REFRESH_DIF);
3527 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3528 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3529 /* repeating block */
3530 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3531 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3532 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3533
3534 if (domain->sig.dif.ref_remap)
3535 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3536
3537 if (domain->sig.dif.app_escape) {
3538 if (domain->sig.dif.ref_escape)
3539 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3540 else
3541 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3542 }
3543
3544 inl->dif_app_bitmask_check =
3545 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3546 }
3547
3548 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3549 struct ib_sig_attrs *sig_attrs,
3550 struct mlx5_bsf *bsf, u32 data_size)
3551 {
3552 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3553 struct mlx5_bsf_basic *basic = &bsf->basic;
3554 struct ib_sig_domain *mem = &sig_attrs->mem;
3555 struct ib_sig_domain *wire = &sig_attrs->wire;
3556
3557 memset(bsf, 0, sizeof(*bsf));
3558
3559 /* Basic + Extended + Inline */
3560 basic->bsf_size_sbs = 1 << 7;
3561 /* Input domain check byte mask */
3562 basic->check_byte_mask = sig_attrs->check_mask;
3563 basic->raw_data_size = cpu_to_be32(data_size);
3564
3565 /* Memory domain */
3566 switch (sig_attrs->mem.sig_type) {
3567 case IB_SIG_TYPE_NONE:
3568 break;
3569 case IB_SIG_TYPE_T10_DIF:
3570 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3571 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3572 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3573 break;
3574 default:
3575 return -EINVAL;
3576 }
3577
3578 /* Wire domain */
3579 switch (sig_attrs->wire.sig_type) {
3580 case IB_SIG_TYPE_NONE:
3581 break;
3582 case IB_SIG_TYPE_T10_DIF:
3583 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3584 mem->sig_type == wire->sig_type) {
3585 /* Same block structure */
3586 basic->bsf_size_sbs |= 1 << 4;
3587 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3588 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3589 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3590 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3591 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3592 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3593 } else
3594 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3595
3596 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3597 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3598 break;
3599 default:
3600 return -EINVAL;
3601 }
3602
3603 return 0;
3604 }
3605
3606 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3607 struct mlx5_ib_qp *qp, void **seg, int *size)
3608 {
3609 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3610 struct ib_mr *sig_mr = wr->sig_mr;
3611 struct mlx5_bsf *bsf;
3612 u32 data_len = wr->wr.sg_list->length;
3613 u32 data_key = wr->wr.sg_list->lkey;
3614 u64 data_va = wr->wr.sg_list->addr;
3615 int ret;
3616 int wqe_size;
3617
3618 if (!wr->prot ||
3619 (data_key == wr->prot->lkey &&
3620 data_va == wr->prot->addr &&
3621 data_len == wr->prot->length)) {
3622 /**
3623 * Source domain doesn't contain signature information
3624 * or data and protection are interleaved in memory.
3625 * So need construct:
3626 * ------------------
3627 * | data_klm |
3628 * ------------------
3629 * | BSF |
3630 * ------------------
3631 **/
3632 struct mlx5_klm *data_klm = *seg;
3633
3634 data_klm->bcount = cpu_to_be32(data_len);
3635 data_klm->key = cpu_to_be32(data_key);
3636 data_klm->va = cpu_to_be64(data_va);
3637 wqe_size = ALIGN(sizeof(*data_klm), 64);
3638 } else {
3639 /**
3640 * Source domain contains signature information
3641 * So need construct a strided block format:
3642 * ---------------------------
3643 * | stride_block_ctrl |
3644 * ---------------------------
3645 * | data_klm |
3646 * ---------------------------
3647 * | prot_klm |
3648 * ---------------------------
3649 * | BSF |
3650 * ---------------------------
3651 **/
3652 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3653 struct mlx5_stride_block_entry *data_sentry;
3654 struct mlx5_stride_block_entry *prot_sentry;
3655 u32 prot_key = wr->prot->lkey;
3656 u64 prot_va = wr->prot->addr;
3657 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3658 int prot_size;
3659
3660 sblock_ctrl = *seg;
3661 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3662 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3663
3664 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3665 if (!prot_size) {
3666 pr_err("Bad block size given: %u\n", block_size);
3667 return -EINVAL;
3668 }
3669 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3670 prot_size);
3671 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3672 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3673 sblock_ctrl->num_entries = cpu_to_be16(2);
3674
3675 data_sentry->bcount = cpu_to_be16(block_size);
3676 data_sentry->key = cpu_to_be32(data_key);
3677 data_sentry->va = cpu_to_be64(data_va);
3678 data_sentry->stride = cpu_to_be16(block_size);
3679
3680 prot_sentry->bcount = cpu_to_be16(prot_size);
3681 prot_sentry->key = cpu_to_be32(prot_key);
3682 prot_sentry->va = cpu_to_be64(prot_va);
3683 prot_sentry->stride = cpu_to_be16(prot_size);
3684
3685 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3686 sizeof(*prot_sentry), 64);
3687 }
3688
3689 *seg += wqe_size;
3690 *size += wqe_size / 16;
3691 if (unlikely((*seg == qp->sq.qend)))
3692 *seg = mlx5_get_send_wqe(qp, 0);
3693
3694 bsf = *seg;
3695 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3696 if (ret)
3697 return -EINVAL;
3698
3699 *seg += sizeof(*bsf);
3700 *size += sizeof(*bsf) / 16;
3701 if (unlikely((*seg == qp->sq.qend)))
3702 *seg = mlx5_get_send_wqe(qp, 0);
3703
3704 return 0;
3705 }
3706
3707 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3708 struct ib_sig_handover_wr *wr, u32 size,
3709 u32 length, u32 pdn)
3710 {
3711 struct ib_mr *sig_mr = wr->sig_mr;
3712 u32 sig_key = sig_mr->rkey;
3713 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3714
3715 memset(seg, 0, sizeof(*seg));
3716
3717 seg->flags = get_umr_flags(wr->access_flags) |
3718 MLX5_MKC_ACCESS_MODE_KLMS;
3719 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3720 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3721 MLX5_MKEY_BSF_EN | pdn);
3722 seg->len = cpu_to_be64(length);
3723 seg->xlt_oct_size = cpu_to_be32(get_xlt_octo(size));
3724 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3725 }
3726
3727 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3728 u32 size)
3729 {
3730 memset(umr, 0, sizeof(*umr));
3731
3732 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3733 umr->xlt_octowords = cpu_to_be16(get_xlt_octo(size));
3734 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3735 umr->mkey_mask = sig_mkey_mask();
3736 }
3737
3738
3739 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3740 void **seg, int *size)
3741 {
3742 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3743 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3744 u32 pdn = get_pd(qp)->pdn;
3745 u32 xlt_size;
3746 int region_len, ret;
3747
3748 if (unlikely(wr->wr.num_sge != 1) ||
3749 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3750 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3751 unlikely(!sig_mr->sig->sig_status_checked))
3752 return -EINVAL;
3753
3754 /* length of the protected region, data + protection */
3755 region_len = wr->wr.sg_list->length;
3756 if (wr->prot &&
3757 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3758 wr->prot->addr != wr->wr.sg_list->addr ||
3759 wr->prot->length != wr->wr.sg_list->length))
3760 region_len += wr->prot->length;
3761
3762 /**
3763 * KLM octoword size - if protection was provided
3764 * then we use strided block format (3 octowords),
3765 * else we use single KLM (1 octoword)
3766 **/
3767 xlt_size = wr->prot ? 0x30 : sizeof(struct mlx5_klm);
3768
3769 set_sig_umr_segment(*seg, xlt_size);
3770 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3771 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3772 if (unlikely((*seg == qp->sq.qend)))
3773 *seg = mlx5_get_send_wqe(qp, 0);
3774
3775 set_sig_mkey_segment(*seg, wr, xlt_size, region_len, pdn);
3776 *seg += sizeof(struct mlx5_mkey_seg);
3777 *size += sizeof(struct mlx5_mkey_seg) / 16;
3778 if (unlikely((*seg == qp->sq.qend)))
3779 *seg = mlx5_get_send_wqe(qp, 0);
3780
3781 ret = set_sig_data_segment(wr, qp, seg, size);
3782 if (ret)
3783 return ret;
3784
3785 sig_mr->sig->sig_status_checked = false;
3786 return 0;
3787 }
3788
3789 static int set_psv_wr(struct ib_sig_domain *domain,
3790 u32 psv_idx, void **seg, int *size)
3791 {
3792 struct mlx5_seg_set_psv *psv_seg = *seg;
3793
3794 memset(psv_seg, 0, sizeof(*psv_seg));
3795 psv_seg->psv_num = cpu_to_be32(psv_idx);
3796 switch (domain->sig_type) {
3797 case IB_SIG_TYPE_NONE:
3798 break;
3799 case IB_SIG_TYPE_T10_DIF:
3800 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3801 domain->sig.dif.app_tag);
3802 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3803 break;
3804 default:
3805 pr_err("Bad signature type (%d) is given.\n",
3806 domain->sig_type);
3807 return -EINVAL;
3808 }
3809
3810 *seg += sizeof(*psv_seg);
3811 *size += sizeof(*psv_seg) / 16;
3812
3813 return 0;
3814 }
3815
3816 static int set_reg_wr(struct mlx5_ib_qp *qp,
3817 struct ib_reg_wr *wr,
3818 void **seg, int *size)
3819 {
3820 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3821 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3822
3823 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3824 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3825 "Invalid IB_SEND_INLINE send flag\n");
3826 return -EINVAL;
3827 }
3828
3829 set_reg_umr_seg(*seg, mr);
3830 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3831 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3832 if (unlikely((*seg == qp->sq.qend)))
3833 *seg = mlx5_get_send_wqe(qp, 0);
3834
3835 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3836 *seg += sizeof(struct mlx5_mkey_seg);
3837 *size += sizeof(struct mlx5_mkey_seg) / 16;
3838 if (unlikely((*seg == qp->sq.qend)))
3839 *seg = mlx5_get_send_wqe(qp, 0);
3840
3841 set_reg_data_seg(*seg, mr, pd);
3842 *seg += sizeof(struct mlx5_wqe_data_seg);
3843 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3844
3845 return 0;
3846 }
3847
3848 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3849 {
3850 set_linv_umr_seg(*seg);
3851 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3852 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3853 if (unlikely((*seg == qp->sq.qend)))
3854 *seg = mlx5_get_send_wqe(qp, 0);
3855 set_linv_mkey_seg(*seg);
3856 *seg += sizeof(struct mlx5_mkey_seg);
3857 *size += sizeof(struct mlx5_mkey_seg) / 16;
3858 if (unlikely((*seg == qp->sq.qend)))
3859 *seg = mlx5_get_send_wqe(qp, 0);
3860 }
3861
3862 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3863 {
3864 __be32 *p = NULL;
3865 int tidx = idx;
3866 int i, j;
3867
3868 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3869 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3870 if ((i & 0xf) == 0) {
3871 void *buf = mlx5_get_send_wqe(qp, tidx);
3872 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3873 p = buf;
3874 j = 0;
3875 }
3876 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3877 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3878 be32_to_cpu(p[j + 3]));
3879 }
3880 }
3881
3882 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3883 struct mlx5_wqe_ctrl_seg **ctrl,
3884 struct ib_send_wr *wr, unsigned *idx,
3885 int *size, int nreq)
3886 {
3887 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3888 return -ENOMEM;
3889
3890 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3891 *seg = mlx5_get_send_wqe(qp, *idx);
3892 *ctrl = *seg;
3893 *(uint32_t *)(*seg + 8) = 0;
3894 (*ctrl)->imm = send_ieth(wr);
3895 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3896 (wr->send_flags & IB_SEND_SIGNALED ?
3897 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3898 (wr->send_flags & IB_SEND_SOLICITED ?
3899 MLX5_WQE_CTRL_SOLICITED : 0);
3900
3901 *seg += sizeof(**ctrl);
3902 *size = sizeof(**ctrl) / 16;
3903
3904 return 0;
3905 }
3906
3907 static void finish_wqe(struct mlx5_ib_qp *qp,
3908 struct mlx5_wqe_ctrl_seg *ctrl,
3909 u8 size, unsigned idx, u64 wr_id,
3910 int nreq, u8 fence, u32 mlx5_opcode)
3911 {
3912 u8 opmod = 0;
3913
3914 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3915 mlx5_opcode | ((u32)opmod << 24));
3916 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3917 ctrl->fm_ce_se |= fence;
3918 if (unlikely(qp->wq_sig))
3919 ctrl->signature = wq_sig(ctrl);
3920
3921 qp->sq.wrid[idx] = wr_id;
3922 qp->sq.w_list[idx].opcode = mlx5_opcode;
3923 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3924 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3925 qp->sq.w_list[idx].next = qp->sq.cur_post;
3926 }
3927
3928
3929 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3930 struct ib_send_wr **bad_wr)
3931 {
3932 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3933 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3934 struct mlx5_core_dev *mdev = dev->mdev;
3935 struct mlx5_ib_qp *qp;
3936 struct mlx5_ib_mr *mr;
3937 struct mlx5_wqe_data_seg *dpseg;
3938 struct mlx5_wqe_xrc_seg *xrc;
3939 struct mlx5_bf *bf;
3940 int uninitialized_var(size);
3941 void *qend;
3942 unsigned long flags;
3943 unsigned idx;
3944 int err = 0;
3945 int num_sge;
3946 void *seg;
3947 int nreq;
3948 int i;
3949 u8 next_fence = 0;
3950 u8 fence;
3951
3952 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3953 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3954
3955 qp = to_mqp(ibqp);
3956 bf = &qp->bf;
3957 qend = qp->sq.qend;
3958
3959 spin_lock_irqsave(&qp->sq.lock, flags);
3960
3961 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3962 err = -EIO;
3963 *bad_wr = wr;
3964 nreq = 0;
3965 goto out;
3966 }
3967
3968 for (nreq = 0; wr; nreq++, wr = wr->next) {
3969 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3970 mlx5_ib_warn(dev, "\n");
3971 err = -EINVAL;
3972 *bad_wr = wr;
3973 goto out;
3974 }
3975
3976 num_sge = wr->num_sge;
3977 if (unlikely(num_sge > qp->sq.max_gs)) {
3978 mlx5_ib_warn(dev, "\n");
3979 err = -EINVAL;
3980 *bad_wr = wr;
3981 goto out;
3982 }
3983
3984 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3985 if (err) {
3986 mlx5_ib_warn(dev, "\n");
3987 err = -ENOMEM;
3988 *bad_wr = wr;
3989 goto out;
3990 }
3991
3992 if (wr->opcode == IB_WR_REG_MR) {
3993 fence = dev->umr_fence;
3994 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3995 } else {
3996 if (wr->send_flags & IB_SEND_FENCE) {
3997 if (qp->next_fence)
3998 fence = MLX5_FENCE_MODE_SMALL_AND_FENCE;
3999 else
4000 fence = MLX5_FENCE_MODE_FENCE;
4001 } else {
4002 fence = qp->next_fence;
4003 }
4004 }
4005
4006 switch (ibqp->qp_type) {
4007 case IB_QPT_XRC_INI:
4008 xrc = seg;
4009 seg += sizeof(*xrc);
4010 size += sizeof(*xrc) / 16;
4011 /* fall through */
4012 case IB_QPT_RC:
4013 switch (wr->opcode) {
4014 case IB_WR_RDMA_READ:
4015 case IB_WR_RDMA_WRITE:
4016 case IB_WR_RDMA_WRITE_WITH_IMM:
4017 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4018 rdma_wr(wr)->rkey);
4019 seg += sizeof(struct mlx5_wqe_raddr_seg);
4020 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4021 break;
4022
4023 case IB_WR_ATOMIC_CMP_AND_SWP:
4024 case IB_WR_ATOMIC_FETCH_AND_ADD:
4025 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
4026 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
4027 err = -ENOSYS;
4028 *bad_wr = wr;
4029 goto out;
4030
4031 case IB_WR_LOCAL_INV:
4032 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
4033 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
4034 set_linv_wr(qp, &seg, &size);
4035 num_sge = 0;
4036 break;
4037
4038 case IB_WR_REG_MR:
4039 qp->sq.wr_data[idx] = IB_WR_REG_MR;
4040 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
4041 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
4042 if (err) {
4043 *bad_wr = wr;
4044 goto out;
4045 }
4046 num_sge = 0;
4047 break;
4048
4049 case IB_WR_REG_SIG_MR:
4050 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
4051 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
4052
4053 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
4054 err = set_sig_umr_wr(wr, qp, &seg, &size);
4055 if (err) {
4056 mlx5_ib_warn(dev, "\n");
4057 *bad_wr = wr;
4058 goto out;
4059 }
4060
4061 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4062 fence, MLX5_OPCODE_UMR);
4063 /*
4064 * SET_PSV WQEs are not signaled and solicited
4065 * on error
4066 */
4067 wr->send_flags &= ~IB_SEND_SIGNALED;
4068 wr->send_flags |= IB_SEND_SOLICITED;
4069 err = begin_wqe(qp, &seg, &ctrl, wr,
4070 &idx, &size, nreq);
4071 if (err) {
4072 mlx5_ib_warn(dev, "\n");
4073 err = -ENOMEM;
4074 *bad_wr = wr;
4075 goto out;
4076 }
4077
4078 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
4079 mr->sig->psv_memory.psv_idx, &seg,
4080 &size);
4081 if (err) {
4082 mlx5_ib_warn(dev, "\n");
4083 *bad_wr = wr;
4084 goto out;
4085 }
4086
4087 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4088 fence, MLX5_OPCODE_SET_PSV);
4089 err = begin_wqe(qp, &seg, &ctrl, wr,
4090 &idx, &size, nreq);
4091 if (err) {
4092 mlx5_ib_warn(dev, "\n");
4093 err = -ENOMEM;
4094 *bad_wr = wr;
4095 goto out;
4096 }
4097
4098 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
4099 mr->sig->psv_wire.psv_idx, &seg,
4100 &size);
4101 if (err) {
4102 mlx5_ib_warn(dev, "\n");
4103 *bad_wr = wr;
4104 goto out;
4105 }
4106
4107 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4108 fence, MLX5_OPCODE_SET_PSV);
4109 qp->next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
4110 num_sge = 0;
4111 goto skip_psv;
4112
4113 default:
4114 break;
4115 }
4116 break;
4117
4118 case IB_QPT_UC:
4119 switch (wr->opcode) {
4120 case IB_WR_RDMA_WRITE:
4121 case IB_WR_RDMA_WRITE_WITH_IMM:
4122 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
4123 rdma_wr(wr)->rkey);
4124 seg += sizeof(struct mlx5_wqe_raddr_seg);
4125 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
4126 break;
4127
4128 default:
4129 break;
4130 }
4131 break;
4132
4133 case IB_QPT_SMI:
4134 if (unlikely(!mdev->port_caps[qp->port - 1].has_smi)) {
4135 mlx5_ib_warn(dev, "Send SMP MADs is not allowed\n");
4136 err = -EPERM;
4137 *bad_wr = wr;
4138 goto out;
4139 }
4140 /* fall through */
4141 case MLX5_IB_QPT_HW_GSI:
4142 set_datagram_seg(seg, wr);
4143 seg += sizeof(struct mlx5_wqe_datagram_seg);
4144 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4145 if (unlikely((seg == qend)))
4146 seg = mlx5_get_send_wqe(qp, 0);
4147 break;
4148 case IB_QPT_UD:
4149 set_datagram_seg(seg, wr);
4150 seg += sizeof(struct mlx5_wqe_datagram_seg);
4151 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4152
4153 if (unlikely((seg == qend)))
4154 seg = mlx5_get_send_wqe(qp, 0);
4155
4156 /* handle qp that supports ud offload */
4157 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4158 struct mlx5_wqe_eth_pad *pad;
4159
4160 pad = seg;
4161 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4162 seg += sizeof(struct mlx5_wqe_eth_pad);
4163 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4164
4165 seg = set_eth_seg(seg, wr, qend, qp, &size);
4166
4167 if (unlikely((seg == qend)))
4168 seg = mlx5_get_send_wqe(qp, 0);
4169 }
4170 break;
4171 case MLX5_IB_QPT_REG_UMR:
4172 if (wr->opcode != MLX5_IB_WR_UMR) {
4173 err = -EINVAL;
4174 mlx5_ib_warn(dev, "bad opcode\n");
4175 goto out;
4176 }
4177 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4178 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4179 set_reg_umr_segment(seg, wr, !!(MLX5_CAP_GEN(mdev, atomic)));
4180 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4181 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4182 if (unlikely((seg == qend)))
4183 seg = mlx5_get_send_wqe(qp, 0);
4184 set_reg_mkey_segment(seg, wr);
4185 seg += sizeof(struct mlx5_mkey_seg);
4186 size += sizeof(struct mlx5_mkey_seg) / 16;
4187 if (unlikely((seg == qend)))
4188 seg = mlx5_get_send_wqe(qp, 0);
4189 break;
4190
4191 default:
4192 break;
4193 }
4194
4195 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4196 int uninitialized_var(sz);
4197
4198 err = set_data_inl_seg(qp, wr, seg, &sz);
4199 if (unlikely(err)) {
4200 mlx5_ib_warn(dev, "\n");
4201 *bad_wr = wr;
4202 goto out;
4203 }
4204 size += sz;
4205 } else {
4206 dpseg = seg;
4207 for (i = 0; i < num_sge; i++) {
4208 if (unlikely(dpseg == qend)) {
4209 seg = mlx5_get_send_wqe(qp, 0);
4210 dpseg = seg;
4211 }
4212 if (likely(wr->sg_list[i].length)) {
4213 set_data_ptr_seg(dpseg, wr->sg_list + i);
4214 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4215 dpseg++;
4216 }
4217 }
4218 }
4219
4220 qp->next_fence = next_fence;
4221 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq, fence,
4222 mlx5_ib_opcode[wr->opcode]);
4223 skip_psv:
4224 if (0)
4225 dump_wqe(qp, idx, size);
4226 }
4227
4228 out:
4229 if (likely(nreq)) {
4230 qp->sq.head += nreq;
4231
4232 /* Make sure that descriptors are written before
4233 * updating doorbell record and ringing the doorbell
4234 */
4235 wmb();
4236
4237 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4238
4239 /* Make sure doorbell record is visible to the HCA before
4240 * we hit doorbell */
4241 wmb();
4242
4243 /* currently we support only regular doorbells */
4244 mlx5_write64((__be32 *)ctrl, bf->bfreg->map + bf->offset, NULL);
4245 /* Make sure doorbells don't leak out of SQ spinlock
4246 * and reach the HCA out of order.
4247 */
4248 mmiowb();
4249 bf->offset ^= bf->buf_size;
4250 }
4251
4252 spin_unlock_irqrestore(&qp->sq.lock, flags);
4253
4254 return err;
4255 }
4256
4257 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4258 {
4259 sig->signature = calc_sig(sig, size);
4260 }
4261
4262 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4263 struct ib_recv_wr **bad_wr)
4264 {
4265 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4266 struct mlx5_wqe_data_seg *scat;
4267 struct mlx5_rwqe_sig *sig;
4268 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4269 struct mlx5_core_dev *mdev = dev->mdev;
4270 unsigned long flags;
4271 int err = 0;
4272 int nreq;
4273 int ind;
4274 int i;
4275
4276 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4277 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4278
4279 spin_lock_irqsave(&qp->rq.lock, flags);
4280
4281 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4282 err = -EIO;
4283 *bad_wr = wr;
4284 nreq = 0;
4285 goto out;
4286 }
4287
4288 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4289
4290 for (nreq = 0; wr; nreq++, wr = wr->next) {
4291 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4292 err = -ENOMEM;
4293 *bad_wr = wr;
4294 goto out;
4295 }
4296
4297 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4298 err = -EINVAL;
4299 *bad_wr = wr;
4300 goto out;
4301 }
4302
4303 scat = get_recv_wqe(qp, ind);
4304 if (qp->wq_sig)
4305 scat++;
4306
4307 for (i = 0; i < wr->num_sge; i++)
4308 set_data_ptr_seg(scat + i, wr->sg_list + i);
4309
4310 if (i < qp->rq.max_gs) {
4311 scat[i].byte_count = 0;
4312 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4313 scat[i].addr = 0;
4314 }
4315
4316 if (qp->wq_sig) {
4317 sig = (struct mlx5_rwqe_sig *)scat;
4318 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4319 }
4320
4321 qp->rq.wrid[ind] = wr->wr_id;
4322
4323 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4324 }
4325
4326 out:
4327 if (likely(nreq)) {
4328 qp->rq.head += nreq;
4329
4330 /* Make sure that descriptors are written before
4331 * doorbell record.
4332 */
4333 wmb();
4334
4335 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4336 }
4337
4338 spin_unlock_irqrestore(&qp->rq.lock, flags);
4339
4340 return err;
4341 }
4342
4343 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4344 {
4345 switch (mlx5_state) {
4346 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4347 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4348 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4349 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4350 case MLX5_QP_STATE_SQ_DRAINING:
4351 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4352 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4353 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4354 default: return -1;
4355 }
4356 }
4357
4358 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4359 {
4360 switch (mlx5_mig_state) {
4361 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4362 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4363 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4364 default: return -1;
4365 }
4366 }
4367
4368 static int to_ib_qp_access_flags(int mlx5_flags)
4369 {
4370 int ib_flags = 0;
4371
4372 if (mlx5_flags & MLX5_QP_BIT_RRE)
4373 ib_flags |= IB_ACCESS_REMOTE_READ;
4374 if (mlx5_flags & MLX5_QP_BIT_RWE)
4375 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4376 if (mlx5_flags & MLX5_QP_BIT_RAE)
4377 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4378
4379 return ib_flags;
4380 }
4381
4382 static void to_rdma_ah_attr(struct mlx5_ib_dev *ibdev,
4383 struct rdma_ah_attr *ah_attr,
4384 struct mlx5_qp_path *path)
4385 {
4386 struct mlx5_core_dev *dev = ibdev->mdev;
4387
4388 memset(ah_attr, 0, sizeof(*ah_attr));
4389
4390 if (!path->port || path->port > MLX5_CAP_GEN(dev, num_ports))
4391 return;
4392
4393 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, path->port);
4394
4395 rdma_ah_set_port_num(ah_attr, path->port);
4396 rdma_ah_set_sl(ah_attr, path->dci_cfi_prio_sl & 0xf);
4397
4398 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
4399 rdma_ah_set_path_bits(ah_attr, path->grh_mlid & 0x7f);
4400 rdma_ah_set_static_rate(ah_attr,
4401 path->static_rate ? path->static_rate - 5 : 0);
4402 if (path->grh_mlid & (1 << 7)) {
4403 u32 tc_fl = be32_to_cpu(path->tclass_flowlabel);
4404
4405 rdma_ah_set_grh(ah_attr, NULL,
4406 tc_fl & 0xfffff,
4407 path->mgid_index,
4408 path->hop_limit,
4409 (tc_fl >> 20) & 0xff);
4410 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
4411 }
4412 }
4413
4414 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4415 struct mlx5_ib_sq *sq,
4416 u8 *sq_state)
4417 {
4418 void *out;
4419 void *sqc;
4420 int inlen;
4421 int err;
4422
4423 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4424 out = kvzalloc(inlen, GFP_KERNEL);
4425 if (!out)
4426 return -ENOMEM;
4427
4428 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4429 if (err)
4430 goto out;
4431
4432 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4433 *sq_state = MLX5_GET(sqc, sqc, state);
4434 sq->state = *sq_state;
4435
4436 out:
4437 kvfree(out);
4438 return err;
4439 }
4440
4441 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4442 struct mlx5_ib_rq *rq,
4443 u8 *rq_state)
4444 {
4445 void *out;
4446 void *rqc;
4447 int inlen;
4448 int err;
4449
4450 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4451 out = kvzalloc(inlen, GFP_KERNEL);
4452 if (!out)
4453 return -ENOMEM;
4454
4455 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4456 if (err)
4457 goto out;
4458
4459 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4460 *rq_state = MLX5_GET(rqc, rqc, state);
4461 rq->state = *rq_state;
4462
4463 out:
4464 kvfree(out);
4465 return err;
4466 }
4467
4468 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4469 struct mlx5_ib_qp *qp, u8 *qp_state)
4470 {
4471 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4472 [MLX5_RQC_STATE_RST] = {
4473 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4474 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4475 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4476 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4477 },
4478 [MLX5_RQC_STATE_RDY] = {
4479 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4480 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4481 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4482 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4483 },
4484 [MLX5_RQC_STATE_ERR] = {
4485 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4486 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4487 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4488 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4489 },
4490 [MLX5_RQ_STATE_NA] = {
4491 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4492 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4493 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4494 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4495 },
4496 };
4497
4498 *qp_state = sqrq_trans[rq_state][sq_state];
4499
4500 if (*qp_state == MLX5_QP_STATE_BAD) {
4501 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4502 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4503 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4504 return -EINVAL;
4505 }
4506
4507 if (*qp_state == MLX5_QP_STATE)
4508 *qp_state = qp->state;
4509
4510 return 0;
4511 }
4512
4513 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4514 struct mlx5_ib_qp *qp,
4515 u8 *raw_packet_qp_state)
4516 {
4517 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4518 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4519 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4520 int err;
4521 u8 sq_state = MLX5_SQ_STATE_NA;
4522 u8 rq_state = MLX5_RQ_STATE_NA;
4523
4524 if (qp->sq.wqe_cnt) {
4525 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4526 if (err)
4527 return err;
4528 }
4529
4530 if (qp->rq.wqe_cnt) {
4531 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4532 if (err)
4533 return err;
4534 }
4535
4536 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4537 raw_packet_qp_state);
4538 }
4539
4540 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4541 struct ib_qp_attr *qp_attr)
4542 {
4543 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4544 struct mlx5_qp_context *context;
4545 int mlx5_state;
4546 u32 *outb;
4547 int err = 0;
4548
4549 outb = kzalloc(outlen, GFP_KERNEL);
4550 if (!outb)
4551 return -ENOMEM;
4552
4553 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4554 outlen);
4555 if (err)
4556 goto out;
4557
4558 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4559 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4560
4561 mlx5_state = be32_to_cpu(context->flags) >> 28;
4562
4563 qp->state = to_ib_qp_state(mlx5_state);
4564 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4565 qp_attr->path_mig_state =
4566 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4567 qp_attr->qkey = be32_to_cpu(context->qkey);
4568 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4569 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4570 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4571 qp_attr->qp_access_flags =
4572 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4573
4574 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4575 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4576 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4577 qp_attr->alt_pkey_index =
4578 be16_to_cpu(context->alt_path.pkey_index);
4579 qp_attr->alt_port_num =
4580 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
4581 }
4582
4583 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4584 qp_attr->port_num = context->pri_path.port;
4585
4586 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4587 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4588
4589 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4590
4591 qp_attr->max_dest_rd_atomic =
4592 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4593 qp_attr->min_rnr_timer =
4594 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4595 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4596 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4597 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4598 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4599
4600 out:
4601 kfree(outb);
4602 return err;
4603 }
4604
4605 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4606 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4607 {
4608 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4609 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4610 int err = 0;
4611 u8 raw_packet_qp_state;
4612
4613 if (ibqp->rwq_ind_tbl)
4614 return -ENOSYS;
4615
4616 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4617 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4618 qp_init_attr);
4619
4620 /* Not all of output fields are applicable, make sure to zero them */
4621 memset(qp_init_attr, 0, sizeof(*qp_init_attr));
4622 memset(qp_attr, 0, sizeof(*qp_attr));
4623
4624 mutex_lock(&qp->mutex);
4625
4626 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET ||
4627 qp->flags & MLX5_IB_QP_UNDERLAY) {
4628 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4629 if (err)
4630 goto out;
4631 qp->state = raw_packet_qp_state;
4632 qp_attr->port_num = 1;
4633 } else {
4634 err = query_qp_attr(dev, qp, qp_attr);
4635 if (err)
4636 goto out;
4637 }
4638
4639 qp_attr->qp_state = qp->state;
4640 qp_attr->cur_qp_state = qp_attr->qp_state;
4641 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4642 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4643
4644 if (!ibqp->uobject) {
4645 qp_attr->cap.max_send_wr = qp->sq.max_post;
4646 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4647 qp_init_attr->qp_context = ibqp->qp_context;
4648 } else {
4649 qp_attr->cap.max_send_wr = 0;
4650 qp_attr->cap.max_send_sge = 0;
4651 }
4652
4653 qp_init_attr->qp_type = ibqp->qp_type;
4654 qp_init_attr->recv_cq = ibqp->recv_cq;
4655 qp_init_attr->send_cq = ibqp->send_cq;
4656 qp_init_attr->srq = ibqp->srq;
4657 qp_attr->cap.max_inline_data = qp->max_inline_data;
4658
4659 qp_init_attr->cap = qp_attr->cap;
4660
4661 qp_init_attr->create_flags = 0;
4662 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4663 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4664
4665 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4666 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4667 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4668 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4669 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4670 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4671 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4672 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4673
4674 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4675 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4676
4677 out:
4678 mutex_unlock(&qp->mutex);
4679 return err;
4680 }
4681
4682 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4683 struct ib_ucontext *context,
4684 struct ib_udata *udata)
4685 {
4686 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4687 struct mlx5_ib_xrcd *xrcd;
4688 int err;
4689
4690 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4691 return ERR_PTR(-ENOSYS);
4692
4693 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4694 if (!xrcd)
4695 return ERR_PTR(-ENOMEM);
4696
4697 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4698 if (err) {
4699 kfree(xrcd);
4700 return ERR_PTR(-ENOMEM);
4701 }
4702
4703 return &xrcd->ibxrcd;
4704 }
4705
4706 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4707 {
4708 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4709 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4710 int err;
4711
4712 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4713 if (err)
4714 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4715
4716 kfree(xrcd);
4717 return 0;
4718 }
4719
4720 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4721 {
4722 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4723 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4724 struct ib_event event;
4725
4726 if (rwq->ibwq.event_handler) {
4727 event.device = rwq->ibwq.device;
4728 event.element.wq = &rwq->ibwq;
4729 switch (type) {
4730 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4731 event.event = IB_EVENT_WQ_FATAL;
4732 break;
4733 default:
4734 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4735 return;
4736 }
4737
4738 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4739 }
4740 }
4741
4742 static int set_delay_drop(struct mlx5_ib_dev *dev)
4743 {
4744 int err = 0;
4745
4746 mutex_lock(&dev->delay_drop.lock);
4747 if (dev->delay_drop.activate)
4748 goto out;
4749
4750 err = mlx5_core_set_delay_drop(dev->mdev, dev->delay_drop.timeout);
4751 if (err)
4752 goto out;
4753
4754 dev->delay_drop.activate = true;
4755 out:
4756 mutex_unlock(&dev->delay_drop.lock);
4757
4758 if (!err)
4759 atomic_inc(&dev->delay_drop.rqs_cnt);
4760 return err;
4761 }
4762
4763 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4764 struct ib_wq_init_attr *init_attr)
4765 {
4766 struct mlx5_ib_dev *dev;
4767 int has_net_offloads;
4768 __be64 *rq_pas0;
4769 void *in;
4770 void *rqc;
4771 void *wq;
4772 int inlen;
4773 int err;
4774
4775 dev = to_mdev(pd->device);
4776
4777 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4778 in = kvzalloc(inlen, GFP_KERNEL);
4779 if (!in)
4780 return -ENOMEM;
4781
4782 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4783 MLX5_SET(rqc, rqc, mem_rq_type,
4784 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4785 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4786 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4787 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4788 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4789 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4790 MLX5_SET(wq, wq, wq_type,
4791 rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ ?
4792 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ : MLX5_WQ_TYPE_CYCLIC);
4793 if (init_attr->create_flags & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
4794 if (!MLX5_CAP_GEN(dev->mdev, end_pad)) {
4795 mlx5_ib_dbg(dev, "Scatter end padding is not supported\n");
4796 err = -EOPNOTSUPP;
4797 goto out;
4798 } else {
4799 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4800 }
4801 }
4802 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4803 if (rwq->create_flags & MLX5_IB_WQ_FLAGS_STRIDING_RQ) {
4804 MLX5_SET(wq, wq, two_byte_shift_en, rwq->two_byte_shift_en);
4805 MLX5_SET(wq, wq, log_wqe_stride_size,
4806 rwq->single_stride_log_num_of_bytes -
4807 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES);
4808 MLX5_SET(wq, wq, log_wqe_num_of_strides, rwq->log_num_strides -
4809 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES);
4810 }
4811 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4812 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4813 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4814 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4815 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4816 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4817 has_net_offloads = MLX5_CAP_GEN(dev->mdev, eth_net_offloads);
4818 if (init_attr->create_flags & IB_WQ_FLAGS_CVLAN_STRIPPING) {
4819 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
4820 mlx5_ib_dbg(dev, "VLAN offloads are not supported\n");
4821 err = -EOPNOTSUPP;
4822 goto out;
4823 }
4824 } else {
4825 MLX5_SET(rqc, rqc, vsd, 1);
4826 }
4827 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS) {
4828 if (!(has_net_offloads && MLX5_CAP_ETH(dev->mdev, scatter_fcs))) {
4829 mlx5_ib_dbg(dev, "Scatter FCS is not supported\n");
4830 err = -EOPNOTSUPP;
4831 goto out;
4832 }
4833 MLX5_SET(rqc, rqc, scatter_fcs, 1);
4834 }
4835 if (init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4836 if (!(dev->ib_dev.attrs.raw_packet_caps &
4837 IB_RAW_PACKET_CAP_DELAY_DROP)) {
4838 mlx5_ib_dbg(dev, "Delay drop is not supported\n");
4839 err = -EOPNOTSUPP;
4840 goto out;
4841 }
4842 MLX5_SET(rqc, rqc, delay_drop_en, 1);
4843 }
4844 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4845 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4846 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4847 if (!err && init_attr->create_flags & IB_WQ_FLAGS_DELAY_DROP) {
4848 err = set_delay_drop(dev);
4849 if (err) {
4850 mlx5_ib_warn(dev, "Failed to enable delay drop err=%d\n",
4851 err);
4852 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4853 } else {
4854 rwq->create_flags |= MLX5_IB_WQ_FLAGS_DELAY_DROP;
4855 }
4856 }
4857 out:
4858 kvfree(in);
4859 return err;
4860 }
4861
4862 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4863 struct ib_wq_init_attr *wq_init_attr,
4864 struct mlx5_ib_create_wq *ucmd,
4865 struct mlx5_ib_rwq *rwq)
4866 {
4867 /* Sanity check RQ size before proceeding */
4868 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4869 return -EINVAL;
4870
4871 if (!ucmd->rq_wqe_count)
4872 return -EINVAL;
4873
4874 rwq->wqe_count = ucmd->rq_wqe_count;
4875 rwq->wqe_shift = ucmd->rq_wqe_shift;
4876 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4877 rwq->log_rq_stride = rwq->wqe_shift;
4878 rwq->log_rq_size = ilog2(rwq->wqe_count);
4879 return 0;
4880 }
4881
4882 static int prepare_user_rq(struct ib_pd *pd,
4883 struct ib_wq_init_attr *init_attr,
4884 struct ib_udata *udata,
4885 struct mlx5_ib_rwq *rwq)
4886 {
4887 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4888 struct mlx5_ib_create_wq ucmd = {};
4889 int err;
4890 size_t required_cmd_sz;
4891
4892 required_cmd_sz = offsetof(typeof(ucmd), single_stride_log_num_of_bytes)
4893 + sizeof(ucmd.single_stride_log_num_of_bytes);
4894 if (udata->inlen < required_cmd_sz) {
4895 mlx5_ib_dbg(dev, "invalid inlen\n");
4896 return -EINVAL;
4897 }
4898
4899 if (udata->inlen > sizeof(ucmd) &&
4900 !ib_is_udata_cleared(udata, sizeof(ucmd),
4901 udata->inlen - sizeof(ucmd))) {
4902 mlx5_ib_dbg(dev, "inlen is not supported\n");
4903 return -EOPNOTSUPP;
4904 }
4905
4906 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4907 mlx5_ib_dbg(dev, "copy failed\n");
4908 return -EFAULT;
4909 }
4910
4911 if (ucmd.comp_mask & (~MLX5_IB_CREATE_WQ_STRIDING_RQ)) {
4912 mlx5_ib_dbg(dev, "invalid comp mask\n");
4913 return -EOPNOTSUPP;
4914 } else if (ucmd.comp_mask & MLX5_IB_CREATE_WQ_STRIDING_RQ) {
4915 if (!MLX5_CAP_GEN(dev->mdev, striding_rq)) {
4916 mlx5_ib_dbg(dev, "Striding RQ is not supported\n");
4917 return -EOPNOTSUPP;
4918 }
4919 if ((ucmd.single_stride_log_num_of_bytes <
4920 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES) ||
4921 (ucmd.single_stride_log_num_of_bytes >
4922 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES)) {
4923 mlx5_ib_dbg(dev, "Invalid log stride size (%u. Range is %u - %u)\n",
4924 ucmd.single_stride_log_num_of_bytes,
4925 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES,
4926 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES);
4927 return -EINVAL;
4928 }
4929 if ((ucmd.single_wqe_log_num_of_strides >
4930 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES) ||
4931 (ucmd.single_wqe_log_num_of_strides <
4932 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES)) {
4933 mlx5_ib_dbg(dev, "Invalid log num strides (%u. Range is %u - %u)\n",
4934 ucmd.single_wqe_log_num_of_strides,
4935 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES,
4936 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES);
4937 return -EINVAL;
4938 }
4939 rwq->single_stride_log_num_of_bytes =
4940 ucmd.single_stride_log_num_of_bytes;
4941 rwq->log_num_strides = ucmd.single_wqe_log_num_of_strides;
4942 rwq->two_byte_shift_en = !!ucmd.two_byte_shift_en;
4943 rwq->create_flags |= MLX5_IB_WQ_FLAGS_STRIDING_RQ;
4944 }
4945
4946 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4947 if (err) {
4948 mlx5_ib_dbg(dev, "err %d\n", err);
4949 return err;
4950 }
4951
4952 err = create_user_rq(dev, pd, rwq, &ucmd);
4953 if (err) {
4954 mlx5_ib_dbg(dev, "err %d\n", err);
4955 if (err)
4956 return err;
4957 }
4958
4959 rwq->user_index = ucmd.user_index;
4960 return 0;
4961 }
4962
4963 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4964 struct ib_wq_init_attr *init_attr,
4965 struct ib_udata *udata)
4966 {
4967 struct mlx5_ib_dev *dev;
4968 struct mlx5_ib_rwq *rwq;
4969 struct mlx5_ib_create_wq_resp resp = {};
4970 size_t min_resp_len;
4971 int err;
4972
4973 if (!udata)
4974 return ERR_PTR(-ENOSYS);
4975
4976 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4977 if (udata->outlen && udata->outlen < min_resp_len)
4978 return ERR_PTR(-EINVAL);
4979
4980 dev = to_mdev(pd->device);
4981 switch (init_attr->wq_type) {
4982 case IB_WQT_RQ:
4983 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4984 if (!rwq)
4985 return ERR_PTR(-ENOMEM);
4986 err = prepare_user_rq(pd, init_attr, udata, rwq);
4987 if (err)
4988 goto err;
4989 err = create_rq(rwq, pd, init_attr);
4990 if (err)
4991 goto err_user_rq;
4992 break;
4993 default:
4994 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4995 init_attr->wq_type);
4996 return ERR_PTR(-EINVAL);
4997 }
4998
4999 rwq->ibwq.wq_num = rwq->core_qp.qpn;
5000 rwq->ibwq.state = IB_WQS_RESET;
5001 if (udata->outlen) {
5002 resp.response_length = offsetof(typeof(resp), response_length) +
5003 sizeof(resp.response_length);
5004 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5005 if (err)
5006 goto err_copy;
5007 }
5008
5009 rwq->core_qp.event = mlx5_ib_wq_event;
5010 rwq->ibwq.event_handler = init_attr->event_handler;
5011 return &rwq->ibwq;
5012
5013 err_copy:
5014 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5015 err_user_rq:
5016 destroy_user_rq(dev, pd, rwq);
5017 err:
5018 kfree(rwq);
5019 return ERR_PTR(err);
5020 }
5021
5022 int mlx5_ib_destroy_wq(struct ib_wq *wq)
5023 {
5024 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5025 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5026
5027 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
5028 destroy_user_rq(dev, wq->pd, rwq);
5029 kfree(rwq);
5030
5031 return 0;
5032 }
5033
5034 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
5035 struct ib_rwq_ind_table_init_attr *init_attr,
5036 struct ib_udata *udata)
5037 {
5038 struct mlx5_ib_dev *dev = to_mdev(device);
5039 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
5040 int sz = 1 << init_attr->log_ind_tbl_size;
5041 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
5042 size_t min_resp_len;
5043 int inlen;
5044 int err;
5045 int i;
5046 u32 *in;
5047 void *rqtc;
5048
5049 if (udata->inlen > 0 &&
5050 !ib_is_udata_cleared(udata, 0,
5051 udata->inlen))
5052 return ERR_PTR(-EOPNOTSUPP);
5053
5054 if (init_attr->log_ind_tbl_size >
5055 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
5056 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5057 init_attr->log_ind_tbl_size,
5058 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
5059 return ERR_PTR(-EINVAL);
5060 }
5061
5062 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
5063 if (udata->outlen && udata->outlen < min_resp_len)
5064 return ERR_PTR(-EINVAL);
5065
5066 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
5067 if (!rwq_ind_tbl)
5068 return ERR_PTR(-ENOMEM);
5069
5070 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
5071 in = kvzalloc(inlen, GFP_KERNEL);
5072 if (!in) {
5073 err = -ENOMEM;
5074 goto err;
5075 }
5076
5077 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
5078
5079 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
5080 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
5081
5082 for (i = 0; i < sz; i++)
5083 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
5084
5085 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
5086 kvfree(in);
5087
5088 if (err)
5089 goto err;
5090
5091 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
5092 if (udata->outlen) {
5093 resp.response_length = offsetof(typeof(resp), response_length) +
5094 sizeof(resp.response_length);
5095 err = ib_copy_to_udata(udata, &resp, resp.response_length);
5096 if (err)
5097 goto err_copy;
5098 }
5099
5100 return &rwq_ind_tbl->ib_rwq_ind_tbl;
5101
5102 err_copy:
5103 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5104 err:
5105 kfree(rwq_ind_tbl);
5106 return ERR_PTR(err);
5107 }
5108
5109 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
5110 {
5111 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
5112 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
5113
5114 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
5115
5116 kfree(rwq_ind_tbl);
5117 return 0;
5118 }
5119
5120 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
5121 u32 wq_attr_mask, struct ib_udata *udata)
5122 {
5123 struct mlx5_ib_dev *dev = to_mdev(wq->device);
5124 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
5125 struct mlx5_ib_modify_wq ucmd = {};
5126 size_t required_cmd_sz;
5127 int curr_wq_state;
5128 int wq_state;
5129 int inlen;
5130 int err;
5131 void *rqc;
5132 void *in;
5133
5134 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
5135 if (udata->inlen < required_cmd_sz)
5136 return -EINVAL;
5137
5138 if (udata->inlen > sizeof(ucmd) &&
5139 !ib_is_udata_cleared(udata, sizeof(ucmd),
5140 udata->inlen - sizeof(ucmd)))
5141 return -EOPNOTSUPP;
5142
5143 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
5144 return -EFAULT;
5145
5146 if (ucmd.comp_mask || ucmd.reserved)
5147 return -EOPNOTSUPP;
5148
5149 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
5150 in = kvzalloc(inlen, GFP_KERNEL);
5151 if (!in)
5152 return -ENOMEM;
5153
5154 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
5155
5156 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
5157 wq_attr->curr_wq_state : wq->state;
5158 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
5159 wq_attr->wq_state : curr_wq_state;
5160 if (curr_wq_state == IB_WQS_ERR)
5161 curr_wq_state = MLX5_RQC_STATE_ERR;
5162 if (wq_state == IB_WQS_ERR)
5163 wq_state = MLX5_RQC_STATE_ERR;
5164 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
5165 MLX5_SET(rqc, rqc, state, wq_state);
5166
5167 if (wq_attr_mask & IB_WQ_FLAGS) {
5168 if (wq_attr->flags_mask & IB_WQ_FLAGS_CVLAN_STRIPPING) {
5169 if (!(MLX5_CAP_GEN(dev->mdev, eth_net_offloads) &&
5170 MLX5_CAP_ETH(dev->mdev, vlan_cap))) {
5171 mlx5_ib_dbg(dev, "VLAN offloads are not "
5172 "supported\n");
5173 err = -EOPNOTSUPP;
5174 goto out;
5175 }
5176 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5177 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
5178 MLX5_SET(rqc, rqc, vsd,
5179 (wq_attr->flags & IB_WQ_FLAGS_CVLAN_STRIPPING) ? 0 : 1);
5180 }
5181
5182 if (wq_attr->flags_mask & IB_WQ_FLAGS_PCI_WRITE_END_PADDING) {
5183 mlx5_ib_dbg(dev, "Modifying scatter end padding is not supported\n");
5184 err = -EOPNOTSUPP;
5185 goto out;
5186 }
5187 }
5188
5189 if (curr_wq_state == IB_WQS_RESET && wq_state == IB_WQS_RDY) {
5190 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
5191 MLX5_SET64(modify_rq_in, in, modify_bitmask,
5192 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID);
5193 MLX5_SET(rqc, rqc, counter_set_id,
5194 dev->port->cnts.set_id);
5195 } else
5196 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5197 dev->ib_dev.name);
5198 }
5199
5200 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
5201 if (!err)
5202 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
5203
5204 out:
5205 kvfree(in);
5206 return err;
5207 }
ubuntu-bionic-kernel mirror