2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/mlx5/fs.h>
41 /* not supported currently */
42 static int wq_signature
;
45 MLX5_IB_ACK_REQ_FREQ
= 8,
49 MLX5_IB_DEFAULT_SCHED_QUEUE
= 0x83,
50 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE
= 0x3f,
51 MLX5_IB_LINK_TYPE_IB
= 0,
52 MLX5_IB_LINK_TYPE_ETH
= 1
56 MLX5_IB_SQ_STRIDE
= 6,
59 static const u32 mlx5_ib_opcode
[] = {
60 [IB_WR_SEND
] = MLX5_OPCODE_SEND
,
61 [IB_WR_LSO
] = MLX5_OPCODE_LSO
,
62 [IB_WR_SEND_WITH_IMM
] = MLX5_OPCODE_SEND_IMM
,
63 [IB_WR_RDMA_WRITE
] = MLX5_OPCODE_RDMA_WRITE
,
64 [IB_WR_RDMA_WRITE_WITH_IMM
] = MLX5_OPCODE_RDMA_WRITE_IMM
,
65 [IB_WR_RDMA_READ
] = MLX5_OPCODE_RDMA_READ
,
66 [IB_WR_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_CS
,
67 [IB_WR_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_FA
,
68 [IB_WR_SEND_WITH_INV
] = MLX5_OPCODE_SEND_INVAL
,
69 [IB_WR_LOCAL_INV
] = MLX5_OPCODE_UMR
,
70 [IB_WR_REG_MR
] = MLX5_OPCODE_UMR
,
71 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP
] = MLX5_OPCODE_ATOMIC_MASKED_CS
,
72 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD
] = MLX5_OPCODE_ATOMIC_MASKED_FA
,
73 [MLX5_IB_WR_UMR
] = MLX5_OPCODE_UMR
,
76 struct mlx5_wqe_eth_pad
{
80 enum raw_qp_set_mask_map
{
81 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID
= 1UL << 0,
82 MLX5_RAW_QP_RATE_LIMIT
= 1UL << 1,
85 struct mlx5_modify_raw_qp_param
{
88 u32 set_mask
; /* raw_qp_set_mask_map */
90 struct mlx5_rate_limit rl
;
95 static void get_cqs(enum ib_qp_type qp_type
,
96 struct ib_cq
*ib_send_cq
, struct ib_cq
*ib_recv_cq
,
97 struct mlx5_ib_cq
**send_cq
, struct mlx5_ib_cq
**recv_cq
);
99 static int is_qp0(enum ib_qp_type qp_type
)
101 return qp_type
== IB_QPT_SMI
;
104 static int is_sqp(enum ib_qp_type qp_type
)
106 return is_qp0(qp_type
) || is_qp1(qp_type
);
109 static void *get_wqe(struct mlx5_ib_qp
*qp
, int offset
)
111 return mlx5_buf_offset(&qp
->buf
, offset
);
114 static void *get_recv_wqe(struct mlx5_ib_qp
*qp
, int n
)
116 return get_wqe(qp
, qp
->rq
.offset
+ (n
<< qp
->rq
.wqe_shift
));
119 void *mlx5_get_send_wqe(struct mlx5_ib_qp
*qp
, int n
)
121 return get_wqe(qp
, qp
->sq
.offset
+ (n
<< MLX5_IB_SQ_STRIDE
));
125 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
127 * @qp: QP to copy from.
128 * @send: copy from the send queue when non-zero, use the receive queue
130 * @wqe_index: index to start copying from. For send work queues, the
131 * wqe_index is in units of MLX5_SEND_WQE_BB.
132 * For receive work queue, it is the number of work queue
133 * element in the queue.
134 * @buffer: destination buffer.
135 * @length: maximum number of bytes to copy.
137 * Copies at least a single WQE, but may copy more data.
139 * Return: the number of bytes copied, or an error code.
141 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp
*qp
, int send
, int wqe_index
,
142 void *buffer
, u32 length
,
143 struct mlx5_ib_qp_base
*base
)
145 struct ib_device
*ibdev
= qp
->ibqp
.device
;
146 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
147 struct mlx5_ib_wq
*wq
= send
? &qp
->sq
: &qp
->rq
;
150 struct ib_umem
*umem
= base
->ubuffer
.umem
;
151 u32 first_copy_length
;
155 if (wq
->wqe_cnt
== 0) {
156 mlx5_ib_dbg(dev
, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
161 offset
= wq
->offset
+ ((wqe_index
% wq
->wqe_cnt
) << wq
->wqe_shift
);
162 wq_end
= wq
->offset
+ (wq
->wqe_cnt
<< wq
->wqe_shift
);
164 if (send
&& length
< sizeof(struct mlx5_wqe_ctrl_seg
))
167 if (offset
> umem
->length
||
168 (send
&& offset
+ sizeof(struct mlx5_wqe_ctrl_seg
) > umem
->length
))
171 first_copy_length
= min_t(u32
, offset
+ length
, wq_end
) - offset
;
172 ret
= ib_umem_copy_from(buffer
, umem
, offset
, first_copy_length
);
177 struct mlx5_wqe_ctrl_seg
*ctrl
= buffer
;
178 int ds
= be32_to_cpu(ctrl
->qpn_ds
) & MLX5_WQE_CTRL_DS_MASK
;
180 wqe_length
= ds
* MLX5_WQE_DS_UNITS
;
182 wqe_length
= 1 << wq
->wqe_shift
;
185 if (wqe_length
<= first_copy_length
)
186 return first_copy_length
;
188 ret
= ib_umem_copy_from(buffer
+ first_copy_length
, umem
, wq
->offset
,
189 wqe_length
- first_copy_length
);
196 static void mlx5_ib_qp_event(struct mlx5_core_qp
*qp
, int type
)
198 struct ib_qp
*ibqp
= &to_mibqp(qp
)->ibqp
;
199 struct ib_event event
;
201 if (type
== MLX5_EVENT_TYPE_PATH_MIG
) {
202 /* This event is only valid for trans_qps */
203 to_mibqp(qp
)->port
= to_mibqp(qp
)->trans_qp
.alt_port
;
206 if (ibqp
->event_handler
) {
207 event
.device
= ibqp
->device
;
208 event
.element
.qp
= ibqp
;
210 case MLX5_EVENT_TYPE_PATH_MIG
:
211 event
.event
= IB_EVENT_PATH_MIG
;
213 case MLX5_EVENT_TYPE_COMM_EST
:
214 event
.event
= IB_EVENT_COMM_EST
;
216 case MLX5_EVENT_TYPE_SQ_DRAINED
:
217 event
.event
= IB_EVENT_SQ_DRAINED
;
219 case MLX5_EVENT_TYPE_SRQ_LAST_WQE
:
220 event
.event
= IB_EVENT_QP_LAST_WQE_REACHED
;
222 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR
:
223 event
.event
= IB_EVENT_QP_FATAL
;
225 case MLX5_EVENT_TYPE_PATH_MIG_FAILED
:
226 event
.event
= IB_EVENT_PATH_MIG_ERR
;
228 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR
:
229 event
.event
= IB_EVENT_QP_REQ_ERR
;
231 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR
:
232 event
.event
= IB_EVENT_QP_ACCESS_ERR
;
235 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type
, qp
->qpn
);
239 ibqp
->event_handler(&event
, ibqp
->qp_context
);
243 static int set_rq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_cap
*cap
,
244 int has_rq
, struct mlx5_ib_qp
*qp
, struct mlx5_ib_create_qp
*ucmd
)
249 /* Sanity check RQ size before proceeding */
250 if (cap
->max_recv_wr
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
)))
256 qp
->rq
.wqe_shift
= 0;
257 cap
->max_recv_wr
= 0;
258 cap
->max_recv_sge
= 0;
261 qp
->rq
.wqe_cnt
= ucmd
->rq_wqe_count
;
262 qp
->rq
.wqe_shift
= ucmd
->rq_wqe_shift
;
263 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
264 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
266 wqe_size
= qp
->wq_sig
? sizeof(struct mlx5_wqe_signature_seg
) : 0;
267 wqe_size
+= cap
->max_recv_sge
* sizeof(struct mlx5_wqe_data_seg
);
268 wqe_size
= roundup_pow_of_two(wqe_size
);
269 wq_size
= roundup_pow_of_two(cap
->max_recv_wr
) * wqe_size
;
270 wq_size
= max_t(int, wq_size
, MLX5_SEND_WQE_BB
);
271 qp
->rq
.wqe_cnt
= wq_size
/ wqe_size
;
272 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_rq
)) {
273 mlx5_ib_dbg(dev
, "wqe_size %d, max %d\n",
275 MLX5_CAP_GEN(dev
->mdev
,
279 qp
->rq
.wqe_shift
= ilog2(wqe_size
);
280 qp
->rq
.max_gs
= (1 << qp
->rq
.wqe_shift
) / sizeof(struct mlx5_wqe_data_seg
) - qp
->wq_sig
;
281 qp
->rq
.max_post
= qp
->rq
.wqe_cnt
;
288 static int sq_overhead(struct ib_qp_init_attr
*attr
)
292 switch (attr
->qp_type
) {
294 size
+= sizeof(struct mlx5_wqe_xrc_seg
);
297 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
298 max(sizeof(struct mlx5_wqe_atomic_seg
) +
299 sizeof(struct mlx5_wqe_raddr_seg
),
300 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
301 sizeof(struct mlx5_mkey_seg
));
308 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
309 max(sizeof(struct mlx5_wqe_raddr_seg
),
310 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
311 sizeof(struct mlx5_mkey_seg
));
315 if (attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)
316 size
+= sizeof(struct mlx5_wqe_eth_pad
) +
317 sizeof(struct mlx5_wqe_eth_seg
);
320 case MLX5_IB_QPT_HW_GSI
:
321 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
322 sizeof(struct mlx5_wqe_datagram_seg
);
325 case MLX5_IB_QPT_REG_UMR
:
326 size
+= sizeof(struct mlx5_wqe_ctrl_seg
) +
327 sizeof(struct mlx5_wqe_umr_ctrl_seg
) +
328 sizeof(struct mlx5_mkey_seg
);
338 static int calc_send_wqe(struct ib_qp_init_attr
*attr
)
343 size
= sq_overhead(attr
);
347 if (attr
->cap
.max_inline_data
) {
348 inl_size
= size
+ sizeof(struct mlx5_wqe_inline_seg
) +
349 attr
->cap
.max_inline_data
;
352 size
+= attr
->cap
.max_send_sge
* sizeof(struct mlx5_wqe_data_seg
);
353 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
&&
354 ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
) < MLX5_SIG_WQE_SIZE
)
355 return MLX5_SIG_WQE_SIZE
;
357 return ALIGN(max_t(int, inl_size
, size
), MLX5_SEND_WQE_BB
);
360 static int get_send_sge(struct ib_qp_init_attr
*attr
, int wqe_size
)
364 if (attr
->qp_type
== IB_QPT_RC
)
365 max_sge
= (min_t(int, wqe_size
, 512) -
366 sizeof(struct mlx5_wqe_ctrl_seg
) -
367 sizeof(struct mlx5_wqe_raddr_seg
)) /
368 sizeof(struct mlx5_wqe_data_seg
);
369 else if (attr
->qp_type
== IB_QPT_XRC_INI
)
370 max_sge
= (min_t(int, wqe_size
, 512) -
371 sizeof(struct mlx5_wqe_ctrl_seg
) -
372 sizeof(struct mlx5_wqe_xrc_seg
) -
373 sizeof(struct mlx5_wqe_raddr_seg
)) /
374 sizeof(struct mlx5_wqe_data_seg
);
376 max_sge
= (wqe_size
- sq_overhead(attr
)) /
377 sizeof(struct mlx5_wqe_data_seg
);
379 return min_t(int, max_sge
, wqe_size
- sq_overhead(attr
) /
380 sizeof(struct mlx5_wqe_data_seg
));
383 static int calc_sq_size(struct mlx5_ib_dev
*dev
, struct ib_qp_init_attr
*attr
,
384 struct mlx5_ib_qp
*qp
)
389 if (!attr
->cap
.max_send_wr
)
392 wqe_size
= calc_send_wqe(attr
);
393 mlx5_ib_dbg(dev
, "wqe_size %d\n", wqe_size
);
397 if (wqe_size
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
398 mlx5_ib_dbg(dev
, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
399 wqe_size
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
403 qp
->max_inline_data
= wqe_size
- sq_overhead(attr
) -
404 sizeof(struct mlx5_wqe_inline_seg
);
405 attr
->cap
.max_inline_data
= qp
->max_inline_data
;
407 if (attr
->create_flags
& IB_QP_CREATE_SIGNATURE_EN
)
408 qp
->signature_en
= true;
410 wq_size
= roundup_pow_of_two(attr
->cap
.max_send_wr
* wqe_size
);
411 qp
->sq
.wqe_cnt
= wq_size
/ MLX5_SEND_WQE_BB
;
412 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
413 mlx5_ib_dbg(dev
, "send queue size (%d * %d / %d -> %d) exceeds limits(%d)\n",
414 attr
->cap
.max_send_wr
, wqe_size
, MLX5_SEND_WQE_BB
,
416 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
419 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
420 qp
->sq
.max_gs
= get_send_sge(attr
, wqe_size
);
421 if (qp
->sq
.max_gs
< attr
->cap
.max_send_sge
)
424 attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
425 qp
->sq
.max_post
= wq_size
/ wqe_size
;
426 attr
->cap
.max_send_wr
= qp
->sq
.max_post
;
431 static int set_user_buf_size(struct mlx5_ib_dev
*dev
,
432 struct mlx5_ib_qp
*qp
,
433 struct mlx5_ib_create_qp
*ucmd
,
434 struct mlx5_ib_qp_base
*base
,
435 struct ib_qp_init_attr
*attr
)
437 int desc_sz
= 1 << qp
->sq
.wqe_shift
;
439 if (desc_sz
> MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
)) {
440 mlx5_ib_warn(dev
, "desc_sz %d, max_sq_desc_sz %d\n",
441 desc_sz
, MLX5_CAP_GEN(dev
->mdev
, max_wqe_sz_sq
));
445 if (ucmd
->sq_wqe_count
&& ((1 << ilog2(ucmd
->sq_wqe_count
)) != ucmd
->sq_wqe_count
)) {
446 mlx5_ib_warn(dev
, "sq_wqe_count %d, sq_wqe_count %d\n",
447 ucmd
->sq_wqe_count
, ucmd
->sq_wqe_count
);
451 qp
->sq
.wqe_cnt
= ucmd
->sq_wqe_count
;
453 if (qp
->sq
.wqe_cnt
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
))) {
454 mlx5_ib_warn(dev
, "wqe_cnt %d, max_wqes %d\n",
456 1 << MLX5_CAP_GEN(dev
->mdev
, log_max_qp_sz
));
460 if (attr
->qp_type
== IB_QPT_RAW_PACKET
||
461 qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
462 base
->ubuffer
.buf_size
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
463 qp
->raw_packet_qp
.sq
.ubuffer
.buf_size
= qp
->sq
.wqe_cnt
<< 6;
465 base
->ubuffer
.buf_size
= (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
) +
466 (qp
->sq
.wqe_cnt
<< 6);
472 static int qp_has_rq(struct ib_qp_init_attr
*attr
)
474 if (attr
->qp_type
== IB_QPT_XRC_INI
||
475 attr
->qp_type
== IB_QPT_XRC_TGT
|| attr
->srq
||
476 attr
->qp_type
== MLX5_IB_QPT_REG_UMR
||
477 !attr
->cap
.max_recv_wr
)
483 static int first_med_bfreg(void)
489 /* this is the first blue flame register in the array of bfregs assigned
490 * to a processes. Since we do not use it for blue flame but rather
491 * regular 64 bit doorbells, we do not need a lock for maintaiing
494 NUM_NON_BLUE_FLAME_BFREGS
= 1,
497 static int max_bfregs(struct mlx5_ib_dev
*dev
, struct mlx5_bfreg_info
*bfregi
)
499 return get_num_static_uars(dev
, bfregi
) * MLX5_NON_FP_BFREGS_PER_UAR
;
502 static int num_med_bfreg(struct mlx5_ib_dev
*dev
,
503 struct mlx5_bfreg_info
*bfregi
)
507 n
= max_bfregs(dev
, bfregi
) - bfregi
->num_low_latency_bfregs
-
508 NUM_NON_BLUE_FLAME_BFREGS
;
510 return n
>= 0 ? n
: 0;
513 static int first_hi_bfreg(struct mlx5_ib_dev
*dev
,
514 struct mlx5_bfreg_info
*bfregi
)
518 med
= num_med_bfreg(dev
, bfregi
);
522 static int alloc_high_class_bfreg(struct mlx5_ib_dev
*dev
,
523 struct mlx5_bfreg_info
*bfregi
)
527 for (i
= first_hi_bfreg(dev
, bfregi
); i
< max_bfregs(dev
, bfregi
); i
++) {
528 if (!bfregi
->count
[i
]) {
537 static int alloc_med_class_bfreg(struct mlx5_ib_dev
*dev
,
538 struct mlx5_bfreg_info
*bfregi
)
540 int minidx
= first_med_bfreg();
543 for (i
= first_med_bfreg(); i
< first_hi_bfreg(dev
, bfregi
); i
++) {
544 if (bfregi
->count
[i
] < bfregi
->count
[minidx
])
546 if (!bfregi
->count
[minidx
])
550 bfregi
->count
[minidx
]++;
554 static int alloc_bfreg(struct mlx5_ib_dev
*dev
,
555 struct mlx5_bfreg_info
*bfregi
,
556 enum mlx5_ib_latency_class lat
)
558 int bfregn
= -EINVAL
;
560 mutex_lock(&bfregi
->lock
);
562 case MLX5_IB_LATENCY_CLASS_LOW
:
563 BUILD_BUG_ON(NUM_NON_BLUE_FLAME_BFREGS
!= 1);
565 bfregi
->count
[bfregn
]++;
568 case MLX5_IB_LATENCY_CLASS_MEDIUM
:
572 bfregn
= alloc_med_class_bfreg(dev
, bfregi
);
575 case MLX5_IB_LATENCY_CLASS_HIGH
:
579 bfregn
= alloc_high_class_bfreg(dev
, bfregi
);
582 mutex_unlock(&bfregi
->lock
);
587 void mlx5_ib_free_bfreg(struct mlx5_ib_dev
*dev
, struct mlx5_bfreg_info
*bfregi
, int bfregn
)
589 mutex_lock(&bfregi
->lock
);
590 bfregi
->count
[bfregn
]--;
591 mutex_unlock(&bfregi
->lock
);
594 static enum mlx5_qp_state
to_mlx5_state(enum ib_qp_state state
)
597 case IB_QPS_RESET
: return MLX5_QP_STATE_RST
;
598 case IB_QPS_INIT
: return MLX5_QP_STATE_INIT
;
599 case IB_QPS_RTR
: return MLX5_QP_STATE_RTR
;
600 case IB_QPS_RTS
: return MLX5_QP_STATE_RTS
;
601 case IB_QPS_SQD
: return MLX5_QP_STATE_SQD
;
602 case IB_QPS_SQE
: return MLX5_QP_STATE_SQER
;
603 case IB_QPS_ERR
: return MLX5_QP_STATE_ERR
;
608 static int to_mlx5_st(enum ib_qp_type type
)
611 case IB_QPT_RC
: return MLX5_QP_ST_RC
;
612 case IB_QPT_UC
: return MLX5_QP_ST_UC
;
613 case IB_QPT_UD
: return MLX5_QP_ST_UD
;
614 case MLX5_IB_QPT_REG_UMR
: return MLX5_QP_ST_REG_UMR
;
616 case IB_QPT_XRC_TGT
: return MLX5_QP_ST_XRC
;
617 case IB_QPT_SMI
: return MLX5_QP_ST_QP0
;
618 case MLX5_IB_QPT_HW_GSI
: return MLX5_QP_ST_QP1
;
619 case MLX5_IB_QPT_DCI
: return MLX5_QP_ST_DCI
;
620 case IB_QPT_RAW_IPV6
: return MLX5_QP_ST_RAW_IPV6
;
621 case IB_QPT_RAW_PACKET
:
622 case IB_QPT_RAW_ETHERTYPE
: return MLX5_QP_ST_RAW_ETHERTYPE
;
624 default: return -EINVAL
;
628 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq
*send_cq
,
629 struct mlx5_ib_cq
*recv_cq
);
630 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq
*send_cq
,
631 struct mlx5_ib_cq
*recv_cq
);
633 static int bfregn_to_uar_index(struct mlx5_ib_dev
*dev
,
634 struct mlx5_bfreg_info
*bfregi
, int bfregn
,
637 int bfregs_per_sys_page
;
638 int index_of_sys_page
;
641 bfregs_per_sys_page
= get_uars_per_sys_page(dev
, bfregi
->lib_uar_4k
) *
642 MLX5_NON_FP_BFREGS_PER_UAR
;
643 index_of_sys_page
= bfregn
/ bfregs_per_sys_page
;
646 index_of_sys_page
+= bfregi
->num_static_sys_pages
;
647 if (bfregn
> bfregi
->num_dyn_bfregs
||
648 bfregi
->sys_pages
[index_of_sys_page
] == MLX5_IB_INVALID_UAR_INDEX
) {
649 mlx5_ib_dbg(dev
, "Invalid dynamic uar index\n");
654 offset
= bfregn
% bfregs_per_sys_page
/ MLX5_NON_FP_BFREGS_PER_UAR
;
655 return bfregi
->sys_pages
[index_of_sys_page
] + offset
;
658 static int mlx5_ib_umem_get(struct mlx5_ib_dev
*dev
,
660 unsigned long addr
, size_t size
,
661 struct ib_umem
**umem
,
662 int *npages
, int *page_shift
, int *ncont
,
667 *umem
= ib_umem_get(pd
->uobject
->context
, addr
, size
, 0, 0);
669 mlx5_ib_dbg(dev
, "umem_get failed\n");
670 return PTR_ERR(*umem
);
673 mlx5_ib_cont_pages(*umem
, addr
, 0, npages
, page_shift
, ncont
, NULL
);
675 err
= mlx5_ib_get_buf_offset(addr
, *page_shift
, offset
);
677 mlx5_ib_warn(dev
, "bad offset\n");
681 mlx5_ib_dbg(dev
, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
682 addr
, size
, *npages
, *page_shift
, *ncont
, *offset
);
687 ib_umem_release(*umem
);
693 static void destroy_user_rq(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
694 struct mlx5_ib_rwq
*rwq
)
696 struct mlx5_ib_ucontext
*context
;
698 if (rwq
->create_flags
& MLX5_IB_WQ_FLAGS_DELAY_DROP
)
699 atomic_dec(&dev
->delay_drop
.rqs_cnt
);
701 context
= to_mucontext(pd
->uobject
->context
);
702 mlx5_ib_db_unmap_user(context
, &rwq
->db
);
704 ib_umem_release(rwq
->umem
);
707 static int create_user_rq(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
708 struct mlx5_ib_rwq
*rwq
,
709 struct mlx5_ib_create_wq
*ucmd
)
711 struct mlx5_ib_ucontext
*context
;
721 context
= to_mucontext(pd
->uobject
->context
);
722 rwq
->umem
= ib_umem_get(pd
->uobject
->context
, ucmd
->buf_addr
,
723 rwq
->buf_size
, 0, 0);
724 if (IS_ERR(rwq
->umem
)) {
725 mlx5_ib_dbg(dev
, "umem_get failed\n");
726 err
= PTR_ERR(rwq
->umem
);
730 mlx5_ib_cont_pages(rwq
->umem
, ucmd
->buf_addr
, 0, &npages
, &page_shift
,
732 err
= mlx5_ib_get_buf_offset(ucmd
->buf_addr
, page_shift
,
733 &rwq
->rq_page_offset
);
735 mlx5_ib_warn(dev
, "bad offset\n");
739 rwq
->rq_num_pas
= ncont
;
740 rwq
->page_shift
= page_shift
;
741 rwq
->log_page_size
= page_shift
- MLX5_ADAPTER_PAGE_SHIFT
;
742 rwq
->wq_sig
= !!(ucmd
->flags
& MLX5_WQ_FLAG_SIGNATURE
);
744 mlx5_ib_dbg(dev
, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
745 (unsigned long long)ucmd
->buf_addr
, rwq
->buf_size
,
746 npages
, page_shift
, ncont
, offset
);
748 err
= mlx5_ib_db_map_user(context
, ucmd
->db_addr
, &rwq
->db
);
750 mlx5_ib_dbg(dev
, "map failed\n");
754 rwq
->create_type
= MLX5_WQ_USER
;
758 ib_umem_release(rwq
->umem
);
762 static int adjust_bfregn(struct mlx5_ib_dev
*dev
,
763 struct mlx5_bfreg_info
*bfregi
, int bfregn
)
765 return bfregn
/ MLX5_NON_FP_BFREGS_PER_UAR
* MLX5_BFREGS_PER_UAR
+
766 bfregn
% MLX5_NON_FP_BFREGS_PER_UAR
;
769 static int create_user_qp(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
770 struct mlx5_ib_qp
*qp
, struct ib_udata
*udata
,
771 struct ib_qp_init_attr
*attr
,
773 struct mlx5_ib_create_qp_resp
*resp
, int *inlen
,
774 struct mlx5_ib_qp_base
*base
)
776 struct mlx5_ib_ucontext
*context
;
777 struct mlx5_ib_create_qp ucmd
;
778 struct mlx5_ib_ubuffer
*ubuffer
= &base
->ubuffer
;
789 err
= ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
));
791 mlx5_ib_dbg(dev
, "copy failed\n");
795 context
= to_mucontext(pd
->uobject
->context
);
796 if (ucmd
.flags
& MLX5_QP_FLAG_BFREG_INDEX
) {
797 uar_index
= bfregn_to_uar_index(dev
, &context
->bfregi
,
798 ucmd
.bfreg_index
, true);
802 bfregn
= MLX5_IB_INVALID_BFREG
;
803 } else if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
) {
805 * TBD: should come from the verbs when we have the API
807 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
808 bfregn
= MLX5_CROSS_CHANNEL_BFREG
;
811 bfregn
= alloc_bfreg(dev
, &context
->bfregi
, MLX5_IB_LATENCY_CLASS_HIGH
);
813 mlx5_ib_dbg(dev
, "failed to allocate low latency BFREG\n");
814 mlx5_ib_dbg(dev
, "reverting to medium latency\n");
815 bfregn
= alloc_bfreg(dev
, &context
->bfregi
, MLX5_IB_LATENCY_CLASS_MEDIUM
);
817 mlx5_ib_dbg(dev
, "failed to allocate medium latency BFREG\n");
818 mlx5_ib_dbg(dev
, "reverting to high latency\n");
819 bfregn
= alloc_bfreg(dev
, &context
->bfregi
, MLX5_IB_LATENCY_CLASS_LOW
);
821 mlx5_ib_warn(dev
, "bfreg allocation failed\n");
828 mlx5_ib_dbg(dev
, "bfregn 0x%x, uar_index 0x%x\n", bfregn
, uar_index
);
829 if (bfregn
!= MLX5_IB_INVALID_BFREG
)
830 uar_index
= bfregn_to_uar_index(dev
, &context
->bfregi
, bfregn
,
834 qp
->sq
.wqe_shift
= ilog2(MLX5_SEND_WQE_BB
);
835 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
837 err
= set_user_buf_size(dev
, qp
, &ucmd
, base
, attr
);
841 if (ucmd
.buf_addr
&& ubuffer
->buf_size
) {
842 ubuffer
->buf_addr
= ucmd
.buf_addr
;
843 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
,
845 &ubuffer
->umem
, &npages
, &page_shift
,
850 ubuffer
->umem
= NULL
;
853 *inlen
= MLX5_ST_SZ_BYTES(create_qp_in
) +
854 MLX5_FLD_SZ_BYTES(create_qp_in
, pas
[0]) * ncont
;
855 *in
= kvzalloc(*inlen
, GFP_KERNEL
);
861 pas
= (__be64
*)MLX5_ADDR_OF(create_qp_in
, *in
, pas
);
863 mlx5_ib_populate_pas(dev
, ubuffer
->umem
, page_shift
, pas
, 0);
865 qpc
= MLX5_ADDR_OF(create_qp_in
, *in
, qpc
);
867 MLX5_SET(qpc
, qpc
, log_page_size
, page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
868 MLX5_SET(qpc
, qpc
, page_offset
, offset
);
870 MLX5_SET(qpc
, qpc
, uar_page
, uar_index
);
871 if (bfregn
!= MLX5_IB_INVALID_BFREG
)
872 resp
->bfreg_index
= adjust_bfregn(dev
, &context
->bfregi
, bfregn
);
874 resp
->bfreg_index
= MLX5_IB_INVALID_BFREG
;
877 err
= mlx5_ib_db_map_user(context
, ucmd
.db_addr
, &qp
->db
);
879 mlx5_ib_dbg(dev
, "map failed\n");
883 err
= ib_copy_to_udata(udata
, resp
, sizeof(*resp
));
885 mlx5_ib_dbg(dev
, "copy failed\n");
888 qp
->create_type
= MLX5_QP_USER
;
893 mlx5_ib_db_unmap_user(context
, &qp
->db
);
900 ib_umem_release(ubuffer
->umem
);
903 if (bfregn
!= MLX5_IB_INVALID_BFREG
)
904 mlx5_ib_free_bfreg(dev
, &context
->bfregi
, bfregn
);
908 static void destroy_qp_user(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
909 struct mlx5_ib_qp
*qp
, struct mlx5_ib_qp_base
*base
)
911 struct mlx5_ib_ucontext
*context
;
913 context
= to_mucontext(pd
->uobject
->context
);
914 mlx5_ib_db_unmap_user(context
, &qp
->db
);
915 if (base
->ubuffer
.umem
)
916 ib_umem_release(base
->ubuffer
.umem
);
919 * Free only the BFREGs which are handled by the kernel.
920 * BFREGs of UARs allocated dynamically are handled by user.
922 if (qp
->bfregn
!= MLX5_IB_INVALID_BFREG
)
923 mlx5_ib_free_bfreg(dev
, &context
->bfregi
, qp
->bfregn
);
926 static int create_kernel_qp(struct mlx5_ib_dev
*dev
,
927 struct ib_qp_init_attr
*init_attr
,
928 struct mlx5_ib_qp
*qp
,
929 u32
**in
, int *inlen
,
930 struct mlx5_ib_qp_base
*base
)
936 if (init_attr
->create_flags
& ~(IB_QP_CREATE_SIGNATURE_EN
|
937 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
|
938 IB_QP_CREATE_IPOIB_UD_LSO
|
939 IB_QP_CREATE_NETIF_QP
|
940 mlx5_ib_create_qp_sqpn_qp1()))
943 if (init_attr
->qp_type
== MLX5_IB_QPT_REG_UMR
)
944 qp
->bf
.bfreg
= &dev
->fp_bfreg
;
946 qp
->bf
.bfreg
= &dev
->bfreg
;
948 /* We need to divide by two since each register is comprised of
949 * two buffers of identical size, namely odd and even
951 qp
->bf
.buf_size
= (1 << MLX5_CAP_GEN(dev
->mdev
, log_bf_reg_size
)) / 2;
952 uar_index
= qp
->bf
.bfreg
->index
;
954 err
= calc_sq_size(dev
, init_attr
, qp
);
956 mlx5_ib_dbg(dev
, "err %d\n", err
);
961 qp
->sq
.offset
= qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
;
962 base
->ubuffer
.buf_size
= err
+ (qp
->rq
.wqe_cnt
<< qp
->rq
.wqe_shift
);
964 err
= mlx5_buf_alloc(dev
->mdev
, base
->ubuffer
.buf_size
, &qp
->buf
);
966 mlx5_ib_dbg(dev
, "err %d\n", err
);
970 qp
->sq
.qend
= mlx5_get_send_wqe(qp
, qp
->sq
.wqe_cnt
);
971 *inlen
= MLX5_ST_SZ_BYTES(create_qp_in
) +
972 MLX5_FLD_SZ_BYTES(create_qp_in
, pas
[0]) * qp
->buf
.npages
;
973 *in
= kvzalloc(*inlen
, GFP_KERNEL
);
979 qpc
= MLX5_ADDR_OF(create_qp_in
, *in
, qpc
);
980 MLX5_SET(qpc
, qpc
, uar_page
, uar_index
);
981 MLX5_SET(qpc
, qpc
, log_page_size
, qp
->buf
.page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
983 /* Set "fast registration enabled" for all kernel QPs */
984 MLX5_SET(qpc
, qpc
, fre
, 1);
985 MLX5_SET(qpc
, qpc
, rlky
, 1);
987 if (init_attr
->create_flags
& mlx5_ib_create_qp_sqpn_qp1()) {
988 MLX5_SET(qpc
, qpc
, deth_sqpn
, 1);
989 qp
->flags
|= MLX5_IB_QP_SQPN_QP1
;
992 mlx5_fill_page_array(&qp
->buf
,
993 (__be64
*)MLX5_ADDR_OF(create_qp_in
, *in
, pas
));
995 err
= mlx5_db_alloc(dev
->mdev
, &qp
->db
);
997 mlx5_ib_dbg(dev
, "err %d\n", err
);
1001 qp
->sq
.wrid
= kvmalloc_array(qp
->sq
.wqe_cnt
,
1002 sizeof(*qp
->sq
.wrid
), GFP_KERNEL
);
1003 qp
->sq
.wr_data
= kvmalloc_array(qp
->sq
.wqe_cnt
,
1004 sizeof(*qp
->sq
.wr_data
), GFP_KERNEL
);
1005 qp
->rq
.wrid
= kvmalloc_array(qp
->rq
.wqe_cnt
,
1006 sizeof(*qp
->rq
.wrid
), GFP_KERNEL
);
1007 qp
->sq
.w_list
= kvmalloc_array(qp
->sq
.wqe_cnt
,
1008 sizeof(*qp
->sq
.w_list
), GFP_KERNEL
);
1009 qp
->sq
.wqe_head
= kvmalloc_array(qp
->sq
.wqe_cnt
,
1010 sizeof(*qp
->sq
.wqe_head
), GFP_KERNEL
);
1012 if (!qp
->sq
.wrid
|| !qp
->sq
.wr_data
|| !qp
->rq
.wrid
||
1013 !qp
->sq
.w_list
|| !qp
->sq
.wqe_head
) {
1017 qp
->create_type
= MLX5_QP_KERNEL
;
1022 kvfree(qp
->sq
.wqe_head
);
1023 kvfree(qp
->sq
.w_list
);
1024 kvfree(qp
->sq
.wrid
);
1025 kvfree(qp
->sq
.wr_data
);
1026 kvfree(qp
->rq
.wrid
);
1027 mlx5_db_free(dev
->mdev
, &qp
->db
);
1033 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
1037 static void destroy_qp_kernel(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
1039 kvfree(qp
->sq
.wqe_head
);
1040 kvfree(qp
->sq
.w_list
);
1041 kvfree(qp
->sq
.wrid
);
1042 kvfree(qp
->sq
.wr_data
);
1043 kvfree(qp
->rq
.wrid
);
1044 mlx5_db_free(dev
->mdev
, &qp
->db
);
1045 mlx5_buf_free(dev
->mdev
, &qp
->buf
);
1048 static u32
get_rx_type(struct mlx5_ib_qp
*qp
, struct ib_qp_init_attr
*attr
)
1050 if (attr
->srq
|| (attr
->qp_type
== IB_QPT_XRC_TGT
) ||
1051 (attr
->qp_type
== MLX5_IB_QPT_DCI
) ||
1052 (attr
->qp_type
== IB_QPT_XRC_INI
))
1054 else if (!qp
->has_rq
)
1055 return MLX5_ZERO_LEN_RQ
;
1057 return MLX5_NON_ZERO_RQ
;
1060 static int is_connected(enum ib_qp_type qp_type
)
1062 if (qp_type
== IB_QPT_RC
|| qp_type
== IB_QPT_UC
)
1068 static int create_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
1069 struct mlx5_ib_qp
*qp
,
1070 struct mlx5_ib_sq
*sq
, u32 tdn
)
1072 u32 in
[MLX5_ST_SZ_DW(create_tis_in
)] = {0};
1073 void *tisc
= MLX5_ADDR_OF(create_tis_in
, in
, ctx
);
1075 MLX5_SET(tisc
, tisc
, transport_domain
, tdn
);
1076 if (qp
->flags
& MLX5_IB_QP_UNDERLAY
)
1077 MLX5_SET(tisc
, tisc
, underlay_qpn
, qp
->underlay_qpn
);
1079 return mlx5_core_create_tis(dev
->mdev
, in
, sizeof(in
), &sq
->tisn
);
1082 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev
*dev
,
1083 struct mlx5_ib_sq
*sq
)
1085 mlx5_core_destroy_tis(dev
->mdev
, sq
->tisn
);
1088 static void destroy_flow_rule_vport_sq(struct mlx5_ib_dev
*dev
,
1089 struct mlx5_ib_sq
*sq
)
1092 mlx5_del_flow_rules(sq
->flow_rule
);
1095 static int create_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
1096 struct mlx5_ib_sq
*sq
, void *qpin
,
1099 struct mlx5_ib_ubuffer
*ubuffer
= &sq
->ubuffer
;
1103 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
1112 err
= mlx5_ib_umem_get(dev
, pd
, ubuffer
->buf_addr
, ubuffer
->buf_size
,
1113 &sq
->ubuffer
.umem
, &npages
, &page_shift
,
1118 inlen
= MLX5_ST_SZ_BYTES(create_sq_in
) + sizeof(u64
) * ncont
;
1119 in
= kvzalloc(inlen
, GFP_KERNEL
);
1125 sqc
= MLX5_ADDR_OF(create_sq_in
, in
, ctx
);
1126 MLX5_SET(sqc
, sqc
, flush_in_error_en
, 1);
1127 if (MLX5_CAP_ETH(dev
->mdev
, multi_pkt_send_wqe
))
1128 MLX5_SET(sqc
, sqc
, allow_multi_pkt_send_wqe
, 1);
1129 MLX5_SET(sqc
, sqc
, state
, MLX5_SQC_STATE_RST
);
1130 MLX5_SET(sqc
, sqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
1131 MLX5_SET(sqc
, sqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_snd
));
1132 MLX5_SET(sqc
, sqc
, tis_lst_sz
, 1);
1133 MLX5_SET(sqc
, sqc
, tis_num_0
, sq
->tisn
);
1134 if (MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
1135 MLX5_CAP_ETH(dev
->mdev
, swp
))
1136 MLX5_SET(sqc
, sqc
, allow_swp
, 1);
1138 wq
= MLX5_ADDR_OF(sqc
, sqc
, wq
);
1139 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1140 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
1141 MLX5_SET(wq
, wq
, uar_page
, MLX5_GET(qpc
, qpc
, uar_page
));
1142 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
1143 MLX5_SET(wq
, wq
, log_wq_stride
, ilog2(MLX5_SEND_WQE_BB
));
1144 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_sq_size
));
1145 MLX5_SET(wq
, wq
, log_wq_pg_sz
, page_shift
- MLX5_ADAPTER_PAGE_SHIFT
);
1146 MLX5_SET(wq
, wq
, page_offset
, offset
);
1148 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
1149 mlx5_ib_populate_pas(dev
, sq
->ubuffer
.umem
, page_shift
, pas
, 0);
1151 err
= mlx5_core_create_sq_tracked(dev
->mdev
, in
, inlen
, &sq
->base
.mqp
);
1158 err
= create_flow_rule_vport_sq(dev
, sq
);
1165 mlx5_core_destroy_sq_tracked(dev
->mdev
, &sq
->base
.mqp
);
1168 ib_umem_release(sq
->ubuffer
.umem
);
1169 sq
->ubuffer
.umem
= NULL
;
1174 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev
*dev
,
1175 struct mlx5_ib_sq
*sq
)
1177 destroy_flow_rule_vport_sq(dev
, sq
);
1178 mlx5_core_destroy_sq_tracked(dev
->mdev
, &sq
->base
.mqp
);
1179 ib_umem_release(sq
->ubuffer
.umem
);
1182 static size_t get_rq_pas_size(void *qpc
)
1184 u32 log_page_size
= MLX5_GET(qpc
, qpc
, log_page_size
) + 12;
1185 u32 log_rq_stride
= MLX5_GET(qpc
, qpc
, log_rq_stride
);
1186 u32 log_rq_size
= MLX5_GET(qpc
, qpc
, log_rq_size
);
1187 u32 page_offset
= MLX5_GET(qpc
, qpc
, page_offset
);
1188 u32 po_quanta
= 1 << (log_page_size
- 6);
1189 u32 rq_sz
= 1 << (log_rq_size
+ 4 + log_rq_stride
);
1190 u32 page_size
= 1 << log_page_size
;
1191 u32 rq_sz_po
= rq_sz
+ (page_offset
* po_quanta
);
1192 u32 rq_num_pas
= (rq_sz_po
+ page_size
- 1) / page_size
;
1194 return rq_num_pas
* sizeof(u64
);
1197 static int create_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1198 struct mlx5_ib_rq
*rq
, void *qpin
,
1201 struct mlx5_ib_qp
*mqp
= rq
->base
.container_mibqp
;
1207 void *qpc
= MLX5_ADDR_OF(create_qp_in
, qpin
, qpc
);
1208 size_t rq_pas_size
= get_rq_pas_size(qpc
);
1212 if (qpinlen
< rq_pas_size
+ MLX5_BYTE_OFF(create_qp_in
, pas
))
1215 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) + rq_pas_size
;
1216 in
= kvzalloc(inlen
, GFP_KERNEL
);
1220 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
1221 if (!(rq
->flags
& MLX5_IB_RQ_CVLAN_STRIPPING
))
1222 MLX5_SET(rqc
, rqc
, vsd
, 1);
1223 MLX5_SET(rqc
, rqc
, mem_rq_type
, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
);
1224 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
1225 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
1226 MLX5_SET(rqc
, rqc
, user_index
, MLX5_GET(qpc
, qpc
, user_index
));
1227 MLX5_SET(rqc
, rqc
, cqn
, MLX5_GET(qpc
, qpc
, cqn_rcv
));
1229 if (mqp
->flags
& MLX5_IB_QP_CAP_SCATTER_FCS
)
1230 MLX5_SET(rqc
, rqc
, scatter_fcs
, 1);
1232 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
1233 MLX5_SET(wq
, wq
, wq_type
, MLX5_WQ_TYPE_CYCLIC
);
1234 if (rq
->flags
& MLX5_IB_RQ_PCI_WRITE_END_PADDING
)
1235 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
1236 MLX5_SET(wq
, wq
, page_offset
, MLX5_GET(qpc
, qpc
, page_offset
));
1237 MLX5_SET(wq
, wq
, pd
, MLX5_GET(qpc
, qpc
, pd
));
1238 MLX5_SET64(wq
, wq
, dbr_addr
, MLX5_GET64(qpc
, qpc
, dbr_addr
));
1239 MLX5_SET(wq
, wq
, log_wq_stride
, MLX5_GET(qpc
, qpc
, log_rq_stride
) + 4);
1240 MLX5_SET(wq
, wq
, log_wq_pg_sz
, MLX5_GET(qpc
, qpc
, log_page_size
));
1241 MLX5_SET(wq
, wq
, log_wq_sz
, MLX5_GET(qpc
, qpc
, log_rq_size
));
1243 pas
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
1244 qp_pas
= (__be64
*)MLX5_ADDR_OF(create_qp_in
, qpin
, pas
);
1245 memcpy(pas
, qp_pas
, rq_pas_size
);
1247 err
= mlx5_core_create_rq_tracked(dev
->mdev
, in
, inlen
, &rq
->base
.mqp
);
1254 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
1255 struct mlx5_ib_rq
*rq
)
1257 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rq
->base
.mqp
);
1260 static bool tunnel_offload_supported(struct mlx5_core_dev
*dev
)
1262 return (MLX5_CAP_ETH(dev
, tunnel_stateless_vxlan
) ||
1263 MLX5_CAP_ETH(dev
, tunnel_stateless_gre
) ||
1264 MLX5_CAP_ETH(dev
, tunnel_stateless_geneve_rx
));
1267 static int create_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1268 struct mlx5_ib_rq
*rq
, u32 tdn
,
1269 bool tunnel_offload_en
)
1276 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1277 in
= kvzalloc(inlen
, GFP_KERNEL
);
1281 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1282 MLX5_SET(tirc
, tirc
, disp_type
, MLX5_TIRC_DISP_TYPE_DIRECT
);
1283 MLX5_SET(tirc
, tirc
, inline_rqn
, rq
->base
.mqp
.qpn
);
1284 MLX5_SET(tirc
, tirc
, transport_domain
, tdn
);
1285 if (tunnel_offload_en
)
1286 MLX5_SET(tirc
, tirc
, tunneled_offload_en
, 1);
1289 MLX5_SET(tirc
, tirc
, self_lb_block
,
1290 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
);
1292 err
= mlx5_core_create_tir(dev
->mdev
, in
, inlen
, &rq
->tirn
);
1299 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev
*dev
,
1300 struct mlx5_ib_rq
*rq
)
1302 mlx5_core_destroy_tir(dev
->mdev
, rq
->tirn
);
1305 static int create_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1306 u32
*in
, size_t inlen
,
1309 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1310 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1311 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1312 struct ib_uobject
*uobj
= pd
->uobject
;
1313 struct ib_ucontext
*ucontext
= uobj
->context
;
1314 struct mlx5_ib_ucontext
*mucontext
= to_mucontext(ucontext
);
1316 u32 tdn
= mucontext
->tdn
;
1318 if (qp
->sq
.wqe_cnt
) {
1319 err
= create_raw_packet_qp_tis(dev
, qp
, sq
, tdn
);
1323 err
= create_raw_packet_qp_sq(dev
, sq
, in
, pd
);
1325 goto err_destroy_tis
;
1327 sq
->base
.container_mibqp
= qp
;
1328 sq
->base
.mqp
.event
= mlx5_ib_qp_event
;
1331 if (qp
->rq
.wqe_cnt
) {
1332 rq
->base
.container_mibqp
= qp
;
1334 if (qp
->flags
& MLX5_IB_QP_CVLAN_STRIPPING
)
1335 rq
->flags
|= MLX5_IB_RQ_CVLAN_STRIPPING
;
1336 if (qp
->flags
& MLX5_IB_QP_PCI_WRITE_END_PADDING
)
1337 rq
->flags
|= MLX5_IB_RQ_PCI_WRITE_END_PADDING
;
1338 err
= create_raw_packet_qp_rq(dev
, rq
, in
, inlen
);
1340 goto err_destroy_sq
;
1343 err
= create_raw_packet_qp_tir(dev
, rq
, tdn
,
1344 qp
->tunnel_offload_en
);
1346 goto err_destroy_rq
;
1349 qp
->trans_qp
.base
.mqp
.qpn
= qp
->sq
.wqe_cnt
? sq
->base
.mqp
.qpn
:
1355 destroy_raw_packet_qp_rq(dev
, rq
);
1357 if (!qp
->sq
.wqe_cnt
)
1359 destroy_raw_packet_qp_sq(dev
, sq
);
1361 destroy_raw_packet_qp_tis(dev
, sq
);
1366 static void destroy_raw_packet_qp(struct mlx5_ib_dev
*dev
,
1367 struct mlx5_ib_qp
*qp
)
1369 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
1370 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1371 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1373 if (qp
->rq
.wqe_cnt
) {
1374 destroy_raw_packet_qp_tir(dev
, rq
);
1375 destroy_raw_packet_qp_rq(dev
, rq
);
1378 if (qp
->sq
.wqe_cnt
) {
1379 destroy_raw_packet_qp_sq(dev
, sq
);
1380 destroy_raw_packet_qp_tis(dev
, sq
);
1384 static void raw_packet_qp_copy_info(struct mlx5_ib_qp
*qp
,
1385 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
)
1387 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
1388 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
1392 sq
->doorbell
= &qp
->db
;
1393 rq
->doorbell
= &qp
->db
;
1396 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
1398 mlx5_core_destroy_tir(dev
->mdev
, qp
->rss_qp
.tirn
);
1401 static int create_rss_raw_qp_tir(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
1403 struct ib_qp_init_attr
*init_attr
,
1404 struct ib_udata
*udata
)
1406 struct ib_uobject
*uobj
= pd
->uobject
;
1407 struct ib_ucontext
*ucontext
= uobj
->context
;
1408 struct mlx5_ib_ucontext
*mucontext
= to_mucontext(ucontext
);
1409 struct mlx5_ib_create_qp_resp resp
= {};
1415 u32 selected_fields
= 0;
1416 size_t min_resp_len
;
1417 u32 tdn
= mucontext
->tdn
;
1418 struct mlx5_ib_create_qp_rss ucmd
= {};
1419 size_t required_cmd_sz
;
1421 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
)
1424 if (init_attr
->create_flags
|| init_attr
->send_cq
)
1427 min_resp_len
= offsetof(typeof(resp
), bfreg_index
) + sizeof(resp
.bfreg_index
);
1428 if (udata
->outlen
< min_resp_len
)
1431 required_cmd_sz
= offsetof(typeof(ucmd
), flags
) + sizeof(ucmd
.flags
);
1432 if (udata
->inlen
< required_cmd_sz
) {
1433 mlx5_ib_dbg(dev
, "invalid inlen\n");
1437 if (udata
->inlen
> sizeof(ucmd
) &&
1438 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
1439 udata
->inlen
- sizeof(ucmd
))) {
1440 mlx5_ib_dbg(dev
, "inlen is not supported\n");
1444 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
))) {
1445 mlx5_ib_dbg(dev
, "copy failed\n");
1449 if (ucmd
.comp_mask
) {
1450 mlx5_ib_dbg(dev
, "invalid comp mask\n");
1454 if (ucmd
.flags
& ~MLX5_QP_FLAG_TUNNEL_OFFLOADS
) {
1455 mlx5_ib_dbg(dev
, "invalid flags\n");
1459 if (ucmd
.flags
& MLX5_QP_FLAG_TUNNEL_OFFLOADS
&&
1460 !tunnel_offload_supported(dev
->mdev
)) {
1461 mlx5_ib_dbg(dev
, "tunnel offloads isn't supported\n");
1465 if (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_INNER
&&
1466 !(ucmd
.flags
& MLX5_QP_FLAG_TUNNEL_OFFLOADS
)) {
1467 mlx5_ib_dbg(dev
, "Tunnel offloads must be set for inner RSS\n");
1471 err
= ib_copy_to_udata(udata
, &resp
, min_resp_len
);
1473 mlx5_ib_dbg(dev
, "copy failed\n");
1477 inlen
= MLX5_ST_SZ_BYTES(create_tir_in
);
1478 in
= kvzalloc(inlen
, GFP_KERNEL
);
1482 tirc
= MLX5_ADDR_OF(create_tir_in
, in
, ctx
);
1483 MLX5_SET(tirc
, tirc
, disp_type
,
1484 MLX5_TIRC_DISP_TYPE_INDIRECT
);
1485 MLX5_SET(tirc
, tirc
, indirect_table
,
1486 init_attr
->rwq_ind_tbl
->ind_tbl_num
);
1487 MLX5_SET(tirc
, tirc
, transport_domain
, tdn
);
1489 hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1491 if (ucmd
.flags
& MLX5_QP_FLAG_TUNNEL_OFFLOADS
)
1492 MLX5_SET(tirc
, tirc
, tunneled_offload_en
, 1);
1494 if (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_INNER
)
1495 hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_inner
);
1497 hfso
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_field_selector_outer
);
1499 switch (ucmd
.rx_hash_function
) {
1500 case MLX5_RX_HASH_FUNC_TOEPLITZ
:
1502 void *rss_key
= MLX5_ADDR_OF(tirc
, tirc
, rx_hash_toeplitz_key
);
1503 size_t len
= MLX5_FLD_SZ_BYTES(tirc
, rx_hash_toeplitz_key
);
1505 if (len
!= ucmd
.rx_key_len
) {
1510 MLX5_SET(tirc
, tirc
, rx_hash_fn
, MLX5_RX_HASH_FN_TOEPLITZ
);
1511 MLX5_SET(tirc
, tirc
, rx_hash_symmetric
, 1);
1512 memcpy(rss_key
, ucmd
.rx_hash_key
, len
);
1520 if (!ucmd
.rx_hash_fields_mask
) {
1521 /* special case when this TIR serves as steering entry without hashing */
1522 if (!init_attr
->rwq_ind_tbl
->log_ind_tbl_size
)
1528 if (((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1529 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
)) &&
1530 ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
) ||
1531 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))) {
1536 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1537 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1538 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
))
1539 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1540 MLX5_L3_PROT_TYPE_IPV4
);
1541 else if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
) ||
1542 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))
1543 MLX5_SET(rx_hash_field_select
, hfso
, l3_prot_type
,
1544 MLX5_L3_PROT_TYPE_IPV6
);
1546 if (((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1547 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
)) &&
1548 ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
) ||
1549 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))) {
1554 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1555 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1556 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
))
1557 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1558 MLX5_L4_PROT_TYPE_TCP
);
1559 else if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
) ||
1560 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))
1561 MLX5_SET(rx_hash_field_select
, hfso
, l4_prot_type
,
1562 MLX5_L4_PROT_TYPE_UDP
);
1564 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV4
) ||
1565 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_IPV6
))
1566 selected_fields
|= MLX5_HASH_FIELD_SEL_SRC_IP
;
1568 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV4
) ||
1569 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_IPV6
))
1570 selected_fields
|= MLX5_HASH_FIELD_SEL_DST_IP
;
1572 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_TCP
) ||
1573 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_SRC_PORT_UDP
))
1574 selected_fields
|= MLX5_HASH_FIELD_SEL_L4_SPORT
;
1576 if ((ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_TCP
) ||
1577 (ucmd
.rx_hash_fields_mask
& MLX5_RX_HASH_DST_PORT_UDP
))
1578 selected_fields
|= MLX5_HASH_FIELD_SEL_L4_DPORT
;
1580 MLX5_SET(rx_hash_field_select
, hfso
, selected_fields
, selected_fields
);
1584 MLX5_SET(tirc
, tirc
, self_lb_block
,
1585 MLX5_TIRC_SELF_LB_BLOCK_BLOCK_UNICAST_
);
1587 err
= mlx5_core_create_tir(dev
->mdev
, in
, inlen
, &qp
->rss_qp
.tirn
);
1593 /* qpn is reserved for that QP */
1594 qp
->trans_qp
.base
.mqp
.qpn
= 0;
1595 qp
->flags
|= MLX5_IB_QP_RSS
;
1603 static int create_qp_common(struct mlx5_ib_dev
*dev
, struct ib_pd
*pd
,
1604 struct ib_qp_init_attr
*init_attr
,
1605 struct ib_udata
*udata
, struct mlx5_ib_qp
*qp
)
1607 struct mlx5_ib_resources
*devr
= &dev
->devr
;
1608 int inlen
= MLX5_ST_SZ_BYTES(create_qp_in
);
1609 struct mlx5_core_dev
*mdev
= dev
->mdev
;
1610 struct mlx5_ib_create_qp_resp resp
;
1611 struct mlx5_ib_cq
*send_cq
;
1612 struct mlx5_ib_cq
*recv_cq
;
1613 unsigned long flags
;
1614 u32 uidx
= MLX5_IB_DEFAULT_UIDX
;
1615 struct mlx5_ib_create_qp ucmd
;
1616 struct mlx5_ib_qp_base
*base
;
1622 mutex_init(&qp
->mutex
);
1623 spin_lock_init(&qp
->sq
.lock
);
1624 spin_lock_init(&qp
->rq
.lock
);
1626 mlx5_st
= to_mlx5_st(init_attr
->qp_type
);
1630 if (init_attr
->rwq_ind_tbl
) {
1634 err
= create_rss_raw_qp_tir(dev
, qp
, pd
, init_attr
, udata
);
1638 if (init_attr
->create_flags
& IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
) {
1639 if (!MLX5_CAP_GEN(mdev
, block_lb_mc
)) {
1640 mlx5_ib_dbg(dev
, "block multicast loopback isn't supported\n");
1643 qp
->flags
|= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
;
1647 if (init_attr
->create_flags
&
1648 (IB_QP_CREATE_CROSS_CHANNEL
|
1649 IB_QP_CREATE_MANAGED_SEND
|
1650 IB_QP_CREATE_MANAGED_RECV
)) {
1651 if (!MLX5_CAP_GEN(mdev
, cd
)) {
1652 mlx5_ib_dbg(dev
, "cross-channel isn't supported\n");
1655 if (init_attr
->create_flags
& IB_QP_CREATE_CROSS_CHANNEL
)
1656 qp
->flags
|= MLX5_IB_QP_CROSS_CHANNEL
;
1657 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_SEND
)
1658 qp
->flags
|= MLX5_IB_QP_MANAGED_SEND
;
1659 if (init_attr
->create_flags
& IB_QP_CREATE_MANAGED_RECV
)
1660 qp
->flags
|= MLX5_IB_QP_MANAGED_RECV
;
1663 if (init_attr
->qp_type
== IB_QPT_UD
&&
1664 (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
))
1665 if (!MLX5_CAP_GEN(mdev
, ipoib_basic_offloads
)) {
1666 mlx5_ib_dbg(dev
, "ipoib UD lso qp isn't supported\n");
1670 if (init_attr
->create_flags
& IB_QP_CREATE_SCATTER_FCS
) {
1671 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
) {
1672 mlx5_ib_dbg(dev
, "Scatter FCS is supported only for Raw Packet QPs");
1675 if (!MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) ||
1676 !MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
)) {
1677 mlx5_ib_dbg(dev
, "Scatter FCS isn't supported\n");
1680 qp
->flags
|= MLX5_IB_QP_CAP_SCATTER_FCS
;
1683 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
)
1684 qp
->sq_signal_bits
= MLX5_WQE_CTRL_CQ_UPDATE
;
1686 if (init_attr
->create_flags
& IB_QP_CREATE_CVLAN_STRIPPING
) {
1687 if (!(MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
1688 MLX5_CAP_ETH(dev
->mdev
, vlan_cap
)) ||
1689 (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
))
1691 qp
->flags
|= MLX5_IB_QP_CVLAN_STRIPPING
;
1694 if (pd
&& pd
->uobject
) {
1695 if (ib_copy_from_udata(&ucmd
, udata
, sizeof(ucmd
))) {
1696 mlx5_ib_dbg(dev
, "copy failed\n");
1700 err
= get_qp_user_index(to_mucontext(pd
->uobject
->context
),
1701 &ucmd
, udata
->inlen
, &uidx
);
1705 qp
->wq_sig
= !!(ucmd
.flags
& MLX5_QP_FLAG_SIGNATURE
);
1706 qp
->scat_cqe
= !!(ucmd
.flags
& MLX5_QP_FLAG_SCATTER_CQE
);
1707 if (ucmd
.flags
& MLX5_QP_FLAG_TUNNEL_OFFLOADS
) {
1708 if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
||
1709 !tunnel_offload_supported(mdev
)) {
1710 mlx5_ib_dbg(dev
, "Tunnel offload isn't supported\n");
1713 qp
->tunnel_offload_en
= true;
1716 if (init_attr
->create_flags
& IB_QP_CREATE_SOURCE_QPN
) {
1717 if (init_attr
->qp_type
!= IB_QPT_UD
||
1718 (MLX5_CAP_GEN(dev
->mdev
, port_type
) !=
1719 MLX5_CAP_PORT_TYPE_IB
) ||
1720 !mlx5_get_flow_namespace(dev
->mdev
, MLX5_FLOW_NAMESPACE_BYPASS
)) {
1721 mlx5_ib_dbg(dev
, "Source QP option isn't supported\n");
1725 qp
->flags
|= MLX5_IB_QP_UNDERLAY
;
1726 qp
->underlay_qpn
= init_attr
->source_qpn
;
1729 qp
->wq_sig
= !!wq_signature
;
1732 base
= (init_attr
->qp_type
== IB_QPT_RAW_PACKET
||
1733 qp
->flags
& MLX5_IB_QP_UNDERLAY
) ?
1734 &qp
->raw_packet_qp
.rq
.base
:
1737 qp
->has_rq
= qp_has_rq(init_attr
);
1738 err
= set_rq_size(dev
, &init_attr
->cap
, qp
->has_rq
,
1739 qp
, (pd
&& pd
->uobject
) ? &ucmd
: NULL
);
1741 mlx5_ib_dbg(dev
, "err %d\n", err
);
1748 1 << MLX5_CAP_GEN(mdev
, log_max_qp_sz
);
1749 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d)\n", ucmd
.sq_wqe_count
);
1750 if (ucmd
.rq_wqe_shift
!= qp
->rq
.wqe_shift
||
1751 ucmd
.rq_wqe_count
!= qp
->rq
.wqe_cnt
) {
1752 mlx5_ib_dbg(dev
, "invalid rq params\n");
1755 if (ucmd
.sq_wqe_count
> max_wqes
) {
1756 mlx5_ib_dbg(dev
, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1757 ucmd
.sq_wqe_count
, max_wqes
);
1760 if (init_attr
->create_flags
&
1761 mlx5_ib_create_qp_sqpn_qp1()) {
1762 mlx5_ib_dbg(dev
, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1765 err
= create_user_qp(dev
, pd
, qp
, udata
, init_attr
, &in
,
1766 &resp
, &inlen
, base
);
1768 mlx5_ib_dbg(dev
, "err %d\n", err
);
1770 err
= create_kernel_qp(dev
, init_attr
, qp
, &in
, &inlen
,
1773 mlx5_ib_dbg(dev
, "err %d\n", err
);
1779 in
= kvzalloc(inlen
, GFP_KERNEL
);
1783 qp
->create_type
= MLX5_QP_EMPTY
;
1786 if (is_sqp(init_attr
->qp_type
))
1787 qp
->port
= init_attr
->port_num
;
1789 qpc
= MLX5_ADDR_OF(create_qp_in
, in
, qpc
);
1791 MLX5_SET(qpc
, qpc
, st
, mlx5_st
);
1792 MLX5_SET(qpc
, qpc
, pm_state
, MLX5_QP_PM_MIGRATED
);
1794 if (init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
)
1795 MLX5_SET(qpc
, qpc
, pd
, to_mpd(pd
? pd
: devr
->p0
)->pdn
);
1797 MLX5_SET(qpc
, qpc
, latency_sensitive
, 1);
1801 MLX5_SET(qpc
, qpc
, wq_signature
, 1);
1803 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
1804 MLX5_SET(qpc
, qpc
, block_lb_mc
, 1);
1806 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
1807 MLX5_SET(qpc
, qpc
, cd_master
, 1);
1808 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
1809 MLX5_SET(qpc
, qpc
, cd_slave_send
, 1);
1810 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
1811 MLX5_SET(qpc
, qpc
, cd_slave_receive
, 1);
1813 if (qp
->scat_cqe
&& is_connected(init_attr
->qp_type
)) {
1817 rcqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->recv_cq
);
1818 scqe_sz
= mlx5_ib_get_cqe_size(dev
, init_attr
->send_cq
);
1821 MLX5_SET(qpc
, qpc
, cs_res
, MLX5_RES_SCAT_DATA64_CQE
);
1823 MLX5_SET(qpc
, qpc
, cs_res
, MLX5_RES_SCAT_DATA32_CQE
);
1825 if (init_attr
->sq_sig_type
== IB_SIGNAL_ALL_WR
) {
1827 MLX5_SET(qpc
, qpc
, cs_req
, MLX5_REQ_SCAT_DATA64_CQE
);
1829 MLX5_SET(qpc
, qpc
, cs_req
, MLX5_REQ_SCAT_DATA32_CQE
);
1833 if (qp
->rq
.wqe_cnt
) {
1834 MLX5_SET(qpc
, qpc
, log_rq_stride
, qp
->rq
.wqe_shift
- 4);
1835 MLX5_SET(qpc
, qpc
, log_rq_size
, ilog2(qp
->rq
.wqe_cnt
));
1838 MLX5_SET(qpc
, qpc
, rq_type
, get_rx_type(qp
, init_attr
));
1840 if (qp
->sq
.wqe_cnt
) {
1841 MLX5_SET(qpc
, qpc
, log_sq_size
, ilog2(qp
->sq
.wqe_cnt
));
1843 MLX5_SET(qpc
, qpc
, no_sq
, 1);
1844 if (init_attr
->srq
&&
1845 init_attr
->srq
->srq_type
== IB_SRQT_TM
)
1846 MLX5_SET(qpc
, qpc
, offload_type
,
1847 MLX5_QPC_OFFLOAD_TYPE_RNDV
);
1850 /* Set default resources */
1851 switch (init_attr
->qp_type
) {
1852 case IB_QPT_XRC_TGT
:
1853 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(devr
->c0
)->mcq
.cqn
);
1854 MLX5_SET(qpc
, qpc
, cqn_snd
, to_mcq(devr
->c0
)->mcq
.cqn
);
1855 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s0
)->msrq
.srqn
);
1856 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(init_attr
->xrcd
)->xrcdn
);
1858 case IB_QPT_XRC_INI
:
1859 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(devr
->c0
)->mcq
.cqn
);
1860 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x1
)->xrcdn
);
1861 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s0
)->msrq
.srqn
);
1864 if (init_attr
->srq
) {
1865 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x0
)->xrcdn
);
1866 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(init_attr
->srq
)->msrq
.srqn
);
1868 MLX5_SET(qpc
, qpc
, xrcd
, to_mxrcd(devr
->x1
)->xrcdn
);
1869 MLX5_SET(qpc
, qpc
, srqn_rmpn_xrqn
, to_msrq(devr
->s1
)->msrq
.srqn
);
1873 if (init_attr
->send_cq
)
1874 MLX5_SET(qpc
, qpc
, cqn_snd
, to_mcq(init_attr
->send_cq
)->mcq
.cqn
);
1876 if (init_attr
->recv_cq
)
1877 MLX5_SET(qpc
, qpc
, cqn_rcv
, to_mcq(init_attr
->recv_cq
)->mcq
.cqn
);
1879 MLX5_SET64(qpc
, qpc
, dbr_addr
, qp
->db
.dma
);
1881 /* 0xffffff means we ask to work with cqe version 0 */
1882 if (MLX5_CAP_GEN(mdev
, cqe_version
) == MLX5_CQE_VERSION_V1
)
1883 MLX5_SET(qpc
, qpc
, user_index
, uidx
);
1885 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1886 if (init_attr
->qp_type
== IB_QPT_UD
&&
1887 (init_attr
->create_flags
& IB_QP_CREATE_IPOIB_UD_LSO
)) {
1888 MLX5_SET(qpc
, qpc
, ulp_stateless_offload_mode
, 1);
1889 qp
->flags
|= MLX5_IB_QP_LSO
;
1892 if (init_attr
->create_flags
& IB_QP_CREATE_PCI_WRITE_END_PADDING
) {
1893 if (!MLX5_CAP_GEN(dev
->mdev
, end_pad
)) {
1894 mlx5_ib_dbg(dev
, "scatter end padding is not supported\n");
1897 } else if (init_attr
->qp_type
!= IB_QPT_RAW_PACKET
) {
1898 MLX5_SET(qpc
, qpc
, end_padding_mode
,
1899 MLX5_WQ_END_PAD_MODE_ALIGN
);
1901 qp
->flags
|= MLX5_IB_QP_PCI_WRITE_END_PADDING
;
1910 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
||
1911 qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
1912 qp
->raw_packet_qp
.sq
.ubuffer
.buf_addr
= ucmd
.sq_buf_addr
;
1913 raw_packet_qp_copy_info(qp
, &qp
->raw_packet_qp
);
1914 err
= create_raw_packet_qp(dev
, qp
, in
, inlen
, pd
);
1916 err
= mlx5_core_create_qp(dev
->mdev
, &base
->mqp
, in
, inlen
);
1920 mlx5_ib_dbg(dev
, "create qp failed\n");
1926 base
->container_mibqp
= qp
;
1927 base
->mqp
.event
= mlx5_ib_qp_event
;
1929 get_cqs(init_attr
->qp_type
, init_attr
->send_cq
, init_attr
->recv_cq
,
1930 &send_cq
, &recv_cq
);
1931 spin_lock_irqsave(&dev
->reset_flow_resource_lock
, flags
);
1932 mlx5_ib_lock_cqs(send_cq
, recv_cq
);
1933 /* Maintain device to QPs access, needed for further handling via reset
1936 list_add_tail(&qp
->qps_list
, &dev
->qp_list
);
1937 /* Maintain CQ to QPs access, needed for further handling via reset flow
1940 list_add_tail(&qp
->cq_send_list
, &send_cq
->list_send_qp
);
1942 list_add_tail(&qp
->cq_recv_list
, &recv_cq
->list_recv_qp
);
1943 mlx5_ib_unlock_cqs(send_cq
, recv_cq
);
1944 spin_unlock_irqrestore(&dev
->reset_flow_resource_lock
, flags
);
1949 if (qp
->create_type
== MLX5_QP_USER
)
1950 destroy_qp_user(dev
, pd
, qp
, base
);
1951 else if (qp
->create_type
== MLX5_QP_KERNEL
)
1952 destroy_qp_kernel(dev
, qp
);
1959 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1960 __acquires(&send_cq
->lock
) __acquires(&recv_cq
->lock
)
1964 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1965 spin_lock(&send_cq
->lock
);
1966 spin_lock_nested(&recv_cq
->lock
,
1967 SINGLE_DEPTH_NESTING
);
1968 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1969 spin_lock(&send_cq
->lock
);
1970 __acquire(&recv_cq
->lock
);
1972 spin_lock(&recv_cq
->lock
);
1973 spin_lock_nested(&send_cq
->lock
,
1974 SINGLE_DEPTH_NESTING
);
1977 spin_lock(&send_cq
->lock
);
1978 __acquire(&recv_cq
->lock
);
1980 } else if (recv_cq
) {
1981 spin_lock(&recv_cq
->lock
);
1982 __acquire(&send_cq
->lock
);
1984 __acquire(&send_cq
->lock
);
1985 __acquire(&recv_cq
->lock
);
1989 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq
*send_cq
, struct mlx5_ib_cq
*recv_cq
)
1990 __releases(&send_cq
->lock
) __releases(&recv_cq
->lock
)
1994 if (send_cq
->mcq
.cqn
< recv_cq
->mcq
.cqn
) {
1995 spin_unlock(&recv_cq
->lock
);
1996 spin_unlock(&send_cq
->lock
);
1997 } else if (send_cq
->mcq
.cqn
== recv_cq
->mcq
.cqn
) {
1998 __release(&recv_cq
->lock
);
1999 spin_unlock(&send_cq
->lock
);
2001 spin_unlock(&send_cq
->lock
);
2002 spin_unlock(&recv_cq
->lock
);
2005 __release(&recv_cq
->lock
);
2006 spin_unlock(&send_cq
->lock
);
2008 } else if (recv_cq
) {
2009 __release(&send_cq
->lock
);
2010 spin_unlock(&recv_cq
->lock
);
2012 __release(&recv_cq
->lock
);
2013 __release(&send_cq
->lock
);
2017 static struct mlx5_ib_pd
*get_pd(struct mlx5_ib_qp
*qp
)
2019 return to_mpd(qp
->ibqp
.pd
);
2022 static void get_cqs(enum ib_qp_type qp_type
,
2023 struct ib_cq
*ib_send_cq
, struct ib_cq
*ib_recv_cq
,
2024 struct mlx5_ib_cq
**send_cq
, struct mlx5_ib_cq
**recv_cq
)
2027 case IB_QPT_XRC_TGT
:
2031 case MLX5_IB_QPT_REG_UMR
:
2032 case IB_QPT_XRC_INI
:
2033 *send_cq
= ib_send_cq
? to_mcq(ib_send_cq
) : NULL
;
2038 case MLX5_IB_QPT_HW_GSI
:
2042 case IB_QPT_RAW_IPV6
:
2043 case IB_QPT_RAW_ETHERTYPE
:
2044 case IB_QPT_RAW_PACKET
:
2045 *send_cq
= ib_send_cq
? to_mcq(ib_send_cq
) : NULL
;
2046 *recv_cq
= ib_recv_cq
? to_mcq(ib_recv_cq
) : NULL
;
2057 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2058 const struct mlx5_modify_raw_qp_param
*raw_qp_param
,
2059 u8 lag_tx_affinity
);
2061 static void destroy_qp_common(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
)
2063 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
2064 struct mlx5_ib_qp_base
*base
;
2065 unsigned long flags
;
2068 if (qp
->ibqp
.rwq_ind_tbl
) {
2069 destroy_rss_raw_qp_tir(dev
, qp
);
2073 base
= (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
||
2074 qp
->flags
& MLX5_IB_QP_UNDERLAY
) ?
2075 &qp
->raw_packet_qp
.rq
.base
:
2078 if (qp
->state
!= IB_QPS_RESET
) {
2079 if (qp
->ibqp
.qp_type
!= IB_QPT_RAW_PACKET
&&
2080 !(qp
->flags
& MLX5_IB_QP_UNDERLAY
)) {
2081 err
= mlx5_core_qp_modify(dev
->mdev
,
2082 MLX5_CMD_OP_2RST_QP
, 0,
2085 struct mlx5_modify_raw_qp_param raw_qp_param
= {
2086 .operation
= MLX5_CMD_OP_2RST_QP
2089 err
= modify_raw_packet_qp(dev
, qp
, &raw_qp_param
, 0);
2092 mlx5_ib_warn(dev
, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
2096 get_cqs(qp
->ibqp
.qp_type
, qp
->ibqp
.send_cq
, qp
->ibqp
.recv_cq
,
2097 &send_cq
, &recv_cq
);
2099 spin_lock_irqsave(&dev
->reset_flow_resource_lock
, flags
);
2100 mlx5_ib_lock_cqs(send_cq
, recv_cq
);
2101 /* del from lists under both locks above to protect reset flow paths */
2102 list_del(&qp
->qps_list
);
2104 list_del(&qp
->cq_send_list
);
2107 list_del(&qp
->cq_recv_list
);
2109 if (qp
->create_type
== MLX5_QP_KERNEL
) {
2110 __mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
2111 qp
->ibqp
.srq
? to_msrq(qp
->ibqp
.srq
) : NULL
);
2112 if (send_cq
!= recv_cq
)
2113 __mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
,
2116 mlx5_ib_unlock_cqs(send_cq
, recv_cq
);
2117 spin_unlock_irqrestore(&dev
->reset_flow_resource_lock
, flags
);
2119 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
||
2120 qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
2121 destroy_raw_packet_qp(dev
, qp
);
2123 err
= mlx5_core_destroy_qp(dev
->mdev
, &base
->mqp
);
2125 mlx5_ib_warn(dev
, "failed to destroy QP 0x%x\n",
2129 if (qp
->create_type
== MLX5_QP_KERNEL
)
2130 destroy_qp_kernel(dev
, qp
);
2131 else if (qp
->create_type
== MLX5_QP_USER
)
2132 destroy_qp_user(dev
, &get_pd(qp
)->ibpd
, qp
, base
);
2135 static const char *ib_qp_type_str(enum ib_qp_type type
)
2139 return "IB_QPT_SMI";
2141 return "IB_QPT_GSI";
2148 case IB_QPT_RAW_IPV6
:
2149 return "IB_QPT_RAW_IPV6";
2150 case IB_QPT_RAW_ETHERTYPE
:
2151 return "IB_QPT_RAW_ETHERTYPE";
2152 case IB_QPT_XRC_INI
:
2153 return "IB_QPT_XRC_INI";
2154 case IB_QPT_XRC_TGT
:
2155 return "IB_QPT_XRC_TGT";
2156 case IB_QPT_RAW_PACKET
:
2157 return "IB_QPT_RAW_PACKET";
2158 case MLX5_IB_QPT_REG_UMR
:
2159 return "MLX5_IB_QPT_REG_UMR";
2161 return "IB_QPT_DRIVER";
2164 return "Invalid QP type";
2168 static struct ib_qp
*mlx5_ib_create_dct(struct ib_pd
*pd
,
2169 struct ib_qp_init_attr
*attr
,
2170 struct mlx5_ib_create_qp
*ucmd
)
2172 struct mlx5_ib_qp
*qp
;
2174 u32 uidx
= MLX5_IB_DEFAULT_UIDX
;
2177 if (!attr
->srq
|| !attr
->recv_cq
)
2178 return ERR_PTR(-EINVAL
);
2180 err
= get_qp_user_index(to_mucontext(pd
->uobject
->context
),
2181 ucmd
, sizeof(*ucmd
), &uidx
);
2183 return ERR_PTR(err
);
2185 qp
= kzalloc(sizeof(*qp
), GFP_KERNEL
);
2187 return ERR_PTR(-ENOMEM
);
2189 qp
->dct
.in
= kzalloc(MLX5_ST_SZ_BYTES(create_dct_in
), GFP_KERNEL
);
2195 dctc
= MLX5_ADDR_OF(create_dct_in
, qp
->dct
.in
, dct_context_entry
);
2196 qp
->qp_sub_type
= MLX5_IB_QPT_DCT
;
2197 MLX5_SET(dctc
, dctc
, pd
, to_mpd(pd
)->pdn
);
2198 MLX5_SET(dctc
, dctc
, srqn_xrqn
, to_msrq(attr
->srq
)->msrq
.srqn
);
2199 MLX5_SET(dctc
, dctc
, cqn
, to_mcq(attr
->recv_cq
)->mcq
.cqn
);
2200 MLX5_SET64(dctc
, dctc
, dc_access_key
, ucmd
->access_key
);
2201 MLX5_SET(dctc
, dctc
, user_index
, uidx
);
2203 qp
->state
= IB_QPS_RESET
;
2208 return ERR_PTR(err
);
2211 static int set_mlx_qp_type(struct mlx5_ib_dev
*dev
,
2212 struct ib_qp_init_attr
*init_attr
,
2213 struct mlx5_ib_create_qp
*ucmd
,
2214 struct ib_udata
*udata
)
2216 enum { MLX_QP_FLAGS
= MLX5_QP_FLAG_TYPE_DCT
| MLX5_QP_FLAG_TYPE_DCI
};
2222 if (udata
->inlen
< sizeof(*ucmd
)) {
2223 mlx5_ib_dbg(dev
, "create_qp user command is smaller than expected\n");
2226 err
= ib_copy_from_udata(ucmd
, udata
, sizeof(*ucmd
));
2230 if ((ucmd
->flags
& MLX_QP_FLAGS
) == MLX5_QP_FLAG_TYPE_DCI
) {
2231 init_attr
->qp_type
= MLX5_IB_QPT_DCI
;
2233 if ((ucmd
->flags
& MLX_QP_FLAGS
) == MLX5_QP_FLAG_TYPE_DCT
) {
2234 init_attr
->qp_type
= MLX5_IB_QPT_DCT
;
2236 mlx5_ib_dbg(dev
, "Invalid QP flags\n");
2241 if (!MLX5_CAP_GEN(dev
->mdev
, dct
)) {
2242 mlx5_ib_dbg(dev
, "DC transport is not supported\n");
2249 struct ib_qp
*mlx5_ib_create_qp(struct ib_pd
*pd
,
2250 struct ib_qp_init_attr
*verbs_init_attr
,
2251 struct ib_udata
*udata
)
2253 struct mlx5_ib_dev
*dev
;
2254 struct mlx5_ib_qp
*qp
;
2257 struct ib_qp_init_attr mlx_init_attr
;
2258 struct ib_qp_init_attr
*init_attr
= verbs_init_attr
;
2261 dev
= to_mdev(pd
->device
);
2263 if (init_attr
->qp_type
== IB_QPT_RAW_PACKET
) {
2265 mlx5_ib_dbg(dev
, "Raw Packet QP is not supported for kernel consumers\n");
2266 return ERR_PTR(-EINVAL
);
2267 } else if (!to_mucontext(pd
->uobject
->context
)->cqe_version
) {
2268 mlx5_ib_dbg(dev
, "Raw Packet QP is only supported for CQE version > 0\n");
2269 return ERR_PTR(-EINVAL
);
2273 /* being cautious here */
2274 if (init_attr
->qp_type
!= IB_QPT_XRC_TGT
&&
2275 init_attr
->qp_type
!= MLX5_IB_QPT_REG_UMR
) {
2276 pr_warn("%s: no PD for transport %s\n", __func__
,
2277 ib_qp_type_str(init_attr
->qp_type
));
2278 return ERR_PTR(-EINVAL
);
2280 dev
= to_mdev(to_mxrcd(init_attr
->xrcd
)->ibxrcd
.device
);
2283 if (init_attr
->qp_type
== IB_QPT_DRIVER
) {
2284 struct mlx5_ib_create_qp ucmd
;
2286 init_attr
= &mlx_init_attr
;
2287 memcpy(init_attr
, verbs_init_attr
, sizeof(*verbs_init_attr
));
2288 err
= set_mlx_qp_type(dev
, init_attr
, &ucmd
, udata
);
2290 return ERR_PTR(err
);
2292 if (init_attr
->qp_type
== MLX5_IB_QPT_DCI
) {
2293 if (init_attr
->cap
.max_recv_wr
||
2294 init_attr
->cap
.max_recv_sge
) {
2295 mlx5_ib_dbg(dev
, "DCI QP requires zero size receive queue\n");
2296 return ERR_PTR(-EINVAL
);
2299 return mlx5_ib_create_dct(pd
, init_attr
, &ucmd
);
2303 switch (init_attr
->qp_type
) {
2304 case IB_QPT_XRC_TGT
:
2305 case IB_QPT_XRC_INI
:
2306 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
)) {
2307 mlx5_ib_dbg(dev
, "XRC not supported\n");
2308 return ERR_PTR(-ENOSYS
);
2310 init_attr
->recv_cq
= NULL
;
2311 if (init_attr
->qp_type
== IB_QPT_XRC_TGT
) {
2312 xrcdn
= to_mxrcd(init_attr
->xrcd
)->xrcdn
;
2313 init_attr
->send_cq
= NULL
;
2317 case IB_QPT_RAW_PACKET
:
2322 case MLX5_IB_QPT_HW_GSI
:
2323 case MLX5_IB_QPT_REG_UMR
:
2324 case MLX5_IB_QPT_DCI
:
2325 qp
= kzalloc(sizeof(*qp
), GFP_KERNEL
);
2327 return ERR_PTR(-ENOMEM
);
2329 err
= create_qp_common(dev
, pd
, init_attr
, udata
, qp
);
2331 mlx5_ib_dbg(dev
, "create_qp_common failed\n");
2333 return ERR_PTR(err
);
2336 if (is_qp0(init_attr
->qp_type
))
2337 qp
->ibqp
.qp_num
= 0;
2338 else if (is_qp1(init_attr
->qp_type
))
2339 qp
->ibqp
.qp_num
= 1;
2341 qp
->ibqp
.qp_num
= qp
->trans_qp
.base
.mqp
.qpn
;
2343 mlx5_ib_dbg(dev
, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2344 qp
->ibqp
.qp_num
, qp
->trans_qp
.base
.mqp
.qpn
,
2345 init_attr
->recv_cq
? to_mcq(init_attr
->recv_cq
)->mcq
.cqn
: -1,
2346 init_attr
->send_cq
? to_mcq(init_attr
->send_cq
)->mcq
.cqn
: -1);
2348 qp
->trans_qp
.xrcdn
= xrcdn
;
2353 return mlx5_ib_gsi_create_qp(pd
, init_attr
);
2355 case IB_QPT_RAW_IPV6
:
2356 case IB_QPT_RAW_ETHERTYPE
:
2359 mlx5_ib_dbg(dev
, "unsupported qp type %d\n",
2360 init_attr
->qp_type
);
2361 /* Don't support raw QPs */
2362 return ERR_PTR(-EINVAL
);
2365 if (verbs_init_attr
->qp_type
== IB_QPT_DRIVER
)
2366 qp
->qp_sub_type
= init_attr
->qp_type
;
2371 static int mlx5_ib_destroy_dct(struct mlx5_ib_qp
*mqp
)
2373 struct mlx5_ib_dev
*dev
= to_mdev(mqp
->ibqp
.device
);
2375 if (mqp
->state
== IB_QPS_RTR
) {
2378 err
= mlx5_core_destroy_dct(dev
->mdev
, &mqp
->dct
.mdct
);
2380 mlx5_ib_warn(dev
, "failed to destroy DCT %d\n", err
);
2390 int mlx5_ib_destroy_qp(struct ib_qp
*qp
)
2392 struct mlx5_ib_dev
*dev
= to_mdev(qp
->device
);
2393 struct mlx5_ib_qp
*mqp
= to_mqp(qp
);
2395 if (unlikely(qp
->qp_type
== IB_QPT_GSI
))
2396 return mlx5_ib_gsi_destroy_qp(qp
);
2398 if (mqp
->qp_sub_type
== MLX5_IB_QPT_DCT
)
2399 return mlx5_ib_destroy_dct(mqp
);
2401 destroy_qp_common(dev
, mqp
);
2408 static __be32
to_mlx5_access_flags(struct mlx5_ib_qp
*qp
, const struct ib_qp_attr
*attr
,
2411 u32 hw_access_flags
= 0;
2415 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
2416 dest_rd_atomic
= attr
->max_dest_rd_atomic
;
2418 dest_rd_atomic
= qp
->trans_qp
.resp_depth
;
2420 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
2421 access_flags
= attr
->qp_access_flags
;
2423 access_flags
= qp
->trans_qp
.atomic_rd_en
;
2425 if (!dest_rd_atomic
)
2426 access_flags
&= IB_ACCESS_REMOTE_WRITE
;
2428 if (access_flags
& IB_ACCESS_REMOTE_READ
)
2429 hw_access_flags
|= MLX5_QP_BIT_RRE
;
2430 if (access_flags
& IB_ACCESS_REMOTE_ATOMIC
)
2431 hw_access_flags
|= (MLX5_QP_BIT_RAE
| MLX5_ATOMIC_MODE_CX
);
2432 if (access_flags
& IB_ACCESS_REMOTE_WRITE
)
2433 hw_access_flags
|= MLX5_QP_BIT_RWE
;
2435 return cpu_to_be32(hw_access_flags
);
2439 MLX5_PATH_FLAG_FL
= 1 << 0,
2440 MLX5_PATH_FLAG_FREE_AR
= 1 << 1,
2441 MLX5_PATH_FLAG_COUNTER
= 1 << 2,
2444 static int ib_rate_to_mlx5(struct mlx5_ib_dev
*dev
, u8 rate
)
2446 if (rate
== IB_RATE_PORT_CURRENT
) {
2448 } else if (rate
< IB_RATE_2_5_GBPS
|| rate
> IB_RATE_300_GBPS
) {
2451 while (rate
!= IB_RATE_2_5_GBPS
&&
2452 !(1 << (rate
+ MLX5_STAT_RATE_OFFSET
) &
2453 MLX5_CAP_GEN(dev
->mdev
, stat_rate_support
)))
2457 return rate
+ MLX5_STAT_RATE_OFFSET
;
2460 static int modify_raw_packet_eth_prio(struct mlx5_core_dev
*dev
,
2461 struct mlx5_ib_sq
*sq
, u8 sl
)
2468 inlen
= MLX5_ST_SZ_BYTES(modify_tis_in
);
2469 in
= kvzalloc(inlen
, GFP_KERNEL
);
2473 MLX5_SET(modify_tis_in
, in
, bitmask
.prio
, 1);
2475 tisc
= MLX5_ADDR_OF(modify_tis_in
, in
, ctx
);
2476 MLX5_SET(tisc
, tisc
, prio
, ((sl
& 0x7) << 1));
2478 err
= mlx5_core_modify_tis(dev
, sq
->tisn
, in
, inlen
);
2485 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev
*dev
,
2486 struct mlx5_ib_sq
*sq
, u8 tx_affinity
)
2493 inlen
= MLX5_ST_SZ_BYTES(modify_tis_in
);
2494 in
= kvzalloc(inlen
, GFP_KERNEL
);
2498 MLX5_SET(modify_tis_in
, in
, bitmask
.lag_tx_port_affinity
, 1);
2500 tisc
= MLX5_ADDR_OF(modify_tis_in
, in
, ctx
);
2501 MLX5_SET(tisc
, tisc
, lag_tx_port_affinity
, tx_affinity
);
2503 err
= mlx5_core_modify_tis(dev
, sq
->tisn
, in
, inlen
);
2510 static int mlx5_set_path(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2511 const struct rdma_ah_attr
*ah
,
2512 struct mlx5_qp_path
*path
, u8 port
, int attr_mask
,
2513 u32 path_flags
, const struct ib_qp_attr
*attr
,
2516 const struct ib_global_route
*grh
= rdma_ah_read_grh(ah
);
2518 enum ib_gid_type gid_type
;
2519 u8 ah_flags
= rdma_ah_get_ah_flags(ah
);
2520 u8 sl
= rdma_ah_get_sl(ah
);
2522 if (attr_mask
& IB_QP_PKEY_INDEX
)
2523 path
->pkey_index
= cpu_to_be16(alt
? attr
->alt_pkey_index
:
2526 if (ah_flags
& IB_AH_GRH
) {
2527 if (grh
->sgid_index
>=
2528 dev
->mdev
->port_caps
[port
- 1].gid_table_len
) {
2529 pr_err("sgid_index (%u) too large. max is %d\n",
2531 dev
->mdev
->port_caps
[port
- 1].gid_table_len
);
2536 if (ah
->type
== RDMA_AH_ATTR_TYPE_ROCE
) {
2537 if (!(ah_flags
& IB_AH_GRH
))
2539 err
= mlx5_get_roce_gid_type(dev
, port
, grh
->sgid_index
,
2543 memcpy(path
->rmac
, ah
->roce
.dmac
, sizeof(ah
->roce
.dmac
));
2544 if (qp
->ibqp
.qp_type
== IB_QPT_RC
||
2545 qp
->ibqp
.qp_type
== IB_QPT_UC
||
2546 qp
->ibqp
.qp_type
== IB_QPT_XRC_INI
||
2547 qp
->ibqp
.qp_type
== IB_QPT_XRC_TGT
)
2548 path
->udp_sport
= mlx5_get_roce_udp_sport(dev
, port
,
2550 path
->dci_cfi_prio_sl
= (sl
& 0x7) << 4;
2551 if (gid_type
== IB_GID_TYPE_ROCE_UDP_ENCAP
)
2552 path
->ecn_dscp
= (grh
->traffic_class
>> 2) & 0x3f;
2554 path
->fl_free_ar
= (path_flags
& MLX5_PATH_FLAG_FL
) ? 0x80 : 0;
2556 (path_flags
& MLX5_PATH_FLAG_FREE_AR
) ? 0x40 : 0;
2557 path
->rlid
= cpu_to_be16(rdma_ah_get_dlid(ah
));
2558 path
->grh_mlid
= rdma_ah_get_path_bits(ah
) & 0x7f;
2559 if (ah_flags
& IB_AH_GRH
)
2560 path
->grh_mlid
|= 1 << 7;
2561 path
->dci_cfi_prio_sl
= sl
& 0xf;
2564 if (ah_flags
& IB_AH_GRH
) {
2565 path
->mgid_index
= grh
->sgid_index
;
2566 path
->hop_limit
= grh
->hop_limit
;
2567 path
->tclass_flowlabel
=
2568 cpu_to_be32((grh
->traffic_class
<< 20) |
2570 memcpy(path
->rgid
, grh
->dgid
.raw
, 16);
2573 err
= ib_rate_to_mlx5(dev
, rdma_ah_get_static_rate(ah
));
2576 path
->static_rate
= err
;
2579 if (attr_mask
& IB_QP_TIMEOUT
)
2580 path
->ackto_lt
= (alt
? attr
->alt_timeout
: attr
->timeout
) << 3;
2582 if ((qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
) && qp
->sq
.wqe_cnt
)
2583 return modify_raw_packet_eth_prio(dev
->mdev
,
2584 &qp
->raw_packet_qp
.sq
,
2590 static enum mlx5_qp_optpar opt_mask
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
][MLX5_QP_ST_MAX
] = {
2591 [MLX5_QP_STATE_INIT
] = {
2592 [MLX5_QP_STATE_INIT
] = {
2593 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
2594 MLX5_QP_OPTPAR_RAE
|
2595 MLX5_QP_OPTPAR_RWE
|
2596 MLX5_QP_OPTPAR_PKEY_INDEX
|
2597 MLX5_QP_OPTPAR_PRI_PORT
,
2598 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
2599 MLX5_QP_OPTPAR_PKEY_INDEX
|
2600 MLX5_QP_OPTPAR_PRI_PORT
,
2601 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2602 MLX5_QP_OPTPAR_Q_KEY
|
2603 MLX5_QP_OPTPAR_PRI_PORT
,
2605 [MLX5_QP_STATE_RTR
] = {
2606 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2607 MLX5_QP_OPTPAR_RRE
|
2608 MLX5_QP_OPTPAR_RAE
|
2609 MLX5_QP_OPTPAR_RWE
|
2610 MLX5_QP_OPTPAR_PKEY_INDEX
,
2611 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2612 MLX5_QP_OPTPAR_RWE
|
2613 MLX5_QP_OPTPAR_PKEY_INDEX
,
2614 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2615 MLX5_QP_OPTPAR_Q_KEY
,
2616 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_PKEY_INDEX
|
2617 MLX5_QP_OPTPAR_Q_KEY
,
2618 [MLX5_QP_ST_XRC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2619 MLX5_QP_OPTPAR_RRE
|
2620 MLX5_QP_OPTPAR_RAE
|
2621 MLX5_QP_OPTPAR_RWE
|
2622 MLX5_QP_OPTPAR_PKEY_INDEX
,
2625 [MLX5_QP_STATE_RTR
] = {
2626 [MLX5_QP_STATE_RTS
] = {
2627 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2628 MLX5_QP_OPTPAR_RRE
|
2629 MLX5_QP_OPTPAR_RAE
|
2630 MLX5_QP_OPTPAR_RWE
|
2631 MLX5_QP_OPTPAR_PM_STATE
|
2632 MLX5_QP_OPTPAR_RNR_TIMEOUT
,
2633 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_ALT_ADDR_PATH
|
2634 MLX5_QP_OPTPAR_RWE
|
2635 MLX5_QP_OPTPAR_PM_STATE
,
2636 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
2639 [MLX5_QP_STATE_RTS
] = {
2640 [MLX5_QP_STATE_RTS
] = {
2641 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RRE
|
2642 MLX5_QP_OPTPAR_RAE
|
2643 MLX5_QP_OPTPAR_RWE
|
2644 MLX5_QP_OPTPAR_RNR_TIMEOUT
|
2645 MLX5_QP_OPTPAR_PM_STATE
|
2646 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
2647 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
|
2648 MLX5_QP_OPTPAR_PM_STATE
|
2649 MLX5_QP_OPTPAR_ALT_ADDR_PATH
,
2650 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
|
2651 MLX5_QP_OPTPAR_SRQN
|
2652 MLX5_QP_OPTPAR_CQN_RCV
,
2655 [MLX5_QP_STATE_SQER
] = {
2656 [MLX5_QP_STATE_RTS
] = {
2657 [MLX5_QP_ST_UD
] = MLX5_QP_OPTPAR_Q_KEY
,
2658 [MLX5_QP_ST_MLX
] = MLX5_QP_OPTPAR_Q_KEY
,
2659 [MLX5_QP_ST_UC
] = MLX5_QP_OPTPAR_RWE
,
2660 [MLX5_QP_ST_RC
] = MLX5_QP_OPTPAR_RNR_TIMEOUT
|
2661 MLX5_QP_OPTPAR_RWE
|
2662 MLX5_QP_OPTPAR_RAE
|
2668 static int ib_nr_to_mlx5_nr(int ib_mask
)
2673 case IB_QP_CUR_STATE
:
2675 case IB_QP_EN_SQD_ASYNC_NOTIFY
:
2677 case IB_QP_ACCESS_FLAGS
:
2678 return MLX5_QP_OPTPAR_RWE
| MLX5_QP_OPTPAR_RRE
|
2680 case IB_QP_PKEY_INDEX
:
2681 return MLX5_QP_OPTPAR_PKEY_INDEX
;
2683 return MLX5_QP_OPTPAR_PRI_PORT
;
2685 return MLX5_QP_OPTPAR_Q_KEY
;
2687 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH
|
2688 MLX5_QP_OPTPAR_PRI_PORT
;
2689 case IB_QP_PATH_MTU
:
2692 return MLX5_QP_OPTPAR_ACK_TIMEOUT
;
2693 case IB_QP_RETRY_CNT
:
2694 return MLX5_QP_OPTPAR_RETRY_COUNT
;
2695 case IB_QP_RNR_RETRY
:
2696 return MLX5_QP_OPTPAR_RNR_RETRY
;
2699 case IB_QP_MAX_QP_RD_ATOMIC
:
2700 return MLX5_QP_OPTPAR_SRA_MAX
;
2701 case IB_QP_ALT_PATH
:
2702 return MLX5_QP_OPTPAR_ALT_ADDR_PATH
;
2703 case IB_QP_MIN_RNR_TIMER
:
2704 return MLX5_QP_OPTPAR_RNR_TIMEOUT
;
2707 case IB_QP_MAX_DEST_RD_ATOMIC
:
2708 return MLX5_QP_OPTPAR_RRA_MAX
| MLX5_QP_OPTPAR_RWE
|
2709 MLX5_QP_OPTPAR_RRE
| MLX5_QP_OPTPAR_RAE
;
2710 case IB_QP_PATH_MIG_STATE
:
2711 return MLX5_QP_OPTPAR_PM_STATE
;
2714 case IB_QP_DEST_QPN
:
2720 static int ib_mask_to_mlx5_opt(int ib_mask
)
2725 for (i
= 0; i
< 8 * sizeof(int); i
++) {
2726 if ((1 << i
) & ib_mask
)
2727 result
|= ib_nr_to_mlx5_nr(1 << i
);
2733 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev
*dev
,
2734 struct mlx5_ib_rq
*rq
, int new_state
,
2735 const struct mlx5_modify_raw_qp_param
*raw_qp_param
)
2742 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
2743 in
= kvzalloc(inlen
, GFP_KERNEL
);
2747 MLX5_SET(modify_rq_in
, in
, rq_state
, rq
->state
);
2749 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
2750 MLX5_SET(rqc
, rqc
, state
, new_state
);
2752 if (raw_qp_param
->set_mask
& MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID
) {
2753 if (MLX5_CAP_GEN(dev
->mdev
, modify_rq_counter_set_id
)) {
2754 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
2755 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID
);
2756 MLX5_SET(rqc
, rqc
, counter_set_id
, raw_qp_param
->rq_q_ctr_id
);
2758 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2762 err
= mlx5_core_modify_rq(dev
->mdev
, rq
->base
.mqp
.qpn
, in
, inlen
);
2766 rq
->state
= new_state
;
2773 static int modify_raw_packet_qp_sq(struct mlx5_core_dev
*dev
,
2774 struct mlx5_ib_sq
*sq
,
2776 const struct mlx5_modify_raw_qp_param
*raw_qp_param
)
2778 struct mlx5_ib_qp
*ibqp
= sq
->base
.container_mibqp
;
2779 struct mlx5_rate_limit old_rl
= ibqp
->rl
;
2780 struct mlx5_rate_limit new_rl
= old_rl
;
2781 bool new_rate_added
= false;
2788 inlen
= MLX5_ST_SZ_BYTES(modify_sq_in
);
2789 in
= kvzalloc(inlen
, GFP_KERNEL
);
2793 MLX5_SET(modify_sq_in
, in
, sq_state
, sq
->state
);
2795 sqc
= MLX5_ADDR_OF(modify_sq_in
, in
, ctx
);
2796 MLX5_SET(sqc
, sqc
, state
, new_state
);
2798 if (raw_qp_param
->set_mask
& MLX5_RAW_QP_RATE_LIMIT
) {
2799 if (new_state
!= MLX5_SQC_STATE_RDY
)
2800 pr_warn("%s: Rate limit can only be changed when SQ is moving to RDY\n",
2803 new_rl
= raw_qp_param
->rl
;
2806 if (!mlx5_rl_are_equal(&old_rl
, &new_rl
)) {
2808 err
= mlx5_rl_add_rate(dev
, &rl_index
, &new_rl
);
2810 pr_err("Failed configuring rate limit(err %d): \
2811 rate %u, max_burst_sz %u, typical_pkt_sz %u\n",
2812 err
, new_rl
.rate
, new_rl
.max_burst_sz
,
2813 new_rl
.typical_pkt_sz
);
2817 new_rate_added
= true;
2820 MLX5_SET64(modify_sq_in
, in
, modify_bitmask
, 1);
2821 /* index 0 means no limit */
2822 MLX5_SET(sqc
, sqc
, packet_pacing_rate_limit_index
, rl_index
);
2825 err
= mlx5_core_modify_sq(dev
, sq
->base
.mqp
.qpn
, in
, inlen
);
2827 /* Remove new rate from table if failed */
2829 mlx5_rl_remove_rate(dev
, &new_rl
);
2833 /* Only remove the old rate after new rate was set */
2835 !mlx5_rl_are_equal(&old_rl
, &new_rl
)) ||
2836 (new_state
!= MLX5_SQC_STATE_RDY
))
2837 mlx5_rl_remove_rate(dev
, &old_rl
);
2840 sq
->state
= new_state
;
2847 static int modify_raw_packet_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
2848 const struct mlx5_modify_raw_qp_param
*raw_qp_param
,
2851 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
2852 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
2853 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
2854 int modify_rq
= !!qp
->rq
.wqe_cnt
;
2855 int modify_sq
= !!qp
->sq
.wqe_cnt
;
2860 switch (raw_qp_param
->operation
) {
2861 case MLX5_CMD_OP_RST2INIT_QP
:
2862 rq_state
= MLX5_RQC_STATE_RDY
;
2863 sq_state
= MLX5_SQC_STATE_RDY
;
2865 case MLX5_CMD_OP_2ERR_QP
:
2866 rq_state
= MLX5_RQC_STATE_ERR
;
2867 sq_state
= MLX5_SQC_STATE_ERR
;
2869 case MLX5_CMD_OP_2RST_QP
:
2870 rq_state
= MLX5_RQC_STATE_RST
;
2871 sq_state
= MLX5_SQC_STATE_RST
;
2873 case MLX5_CMD_OP_RTR2RTS_QP
:
2874 case MLX5_CMD_OP_RTS2RTS_QP
:
2875 if (raw_qp_param
->set_mask
==
2876 MLX5_RAW_QP_RATE_LIMIT
) {
2878 sq_state
= sq
->state
;
2880 return raw_qp_param
->set_mask
? -EINVAL
: 0;
2883 case MLX5_CMD_OP_INIT2INIT_QP
:
2884 case MLX5_CMD_OP_INIT2RTR_QP
:
2885 if (raw_qp_param
->set_mask
)
2895 err
= modify_raw_packet_qp_rq(dev
, rq
, rq_state
, raw_qp_param
);
2902 err
= modify_raw_packet_tx_affinity(dev
->mdev
, sq
,
2908 return modify_raw_packet_qp_sq(dev
->mdev
, sq
, sq_state
, raw_qp_param
);
2914 static int __mlx5_ib_modify_qp(struct ib_qp
*ibqp
,
2915 const struct ib_qp_attr
*attr
, int attr_mask
,
2916 enum ib_qp_state cur_state
, enum ib_qp_state new_state
,
2917 const struct mlx5_ib_modify_qp
*ucmd
)
2919 static const u16 optab
[MLX5_QP_NUM_STATE
][MLX5_QP_NUM_STATE
] = {
2920 [MLX5_QP_STATE_RST
] = {
2921 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2922 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2923 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_RST2INIT_QP
,
2925 [MLX5_QP_STATE_INIT
] = {
2926 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2927 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2928 [MLX5_QP_STATE_INIT
] = MLX5_CMD_OP_INIT2INIT_QP
,
2929 [MLX5_QP_STATE_RTR
] = MLX5_CMD_OP_INIT2RTR_QP
,
2931 [MLX5_QP_STATE_RTR
] = {
2932 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2933 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2934 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTR2RTS_QP
,
2936 [MLX5_QP_STATE_RTS
] = {
2937 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2938 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2939 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_RTS2RTS_QP
,
2941 [MLX5_QP_STATE_SQD
] = {
2942 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2943 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2945 [MLX5_QP_STATE_SQER
] = {
2946 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2947 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2948 [MLX5_QP_STATE_RTS
] = MLX5_CMD_OP_SQERR2RTS_QP
,
2950 [MLX5_QP_STATE_ERR
] = {
2951 [MLX5_QP_STATE_RST
] = MLX5_CMD_OP_2RST_QP
,
2952 [MLX5_QP_STATE_ERR
] = MLX5_CMD_OP_2ERR_QP
,
2956 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
2957 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
2958 struct mlx5_ib_qp_base
*base
= &qp
->trans_qp
.base
;
2959 struct mlx5_ib_cq
*send_cq
, *recv_cq
;
2960 struct mlx5_qp_context
*context
;
2961 struct mlx5_ib_pd
*pd
;
2962 struct mlx5_ib_port
*mibport
= NULL
;
2963 enum mlx5_qp_state mlx5_cur
, mlx5_new
;
2964 enum mlx5_qp_optpar optpar
;
2970 mlx5_st
= to_mlx5_st(ibqp
->qp_type
== IB_QPT_DRIVER
?
2971 qp
->qp_sub_type
: ibqp
->qp_type
);
2975 context
= kzalloc(sizeof(*context
), GFP_KERNEL
);
2979 context
->flags
= cpu_to_be32(mlx5_st
<< 16);
2981 if (!(attr_mask
& IB_QP_PATH_MIG_STATE
)) {
2982 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2984 switch (attr
->path_mig_state
) {
2985 case IB_MIG_MIGRATED
:
2986 context
->flags
|= cpu_to_be32(MLX5_QP_PM_MIGRATED
<< 11);
2989 context
->flags
|= cpu_to_be32(MLX5_QP_PM_REARM
<< 11);
2992 context
->flags
|= cpu_to_be32(MLX5_QP_PM_ARMED
<< 11);
2997 if ((cur_state
== IB_QPS_RESET
) && (new_state
== IB_QPS_INIT
)) {
2998 if ((ibqp
->qp_type
== IB_QPT_RC
) ||
2999 (ibqp
->qp_type
== IB_QPT_UD
&&
3000 !(qp
->flags
& MLX5_IB_QP_SQPN_QP1
)) ||
3001 (ibqp
->qp_type
== IB_QPT_UC
) ||
3002 (ibqp
->qp_type
== IB_QPT_RAW_PACKET
) ||
3003 (ibqp
->qp_type
== IB_QPT_XRC_INI
) ||
3004 (ibqp
->qp_type
== IB_QPT_XRC_TGT
)) {
3005 if (mlx5_lag_is_active(dev
->mdev
)) {
3006 u8 p
= mlx5_core_native_port_num(dev
->mdev
);
3007 tx_affinity
= (unsigned int)atomic_add_return(1,
3008 &dev
->roce
[p
].next_port
) %
3010 context
->flags
|= cpu_to_be32(tx_affinity
<< 24);
3015 if (is_sqp(ibqp
->qp_type
)) {
3016 context
->mtu_msgmax
= (IB_MTU_256
<< 5) | 8;
3017 } else if ((ibqp
->qp_type
== IB_QPT_UD
&&
3018 !(qp
->flags
& MLX5_IB_QP_UNDERLAY
)) ||
3019 ibqp
->qp_type
== MLX5_IB_QPT_REG_UMR
) {
3020 context
->mtu_msgmax
= (IB_MTU_4096
<< 5) | 12;
3021 } else if (attr_mask
& IB_QP_PATH_MTU
) {
3022 if (attr
->path_mtu
< IB_MTU_256
||
3023 attr
->path_mtu
> IB_MTU_4096
) {
3024 mlx5_ib_warn(dev
, "invalid mtu %d\n", attr
->path_mtu
);
3028 context
->mtu_msgmax
= (attr
->path_mtu
<< 5) |
3029 (u8
)MLX5_CAP_GEN(dev
->mdev
, log_max_msg
);
3032 if (attr_mask
& IB_QP_DEST_QPN
)
3033 context
->log_pg_sz_remote_qpn
= cpu_to_be32(attr
->dest_qp_num
);
3035 if (attr_mask
& IB_QP_PKEY_INDEX
)
3036 context
->pri_path
.pkey_index
= cpu_to_be16(attr
->pkey_index
);
3038 /* todo implement counter_index functionality */
3040 if (is_sqp(ibqp
->qp_type
))
3041 context
->pri_path
.port
= qp
->port
;
3043 if (attr_mask
& IB_QP_PORT
)
3044 context
->pri_path
.port
= attr
->port_num
;
3046 if (attr_mask
& IB_QP_AV
) {
3047 err
= mlx5_set_path(dev
, qp
, &attr
->ah_attr
, &context
->pri_path
,
3048 attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
,
3049 attr_mask
, 0, attr
, false);
3054 if (attr_mask
& IB_QP_TIMEOUT
)
3055 context
->pri_path
.ackto_lt
|= attr
->timeout
<< 3;
3057 if (attr_mask
& IB_QP_ALT_PATH
) {
3058 err
= mlx5_set_path(dev
, qp
, &attr
->alt_ah_attr
,
3061 attr_mask
| IB_QP_PKEY_INDEX
| IB_QP_TIMEOUT
,
3068 get_cqs(qp
->ibqp
.qp_type
, qp
->ibqp
.send_cq
, qp
->ibqp
.recv_cq
,
3069 &send_cq
, &recv_cq
);
3071 context
->flags_pd
= cpu_to_be32(pd
? pd
->pdn
: to_mpd(dev
->devr
.p0
)->pdn
);
3072 context
->cqn_send
= send_cq
? cpu_to_be32(send_cq
->mcq
.cqn
) : 0;
3073 context
->cqn_recv
= recv_cq
? cpu_to_be32(recv_cq
->mcq
.cqn
) : 0;
3074 context
->params1
= cpu_to_be32(MLX5_IB_ACK_REQ_FREQ
<< 28);
3076 if (attr_mask
& IB_QP_RNR_RETRY
)
3077 context
->params1
|= cpu_to_be32(attr
->rnr_retry
<< 13);
3079 if (attr_mask
& IB_QP_RETRY_CNT
)
3080 context
->params1
|= cpu_to_be32(attr
->retry_cnt
<< 16);
3082 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
) {
3083 if (attr
->max_rd_atomic
)
3085 cpu_to_be32(fls(attr
->max_rd_atomic
- 1) << 21);
3088 if (attr_mask
& IB_QP_SQ_PSN
)
3089 context
->next_send_psn
= cpu_to_be32(attr
->sq_psn
);
3091 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
) {
3092 if (attr
->max_dest_rd_atomic
)
3094 cpu_to_be32(fls(attr
->max_dest_rd_atomic
- 1) << 21);
3097 if (attr_mask
& (IB_QP_ACCESS_FLAGS
| IB_QP_MAX_DEST_RD_ATOMIC
))
3098 context
->params2
|= to_mlx5_access_flags(qp
, attr
, attr_mask
);
3100 if (attr_mask
& IB_QP_MIN_RNR_TIMER
)
3101 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->min_rnr_timer
<< 24);
3103 if (attr_mask
& IB_QP_RQ_PSN
)
3104 context
->rnr_nextrecvpsn
|= cpu_to_be32(attr
->rq_psn
);
3106 if (attr_mask
& IB_QP_QKEY
)
3107 context
->qkey
= cpu_to_be32(attr
->qkey
);
3109 if (qp
->rq
.wqe_cnt
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
3110 context
->db_rec_addr
= cpu_to_be64(qp
->db
.dma
);
3112 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
3113 u8 port_num
= (attr_mask
& IB_QP_PORT
? attr
->port_num
:
3116 /* Underlay port should be used - index 0 function per port */
3117 if (qp
->flags
& MLX5_IB_QP_UNDERLAY
)
3120 mibport
= &dev
->port
[port_num
];
3121 context
->qp_counter_set_usr_page
|=
3122 cpu_to_be32((u32
)(mibport
->cnts
.set_id
) << 24);
3125 if (!ibqp
->uobject
&& cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
)
3126 context
->sq_crq_size
|= cpu_to_be16(1 << 4);
3128 if (qp
->flags
& MLX5_IB_QP_SQPN_QP1
)
3129 context
->deth_sqpn
= cpu_to_be32(1);
3131 mlx5_cur
= to_mlx5_state(cur_state
);
3132 mlx5_new
= to_mlx5_state(new_state
);
3134 if (mlx5_cur
>= MLX5_QP_NUM_STATE
|| mlx5_new
>= MLX5_QP_NUM_STATE
||
3135 !optab
[mlx5_cur
][mlx5_new
]) {
3140 op
= optab
[mlx5_cur
][mlx5_new
];
3141 optpar
= ib_mask_to_mlx5_opt(attr_mask
);
3142 optpar
&= opt_mask
[mlx5_cur
][mlx5_new
][mlx5_st
];
3144 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
||
3145 qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
3146 struct mlx5_modify_raw_qp_param raw_qp_param
= {};
3148 raw_qp_param
.operation
= op
;
3149 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
3150 raw_qp_param
.rq_q_ctr_id
= mibport
->cnts
.set_id
;
3151 raw_qp_param
.set_mask
|= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID
;
3154 if (attr_mask
& IB_QP_RATE_LIMIT
) {
3155 raw_qp_param
.rl
.rate
= attr
->rate_limit
;
3157 if (ucmd
->burst_info
.max_burst_sz
) {
3158 if (attr
->rate_limit
&&
3159 MLX5_CAP_QOS(dev
->mdev
, packet_pacing_burst_bound
)) {
3160 raw_qp_param
.rl
.max_burst_sz
=
3161 ucmd
->burst_info
.max_burst_sz
;
3168 if (ucmd
->burst_info
.typical_pkt_sz
) {
3169 if (attr
->rate_limit
&&
3170 MLX5_CAP_QOS(dev
->mdev
, packet_pacing_typical_size
)) {
3171 raw_qp_param
.rl
.typical_pkt_sz
=
3172 ucmd
->burst_info
.typical_pkt_sz
;
3179 raw_qp_param
.set_mask
|= MLX5_RAW_QP_RATE_LIMIT
;
3182 err
= modify_raw_packet_qp(dev
, qp
, &raw_qp_param
, tx_affinity
);
3184 err
= mlx5_core_qp_modify(dev
->mdev
, op
, optpar
, context
,
3191 qp
->state
= new_state
;
3193 if (attr_mask
& IB_QP_ACCESS_FLAGS
)
3194 qp
->trans_qp
.atomic_rd_en
= attr
->qp_access_flags
;
3195 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
)
3196 qp
->trans_qp
.resp_depth
= attr
->max_dest_rd_atomic
;
3197 if (attr_mask
& IB_QP_PORT
)
3198 qp
->port
= attr
->port_num
;
3199 if (attr_mask
& IB_QP_ALT_PATH
)
3200 qp
->trans_qp
.alt_port
= attr
->alt_port_num
;
3203 * If we moved a kernel QP to RESET, clean up all old CQ
3204 * entries and reinitialize the QP.
3206 if (new_state
== IB_QPS_RESET
&&
3207 !ibqp
->uobject
&& ibqp
->qp_type
!= IB_QPT_XRC_TGT
) {
3208 mlx5_ib_cq_clean(recv_cq
, base
->mqp
.qpn
,
3209 ibqp
->srq
? to_msrq(ibqp
->srq
) : NULL
);
3210 if (send_cq
!= recv_cq
)
3211 mlx5_ib_cq_clean(send_cq
, base
->mqp
.qpn
, NULL
);
3217 qp
->sq
.cur_post
= 0;
3218 qp
->sq
.last_poll
= 0;
3219 qp
->db
.db
[MLX5_RCV_DBR
] = 0;
3220 qp
->db
.db
[MLX5_SND_DBR
] = 0;
3228 static inline bool is_valid_mask(int mask
, int req
, int opt
)
3230 if ((mask
& req
) != req
)
3233 if (mask
& ~(req
| opt
))
3239 /* check valid transition for driver QP types
3240 * for now the only QP type that this function supports is DCI
3242 static bool modify_dci_qp_is_ok(enum ib_qp_state cur_state
, enum ib_qp_state new_state
,
3243 enum ib_qp_attr_mask attr_mask
)
3245 int req
= IB_QP_STATE
;
3248 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
3249 req
|= IB_QP_PKEY_INDEX
| IB_QP_PORT
;
3250 return is_valid_mask(attr_mask
, req
, opt
);
3251 } else if (cur_state
== IB_QPS_INIT
&& new_state
== IB_QPS_INIT
) {
3252 opt
= IB_QP_PKEY_INDEX
| IB_QP_PORT
;
3253 return is_valid_mask(attr_mask
, req
, opt
);
3254 } else if (cur_state
== IB_QPS_INIT
&& new_state
== IB_QPS_RTR
) {
3255 req
|= IB_QP_PATH_MTU
;
3256 opt
= IB_QP_PKEY_INDEX
;
3257 return is_valid_mask(attr_mask
, req
, opt
);
3258 } else if (cur_state
== IB_QPS_RTR
&& new_state
== IB_QPS_RTS
) {
3259 req
|= IB_QP_TIMEOUT
| IB_QP_RETRY_CNT
| IB_QP_RNR_RETRY
|
3260 IB_QP_MAX_QP_RD_ATOMIC
| IB_QP_SQ_PSN
;
3261 opt
= IB_QP_MIN_RNR_TIMER
;
3262 return is_valid_mask(attr_mask
, req
, opt
);
3263 } else if (cur_state
== IB_QPS_RTS
&& new_state
== IB_QPS_RTS
) {
3264 opt
= IB_QP_MIN_RNR_TIMER
;
3265 return is_valid_mask(attr_mask
, req
, opt
);
3266 } else if (cur_state
!= IB_QPS_RESET
&& new_state
== IB_QPS_ERR
) {
3267 return is_valid_mask(attr_mask
, req
, opt
);
3272 /* mlx5_ib_modify_dct: modify a DCT QP
3273 * valid transitions are:
3274 * RESET to INIT: must set access_flags, pkey_index and port
3275 * INIT to RTR : must set min_rnr_timer, tclass, flow_label,
3276 * mtu, gid_index and hop_limit
3277 * Other transitions and attributes are illegal
3279 static int mlx5_ib_modify_dct(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
3280 int attr_mask
, struct ib_udata
*udata
)
3282 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
3283 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3284 enum ib_qp_state cur_state
, new_state
;
3286 int required
= IB_QP_STATE
;
3289 if (!(attr_mask
& IB_QP_STATE
))
3292 cur_state
= qp
->state
;
3293 new_state
= attr
->qp_state
;
3295 dctc
= MLX5_ADDR_OF(create_dct_in
, qp
->dct
.in
, dct_context_entry
);
3296 if (cur_state
== IB_QPS_RESET
&& new_state
== IB_QPS_INIT
) {
3297 required
|= IB_QP_ACCESS_FLAGS
| IB_QP_PKEY_INDEX
| IB_QP_PORT
;
3298 if (!is_valid_mask(attr_mask
, required
, 0))
3301 if (attr
->port_num
== 0 ||
3302 attr
->port_num
> MLX5_CAP_GEN(dev
->mdev
, num_ports
)) {
3303 mlx5_ib_dbg(dev
, "invalid port number %d. number of ports is %d\n",
3304 attr
->port_num
, dev
->num_ports
);
3307 if (attr
->qp_access_flags
& IB_ACCESS_REMOTE_READ
)
3308 MLX5_SET(dctc
, dctc
, rre
, 1);
3309 if (attr
->qp_access_flags
& IB_ACCESS_REMOTE_WRITE
)
3310 MLX5_SET(dctc
, dctc
, rwe
, 1);
3311 if (attr
->qp_access_flags
& IB_ACCESS_REMOTE_ATOMIC
) {
3312 if (!mlx5_ib_dc_atomic_is_supported(dev
))
3314 MLX5_SET(dctc
, dctc
, rae
, 1);
3315 MLX5_SET(dctc
, dctc
, atomic_mode
, MLX5_ATOMIC_MODE_DCT_CX
);
3317 MLX5_SET(dctc
, dctc
, pkey_index
, attr
->pkey_index
);
3318 MLX5_SET(dctc
, dctc
, port
, attr
->port_num
);
3319 MLX5_SET(dctc
, dctc
, counter_set_id
, dev
->port
[attr
->port_num
- 1].cnts
.set_id
);
3321 } else if (cur_state
== IB_QPS_INIT
&& new_state
== IB_QPS_RTR
) {
3322 struct mlx5_ib_modify_qp_resp resp
= {};
3323 u32 min_resp_len
= offsetof(typeof(resp
), dctn
) +
3326 if (udata
->outlen
< min_resp_len
)
3328 resp
.response_length
= min_resp_len
;
3330 required
|= IB_QP_MIN_RNR_TIMER
| IB_QP_AV
| IB_QP_PATH_MTU
;
3331 if (!is_valid_mask(attr_mask
, required
, 0))
3333 MLX5_SET(dctc
, dctc
, min_rnr_nak
, attr
->min_rnr_timer
);
3334 MLX5_SET(dctc
, dctc
, tclass
, attr
->ah_attr
.grh
.traffic_class
);
3335 MLX5_SET(dctc
, dctc
, flow_label
, attr
->ah_attr
.grh
.flow_label
);
3336 MLX5_SET(dctc
, dctc
, mtu
, attr
->path_mtu
);
3337 MLX5_SET(dctc
, dctc
, my_addr_index
, attr
->ah_attr
.grh
.sgid_index
);
3338 MLX5_SET(dctc
, dctc
, hop_limit
, attr
->ah_attr
.grh
.hop_limit
);
3340 err
= mlx5_core_create_dct(dev
->mdev
, &qp
->dct
.mdct
, qp
->dct
.in
,
3341 MLX5_ST_SZ_BYTES(create_dct_in
));
3344 resp
.dctn
= qp
->dct
.mdct
.mqp
.qpn
;
3345 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
3347 mlx5_core_destroy_dct(dev
->mdev
, &qp
->dct
.mdct
);
3351 mlx5_ib_warn(dev
, "Modify DCT: Invalid transition from %d to %d\n", cur_state
, new_state
);
3355 qp
->state
= IB_QPS_ERR
;
3357 qp
->state
= new_state
;
3361 int mlx5_ib_modify_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*attr
,
3362 int attr_mask
, struct ib_udata
*udata
)
3364 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
3365 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
3366 struct mlx5_ib_modify_qp ucmd
= {};
3367 enum ib_qp_type qp_type
;
3368 enum ib_qp_state cur_state
, new_state
;
3369 size_t required_cmd_sz
;
3372 enum rdma_link_layer ll
= IB_LINK_LAYER_UNSPECIFIED
;
3374 if (ibqp
->rwq_ind_tbl
)
3377 if (udata
&& udata
->inlen
) {
3378 required_cmd_sz
= offsetof(typeof(ucmd
), reserved
) +
3379 sizeof(ucmd
.reserved
);
3380 if (udata
->inlen
< required_cmd_sz
)
3383 if (udata
->inlen
> sizeof(ucmd
) &&
3384 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
3385 udata
->inlen
- sizeof(ucmd
)))
3388 if (ib_copy_from_udata(&ucmd
, udata
,
3389 min(udata
->inlen
, sizeof(ucmd
))))
3392 if (ucmd
.comp_mask
||
3393 memchr_inv(&ucmd
.reserved
, 0, sizeof(ucmd
.reserved
)) ||
3394 memchr_inv(&ucmd
.burst_info
.reserved
, 0,
3395 sizeof(ucmd
.burst_info
.reserved
)))
3399 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
3400 return mlx5_ib_gsi_modify_qp(ibqp
, attr
, attr_mask
);
3402 if (ibqp
->qp_type
== IB_QPT_DRIVER
)
3403 qp_type
= qp
->qp_sub_type
;
3405 qp_type
= (unlikely(ibqp
->qp_type
== MLX5_IB_QPT_HW_GSI
)) ?
3406 IB_QPT_GSI
: ibqp
->qp_type
;
3408 if (qp_type
== MLX5_IB_QPT_DCT
)
3409 return mlx5_ib_modify_dct(ibqp
, attr
, attr_mask
, udata
);
3411 mutex_lock(&qp
->mutex
);
3413 cur_state
= attr_mask
& IB_QP_CUR_STATE
? attr
->cur_qp_state
: qp
->state
;
3414 new_state
= attr_mask
& IB_QP_STATE
? attr
->qp_state
: cur_state
;
3416 if (!(cur_state
== new_state
&& cur_state
== IB_QPS_RESET
)) {
3417 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
3418 ll
= dev
->ib_dev
.get_link_layer(&dev
->ib_dev
, port
);
3421 if (qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
3422 if (attr_mask
& ~(IB_QP_STATE
| IB_QP_CUR_STATE
)) {
3423 mlx5_ib_dbg(dev
, "invalid attr_mask 0x%x when underlay QP is used\n",
3427 } else if (qp_type
!= MLX5_IB_QPT_REG_UMR
&&
3428 qp_type
!= MLX5_IB_QPT_DCI
&&
3429 !ib_modify_qp_is_ok(cur_state
, new_state
, qp_type
, attr_mask
, ll
)) {
3430 mlx5_ib_dbg(dev
, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3431 cur_state
, new_state
, ibqp
->qp_type
, attr_mask
);
3433 } else if (qp_type
== MLX5_IB_QPT_DCI
&&
3434 !modify_dci_qp_is_ok(cur_state
, new_state
, attr_mask
)) {
3435 mlx5_ib_dbg(dev
, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
3436 cur_state
, new_state
, qp_type
, attr_mask
);
3440 if ((attr_mask
& IB_QP_PORT
) &&
3441 (attr
->port_num
== 0 ||
3442 attr
->port_num
> dev
->num_ports
)) {
3443 mlx5_ib_dbg(dev
, "invalid port number %d. number of ports is %d\n",
3444 attr
->port_num
, dev
->num_ports
);
3448 if (attr_mask
& IB_QP_PKEY_INDEX
) {
3449 port
= attr_mask
& IB_QP_PORT
? attr
->port_num
: qp
->port
;
3450 if (attr
->pkey_index
>=
3451 dev
->mdev
->port_caps
[port
- 1].pkey_table_len
) {
3452 mlx5_ib_dbg(dev
, "invalid pkey index %d\n",
3458 if (attr_mask
& IB_QP_MAX_QP_RD_ATOMIC
&&
3459 attr
->max_rd_atomic
>
3460 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_res_qp
))) {
3461 mlx5_ib_dbg(dev
, "invalid max_rd_atomic value %d\n",
3462 attr
->max_rd_atomic
);
3466 if (attr_mask
& IB_QP_MAX_DEST_RD_ATOMIC
&&
3467 attr
->max_dest_rd_atomic
>
3468 (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_ra_req_qp
))) {
3469 mlx5_ib_dbg(dev
, "invalid max_dest_rd_atomic value %d\n",
3470 attr
->max_dest_rd_atomic
);
3474 if (cur_state
== new_state
&& cur_state
== IB_QPS_RESET
) {
3479 err
= __mlx5_ib_modify_qp(ibqp
, attr
, attr_mask
, cur_state
,
3483 mutex_unlock(&qp
->mutex
);
3487 static int mlx5_wq_overflow(struct mlx5_ib_wq
*wq
, int nreq
, struct ib_cq
*ib_cq
)
3489 struct mlx5_ib_cq
*cq
;
3492 cur
= wq
->head
- wq
->tail
;
3493 if (likely(cur
+ nreq
< wq
->max_post
))
3497 spin_lock(&cq
->lock
);
3498 cur
= wq
->head
- wq
->tail
;
3499 spin_unlock(&cq
->lock
);
3501 return cur
+ nreq
>= wq
->max_post
;
3504 static __always_inline
void set_raddr_seg(struct mlx5_wqe_raddr_seg
*rseg
,
3505 u64 remote_addr
, u32 rkey
)
3507 rseg
->raddr
= cpu_to_be64(remote_addr
);
3508 rseg
->rkey
= cpu_to_be32(rkey
);
3512 static void *set_eth_seg(struct mlx5_wqe_eth_seg
*eseg
,
3513 struct ib_send_wr
*wr
, void *qend
,
3514 struct mlx5_ib_qp
*qp
, int *size
)
3518 memset(eseg
, 0, sizeof(struct mlx5_wqe_eth_seg
));
3520 if (wr
->send_flags
& IB_SEND_IP_CSUM
)
3521 eseg
->cs_flags
= MLX5_ETH_WQE_L3_CSUM
|
3522 MLX5_ETH_WQE_L4_CSUM
;
3524 seg
+= sizeof(struct mlx5_wqe_eth_seg
);
3525 *size
+= sizeof(struct mlx5_wqe_eth_seg
) / 16;
3527 if (wr
->opcode
== IB_WR_LSO
) {
3528 struct ib_ud_wr
*ud_wr
= container_of(wr
, struct ib_ud_wr
, wr
);
3529 int size_of_inl_hdr_start
= sizeof(eseg
->inline_hdr
.start
);
3530 u64 left
, leftlen
, copysz
;
3531 void *pdata
= ud_wr
->header
;
3534 eseg
->mss
= cpu_to_be16(ud_wr
->mss
);
3535 eseg
->inline_hdr
.sz
= cpu_to_be16(left
);
3538 * check if there is space till the end of queue, if yes,
3539 * copy all in one shot, otherwise copy till the end of queue,
3540 * rollback and than the copy the left
3542 leftlen
= qend
- (void *)eseg
->inline_hdr
.start
;
3543 copysz
= min_t(u64
, leftlen
, left
);
3545 memcpy(seg
- size_of_inl_hdr_start
, pdata
, copysz
);
3547 if (likely(copysz
> size_of_inl_hdr_start
)) {
3548 seg
+= ALIGN(copysz
- size_of_inl_hdr_start
, 16);
3549 *size
+= ALIGN(copysz
- size_of_inl_hdr_start
, 16) / 16;
3552 if (unlikely(copysz
< left
)) { /* the last wqe in the queue */
3553 seg
= mlx5_get_send_wqe(qp
, 0);
3556 memcpy(seg
, pdata
, left
);
3557 seg
+= ALIGN(left
, 16);
3558 *size
+= ALIGN(left
, 16) / 16;
3565 static void set_datagram_seg(struct mlx5_wqe_datagram_seg
*dseg
,
3566 struct ib_send_wr
*wr
)
3568 memcpy(&dseg
->av
, &to_mah(ud_wr(wr
)->ah
)->av
, sizeof(struct mlx5_av
));
3569 dseg
->av
.dqp_dct
= cpu_to_be32(ud_wr(wr
)->remote_qpn
| MLX5_EXTENDED_UD_AV
);
3570 dseg
->av
.key
.qkey
.qkey
= cpu_to_be32(ud_wr(wr
)->remote_qkey
);
3573 static void set_data_ptr_seg(struct mlx5_wqe_data_seg
*dseg
, struct ib_sge
*sg
)
3575 dseg
->byte_count
= cpu_to_be32(sg
->length
);
3576 dseg
->lkey
= cpu_to_be32(sg
->lkey
);
3577 dseg
->addr
= cpu_to_be64(sg
->addr
);
3580 static u64
get_xlt_octo(u64 bytes
)
3582 return ALIGN(bytes
, MLX5_IB_UMR_XLT_ALIGNMENT
) /
3583 MLX5_IB_UMR_OCTOWORD
;
3586 static __be64
frwr_mkey_mask(void)
3590 result
= MLX5_MKEY_MASK_LEN
|
3591 MLX5_MKEY_MASK_PAGE_SIZE
|
3592 MLX5_MKEY_MASK_START_ADDR
|
3593 MLX5_MKEY_MASK_EN_RINVAL
|
3594 MLX5_MKEY_MASK_KEY
|
3600 MLX5_MKEY_MASK_SMALL_FENCE
|
3601 MLX5_MKEY_MASK_FREE
;
3603 return cpu_to_be64(result
);
3606 static __be64
sig_mkey_mask(void)
3610 result
= MLX5_MKEY_MASK_LEN
|
3611 MLX5_MKEY_MASK_PAGE_SIZE
|
3612 MLX5_MKEY_MASK_START_ADDR
|
3613 MLX5_MKEY_MASK_EN_SIGERR
|
3614 MLX5_MKEY_MASK_EN_RINVAL
|
3615 MLX5_MKEY_MASK_KEY
|
3620 MLX5_MKEY_MASK_SMALL_FENCE
|
3621 MLX5_MKEY_MASK_FREE
|
3622 MLX5_MKEY_MASK_BSF_EN
;
3624 return cpu_to_be64(result
);
3627 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
,
3628 struct mlx5_ib_mr
*mr
)
3630 int size
= mr
->ndescs
* mr
->desc_size
;
3632 memset(umr
, 0, sizeof(*umr
));
3634 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
;
3635 umr
->xlt_octowords
= cpu_to_be16(get_xlt_octo(size
));
3636 umr
->mkey_mask
= frwr_mkey_mask();
3639 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg
*umr
)
3641 memset(umr
, 0, sizeof(*umr
));
3642 umr
->mkey_mask
= cpu_to_be64(MLX5_MKEY_MASK_FREE
);
3643 umr
->flags
= MLX5_UMR_INLINE
;
3646 static __be64
get_umr_enable_mr_mask(void)
3650 result
= MLX5_MKEY_MASK_KEY
|
3651 MLX5_MKEY_MASK_FREE
;
3653 return cpu_to_be64(result
);
3656 static __be64
get_umr_disable_mr_mask(void)
3660 result
= MLX5_MKEY_MASK_FREE
;
3662 return cpu_to_be64(result
);
3665 static __be64
get_umr_update_translation_mask(void)
3669 result
= MLX5_MKEY_MASK_LEN
|
3670 MLX5_MKEY_MASK_PAGE_SIZE
|
3671 MLX5_MKEY_MASK_START_ADDR
;
3673 return cpu_to_be64(result
);
3676 static __be64
get_umr_update_access_mask(int atomic
)
3680 result
= MLX5_MKEY_MASK_LR
|
3686 result
|= MLX5_MKEY_MASK_A
;
3688 return cpu_to_be64(result
);
3691 static __be64
get_umr_update_pd_mask(void)
3695 result
= MLX5_MKEY_MASK_PD
;
3697 return cpu_to_be64(result
);
3700 static int umr_check_mkey_mask(struct mlx5_ib_dev
*dev
, u64 mask
)
3702 if ((mask
& MLX5_MKEY_MASK_PAGE_SIZE
&&
3703 MLX5_CAP_GEN(dev
->mdev
, umr_modify_entity_size_disabled
)) ||
3704 (mask
& MLX5_MKEY_MASK_A
&&
3705 MLX5_CAP_GEN(dev
->mdev
, umr_modify_atomic_disabled
)))
3710 static int set_reg_umr_segment(struct mlx5_ib_dev
*dev
,
3711 struct mlx5_wqe_umr_ctrl_seg
*umr
,
3712 struct ib_send_wr
*wr
, int atomic
)
3714 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
3716 memset(umr
, 0, sizeof(*umr
));
3718 if (wr
->send_flags
& MLX5_IB_SEND_UMR_FAIL_IF_FREE
)
3719 umr
->flags
= MLX5_UMR_CHECK_FREE
; /* fail if free */
3721 umr
->flags
= MLX5_UMR_CHECK_NOT_FREE
; /* fail if not free */
3723 umr
->xlt_octowords
= cpu_to_be16(get_xlt_octo(umrwr
->xlt_size
));
3724 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_XLT
) {
3725 u64 offset
= get_xlt_octo(umrwr
->offset
);
3727 umr
->xlt_offset
= cpu_to_be16(offset
& 0xffff);
3728 umr
->xlt_offset_47_16
= cpu_to_be32(offset
>> 16);
3729 umr
->flags
|= MLX5_UMR_TRANSLATION_OFFSET_EN
;
3731 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
)
3732 umr
->mkey_mask
|= get_umr_update_translation_mask();
3733 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_PD_ACCESS
) {
3734 umr
->mkey_mask
|= get_umr_update_access_mask(atomic
);
3735 umr
->mkey_mask
|= get_umr_update_pd_mask();
3737 if (wr
->send_flags
& MLX5_IB_SEND_UMR_ENABLE_MR
)
3738 umr
->mkey_mask
|= get_umr_enable_mr_mask();
3739 if (wr
->send_flags
& MLX5_IB_SEND_UMR_DISABLE_MR
)
3740 umr
->mkey_mask
|= get_umr_disable_mr_mask();
3743 umr
->flags
|= MLX5_UMR_INLINE
;
3745 return umr_check_mkey_mask(dev
, be64_to_cpu(umr
->mkey_mask
));
3748 static u8
get_umr_flags(int acc
)
3750 return (acc
& IB_ACCESS_REMOTE_ATOMIC
? MLX5_PERM_ATOMIC
: 0) |
3751 (acc
& IB_ACCESS_REMOTE_WRITE
? MLX5_PERM_REMOTE_WRITE
: 0) |
3752 (acc
& IB_ACCESS_REMOTE_READ
? MLX5_PERM_REMOTE_READ
: 0) |
3753 (acc
& IB_ACCESS_LOCAL_WRITE
? MLX5_PERM_LOCAL_WRITE
: 0) |
3754 MLX5_PERM_LOCAL_READ
| MLX5_PERM_UMR_EN
;
3757 static void set_reg_mkey_seg(struct mlx5_mkey_seg
*seg
,
3758 struct mlx5_ib_mr
*mr
,
3759 u32 key
, int access
)
3761 int ndescs
= ALIGN(mr
->ndescs
, 8) >> 1;
3763 memset(seg
, 0, sizeof(*seg
));
3765 if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_MTT
)
3766 seg
->log2_page_size
= ilog2(mr
->ibmr
.page_size
);
3767 else if (mr
->access_mode
== MLX5_MKC_ACCESS_MODE_KLMS
)
3768 /* KLMs take twice the size of MTTs */
3771 seg
->flags
= get_umr_flags(access
) | mr
->access_mode
;
3772 seg
->qpn_mkey7_0
= cpu_to_be32((key
& 0xff) | 0xffffff00);
3773 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
);
3774 seg
->start_addr
= cpu_to_be64(mr
->ibmr
.iova
);
3775 seg
->len
= cpu_to_be64(mr
->ibmr
.length
);
3776 seg
->xlt_oct_size
= cpu_to_be32(ndescs
);
3779 static void set_linv_mkey_seg(struct mlx5_mkey_seg
*seg
)
3781 memset(seg
, 0, sizeof(*seg
));
3782 seg
->status
= MLX5_MKEY_STATUS_FREE
;
3785 static void set_reg_mkey_segment(struct mlx5_mkey_seg
*seg
, struct ib_send_wr
*wr
)
3787 struct mlx5_umr_wr
*umrwr
= umr_wr(wr
);
3789 memset(seg
, 0, sizeof(*seg
));
3790 if (wr
->send_flags
& MLX5_IB_SEND_UMR_DISABLE_MR
)
3791 seg
->status
= MLX5_MKEY_STATUS_FREE
;
3793 seg
->flags
= convert_access(umrwr
->access_flags
);
3795 seg
->flags_pd
= cpu_to_be32(to_mpd(umrwr
->pd
)->pdn
);
3796 if (wr
->send_flags
& MLX5_IB_SEND_UMR_UPDATE_TRANSLATION
&&
3798 seg
->flags_pd
|= cpu_to_be32(MLX5_MKEY_LEN64
);
3800 seg
->start_addr
= cpu_to_be64(umrwr
->virt_addr
);
3801 seg
->len
= cpu_to_be64(umrwr
->length
);
3802 seg
->log2_page_size
= umrwr
->page_shift
;
3803 seg
->qpn_mkey7_0
= cpu_to_be32(0xffffff00 |
3804 mlx5_mkey_variant(umrwr
->mkey
));
3807 static void set_reg_data_seg(struct mlx5_wqe_data_seg
*dseg
,
3808 struct mlx5_ib_mr
*mr
,
3809 struct mlx5_ib_pd
*pd
)
3811 int bcount
= mr
->desc_size
* mr
->ndescs
;
3813 dseg
->addr
= cpu_to_be64(mr
->desc_map
);
3814 dseg
->byte_count
= cpu_to_be32(ALIGN(bcount
, 64));
3815 dseg
->lkey
= cpu_to_be32(pd
->ibpd
.local_dma_lkey
);
3818 static __be32
send_ieth(struct ib_send_wr
*wr
)
3820 switch (wr
->opcode
) {
3821 case IB_WR_SEND_WITH_IMM
:
3822 case IB_WR_RDMA_WRITE_WITH_IMM
:
3823 return wr
->ex
.imm_data
;
3825 case IB_WR_SEND_WITH_INV
:
3826 return cpu_to_be32(wr
->ex
.invalidate_rkey
);
3833 static u8
calc_sig(void *wqe
, int size
)
3839 for (i
= 0; i
< size
; i
++)
3845 static u8
wq_sig(void *wqe
)
3847 return calc_sig(wqe
, (*((u8
*)wqe
+ 8) & 0x3f) << 4);
3850 static int set_data_inl_seg(struct mlx5_ib_qp
*qp
, struct ib_send_wr
*wr
,
3853 struct mlx5_wqe_inline_seg
*seg
;
3854 void *qend
= qp
->sq
.qend
;
3862 wqe
+= sizeof(*seg
);
3863 for (i
= 0; i
< wr
->num_sge
; i
++) {
3864 addr
= (void *)(unsigned long)(wr
->sg_list
[i
].addr
);
3865 len
= wr
->sg_list
[i
].length
;
3868 if (unlikely(inl
> qp
->max_inline_data
))
3871 if (unlikely(wqe
+ len
> qend
)) {
3873 memcpy(wqe
, addr
, copy
);
3876 wqe
= mlx5_get_send_wqe(qp
, 0);
3878 memcpy(wqe
, addr
, len
);
3882 seg
->byte_count
= cpu_to_be32(inl
| MLX5_INLINE_SEG
);
3884 *sz
= ALIGN(inl
+ sizeof(seg
->byte_count
), 16) / 16;
3889 static u16
prot_field_size(enum ib_signature_type type
)
3892 case IB_SIG_TYPE_T10_DIF
:
3893 return MLX5_DIF_SIZE
;
3899 static u8
bs_selector(int block_size
)
3901 switch (block_size
) {
3902 case 512: return 0x1;
3903 case 520: return 0x2;
3904 case 4096: return 0x3;
3905 case 4160: return 0x4;
3906 case 1073741824: return 0x5;
3911 static void mlx5_fill_inl_bsf(struct ib_sig_domain
*domain
,
3912 struct mlx5_bsf_inl
*inl
)
3914 /* Valid inline section and allow BSF refresh */
3915 inl
->vld_refresh
= cpu_to_be16(MLX5_BSF_INL_VALID
|
3916 MLX5_BSF_REFRESH_DIF
);
3917 inl
->dif_apptag
= cpu_to_be16(domain
->sig
.dif
.app_tag
);
3918 inl
->dif_reftag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
3919 /* repeating block */
3920 inl
->rp_inv_seed
= MLX5_BSF_REPEAT_BLOCK
;
3921 inl
->sig_type
= domain
->sig
.dif
.bg_type
== IB_T10DIF_CRC
?
3922 MLX5_DIF_CRC
: MLX5_DIF_IPCS
;
3924 if (domain
->sig
.dif
.ref_remap
)
3925 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_INC_REFTAG
;
3927 if (domain
->sig
.dif
.app_escape
) {
3928 if (domain
->sig
.dif
.ref_escape
)
3929 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPREF_ESCAPE
;
3931 inl
->dif_inc_ref_guard_check
|= MLX5_BSF_APPTAG_ESCAPE
;
3934 inl
->dif_app_bitmask_check
=
3935 cpu_to_be16(domain
->sig
.dif
.apptag_check_mask
);
3938 static int mlx5_set_bsf(struct ib_mr
*sig_mr
,
3939 struct ib_sig_attrs
*sig_attrs
,
3940 struct mlx5_bsf
*bsf
, u32 data_size
)
3942 struct mlx5_core_sig_ctx
*msig
= to_mmr(sig_mr
)->sig
;
3943 struct mlx5_bsf_basic
*basic
= &bsf
->basic
;
3944 struct ib_sig_domain
*mem
= &sig_attrs
->mem
;
3945 struct ib_sig_domain
*wire
= &sig_attrs
->wire
;
3947 memset(bsf
, 0, sizeof(*bsf
));
3949 /* Basic + Extended + Inline */
3950 basic
->bsf_size_sbs
= 1 << 7;
3951 /* Input domain check byte mask */
3952 basic
->check_byte_mask
= sig_attrs
->check_mask
;
3953 basic
->raw_data_size
= cpu_to_be32(data_size
);
3956 switch (sig_attrs
->mem
.sig_type
) {
3957 case IB_SIG_TYPE_NONE
:
3959 case IB_SIG_TYPE_T10_DIF
:
3960 basic
->mem
.bs_selector
= bs_selector(mem
->sig
.dif
.pi_interval
);
3961 basic
->m_bfs_psv
= cpu_to_be32(msig
->psv_memory
.psv_idx
);
3962 mlx5_fill_inl_bsf(mem
, &bsf
->m_inl
);
3969 switch (sig_attrs
->wire
.sig_type
) {
3970 case IB_SIG_TYPE_NONE
:
3972 case IB_SIG_TYPE_T10_DIF
:
3973 if (mem
->sig
.dif
.pi_interval
== wire
->sig
.dif
.pi_interval
&&
3974 mem
->sig_type
== wire
->sig_type
) {
3975 /* Same block structure */
3976 basic
->bsf_size_sbs
|= 1 << 4;
3977 if (mem
->sig
.dif
.bg_type
== wire
->sig
.dif
.bg_type
)
3978 basic
->wire
.copy_byte_mask
|= MLX5_CPY_GRD_MASK
;
3979 if (mem
->sig
.dif
.app_tag
== wire
->sig
.dif
.app_tag
)
3980 basic
->wire
.copy_byte_mask
|= MLX5_CPY_APP_MASK
;
3981 if (mem
->sig
.dif
.ref_tag
== wire
->sig
.dif
.ref_tag
)
3982 basic
->wire
.copy_byte_mask
|= MLX5_CPY_REF_MASK
;
3984 basic
->wire
.bs_selector
= bs_selector(wire
->sig
.dif
.pi_interval
);
3986 basic
->w_bfs_psv
= cpu_to_be32(msig
->psv_wire
.psv_idx
);
3987 mlx5_fill_inl_bsf(wire
, &bsf
->w_inl
);
3996 static int set_sig_data_segment(struct ib_sig_handover_wr
*wr
,
3997 struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
3999 struct ib_sig_attrs
*sig_attrs
= wr
->sig_attrs
;
4000 struct ib_mr
*sig_mr
= wr
->sig_mr
;
4001 struct mlx5_bsf
*bsf
;
4002 u32 data_len
= wr
->wr
.sg_list
->length
;
4003 u32 data_key
= wr
->wr
.sg_list
->lkey
;
4004 u64 data_va
= wr
->wr
.sg_list
->addr
;
4009 (data_key
== wr
->prot
->lkey
&&
4010 data_va
== wr
->prot
->addr
&&
4011 data_len
== wr
->prot
->length
)) {
4013 * Source domain doesn't contain signature information
4014 * or data and protection are interleaved in memory.
4015 * So need construct:
4016 * ------------------
4018 * ------------------
4020 * ------------------
4022 struct mlx5_klm
*data_klm
= *seg
;
4024 data_klm
->bcount
= cpu_to_be32(data_len
);
4025 data_klm
->key
= cpu_to_be32(data_key
);
4026 data_klm
->va
= cpu_to_be64(data_va
);
4027 wqe_size
= ALIGN(sizeof(*data_klm
), 64);
4030 * Source domain contains signature information
4031 * So need construct a strided block format:
4032 * ---------------------------
4033 * | stride_block_ctrl |
4034 * ---------------------------
4036 * ---------------------------
4038 * ---------------------------
4040 * ---------------------------
4042 struct mlx5_stride_block_ctrl_seg
*sblock_ctrl
;
4043 struct mlx5_stride_block_entry
*data_sentry
;
4044 struct mlx5_stride_block_entry
*prot_sentry
;
4045 u32 prot_key
= wr
->prot
->lkey
;
4046 u64 prot_va
= wr
->prot
->addr
;
4047 u16 block_size
= sig_attrs
->mem
.sig
.dif
.pi_interval
;
4051 data_sentry
= (void *)sblock_ctrl
+ sizeof(*sblock_ctrl
);
4052 prot_sentry
= (void *)data_sentry
+ sizeof(*data_sentry
);
4054 prot_size
= prot_field_size(sig_attrs
->mem
.sig_type
);
4056 pr_err("Bad block size given: %u\n", block_size
);
4059 sblock_ctrl
->bcount_per_cycle
= cpu_to_be32(block_size
+
4061 sblock_ctrl
->op
= cpu_to_be32(MLX5_STRIDE_BLOCK_OP
);
4062 sblock_ctrl
->repeat_count
= cpu_to_be32(data_len
/ block_size
);
4063 sblock_ctrl
->num_entries
= cpu_to_be16(2);
4065 data_sentry
->bcount
= cpu_to_be16(block_size
);
4066 data_sentry
->key
= cpu_to_be32(data_key
);
4067 data_sentry
->va
= cpu_to_be64(data_va
);
4068 data_sentry
->stride
= cpu_to_be16(block_size
);
4070 prot_sentry
->bcount
= cpu_to_be16(prot_size
);
4071 prot_sentry
->key
= cpu_to_be32(prot_key
);
4072 prot_sentry
->va
= cpu_to_be64(prot_va
);
4073 prot_sentry
->stride
= cpu_to_be16(prot_size
);
4075 wqe_size
= ALIGN(sizeof(*sblock_ctrl
) + sizeof(*data_sentry
) +
4076 sizeof(*prot_sentry
), 64);
4080 *size
+= wqe_size
/ 16;
4081 if (unlikely((*seg
== qp
->sq
.qend
)))
4082 *seg
= mlx5_get_send_wqe(qp
, 0);
4085 ret
= mlx5_set_bsf(sig_mr
, sig_attrs
, bsf
, data_len
);
4089 *seg
+= sizeof(*bsf
);
4090 *size
+= sizeof(*bsf
) / 16;
4091 if (unlikely((*seg
== qp
->sq
.qend
)))
4092 *seg
= mlx5_get_send_wqe(qp
, 0);
4097 static void set_sig_mkey_segment(struct mlx5_mkey_seg
*seg
,
4098 struct ib_sig_handover_wr
*wr
, u32 size
,
4099 u32 length
, u32 pdn
)
4101 struct ib_mr
*sig_mr
= wr
->sig_mr
;
4102 u32 sig_key
= sig_mr
->rkey
;
4103 u8 sigerr
= to_mmr(sig_mr
)->sig
->sigerr_count
& 1;
4105 memset(seg
, 0, sizeof(*seg
));
4107 seg
->flags
= get_umr_flags(wr
->access_flags
) |
4108 MLX5_MKC_ACCESS_MODE_KLMS
;
4109 seg
->qpn_mkey7_0
= cpu_to_be32((sig_key
& 0xff) | 0xffffff00);
4110 seg
->flags_pd
= cpu_to_be32(MLX5_MKEY_REMOTE_INVAL
| sigerr
<< 26 |
4111 MLX5_MKEY_BSF_EN
| pdn
);
4112 seg
->len
= cpu_to_be64(length
);
4113 seg
->xlt_oct_size
= cpu_to_be32(get_xlt_octo(size
));
4114 seg
->bsfs_octo_size
= cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE
);
4117 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg
*umr
,
4120 memset(umr
, 0, sizeof(*umr
));
4122 umr
->flags
= MLX5_FLAGS_INLINE
| MLX5_FLAGS_CHECK_FREE
;
4123 umr
->xlt_octowords
= cpu_to_be16(get_xlt_octo(size
));
4124 umr
->bsf_octowords
= cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE
);
4125 umr
->mkey_mask
= sig_mkey_mask();
4129 static int set_sig_umr_wr(struct ib_send_wr
*send_wr
, struct mlx5_ib_qp
*qp
,
4130 void **seg
, int *size
)
4132 struct ib_sig_handover_wr
*wr
= sig_handover_wr(send_wr
);
4133 struct mlx5_ib_mr
*sig_mr
= to_mmr(wr
->sig_mr
);
4134 u32 pdn
= get_pd(qp
)->pdn
;
4136 int region_len
, ret
;
4138 if (unlikely(wr
->wr
.num_sge
!= 1) ||
4139 unlikely(wr
->access_flags
& IB_ACCESS_REMOTE_ATOMIC
) ||
4140 unlikely(!sig_mr
->sig
) || unlikely(!qp
->signature_en
) ||
4141 unlikely(!sig_mr
->sig
->sig_status_checked
))
4144 /* length of the protected region, data + protection */
4145 region_len
= wr
->wr
.sg_list
->length
;
4147 (wr
->prot
->lkey
!= wr
->wr
.sg_list
->lkey
||
4148 wr
->prot
->addr
!= wr
->wr
.sg_list
->addr
||
4149 wr
->prot
->length
!= wr
->wr
.sg_list
->length
))
4150 region_len
+= wr
->prot
->length
;
4153 * KLM octoword size - if protection was provided
4154 * then we use strided block format (3 octowords),
4155 * else we use single KLM (1 octoword)
4157 xlt_size
= wr
->prot
? 0x30 : sizeof(struct mlx5_klm
);
4159 set_sig_umr_segment(*seg
, xlt_size
);
4160 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
4161 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
4162 if (unlikely((*seg
== qp
->sq
.qend
)))
4163 *seg
= mlx5_get_send_wqe(qp
, 0);
4165 set_sig_mkey_segment(*seg
, wr
, xlt_size
, region_len
, pdn
);
4166 *seg
+= sizeof(struct mlx5_mkey_seg
);
4167 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
4168 if (unlikely((*seg
== qp
->sq
.qend
)))
4169 *seg
= mlx5_get_send_wqe(qp
, 0);
4171 ret
= set_sig_data_segment(wr
, qp
, seg
, size
);
4175 sig_mr
->sig
->sig_status_checked
= false;
4179 static int set_psv_wr(struct ib_sig_domain
*domain
,
4180 u32 psv_idx
, void **seg
, int *size
)
4182 struct mlx5_seg_set_psv
*psv_seg
= *seg
;
4184 memset(psv_seg
, 0, sizeof(*psv_seg
));
4185 psv_seg
->psv_num
= cpu_to_be32(psv_idx
);
4186 switch (domain
->sig_type
) {
4187 case IB_SIG_TYPE_NONE
:
4189 case IB_SIG_TYPE_T10_DIF
:
4190 psv_seg
->transient_sig
= cpu_to_be32(domain
->sig
.dif
.bg
<< 16 |
4191 domain
->sig
.dif
.app_tag
);
4192 psv_seg
->ref_tag
= cpu_to_be32(domain
->sig
.dif
.ref_tag
);
4195 pr_err("Bad signature type (%d) is given.\n",
4200 *seg
+= sizeof(*psv_seg
);
4201 *size
+= sizeof(*psv_seg
) / 16;
4206 static int set_reg_wr(struct mlx5_ib_qp
*qp
,
4207 struct ib_reg_wr
*wr
,
4208 void **seg
, int *size
)
4210 struct mlx5_ib_mr
*mr
= to_mmr(wr
->mr
);
4211 struct mlx5_ib_pd
*pd
= to_mpd(qp
->ibqp
.pd
);
4213 if (unlikely(wr
->wr
.send_flags
& IB_SEND_INLINE
)) {
4214 mlx5_ib_warn(to_mdev(qp
->ibqp
.device
),
4215 "Invalid IB_SEND_INLINE send flag\n");
4219 set_reg_umr_seg(*seg
, mr
);
4220 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
4221 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
4222 if (unlikely((*seg
== qp
->sq
.qend
)))
4223 *seg
= mlx5_get_send_wqe(qp
, 0);
4225 set_reg_mkey_seg(*seg
, mr
, wr
->key
, wr
->access
);
4226 *seg
+= sizeof(struct mlx5_mkey_seg
);
4227 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
4228 if (unlikely((*seg
== qp
->sq
.qend
)))
4229 *seg
= mlx5_get_send_wqe(qp
, 0);
4231 set_reg_data_seg(*seg
, mr
, pd
);
4232 *seg
+= sizeof(struct mlx5_wqe_data_seg
);
4233 *size
+= (sizeof(struct mlx5_wqe_data_seg
) / 16);
4238 static void set_linv_wr(struct mlx5_ib_qp
*qp
, void **seg
, int *size
)
4240 set_linv_umr_seg(*seg
);
4241 *seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
4242 *size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
4243 if (unlikely((*seg
== qp
->sq
.qend
)))
4244 *seg
= mlx5_get_send_wqe(qp
, 0);
4245 set_linv_mkey_seg(*seg
);
4246 *seg
+= sizeof(struct mlx5_mkey_seg
);
4247 *size
+= sizeof(struct mlx5_mkey_seg
) / 16;
4248 if (unlikely((*seg
== qp
->sq
.qend
)))
4249 *seg
= mlx5_get_send_wqe(qp
, 0);
4252 static void dump_wqe(struct mlx5_ib_qp
*qp
, int idx
, int size_16
)
4258 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp
, tidx
));
4259 for (i
= 0, j
= 0; i
< size_16
* 4; i
+= 4, j
+= 4) {
4260 if ((i
& 0xf) == 0) {
4261 void *buf
= mlx5_get_send_wqe(qp
, tidx
);
4262 tidx
= (tidx
+ 1) & (qp
->sq
.wqe_cnt
- 1);
4266 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p
[j
]),
4267 be32_to_cpu(p
[j
+ 1]), be32_to_cpu(p
[j
+ 2]),
4268 be32_to_cpu(p
[j
+ 3]));
4272 static int begin_wqe(struct mlx5_ib_qp
*qp
, void **seg
,
4273 struct mlx5_wqe_ctrl_seg
**ctrl
,
4274 struct ib_send_wr
*wr
, unsigned *idx
,
4275 int *size
, int nreq
)
4277 if (unlikely(mlx5_wq_overflow(&qp
->sq
, nreq
, qp
->ibqp
.send_cq
)))
4280 *idx
= qp
->sq
.cur_post
& (qp
->sq
.wqe_cnt
- 1);
4281 *seg
= mlx5_get_send_wqe(qp
, *idx
);
4283 *(uint32_t *)(*seg
+ 8) = 0;
4284 (*ctrl
)->imm
= send_ieth(wr
);
4285 (*ctrl
)->fm_ce_se
= qp
->sq_signal_bits
|
4286 (wr
->send_flags
& IB_SEND_SIGNALED
?
4287 MLX5_WQE_CTRL_CQ_UPDATE
: 0) |
4288 (wr
->send_flags
& IB_SEND_SOLICITED
?
4289 MLX5_WQE_CTRL_SOLICITED
: 0);
4291 *seg
+= sizeof(**ctrl
);
4292 *size
= sizeof(**ctrl
) / 16;
4297 static void finish_wqe(struct mlx5_ib_qp
*qp
,
4298 struct mlx5_wqe_ctrl_seg
*ctrl
,
4299 u8 size
, unsigned idx
, u64 wr_id
,
4300 int nreq
, u8 fence
, u32 mlx5_opcode
)
4304 ctrl
->opmod_idx_opcode
= cpu_to_be32(((u32
)(qp
->sq
.cur_post
) << 8) |
4305 mlx5_opcode
| ((u32
)opmod
<< 24));
4306 ctrl
->qpn_ds
= cpu_to_be32(size
| (qp
->trans_qp
.base
.mqp
.qpn
<< 8));
4307 ctrl
->fm_ce_se
|= fence
;
4308 if (unlikely(qp
->wq_sig
))
4309 ctrl
->signature
= wq_sig(ctrl
);
4311 qp
->sq
.wrid
[idx
] = wr_id
;
4312 qp
->sq
.w_list
[idx
].opcode
= mlx5_opcode
;
4313 qp
->sq
.wqe_head
[idx
] = qp
->sq
.head
+ nreq
;
4314 qp
->sq
.cur_post
+= DIV_ROUND_UP(size
* 16, MLX5_SEND_WQE_BB
);
4315 qp
->sq
.w_list
[idx
].next
= qp
->sq
.cur_post
;
4319 int mlx5_ib_post_send(struct ib_qp
*ibqp
, struct ib_send_wr
*wr
,
4320 struct ib_send_wr
**bad_wr
)
4322 struct mlx5_wqe_ctrl_seg
*ctrl
= NULL
; /* compiler warning */
4323 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4324 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4325 struct mlx5_ib_qp
*qp
;
4326 struct mlx5_ib_mr
*mr
;
4327 struct mlx5_wqe_data_seg
*dpseg
;
4328 struct mlx5_wqe_xrc_seg
*xrc
;
4330 int uninitialized_var(size
);
4332 unsigned long flags
;
4342 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
4343 return mlx5_ib_gsi_post_send(ibqp
, wr
, bad_wr
);
4349 spin_lock_irqsave(&qp
->sq
.lock
, flags
);
4351 if (mdev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
4358 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
4359 if (unlikely(wr
->opcode
>= ARRAY_SIZE(mlx5_ib_opcode
))) {
4360 mlx5_ib_warn(dev
, "\n");
4366 num_sge
= wr
->num_sge
;
4367 if (unlikely(num_sge
> qp
->sq
.max_gs
)) {
4368 mlx5_ib_warn(dev
, "\n");
4374 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
, &idx
, &size
, nreq
);
4376 mlx5_ib_warn(dev
, "\n");
4382 if (wr
->opcode
== IB_WR_LOCAL_INV
||
4383 wr
->opcode
== IB_WR_REG_MR
) {
4384 fence
= dev
->umr_fence
;
4385 next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
4386 } else if (wr
->send_flags
& IB_SEND_FENCE
) {
4388 fence
= MLX5_FENCE_MODE_SMALL_AND_FENCE
;
4390 fence
= MLX5_FENCE_MODE_FENCE
;
4392 fence
= qp
->next_fence
;
4395 switch (ibqp
->qp_type
) {
4396 case IB_QPT_XRC_INI
:
4398 seg
+= sizeof(*xrc
);
4399 size
+= sizeof(*xrc
) / 16;
4402 switch (wr
->opcode
) {
4403 case IB_WR_RDMA_READ
:
4404 case IB_WR_RDMA_WRITE
:
4405 case IB_WR_RDMA_WRITE_WITH_IMM
:
4406 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
4408 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
4409 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
4412 case IB_WR_ATOMIC_CMP_AND_SWP
:
4413 case IB_WR_ATOMIC_FETCH_AND_ADD
:
4414 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP
:
4415 mlx5_ib_warn(dev
, "Atomic operations are not supported yet\n");
4420 case IB_WR_LOCAL_INV
:
4421 qp
->sq
.wr_data
[idx
] = IB_WR_LOCAL_INV
;
4422 ctrl
->imm
= cpu_to_be32(wr
->ex
.invalidate_rkey
);
4423 set_linv_wr(qp
, &seg
, &size
);
4428 qp
->sq
.wr_data
[idx
] = IB_WR_REG_MR
;
4429 ctrl
->imm
= cpu_to_be32(reg_wr(wr
)->key
);
4430 err
= set_reg_wr(qp
, reg_wr(wr
), &seg
, &size
);
4438 case IB_WR_REG_SIG_MR
:
4439 qp
->sq
.wr_data
[idx
] = IB_WR_REG_SIG_MR
;
4440 mr
= to_mmr(sig_handover_wr(wr
)->sig_mr
);
4442 ctrl
->imm
= cpu_to_be32(mr
->ibmr
.rkey
);
4443 err
= set_sig_umr_wr(wr
, qp
, &seg
, &size
);
4445 mlx5_ib_warn(dev
, "\n");
4450 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
,
4451 fence
, MLX5_OPCODE_UMR
);
4453 * SET_PSV WQEs are not signaled and solicited
4456 wr
->send_flags
&= ~IB_SEND_SIGNALED
;
4457 wr
->send_flags
|= IB_SEND_SOLICITED
;
4458 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
4461 mlx5_ib_warn(dev
, "\n");
4467 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->mem
,
4468 mr
->sig
->psv_memory
.psv_idx
, &seg
,
4471 mlx5_ib_warn(dev
, "\n");
4476 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
,
4477 fence
, MLX5_OPCODE_SET_PSV
);
4478 err
= begin_wqe(qp
, &seg
, &ctrl
, wr
,
4481 mlx5_ib_warn(dev
, "\n");
4487 err
= set_psv_wr(&sig_handover_wr(wr
)->sig_attrs
->wire
,
4488 mr
->sig
->psv_wire
.psv_idx
, &seg
,
4491 mlx5_ib_warn(dev
, "\n");
4496 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
,
4497 fence
, MLX5_OPCODE_SET_PSV
);
4498 qp
->next_fence
= MLX5_FENCE_MODE_INITIATOR_SMALL
;
4508 switch (wr
->opcode
) {
4509 case IB_WR_RDMA_WRITE
:
4510 case IB_WR_RDMA_WRITE_WITH_IMM
:
4511 set_raddr_seg(seg
, rdma_wr(wr
)->remote_addr
,
4513 seg
+= sizeof(struct mlx5_wqe_raddr_seg
);
4514 size
+= sizeof(struct mlx5_wqe_raddr_seg
) / 16;
4523 if (unlikely(!mdev
->port_caps
[qp
->port
- 1].has_smi
)) {
4524 mlx5_ib_warn(dev
, "Send SMP MADs is not allowed\n");
4530 case MLX5_IB_QPT_HW_GSI
:
4531 set_datagram_seg(seg
, wr
);
4532 seg
+= sizeof(struct mlx5_wqe_datagram_seg
);
4533 size
+= sizeof(struct mlx5_wqe_datagram_seg
) / 16;
4534 if (unlikely((seg
== qend
)))
4535 seg
= mlx5_get_send_wqe(qp
, 0);
4538 set_datagram_seg(seg
, wr
);
4539 seg
+= sizeof(struct mlx5_wqe_datagram_seg
);
4540 size
+= sizeof(struct mlx5_wqe_datagram_seg
) / 16;
4542 if (unlikely((seg
== qend
)))
4543 seg
= mlx5_get_send_wqe(qp
, 0);
4545 /* handle qp that supports ud offload */
4546 if (qp
->flags
& IB_QP_CREATE_IPOIB_UD_LSO
) {
4547 struct mlx5_wqe_eth_pad
*pad
;
4550 memset(pad
, 0, sizeof(struct mlx5_wqe_eth_pad
));
4551 seg
+= sizeof(struct mlx5_wqe_eth_pad
);
4552 size
+= sizeof(struct mlx5_wqe_eth_pad
) / 16;
4554 seg
= set_eth_seg(seg
, wr
, qend
, qp
, &size
);
4556 if (unlikely((seg
== qend
)))
4557 seg
= mlx5_get_send_wqe(qp
, 0);
4560 case MLX5_IB_QPT_REG_UMR
:
4561 if (wr
->opcode
!= MLX5_IB_WR_UMR
) {
4563 mlx5_ib_warn(dev
, "bad opcode\n");
4566 qp
->sq
.wr_data
[idx
] = MLX5_IB_WR_UMR
;
4567 ctrl
->imm
= cpu_to_be32(umr_wr(wr
)->mkey
);
4568 err
= set_reg_umr_segment(dev
, seg
, wr
, !!(MLX5_CAP_GEN(mdev
, atomic
)));
4571 seg
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
);
4572 size
+= sizeof(struct mlx5_wqe_umr_ctrl_seg
) / 16;
4573 if (unlikely((seg
== qend
)))
4574 seg
= mlx5_get_send_wqe(qp
, 0);
4575 set_reg_mkey_segment(seg
, wr
);
4576 seg
+= sizeof(struct mlx5_mkey_seg
);
4577 size
+= sizeof(struct mlx5_mkey_seg
) / 16;
4578 if (unlikely((seg
== qend
)))
4579 seg
= mlx5_get_send_wqe(qp
, 0);
4586 if (wr
->send_flags
& IB_SEND_INLINE
&& num_sge
) {
4587 int uninitialized_var(sz
);
4589 err
= set_data_inl_seg(qp
, wr
, seg
, &sz
);
4590 if (unlikely(err
)) {
4591 mlx5_ib_warn(dev
, "\n");
4598 for (i
= 0; i
< num_sge
; i
++) {
4599 if (unlikely(dpseg
== qend
)) {
4600 seg
= mlx5_get_send_wqe(qp
, 0);
4603 if (likely(wr
->sg_list
[i
].length
)) {
4604 set_data_ptr_seg(dpseg
, wr
->sg_list
+ i
);
4605 size
+= sizeof(struct mlx5_wqe_data_seg
) / 16;
4611 qp
->next_fence
= next_fence
;
4612 finish_wqe(qp
, ctrl
, size
, idx
, wr
->wr_id
, nreq
, fence
,
4613 mlx5_ib_opcode
[wr
->opcode
]);
4616 dump_wqe(qp
, idx
, size
);
4621 qp
->sq
.head
+= nreq
;
4623 /* Make sure that descriptors are written before
4624 * updating doorbell record and ringing the doorbell
4628 qp
->db
.db
[MLX5_SND_DBR
] = cpu_to_be32(qp
->sq
.cur_post
);
4630 /* Make sure doorbell record is visible to the HCA before
4631 * we hit doorbell */
4634 /* currently we support only regular doorbells */
4635 mlx5_write64((__be32
*)ctrl
, bf
->bfreg
->map
+ bf
->offset
, NULL
);
4636 /* Make sure doorbells don't leak out of SQ spinlock
4637 * and reach the HCA out of order.
4640 bf
->offset
^= bf
->buf_size
;
4643 spin_unlock_irqrestore(&qp
->sq
.lock
, flags
);
4648 static void set_sig_seg(struct mlx5_rwqe_sig
*sig
, int size
)
4650 sig
->signature
= calc_sig(sig
, size
);
4653 int mlx5_ib_post_recv(struct ib_qp
*ibqp
, struct ib_recv_wr
*wr
,
4654 struct ib_recv_wr
**bad_wr
)
4656 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
4657 struct mlx5_wqe_data_seg
*scat
;
4658 struct mlx5_rwqe_sig
*sig
;
4659 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
4660 struct mlx5_core_dev
*mdev
= dev
->mdev
;
4661 unsigned long flags
;
4667 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
4668 return mlx5_ib_gsi_post_recv(ibqp
, wr
, bad_wr
);
4670 spin_lock_irqsave(&qp
->rq
.lock
, flags
);
4672 if (mdev
->state
== MLX5_DEVICE_STATE_INTERNAL_ERROR
) {
4679 ind
= qp
->rq
.head
& (qp
->rq
.wqe_cnt
- 1);
4681 for (nreq
= 0; wr
; nreq
++, wr
= wr
->next
) {
4682 if (mlx5_wq_overflow(&qp
->rq
, nreq
, qp
->ibqp
.recv_cq
)) {
4688 if (unlikely(wr
->num_sge
> qp
->rq
.max_gs
)) {
4694 scat
= get_recv_wqe(qp
, ind
);
4698 for (i
= 0; i
< wr
->num_sge
; i
++)
4699 set_data_ptr_seg(scat
+ i
, wr
->sg_list
+ i
);
4701 if (i
< qp
->rq
.max_gs
) {
4702 scat
[i
].byte_count
= 0;
4703 scat
[i
].lkey
= cpu_to_be32(MLX5_INVALID_LKEY
);
4708 sig
= (struct mlx5_rwqe_sig
*)scat
;
4709 set_sig_seg(sig
, (qp
->rq
.max_gs
+ 1) << 2);
4712 qp
->rq
.wrid
[ind
] = wr
->wr_id
;
4714 ind
= (ind
+ 1) & (qp
->rq
.wqe_cnt
- 1);
4719 qp
->rq
.head
+= nreq
;
4721 /* Make sure that descriptors are written before
4726 *qp
->db
.db
= cpu_to_be32(qp
->rq
.head
& 0xffff);
4729 spin_unlock_irqrestore(&qp
->rq
.lock
, flags
);
4734 static inline enum ib_qp_state
to_ib_qp_state(enum mlx5_qp_state mlx5_state
)
4736 switch (mlx5_state
) {
4737 case MLX5_QP_STATE_RST
: return IB_QPS_RESET
;
4738 case MLX5_QP_STATE_INIT
: return IB_QPS_INIT
;
4739 case MLX5_QP_STATE_RTR
: return IB_QPS_RTR
;
4740 case MLX5_QP_STATE_RTS
: return IB_QPS_RTS
;
4741 case MLX5_QP_STATE_SQ_DRAINING
:
4742 case MLX5_QP_STATE_SQD
: return IB_QPS_SQD
;
4743 case MLX5_QP_STATE_SQER
: return IB_QPS_SQE
;
4744 case MLX5_QP_STATE_ERR
: return IB_QPS_ERR
;
4749 static inline enum ib_mig_state
to_ib_mig_state(int mlx5_mig_state
)
4751 switch (mlx5_mig_state
) {
4752 case MLX5_QP_PM_ARMED
: return IB_MIG_ARMED
;
4753 case MLX5_QP_PM_REARM
: return IB_MIG_REARM
;
4754 case MLX5_QP_PM_MIGRATED
: return IB_MIG_MIGRATED
;
4759 static int to_ib_qp_access_flags(int mlx5_flags
)
4763 if (mlx5_flags
& MLX5_QP_BIT_RRE
)
4764 ib_flags
|= IB_ACCESS_REMOTE_READ
;
4765 if (mlx5_flags
& MLX5_QP_BIT_RWE
)
4766 ib_flags
|= IB_ACCESS_REMOTE_WRITE
;
4767 if (mlx5_flags
& MLX5_QP_BIT_RAE
)
4768 ib_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
4773 static void to_rdma_ah_attr(struct mlx5_ib_dev
*ibdev
,
4774 struct rdma_ah_attr
*ah_attr
,
4775 struct mlx5_qp_path
*path
)
4778 memset(ah_attr
, 0, sizeof(*ah_attr
));
4780 if (!path
->port
|| path
->port
> ibdev
->num_ports
)
4783 ah_attr
->type
= rdma_ah_find_type(&ibdev
->ib_dev
, path
->port
);
4785 rdma_ah_set_port_num(ah_attr
, path
->port
);
4786 rdma_ah_set_sl(ah_attr
, path
->dci_cfi_prio_sl
& 0xf);
4788 rdma_ah_set_dlid(ah_attr
, be16_to_cpu(path
->rlid
));
4789 rdma_ah_set_path_bits(ah_attr
, path
->grh_mlid
& 0x7f);
4790 rdma_ah_set_static_rate(ah_attr
,
4791 path
->static_rate
? path
->static_rate
- 5 : 0);
4792 if (path
->grh_mlid
& (1 << 7)) {
4793 u32 tc_fl
= be32_to_cpu(path
->tclass_flowlabel
);
4795 rdma_ah_set_grh(ah_attr
, NULL
,
4799 (tc_fl
>> 20) & 0xff);
4800 rdma_ah_set_dgid_raw(ah_attr
, path
->rgid
);
4804 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev
*dev
,
4805 struct mlx5_ib_sq
*sq
,
4813 inlen
= MLX5_ST_SZ_BYTES(query_sq_out
);
4814 out
= kvzalloc(inlen
, GFP_KERNEL
);
4818 err
= mlx5_core_query_sq(dev
->mdev
, sq
->base
.mqp
.qpn
, out
);
4822 sqc
= MLX5_ADDR_OF(query_sq_out
, out
, sq_context
);
4823 *sq_state
= MLX5_GET(sqc
, sqc
, state
);
4824 sq
->state
= *sq_state
;
4831 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev
*dev
,
4832 struct mlx5_ib_rq
*rq
,
4840 inlen
= MLX5_ST_SZ_BYTES(query_rq_out
);
4841 out
= kvzalloc(inlen
, GFP_KERNEL
);
4845 err
= mlx5_core_query_rq(dev
->mdev
, rq
->base
.mqp
.qpn
, out
);
4849 rqc
= MLX5_ADDR_OF(query_rq_out
, out
, rq_context
);
4850 *rq_state
= MLX5_GET(rqc
, rqc
, state
);
4851 rq
->state
= *rq_state
;
4858 static int sqrq_state_to_qp_state(u8 sq_state
, u8 rq_state
,
4859 struct mlx5_ib_qp
*qp
, u8
*qp_state
)
4861 static const u8 sqrq_trans
[MLX5_RQ_NUM_STATE
][MLX5_SQ_NUM_STATE
] = {
4862 [MLX5_RQC_STATE_RST
] = {
4863 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
4864 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
4865 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE_BAD
,
4866 [MLX5_SQ_STATE_NA
] = IB_QPS_RESET
,
4868 [MLX5_RQC_STATE_RDY
] = {
4869 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
4870 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
4871 [MLX5_SQC_STATE_ERR
] = IB_QPS_SQE
,
4872 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE
,
4874 [MLX5_RQC_STATE_ERR
] = {
4875 [MLX5_SQC_STATE_RST
] = MLX5_QP_STATE_BAD
,
4876 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE_BAD
,
4877 [MLX5_SQC_STATE_ERR
] = IB_QPS_ERR
,
4878 [MLX5_SQ_STATE_NA
] = IB_QPS_ERR
,
4880 [MLX5_RQ_STATE_NA
] = {
4881 [MLX5_SQC_STATE_RST
] = IB_QPS_RESET
,
4882 [MLX5_SQC_STATE_RDY
] = MLX5_QP_STATE
,
4883 [MLX5_SQC_STATE_ERR
] = MLX5_QP_STATE
,
4884 [MLX5_SQ_STATE_NA
] = MLX5_QP_STATE_BAD
,
4888 *qp_state
= sqrq_trans
[rq_state
][sq_state
];
4890 if (*qp_state
== MLX5_QP_STATE_BAD
) {
4891 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4892 qp
->raw_packet_qp
.sq
.base
.mqp
.qpn
, sq_state
,
4893 qp
->raw_packet_qp
.rq
.base
.mqp
.qpn
, rq_state
);
4897 if (*qp_state
== MLX5_QP_STATE
)
4898 *qp_state
= qp
->state
;
4903 static int query_raw_packet_qp_state(struct mlx5_ib_dev
*dev
,
4904 struct mlx5_ib_qp
*qp
,
4905 u8
*raw_packet_qp_state
)
4907 struct mlx5_ib_raw_packet_qp
*raw_packet_qp
= &qp
->raw_packet_qp
;
4908 struct mlx5_ib_sq
*sq
= &raw_packet_qp
->sq
;
4909 struct mlx5_ib_rq
*rq
= &raw_packet_qp
->rq
;
4911 u8 sq_state
= MLX5_SQ_STATE_NA
;
4912 u8 rq_state
= MLX5_RQ_STATE_NA
;
4914 if (qp
->sq
.wqe_cnt
) {
4915 err
= query_raw_packet_qp_sq_state(dev
, sq
, &sq_state
);
4920 if (qp
->rq
.wqe_cnt
) {
4921 err
= query_raw_packet_qp_rq_state(dev
, rq
, &rq_state
);
4926 return sqrq_state_to_qp_state(sq_state
, rq_state
, qp
,
4927 raw_packet_qp_state
);
4930 static int query_qp_attr(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*qp
,
4931 struct ib_qp_attr
*qp_attr
)
4933 int outlen
= MLX5_ST_SZ_BYTES(query_qp_out
);
4934 struct mlx5_qp_context
*context
;
4939 outb
= kzalloc(outlen
, GFP_KERNEL
);
4943 err
= mlx5_core_qp_query(dev
->mdev
, &qp
->trans_qp
.base
.mqp
, outb
,
4948 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4949 context
= (struct mlx5_qp_context
*)MLX5_ADDR_OF(query_qp_out
, outb
, qpc
);
4951 mlx5_state
= be32_to_cpu(context
->flags
) >> 28;
4953 qp
->state
= to_ib_qp_state(mlx5_state
);
4954 qp_attr
->path_mtu
= context
->mtu_msgmax
>> 5;
4955 qp_attr
->path_mig_state
=
4956 to_ib_mig_state((be32_to_cpu(context
->flags
) >> 11) & 0x3);
4957 qp_attr
->qkey
= be32_to_cpu(context
->qkey
);
4958 qp_attr
->rq_psn
= be32_to_cpu(context
->rnr_nextrecvpsn
) & 0xffffff;
4959 qp_attr
->sq_psn
= be32_to_cpu(context
->next_send_psn
) & 0xffffff;
4960 qp_attr
->dest_qp_num
= be32_to_cpu(context
->log_pg_sz_remote_qpn
) & 0xffffff;
4961 qp_attr
->qp_access_flags
=
4962 to_ib_qp_access_flags(be32_to_cpu(context
->params2
));
4964 if (qp
->ibqp
.qp_type
== IB_QPT_RC
|| qp
->ibqp
.qp_type
== IB_QPT_UC
) {
4965 to_rdma_ah_attr(dev
, &qp_attr
->ah_attr
, &context
->pri_path
);
4966 to_rdma_ah_attr(dev
, &qp_attr
->alt_ah_attr
, &context
->alt_path
);
4967 qp_attr
->alt_pkey_index
=
4968 be16_to_cpu(context
->alt_path
.pkey_index
);
4969 qp_attr
->alt_port_num
=
4970 rdma_ah_get_port_num(&qp_attr
->alt_ah_attr
);
4973 qp_attr
->pkey_index
= be16_to_cpu(context
->pri_path
.pkey_index
);
4974 qp_attr
->port_num
= context
->pri_path
.port
;
4976 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4977 qp_attr
->sq_draining
= mlx5_state
== MLX5_QP_STATE_SQ_DRAINING
;
4979 qp_attr
->max_rd_atomic
= 1 << ((be32_to_cpu(context
->params1
) >> 21) & 0x7);
4981 qp_attr
->max_dest_rd_atomic
=
4982 1 << ((be32_to_cpu(context
->params2
) >> 21) & 0x7);
4983 qp_attr
->min_rnr_timer
=
4984 (be32_to_cpu(context
->rnr_nextrecvpsn
) >> 24) & 0x1f;
4985 qp_attr
->timeout
= context
->pri_path
.ackto_lt
>> 3;
4986 qp_attr
->retry_cnt
= (be32_to_cpu(context
->params1
) >> 16) & 0x7;
4987 qp_attr
->rnr_retry
= (be32_to_cpu(context
->params1
) >> 13) & 0x7;
4988 qp_attr
->alt_timeout
= context
->alt_path
.ackto_lt
>> 3;
4995 static int mlx5_ib_dct_query_qp(struct mlx5_ib_dev
*dev
, struct mlx5_ib_qp
*mqp
,
4996 struct ib_qp_attr
*qp_attr
, int qp_attr_mask
,
4997 struct ib_qp_init_attr
*qp_init_attr
)
4999 struct mlx5_core_dct
*dct
= &mqp
->dct
.mdct
;
5001 u32 access_flags
= 0;
5002 int outlen
= MLX5_ST_SZ_BYTES(query_dct_out
);
5005 int supported_mask
= IB_QP_STATE
|
5006 IB_QP_ACCESS_FLAGS
|
5008 IB_QP_MIN_RNR_TIMER
|
5013 if (qp_attr_mask
& ~supported_mask
)
5015 if (mqp
->state
!= IB_QPS_RTR
)
5018 out
= kzalloc(outlen
, GFP_KERNEL
);
5022 err
= mlx5_core_dct_query(dev
->mdev
, dct
, out
, outlen
);
5026 dctc
= MLX5_ADDR_OF(query_dct_out
, out
, dct_context_entry
);
5028 if (qp_attr_mask
& IB_QP_STATE
)
5029 qp_attr
->qp_state
= IB_QPS_RTR
;
5031 if (qp_attr_mask
& IB_QP_ACCESS_FLAGS
) {
5032 if (MLX5_GET(dctc
, dctc
, rre
))
5033 access_flags
|= IB_ACCESS_REMOTE_READ
;
5034 if (MLX5_GET(dctc
, dctc
, rwe
))
5035 access_flags
|= IB_ACCESS_REMOTE_WRITE
;
5036 if (MLX5_GET(dctc
, dctc
, rae
))
5037 access_flags
|= IB_ACCESS_REMOTE_ATOMIC
;
5038 qp_attr
->qp_access_flags
= access_flags
;
5041 if (qp_attr_mask
& IB_QP_PORT
)
5042 qp_attr
->port_num
= MLX5_GET(dctc
, dctc
, port
);
5043 if (qp_attr_mask
& IB_QP_MIN_RNR_TIMER
)
5044 qp_attr
->min_rnr_timer
= MLX5_GET(dctc
, dctc
, min_rnr_nak
);
5045 if (qp_attr_mask
& IB_QP_AV
) {
5046 qp_attr
->ah_attr
.grh
.traffic_class
= MLX5_GET(dctc
, dctc
, tclass
);
5047 qp_attr
->ah_attr
.grh
.flow_label
= MLX5_GET(dctc
, dctc
, flow_label
);
5048 qp_attr
->ah_attr
.grh
.sgid_index
= MLX5_GET(dctc
, dctc
, my_addr_index
);
5049 qp_attr
->ah_attr
.grh
.hop_limit
= MLX5_GET(dctc
, dctc
, hop_limit
);
5051 if (qp_attr_mask
& IB_QP_PATH_MTU
)
5052 qp_attr
->path_mtu
= MLX5_GET(dctc
, dctc
, mtu
);
5053 if (qp_attr_mask
& IB_QP_PKEY_INDEX
)
5054 qp_attr
->pkey_index
= MLX5_GET(dctc
, dctc
, pkey_index
);
5060 int mlx5_ib_query_qp(struct ib_qp
*ibqp
, struct ib_qp_attr
*qp_attr
,
5061 int qp_attr_mask
, struct ib_qp_init_attr
*qp_init_attr
)
5063 struct mlx5_ib_dev
*dev
= to_mdev(ibqp
->device
);
5064 struct mlx5_ib_qp
*qp
= to_mqp(ibqp
);
5066 u8 raw_packet_qp_state
;
5068 if (ibqp
->rwq_ind_tbl
)
5071 if (unlikely(ibqp
->qp_type
== IB_QPT_GSI
))
5072 return mlx5_ib_gsi_query_qp(ibqp
, qp_attr
, qp_attr_mask
,
5075 /* Not all of output fields are applicable, make sure to zero them */
5076 memset(qp_init_attr
, 0, sizeof(*qp_init_attr
));
5077 memset(qp_attr
, 0, sizeof(*qp_attr
));
5079 if (unlikely(qp
->qp_sub_type
== MLX5_IB_QPT_DCT
))
5080 return mlx5_ib_dct_query_qp(dev
, qp
, qp_attr
,
5081 qp_attr_mask
, qp_init_attr
);
5083 mutex_lock(&qp
->mutex
);
5085 if (qp
->ibqp
.qp_type
== IB_QPT_RAW_PACKET
||
5086 qp
->flags
& MLX5_IB_QP_UNDERLAY
) {
5087 err
= query_raw_packet_qp_state(dev
, qp
, &raw_packet_qp_state
);
5090 qp
->state
= raw_packet_qp_state
;
5091 qp_attr
->port_num
= 1;
5093 err
= query_qp_attr(dev
, qp
, qp_attr
);
5098 qp_attr
->qp_state
= qp
->state
;
5099 qp_attr
->cur_qp_state
= qp_attr
->qp_state
;
5100 qp_attr
->cap
.max_recv_wr
= qp
->rq
.wqe_cnt
;
5101 qp_attr
->cap
.max_recv_sge
= qp
->rq
.max_gs
;
5103 if (!ibqp
->uobject
) {
5104 qp_attr
->cap
.max_send_wr
= qp
->sq
.max_post
;
5105 qp_attr
->cap
.max_send_sge
= qp
->sq
.max_gs
;
5106 qp_init_attr
->qp_context
= ibqp
->qp_context
;
5108 qp_attr
->cap
.max_send_wr
= 0;
5109 qp_attr
->cap
.max_send_sge
= 0;
5112 qp_init_attr
->qp_type
= ibqp
->qp_type
;
5113 qp_init_attr
->recv_cq
= ibqp
->recv_cq
;
5114 qp_init_attr
->send_cq
= ibqp
->send_cq
;
5115 qp_init_attr
->srq
= ibqp
->srq
;
5116 qp_attr
->cap
.max_inline_data
= qp
->max_inline_data
;
5118 qp_init_attr
->cap
= qp_attr
->cap
;
5120 qp_init_attr
->create_flags
= 0;
5121 if (qp
->flags
& MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK
)
5122 qp_init_attr
->create_flags
|= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK
;
5124 if (qp
->flags
& MLX5_IB_QP_CROSS_CHANNEL
)
5125 qp_init_attr
->create_flags
|= IB_QP_CREATE_CROSS_CHANNEL
;
5126 if (qp
->flags
& MLX5_IB_QP_MANAGED_SEND
)
5127 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_SEND
;
5128 if (qp
->flags
& MLX5_IB_QP_MANAGED_RECV
)
5129 qp_init_attr
->create_flags
|= IB_QP_CREATE_MANAGED_RECV
;
5130 if (qp
->flags
& MLX5_IB_QP_SQPN_QP1
)
5131 qp_init_attr
->create_flags
|= mlx5_ib_create_qp_sqpn_qp1();
5133 qp_init_attr
->sq_sig_type
= qp
->sq_signal_bits
& MLX5_WQE_CTRL_CQ_UPDATE
?
5134 IB_SIGNAL_ALL_WR
: IB_SIGNAL_REQ_WR
;
5137 mutex_unlock(&qp
->mutex
);
5141 struct ib_xrcd
*mlx5_ib_alloc_xrcd(struct ib_device
*ibdev
,
5142 struct ib_ucontext
*context
,
5143 struct ib_udata
*udata
)
5145 struct mlx5_ib_dev
*dev
= to_mdev(ibdev
);
5146 struct mlx5_ib_xrcd
*xrcd
;
5149 if (!MLX5_CAP_GEN(dev
->mdev
, xrc
))
5150 return ERR_PTR(-ENOSYS
);
5152 xrcd
= kmalloc(sizeof(*xrcd
), GFP_KERNEL
);
5154 return ERR_PTR(-ENOMEM
);
5156 err
= mlx5_core_xrcd_alloc(dev
->mdev
, &xrcd
->xrcdn
);
5159 return ERR_PTR(-ENOMEM
);
5162 return &xrcd
->ibxrcd
;
5165 int mlx5_ib_dealloc_xrcd(struct ib_xrcd
*xrcd
)
5167 struct mlx5_ib_dev
*dev
= to_mdev(xrcd
->device
);
5168 u32 xrcdn
= to_mxrcd(xrcd
)->xrcdn
;
5171 err
= mlx5_core_xrcd_dealloc(dev
->mdev
, xrcdn
);
5173 mlx5_ib_warn(dev
, "failed to dealloc xrcdn 0x%x\n", xrcdn
);
5179 static void mlx5_ib_wq_event(struct mlx5_core_qp
*core_qp
, int type
)
5181 struct mlx5_ib_rwq
*rwq
= to_mibrwq(core_qp
);
5182 struct mlx5_ib_dev
*dev
= to_mdev(rwq
->ibwq
.device
);
5183 struct ib_event event
;
5185 if (rwq
->ibwq
.event_handler
) {
5186 event
.device
= rwq
->ibwq
.device
;
5187 event
.element
.wq
= &rwq
->ibwq
;
5189 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR
:
5190 event
.event
= IB_EVENT_WQ_FATAL
;
5193 mlx5_ib_warn(dev
, "Unexpected event type %d on WQ %06x\n", type
, core_qp
->qpn
);
5197 rwq
->ibwq
.event_handler(&event
, rwq
->ibwq
.wq_context
);
5201 static int set_delay_drop(struct mlx5_ib_dev
*dev
)
5205 mutex_lock(&dev
->delay_drop
.lock
);
5206 if (dev
->delay_drop
.activate
)
5209 err
= mlx5_core_set_delay_drop(dev
->mdev
, dev
->delay_drop
.timeout
);
5213 dev
->delay_drop
.activate
= true;
5215 mutex_unlock(&dev
->delay_drop
.lock
);
5218 atomic_inc(&dev
->delay_drop
.rqs_cnt
);
5222 static int create_rq(struct mlx5_ib_rwq
*rwq
, struct ib_pd
*pd
,
5223 struct ib_wq_init_attr
*init_attr
)
5225 struct mlx5_ib_dev
*dev
;
5226 int has_net_offloads
;
5234 dev
= to_mdev(pd
->device
);
5236 inlen
= MLX5_ST_SZ_BYTES(create_rq_in
) + sizeof(u64
) * rwq
->rq_num_pas
;
5237 in
= kvzalloc(inlen
, GFP_KERNEL
);
5241 rqc
= MLX5_ADDR_OF(create_rq_in
, in
, ctx
);
5242 MLX5_SET(rqc
, rqc
, mem_rq_type
,
5243 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE
);
5244 MLX5_SET(rqc
, rqc
, user_index
, rwq
->user_index
);
5245 MLX5_SET(rqc
, rqc
, cqn
, to_mcq(init_attr
->cq
)->mcq
.cqn
);
5246 MLX5_SET(rqc
, rqc
, state
, MLX5_RQC_STATE_RST
);
5247 MLX5_SET(rqc
, rqc
, flush_in_error_en
, 1);
5248 wq
= MLX5_ADDR_OF(rqc
, rqc
, wq
);
5249 MLX5_SET(wq
, wq
, wq_type
,
5250 rwq
->create_flags
& MLX5_IB_WQ_FLAGS_STRIDING_RQ
?
5251 MLX5_WQ_TYPE_CYCLIC_STRIDING_RQ
: MLX5_WQ_TYPE_CYCLIC
);
5252 if (init_attr
->create_flags
& IB_WQ_FLAGS_PCI_WRITE_END_PADDING
) {
5253 if (!MLX5_CAP_GEN(dev
->mdev
, end_pad
)) {
5254 mlx5_ib_dbg(dev
, "Scatter end padding is not supported\n");
5258 MLX5_SET(wq
, wq
, end_padding_mode
, MLX5_WQ_END_PAD_MODE_ALIGN
);
5261 MLX5_SET(wq
, wq
, log_wq_stride
, rwq
->log_rq_stride
);
5262 if (rwq
->create_flags
& MLX5_IB_WQ_FLAGS_STRIDING_RQ
) {
5263 MLX5_SET(wq
, wq
, two_byte_shift_en
, rwq
->two_byte_shift_en
);
5264 MLX5_SET(wq
, wq
, log_wqe_stride_size
,
5265 rwq
->single_stride_log_num_of_bytes
-
5266 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES
);
5267 MLX5_SET(wq
, wq
, log_wqe_num_of_strides
, rwq
->log_num_strides
-
5268 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES
);
5270 MLX5_SET(wq
, wq
, log_wq_sz
, rwq
->log_rq_size
);
5271 MLX5_SET(wq
, wq
, pd
, to_mpd(pd
)->pdn
);
5272 MLX5_SET(wq
, wq
, page_offset
, rwq
->rq_page_offset
);
5273 MLX5_SET(wq
, wq
, log_wq_pg_sz
, rwq
->log_page_size
);
5274 MLX5_SET(wq
, wq
, wq_signature
, rwq
->wq_sig
);
5275 MLX5_SET64(wq
, wq
, dbr_addr
, rwq
->db
.dma
);
5276 has_net_offloads
= MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
);
5277 if (init_attr
->create_flags
& IB_WQ_FLAGS_CVLAN_STRIPPING
) {
5278 if (!(has_net_offloads
&& MLX5_CAP_ETH(dev
->mdev
, vlan_cap
))) {
5279 mlx5_ib_dbg(dev
, "VLAN offloads are not supported\n");
5284 MLX5_SET(rqc
, rqc
, vsd
, 1);
5286 if (init_attr
->create_flags
& IB_WQ_FLAGS_SCATTER_FCS
) {
5287 if (!(has_net_offloads
&& MLX5_CAP_ETH(dev
->mdev
, scatter_fcs
))) {
5288 mlx5_ib_dbg(dev
, "Scatter FCS is not supported\n");
5292 MLX5_SET(rqc
, rqc
, scatter_fcs
, 1);
5294 if (init_attr
->create_flags
& IB_WQ_FLAGS_DELAY_DROP
) {
5295 if (!(dev
->ib_dev
.attrs
.raw_packet_caps
&
5296 IB_RAW_PACKET_CAP_DELAY_DROP
)) {
5297 mlx5_ib_dbg(dev
, "Delay drop is not supported\n");
5301 MLX5_SET(rqc
, rqc
, delay_drop_en
, 1);
5303 rq_pas0
= (__be64
*)MLX5_ADDR_OF(wq
, wq
, pas
);
5304 mlx5_ib_populate_pas(dev
, rwq
->umem
, rwq
->page_shift
, rq_pas0
, 0);
5305 err
= mlx5_core_create_rq_tracked(dev
->mdev
, in
, inlen
, &rwq
->core_qp
);
5306 if (!err
&& init_attr
->create_flags
& IB_WQ_FLAGS_DELAY_DROP
) {
5307 err
= set_delay_drop(dev
);
5309 mlx5_ib_warn(dev
, "Failed to enable delay drop err=%d\n",
5311 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rwq
->core_qp
);
5313 rwq
->create_flags
|= MLX5_IB_WQ_FLAGS_DELAY_DROP
;
5321 static int set_user_rq_size(struct mlx5_ib_dev
*dev
,
5322 struct ib_wq_init_attr
*wq_init_attr
,
5323 struct mlx5_ib_create_wq
*ucmd
,
5324 struct mlx5_ib_rwq
*rwq
)
5326 /* Sanity check RQ size before proceeding */
5327 if (wq_init_attr
->max_wr
> (1 << MLX5_CAP_GEN(dev
->mdev
, log_max_wq_sz
)))
5330 if (!ucmd
->rq_wqe_count
)
5333 rwq
->wqe_count
= ucmd
->rq_wqe_count
;
5334 rwq
->wqe_shift
= ucmd
->rq_wqe_shift
;
5335 rwq
->buf_size
= (rwq
->wqe_count
<< rwq
->wqe_shift
);
5336 rwq
->log_rq_stride
= rwq
->wqe_shift
;
5337 rwq
->log_rq_size
= ilog2(rwq
->wqe_count
);
5341 static int prepare_user_rq(struct ib_pd
*pd
,
5342 struct ib_wq_init_attr
*init_attr
,
5343 struct ib_udata
*udata
,
5344 struct mlx5_ib_rwq
*rwq
)
5346 struct mlx5_ib_dev
*dev
= to_mdev(pd
->device
);
5347 struct mlx5_ib_create_wq ucmd
= {};
5349 size_t required_cmd_sz
;
5351 required_cmd_sz
= offsetof(typeof(ucmd
), single_stride_log_num_of_bytes
)
5352 + sizeof(ucmd
.single_stride_log_num_of_bytes
);
5353 if (udata
->inlen
< required_cmd_sz
) {
5354 mlx5_ib_dbg(dev
, "invalid inlen\n");
5358 if (udata
->inlen
> sizeof(ucmd
) &&
5359 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
5360 udata
->inlen
- sizeof(ucmd
))) {
5361 mlx5_ib_dbg(dev
, "inlen is not supported\n");
5365 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
))) {
5366 mlx5_ib_dbg(dev
, "copy failed\n");
5370 if (ucmd
.comp_mask
& (~MLX5_IB_CREATE_WQ_STRIDING_RQ
)) {
5371 mlx5_ib_dbg(dev
, "invalid comp mask\n");
5373 } else if (ucmd
.comp_mask
& MLX5_IB_CREATE_WQ_STRIDING_RQ
) {
5374 if (!MLX5_CAP_GEN(dev
->mdev
, striding_rq
)) {
5375 mlx5_ib_dbg(dev
, "Striding RQ is not supported\n");
5378 if ((ucmd
.single_stride_log_num_of_bytes
<
5379 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES
) ||
5380 (ucmd
.single_stride_log_num_of_bytes
>
5381 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES
)) {
5382 mlx5_ib_dbg(dev
, "Invalid log stride size (%u. Range is %u - %u)\n",
5383 ucmd
.single_stride_log_num_of_bytes
,
5384 MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES
,
5385 MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES
);
5388 if ((ucmd
.single_wqe_log_num_of_strides
>
5389 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES
) ||
5390 (ucmd
.single_wqe_log_num_of_strides
<
5391 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES
)) {
5392 mlx5_ib_dbg(dev
, "Invalid log num strides (%u. Range is %u - %u)\n",
5393 ucmd
.single_wqe_log_num_of_strides
,
5394 MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES
,
5395 MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES
);
5398 rwq
->single_stride_log_num_of_bytes
=
5399 ucmd
.single_stride_log_num_of_bytes
;
5400 rwq
->log_num_strides
= ucmd
.single_wqe_log_num_of_strides
;
5401 rwq
->two_byte_shift_en
= !!ucmd
.two_byte_shift_en
;
5402 rwq
->create_flags
|= MLX5_IB_WQ_FLAGS_STRIDING_RQ
;
5405 err
= set_user_rq_size(dev
, init_attr
, &ucmd
, rwq
);
5407 mlx5_ib_dbg(dev
, "err %d\n", err
);
5411 err
= create_user_rq(dev
, pd
, rwq
, &ucmd
);
5413 mlx5_ib_dbg(dev
, "err %d\n", err
);
5418 rwq
->user_index
= ucmd
.user_index
;
5422 struct ib_wq
*mlx5_ib_create_wq(struct ib_pd
*pd
,
5423 struct ib_wq_init_attr
*init_attr
,
5424 struct ib_udata
*udata
)
5426 struct mlx5_ib_dev
*dev
;
5427 struct mlx5_ib_rwq
*rwq
;
5428 struct mlx5_ib_create_wq_resp resp
= {};
5429 size_t min_resp_len
;
5433 return ERR_PTR(-ENOSYS
);
5435 min_resp_len
= offsetof(typeof(resp
), reserved
) + sizeof(resp
.reserved
);
5436 if (udata
->outlen
&& udata
->outlen
< min_resp_len
)
5437 return ERR_PTR(-EINVAL
);
5439 dev
= to_mdev(pd
->device
);
5440 switch (init_attr
->wq_type
) {
5442 rwq
= kzalloc(sizeof(*rwq
), GFP_KERNEL
);
5444 return ERR_PTR(-ENOMEM
);
5445 err
= prepare_user_rq(pd
, init_attr
, udata
, rwq
);
5448 err
= create_rq(rwq
, pd
, init_attr
);
5453 mlx5_ib_dbg(dev
, "unsupported wq type %d\n",
5454 init_attr
->wq_type
);
5455 return ERR_PTR(-EINVAL
);
5458 rwq
->ibwq
.wq_num
= rwq
->core_qp
.qpn
;
5459 rwq
->ibwq
.state
= IB_WQS_RESET
;
5460 if (udata
->outlen
) {
5461 resp
.response_length
= offsetof(typeof(resp
), response_length
) +
5462 sizeof(resp
.response_length
);
5463 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
5468 rwq
->core_qp
.event
= mlx5_ib_wq_event
;
5469 rwq
->ibwq
.event_handler
= init_attr
->event_handler
;
5473 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rwq
->core_qp
);
5475 destroy_user_rq(dev
, pd
, rwq
);
5478 return ERR_PTR(err
);
5481 int mlx5_ib_destroy_wq(struct ib_wq
*wq
)
5483 struct mlx5_ib_dev
*dev
= to_mdev(wq
->device
);
5484 struct mlx5_ib_rwq
*rwq
= to_mrwq(wq
);
5486 mlx5_core_destroy_rq_tracked(dev
->mdev
, &rwq
->core_qp
);
5487 destroy_user_rq(dev
, wq
->pd
, rwq
);
5493 struct ib_rwq_ind_table
*mlx5_ib_create_rwq_ind_table(struct ib_device
*device
,
5494 struct ib_rwq_ind_table_init_attr
*init_attr
,
5495 struct ib_udata
*udata
)
5497 struct mlx5_ib_dev
*dev
= to_mdev(device
);
5498 struct mlx5_ib_rwq_ind_table
*rwq_ind_tbl
;
5499 int sz
= 1 << init_attr
->log_ind_tbl_size
;
5500 struct mlx5_ib_create_rwq_ind_tbl_resp resp
= {};
5501 size_t min_resp_len
;
5508 if (udata
->inlen
> 0 &&
5509 !ib_is_udata_cleared(udata
, 0,
5511 return ERR_PTR(-EOPNOTSUPP
);
5513 if (init_attr
->log_ind_tbl_size
>
5514 MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
)) {
5515 mlx5_ib_dbg(dev
, "log_ind_tbl_size = %d is bigger than supported = %d\n",
5516 init_attr
->log_ind_tbl_size
,
5517 MLX5_CAP_GEN(dev
->mdev
, log_max_rqt_size
));
5518 return ERR_PTR(-EINVAL
);
5521 min_resp_len
= offsetof(typeof(resp
), reserved
) + sizeof(resp
.reserved
);
5522 if (udata
->outlen
&& udata
->outlen
< min_resp_len
)
5523 return ERR_PTR(-EINVAL
);
5525 rwq_ind_tbl
= kzalloc(sizeof(*rwq_ind_tbl
), GFP_KERNEL
);
5527 return ERR_PTR(-ENOMEM
);
5529 inlen
= MLX5_ST_SZ_BYTES(create_rqt_in
) + sizeof(u32
) * sz
;
5530 in
= kvzalloc(inlen
, GFP_KERNEL
);
5536 rqtc
= MLX5_ADDR_OF(create_rqt_in
, in
, rqt_context
);
5538 MLX5_SET(rqtc
, rqtc
, rqt_actual_size
, sz
);
5539 MLX5_SET(rqtc
, rqtc
, rqt_max_size
, sz
);
5541 for (i
= 0; i
< sz
; i
++)
5542 MLX5_SET(rqtc
, rqtc
, rq_num
[i
], init_attr
->ind_tbl
[i
]->wq_num
);
5544 err
= mlx5_core_create_rqt(dev
->mdev
, in
, inlen
, &rwq_ind_tbl
->rqtn
);
5550 rwq_ind_tbl
->ib_rwq_ind_tbl
.ind_tbl_num
= rwq_ind_tbl
->rqtn
;
5551 if (udata
->outlen
) {
5552 resp
.response_length
= offsetof(typeof(resp
), response_length
) +
5553 sizeof(resp
.response_length
);
5554 err
= ib_copy_to_udata(udata
, &resp
, resp
.response_length
);
5559 return &rwq_ind_tbl
->ib_rwq_ind_tbl
;
5562 mlx5_core_destroy_rqt(dev
->mdev
, rwq_ind_tbl
->rqtn
);
5565 return ERR_PTR(err
);
5568 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table
*ib_rwq_ind_tbl
)
5570 struct mlx5_ib_rwq_ind_table
*rwq_ind_tbl
= to_mrwq_ind_table(ib_rwq_ind_tbl
);
5571 struct mlx5_ib_dev
*dev
= to_mdev(ib_rwq_ind_tbl
->device
);
5573 mlx5_core_destroy_rqt(dev
->mdev
, rwq_ind_tbl
->rqtn
);
5579 int mlx5_ib_modify_wq(struct ib_wq
*wq
, struct ib_wq_attr
*wq_attr
,
5580 u32 wq_attr_mask
, struct ib_udata
*udata
)
5582 struct mlx5_ib_dev
*dev
= to_mdev(wq
->device
);
5583 struct mlx5_ib_rwq
*rwq
= to_mrwq(wq
);
5584 struct mlx5_ib_modify_wq ucmd
= {};
5585 size_t required_cmd_sz
;
5593 required_cmd_sz
= offsetof(typeof(ucmd
), reserved
) + sizeof(ucmd
.reserved
);
5594 if (udata
->inlen
< required_cmd_sz
)
5597 if (udata
->inlen
> sizeof(ucmd
) &&
5598 !ib_is_udata_cleared(udata
, sizeof(ucmd
),
5599 udata
->inlen
- sizeof(ucmd
)))
5602 if (ib_copy_from_udata(&ucmd
, udata
, min(sizeof(ucmd
), udata
->inlen
)))
5605 if (ucmd
.comp_mask
|| ucmd
.reserved
)
5608 inlen
= MLX5_ST_SZ_BYTES(modify_rq_in
);
5609 in
= kvzalloc(inlen
, GFP_KERNEL
);
5613 rqc
= MLX5_ADDR_OF(modify_rq_in
, in
, ctx
);
5615 curr_wq_state
= (wq_attr_mask
& IB_WQ_CUR_STATE
) ?
5616 wq_attr
->curr_wq_state
: wq
->state
;
5617 wq_state
= (wq_attr_mask
& IB_WQ_STATE
) ?
5618 wq_attr
->wq_state
: curr_wq_state
;
5619 if (curr_wq_state
== IB_WQS_ERR
)
5620 curr_wq_state
= MLX5_RQC_STATE_ERR
;
5621 if (wq_state
== IB_WQS_ERR
)
5622 wq_state
= MLX5_RQC_STATE_ERR
;
5623 MLX5_SET(modify_rq_in
, in
, rq_state
, curr_wq_state
);
5624 MLX5_SET(rqc
, rqc
, state
, wq_state
);
5626 if (wq_attr_mask
& IB_WQ_FLAGS
) {
5627 if (wq_attr
->flags_mask
& IB_WQ_FLAGS_CVLAN_STRIPPING
) {
5628 if (!(MLX5_CAP_GEN(dev
->mdev
, eth_net_offloads
) &&
5629 MLX5_CAP_ETH(dev
->mdev
, vlan_cap
))) {
5630 mlx5_ib_dbg(dev
, "VLAN offloads are not "
5635 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
5636 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD
);
5637 MLX5_SET(rqc
, rqc
, vsd
,
5638 (wq_attr
->flags
& IB_WQ_FLAGS_CVLAN_STRIPPING
) ? 0 : 1);
5641 if (wq_attr
->flags_mask
& IB_WQ_FLAGS_PCI_WRITE_END_PADDING
) {
5642 mlx5_ib_dbg(dev
, "Modifying scatter end padding is not supported\n");
5648 if (curr_wq_state
== IB_WQS_RESET
&& wq_state
== IB_WQS_RDY
) {
5649 if (MLX5_CAP_GEN(dev
->mdev
, modify_rq_counter_set_id
)) {
5650 MLX5_SET64(modify_rq_in
, in
, modify_bitmask
,
5651 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_RQ_COUNTER_SET_ID
);
5652 MLX5_SET(rqc
, rqc
, counter_set_id
,
5653 dev
->port
->cnts
.set_id
);
5655 pr_info_once("%s: Receive WQ counters are not supported on current FW\n",
5659 err
= mlx5_core_modify_rq(dev
->mdev
, rwq
->core_qp
.qpn
, in
, inlen
);
5661 rwq
->ibwq
.state
= (wq_state
== MLX5_RQC_STATE_ERR
) ? IB_WQS_ERR
: wq_state
;