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IB/mlx5: Add Raw Packet QP query functionality
[mirror_ubuntu-bionic-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38 #include "user.h"
39
40 /* not supported currently */
41 static int wq_signature;
42
43 enum {
44 MLX5_IB_ACK_REQ_FREQ = 8,
45 };
46
47 enum {
48 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
49 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
50 MLX5_IB_LINK_TYPE_IB = 0,
51 MLX5_IB_LINK_TYPE_ETH = 1
52 };
53
54 enum {
55 MLX5_IB_SQ_STRIDE = 6,
56 MLX5_IB_CACHE_LINE_SIZE = 64,
57 };
58
59 static const u32 mlx5_ib_opcode[] = {
60 [IB_WR_SEND] = MLX5_OPCODE_SEND,
61 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
62 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
63 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
64 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
65 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
66 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
67 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
68 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
69 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
70 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
71 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
72 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
73 };
74
75
76 static int is_qp0(enum ib_qp_type qp_type)
77 {
78 return qp_type == IB_QPT_SMI;
79 }
80
81 static int is_sqp(enum ib_qp_type qp_type)
82 {
83 return is_qp0(qp_type) || is_qp1(qp_type);
84 }
85
86 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
87 {
88 return mlx5_buf_offset(&qp->buf, offset);
89 }
90
91 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
92 {
93 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
94 }
95
96 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
97 {
98 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
99 }
100
101 /**
102 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
103 *
104 * @qp: QP to copy from.
105 * @send: copy from the send queue when non-zero, use the receive queue
106 * otherwise.
107 * @wqe_index: index to start copying from. For send work queues, the
108 * wqe_index is in units of MLX5_SEND_WQE_BB.
109 * For receive work queue, it is the number of work queue
110 * element in the queue.
111 * @buffer: destination buffer.
112 * @length: maximum number of bytes to copy.
113 *
114 * Copies at least a single WQE, but may copy more data.
115 *
116 * Return: the number of bytes copied, or an error code.
117 */
118 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
119 void *buffer, u32 length,
120 struct mlx5_ib_qp_base *base)
121 {
122 struct ib_device *ibdev = qp->ibqp.device;
123 struct mlx5_ib_dev *dev = to_mdev(ibdev);
124 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
125 size_t offset;
126 size_t wq_end;
127 struct ib_umem *umem = base->ubuffer.umem;
128 u32 first_copy_length;
129 int wqe_length;
130 int ret;
131
132 if (wq->wqe_cnt == 0) {
133 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
134 qp->ibqp.qp_type);
135 return -EINVAL;
136 }
137
138 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
139 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
140
141 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
142 return -EINVAL;
143
144 if (offset > umem->length ||
145 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
146 return -EINVAL;
147
148 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
149 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
150 if (ret)
151 return ret;
152
153 if (send) {
154 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
155 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
156
157 wqe_length = ds * MLX5_WQE_DS_UNITS;
158 } else {
159 wqe_length = 1 << wq->wqe_shift;
160 }
161
162 if (wqe_length <= first_copy_length)
163 return first_copy_length;
164
165 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
166 wqe_length - first_copy_length);
167 if (ret)
168 return ret;
169
170 return wqe_length;
171 }
172
173 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
174 {
175 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
176 struct ib_event event;
177
178 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
179 /* This event is only valid for trans_qps */
180 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
181 }
182
183 if (ibqp->event_handler) {
184 event.device = ibqp->device;
185 event.element.qp = ibqp;
186 switch (type) {
187 case MLX5_EVENT_TYPE_PATH_MIG:
188 event.event = IB_EVENT_PATH_MIG;
189 break;
190 case MLX5_EVENT_TYPE_COMM_EST:
191 event.event = IB_EVENT_COMM_EST;
192 break;
193 case MLX5_EVENT_TYPE_SQ_DRAINED:
194 event.event = IB_EVENT_SQ_DRAINED;
195 break;
196 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
197 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
198 break;
199 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
200 event.event = IB_EVENT_QP_FATAL;
201 break;
202 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
203 event.event = IB_EVENT_PATH_MIG_ERR;
204 break;
205 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
206 event.event = IB_EVENT_QP_REQ_ERR;
207 break;
208 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
209 event.event = IB_EVENT_QP_ACCESS_ERR;
210 break;
211 default:
212 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
213 return;
214 }
215
216 ibqp->event_handler(&event, ibqp->qp_context);
217 }
218 }
219
220 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
221 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
222 {
223 int wqe_size;
224 int wq_size;
225
226 /* Sanity check RQ size before proceeding */
227 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
228 return -EINVAL;
229
230 if (!has_rq) {
231 qp->rq.max_gs = 0;
232 qp->rq.wqe_cnt = 0;
233 qp->rq.wqe_shift = 0;
234 } else {
235 if (ucmd) {
236 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
237 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
238 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
239 qp->rq.max_post = qp->rq.wqe_cnt;
240 } else {
241 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
242 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
243 wqe_size = roundup_pow_of_two(wqe_size);
244 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
245 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
246 qp->rq.wqe_cnt = wq_size / wqe_size;
247 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
248 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
249 wqe_size,
250 MLX5_CAP_GEN(dev->mdev,
251 max_wqe_sz_rq));
252 return -EINVAL;
253 }
254 qp->rq.wqe_shift = ilog2(wqe_size);
255 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
256 qp->rq.max_post = qp->rq.wqe_cnt;
257 }
258 }
259
260 return 0;
261 }
262
263 static int sq_overhead(enum ib_qp_type qp_type)
264 {
265 int size = 0;
266
267 switch (qp_type) {
268 case IB_QPT_XRC_INI:
269 size += sizeof(struct mlx5_wqe_xrc_seg);
270 /* fall through */
271 case IB_QPT_RC:
272 size += sizeof(struct mlx5_wqe_ctrl_seg) +
273 sizeof(struct mlx5_wqe_atomic_seg) +
274 sizeof(struct mlx5_wqe_raddr_seg);
275 break;
276
277 case IB_QPT_XRC_TGT:
278 return 0;
279
280 case IB_QPT_UC:
281 size += sizeof(struct mlx5_wqe_ctrl_seg) +
282 sizeof(struct mlx5_wqe_raddr_seg) +
283 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
284 sizeof(struct mlx5_mkey_seg);
285 break;
286
287 case IB_QPT_UD:
288 case IB_QPT_SMI:
289 case IB_QPT_GSI:
290 size += sizeof(struct mlx5_wqe_ctrl_seg) +
291 sizeof(struct mlx5_wqe_datagram_seg);
292 break;
293
294 case MLX5_IB_QPT_REG_UMR:
295 size += sizeof(struct mlx5_wqe_ctrl_seg) +
296 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
297 sizeof(struct mlx5_mkey_seg);
298 break;
299
300 default:
301 return -EINVAL;
302 }
303
304 return size;
305 }
306
307 static int calc_send_wqe(struct ib_qp_init_attr *attr)
308 {
309 int inl_size = 0;
310 int size;
311
312 size = sq_overhead(attr->qp_type);
313 if (size < 0)
314 return size;
315
316 if (attr->cap.max_inline_data) {
317 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
318 attr->cap.max_inline_data;
319 }
320
321 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
322 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
323 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
324 return MLX5_SIG_WQE_SIZE;
325 else
326 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
327 }
328
329 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
330 struct mlx5_ib_qp *qp)
331 {
332 int wqe_size;
333 int wq_size;
334
335 if (!attr->cap.max_send_wr)
336 return 0;
337
338 wqe_size = calc_send_wqe(attr);
339 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
340 if (wqe_size < 0)
341 return wqe_size;
342
343 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
344 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
345 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
346 return -EINVAL;
347 }
348
349 qp->max_inline_data = wqe_size - sq_overhead(attr->qp_type) -
350 sizeof(struct mlx5_wqe_inline_seg);
351 attr->cap.max_inline_data = qp->max_inline_data;
352
353 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
354 qp->signature_en = true;
355
356 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
357 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
358 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
359 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
360 qp->sq.wqe_cnt,
361 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
362 return -ENOMEM;
363 }
364 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
365 qp->sq.max_gs = attr->cap.max_send_sge;
366 qp->sq.max_post = wq_size / wqe_size;
367 attr->cap.max_send_wr = qp->sq.max_post;
368
369 return wq_size;
370 }
371
372 static int set_user_buf_size(struct mlx5_ib_dev *dev,
373 struct mlx5_ib_qp *qp,
374 struct mlx5_ib_create_qp *ucmd,
375 struct mlx5_ib_qp_base *base,
376 struct ib_qp_init_attr *attr)
377 {
378 int desc_sz = 1 << qp->sq.wqe_shift;
379
380 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
381 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
382 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
383 return -EINVAL;
384 }
385
386 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
387 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
388 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
389 return -EINVAL;
390 }
391
392 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
393
394 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
395 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
396 qp->sq.wqe_cnt,
397 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
398 return -EINVAL;
399 }
400
401 if (attr->qp_type == IB_QPT_RAW_PACKET) {
402 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
403 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
404 } else {
405 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
406 (qp->sq.wqe_cnt << 6);
407 }
408
409 return 0;
410 }
411
412 static int qp_has_rq(struct ib_qp_init_attr *attr)
413 {
414 if (attr->qp_type == IB_QPT_XRC_INI ||
415 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
416 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
417 !attr->cap.max_recv_wr)
418 return 0;
419
420 return 1;
421 }
422
423 static int first_med_uuar(void)
424 {
425 return 1;
426 }
427
428 static int next_uuar(int n)
429 {
430 n++;
431
432 while (((n % 4) & 2))
433 n++;
434
435 return n;
436 }
437
438 static int num_med_uuar(struct mlx5_uuar_info *uuari)
439 {
440 int n;
441
442 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
443 uuari->num_low_latency_uuars - 1;
444
445 return n >= 0 ? n : 0;
446 }
447
448 static int max_uuari(struct mlx5_uuar_info *uuari)
449 {
450 return uuari->num_uars * 4;
451 }
452
453 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
454 {
455 int med;
456 int i;
457 int t;
458
459 med = num_med_uuar(uuari);
460 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
461 t++;
462 if (t == med)
463 return next_uuar(i);
464 }
465
466 return 0;
467 }
468
469 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
470 {
471 int i;
472
473 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
474 if (!test_bit(i, uuari->bitmap)) {
475 set_bit(i, uuari->bitmap);
476 uuari->count[i]++;
477 return i;
478 }
479 }
480
481 return -ENOMEM;
482 }
483
484 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
485 {
486 int minidx = first_med_uuar();
487 int i;
488
489 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
490 if (uuari->count[i] < uuari->count[minidx])
491 minidx = i;
492 }
493
494 uuari->count[minidx]++;
495 return minidx;
496 }
497
498 static int alloc_uuar(struct mlx5_uuar_info *uuari,
499 enum mlx5_ib_latency_class lat)
500 {
501 int uuarn = -EINVAL;
502
503 mutex_lock(&uuari->lock);
504 switch (lat) {
505 case MLX5_IB_LATENCY_CLASS_LOW:
506 uuarn = 0;
507 uuari->count[uuarn]++;
508 break;
509
510 case MLX5_IB_LATENCY_CLASS_MEDIUM:
511 if (uuari->ver < 2)
512 uuarn = -ENOMEM;
513 else
514 uuarn = alloc_med_class_uuar(uuari);
515 break;
516
517 case MLX5_IB_LATENCY_CLASS_HIGH:
518 if (uuari->ver < 2)
519 uuarn = -ENOMEM;
520 else
521 uuarn = alloc_high_class_uuar(uuari);
522 break;
523
524 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
525 uuarn = 2;
526 break;
527 }
528 mutex_unlock(&uuari->lock);
529
530 return uuarn;
531 }
532
533 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
534 {
535 clear_bit(uuarn, uuari->bitmap);
536 --uuari->count[uuarn];
537 }
538
539 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
540 {
541 clear_bit(uuarn, uuari->bitmap);
542 --uuari->count[uuarn];
543 }
544
545 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
546 {
547 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
548 int high_uuar = nuuars - uuari->num_low_latency_uuars;
549
550 mutex_lock(&uuari->lock);
551 if (uuarn == 0) {
552 --uuari->count[uuarn];
553 goto out;
554 }
555
556 if (uuarn < high_uuar) {
557 free_med_class_uuar(uuari, uuarn);
558 goto out;
559 }
560
561 free_high_class_uuar(uuari, uuarn);
562
563 out:
564 mutex_unlock(&uuari->lock);
565 }
566
567 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
568 {
569 switch (state) {
570 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
571 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
572 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
573 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
574 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
575 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
576 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
577 default: return -1;
578 }
579 }
580
581 static int to_mlx5_st(enum ib_qp_type type)
582 {
583 switch (type) {
584 case IB_QPT_RC: return MLX5_QP_ST_RC;
585 case IB_QPT_UC: return MLX5_QP_ST_UC;
586 case IB_QPT_UD: return MLX5_QP_ST_UD;
587 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
588 case IB_QPT_XRC_INI:
589 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
590 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
591 case IB_QPT_GSI: return MLX5_QP_ST_QP1;
592 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
593 case IB_QPT_RAW_PACKET:
594 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
595 case IB_QPT_MAX:
596 default: return -EINVAL;
597 }
598 }
599
600 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
601 {
602 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
603 }
604
605 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
606 struct ib_pd *pd,
607 unsigned long addr, size_t size,
608 struct ib_umem **umem,
609 int *npages, int *page_shift, int *ncont,
610 u32 *offset)
611 {
612 int err;
613
614 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
615 if (IS_ERR(*umem)) {
616 mlx5_ib_dbg(dev, "umem_get failed\n");
617 return PTR_ERR(*umem);
618 }
619
620 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
621
622 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
623 if (err) {
624 mlx5_ib_warn(dev, "bad offset\n");
625 goto err_umem;
626 }
627
628 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
629 addr, size, *npages, *page_shift, *ncont, *offset);
630
631 return 0;
632
633 err_umem:
634 ib_umem_release(*umem);
635 *umem = NULL;
636
637 return err;
638 }
639
640 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
641 struct mlx5_ib_qp *qp, struct ib_udata *udata,
642 struct ib_qp_init_attr *attr,
643 struct mlx5_create_qp_mbox_in **in,
644 struct mlx5_ib_create_qp_resp *resp, int *inlen,
645 struct mlx5_ib_qp_base *base)
646 {
647 struct mlx5_ib_ucontext *context;
648 struct mlx5_ib_create_qp ucmd;
649 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
650 int page_shift = 0;
651 int uar_index;
652 int npages;
653 u32 offset = 0;
654 int uuarn;
655 int ncont = 0;
656 int err;
657
658 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
659 if (err) {
660 mlx5_ib_dbg(dev, "copy failed\n");
661 return err;
662 }
663
664 context = to_mucontext(pd->uobject->context);
665 /*
666 * TBD: should come from the verbs when we have the API
667 */
668 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
669 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
670 uuarn = MLX5_CROSS_CHANNEL_UUAR;
671 else {
672 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
673 if (uuarn < 0) {
674 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
675 mlx5_ib_dbg(dev, "reverting to medium latency\n");
676 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
677 if (uuarn < 0) {
678 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
679 mlx5_ib_dbg(dev, "reverting to high latency\n");
680 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
681 if (uuarn < 0) {
682 mlx5_ib_warn(dev, "uuar allocation failed\n");
683 return uuarn;
684 }
685 }
686 }
687 }
688
689 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
690 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
691
692 qp->rq.offset = 0;
693 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
694 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
695
696 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
697 if (err)
698 goto err_uuar;
699
700 if (ucmd.buf_addr && ubuffer->buf_size) {
701 ubuffer->buf_addr = ucmd.buf_addr;
702 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
703 ubuffer->buf_size,
704 &ubuffer->umem, &npages, &page_shift,
705 &ncont, &offset);
706 if (err)
707 goto err_uuar;
708 } else {
709 ubuffer->umem = NULL;
710 }
711
712 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * ncont;
713 *in = mlx5_vzalloc(*inlen);
714 if (!*in) {
715 err = -ENOMEM;
716 goto err_umem;
717 }
718 if (ubuffer->umem)
719 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift,
720 (*in)->pas, 0);
721 (*in)->ctx.log_pg_sz_remote_qpn =
722 cpu_to_be32((page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
723 (*in)->ctx.params2 = cpu_to_be32(offset << 6);
724
725 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
726 resp->uuar_index = uuarn;
727 qp->uuarn = uuarn;
728
729 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
730 if (err) {
731 mlx5_ib_dbg(dev, "map failed\n");
732 goto err_free;
733 }
734
735 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
736 if (err) {
737 mlx5_ib_dbg(dev, "copy failed\n");
738 goto err_unmap;
739 }
740 qp->create_type = MLX5_QP_USER;
741
742 return 0;
743
744 err_unmap:
745 mlx5_ib_db_unmap_user(context, &qp->db);
746
747 err_free:
748 kvfree(*in);
749
750 err_umem:
751 if (ubuffer->umem)
752 ib_umem_release(ubuffer->umem);
753
754 err_uuar:
755 free_uuar(&context->uuari, uuarn);
756 return err;
757 }
758
759 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
760 struct mlx5_ib_qp_base *base)
761 {
762 struct mlx5_ib_ucontext *context;
763
764 context = to_mucontext(pd->uobject->context);
765 mlx5_ib_db_unmap_user(context, &qp->db);
766 if (base->ubuffer.umem)
767 ib_umem_release(base->ubuffer.umem);
768 free_uuar(&context->uuari, qp->uuarn);
769 }
770
771 static int create_kernel_qp(struct mlx5_ib_dev *dev,
772 struct ib_qp_init_attr *init_attr,
773 struct mlx5_ib_qp *qp,
774 struct mlx5_create_qp_mbox_in **in, int *inlen,
775 struct mlx5_ib_qp_base *base)
776 {
777 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
778 struct mlx5_uuar_info *uuari;
779 int uar_index;
780 int uuarn;
781 int err;
782
783 uuari = &dev->mdev->priv.uuari;
784 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN | IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK))
785 return -EINVAL;
786
787 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
788 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
789
790 uuarn = alloc_uuar(uuari, lc);
791 if (uuarn < 0) {
792 mlx5_ib_dbg(dev, "\n");
793 return -ENOMEM;
794 }
795
796 qp->bf = &uuari->bfs[uuarn];
797 uar_index = qp->bf->uar->index;
798
799 err = calc_sq_size(dev, init_attr, qp);
800 if (err < 0) {
801 mlx5_ib_dbg(dev, "err %d\n", err);
802 goto err_uuar;
803 }
804
805 qp->rq.offset = 0;
806 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
807 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
808
809 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
810 if (err) {
811 mlx5_ib_dbg(dev, "err %d\n", err);
812 goto err_uuar;
813 }
814
815 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
816 *inlen = sizeof(**in) + sizeof(*(*in)->pas) * qp->buf.npages;
817 *in = mlx5_vzalloc(*inlen);
818 if (!*in) {
819 err = -ENOMEM;
820 goto err_buf;
821 }
822 (*in)->ctx.qp_counter_set_usr_page = cpu_to_be32(uar_index);
823 (*in)->ctx.log_pg_sz_remote_qpn =
824 cpu_to_be32((qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT) << 24);
825 /* Set "fast registration enabled" for all kernel QPs */
826 (*in)->ctx.params1 |= cpu_to_be32(1 << 11);
827 (*in)->ctx.sq_crq_size |= cpu_to_be16(1 << 4);
828
829 mlx5_fill_page_array(&qp->buf, (*in)->pas);
830
831 err = mlx5_db_alloc(dev->mdev, &qp->db);
832 if (err) {
833 mlx5_ib_dbg(dev, "err %d\n", err);
834 goto err_free;
835 }
836
837 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
838 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
839 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
840 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
841 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
842
843 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
844 !qp->sq.w_list || !qp->sq.wqe_head) {
845 err = -ENOMEM;
846 goto err_wrid;
847 }
848 qp->create_type = MLX5_QP_KERNEL;
849
850 return 0;
851
852 err_wrid:
853 mlx5_db_free(dev->mdev, &qp->db);
854 kfree(qp->sq.wqe_head);
855 kfree(qp->sq.w_list);
856 kfree(qp->sq.wrid);
857 kfree(qp->sq.wr_data);
858 kfree(qp->rq.wrid);
859
860 err_free:
861 kvfree(*in);
862
863 err_buf:
864 mlx5_buf_free(dev->mdev, &qp->buf);
865
866 err_uuar:
867 free_uuar(&dev->mdev->priv.uuari, uuarn);
868 return err;
869 }
870
871 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
872 {
873 mlx5_db_free(dev->mdev, &qp->db);
874 kfree(qp->sq.wqe_head);
875 kfree(qp->sq.w_list);
876 kfree(qp->sq.wrid);
877 kfree(qp->sq.wr_data);
878 kfree(qp->rq.wrid);
879 mlx5_buf_free(dev->mdev, &qp->buf);
880 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
881 }
882
883 static __be32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
884 {
885 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
886 (attr->qp_type == IB_QPT_XRC_INI))
887 return cpu_to_be32(MLX5_SRQ_RQ);
888 else if (!qp->has_rq)
889 return cpu_to_be32(MLX5_ZERO_LEN_RQ);
890 else
891 return cpu_to_be32(MLX5_NON_ZERO_RQ);
892 }
893
894 static int is_connected(enum ib_qp_type qp_type)
895 {
896 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
897 return 1;
898
899 return 0;
900 }
901
902 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
903 struct mlx5_ib_sq *sq, u32 tdn)
904 {
905 u32 in[MLX5_ST_SZ_DW(create_tis_in)];
906 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
907
908 memset(in, 0, sizeof(in));
909
910 MLX5_SET(tisc, tisc, transport_domain, tdn);
911
912 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
913 }
914
915 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
916 struct mlx5_ib_sq *sq)
917 {
918 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
919 }
920
921 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
922 struct mlx5_ib_sq *sq, void *qpin,
923 struct ib_pd *pd)
924 {
925 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
926 __be64 *pas;
927 void *in;
928 void *sqc;
929 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
930 void *wq;
931 int inlen;
932 int err;
933 int page_shift = 0;
934 int npages;
935 int ncont = 0;
936 u32 offset = 0;
937
938 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
939 &sq->ubuffer.umem, &npages, &page_shift,
940 &ncont, &offset);
941 if (err)
942 return err;
943
944 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
945 in = mlx5_vzalloc(inlen);
946 if (!in) {
947 err = -ENOMEM;
948 goto err_umem;
949 }
950
951 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
952 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
953 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
954 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
955 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
956 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
957 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
958
959 wq = MLX5_ADDR_OF(sqc, sqc, wq);
960 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
961 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
962 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
963 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
964 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
965 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
966 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
967 MLX5_SET(wq, wq, page_offset, offset);
968
969 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
970 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
971
972 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
973
974 kvfree(in);
975
976 if (err)
977 goto err_umem;
978
979 return 0;
980
981 err_umem:
982 ib_umem_release(sq->ubuffer.umem);
983 sq->ubuffer.umem = NULL;
984
985 return err;
986 }
987
988 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
989 struct mlx5_ib_sq *sq)
990 {
991 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
992 ib_umem_release(sq->ubuffer.umem);
993 }
994
995 static int get_rq_pas_size(void *qpc)
996 {
997 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
998 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
999 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1000 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1001 u32 po_quanta = 1 << (log_page_size - 6);
1002 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1003 u32 page_size = 1 << log_page_size;
1004 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1005 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1006
1007 return rq_num_pas * sizeof(u64);
1008 }
1009
1010 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1011 struct mlx5_ib_rq *rq, void *qpin)
1012 {
1013 __be64 *pas;
1014 __be64 *qp_pas;
1015 void *in;
1016 void *rqc;
1017 void *wq;
1018 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1019 int inlen;
1020 int err;
1021 u32 rq_pas_size = get_rq_pas_size(qpc);
1022
1023 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1024 in = mlx5_vzalloc(inlen);
1025 if (!in)
1026 return -ENOMEM;
1027
1028 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1029 MLX5_SET(rqc, rqc, vsd, 1);
1030 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1031 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1032 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1033 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1034 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1035
1036 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1037 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1038 MLX5_SET(wq, wq, end_padding_mode,
1039 MLX5_GET64(qpc, qpc, end_padding_mode));
1040 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1041 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1042 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1043 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1044 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1045 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1046
1047 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1048 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1049 memcpy(pas, qp_pas, rq_pas_size);
1050
1051 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1052
1053 kvfree(in);
1054
1055 return err;
1056 }
1057
1058 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1059 struct mlx5_ib_rq *rq)
1060 {
1061 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1062 }
1063
1064 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1065 struct mlx5_ib_rq *rq, u32 tdn)
1066 {
1067 u32 *in;
1068 void *tirc;
1069 int inlen;
1070 int err;
1071
1072 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1073 in = mlx5_vzalloc(inlen);
1074 if (!in)
1075 return -ENOMEM;
1076
1077 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1078 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1079 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1080 MLX5_SET(tirc, tirc, transport_domain, tdn);
1081
1082 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1083
1084 kvfree(in);
1085
1086 return err;
1087 }
1088
1089 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1090 struct mlx5_ib_rq *rq)
1091 {
1092 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1093 }
1094
1095 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1096 struct mlx5_create_qp_mbox_in *in,
1097 struct ib_pd *pd)
1098 {
1099 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1100 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1101 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1102 struct ib_uobject *uobj = pd->uobject;
1103 struct ib_ucontext *ucontext = uobj->context;
1104 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1105 int err;
1106 u32 tdn = mucontext->tdn;
1107
1108 if (qp->sq.wqe_cnt) {
1109 err = create_raw_packet_qp_tis(dev, sq, tdn);
1110 if (err)
1111 return err;
1112
1113 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1114 if (err)
1115 goto err_destroy_tis;
1116
1117 sq->base.container_mibqp = qp;
1118 }
1119
1120 if (qp->rq.wqe_cnt) {
1121 err = create_raw_packet_qp_rq(dev, rq, in);
1122 if (err)
1123 goto err_destroy_sq;
1124
1125 rq->base.container_mibqp = qp;
1126
1127 err = create_raw_packet_qp_tir(dev, rq, tdn);
1128 if (err)
1129 goto err_destroy_rq;
1130 }
1131
1132 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1133 rq->base.mqp.qpn;
1134
1135 return 0;
1136
1137 err_destroy_rq:
1138 destroy_raw_packet_qp_rq(dev, rq);
1139 err_destroy_sq:
1140 if (!qp->sq.wqe_cnt)
1141 return err;
1142 destroy_raw_packet_qp_sq(dev, sq);
1143 err_destroy_tis:
1144 destroy_raw_packet_qp_tis(dev, sq);
1145
1146 return err;
1147 }
1148
1149 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1150 struct mlx5_ib_qp *qp)
1151 {
1152 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1153 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1154 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1155
1156 if (qp->rq.wqe_cnt) {
1157 destroy_raw_packet_qp_tir(dev, rq);
1158 destroy_raw_packet_qp_rq(dev, rq);
1159 }
1160
1161 if (qp->sq.wqe_cnt) {
1162 destroy_raw_packet_qp_sq(dev, sq);
1163 destroy_raw_packet_qp_tis(dev, sq);
1164 }
1165 }
1166
1167 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1168 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1169 {
1170 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1171 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1172
1173 sq->sq = &qp->sq;
1174 rq->rq = &qp->rq;
1175 sq->doorbell = &qp->db;
1176 rq->doorbell = &qp->db;
1177 }
1178
1179 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1180 struct ib_qp_init_attr *init_attr,
1181 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1182 {
1183 struct mlx5_ib_resources *devr = &dev->devr;
1184 struct mlx5_core_dev *mdev = dev->mdev;
1185 struct mlx5_ib_qp_base *base;
1186 struct mlx5_ib_create_qp_resp resp;
1187 struct mlx5_create_qp_mbox_in *in;
1188 struct mlx5_ib_create_qp ucmd;
1189 int inlen = sizeof(*in);
1190 int err;
1191 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1192 void *qpc;
1193
1194 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1195 &qp->raw_packet_qp.rq.base :
1196 &qp->trans_qp.base;
1197
1198 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1199 mlx5_ib_odp_create_qp(qp);
1200
1201 mutex_init(&qp->mutex);
1202 spin_lock_init(&qp->sq.lock);
1203 spin_lock_init(&qp->rq.lock);
1204
1205 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1206 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1207 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1208 return -EINVAL;
1209 } else {
1210 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1211 }
1212 }
1213
1214 if (init_attr->create_flags &
1215 (IB_QP_CREATE_CROSS_CHANNEL |
1216 IB_QP_CREATE_MANAGED_SEND |
1217 IB_QP_CREATE_MANAGED_RECV)) {
1218 if (!MLX5_CAP_GEN(mdev, cd)) {
1219 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1220 return -EINVAL;
1221 }
1222 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1223 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1224 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1225 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1226 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1227 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1228 }
1229 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1230 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1231
1232 if (pd && pd->uobject) {
1233 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1234 mlx5_ib_dbg(dev, "copy failed\n");
1235 return -EFAULT;
1236 }
1237
1238 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1239 &ucmd, udata->inlen, &uidx);
1240 if (err)
1241 return err;
1242
1243 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1244 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1245 } else {
1246 qp->wq_sig = !!wq_signature;
1247 }
1248
1249 qp->has_rq = qp_has_rq(init_attr);
1250 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1251 qp, (pd && pd->uobject) ? &ucmd : NULL);
1252 if (err) {
1253 mlx5_ib_dbg(dev, "err %d\n", err);
1254 return err;
1255 }
1256
1257 if (pd) {
1258 if (pd->uobject) {
1259 __u32 max_wqes =
1260 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1261 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1262 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1263 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1264 mlx5_ib_dbg(dev, "invalid rq params\n");
1265 return -EINVAL;
1266 }
1267 if (ucmd.sq_wqe_count > max_wqes) {
1268 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1269 ucmd.sq_wqe_count, max_wqes);
1270 return -EINVAL;
1271 }
1272 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1273 &resp, &inlen, base);
1274 if (err)
1275 mlx5_ib_dbg(dev, "err %d\n", err);
1276 } else {
1277 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1278 base);
1279 if (err)
1280 mlx5_ib_dbg(dev, "err %d\n", err);
1281 }
1282
1283 if (err)
1284 return err;
1285 } else {
1286 in = mlx5_vzalloc(sizeof(*in));
1287 if (!in)
1288 return -ENOMEM;
1289
1290 qp->create_type = MLX5_QP_EMPTY;
1291 }
1292
1293 if (is_sqp(init_attr->qp_type))
1294 qp->port = init_attr->port_num;
1295
1296 in->ctx.flags = cpu_to_be32(to_mlx5_st(init_attr->qp_type) << 16 |
1297 MLX5_QP_PM_MIGRATED << 11);
1298
1299 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1300 in->ctx.flags_pd = cpu_to_be32(to_mpd(pd ? pd : devr->p0)->pdn);
1301 else
1302 in->ctx.flags_pd = cpu_to_be32(MLX5_QP_LAT_SENSITIVE);
1303
1304 if (qp->wq_sig)
1305 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_ENABLE_SIG);
1306
1307 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1308 in->ctx.flags_pd |= cpu_to_be32(MLX5_QP_BLOCK_MCAST);
1309
1310 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1311 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_MASTER);
1312 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1313 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_SEND);
1314 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1315 in->ctx.params2 |= cpu_to_be32(MLX5_QP_BIT_CC_SLAVE_RECV);
1316
1317 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1318 int rcqe_sz;
1319 int scqe_sz;
1320
1321 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1322 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1323
1324 if (rcqe_sz == 128)
1325 in->ctx.cs_res = MLX5_RES_SCAT_DATA64_CQE;
1326 else
1327 in->ctx.cs_res = MLX5_RES_SCAT_DATA32_CQE;
1328
1329 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1330 if (scqe_sz == 128)
1331 in->ctx.cs_req = MLX5_REQ_SCAT_DATA64_CQE;
1332 else
1333 in->ctx.cs_req = MLX5_REQ_SCAT_DATA32_CQE;
1334 }
1335 }
1336
1337 if (qp->rq.wqe_cnt) {
1338 in->ctx.rq_size_stride = (qp->rq.wqe_shift - 4);
1339 in->ctx.rq_size_stride |= ilog2(qp->rq.wqe_cnt) << 3;
1340 }
1341
1342 in->ctx.rq_type_srqn = get_rx_type(qp, init_attr);
1343
1344 if (qp->sq.wqe_cnt)
1345 in->ctx.sq_crq_size |= cpu_to_be16(ilog2(qp->sq.wqe_cnt) << 11);
1346 else
1347 in->ctx.sq_crq_size |= cpu_to_be16(0x8000);
1348
1349 /* Set default resources */
1350 switch (init_attr->qp_type) {
1351 case IB_QPT_XRC_TGT:
1352 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1353 in->ctx.cqn_send = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1354 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1355 in->ctx.xrcd = cpu_to_be32(to_mxrcd(init_attr->xrcd)->xrcdn);
1356 break;
1357 case IB_QPT_XRC_INI:
1358 in->ctx.cqn_recv = cpu_to_be32(to_mcq(devr->c0)->mcq.cqn);
1359 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1360 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(devr->s0)->msrq.srqn);
1361 break;
1362 default:
1363 if (init_attr->srq) {
1364 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x0)->xrcdn);
1365 in->ctx.rq_type_srqn |= cpu_to_be32(to_msrq(init_attr->srq)->msrq.srqn);
1366 } else {
1367 in->ctx.xrcd = cpu_to_be32(to_mxrcd(devr->x1)->xrcdn);
1368 in->ctx.rq_type_srqn |=
1369 cpu_to_be32(to_msrq(devr->s1)->msrq.srqn);
1370 }
1371 }
1372
1373 if (init_attr->send_cq)
1374 in->ctx.cqn_send = cpu_to_be32(to_mcq(init_attr->send_cq)->mcq.cqn);
1375
1376 if (init_attr->recv_cq)
1377 in->ctx.cqn_recv = cpu_to_be32(to_mcq(init_attr->recv_cq)->mcq.cqn);
1378
1379 in->ctx.db_rec_addr = cpu_to_be64(qp->db.dma);
1380
1381 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1) {
1382 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1383 /* 0xffffff means we ask to work with cqe version 0 */
1384 MLX5_SET(qpc, qpc, user_index, uidx);
1385 }
1386
1387 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1388 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1389 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1390 err = create_raw_packet_qp(dev, qp, in, pd);
1391 } else {
1392 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1393 }
1394
1395 if (err) {
1396 mlx5_ib_dbg(dev, "create qp failed\n");
1397 goto err_create;
1398 }
1399
1400 kvfree(in);
1401
1402 base->container_mibqp = qp;
1403 base->mqp.event = mlx5_ib_qp_event;
1404
1405 return 0;
1406
1407 err_create:
1408 if (qp->create_type == MLX5_QP_USER)
1409 destroy_qp_user(pd, qp, base);
1410 else if (qp->create_type == MLX5_QP_KERNEL)
1411 destroy_qp_kernel(dev, qp);
1412
1413 kvfree(in);
1414 return err;
1415 }
1416
1417 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1418 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1419 {
1420 if (send_cq) {
1421 if (recv_cq) {
1422 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1423 spin_lock_irq(&send_cq->lock);
1424 spin_lock_nested(&recv_cq->lock,
1425 SINGLE_DEPTH_NESTING);
1426 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1427 spin_lock_irq(&send_cq->lock);
1428 __acquire(&recv_cq->lock);
1429 } else {
1430 spin_lock_irq(&recv_cq->lock);
1431 spin_lock_nested(&send_cq->lock,
1432 SINGLE_DEPTH_NESTING);
1433 }
1434 } else {
1435 spin_lock_irq(&send_cq->lock);
1436 __acquire(&recv_cq->lock);
1437 }
1438 } else if (recv_cq) {
1439 spin_lock_irq(&recv_cq->lock);
1440 __acquire(&send_cq->lock);
1441 } else {
1442 __acquire(&send_cq->lock);
1443 __acquire(&recv_cq->lock);
1444 }
1445 }
1446
1447 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1448 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1449 {
1450 if (send_cq) {
1451 if (recv_cq) {
1452 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1453 spin_unlock(&recv_cq->lock);
1454 spin_unlock_irq(&send_cq->lock);
1455 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1456 __release(&recv_cq->lock);
1457 spin_unlock_irq(&send_cq->lock);
1458 } else {
1459 spin_unlock(&send_cq->lock);
1460 spin_unlock_irq(&recv_cq->lock);
1461 }
1462 } else {
1463 __release(&recv_cq->lock);
1464 spin_unlock_irq(&send_cq->lock);
1465 }
1466 } else if (recv_cq) {
1467 __release(&send_cq->lock);
1468 spin_unlock_irq(&recv_cq->lock);
1469 } else {
1470 __release(&recv_cq->lock);
1471 __release(&send_cq->lock);
1472 }
1473 }
1474
1475 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1476 {
1477 return to_mpd(qp->ibqp.pd);
1478 }
1479
1480 static void get_cqs(struct mlx5_ib_qp *qp,
1481 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1482 {
1483 switch (qp->ibqp.qp_type) {
1484 case IB_QPT_XRC_TGT:
1485 *send_cq = NULL;
1486 *recv_cq = NULL;
1487 break;
1488 case MLX5_IB_QPT_REG_UMR:
1489 case IB_QPT_XRC_INI:
1490 *send_cq = to_mcq(qp->ibqp.send_cq);
1491 *recv_cq = NULL;
1492 break;
1493
1494 case IB_QPT_SMI:
1495 case IB_QPT_GSI:
1496 case IB_QPT_RC:
1497 case IB_QPT_UC:
1498 case IB_QPT_UD:
1499 case IB_QPT_RAW_IPV6:
1500 case IB_QPT_RAW_ETHERTYPE:
1501 case IB_QPT_RAW_PACKET:
1502 *send_cq = to_mcq(qp->ibqp.send_cq);
1503 *recv_cq = to_mcq(qp->ibqp.recv_cq);
1504 break;
1505
1506 case IB_QPT_MAX:
1507 default:
1508 *send_cq = NULL;
1509 *recv_cq = NULL;
1510 break;
1511 }
1512 }
1513
1514 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1515 {
1516 struct mlx5_ib_cq *send_cq, *recv_cq;
1517 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1518 struct mlx5_modify_qp_mbox_in *in;
1519 int err;
1520
1521 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1522 &qp->raw_packet_qp.rq.base :
1523 &qp->trans_qp.base;
1524
1525 in = kzalloc(sizeof(*in), GFP_KERNEL);
1526 if (!in)
1527 return;
1528
1529 if (qp->state != IB_QPS_RESET) {
1530 mlx5_ib_qp_disable_pagefaults(qp);
1531 if (mlx5_core_qp_modify(dev->mdev, to_mlx5_state(qp->state),
1532 MLX5_QP_STATE_RST, in, 0,
1533 &base->mqp))
1534 mlx5_ib_warn(dev, "mlx5_ib: modify QP %06x to RESET failed\n",
1535 base->mqp.qpn);
1536 }
1537
1538 get_cqs(qp, &send_cq, &recv_cq);
1539
1540 if (qp->create_type == MLX5_QP_KERNEL) {
1541 mlx5_ib_lock_cqs(send_cq, recv_cq);
1542 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1543 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1544 if (send_cq != recv_cq)
1545 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1546 NULL);
1547 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1548 }
1549
1550 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1551 destroy_raw_packet_qp(dev, qp);
1552 } else {
1553 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1554 if (err)
1555 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1556 base->mqp.qpn);
1557 }
1558
1559 kfree(in);
1560
1561 if (qp->create_type == MLX5_QP_KERNEL)
1562 destroy_qp_kernel(dev, qp);
1563 else if (qp->create_type == MLX5_QP_USER)
1564 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1565 }
1566
1567 static const char *ib_qp_type_str(enum ib_qp_type type)
1568 {
1569 switch (type) {
1570 case IB_QPT_SMI:
1571 return "IB_QPT_SMI";
1572 case IB_QPT_GSI:
1573 return "IB_QPT_GSI";
1574 case IB_QPT_RC:
1575 return "IB_QPT_RC";
1576 case IB_QPT_UC:
1577 return "IB_QPT_UC";
1578 case IB_QPT_UD:
1579 return "IB_QPT_UD";
1580 case IB_QPT_RAW_IPV6:
1581 return "IB_QPT_RAW_IPV6";
1582 case IB_QPT_RAW_ETHERTYPE:
1583 return "IB_QPT_RAW_ETHERTYPE";
1584 case IB_QPT_XRC_INI:
1585 return "IB_QPT_XRC_INI";
1586 case IB_QPT_XRC_TGT:
1587 return "IB_QPT_XRC_TGT";
1588 case IB_QPT_RAW_PACKET:
1589 return "IB_QPT_RAW_PACKET";
1590 case MLX5_IB_QPT_REG_UMR:
1591 return "MLX5_IB_QPT_REG_UMR";
1592 case IB_QPT_MAX:
1593 default:
1594 return "Invalid QP type";
1595 }
1596 }
1597
1598 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1599 struct ib_qp_init_attr *init_attr,
1600 struct ib_udata *udata)
1601 {
1602 struct mlx5_ib_dev *dev;
1603 struct mlx5_ib_qp *qp;
1604 u16 xrcdn = 0;
1605 int err;
1606
1607 if (pd) {
1608 dev = to_mdev(pd->device);
1609 } else {
1610 /* being cautious here */
1611 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
1612 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
1613 pr_warn("%s: no PD for transport %s\n", __func__,
1614 ib_qp_type_str(init_attr->qp_type));
1615 return ERR_PTR(-EINVAL);
1616 }
1617 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
1618
1619 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1620 if (!pd->uobject) {
1621 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1622 return ERR_PTR(-EINVAL);
1623 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1624 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1625 return ERR_PTR(-EINVAL);
1626 }
1627 }
1628 }
1629
1630 switch (init_attr->qp_type) {
1631 case IB_QPT_XRC_TGT:
1632 case IB_QPT_XRC_INI:
1633 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
1634 mlx5_ib_dbg(dev, "XRC not supported\n");
1635 return ERR_PTR(-ENOSYS);
1636 }
1637 init_attr->recv_cq = NULL;
1638 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
1639 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1640 init_attr->send_cq = NULL;
1641 }
1642
1643 /* fall through */
1644 case IB_QPT_RAW_PACKET:
1645 case IB_QPT_RC:
1646 case IB_QPT_UC:
1647 case IB_QPT_UD:
1648 case IB_QPT_SMI:
1649 case IB_QPT_GSI:
1650 case MLX5_IB_QPT_REG_UMR:
1651 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1652 if (!qp)
1653 return ERR_PTR(-ENOMEM);
1654
1655 err = create_qp_common(dev, pd, init_attr, udata, qp);
1656 if (err) {
1657 mlx5_ib_dbg(dev, "create_qp_common failed\n");
1658 kfree(qp);
1659 return ERR_PTR(err);
1660 }
1661
1662 if (is_qp0(init_attr->qp_type))
1663 qp->ibqp.qp_num = 0;
1664 else if (is_qp1(init_attr->qp_type))
1665 qp->ibqp.qp_num = 1;
1666 else
1667 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
1668
1669 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
1670 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
1671 to_mcq(init_attr->recv_cq)->mcq.cqn,
1672 to_mcq(init_attr->send_cq)->mcq.cqn);
1673
1674 qp->trans_qp.xrcdn = xrcdn;
1675
1676 break;
1677
1678 case IB_QPT_RAW_IPV6:
1679 case IB_QPT_RAW_ETHERTYPE:
1680 case IB_QPT_MAX:
1681 default:
1682 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
1683 init_attr->qp_type);
1684 /* Don't support raw QPs */
1685 return ERR_PTR(-EINVAL);
1686 }
1687
1688 return &qp->ibqp;
1689 }
1690
1691 int mlx5_ib_destroy_qp(struct ib_qp *qp)
1692 {
1693 struct mlx5_ib_dev *dev = to_mdev(qp->device);
1694 struct mlx5_ib_qp *mqp = to_mqp(qp);
1695
1696 destroy_qp_common(dev, mqp);
1697
1698 kfree(mqp);
1699
1700 return 0;
1701 }
1702
1703 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
1704 int attr_mask)
1705 {
1706 u32 hw_access_flags = 0;
1707 u8 dest_rd_atomic;
1708 u32 access_flags;
1709
1710 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1711 dest_rd_atomic = attr->max_dest_rd_atomic;
1712 else
1713 dest_rd_atomic = qp->trans_qp.resp_depth;
1714
1715 if (attr_mask & IB_QP_ACCESS_FLAGS)
1716 access_flags = attr->qp_access_flags;
1717 else
1718 access_flags = qp->trans_qp.atomic_rd_en;
1719
1720 if (!dest_rd_atomic)
1721 access_flags &= IB_ACCESS_REMOTE_WRITE;
1722
1723 if (access_flags & IB_ACCESS_REMOTE_READ)
1724 hw_access_flags |= MLX5_QP_BIT_RRE;
1725 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1726 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
1727 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1728 hw_access_flags |= MLX5_QP_BIT_RWE;
1729
1730 return cpu_to_be32(hw_access_flags);
1731 }
1732
1733 enum {
1734 MLX5_PATH_FLAG_FL = 1 << 0,
1735 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
1736 MLX5_PATH_FLAG_COUNTER = 1 << 2,
1737 };
1738
1739 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
1740 {
1741 if (rate == IB_RATE_PORT_CURRENT) {
1742 return 0;
1743 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
1744 return -EINVAL;
1745 } else {
1746 while (rate != IB_RATE_2_5_GBPS &&
1747 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
1748 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
1749 --rate;
1750 }
1751
1752 return rate + MLX5_STAT_RATE_OFFSET;
1753 }
1754
1755 static int mlx5_set_path(struct mlx5_ib_dev *dev, const struct ib_ah_attr *ah,
1756 struct mlx5_qp_path *path, u8 port, int attr_mask,
1757 u32 path_flags, const struct ib_qp_attr *attr)
1758 {
1759 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
1760 int err;
1761
1762 if (attr_mask & IB_QP_PKEY_INDEX)
1763 path->pkey_index = attr->pkey_index;
1764
1765 if (ah->ah_flags & IB_AH_GRH) {
1766 if (ah->grh.sgid_index >=
1767 dev->mdev->port_caps[port - 1].gid_table_len) {
1768 pr_err("sgid_index (%u) too large. max is %d\n",
1769 ah->grh.sgid_index,
1770 dev->mdev->port_caps[port - 1].gid_table_len);
1771 return -EINVAL;
1772 }
1773 }
1774
1775 if (ll == IB_LINK_LAYER_ETHERNET) {
1776 if (!(ah->ah_flags & IB_AH_GRH))
1777 return -EINVAL;
1778 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
1779 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
1780 ah->grh.sgid_index);
1781 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
1782 } else {
1783 path->fl = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
1784 path->free_ar = (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x80 :
1785 0;
1786 path->rlid = cpu_to_be16(ah->dlid);
1787 path->grh_mlid = ah->src_path_bits & 0x7f;
1788 if (ah->ah_flags & IB_AH_GRH)
1789 path->grh_mlid |= 1 << 7;
1790 path->dci_cfi_prio_sl = ah->sl & 0xf;
1791 }
1792
1793 if (ah->ah_flags & IB_AH_GRH) {
1794 path->mgid_index = ah->grh.sgid_index;
1795 path->hop_limit = ah->grh.hop_limit;
1796 path->tclass_flowlabel =
1797 cpu_to_be32((ah->grh.traffic_class << 20) |
1798 (ah->grh.flow_label));
1799 memcpy(path->rgid, ah->grh.dgid.raw, 16);
1800 }
1801
1802 err = ib_rate_to_mlx5(dev, ah->static_rate);
1803 if (err < 0)
1804 return err;
1805 path->static_rate = err;
1806 path->port = port;
1807
1808 if (attr_mask & IB_QP_TIMEOUT)
1809 path->ackto_lt = attr->timeout << 3;
1810
1811 return 0;
1812 }
1813
1814 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
1815 [MLX5_QP_STATE_INIT] = {
1816 [MLX5_QP_STATE_INIT] = {
1817 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1818 MLX5_QP_OPTPAR_RAE |
1819 MLX5_QP_OPTPAR_RWE |
1820 MLX5_QP_OPTPAR_PKEY_INDEX |
1821 MLX5_QP_OPTPAR_PRI_PORT,
1822 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1823 MLX5_QP_OPTPAR_PKEY_INDEX |
1824 MLX5_QP_OPTPAR_PRI_PORT,
1825 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1826 MLX5_QP_OPTPAR_Q_KEY |
1827 MLX5_QP_OPTPAR_PRI_PORT,
1828 },
1829 [MLX5_QP_STATE_RTR] = {
1830 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1831 MLX5_QP_OPTPAR_RRE |
1832 MLX5_QP_OPTPAR_RAE |
1833 MLX5_QP_OPTPAR_RWE |
1834 MLX5_QP_OPTPAR_PKEY_INDEX,
1835 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1836 MLX5_QP_OPTPAR_RWE |
1837 MLX5_QP_OPTPAR_PKEY_INDEX,
1838 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
1839 MLX5_QP_OPTPAR_Q_KEY,
1840 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
1841 MLX5_QP_OPTPAR_Q_KEY,
1842 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1843 MLX5_QP_OPTPAR_RRE |
1844 MLX5_QP_OPTPAR_RAE |
1845 MLX5_QP_OPTPAR_RWE |
1846 MLX5_QP_OPTPAR_PKEY_INDEX,
1847 },
1848 },
1849 [MLX5_QP_STATE_RTR] = {
1850 [MLX5_QP_STATE_RTS] = {
1851 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1852 MLX5_QP_OPTPAR_RRE |
1853 MLX5_QP_OPTPAR_RAE |
1854 MLX5_QP_OPTPAR_RWE |
1855 MLX5_QP_OPTPAR_PM_STATE |
1856 MLX5_QP_OPTPAR_RNR_TIMEOUT,
1857 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
1858 MLX5_QP_OPTPAR_RWE |
1859 MLX5_QP_OPTPAR_PM_STATE,
1860 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1861 },
1862 },
1863 [MLX5_QP_STATE_RTS] = {
1864 [MLX5_QP_STATE_RTS] = {
1865 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
1866 MLX5_QP_OPTPAR_RAE |
1867 MLX5_QP_OPTPAR_RWE |
1868 MLX5_QP_OPTPAR_RNR_TIMEOUT |
1869 MLX5_QP_OPTPAR_PM_STATE |
1870 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1871 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
1872 MLX5_QP_OPTPAR_PM_STATE |
1873 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
1874 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
1875 MLX5_QP_OPTPAR_SRQN |
1876 MLX5_QP_OPTPAR_CQN_RCV,
1877 },
1878 },
1879 [MLX5_QP_STATE_SQER] = {
1880 [MLX5_QP_STATE_RTS] = {
1881 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
1882 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
1883 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
1884 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
1885 MLX5_QP_OPTPAR_RWE |
1886 MLX5_QP_OPTPAR_RAE |
1887 MLX5_QP_OPTPAR_RRE,
1888 },
1889 },
1890 };
1891
1892 static int ib_nr_to_mlx5_nr(int ib_mask)
1893 {
1894 switch (ib_mask) {
1895 case IB_QP_STATE:
1896 return 0;
1897 case IB_QP_CUR_STATE:
1898 return 0;
1899 case IB_QP_EN_SQD_ASYNC_NOTIFY:
1900 return 0;
1901 case IB_QP_ACCESS_FLAGS:
1902 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
1903 MLX5_QP_OPTPAR_RAE;
1904 case IB_QP_PKEY_INDEX:
1905 return MLX5_QP_OPTPAR_PKEY_INDEX;
1906 case IB_QP_PORT:
1907 return MLX5_QP_OPTPAR_PRI_PORT;
1908 case IB_QP_QKEY:
1909 return MLX5_QP_OPTPAR_Q_KEY;
1910 case IB_QP_AV:
1911 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
1912 MLX5_QP_OPTPAR_PRI_PORT;
1913 case IB_QP_PATH_MTU:
1914 return 0;
1915 case IB_QP_TIMEOUT:
1916 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
1917 case IB_QP_RETRY_CNT:
1918 return MLX5_QP_OPTPAR_RETRY_COUNT;
1919 case IB_QP_RNR_RETRY:
1920 return MLX5_QP_OPTPAR_RNR_RETRY;
1921 case IB_QP_RQ_PSN:
1922 return 0;
1923 case IB_QP_MAX_QP_RD_ATOMIC:
1924 return MLX5_QP_OPTPAR_SRA_MAX;
1925 case IB_QP_ALT_PATH:
1926 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
1927 case IB_QP_MIN_RNR_TIMER:
1928 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
1929 case IB_QP_SQ_PSN:
1930 return 0;
1931 case IB_QP_MAX_DEST_RD_ATOMIC:
1932 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
1933 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
1934 case IB_QP_PATH_MIG_STATE:
1935 return MLX5_QP_OPTPAR_PM_STATE;
1936 case IB_QP_CAP:
1937 return 0;
1938 case IB_QP_DEST_QPN:
1939 return 0;
1940 }
1941 return 0;
1942 }
1943
1944 static int ib_mask_to_mlx5_opt(int ib_mask)
1945 {
1946 int result = 0;
1947 int i;
1948
1949 for (i = 0; i < 8 * sizeof(int); i++) {
1950 if ((1 << i) & ib_mask)
1951 result |= ib_nr_to_mlx5_nr(1 << i);
1952 }
1953
1954 return result;
1955 }
1956
1957 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
1958 const struct ib_qp_attr *attr, int attr_mask,
1959 enum ib_qp_state cur_state, enum ib_qp_state new_state)
1960 {
1961 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
1962 struct mlx5_ib_qp *qp = to_mqp(ibqp);
1963 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1964 struct mlx5_ib_cq *send_cq, *recv_cq;
1965 struct mlx5_qp_context *context;
1966 struct mlx5_modify_qp_mbox_in *in;
1967 struct mlx5_ib_pd *pd;
1968 enum mlx5_qp_state mlx5_cur, mlx5_new;
1969 enum mlx5_qp_optpar optpar;
1970 int sqd_event;
1971 int mlx5_st;
1972 int err;
1973
1974 in = kzalloc(sizeof(*in), GFP_KERNEL);
1975 if (!in)
1976 return -ENOMEM;
1977
1978 context = &in->ctx;
1979 err = to_mlx5_st(ibqp->qp_type);
1980 if (err < 0)
1981 goto out;
1982
1983 context->flags = cpu_to_be32(err << 16);
1984
1985 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
1986 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1987 } else {
1988 switch (attr->path_mig_state) {
1989 case IB_MIG_MIGRATED:
1990 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
1991 break;
1992 case IB_MIG_REARM:
1993 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
1994 break;
1995 case IB_MIG_ARMED:
1996 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
1997 break;
1998 }
1999 }
2000
2001 if (ibqp->qp_type == IB_QPT_GSI || ibqp->qp_type == IB_QPT_SMI) {
2002 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2003 } else if (ibqp->qp_type == IB_QPT_UD ||
2004 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2005 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2006 } else if (attr_mask & IB_QP_PATH_MTU) {
2007 if (attr->path_mtu < IB_MTU_256 ||
2008 attr->path_mtu > IB_MTU_4096) {
2009 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2010 err = -EINVAL;
2011 goto out;
2012 }
2013 context->mtu_msgmax = (attr->path_mtu << 5) |
2014 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2015 }
2016
2017 if (attr_mask & IB_QP_DEST_QPN)
2018 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2019
2020 if (attr_mask & IB_QP_PKEY_INDEX)
2021 context->pri_path.pkey_index = attr->pkey_index;
2022
2023 /* todo implement counter_index functionality */
2024
2025 if (is_sqp(ibqp->qp_type))
2026 context->pri_path.port = qp->port;
2027
2028 if (attr_mask & IB_QP_PORT)
2029 context->pri_path.port = attr->port_num;
2030
2031 if (attr_mask & IB_QP_AV) {
2032 err = mlx5_set_path(dev, &attr->ah_attr, &context->pri_path,
2033 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2034 attr_mask, 0, attr);
2035 if (err)
2036 goto out;
2037 }
2038
2039 if (attr_mask & IB_QP_TIMEOUT)
2040 context->pri_path.ackto_lt |= attr->timeout << 3;
2041
2042 if (attr_mask & IB_QP_ALT_PATH) {
2043 err = mlx5_set_path(dev, &attr->alt_ah_attr, &context->alt_path,
2044 attr->alt_port_num, attr_mask, 0, attr);
2045 if (err)
2046 goto out;
2047 }
2048
2049 pd = get_pd(qp);
2050 get_cqs(qp, &send_cq, &recv_cq);
2051
2052 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2053 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2054 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2055 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2056
2057 if (attr_mask & IB_QP_RNR_RETRY)
2058 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2059
2060 if (attr_mask & IB_QP_RETRY_CNT)
2061 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2062
2063 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2064 if (attr->max_rd_atomic)
2065 context->params1 |=
2066 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2067 }
2068
2069 if (attr_mask & IB_QP_SQ_PSN)
2070 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2071
2072 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2073 if (attr->max_dest_rd_atomic)
2074 context->params2 |=
2075 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2076 }
2077
2078 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2079 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2080
2081 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2082 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2083
2084 if (attr_mask & IB_QP_RQ_PSN)
2085 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2086
2087 if (attr_mask & IB_QP_QKEY)
2088 context->qkey = cpu_to_be32(attr->qkey);
2089
2090 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2091 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2092
2093 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2094 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2095 sqd_event = 1;
2096 else
2097 sqd_event = 0;
2098
2099 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2100 context->sq_crq_size |= cpu_to_be16(1 << 4);
2101
2102
2103 mlx5_cur = to_mlx5_state(cur_state);
2104 mlx5_new = to_mlx5_state(new_state);
2105 mlx5_st = to_mlx5_st(ibqp->qp_type);
2106 if (mlx5_st < 0)
2107 goto out;
2108
2109 /* If moving to a reset or error state, we must disable page faults on
2110 * this QP and flush all current page faults. Otherwise a stale page
2111 * fault may attempt to work on this QP after it is reset and moved
2112 * again to RTS, and may cause the driver and the device to get out of
2113 * sync. */
2114 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2115 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2116 mlx5_ib_qp_disable_pagefaults(qp);
2117
2118 optpar = ib_mask_to_mlx5_opt(attr_mask);
2119 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2120 in->optparam = cpu_to_be32(optpar);
2121 err = mlx5_core_qp_modify(dev->mdev, to_mlx5_state(cur_state),
2122 to_mlx5_state(new_state), in, sqd_event,
2123 &base->mqp);
2124 if (err)
2125 goto out;
2126
2127 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2128 mlx5_ib_qp_enable_pagefaults(qp);
2129
2130 qp->state = new_state;
2131
2132 if (attr_mask & IB_QP_ACCESS_FLAGS)
2133 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2134 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2135 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2136 if (attr_mask & IB_QP_PORT)
2137 qp->port = attr->port_num;
2138 if (attr_mask & IB_QP_ALT_PATH)
2139 qp->trans_qp.alt_port = attr->alt_port_num;
2140
2141 /*
2142 * If we moved a kernel QP to RESET, clean up all old CQ
2143 * entries and reinitialize the QP.
2144 */
2145 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2146 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2147 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2148 if (send_cq != recv_cq)
2149 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2150
2151 qp->rq.head = 0;
2152 qp->rq.tail = 0;
2153 qp->sq.head = 0;
2154 qp->sq.tail = 0;
2155 qp->sq.cur_post = 0;
2156 qp->sq.last_poll = 0;
2157 qp->db.db[MLX5_RCV_DBR] = 0;
2158 qp->db.db[MLX5_SND_DBR] = 0;
2159 }
2160
2161 out:
2162 kfree(in);
2163 return err;
2164 }
2165
2166 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2167 int attr_mask, struct ib_udata *udata)
2168 {
2169 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2170 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2171 enum ib_qp_state cur_state, new_state;
2172 int err = -EINVAL;
2173 int port;
2174 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2175
2176 mutex_lock(&qp->mutex);
2177
2178 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2179 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2180
2181 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2182 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2183 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2184 }
2185
2186 if (ibqp->qp_type == IB_QPT_RAW_PACKET) {
2187 err = -EOPNOTSUPP;
2188 goto out;
2189 }
2190
2191 if (ibqp->qp_type != MLX5_IB_QPT_REG_UMR &&
2192 !ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
2193 ll))
2194 goto out;
2195
2196 if ((attr_mask & IB_QP_PORT) &&
2197 (attr->port_num == 0 ||
2198 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports)))
2199 goto out;
2200
2201 if (attr_mask & IB_QP_PKEY_INDEX) {
2202 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2203 if (attr->pkey_index >=
2204 dev->mdev->port_caps[port - 1].pkey_table_len)
2205 goto out;
2206 }
2207
2208 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2209 attr->max_rd_atomic >
2210 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp)))
2211 goto out;
2212
2213 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2214 attr->max_dest_rd_atomic >
2215 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp)))
2216 goto out;
2217
2218 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2219 err = 0;
2220 goto out;
2221 }
2222
2223 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2224
2225 out:
2226 mutex_unlock(&qp->mutex);
2227 return err;
2228 }
2229
2230 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2231 {
2232 struct mlx5_ib_cq *cq;
2233 unsigned cur;
2234
2235 cur = wq->head - wq->tail;
2236 if (likely(cur + nreq < wq->max_post))
2237 return 0;
2238
2239 cq = to_mcq(ib_cq);
2240 spin_lock(&cq->lock);
2241 cur = wq->head - wq->tail;
2242 spin_unlock(&cq->lock);
2243
2244 return cur + nreq >= wq->max_post;
2245 }
2246
2247 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2248 u64 remote_addr, u32 rkey)
2249 {
2250 rseg->raddr = cpu_to_be64(remote_addr);
2251 rseg->rkey = cpu_to_be32(rkey);
2252 rseg->reserved = 0;
2253 }
2254
2255 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2256 struct ib_send_wr *wr)
2257 {
2258 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2259 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2260 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2261 }
2262
2263 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2264 {
2265 dseg->byte_count = cpu_to_be32(sg->length);
2266 dseg->lkey = cpu_to_be32(sg->lkey);
2267 dseg->addr = cpu_to_be64(sg->addr);
2268 }
2269
2270 static __be16 get_klm_octo(int npages)
2271 {
2272 return cpu_to_be16(ALIGN(npages, 8) / 2);
2273 }
2274
2275 static __be64 frwr_mkey_mask(void)
2276 {
2277 u64 result;
2278
2279 result = MLX5_MKEY_MASK_LEN |
2280 MLX5_MKEY_MASK_PAGE_SIZE |
2281 MLX5_MKEY_MASK_START_ADDR |
2282 MLX5_MKEY_MASK_EN_RINVAL |
2283 MLX5_MKEY_MASK_KEY |
2284 MLX5_MKEY_MASK_LR |
2285 MLX5_MKEY_MASK_LW |
2286 MLX5_MKEY_MASK_RR |
2287 MLX5_MKEY_MASK_RW |
2288 MLX5_MKEY_MASK_A |
2289 MLX5_MKEY_MASK_SMALL_FENCE |
2290 MLX5_MKEY_MASK_FREE;
2291
2292 return cpu_to_be64(result);
2293 }
2294
2295 static __be64 sig_mkey_mask(void)
2296 {
2297 u64 result;
2298
2299 result = MLX5_MKEY_MASK_LEN |
2300 MLX5_MKEY_MASK_PAGE_SIZE |
2301 MLX5_MKEY_MASK_START_ADDR |
2302 MLX5_MKEY_MASK_EN_SIGERR |
2303 MLX5_MKEY_MASK_EN_RINVAL |
2304 MLX5_MKEY_MASK_KEY |
2305 MLX5_MKEY_MASK_LR |
2306 MLX5_MKEY_MASK_LW |
2307 MLX5_MKEY_MASK_RR |
2308 MLX5_MKEY_MASK_RW |
2309 MLX5_MKEY_MASK_SMALL_FENCE |
2310 MLX5_MKEY_MASK_FREE |
2311 MLX5_MKEY_MASK_BSF_EN;
2312
2313 return cpu_to_be64(result);
2314 }
2315
2316 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
2317 struct mlx5_ib_mr *mr)
2318 {
2319 int ndescs = mr->ndescs;
2320
2321 memset(umr, 0, sizeof(*umr));
2322 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
2323 umr->klm_octowords = get_klm_octo(ndescs);
2324 umr->mkey_mask = frwr_mkey_mask();
2325 }
2326
2327 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
2328 {
2329 memset(umr, 0, sizeof(*umr));
2330 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
2331 umr->flags = 1 << 7;
2332 }
2333
2334 static __be64 get_umr_reg_mr_mask(void)
2335 {
2336 u64 result;
2337
2338 result = MLX5_MKEY_MASK_LEN |
2339 MLX5_MKEY_MASK_PAGE_SIZE |
2340 MLX5_MKEY_MASK_START_ADDR |
2341 MLX5_MKEY_MASK_PD |
2342 MLX5_MKEY_MASK_LR |
2343 MLX5_MKEY_MASK_LW |
2344 MLX5_MKEY_MASK_KEY |
2345 MLX5_MKEY_MASK_RR |
2346 MLX5_MKEY_MASK_RW |
2347 MLX5_MKEY_MASK_A |
2348 MLX5_MKEY_MASK_FREE;
2349
2350 return cpu_to_be64(result);
2351 }
2352
2353 static __be64 get_umr_unreg_mr_mask(void)
2354 {
2355 u64 result;
2356
2357 result = MLX5_MKEY_MASK_FREE;
2358
2359 return cpu_to_be64(result);
2360 }
2361
2362 static __be64 get_umr_update_mtt_mask(void)
2363 {
2364 u64 result;
2365
2366 result = MLX5_MKEY_MASK_FREE;
2367
2368 return cpu_to_be64(result);
2369 }
2370
2371 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2372 struct ib_send_wr *wr)
2373 {
2374 struct mlx5_umr_wr *umrwr = umr_wr(wr);
2375
2376 memset(umr, 0, sizeof(*umr));
2377
2378 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
2379 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
2380 else
2381 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
2382
2383 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
2384 umr->klm_octowords = get_klm_octo(umrwr->npages);
2385 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
2386 umr->mkey_mask = get_umr_update_mtt_mask();
2387 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
2388 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
2389 } else {
2390 umr->mkey_mask = get_umr_reg_mr_mask();
2391 }
2392 } else {
2393 umr->mkey_mask = get_umr_unreg_mr_mask();
2394 }
2395
2396 if (!wr->num_sge)
2397 umr->flags |= MLX5_UMR_INLINE;
2398 }
2399
2400 static u8 get_umr_flags(int acc)
2401 {
2402 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
2403 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
2404 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
2405 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
2406 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
2407 }
2408
2409 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
2410 struct mlx5_ib_mr *mr,
2411 u32 key, int access)
2412 {
2413 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
2414
2415 memset(seg, 0, sizeof(*seg));
2416 seg->flags = get_umr_flags(access) | MLX5_ACCESS_MODE_MTT;
2417 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
2418 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
2419 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
2420 seg->len = cpu_to_be64(mr->ibmr.length);
2421 seg->xlt_oct_size = cpu_to_be32(ndescs);
2422 seg->log2_page_size = ilog2(mr->ibmr.page_size);
2423 }
2424
2425 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
2426 {
2427 memset(seg, 0, sizeof(*seg));
2428 seg->status = MLX5_MKEY_STATUS_FREE;
2429 }
2430
2431 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
2432 {
2433 struct mlx5_umr_wr *umrwr = umr_wr(wr);
2434
2435 memset(seg, 0, sizeof(*seg));
2436 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
2437 seg->status = MLX5_MKEY_STATUS_FREE;
2438 return;
2439 }
2440
2441 seg->flags = convert_access(umrwr->access_flags);
2442 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
2443 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
2444 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
2445 }
2446 seg->len = cpu_to_be64(umrwr->length);
2447 seg->log2_page_size = umrwr->page_shift;
2448 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
2449 mlx5_mkey_variant(umrwr->mkey));
2450 }
2451
2452 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
2453 struct mlx5_ib_mr *mr,
2454 struct mlx5_ib_pd *pd)
2455 {
2456 int bcount = mr->desc_size * mr->ndescs;
2457
2458 dseg->addr = cpu_to_be64(mr->desc_map);
2459 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
2460 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
2461 }
2462
2463 static __be32 send_ieth(struct ib_send_wr *wr)
2464 {
2465 switch (wr->opcode) {
2466 case IB_WR_SEND_WITH_IMM:
2467 case IB_WR_RDMA_WRITE_WITH_IMM:
2468 return wr->ex.imm_data;
2469
2470 case IB_WR_SEND_WITH_INV:
2471 return cpu_to_be32(wr->ex.invalidate_rkey);
2472
2473 default:
2474 return 0;
2475 }
2476 }
2477
2478 static u8 calc_sig(void *wqe, int size)
2479 {
2480 u8 *p = wqe;
2481 u8 res = 0;
2482 int i;
2483
2484 for (i = 0; i < size; i++)
2485 res ^= p[i];
2486
2487 return ~res;
2488 }
2489
2490 static u8 wq_sig(void *wqe)
2491 {
2492 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
2493 }
2494
2495 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
2496 void *wqe, int *sz)
2497 {
2498 struct mlx5_wqe_inline_seg *seg;
2499 void *qend = qp->sq.qend;
2500 void *addr;
2501 int inl = 0;
2502 int copy;
2503 int len;
2504 int i;
2505
2506 seg = wqe;
2507 wqe += sizeof(*seg);
2508 for (i = 0; i < wr->num_sge; i++) {
2509 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
2510 len = wr->sg_list[i].length;
2511 inl += len;
2512
2513 if (unlikely(inl > qp->max_inline_data))
2514 return -ENOMEM;
2515
2516 if (unlikely(wqe + len > qend)) {
2517 copy = qend - wqe;
2518 memcpy(wqe, addr, copy);
2519 addr += copy;
2520 len -= copy;
2521 wqe = mlx5_get_send_wqe(qp, 0);
2522 }
2523 memcpy(wqe, addr, len);
2524 wqe += len;
2525 }
2526
2527 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
2528
2529 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
2530
2531 return 0;
2532 }
2533
2534 static u16 prot_field_size(enum ib_signature_type type)
2535 {
2536 switch (type) {
2537 case IB_SIG_TYPE_T10_DIF:
2538 return MLX5_DIF_SIZE;
2539 default:
2540 return 0;
2541 }
2542 }
2543
2544 static u8 bs_selector(int block_size)
2545 {
2546 switch (block_size) {
2547 case 512: return 0x1;
2548 case 520: return 0x2;
2549 case 4096: return 0x3;
2550 case 4160: return 0x4;
2551 case 1073741824: return 0x5;
2552 default: return 0;
2553 }
2554 }
2555
2556 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
2557 struct mlx5_bsf_inl *inl)
2558 {
2559 /* Valid inline section and allow BSF refresh */
2560 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
2561 MLX5_BSF_REFRESH_DIF);
2562 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
2563 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
2564 /* repeating block */
2565 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
2566 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
2567 MLX5_DIF_CRC : MLX5_DIF_IPCS;
2568
2569 if (domain->sig.dif.ref_remap)
2570 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
2571
2572 if (domain->sig.dif.app_escape) {
2573 if (domain->sig.dif.ref_escape)
2574 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
2575 else
2576 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
2577 }
2578
2579 inl->dif_app_bitmask_check =
2580 cpu_to_be16(domain->sig.dif.apptag_check_mask);
2581 }
2582
2583 static int mlx5_set_bsf(struct ib_mr *sig_mr,
2584 struct ib_sig_attrs *sig_attrs,
2585 struct mlx5_bsf *bsf, u32 data_size)
2586 {
2587 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
2588 struct mlx5_bsf_basic *basic = &bsf->basic;
2589 struct ib_sig_domain *mem = &sig_attrs->mem;
2590 struct ib_sig_domain *wire = &sig_attrs->wire;
2591
2592 memset(bsf, 0, sizeof(*bsf));
2593
2594 /* Basic + Extended + Inline */
2595 basic->bsf_size_sbs = 1 << 7;
2596 /* Input domain check byte mask */
2597 basic->check_byte_mask = sig_attrs->check_mask;
2598 basic->raw_data_size = cpu_to_be32(data_size);
2599
2600 /* Memory domain */
2601 switch (sig_attrs->mem.sig_type) {
2602 case IB_SIG_TYPE_NONE:
2603 break;
2604 case IB_SIG_TYPE_T10_DIF:
2605 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
2606 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
2607 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
2608 break;
2609 default:
2610 return -EINVAL;
2611 }
2612
2613 /* Wire domain */
2614 switch (sig_attrs->wire.sig_type) {
2615 case IB_SIG_TYPE_NONE:
2616 break;
2617 case IB_SIG_TYPE_T10_DIF:
2618 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
2619 mem->sig_type == wire->sig_type) {
2620 /* Same block structure */
2621 basic->bsf_size_sbs |= 1 << 4;
2622 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
2623 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
2624 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
2625 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
2626 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
2627 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
2628 } else
2629 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
2630
2631 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
2632 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
2633 break;
2634 default:
2635 return -EINVAL;
2636 }
2637
2638 return 0;
2639 }
2640
2641 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
2642 struct mlx5_ib_qp *qp, void **seg, int *size)
2643 {
2644 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
2645 struct ib_mr *sig_mr = wr->sig_mr;
2646 struct mlx5_bsf *bsf;
2647 u32 data_len = wr->wr.sg_list->length;
2648 u32 data_key = wr->wr.sg_list->lkey;
2649 u64 data_va = wr->wr.sg_list->addr;
2650 int ret;
2651 int wqe_size;
2652
2653 if (!wr->prot ||
2654 (data_key == wr->prot->lkey &&
2655 data_va == wr->prot->addr &&
2656 data_len == wr->prot->length)) {
2657 /**
2658 * Source domain doesn't contain signature information
2659 * or data and protection are interleaved in memory.
2660 * So need construct:
2661 * ------------------
2662 * | data_klm |
2663 * ------------------
2664 * | BSF |
2665 * ------------------
2666 **/
2667 struct mlx5_klm *data_klm = *seg;
2668
2669 data_klm->bcount = cpu_to_be32(data_len);
2670 data_klm->key = cpu_to_be32(data_key);
2671 data_klm->va = cpu_to_be64(data_va);
2672 wqe_size = ALIGN(sizeof(*data_klm), 64);
2673 } else {
2674 /**
2675 * Source domain contains signature information
2676 * So need construct a strided block format:
2677 * ---------------------------
2678 * | stride_block_ctrl |
2679 * ---------------------------
2680 * | data_klm |
2681 * ---------------------------
2682 * | prot_klm |
2683 * ---------------------------
2684 * | BSF |
2685 * ---------------------------
2686 **/
2687 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
2688 struct mlx5_stride_block_entry *data_sentry;
2689 struct mlx5_stride_block_entry *prot_sentry;
2690 u32 prot_key = wr->prot->lkey;
2691 u64 prot_va = wr->prot->addr;
2692 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
2693 int prot_size;
2694
2695 sblock_ctrl = *seg;
2696 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
2697 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
2698
2699 prot_size = prot_field_size(sig_attrs->mem.sig_type);
2700 if (!prot_size) {
2701 pr_err("Bad block size given: %u\n", block_size);
2702 return -EINVAL;
2703 }
2704 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
2705 prot_size);
2706 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
2707 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
2708 sblock_ctrl->num_entries = cpu_to_be16(2);
2709
2710 data_sentry->bcount = cpu_to_be16(block_size);
2711 data_sentry->key = cpu_to_be32(data_key);
2712 data_sentry->va = cpu_to_be64(data_va);
2713 data_sentry->stride = cpu_to_be16(block_size);
2714
2715 prot_sentry->bcount = cpu_to_be16(prot_size);
2716 prot_sentry->key = cpu_to_be32(prot_key);
2717 prot_sentry->va = cpu_to_be64(prot_va);
2718 prot_sentry->stride = cpu_to_be16(prot_size);
2719
2720 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
2721 sizeof(*prot_sentry), 64);
2722 }
2723
2724 *seg += wqe_size;
2725 *size += wqe_size / 16;
2726 if (unlikely((*seg == qp->sq.qend)))
2727 *seg = mlx5_get_send_wqe(qp, 0);
2728
2729 bsf = *seg;
2730 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
2731 if (ret)
2732 return -EINVAL;
2733
2734 *seg += sizeof(*bsf);
2735 *size += sizeof(*bsf) / 16;
2736 if (unlikely((*seg == qp->sq.qend)))
2737 *seg = mlx5_get_send_wqe(qp, 0);
2738
2739 return 0;
2740 }
2741
2742 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
2743 struct ib_sig_handover_wr *wr, u32 nelements,
2744 u32 length, u32 pdn)
2745 {
2746 struct ib_mr *sig_mr = wr->sig_mr;
2747 u32 sig_key = sig_mr->rkey;
2748 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
2749
2750 memset(seg, 0, sizeof(*seg));
2751
2752 seg->flags = get_umr_flags(wr->access_flags) |
2753 MLX5_ACCESS_MODE_KLM;
2754 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
2755 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
2756 MLX5_MKEY_BSF_EN | pdn);
2757 seg->len = cpu_to_be64(length);
2758 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
2759 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
2760 }
2761
2762 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
2763 u32 nelements)
2764 {
2765 memset(umr, 0, sizeof(*umr));
2766
2767 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
2768 umr->klm_octowords = get_klm_octo(nelements);
2769 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
2770 umr->mkey_mask = sig_mkey_mask();
2771 }
2772
2773
2774 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
2775 void **seg, int *size)
2776 {
2777 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
2778 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
2779 u32 pdn = get_pd(qp)->pdn;
2780 u32 klm_oct_size;
2781 int region_len, ret;
2782
2783 if (unlikely(wr->wr.num_sge != 1) ||
2784 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
2785 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
2786 unlikely(!sig_mr->sig->sig_status_checked))
2787 return -EINVAL;
2788
2789 /* length of the protected region, data + protection */
2790 region_len = wr->wr.sg_list->length;
2791 if (wr->prot &&
2792 (wr->prot->lkey != wr->wr.sg_list->lkey ||
2793 wr->prot->addr != wr->wr.sg_list->addr ||
2794 wr->prot->length != wr->wr.sg_list->length))
2795 region_len += wr->prot->length;
2796
2797 /**
2798 * KLM octoword size - if protection was provided
2799 * then we use strided block format (3 octowords),
2800 * else we use single KLM (1 octoword)
2801 **/
2802 klm_oct_size = wr->prot ? 3 : 1;
2803
2804 set_sig_umr_segment(*seg, klm_oct_size);
2805 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2806 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2807 if (unlikely((*seg == qp->sq.qend)))
2808 *seg = mlx5_get_send_wqe(qp, 0);
2809
2810 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
2811 *seg += sizeof(struct mlx5_mkey_seg);
2812 *size += sizeof(struct mlx5_mkey_seg) / 16;
2813 if (unlikely((*seg == qp->sq.qend)))
2814 *seg = mlx5_get_send_wqe(qp, 0);
2815
2816 ret = set_sig_data_segment(wr, qp, seg, size);
2817 if (ret)
2818 return ret;
2819
2820 sig_mr->sig->sig_status_checked = false;
2821 return 0;
2822 }
2823
2824 static int set_psv_wr(struct ib_sig_domain *domain,
2825 u32 psv_idx, void **seg, int *size)
2826 {
2827 struct mlx5_seg_set_psv *psv_seg = *seg;
2828
2829 memset(psv_seg, 0, sizeof(*psv_seg));
2830 psv_seg->psv_num = cpu_to_be32(psv_idx);
2831 switch (domain->sig_type) {
2832 case IB_SIG_TYPE_NONE:
2833 break;
2834 case IB_SIG_TYPE_T10_DIF:
2835 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
2836 domain->sig.dif.app_tag);
2837 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
2838 break;
2839 default:
2840 pr_err("Bad signature type given.\n");
2841 return 1;
2842 }
2843
2844 *seg += sizeof(*psv_seg);
2845 *size += sizeof(*psv_seg) / 16;
2846
2847 return 0;
2848 }
2849
2850 static int set_reg_wr(struct mlx5_ib_qp *qp,
2851 struct ib_reg_wr *wr,
2852 void **seg, int *size)
2853 {
2854 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
2855 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
2856
2857 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
2858 mlx5_ib_warn(to_mdev(qp->ibqp.device),
2859 "Invalid IB_SEND_INLINE send flag\n");
2860 return -EINVAL;
2861 }
2862
2863 set_reg_umr_seg(*seg, mr);
2864 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2865 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2866 if (unlikely((*seg == qp->sq.qend)))
2867 *seg = mlx5_get_send_wqe(qp, 0);
2868
2869 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
2870 *seg += sizeof(struct mlx5_mkey_seg);
2871 *size += sizeof(struct mlx5_mkey_seg) / 16;
2872 if (unlikely((*seg == qp->sq.qend)))
2873 *seg = mlx5_get_send_wqe(qp, 0);
2874
2875 set_reg_data_seg(*seg, mr, pd);
2876 *seg += sizeof(struct mlx5_wqe_data_seg);
2877 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
2878
2879 return 0;
2880 }
2881
2882 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
2883 {
2884 set_linv_umr_seg(*seg);
2885 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
2886 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
2887 if (unlikely((*seg == qp->sq.qend)))
2888 *seg = mlx5_get_send_wqe(qp, 0);
2889 set_linv_mkey_seg(*seg);
2890 *seg += sizeof(struct mlx5_mkey_seg);
2891 *size += sizeof(struct mlx5_mkey_seg) / 16;
2892 if (unlikely((*seg == qp->sq.qend)))
2893 *seg = mlx5_get_send_wqe(qp, 0);
2894 }
2895
2896 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
2897 {
2898 __be32 *p = NULL;
2899 int tidx = idx;
2900 int i, j;
2901
2902 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
2903 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
2904 if ((i & 0xf) == 0) {
2905 void *buf = mlx5_get_send_wqe(qp, tidx);
2906 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
2907 p = buf;
2908 j = 0;
2909 }
2910 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
2911 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
2912 be32_to_cpu(p[j + 3]));
2913 }
2914 }
2915
2916 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
2917 unsigned bytecnt, struct mlx5_ib_qp *qp)
2918 {
2919 while (bytecnt > 0) {
2920 __iowrite64_copy(dst++, src++, 8);
2921 __iowrite64_copy(dst++, src++, 8);
2922 __iowrite64_copy(dst++, src++, 8);
2923 __iowrite64_copy(dst++, src++, 8);
2924 __iowrite64_copy(dst++, src++, 8);
2925 __iowrite64_copy(dst++, src++, 8);
2926 __iowrite64_copy(dst++, src++, 8);
2927 __iowrite64_copy(dst++, src++, 8);
2928 bytecnt -= 64;
2929 if (unlikely(src == qp->sq.qend))
2930 src = mlx5_get_send_wqe(qp, 0);
2931 }
2932 }
2933
2934 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
2935 {
2936 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
2937 wr->send_flags & IB_SEND_FENCE))
2938 return MLX5_FENCE_MODE_STRONG_ORDERING;
2939
2940 if (unlikely(fence)) {
2941 if (wr->send_flags & IB_SEND_FENCE)
2942 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
2943 else
2944 return fence;
2945
2946 } else {
2947 return 0;
2948 }
2949 }
2950
2951 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
2952 struct mlx5_wqe_ctrl_seg **ctrl,
2953 struct ib_send_wr *wr, unsigned *idx,
2954 int *size, int nreq)
2955 {
2956 int err = 0;
2957
2958 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq))) {
2959 err = -ENOMEM;
2960 return err;
2961 }
2962
2963 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
2964 *seg = mlx5_get_send_wqe(qp, *idx);
2965 *ctrl = *seg;
2966 *(uint32_t *)(*seg + 8) = 0;
2967 (*ctrl)->imm = send_ieth(wr);
2968 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
2969 (wr->send_flags & IB_SEND_SIGNALED ?
2970 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
2971 (wr->send_flags & IB_SEND_SOLICITED ?
2972 MLX5_WQE_CTRL_SOLICITED : 0);
2973
2974 *seg += sizeof(**ctrl);
2975 *size = sizeof(**ctrl) / 16;
2976
2977 return err;
2978 }
2979
2980 static void finish_wqe(struct mlx5_ib_qp *qp,
2981 struct mlx5_wqe_ctrl_seg *ctrl,
2982 u8 size, unsigned idx, u64 wr_id,
2983 int nreq, u8 fence, u8 next_fence,
2984 u32 mlx5_opcode)
2985 {
2986 u8 opmod = 0;
2987
2988 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
2989 mlx5_opcode | ((u32)opmod << 24));
2990 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
2991 ctrl->fm_ce_se |= fence;
2992 qp->fm_cache = next_fence;
2993 if (unlikely(qp->wq_sig))
2994 ctrl->signature = wq_sig(ctrl);
2995
2996 qp->sq.wrid[idx] = wr_id;
2997 qp->sq.w_list[idx].opcode = mlx5_opcode;
2998 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
2999 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3000 qp->sq.w_list[idx].next = qp->sq.cur_post;
3001 }
3002
3003
3004 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3005 struct ib_send_wr **bad_wr)
3006 {
3007 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3008 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3009 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3010 struct mlx5_ib_mr *mr;
3011 struct mlx5_wqe_data_seg *dpseg;
3012 struct mlx5_wqe_xrc_seg *xrc;
3013 struct mlx5_bf *bf = qp->bf;
3014 int uninitialized_var(size);
3015 void *qend = qp->sq.qend;
3016 unsigned long flags;
3017 unsigned idx;
3018 int err = 0;
3019 int inl = 0;
3020 int num_sge;
3021 void *seg;
3022 int nreq;
3023 int i;
3024 u8 next_fence = 0;
3025 u8 fence;
3026
3027 spin_lock_irqsave(&qp->sq.lock, flags);
3028
3029 for (nreq = 0; wr; nreq++, wr = wr->next) {
3030 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3031 mlx5_ib_warn(dev, "\n");
3032 err = -EINVAL;
3033 *bad_wr = wr;
3034 goto out;
3035 }
3036
3037 fence = qp->fm_cache;
3038 num_sge = wr->num_sge;
3039 if (unlikely(num_sge > qp->sq.max_gs)) {
3040 mlx5_ib_warn(dev, "\n");
3041 err = -ENOMEM;
3042 *bad_wr = wr;
3043 goto out;
3044 }
3045
3046 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3047 if (err) {
3048 mlx5_ib_warn(dev, "\n");
3049 err = -ENOMEM;
3050 *bad_wr = wr;
3051 goto out;
3052 }
3053
3054 switch (ibqp->qp_type) {
3055 case IB_QPT_XRC_INI:
3056 xrc = seg;
3057 seg += sizeof(*xrc);
3058 size += sizeof(*xrc) / 16;
3059 /* fall through */
3060 case IB_QPT_RC:
3061 switch (wr->opcode) {
3062 case IB_WR_RDMA_READ:
3063 case IB_WR_RDMA_WRITE:
3064 case IB_WR_RDMA_WRITE_WITH_IMM:
3065 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3066 rdma_wr(wr)->rkey);
3067 seg += sizeof(struct mlx5_wqe_raddr_seg);
3068 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3069 break;
3070
3071 case IB_WR_ATOMIC_CMP_AND_SWP:
3072 case IB_WR_ATOMIC_FETCH_AND_ADD:
3073 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3074 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3075 err = -ENOSYS;
3076 *bad_wr = wr;
3077 goto out;
3078
3079 case IB_WR_LOCAL_INV:
3080 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3081 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3082 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3083 set_linv_wr(qp, &seg, &size);
3084 num_sge = 0;
3085 break;
3086
3087 case IB_WR_REG_MR:
3088 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3089 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3090 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3091 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3092 if (err) {
3093 *bad_wr = wr;
3094 goto out;
3095 }
3096 num_sge = 0;
3097 break;
3098
3099 case IB_WR_REG_SIG_MR:
3100 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3101 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3102
3103 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3104 err = set_sig_umr_wr(wr, qp, &seg, &size);
3105 if (err) {
3106 mlx5_ib_warn(dev, "\n");
3107 *bad_wr = wr;
3108 goto out;
3109 }
3110
3111 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3112 nreq, get_fence(fence, wr),
3113 next_fence, MLX5_OPCODE_UMR);
3114 /*
3115 * SET_PSV WQEs are not signaled and solicited
3116 * on error
3117 */
3118 wr->send_flags &= ~IB_SEND_SIGNALED;
3119 wr->send_flags |= IB_SEND_SOLICITED;
3120 err = begin_wqe(qp, &seg, &ctrl, wr,
3121 &idx, &size, nreq);
3122 if (err) {
3123 mlx5_ib_warn(dev, "\n");
3124 err = -ENOMEM;
3125 *bad_wr = wr;
3126 goto out;
3127 }
3128
3129 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3130 mr->sig->psv_memory.psv_idx, &seg,
3131 &size);
3132 if (err) {
3133 mlx5_ib_warn(dev, "\n");
3134 *bad_wr = wr;
3135 goto out;
3136 }
3137
3138 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3139 nreq, get_fence(fence, wr),
3140 next_fence, MLX5_OPCODE_SET_PSV);
3141 err = begin_wqe(qp, &seg, &ctrl, wr,
3142 &idx, &size, nreq);
3143 if (err) {
3144 mlx5_ib_warn(dev, "\n");
3145 err = -ENOMEM;
3146 *bad_wr = wr;
3147 goto out;
3148 }
3149
3150 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3151 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3152 mr->sig->psv_wire.psv_idx, &seg,
3153 &size);
3154 if (err) {
3155 mlx5_ib_warn(dev, "\n");
3156 *bad_wr = wr;
3157 goto out;
3158 }
3159
3160 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3161 nreq, get_fence(fence, wr),
3162 next_fence, MLX5_OPCODE_SET_PSV);
3163 num_sge = 0;
3164 goto skip_psv;
3165
3166 default:
3167 break;
3168 }
3169 break;
3170
3171 case IB_QPT_UC:
3172 switch (wr->opcode) {
3173 case IB_WR_RDMA_WRITE:
3174 case IB_WR_RDMA_WRITE_WITH_IMM:
3175 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3176 rdma_wr(wr)->rkey);
3177 seg += sizeof(struct mlx5_wqe_raddr_seg);
3178 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3179 break;
3180
3181 default:
3182 break;
3183 }
3184 break;
3185
3186 case IB_QPT_UD:
3187 case IB_QPT_SMI:
3188 case IB_QPT_GSI:
3189 set_datagram_seg(seg, wr);
3190 seg += sizeof(struct mlx5_wqe_datagram_seg);
3191 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3192 if (unlikely((seg == qend)))
3193 seg = mlx5_get_send_wqe(qp, 0);
3194 break;
3195
3196 case MLX5_IB_QPT_REG_UMR:
3197 if (wr->opcode != MLX5_IB_WR_UMR) {
3198 err = -EINVAL;
3199 mlx5_ib_warn(dev, "bad opcode\n");
3200 goto out;
3201 }
3202 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
3203 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
3204 set_reg_umr_segment(seg, wr);
3205 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3206 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3207 if (unlikely((seg == qend)))
3208 seg = mlx5_get_send_wqe(qp, 0);
3209 set_reg_mkey_segment(seg, wr);
3210 seg += sizeof(struct mlx5_mkey_seg);
3211 size += sizeof(struct mlx5_mkey_seg) / 16;
3212 if (unlikely((seg == qend)))
3213 seg = mlx5_get_send_wqe(qp, 0);
3214 break;
3215
3216 default:
3217 break;
3218 }
3219
3220 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
3221 int uninitialized_var(sz);
3222
3223 err = set_data_inl_seg(qp, wr, seg, &sz);
3224 if (unlikely(err)) {
3225 mlx5_ib_warn(dev, "\n");
3226 *bad_wr = wr;
3227 goto out;
3228 }
3229 inl = 1;
3230 size += sz;
3231 } else {
3232 dpseg = seg;
3233 for (i = 0; i < num_sge; i++) {
3234 if (unlikely(dpseg == qend)) {
3235 seg = mlx5_get_send_wqe(qp, 0);
3236 dpseg = seg;
3237 }
3238 if (likely(wr->sg_list[i].length)) {
3239 set_data_ptr_seg(dpseg, wr->sg_list + i);
3240 size += sizeof(struct mlx5_wqe_data_seg) / 16;
3241 dpseg++;
3242 }
3243 }
3244 }
3245
3246 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
3247 get_fence(fence, wr), next_fence,
3248 mlx5_ib_opcode[wr->opcode]);
3249 skip_psv:
3250 if (0)
3251 dump_wqe(qp, idx, size);
3252 }
3253
3254 out:
3255 if (likely(nreq)) {
3256 qp->sq.head += nreq;
3257
3258 /* Make sure that descriptors are written before
3259 * updating doorbell record and ringing the doorbell
3260 */
3261 wmb();
3262
3263 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
3264
3265 /* Make sure doorbell record is visible to the HCA before
3266 * we hit doorbell */
3267 wmb();
3268
3269 if (bf->need_lock)
3270 spin_lock(&bf->lock);
3271 else
3272 __acquire(&bf->lock);
3273
3274 /* TBD enable WC */
3275 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
3276 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
3277 /* wc_wmb(); */
3278 } else {
3279 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
3280 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
3281 /* Make sure doorbells don't leak out of SQ spinlock
3282 * and reach the HCA out of order.
3283 */
3284 mmiowb();
3285 }
3286 bf->offset ^= bf->buf_size;
3287 if (bf->need_lock)
3288 spin_unlock(&bf->lock);
3289 else
3290 __release(&bf->lock);
3291 }
3292
3293 spin_unlock_irqrestore(&qp->sq.lock, flags);
3294
3295 return err;
3296 }
3297
3298 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
3299 {
3300 sig->signature = calc_sig(sig, size);
3301 }
3302
3303 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
3304 struct ib_recv_wr **bad_wr)
3305 {
3306 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3307 struct mlx5_wqe_data_seg *scat;
3308 struct mlx5_rwqe_sig *sig;
3309 unsigned long flags;
3310 int err = 0;
3311 int nreq;
3312 int ind;
3313 int i;
3314
3315 spin_lock_irqsave(&qp->rq.lock, flags);
3316
3317 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3318
3319 for (nreq = 0; wr; nreq++, wr = wr->next) {
3320 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3321 err = -ENOMEM;
3322 *bad_wr = wr;
3323 goto out;
3324 }
3325
3326 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3327 err = -EINVAL;
3328 *bad_wr = wr;
3329 goto out;
3330 }
3331
3332 scat = get_recv_wqe(qp, ind);
3333 if (qp->wq_sig)
3334 scat++;
3335
3336 for (i = 0; i < wr->num_sge; i++)
3337 set_data_ptr_seg(scat + i, wr->sg_list + i);
3338
3339 if (i < qp->rq.max_gs) {
3340 scat[i].byte_count = 0;
3341 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
3342 scat[i].addr = 0;
3343 }
3344
3345 if (qp->wq_sig) {
3346 sig = (struct mlx5_rwqe_sig *)scat;
3347 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
3348 }
3349
3350 qp->rq.wrid[ind] = wr->wr_id;
3351
3352 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3353 }
3354
3355 out:
3356 if (likely(nreq)) {
3357 qp->rq.head += nreq;
3358
3359 /* Make sure that descriptors are written before
3360 * doorbell record.
3361 */
3362 wmb();
3363
3364 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3365 }
3366
3367 spin_unlock_irqrestore(&qp->rq.lock, flags);
3368
3369 return err;
3370 }
3371
3372 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
3373 {
3374 switch (mlx5_state) {
3375 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
3376 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
3377 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
3378 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
3379 case MLX5_QP_STATE_SQ_DRAINING:
3380 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
3381 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
3382 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
3383 default: return -1;
3384 }
3385 }
3386
3387 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
3388 {
3389 switch (mlx5_mig_state) {
3390 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
3391 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
3392 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3393 default: return -1;
3394 }
3395 }
3396
3397 static int to_ib_qp_access_flags(int mlx5_flags)
3398 {
3399 int ib_flags = 0;
3400
3401 if (mlx5_flags & MLX5_QP_BIT_RRE)
3402 ib_flags |= IB_ACCESS_REMOTE_READ;
3403 if (mlx5_flags & MLX5_QP_BIT_RWE)
3404 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3405 if (mlx5_flags & MLX5_QP_BIT_RAE)
3406 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3407
3408 return ib_flags;
3409 }
3410
3411 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
3412 struct mlx5_qp_path *path)
3413 {
3414 struct mlx5_core_dev *dev = ibdev->mdev;
3415
3416 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
3417 ib_ah_attr->port_num = path->port;
3418
3419 if (ib_ah_attr->port_num == 0 ||
3420 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
3421 return;
3422
3423 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
3424
3425 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
3426 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
3427 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
3428 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
3429 if (ib_ah_attr->ah_flags) {
3430 ib_ah_attr->grh.sgid_index = path->mgid_index;
3431 ib_ah_attr->grh.hop_limit = path->hop_limit;
3432 ib_ah_attr->grh.traffic_class =
3433 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
3434 ib_ah_attr->grh.flow_label =
3435 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
3436 memcpy(ib_ah_attr->grh.dgid.raw,
3437 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
3438 }
3439 }
3440
3441 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
3442 struct mlx5_ib_sq *sq,
3443 u8 *sq_state)
3444 {
3445 void *out;
3446 void *sqc;
3447 int inlen;
3448 int err;
3449
3450 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
3451 out = mlx5_vzalloc(inlen);
3452 if (!out)
3453 return -ENOMEM;
3454
3455 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
3456 if (err)
3457 goto out;
3458
3459 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
3460 *sq_state = MLX5_GET(sqc, sqc, state);
3461 sq->state = *sq_state;
3462
3463 out:
3464 kvfree(out);
3465 return err;
3466 }
3467
3468 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
3469 struct mlx5_ib_rq *rq,
3470 u8 *rq_state)
3471 {
3472 void *out;
3473 void *rqc;
3474 int inlen;
3475 int err;
3476
3477 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
3478 out = mlx5_vzalloc(inlen);
3479 if (!out)
3480 return -ENOMEM;
3481
3482 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
3483 if (err)
3484 goto out;
3485
3486 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
3487 *rq_state = MLX5_GET(rqc, rqc, state);
3488 rq->state = *rq_state;
3489
3490 out:
3491 kvfree(out);
3492 return err;
3493 }
3494
3495 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
3496 struct mlx5_ib_qp *qp, u8 *qp_state)
3497 {
3498 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
3499 [MLX5_RQC_STATE_RST] = {
3500 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3501 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3502 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
3503 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
3504 },
3505 [MLX5_RQC_STATE_RDY] = {
3506 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3507 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3508 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
3509 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
3510 },
3511 [MLX5_RQC_STATE_ERR] = {
3512 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
3513 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
3514 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
3515 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
3516 },
3517 [MLX5_RQ_STATE_NA] = {
3518 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
3519 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
3520 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
3521 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
3522 },
3523 };
3524
3525 *qp_state = sqrq_trans[rq_state][sq_state];
3526
3527 if (*qp_state == MLX5_QP_STATE_BAD) {
3528 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
3529 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
3530 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
3531 return -EINVAL;
3532 }
3533
3534 if (*qp_state == MLX5_QP_STATE)
3535 *qp_state = qp->state;
3536
3537 return 0;
3538 }
3539
3540 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
3541 struct mlx5_ib_qp *qp,
3542 u8 *raw_packet_qp_state)
3543 {
3544 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
3545 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
3546 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
3547 int err;
3548 u8 sq_state = MLX5_SQ_STATE_NA;
3549 u8 rq_state = MLX5_RQ_STATE_NA;
3550
3551 if (qp->sq.wqe_cnt) {
3552 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
3553 if (err)
3554 return err;
3555 }
3556
3557 if (qp->rq.wqe_cnt) {
3558 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
3559 if (err)
3560 return err;
3561 }
3562
3563 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
3564 raw_packet_qp_state);
3565 }
3566
3567 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
3568 struct ib_qp_attr *qp_attr)
3569 {
3570 struct mlx5_query_qp_mbox_out *outb;
3571 struct mlx5_qp_context *context;
3572 int mlx5_state;
3573 int err = 0;
3574
3575 outb = kzalloc(sizeof(*outb), GFP_KERNEL);
3576 if (!outb)
3577 return -ENOMEM;
3578
3579 context = &outb->ctx;
3580 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
3581 sizeof(*outb));
3582 if (err)
3583 goto out;
3584
3585 mlx5_state = be32_to_cpu(context->flags) >> 28;
3586
3587 qp->state = to_ib_qp_state(mlx5_state);
3588 qp_attr->path_mtu = context->mtu_msgmax >> 5;
3589 qp_attr->path_mig_state =
3590 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
3591 qp_attr->qkey = be32_to_cpu(context->qkey);
3592 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
3593 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
3594 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
3595 qp_attr->qp_access_flags =
3596 to_ib_qp_access_flags(be32_to_cpu(context->params2));
3597
3598 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3599 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
3600 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
3601 qp_attr->alt_pkey_index = context->alt_path.pkey_index & 0x7f;
3602 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
3603 }
3604
3605 qp_attr->pkey_index = context->pri_path.pkey_index & 0x7f;
3606 qp_attr->port_num = context->pri_path.port;
3607
3608 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3609 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
3610
3611 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
3612
3613 qp_attr->max_dest_rd_atomic =
3614 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
3615 qp_attr->min_rnr_timer =
3616 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
3617 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
3618 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
3619 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
3620 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
3621
3622 out:
3623 kfree(outb);
3624 return err;
3625 }
3626
3627 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
3628 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
3629 {
3630 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3631 struct mlx5_ib_qp *qp = to_mqp(ibqp);
3632 int err = 0;
3633 u8 raw_packet_qp_state;
3634
3635 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
3636 /*
3637 * Wait for any outstanding page faults, in case the user frees memory
3638 * based upon this query's result.
3639 */
3640 flush_workqueue(mlx5_ib_page_fault_wq);
3641 #endif
3642
3643 mutex_lock(&qp->mutex);
3644
3645 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
3646 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
3647 if (err)
3648 goto out;
3649 qp->state = raw_packet_qp_state;
3650 qp_attr->port_num = 1;
3651 } else {
3652 err = query_qp_attr(dev, qp, qp_attr);
3653 if (err)
3654 goto out;
3655 }
3656
3657 qp_attr->qp_state = qp->state;
3658 qp_attr->cur_qp_state = qp_attr->qp_state;
3659 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
3660 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
3661
3662 if (!ibqp->uobject) {
3663 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
3664 qp_attr->cap.max_send_sge = qp->sq.max_gs;
3665 } else {
3666 qp_attr->cap.max_send_wr = 0;
3667 qp_attr->cap.max_send_sge = 0;
3668 }
3669
3670 /* We don't support inline sends for kernel QPs (yet), and we
3671 * don't know what userspace's value should be.
3672 */
3673 qp_attr->cap.max_inline_data = 0;
3674
3675 qp_init_attr->cap = qp_attr->cap;
3676
3677 qp_init_attr->create_flags = 0;
3678 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
3679 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
3680
3681 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
3682 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
3683 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
3684 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
3685 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
3686 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
3687
3688 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
3689 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
3690
3691 out:
3692 mutex_unlock(&qp->mutex);
3693 return err;
3694 }
3695
3696 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
3697 struct ib_ucontext *context,
3698 struct ib_udata *udata)
3699 {
3700 struct mlx5_ib_dev *dev = to_mdev(ibdev);
3701 struct mlx5_ib_xrcd *xrcd;
3702 int err;
3703
3704 if (!MLX5_CAP_GEN(dev->mdev, xrc))
3705 return ERR_PTR(-ENOSYS);
3706
3707 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
3708 if (!xrcd)
3709 return ERR_PTR(-ENOMEM);
3710
3711 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
3712 if (err) {
3713 kfree(xrcd);
3714 return ERR_PTR(-ENOMEM);
3715 }
3716
3717 return &xrcd->ibxrcd;
3718 }
3719
3720 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
3721 {
3722 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
3723 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
3724 int err;
3725
3726 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
3727 if (err) {
3728 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
3729 return err;
3730 }
3731
3732 kfree(xrcd);
3733
3734 return 0;
3735 }
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