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Merge branch 'stable/for-linus-4.9' of git://git.kernel.org/pub/scm/linux/kernel...
[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mlx5 / qp.c
1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34 #include <rdma/ib_umem.h>
35 #include <rdma/ib_cache.h>
36 #include <rdma/ib_user_verbs.h>
37 #include "mlx5_ib.h"
38
39 /* not supported currently */
40 static int wq_signature;
41
42 enum {
43 MLX5_IB_ACK_REQ_FREQ = 8,
44 };
45
46 enum {
47 MLX5_IB_DEFAULT_SCHED_QUEUE = 0x83,
48 MLX5_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
49 MLX5_IB_LINK_TYPE_IB = 0,
50 MLX5_IB_LINK_TYPE_ETH = 1
51 };
52
53 enum {
54 MLX5_IB_SQ_STRIDE = 6,
55 };
56
57 static const u32 mlx5_ib_opcode[] = {
58 [IB_WR_SEND] = MLX5_OPCODE_SEND,
59 [IB_WR_LSO] = MLX5_OPCODE_LSO,
60 [IB_WR_SEND_WITH_IMM] = MLX5_OPCODE_SEND_IMM,
61 [IB_WR_RDMA_WRITE] = MLX5_OPCODE_RDMA_WRITE,
62 [IB_WR_RDMA_WRITE_WITH_IMM] = MLX5_OPCODE_RDMA_WRITE_IMM,
63 [IB_WR_RDMA_READ] = MLX5_OPCODE_RDMA_READ,
64 [IB_WR_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_CS,
65 [IB_WR_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_FA,
66 [IB_WR_SEND_WITH_INV] = MLX5_OPCODE_SEND_INVAL,
67 [IB_WR_LOCAL_INV] = MLX5_OPCODE_UMR,
68 [IB_WR_REG_MR] = MLX5_OPCODE_UMR,
69 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = MLX5_OPCODE_ATOMIC_MASKED_CS,
70 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = MLX5_OPCODE_ATOMIC_MASKED_FA,
71 [MLX5_IB_WR_UMR] = MLX5_OPCODE_UMR,
72 };
73
74 struct mlx5_wqe_eth_pad {
75 u8 rsvd0[16];
76 };
77
78 enum raw_qp_set_mask_map {
79 MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID = 1UL << 0,
80 };
81
82 struct mlx5_modify_raw_qp_param {
83 u16 operation;
84
85 u32 set_mask; /* raw_qp_set_mask_map */
86 u8 rq_q_ctr_id;
87 };
88
89 static void get_cqs(enum ib_qp_type qp_type,
90 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
91 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq);
92
93 static int is_qp0(enum ib_qp_type qp_type)
94 {
95 return qp_type == IB_QPT_SMI;
96 }
97
98 static int is_sqp(enum ib_qp_type qp_type)
99 {
100 return is_qp0(qp_type) || is_qp1(qp_type);
101 }
102
103 static void *get_wqe(struct mlx5_ib_qp *qp, int offset)
104 {
105 return mlx5_buf_offset(&qp->buf, offset);
106 }
107
108 static void *get_recv_wqe(struct mlx5_ib_qp *qp, int n)
109 {
110 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
111 }
112
113 void *mlx5_get_send_wqe(struct mlx5_ib_qp *qp, int n)
114 {
115 return get_wqe(qp, qp->sq.offset + (n << MLX5_IB_SQ_STRIDE));
116 }
117
118 /**
119 * mlx5_ib_read_user_wqe() - Copy a user-space WQE to kernel space.
120 *
121 * @qp: QP to copy from.
122 * @send: copy from the send queue when non-zero, use the receive queue
123 * otherwise.
124 * @wqe_index: index to start copying from. For send work queues, the
125 * wqe_index is in units of MLX5_SEND_WQE_BB.
126 * For receive work queue, it is the number of work queue
127 * element in the queue.
128 * @buffer: destination buffer.
129 * @length: maximum number of bytes to copy.
130 *
131 * Copies at least a single WQE, but may copy more data.
132 *
133 * Return: the number of bytes copied, or an error code.
134 */
135 int mlx5_ib_read_user_wqe(struct mlx5_ib_qp *qp, int send, int wqe_index,
136 void *buffer, u32 length,
137 struct mlx5_ib_qp_base *base)
138 {
139 struct ib_device *ibdev = qp->ibqp.device;
140 struct mlx5_ib_dev *dev = to_mdev(ibdev);
141 struct mlx5_ib_wq *wq = send ? &qp->sq : &qp->rq;
142 size_t offset;
143 size_t wq_end;
144 struct ib_umem *umem = base->ubuffer.umem;
145 u32 first_copy_length;
146 int wqe_length;
147 int ret;
148
149 if (wq->wqe_cnt == 0) {
150 mlx5_ib_dbg(dev, "mlx5_ib_read_user_wqe for a QP with wqe_cnt == 0. qp_type: 0x%x\n",
151 qp->ibqp.qp_type);
152 return -EINVAL;
153 }
154
155 offset = wq->offset + ((wqe_index % wq->wqe_cnt) << wq->wqe_shift);
156 wq_end = wq->offset + (wq->wqe_cnt << wq->wqe_shift);
157
158 if (send && length < sizeof(struct mlx5_wqe_ctrl_seg))
159 return -EINVAL;
160
161 if (offset > umem->length ||
162 (send && offset + sizeof(struct mlx5_wqe_ctrl_seg) > umem->length))
163 return -EINVAL;
164
165 first_copy_length = min_t(u32, offset + length, wq_end) - offset;
166 ret = ib_umem_copy_from(buffer, umem, offset, first_copy_length);
167 if (ret)
168 return ret;
169
170 if (send) {
171 struct mlx5_wqe_ctrl_seg *ctrl = buffer;
172 int ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
173
174 wqe_length = ds * MLX5_WQE_DS_UNITS;
175 } else {
176 wqe_length = 1 << wq->wqe_shift;
177 }
178
179 if (wqe_length <= first_copy_length)
180 return first_copy_length;
181
182 ret = ib_umem_copy_from(buffer + first_copy_length, umem, wq->offset,
183 wqe_length - first_copy_length);
184 if (ret)
185 return ret;
186
187 return wqe_length;
188 }
189
190 static void mlx5_ib_qp_event(struct mlx5_core_qp *qp, int type)
191 {
192 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
193 struct ib_event event;
194
195 if (type == MLX5_EVENT_TYPE_PATH_MIG) {
196 /* This event is only valid for trans_qps */
197 to_mibqp(qp)->port = to_mibqp(qp)->trans_qp.alt_port;
198 }
199
200 if (ibqp->event_handler) {
201 event.device = ibqp->device;
202 event.element.qp = ibqp;
203 switch (type) {
204 case MLX5_EVENT_TYPE_PATH_MIG:
205 event.event = IB_EVENT_PATH_MIG;
206 break;
207 case MLX5_EVENT_TYPE_COMM_EST:
208 event.event = IB_EVENT_COMM_EST;
209 break;
210 case MLX5_EVENT_TYPE_SQ_DRAINED:
211 event.event = IB_EVENT_SQ_DRAINED;
212 break;
213 case MLX5_EVENT_TYPE_SRQ_LAST_WQE:
214 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
215 break;
216 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
217 event.event = IB_EVENT_QP_FATAL;
218 break;
219 case MLX5_EVENT_TYPE_PATH_MIG_FAILED:
220 event.event = IB_EVENT_PATH_MIG_ERR;
221 break;
222 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
223 event.event = IB_EVENT_QP_REQ_ERR;
224 break;
225 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR:
226 event.event = IB_EVENT_QP_ACCESS_ERR;
227 break;
228 default:
229 pr_warn("mlx5_ib: Unexpected event type %d on QP %06x\n", type, qp->qpn);
230 return;
231 }
232
233 ibqp->event_handler(&event, ibqp->qp_context);
234 }
235 }
236
237 static int set_rq_size(struct mlx5_ib_dev *dev, struct ib_qp_cap *cap,
238 int has_rq, struct mlx5_ib_qp *qp, struct mlx5_ib_create_qp *ucmd)
239 {
240 int wqe_size;
241 int wq_size;
242
243 /* Sanity check RQ size before proceeding */
244 if (cap->max_recv_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz)))
245 return -EINVAL;
246
247 if (!has_rq) {
248 qp->rq.max_gs = 0;
249 qp->rq.wqe_cnt = 0;
250 qp->rq.wqe_shift = 0;
251 cap->max_recv_wr = 0;
252 cap->max_recv_sge = 0;
253 } else {
254 if (ucmd) {
255 qp->rq.wqe_cnt = ucmd->rq_wqe_count;
256 qp->rq.wqe_shift = ucmd->rq_wqe_shift;
257 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
258 qp->rq.max_post = qp->rq.wqe_cnt;
259 } else {
260 wqe_size = qp->wq_sig ? sizeof(struct mlx5_wqe_signature_seg) : 0;
261 wqe_size += cap->max_recv_sge * sizeof(struct mlx5_wqe_data_seg);
262 wqe_size = roundup_pow_of_two(wqe_size);
263 wq_size = roundup_pow_of_two(cap->max_recv_wr) * wqe_size;
264 wq_size = max_t(int, wq_size, MLX5_SEND_WQE_BB);
265 qp->rq.wqe_cnt = wq_size / wqe_size;
266 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_rq)) {
267 mlx5_ib_dbg(dev, "wqe_size %d, max %d\n",
268 wqe_size,
269 MLX5_CAP_GEN(dev->mdev,
270 max_wqe_sz_rq));
271 return -EINVAL;
272 }
273 qp->rq.wqe_shift = ilog2(wqe_size);
274 qp->rq.max_gs = (1 << qp->rq.wqe_shift) / sizeof(struct mlx5_wqe_data_seg) - qp->wq_sig;
275 qp->rq.max_post = qp->rq.wqe_cnt;
276 }
277 }
278
279 return 0;
280 }
281
282 static int sq_overhead(struct ib_qp_init_attr *attr)
283 {
284 int size = 0;
285
286 switch (attr->qp_type) {
287 case IB_QPT_XRC_INI:
288 size += sizeof(struct mlx5_wqe_xrc_seg);
289 /* fall through */
290 case IB_QPT_RC:
291 size += sizeof(struct mlx5_wqe_ctrl_seg) +
292 max(sizeof(struct mlx5_wqe_atomic_seg) +
293 sizeof(struct mlx5_wqe_raddr_seg),
294 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
295 sizeof(struct mlx5_mkey_seg));
296 break;
297
298 case IB_QPT_XRC_TGT:
299 return 0;
300
301 case IB_QPT_UC:
302 size += sizeof(struct mlx5_wqe_ctrl_seg) +
303 max(sizeof(struct mlx5_wqe_raddr_seg),
304 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
305 sizeof(struct mlx5_mkey_seg));
306 break;
307
308 case IB_QPT_UD:
309 if (attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
310 size += sizeof(struct mlx5_wqe_eth_pad) +
311 sizeof(struct mlx5_wqe_eth_seg);
312 /* fall through */
313 case IB_QPT_SMI:
314 case MLX5_IB_QPT_HW_GSI:
315 size += sizeof(struct mlx5_wqe_ctrl_seg) +
316 sizeof(struct mlx5_wqe_datagram_seg);
317 break;
318
319 case MLX5_IB_QPT_REG_UMR:
320 size += sizeof(struct mlx5_wqe_ctrl_seg) +
321 sizeof(struct mlx5_wqe_umr_ctrl_seg) +
322 sizeof(struct mlx5_mkey_seg);
323 break;
324
325 default:
326 return -EINVAL;
327 }
328
329 return size;
330 }
331
332 static int calc_send_wqe(struct ib_qp_init_attr *attr)
333 {
334 int inl_size = 0;
335 int size;
336
337 size = sq_overhead(attr);
338 if (size < 0)
339 return size;
340
341 if (attr->cap.max_inline_data) {
342 inl_size = size + sizeof(struct mlx5_wqe_inline_seg) +
343 attr->cap.max_inline_data;
344 }
345
346 size += attr->cap.max_send_sge * sizeof(struct mlx5_wqe_data_seg);
347 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN &&
348 ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB) < MLX5_SIG_WQE_SIZE)
349 return MLX5_SIG_WQE_SIZE;
350 else
351 return ALIGN(max_t(int, inl_size, size), MLX5_SEND_WQE_BB);
352 }
353
354 static int calc_sq_size(struct mlx5_ib_dev *dev, struct ib_qp_init_attr *attr,
355 struct mlx5_ib_qp *qp)
356 {
357 int wqe_size;
358 int wq_size;
359
360 if (!attr->cap.max_send_wr)
361 return 0;
362
363 wqe_size = calc_send_wqe(attr);
364 mlx5_ib_dbg(dev, "wqe_size %d\n", wqe_size);
365 if (wqe_size < 0)
366 return wqe_size;
367
368 if (wqe_size > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
369 mlx5_ib_dbg(dev, "wqe_size(%d) > max_sq_desc_sz(%d)\n",
370 wqe_size, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
371 return -EINVAL;
372 }
373
374 qp->max_inline_data = wqe_size - sq_overhead(attr) -
375 sizeof(struct mlx5_wqe_inline_seg);
376 attr->cap.max_inline_data = qp->max_inline_data;
377
378 if (attr->create_flags & IB_QP_CREATE_SIGNATURE_EN)
379 qp->signature_en = true;
380
381 wq_size = roundup_pow_of_two(attr->cap.max_send_wr * wqe_size);
382 qp->sq.wqe_cnt = wq_size / MLX5_SEND_WQE_BB;
383 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
384 mlx5_ib_dbg(dev, "wqe count(%d) exceeds limits(%d)\n",
385 qp->sq.wqe_cnt,
386 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
387 return -ENOMEM;
388 }
389 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
390 qp->sq.max_gs = attr->cap.max_send_sge;
391 qp->sq.max_post = wq_size / wqe_size;
392 attr->cap.max_send_wr = qp->sq.max_post;
393
394 return wq_size;
395 }
396
397 static int set_user_buf_size(struct mlx5_ib_dev *dev,
398 struct mlx5_ib_qp *qp,
399 struct mlx5_ib_create_qp *ucmd,
400 struct mlx5_ib_qp_base *base,
401 struct ib_qp_init_attr *attr)
402 {
403 int desc_sz = 1 << qp->sq.wqe_shift;
404
405 if (desc_sz > MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq)) {
406 mlx5_ib_warn(dev, "desc_sz %d, max_sq_desc_sz %d\n",
407 desc_sz, MLX5_CAP_GEN(dev->mdev, max_wqe_sz_sq));
408 return -EINVAL;
409 }
410
411 if (ucmd->sq_wqe_count && ((1 << ilog2(ucmd->sq_wqe_count)) != ucmd->sq_wqe_count)) {
412 mlx5_ib_warn(dev, "sq_wqe_count %d, sq_wqe_count %d\n",
413 ucmd->sq_wqe_count, ucmd->sq_wqe_count);
414 return -EINVAL;
415 }
416
417 qp->sq.wqe_cnt = ucmd->sq_wqe_count;
418
419 if (qp->sq.wqe_cnt > (1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz))) {
420 mlx5_ib_warn(dev, "wqe_cnt %d, max_wqes %d\n",
421 qp->sq.wqe_cnt,
422 1 << MLX5_CAP_GEN(dev->mdev, log_max_qp_sz));
423 return -EINVAL;
424 }
425
426 if (attr->qp_type == IB_QPT_RAW_PACKET) {
427 base->ubuffer.buf_size = qp->rq.wqe_cnt << qp->rq.wqe_shift;
428 qp->raw_packet_qp.sq.ubuffer.buf_size = qp->sq.wqe_cnt << 6;
429 } else {
430 base->ubuffer.buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
431 (qp->sq.wqe_cnt << 6);
432 }
433
434 return 0;
435 }
436
437 static int qp_has_rq(struct ib_qp_init_attr *attr)
438 {
439 if (attr->qp_type == IB_QPT_XRC_INI ||
440 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
441 attr->qp_type == MLX5_IB_QPT_REG_UMR ||
442 !attr->cap.max_recv_wr)
443 return 0;
444
445 return 1;
446 }
447
448 static int first_med_uuar(void)
449 {
450 return 1;
451 }
452
453 static int next_uuar(int n)
454 {
455 n++;
456
457 while (((n % 4) & 2))
458 n++;
459
460 return n;
461 }
462
463 static int num_med_uuar(struct mlx5_uuar_info *uuari)
464 {
465 int n;
466
467 n = uuari->num_uars * MLX5_NON_FP_BF_REGS_PER_PAGE -
468 uuari->num_low_latency_uuars - 1;
469
470 return n >= 0 ? n : 0;
471 }
472
473 static int max_uuari(struct mlx5_uuar_info *uuari)
474 {
475 return uuari->num_uars * 4;
476 }
477
478 static int first_hi_uuar(struct mlx5_uuar_info *uuari)
479 {
480 int med;
481 int i;
482 int t;
483
484 med = num_med_uuar(uuari);
485 for (t = 0, i = first_med_uuar();; i = next_uuar(i)) {
486 t++;
487 if (t == med)
488 return next_uuar(i);
489 }
490
491 return 0;
492 }
493
494 static int alloc_high_class_uuar(struct mlx5_uuar_info *uuari)
495 {
496 int i;
497
498 for (i = first_hi_uuar(uuari); i < max_uuari(uuari); i = next_uuar(i)) {
499 if (!test_bit(i, uuari->bitmap)) {
500 set_bit(i, uuari->bitmap);
501 uuari->count[i]++;
502 return i;
503 }
504 }
505
506 return -ENOMEM;
507 }
508
509 static int alloc_med_class_uuar(struct mlx5_uuar_info *uuari)
510 {
511 int minidx = first_med_uuar();
512 int i;
513
514 for (i = first_med_uuar(); i < first_hi_uuar(uuari); i = next_uuar(i)) {
515 if (uuari->count[i] < uuari->count[minidx])
516 minidx = i;
517 }
518
519 uuari->count[minidx]++;
520 return minidx;
521 }
522
523 static int alloc_uuar(struct mlx5_uuar_info *uuari,
524 enum mlx5_ib_latency_class lat)
525 {
526 int uuarn = -EINVAL;
527
528 mutex_lock(&uuari->lock);
529 switch (lat) {
530 case MLX5_IB_LATENCY_CLASS_LOW:
531 uuarn = 0;
532 uuari->count[uuarn]++;
533 break;
534
535 case MLX5_IB_LATENCY_CLASS_MEDIUM:
536 if (uuari->ver < 2)
537 uuarn = -ENOMEM;
538 else
539 uuarn = alloc_med_class_uuar(uuari);
540 break;
541
542 case MLX5_IB_LATENCY_CLASS_HIGH:
543 if (uuari->ver < 2)
544 uuarn = -ENOMEM;
545 else
546 uuarn = alloc_high_class_uuar(uuari);
547 break;
548
549 case MLX5_IB_LATENCY_CLASS_FAST_PATH:
550 uuarn = 2;
551 break;
552 }
553 mutex_unlock(&uuari->lock);
554
555 return uuarn;
556 }
557
558 static void free_med_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
559 {
560 clear_bit(uuarn, uuari->bitmap);
561 --uuari->count[uuarn];
562 }
563
564 static void free_high_class_uuar(struct mlx5_uuar_info *uuari, int uuarn)
565 {
566 clear_bit(uuarn, uuari->bitmap);
567 --uuari->count[uuarn];
568 }
569
570 static void free_uuar(struct mlx5_uuar_info *uuari, int uuarn)
571 {
572 int nuuars = uuari->num_uars * MLX5_BF_REGS_PER_PAGE;
573 int high_uuar = nuuars - uuari->num_low_latency_uuars;
574
575 mutex_lock(&uuari->lock);
576 if (uuarn == 0) {
577 --uuari->count[uuarn];
578 goto out;
579 }
580
581 if (uuarn < high_uuar) {
582 free_med_class_uuar(uuari, uuarn);
583 goto out;
584 }
585
586 free_high_class_uuar(uuari, uuarn);
587
588 out:
589 mutex_unlock(&uuari->lock);
590 }
591
592 static enum mlx5_qp_state to_mlx5_state(enum ib_qp_state state)
593 {
594 switch (state) {
595 case IB_QPS_RESET: return MLX5_QP_STATE_RST;
596 case IB_QPS_INIT: return MLX5_QP_STATE_INIT;
597 case IB_QPS_RTR: return MLX5_QP_STATE_RTR;
598 case IB_QPS_RTS: return MLX5_QP_STATE_RTS;
599 case IB_QPS_SQD: return MLX5_QP_STATE_SQD;
600 case IB_QPS_SQE: return MLX5_QP_STATE_SQER;
601 case IB_QPS_ERR: return MLX5_QP_STATE_ERR;
602 default: return -1;
603 }
604 }
605
606 static int to_mlx5_st(enum ib_qp_type type)
607 {
608 switch (type) {
609 case IB_QPT_RC: return MLX5_QP_ST_RC;
610 case IB_QPT_UC: return MLX5_QP_ST_UC;
611 case IB_QPT_UD: return MLX5_QP_ST_UD;
612 case MLX5_IB_QPT_REG_UMR: return MLX5_QP_ST_REG_UMR;
613 case IB_QPT_XRC_INI:
614 case IB_QPT_XRC_TGT: return MLX5_QP_ST_XRC;
615 case IB_QPT_SMI: return MLX5_QP_ST_QP0;
616 case MLX5_IB_QPT_HW_GSI: return MLX5_QP_ST_QP1;
617 case IB_QPT_RAW_IPV6: return MLX5_QP_ST_RAW_IPV6;
618 case IB_QPT_RAW_PACKET:
619 case IB_QPT_RAW_ETHERTYPE: return MLX5_QP_ST_RAW_ETHERTYPE;
620 case IB_QPT_MAX:
621 default: return -EINVAL;
622 }
623 }
624
625 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq,
626 struct mlx5_ib_cq *recv_cq);
627 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq,
628 struct mlx5_ib_cq *recv_cq);
629
630 static int uuarn_to_uar_index(struct mlx5_uuar_info *uuari, int uuarn)
631 {
632 return uuari->uars[uuarn / MLX5_BF_REGS_PER_PAGE].index;
633 }
634
635 static int mlx5_ib_umem_get(struct mlx5_ib_dev *dev,
636 struct ib_pd *pd,
637 unsigned long addr, size_t size,
638 struct ib_umem **umem,
639 int *npages, int *page_shift, int *ncont,
640 u32 *offset)
641 {
642 int err;
643
644 *umem = ib_umem_get(pd->uobject->context, addr, size, 0, 0);
645 if (IS_ERR(*umem)) {
646 mlx5_ib_dbg(dev, "umem_get failed\n");
647 return PTR_ERR(*umem);
648 }
649
650 mlx5_ib_cont_pages(*umem, addr, npages, page_shift, ncont, NULL);
651
652 err = mlx5_ib_get_buf_offset(addr, *page_shift, offset);
653 if (err) {
654 mlx5_ib_warn(dev, "bad offset\n");
655 goto err_umem;
656 }
657
658 mlx5_ib_dbg(dev, "addr 0x%lx, size %zu, npages %d, page_shift %d, ncont %d, offset %d\n",
659 addr, size, *npages, *page_shift, *ncont, *offset);
660
661 return 0;
662
663 err_umem:
664 ib_umem_release(*umem);
665 *umem = NULL;
666
667 return err;
668 }
669
670 static void destroy_user_rq(struct ib_pd *pd, struct mlx5_ib_rwq *rwq)
671 {
672 struct mlx5_ib_ucontext *context;
673
674 context = to_mucontext(pd->uobject->context);
675 mlx5_ib_db_unmap_user(context, &rwq->db);
676 if (rwq->umem)
677 ib_umem_release(rwq->umem);
678 }
679
680 static int create_user_rq(struct mlx5_ib_dev *dev, struct ib_pd *pd,
681 struct mlx5_ib_rwq *rwq,
682 struct mlx5_ib_create_wq *ucmd)
683 {
684 struct mlx5_ib_ucontext *context;
685 int page_shift = 0;
686 int npages;
687 u32 offset = 0;
688 int ncont = 0;
689 int err;
690
691 if (!ucmd->buf_addr)
692 return -EINVAL;
693
694 context = to_mucontext(pd->uobject->context);
695 rwq->umem = ib_umem_get(pd->uobject->context, ucmd->buf_addr,
696 rwq->buf_size, 0, 0);
697 if (IS_ERR(rwq->umem)) {
698 mlx5_ib_dbg(dev, "umem_get failed\n");
699 err = PTR_ERR(rwq->umem);
700 return err;
701 }
702
703 mlx5_ib_cont_pages(rwq->umem, ucmd->buf_addr, &npages, &page_shift,
704 &ncont, NULL);
705 err = mlx5_ib_get_buf_offset(ucmd->buf_addr, page_shift,
706 &rwq->rq_page_offset);
707 if (err) {
708 mlx5_ib_warn(dev, "bad offset\n");
709 goto err_umem;
710 }
711
712 rwq->rq_num_pas = ncont;
713 rwq->page_shift = page_shift;
714 rwq->log_page_size = page_shift - MLX5_ADAPTER_PAGE_SHIFT;
715 rwq->wq_sig = !!(ucmd->flags & MLX5_WQ_FLAG_SIGNATURE);
716
717 mlx5_ib_dbg(dev, "addr 0x%llx, size %zd, npages %d, page_shift %d, ncont %d, offset %d\n",
718 (unsigned long long)ucmd->buf_addr, rwq->buf_size,
719 npages, page_shift, ncont, offset);
720
721 err = mlx5_ib_db_map_user(context, ucmd->db_addr, &rwq->db);
722 if (err) {
723 mlx5_ib_dbg(dev, "map failed\n");
724 goto err_umem;
725 }
726
727 rwq->create_type = MLX5_WQ_USER;
728 return 0;
729
730 err_umem:
731 ib_umem_release(rwq->umem);
732 return err;
733 }
734
735 static int create_user_qp(struct mlx5_ib_dev *dev, struct ib_pd *pd,
736 struct mlx5_ib_qp *qp, struct ib_udata *udata,
737 struct ib_qp_init_attr *attr,
738 u32 **in,
739 struct mlx5_ib_create_qp_resp *resp, int *inlen,
740 struct mlx5_ib_qp_base *base)
741 {
742 struct mlx5_ib_ucontext *context;
743 struct mlx5_ib_create_qp ucmd;
744 struct mlx5_ib_ubuffer *ubuffer = &base->ubuffer;
745 int page_shift = 0;
746 int uar_index;
747 int npages;
748 u32 offset = 0;
749 int uuarn;
750 int ncont = 0;
751 __be64 *pas;
752 void *qpc;
753 int err;
754
755 err = ib_copy_from_udata(&ucmd, udata, sizeof(ucmd));
756 if (err) {
757 mlx5_ib_dbg(dev, "copy failed\n");
758 return err;
759 }
760
761 context = to_mucontext(pd->uobject->context);
762 /*
763 * TBD: should come from the verbs when we have the API
764 */
765 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
766 /* In CROSS_CHANNEL CQ and QP must use the same UAR */
767 uuarn = MLX5_CROSS_CHANNEL_UUAR;
768 else {
769 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_HIGH);
770 if (uuarn < 0) {
771 mlx5_ib_dbg(dev, "failed to allocate low latency UUAR\n");
772 mlx5_ib_dbg(dev, "reverting to medium latency\n");
773 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_MEDIUM);
774 if (uuarn < 0) {
775 mlx5_ib_dbg(dev, "failed to allocate medium latency UUAR\n");
776 mlx5_ib_dbg(dev, "reverting to high latency\n");
777 uuarn = alloc_uuar(&context->uuari, MLX5_IB_LATENCY_CLASS_LOW);
778 if (uuarn < 0) {
779 mlx5_ib_warn(dev, "uuar allocation failed\n");
780 return uuarn;
781 }
782 }
783 }
784 }
785
786 uar_index = uuarn_to_uar_index(&context->uuari, uuarn);
787 mlx5_ib_dbg(dev, "uuarn 0x%x, uar_index 0x%x\n", uuarn, uar_index);
788
789 qp->rq.offset = 0;
790 qp->sq.wqe_shift = ilog2(MLX5_SEND_WQE_BB);
791 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
792
793 err = set_user_buf_size(dev, qp, &ucmd, base, attr);
794 if (err)
795 goto err_uuar;
796
797 if (ucmd.buf_addr && ubuffer->buf_size) {
798 ubuffer->buf_addr = ucmd.buf_addr;
799 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr,
800 ubuffer->buf_size,
801 &ubuffer->umem, &npages, &page_shift,
802 &ncont, &offset);
803 if (err)
804 goto err_uuar;
805 } else {
806 ubuffer->umem = NULL;
807 }
808
809 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
810 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * ncont;
811 *in = mlx5_vzalloc(*inlen);
812 if (!*in) {
813 err = -ENOMEM;
814 goto err_umem;
815 }
816
817 pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas);
818 if (ubuffer->umem)
819 mlx5_ib_populate_pas(dev, ubuffer->umem, page_shift, pas, 0);
820
821 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
822
823 MLX5_SET(qpc, qpc, log_page_size, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
824 MLX5_SET(qpc, qpc, page_offset, offset);
825
826 MLX5_SET(qpc, qpc, uar_page, uar_index);
827 resp->uuar_index = uuarn;
828 qp->uuarn = uuarn;
829
830 err = mlx5_ib_db_map_user(context, ucmd.db_addr, &qp->db);
831 if (err) {
832 mlx5_ib_dbg(dev, "map failed\n");
833 goto err_free;
834 }
835
836 err = ib_copy_to_udata(udata, resp, sizeof(*resp));
837 if (err) {
838 mlx5_ib_dbg(dev, "copy failed\n");
839 goto err_unmap;
840 }
841 qp->create_type = MLX5_QP_USER;
842
843 return 0;
844
845 err_unmap:
846 mlx5_ib_db_unmap_user(context, &qp->db);
847
848 err_free:
849 kvfree(*in);
850
851 err_umem:
852 if (ubuffer->umem)
853 ib_umem_release(ubuffer->umem);
854
855 err_uuar:
856 free_uuar(&context->uuari, uuarn);
857 return err;
858 }
859
860 static void destroy_qp_user(struct ib_pd *pd, struct mlx5_ib_qp *qp,
861 struct mlx5_ib_qp_base *base)
862 {
863 struct mlx5_ib_ucontext *context;
864
865 context = to_mucontext(pd->uobject->context);
866 mlx5_ib_db_unmap_user(context, &qp->db);
867 if (base->ubuffer.umem)
868 ib_umem_release(base->ubuffer.umem);
869 free_uuar(&context->uuari, qp->uuarn);
870 }
871
872 static int create_kernel_qp(struct mlx5_ib_dev *dev,
873 struct ib_qp_init_attr *init_attr,
874 struct mlx5_ib_qp *qp,
875 u32 **in, int *inlen,
876 struct mlx5_ib_qp_base *base)
877 {
878 enum mlx5_ib_latency_class lc = MLX5_IB_LATENCY_CLASS_LOW;
879 struct mlx5_uuar_info *uuari;
880 int uar_index;
881 void *qpc;
882 int uuarn;
883 int err;
884
885 uuari = &dev->mdev->priv.uuari;
886 if (init_attr->create_flags & ~(IB_QP_CREATE_SIGNATURE_EN |
887 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK |
888 IB_QP_CREATE_IPOIB_UD_LSO |
889 mlx5_ib_create_qp_sqpn_qp1()))
890 return -EINVAL;
891
892 if (init_attr->qp_type == MLX5_IB_QPT_REG_UMR)
893 lc = MLX5_IB_LATENCY_CLASS_FAST_PATH;
894
895 uuarn = alloc_uuar(uuari, lc);
896 if (uuarn < 0) {
897 mlx5_ib_dbg(dev, "\n");
898 return -ENOMEM;
899 }
900
901 qp->bf = &uuari->bfs[uuarn];
902 uar_index = qp->bf->uar->index;
903
904 err = calc_sq_size(dev, init_attr, qp);
905 if (err < 0) {
906 mlx5_ib_dbg(dev, "err %d\n", err);
907 goto err_uuar;
908 }
909
910 qp->rq.offset = 0;
911 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
912 base->ubuffer.buf_size = err + (qp->rq.wqe_cnt << qp->rq.wqe_shift);
913
914 err = mlx5_buf_alloc(dev->mdev, base->ubuffer.buf_size, &qp->buf);
915 if (err) {
916 mlx5_ib_dbg(dev, "err %d\n", err);
917 goto err_uuar;
918 }
919
920 qp->sq.qend = mlx5_get_send_wqe(qp, qp->sq.wqe_cnt);
921 *inlen = MLX5_ST_SZ_BYTES(create_qp_in) +
922 MLX5_FLD_SZ_BYTES(create_qp_in, pas[0]) * qp->buf.npages;
923 *in = mlx5_vzalloc(*inlen);
924 if (!*in) {
925 err = -ENOMEM;
926 goto err_buf;
927 }
928
929 qpc = MLX5_ADDR_OF(create_qp_in, *in, qpc);
930 MLX5_SET(qpc, qpc, uar_page, uar_index);
931 MLX5_SET(qpc, qpc, log_page_size, qp->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT);
932
933 /* Set "fast registration enabled" for all kernel QPs */
934 MLX5_SET(qpc, qpc, fre, 1);
935 MLX5_SET(qpc, qpc, rlky, 1);
936
937 if (init_attr->create_flags & mlx5_ib_create_qp_sqpn_qp1()) {
938 MLX5_SET(qpc, qpc, deth_sqpn, 1);
939 qp->flags |= MLX5_IB_QP_SQPN_QP1;
940 }
941
942 mlx5_fill_page_array(&qp->buf,
943 (__be64 *)MLX5_ADDR_OF(create_qp_in, *in, pas));
944
945 err = mlx5_db_alloc(dev->mdev, &qp->db);
946 if (err) {
947 mlx5_ib_dbg(dev, "err %d\n", err);
948 goto err_free;
949 }
950
951 qp->sq.wrid = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wrid), GFP_KERNEL);
952 qp->sq.wr_data = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wr_data), GFP_KERNEL);
953 qp->rq.wrid = kmalloc(qp->rq.wqe_cnt * sizeof(*qp->rq.wrid), GFP_KERNEL);
954 qp->sq.w_list = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.w_list), GFP_KERNEL);
955 qp->sq.wqe_head = kmalloc(qp->sq.wqe_cnt * sizeof(*qp->sq.wqe_head), GFP_KERNEL);
956
957 if (!qp->sq.wrid || !qp->sq.wr_data || !qp->rq.wrid ||
958 !qp->sq.w_list || !qp->sq.wqe_head) {
959 err = -ENOMEM;
960 goto err_wrid;
961 }
962 qp->create_type = MLX5_QP_KERNEL;
963
964 return 0;
965
966 err_wrid:
967 mlx5_db_free(dev->mdev, &qp->db);
968 kfree(qp->sq.wqe_head);
969 kfree(qp->sq.w_list);
970 kfree(qp->sq.wrid);
971 kfree(qp->sq.wr_data);
972 kfree(qp->rq.wrid);
973
974 err_free:
975 kvfree(*in);
976
977 err_buf:
978 mlx5_buf_free(dev->mdev, &qp->buf);
979
980 err_uuar:
981 free_uuar(&dev->mdev->priv.uuari, uuarn);
982 return err;
983 }
984
985 static void destroy_qp_kernel(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
986 {
987 mlx5_db_free(dev->mdev, &qp->db);
988 kfree(qp->sq.wqe_head);
989 kfree(qp->sq.w_list);
990 kfree(qp->sq.wrid);
991 kfree(qp->sq.wr_data);
992 kfree(qp->rq.wrid);
993 mlx5_buf_free(dev->mdev, &qp->buf);
994 free_uuar(&dev->mdev->priv.uuari, qp->bf->uuarn);
995 }
996
997 static u32 get_rx_type(struct mlx5_ib_qp *qp, struct ib_qp_init_attr *attr)
998 {
999 if (attr->srq || (attr->qp_type == IB_QPT_XRC_TGT) ||
1000 (attr->qp_type == IB_QPT_XRC_INI))
1001 return MLX5_SRQ_RQ;
1002 else if (!qp->has_rq)
1003 return MLX5_ZERO_LEN_RQ;
1004 else
1005 return MLX5_NON_ZERO_RQ;
1006 }
1007
1008 static int is_connected(enum ib_qp_type qp_type)
1009 {
1010 if (qp_type == IB_QPT_RC || qp_type == IB_QPT_UC)
1011 return 1;
1012
1013 return 0;
1014 }
1015
1016 static int create_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1017 struct mlx5_ib_sq *sq, u32 tdn)
1018 {
1019 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
1020 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
1021
1022 MLX5_SET(tisc, tisc, transport_domain, tdn);
1023 return mlx5_core_create_tis(dev->mdev, in, sizeof(in), &sq->tisn);
1024 }
1025
1026 static void destroy_raw_packet_qp_tis(struct mlx5_ib_dev *dev,
1027 struct mlx5_ib_sq *sq)
1028 {
1029 mlx5_core_destroy_tis(dev->mdev, sq->tisn);
1030 }
1031
1032 static int create_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1033 struct mlx5_ib_sq *sq, void *qpin,
1034 struct ib_pd *pd)
1035 {
1036 struct mlx5_ib_ubuffer *ubuffer = &sq->ubuffer;
1037 __be64 *pas;
1038 void *in;
1039 void *sqc;
1040 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1041 void *wq;
1042 int inlen;
1043 int err;
1044 int page_shift = 0;
1045 int npages;
1046 int ncont = 0;
1047 u32 offset = 0;
1048
1049 err = mlx5_ib_umem_get(dev, pd, ubuffer->buf_addr, ubuffer->buf_size,
1050 &sq->ubuffer.umem, &npages, &page_shift,
1051 &ncont, &offset);
1052 if (err)
1053 return err;
1054
1055 inlen = MLX5_ST_SZ_BYTES(create_sq_in) + sizeof(u64) * ncont;
1056 in = mlx5_vzalloc(inlen);
1057 if (!in) {
1058 err = -ENOMEM;
1059 goto err_umem;
1060 }
1061
1062 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1063 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1064 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1065 MLX5_SET(sqc, sqc, user_index, MLX5_GET(qpc, qpc, user_index));
1066 MLX5_SET(sqc, sqc, cqn, MLX5_GET(qpc, qpc, cqn_snd));
1067 MLX5_SET(sqc, sqc, tis_lst_sz, 1);
1068 MLX5_SET(sqc, sqc, tis_num_0, sq->tisn);
1069
1070 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1071 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1072 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1073 MLX5_SET(wq, wq, uar_page, MLX5_GET(qpc, qpc, uar_page));
1074 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1075 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1076 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_sq_size));
1077 MLX5_SET(wq, wq, log_wq_pg_sz, page_shift - MLX5_ADAPTER_PAGE_SHIFT);
1078 MLX5_SET(wq, wq, page_offset, offset);
1079
1080 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1081 mlx5_ib_populate_pas(dev, sq->ubuffer.umem, page_shift, pas, 0);
1082
1083 err = mlx5_core_create_sq_tracked(dev->mdev, in, inlen, &sq->base.mqp);
1084
1085 kvfree(in);
1086
1087 if (err)
1088 goto err_umem;
1089
1090 return 0;
1091
1092 err_umem:
1093 ib_umem_release(sq->ubuffer.umem);
1094 sq->ubuffer.umem = NULL;
1095
1096 return err;
1097 }
1098
1099 static void destroy_raw_packet_qp_sq(struct mlx5_ib_dev *dev,
1100 struct mlx5_ib_sq *sq)
1101 {
1102 mlx5_core_destroy_sq_tracked(dev->mdev, &sq->base.mqp);
1103 ib_umem_release(sq->ubuffer.umem);
1104 }
1105
1106 static int get_rq_pas_size(void *qpc)
1107 {
1108 u32 log_page_size = MLX5_GET(qpc, qpc, log_page_size) + 12;
1109 u32 log_rq_stride = MLX5_GET(qpc, qpc, log_rq_stride);
1110 u32 log_rq_size = MLX5_GET(qpc, qpc, log_rq_size);
1111 u32 page_offset = MLX5_GET(qpc, qpc, page_offset);
1112 u32 po_quanta = 1 << (log_page_size - 6);
1113 u32 rq_sz = 1 << (log_rq_size + 4 + log_rq_stride);
1114 u32 page_size = 1 << log_page_size;
1115 u32 rq_sz_po = rq_sz + (page_offset * po_quanta);
1116 u32 rq_num_pas = (rq_sz_po + page_size - 1) / page_size;
1117
1118 return rq_num_pas * sizeof(u64);
1119 }
1120
1121 static int create_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1122 struct mlx5_ib_rq *rq, void *qpin)
1123 {
1124 struct mlx5_ib_qp *mqp = rq->base.container_mibqp;
1125 __be64 *pas;
1126 __be64 *qp_pas;
1127 void *in;
1128 void *rqc;
1129 void *wq;
1130 void *qpc = MLX5_ADDR_OF(create_qp_in, qpin, qpc);
1131 int inlen;
1132 int err;
1133 u32 rq_pas_size = get_rq_pas_size(qpc);
1134
1135 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + rq_pas_size;
1136 in = mlx5_vzalloc(inlen);
1137 if (!in)
1138 return -ENOMEM;
1139
1140 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
1141 MLX5_SET(rqc, rqc, vsd, 1);
1142 MLX5_SET(rqc, rqc, mem_rq_type, MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
1143 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
1144 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
1145 MLX5_SET(rqc, rqc, user_index, MLX5_GET(qpc, qpc, user_index));
1146 MLX5_SET(rqc, rqc, cqn, MLX5_GET(qpc, qpc, cqn_rcv));
1147
1148 if (mqp->flags & MLX5_IB_QP_CAP_SCATTER_FCS)
1149 MLX5_SET(rqc, rqc, scatter_fcs, 1);
1150
1151 wq = MLX5_ADDR_OF(rqc, rqc, wq);
1152 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1153 MLX5_SET(wq, wq, end_padding_mode,
1154 MLX5_GET(qpc, qpc, end_padding_mode));
1155 MLX5_SET(wq, wq, page_offset, MLX5_GET(qpc, qpc, page_offset));
1156 MLX5_SET(wq, wq, pd, MLX5_GET(qpc, qpc, pd));
1157 MLX5_SET64(wq, wq, dbr_addr, MLX5_GET64(qpc, qpc, dbr_addr));
1158 MLX5_SET(wq, wq, log_wq_stride, MLX5_GET(qpc, qpc, log_rq_stride) + 4);
1159 MLX5_SET(wq, wq, log_wq_pg_sz, MLX5_GET(qpc, qpc, log_page_size));
1160 MLX5_SET(wq, wq, log_wq_sz, MLX5_GET(qpc, qpc, log_rq_size));
1161
1162 pas = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
1163 qp_pas = (__be64 *)MLX5_ADDR_OF(create_qp_in, qpin, pas);
1164 memcpy(pas, qp_pas, rq_pas_size);
1165
1166 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rq->base.mqp);
1167
1168 kvfree(in);
1169
1170 return err;
1171 }
1172
1173 static void destroy_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
1174 struct mlx5_ib_rq *rq)
1175 {
1176 mlx5_core_destroy_rq_tracked(dev->mdev, &rq->base.mqp);
1177 }
1178
1179 static int create_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1180 struct mlx5_ib_rq *rq, u32 tdn)
1181 {
1182 u32 *in;
1183 void *tirc;
1184 int inlen;
1185 int err;
1186
1187 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1188 in = mlx5_vzalloc(inlen);
1189 if (!in)
1190 return -ENOMEM;
1191
1192 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1193 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_DIRECT);
1194 MLX5_SET(tirc, tirc, inline_rqn, rq->base.mqp.qpn);
1195 MLX5_SET(tirc, tirc, transport_domain, tdn);
1196
1197 err = mlx5_core_create_tir(dev->mdev, in, inlen, &rq->tirn);
1198
1199 kvfree(in);
1200
1201 return err;
1202 }
1203
1204 static void destroy_raw_packet_qp_tir(struct mlx5_ib_dev *dev,
1205 struct mlx5_ib_rq *rq)
1206 {
1207 mlx5_core_destroy_tir(dev->mdev, rq->tirn);
1208 }
1209
1210 static int create_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1211 u32 *in,
1212 struct ib_pd *pd)
1213 {
1214 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1215 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1216 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1217 struct ib_uobject *uobj = pd->uobject;
1218 struct ib_ucontext *ucontext = uobj->context;
1219 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1220 int err;
1221 u32 tdn = mucontext->tdn;
1222
1223 if (qp->sq.wqe_cnt) {
1224 err = create_raw_packet_qp_tis(dev, sq, tdn);
1225 if (err)
1226 return err;
1227
1228 err = create_raw_packet_qp_sq(dev, sq, in, pd);
1229 if (err)
1230 goto err_destroy_tis;
1231
1232 sq->base.container_mibqp = qp;
1233 }
1234
1235 if (qp->rq.wqe_cnt) {
1236 rq->base.container_mibqp = qp;
1237
1238 err = create_raw_packet_qp_rq(dev, rq, in);
1239 if (err)
1240 goto err_destroy_sq;
1241
1242
1243 err = create_raw_packet_qp_tir(dev, rq, tdn);
1244 if (err)
1245 goto err_destroy_rq;
1246 }
1247
1248 qp->trans_qp.base.mqp.qpn = qp->sq.wqe_cnt ? sq->base.mqp.qpn :
1249 rq->base.mqp.qpn;
1250
1251 return 0;
1252
1253 err_destroy_rq:
1254 destroy_raw_packet_qp_rq(dev, rq);
1255 err_destroy_sq:
1256 if (!qp->sq.wqe_cnt)
1257 return err;
1258 destroy_raw_packet_qp_sq(dev, sq);
1259 err_destroy_tis:
1260 destroy_raw_packet_qp_tis(dev, sq);
1261
1262 return err;
1263 }
1264
1265 static void destroy_raw_packet_qp(struct mlx5_ib_dev *dev,
1266 struct mlx5_ib_qp *qp)
1267 {
1268 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
1269 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1270 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1271
1272 if (qp->rq.wqe_cnt) {
1273 destroy_raw_packet_qp_tir(dev, rq);
1274 destroy_raw_packet_qp_rq(dev, rq);
1275 }
1276
1277 if (qp->sq.wqe_cnt) {
1278 destroy_raw_packet_qp_sq(dev, sq);
1279 destroy_raw_packet_qp_tis(dev, sq);
1280 }
1281 }
1282
1283 static void raw_packet_qp_copy_info(struct mlx5_ib_qp *qp,
1284 struct mlx5_ib_raw_packet_qp *raw_packet_qp)
1285 {
1286 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
1287 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
1288
1289 sq->sq = &qp->sq;
1290 rq->rq = &qp->rq;
1291 sq->doorbell = &qp->db;
1292 rq->doorbell = &qp->db;
1293 }
1294
1295 static void destroy_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1296 {
1297 mlx5_core_destroy_tir(dev->mdev, qp->rss_qp.tirn);
1298 }
1299
1300 static int create_rss_raw_qp_tir(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1301 struct ib_pd *pd,
1302 struct ib_qp_init_attr *init_attr,
1303 struct ib_udata *udata)
1304 {
1305 struct ib_uobject *uobj = pd->uobject;
1306 struct ib_ucontext *ucontext = uobj->context;
1307 struct mlx5_ib_ucontext *mucontext = to_mucontext(ucontext);
1308 struct mlx5_ib_create_qp_resp resp = {};
1309 int inlen;
1310 int err;
1311 u32 *in;
1312 void *tirc;
1313 void *hfso;
1314 u32 selected_fields = 0;
1315 size_t min_resp_len;
1316 u32 tdn = mucontext->tdn;
1317 struct mlx5_ib_create_qp_rss ucmd = {};
1318 size_t required_cmd_sz;
1319
1320 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1321 return -EOPNOTSUPP;
1322
1323 if (init_attr->create_flags || init_attr->send_cq)
1324 return -EINVAL;
1325
1326 min_resp_len = offsetof(typeof(resp), uuar_index) + sizeof(resp.uuar_index);
1327 if (udata->outlen < min_resp_len)
1328 return -EINVAL;
1329
1330 required_cmd_sz = offsetof(typeof(ucmd), reserved1) + sizeof(ucmd.reserved1);
1331 if (udata->inlen < required_cmd_sz) {
1332 mlx5_ib_dbg(dev, "invalid inlen\n");
1333 return -EINVAL;
1334 }
1335
1336 if (udata->inlen > sizeof(ucmd) &&
1337 !ib_is_udata_cleared(udata, sizeof(ucmd),
1338 udata->inlen - sizeof(ucmd))) {
1339 mlx5_ib_dbg(dev, "inlen is not supported\n");
1340 return -EOPNOTSUPP;
1341 }
1342
1343 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
1344 mlx5_ib_dbg(dev, "copy failed\n");
1345 return -EFAULT;
1346 }
1347
1348 if (ucmd.comp_mask) {
1349 mlx5_ib_dbg(dev, "invalid comp mask\n");
1350 return -EOPNOTSUPP;
1351 }
1352
1353 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)) || ucmd.reserved1) {
1354 mlx5_ib_dbg(dev, "invalid reserved\n");
1355 return -EOPNOTSUPP;
1356 }
1357
1358 err = ib_copy_to_udata(udata, &resp, min_resp_len);
1359 if (err) {
1360 mlx5_ib_dbg(dev, "copy failed\n");
1361 return -EINVAL;
1362 }
1363
1364 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
1365 in = mlx5_vzalloc(inlen);
1366 if (!in)
1367 return -ENOMEM;
1368
1369 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
1370 MLX5_SET(tirc, tirc, disp_type,
1371 MLX5_TIRC_DISP_TYPE_INDIRECT);
1372 MLX5_SET(tirc, tirc, indirect_table,
1373 init_attr->rwq_ind_tbl->ind_tbl_num);
1374 MLX5_SET(tirc, tirc, transport_domain, tdn);
1375
1376 hfso = MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
1377 switch (ucmd.rx_hash_function) {
1378 case MLX5_RX_HASH_FUNC_TOEPLITZ:
1379 {
1380 void *rss_key = MLX5_ADDR_OF(tirc, tirc, rx_hash_toeplitz_key);
1381 size_t len = MLX5_FLD_SZ_BYTES(tirc, rx_hash_toeplitz_key);
1382
1383 if (len != ucmd.rx_key_len) {
1384 err = -EINVAL;
1385 goto err;
1386 }
1387
1388 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_TOEPLITZ);
1389 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
1390 memcpy(rss_key, ucmd.rx_hash_key, len);
1391 break;
1392 }
1393 default:
1394 err = -EOPNOTSUPP;
1395 goto err;
1396 }
1397
1398 if (!ucmd.rx_hash_fields_mask) {
1399 /* special case when this TIR serves as steering entry without hashing */
1400 if (!init_attr->rwq_ind_tbl->log_ind_tbl_size)
1401 goto create_tir;
1402 err = -EINVAL;
1403 goto err;
1404 }
1405
1406 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1407 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4)) &&
1408 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1409 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))) {
1410 err = -EINVAL;
1411 goto err;
1412 }
1413
1414 /* If none of IPV4 & IPV6 SRC/DST was set - this bit field is ignored */
1415 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1416 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4))
1417 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1418 MLX5_L3_PROT_TYPE_IPV4);
1419 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6) ||
1420 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1421 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
1422 MLX5_L3_PROT_TYPE_IPV6);
1423
1424 if (((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1425 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP)) &&
1426 ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1427 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))) {
1428 err = -EINVAL;
1429 goto err;
1430 }
1431
1432 /* If none of TCP & UDP SRC/DST was set - this bit field is ignored */
1433 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1434 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP))
1435 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1436 MLX5_L4_PROT_TYPE_TCP);
1437 else if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP) ||
1438 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1439 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
1440 MLX5_L4_PROT_TYPE_UDP);
1441
1442 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV4) ||
1443 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_IPV6))
1444 selected_fields |= MLX5_HASH_FIELD_SEL_SRC_IP;
1445
1446 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV4) ||
1447 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_IPV6))
1448 selected_fields |= MLX5_HASH_FIELD_SEL_DST_IP;
1449
1450 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_TCP) ||
1451 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_SRC_PORT_UDP))
1452 selected_fields |= MLX5_HASH_FIELD_SEL_L4_SPORT;
1453
1454 if ((ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_TCP) ||
1455 (ucmd.rx_hash_fields_mask & MLX5_RX_HASH_DST_PORT_UDP))
1456 selected_fields |= MLX5_HASH_FIELD_SEL_L4_DPORT;
1457
1458 MLX5_SET(rx_hash_field_select, hfso, selected_fields, selected_fields);
1459
1460 create_tir:
1461 err = mlx5_core_create_tir(dev->mdev, in, inlen, &qp->rss_qp.tirn);
1462
1463 if (err)
1464 goto err;
1465
1466 kvfree(in);
1467 /* qpn is reserved for that QP */
1468 qp->trans_qp.base.mqp.qpn = 0;
1469 qp->flags |= MLX5_IB_QP_RSS;
1470 return 0;
1471
1472 err:
1473 kvfree(in);
1474 return err;
1475 }
1476
1477 static int create_qp_common(struct mlx5_ib_dev *dev, struct ib_pd *pd,
1478 struct ib_qp_init_attr *init_attr,
1479 struct ib_udata *udata, struct mlx5_ib_qp *qp)
1480 {
1481 struct mlx5_ib_resources *devr = &dev->devr;
1482 int inlen = MLX5_ST_SZ_BYTES(create_qp_in);
1483 struct mlx5_core_dev *mdev = dev->mdev;
1484 struct mlx5_ib_create_qp_resp resp;
1485 struct mlx5_ib_cq *send_cq;
1486 struct mlx5_ib_cq *recv_cq;
1487 unsigned long flags;
1488 u32 uidx = MLX5_IB_DEFAULT_UIDX;
1489 struct mlx5_ib_create_qp ucmd;
1490 struct mlx5_ib_qp_base *base;
1491 void *qpc;
1492 u32 *in;
1493 int err;
1494
1495 base = init_attr->qp_type == IB_QPT_RAW_PACKET ?
1496 &qp->raw_packet_qp.rq.base :
1497 &qp->trans_qp.base;
1498
1499 if (init_attr->qp_type != IB_QPT_RAW_PACKET)
1500 mlx5_ib_odp_create_qp(qp);
1501
1502 mutex_init(&qp->mutex);
1503 spin_lock_init(&qp->sq.lock);
1504 spin_lock_init(&qp->rq.lock);
1505
1506 if (init_attr->rwq_ind_tbl) {
1507 if (!udata)
1508 return -ENOSYS;
1509
1510 err = create_rss_raw_qp_tir(dev, qp, pd, init_attr, udata);
1511 return err;
1512 }
1513
1514 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
1515 if (!MLX5_CAP_GEN(mdev, block_lb_mc)) {
1516 mlx5_ib_dbg(dev, "block multicast loopback isn't supported\n");
1517 return -EINVAL;
1518 } else {
1519 qp->flags |= MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1520 }
1521 }
1522
1523 if (init_attr->create_flags &
1524 (IB_QP_CREATE_CROSS_CHANNEL |
1525 IB_QP_CREATE_MANAGED_SEND |
1526 IB_QP_CREATE_MANAGED_RECV)) {
1527 if (!MLX5_CAP_GEN(mdev, cd)) {
1528 mlx5_ib_dbg(dev, "cross-channel isn't supported\n");
1529 return -EINVAL;
1530 }
1531 if (init_attr->create_flags & IB_QP_CREATE_CROSS_CHANNEL)
1532 qp->flags |= MLX5_IB_QP_CROSS_CHANNEL;
1533 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_SEND)
1534 qp->flags |= MLX5_IB_QP_MANAGED_SEND;
1535 if (init_attr->create_flags & IB_QP_CREATE_MANAGED_RECV)
1536 qp->flags |= MLX5_IB_QP_MANAGED_RECV;
1537 }
1538
1539 if (init_attr->qp_type == IB_QPT_UD &&
1540 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO))
1541 if (!MLX5_CAP_GEN(mdev, ipoib_basic_offloads)) {
1542 mlx5_ib_dbg(dev, "ipoib UD lso qp isn't supported\n");
1543 return -EOPNOTSUPP;
1544 }
1545
1546 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
1547 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
1548 mlx5_ib_dbg(dev, "Scatter FCS is supported only for Raw Packet QPs");
1549 return -EOPNOTSUPP;
1550 }
1551 if (!MLX5_CAP_GEN(dev->mdev, eth_net_offloads) ||
1552 !MLX5_CAP_ETH(dev->mdev, scatter_fcs)) {
1553 mlx5_ib_dbg(dev, "Scatter FCS isn't supported\n");
1554 return -EOPNOTSUPP;
1555 }
1556 qp->flags |= MLX5_IB_QP_CAP_SCATTER_FCS;
1557 }
1558
1559 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
1560 qp->sq_signal_bits = MLX5_WQE_CTRL_CQ_UPDATE;
1561
1562 if (pd && pd->uobject) {
1563 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
1564 mlx5_ib_dbg(dev, "copy failed\n");
1565 return -EFAULT;
1566 }
1567
1568 err = get_qp_user_index(to_mucontext(pd->uobject->context),
1569 &ucmd, udata->inlen, &uidx);
1570 if (err)
1571 return err;
1572
1573 qp->wq_sig = !!(ucmd.flags & MLX5_QP_FLAG_SIGNATURE);
1574 qp->scat_cqe = !!(ucmd.flags & MLX5_QP_FLAG_SCATTER_CQE);
1575 } else {
1576 qp->wq_sig = !!wq_signature;
1577 }
1578
1579 qp->has_rq = qp_has_rq(init_attr);
1580 err = set_rq_size(dev, &init_attr->cap, qp->has_rq,
1581 qp, (pd && pd->uobject) ? &ucmd : NULL);
1582 if (err) {
1583 mlx5_ib_dbg(dev, "err %d\n", err);
1584 return err;
1585 }
1586
1587 if (pd) {
1588 if (pd->uobject) {
1589 __u32 max_wqes =
1590 1 << MLX5_CAP_GEN(mdev, log_max_qp_sz);
1591 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d)\n", ucmd.sq_wqe_count);
1592 if (ucmd.rq_wqe_shift != qp->rq.wqe_shift ||
1593 ucmd.rq_wqe_count != qp->rq.wqe_cnt) {
1594 mlx5_ib_dbg(dev, "invalid rq params\n");
1595 return -EINVAL;
1596 }
1597 if (ucmd.sq_wqe_count > max_wqes) {
1598 mlx5_ib_dbg(dev, "requested sq_wqe_count (%d) > max allowed (%d)\n",
1599 ucmd.sq_wqe_count, max_wqes);
1600 return -EINVAL;
1601 }
1602 if (init_attr->create_flags &
1603 mlx5_ib_create_qp_sqpn_qp1()) {
1604 mlx5_ib_dbg(dev, "user-space is not allowed to create UD QPs spoofing as QP1\n");
1605 return -EINVAL;
1606 }
1607 err = create_user_qp(dev, pd, qp, udata, init_attr, &in,
1608 &resp, &inlen, base);
1609 if (err)
1610 mlx5_ib_dbg(dev, "err %d\n", err);
1611 } else {
1612 err = create_kernel_qp(dev, init_attr, qp, &in, &inlen,
1613 base);
1614 if (err)
1615 mlx5_ib_dbg(dev, "err %d\n", err);
1616 }
1617
1618 if (err)
1619 return err;
1620 } else {
1621 in = mlx5_vzalloc(inlen);
1622 if (!in)
1623 return -ENOMEM;
1624
1625 qp->create_type = MLX5_QP_EMPTY;
1626 }
1627
1628 if (is_sqp(init_attr->qp_type))
1629 qp->port = init_attr->port_num;
1630
1631 qpc = MLX5_ADDR_OF(create_qp_in, in, qpc);
1632
1633 MLX5_SET(qpc, qpc, st, to_mlx5_st(init_attr->qp_type));
1634 MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
1635
1636 if (init_attr->qp_type != MLX5_IB_QPT_REG_UMR)
1637 MLX5_SET(qpc, qpc, pd, to_mpd(pd ? pd : devr->p0)->pdn);
1638 else
1639 MLX5_SET(qpc, qpc, latency_sensitive, 1);
1640
1641
1642 if (qp->wq_sig)
1643 MLX5_SET(qpc, qpc, wq_signature, 1);
1644
1645 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
1646 MLX5_SET(qpc, qpc, block_lb_mc, 1);
1647
1648 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
1649 MLX5_SET(qpc, qpc, cd_master, 1);
1650 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
1651 MLX5_SET(qpc, qpc, cd_slave_send, 1);
1652 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
1653 MLX5_SET(qpc, qpc, cd_slave_receive, 1);
1654
1655 if (qp->scat_cqe && is_connected(init_attr->qp_type)) {
1656 int rcqe_sz;
1657 int scqe_sz;
1658
1659 rcqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->recv_cq);
1660 scqe_sz = mlx5_ib_get_cqe_size(dev, init_attr->send_cq);
1661
1662 if (rcqe_sz == 128)
1663 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA64_CQE);
1664 else
1665 MLX5_SET(qpc, qpc, cs_res, MLX5_RES_SCAT_DATA32_CQE);
1666
1667 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) {
1668 if (scqe_sz == 128)
1669 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA64_CQE);
1670 else
1671 MLX5_SET(qpc, qpc, cs_req, MLX5_REQ_SCAT_DATA32_CQE);
1672 }
1673 }
1674
1675 if (qp->rq.wqe_cnt) {
1676 MLX5_SET(qpc, qpc, log_rq_stride, qp->rq.wqe_shift - 4);
1677 MLX5_SET(qpc, qpc, log_rq_size, ilog2(qp->rq.wqe_cnt));
1678 }
1679
1680 MLX5_SET(qpc, qpc, rq_type, get_rx_type(qp, init_attr));
1681
1682 if (qp->sq.wqe_cnt)
1683 MLX5_SET(qpc, qpc, log_sq_size, ilog2(qp->sq.wqe_cnt));
1684 else
1685 MLX5_SET(qpc, qpc, no_sq, 1);
1686
1687 /* Set default resources */
1688 switch (init_attr->qp_type) {
1689 case IB_QPT_XRC_TGT:
1690 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1691 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(devr->c0)->mcq.cqn);
1692 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1693 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(init_attr->xrcd)->xrcdn);
1694 break;
1695 case IB_QPT_XRC_INI:
1696 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(devr->c0)->mcq.cqn);
1697 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1698 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s0)->msrq.srqn);
1699 break;
1700 default:
1701 if (init_attr->srq) {
1702 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x0)->xrcdn);
1703 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(init_attr->srq)->msrq.srqn);
1704 } else {
1705 MLX5_SET(qpc, qpc, xrcd, to_mxrcd(devr->x1)->xrcdn);
1706 MLX5_SET(qpc, qpc, srqn_rmpn_xrqn, to_msrq(devr->s1)->msrq.srqn);
1707 }
1708 }
1709
1710 if (init_attr->send_cq)
1711 MLX5_SET(qpc, qpc, cqn_snd, to_mcq(init_attr->send_cq)->mcq.cqn);
1712
1713 if (init_attr->recv_cq)
1714 MLX5_SET(qpc, qpc, cqn_rcv, to_mcq(init_attr->recv_cq)->mcq.cqn);
1715
1716 MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
1717
1718 /* 0xffffff means we ask to work with cqe version 0 */
1719 if (MLX5_CAP_GEN(mdev, cqe_version) == MLX5_CQE_VERSION_V1)
1720 MLX5_SET(qpc, qpc, user_index, uidx);
1721
1722 /* we use IB_QP_CREATE_IPOIB_UD_LSO to indicates ipoib qp */
1723 if (init_attr->qp_type == IB_QPT_UD &&
1724 (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)) {
1725 MLX5_SET(qpc, qpc, ulp_stateless_offload_mode, 1);
1726 qp->flags |= MLX5_IB_QP_LSO;
1727 }
1728
1729 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1730 qp->raw_packet_qp.sq.ubuffer.buf_addr = ucmd.sq_buf_addr;
1731 raw_packet_qp_copy_info(qp, &qp->raw_packet_qp);
1732 err = create_raw_packet_qp(dev, qp, in, pd);
1733 } else {
1734 err = mlx5_core_create_qp(dev->mdev, &base->mqp, in, inlen);
1735 }
1736
1737 if (err) {
1738 mlx5_ib_dbg(dev, "create qp failed\n");
1739 goto err_create;
1740 }
1741
1742 kvfree(in);
1743
1744 base->container_mibqp = qp;
1745 base->mqp.event = mlx5_ib_qp_event;
1746
1747 get_cqs(init_attr->qp_type, init_attr->send_cq, init_attr->recv_cq,
1748 &send_cq, &recv_cq);
1749 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1750 mlx5_ib_lock_cqs(send_cq, recv_cq);
1751 /* Maintain device to QPs access, needed for further handling via reset
1752 * flow
1753 */
1754 list_add_tail(&qp->qps_list, &dev->qp_list);
1755 /* Maintain CQ to QPs access, needed for further handling via reset flow
1756 */
1757 if (send_cq)
1758 list_add_tail(&qp->cq_send_list, &send_cq->list_send_qp);
1759 if (recv_cq)
1760 list_add_tail(&qp->cq_recv_list, &recv_cq->list_recv_qp);
1761 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1762 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1763
1764 return 0;
1765
1766 err_create:
1767 if (qp->create_type == MLX5_QP_USER)
1768 destroy_qp_user(pd, qp, base);
1769 else if (qp->create_type == MLX5_QP_KERNEL)
1770 destroy_qp_kernel(dev, qp);
1771
1772 kvfree(in);
1773 return err;
1774 }
1775
1776 static void mlx5_ib_lock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1777 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1778 {
1779 if (send_cq) {
1780 if (recv_cq) {
1781 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1782 spin_lock(&send_cq->lock);
1783 spin_lock_nested(&recv_cq->lock,
1784 SINGLE_DEPTH_NESTING);
1785 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1786 spin_lock(&send_cq->lock);
1787 __acquire(&recv_cq->lock);
1788 } else {
1789 spin_lock(&recv_cq->lock);
1790 spin_lock_nested(&send_cq->lock,
1791 SINGLE_DEPTH_NESTING);
1792 }
1793 } else {
1794 spin_lock(&send_cq->lock);
1795 __acquire(&recv_cq->lock);
1796 }
1797 } else if (recv_cq) {
1798 spin_lock(&recv_cq->lock);
1799 __acquire(&send_cq->lock);
1800 } else {
1801 __acquire(&send_cq->lock);
1802 __acquire(&recv_cq->lock);
1803 }
1804 }
1805
1806 static void mlx5_ib_unlock_cqs(struct mlx5_ib_cq *send_cq, struct mlx5_ib_cq *recv_cq)
1807 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1808 {
1809 if (send_cq) {
1810 if (recv_cq) {
1811 if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1812 spin_unlock(&recv_cq->lock);
1813 spin_unlock(&send_cq->lock);
1814 } else if (send_cq->mcq.cqn == recv_cq->mcq.cqn) {
1815 __release(&recv_cq->lock);
1816 spin_unlock(&send_cq->lock);
1817 } else {
1818 spin_unlock(&send_cq->lock);
1819 spin_unlock(&recv_cq->lock);
1820 }
1821 } else {
1822 __release(&recv_cq->lock);
1823 spin_unlock(&send_cq->lock);
1824 }
1825 } else if (recv_cq) {
1826 __release(&send_cq->lock);
1827 spin_unlock(&recv_cq->lock);
1828 } else {
1829 __release(&recv_cq->lock);
1830 __release(&send_cq->lock);
1831 }
1832 }
1833
1834 static struct mlx5_ib_pd *get_pd(struct mlx5_ib_qp *qp)
1835 {
1836 return to_mpd(qp->ibqp.pd);
1837 }
1838
1839 static void get_cqs(enum ib_qp_type qp_type,
1840 struct ib_cq *ib_send_cq, struct ib_cq *ib_recv_cq,
1841 struct mlx5_ib_cq **send_cq, struct mlx5_ib_cq **recv_cq)
1842 {
1843 switch (qp_type) {
1844 case IB_QPT_XRC_TGT:
1845 *send_cq = NULL;
1846 *recv_cq = NULL;
1847 break;
1848 case MLX5_IB_QPT_REG_UMR:
1849 case IB_QPT_XRC_INI:
1850 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1851 *recv_cq = NULL;
1852 break;
1853
1854 case IB_QPT_SMI:
1855 case MLX5_IB_QPT_HW_GSI:
1856 case IB_QPT_RC:
1857 case IB_QPT_UC:
1858 case IB_QPT_UD:
1859 case IB_QPT_RAW_IPV6:
1860 case IB_QPT_RAW_ETHERTYPE:
1861 case IB_QPT_RAW_PACKET:
1862 *send_cq = ib_send_cq ? to_mcq(ib_send_cq) : NULL;
1863 *recv_cq = ib_recv_cq ? to_mcq(ib_recv_cq) : NULL;
1864 break;
1865
1866 case IB_QPT_MAX:
1867 default:
1868 *send_cq = NULL;
1869 *recv_cq = NULL;
1870 break;
1871 }
1872 }
1873
1874 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
1875 const struct mlx5_modify_raw_qp_param *raw_qp_param,
1876 u8 lag_tx_affinity);
1877
1878 static void destroy_qp_common(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp)
1879 {
1880 struct mlx5_ib_cq *send_cq, *recv_cq;
1881 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
1882 unsigned long flags;
1883 int err;
1884
1885 if (qp->ibqp.rwq_ind_tbl) {
1886 destroy_rss_raw_qp_tir(dev, qp);
1887 return;
1888 }
1889
1890 base = qp->ibqp.qp_type == IB_QPT_RAW_PACKET ?
1891 &qp->raw_packet_qp.rq.base :
1892 &qp->trans_qp.base;
1893
1894 if (qp->state != IB_QPS_RESET) {
1895 if (qp->ibqp.qp_type != IB_QPT_RAW_PACKET) {
1896 mlx5_ib_qp_disable_pagefaults(qp);
1897 err = mlx5_core_qp_modify(dev->mdev,
1898 MLX5_CMD_OP_2RST_QP, 0,
1899 NULL, &base->mqp);
1900 } else {
1901 struct mlx5_modify_raw_qp_param raw_qp_param = {
1902 .operation = MLX5_CMD_OP_2RST_QP
1903 };
1904
1905 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, 0);
1906 }
1907 if (err)
1908 mlx5_ib_warn(dev, "mlx5_ib: modify QP 0x%06x to RESET failed\n",
1909 base->mqp.qpn);
1910 }
1911
1912 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
1913 &send_cq, &recv_cq);
1914
1915 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1916 mlx5_ib_lock_cqs(send_cq, recv_cq);
1917 /* del from lists under both locks above to protect reset flow paths */
1918 list_del(&qp->qps_list);
1919 if (send_cq)
1920 list_del(&qp->cq_send_list);
1921
1922 if (recv_cq)
1923 list_del(&qp->cq_recv_list);
1924
1925 if (qp->create_type == MLX5_QP_KERNEL) {
1926 __mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
1927 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1928 if (send_cq != recv_cq)
1929 __mlx5_ib_cq_clean(send_cq, base->mqp.qpn,
1930 NULL);
1931 }
1932 mlx5_ib_unlock_cqs(send_cq, recv_cq);
1933 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1934
1935 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
1936 destroy_raw_packet_qp(dev, qp);
1937 } else {
1938 err = mlx5_core_destroy_qp(dev->mdev, &base->mqp);
1939 if (err)
1940 mlx5_ib_warn(dev, "failed to destroy QP 0x%x\n",
1941 base->mqp.qpn);
1942 }
1943
1944 if (qp->create_type == MLX5_QP_KERNEL)
1945 destroy_qp_kernel(dev, qp);
1946 else if (qp->create_type == MLX5_QP_USER)
1947 destroy_qp_user(&get_pd(qp)->ibpd, qp, base);
1948 }
1949
1950 static const char *ib_qp_type_str(enum ib_qp_type type)
1951 {
1952 switch (type) {
1953 case IB_QPT_SMI:
1954 return "IB_QPT_SMI";
1955 case IB_QPT_GSI:
1956 return "IB_QPT_GSI";
1957 case IB_QPT_RC:
1958 return "IB_QPT_RC";
1959 case IB_QPT_UC:
1960 return "IB_QPT_UC";
1961 case IB_QPT_UD:
1962 return "IB_QPT_UD";
1963 case IB_QPT_RAW_IPV6:
1964 return "IB_QPT_RAW_IPV6";
1965 case IB_QPT_RAW_ETHERTYPE:
1966 return "IB_QPT_RAW_ETHERTYPE";
1967 case IB_QPT_XRC_INI:
1968 return "IB_QPT_XRC_INI";
1969 case IB_QPT_XRC_TGT:
1970 return "IB_QPT_XRC_TGT";
1971 case IB_QPT_RAW_PACKET:
1972 return "IB_QPT_RAW_PACKET";
1973 case MLX5_IB_QPT_REG_UMR:
1974 return "MLX5_IB_QPT_REG_UMR";
1975 case IB_QPT_MAX:
1976 default:
1977 return "Invalid QP type";
1978 }
1979 }
1980
1981 struct ib_qp *mlx5_ib_create_qp(struct ib_pd *pd,
1982 struct ib_qp_init_attr *init_attr,
1983 struct ib_udata *udata)
1984 {
1985 struct mlx5_ib_dev *dev;
1986 struct mlx5_ib_qp *qp;
1987 u16 xrcdn = 0;
1988 int err;
1989
1990 if (pd) {
1991 dev = to_mdev(pd->device);
1992
1993 if (init_attr->qp_type == IB_QPT_RAW_PACKET) {
1994 if (!pd->uobject) {
1995 mlx5_ib_dbg(dev, "Raw Packet QP is not supported for kernel consumers\n");
1996 return ERR_PTR(-EINVAL);
1997 } else if (!to_mucontext(pd->uobject->context)->cqe_version) {
1998 mlx5_ib_dbg(dev, "Raw Packet QP is only supported for CQE version > 0\n");
1999 return ERR_PTR(-EINVAL);
2000 }
2001 }
2002 } else {
2003 /* being cautious here */
2004 if (init_attr->qp_type != IB_QPT_XRC_TGT &&
2005 init_attr->qp_type != MLX5_IB_QPT_REG_UMR) {
2006 pr_warn("%s: no PD for transport %s\n", __func__,
2007 ib_qp_type_str(init_attr->qp_type));
2008 return ERR_PTR(-EINVAL);
2009 }
2010 dev = to_mdev(to_mxrcd(init_attr->xrcd)->ibxrcd.device);
2011 }
2012
2013 switch (init_attr->qp_type) {
2014 case IB_QPT_XRC_TGT:
2015 case IB_QPT_XRC_INI:
2016 if (!MLX5_CAP_GEN(dev->mdev, xrc)) {
2017 mlx5_ib_dbg(dev, "XRC not supported\n");
2018 return ERR_PTR(-ENOSYS);
2019 }
2020 init_attr->recv_cq = NULL;
2021 if (init_attr->qp_type == IB_QPT_XRC_TGT) {
2022 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
2023 init_attr->send_cq = NULL;
2024 }
2025
2026 /* fall through */
2027 case IB_QPT_RAW_PACKET:
2028 case IB_QPT_RC:
2029 case IB_QPT_UC:
2030 case IB_QPT_UD:
2031 case IB_QPT_SMI:
2032 case MLX5_IB_QPT_HW_GSI:
2033 case MLX5_IB_QPT_REG_UMR:
2034 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
2035 if (!qp)
2036 return ERR_PTR(-ENOMEM);
2037
2038 err = create_qp_common(dev, pd, init_attr, udata, qp);
2039 if (err) {
2040 mlx5_ib_dbg(dev, "create_qp_common failed\n");
2041 kfree(qp);
2042 return ERR_PTR(err);
2043 }
2044
2045 if (is_qp0(init_attr->qp_type))
2046 qp->ibqp.qp_num = 0;
2047 else if (is_qp1(init_attr->qp_type))
2048 qp->ibqp.qp_num = 1;
2049 else
2050 qp->ibqp.qp_num = qp->trans_qp.base.mqp.qpn;
2051
2052 mlx5_ib_dbg(dev, "ib qpnum 0x%x, mlx qpn 0x%x, rcqn 0x%x, scqn 0x%x\n",
2053 qp->ibqp.qp_num, qp->trans_qp.base.mqp.qpn,
2054 init_attr->recv_cq ? to_mcq(init_attr->recv_cq)->mcq.cqn : -1,
2055 init_attr->send_cq ? to_mcq(init_attr->send_cq)->mcq.cqn : -1);
2056
2057 qp->trans_qp.xrcdn = xrcdn;
2058
2059 break;
2060
2061 case IB_QPT_GSI:
2062 return mlx5_ib_gsi_create_qp(pd, init_attr);
2063
2064 case IB_QPT_RAW_IPV6:
2065 case IB_QPT_RAW_ETHERTYPE:
2066 case IB_QPT_MAX:
2067 default:
2068 mlx5_ib_dbg(dev, "unsupported qp type %d\n",
2069 init_attr->qp_type);
2070 /* Don't support raw QPs */
2071 return ERR_PTR(-EINVAL);
2072 }
2073
2074 return &qp->ibqp;
2075 }
2076
2077 int mlx5_ib_destroy_qp(struct ib_qp *qp)
2078 {
2079 struct mlx5_ib_dev *dev = to_mdev(qp->device);
2080 struct mlx5_ib_qp *mqp = to_mqp(qp);
2081
2082 if (unlikely(qp->qp_type == IB_QPT_GSI))
2083 return mlx5_ib_gsi_destroy_qp(qp);
2084
2085 destroy_qp_common(dev, mqp);
2086
2087 kfree(mqp);
2088
2089 return 0;
2090 }
2091
2092 static __be32 to_mlx5_access_flags(struct mlx5_ib_qp *qp, const struct ib_qp_attr *attr,
2093 int attr_mask)
2094 {
2095 u32 hw_access_flags = 0;
2096 u8 dest_rd_atomic;
2097 u32 access_flags;
2098
2099 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2100 dest_rd_atomic = attr->max_dest_rd_atomic;
2101 else
2102 dest_rd_atomic = qp->trans_qp.resp_depth;
2103
2104 if (attr_mask & IB_QP_ACCESS_FLAGS)
2105 access_flags = attr->qp_access_flags;
2106 else
2107 access_flags = qp->trans_qp.atomic_rd_en;
2108
2109 if (!dest_rd_atomic)
2110 access_flags &= IB_ACCESS_REMOTE_WRITE;
2111
2112 if (access_flags & IB_ACCESS_REMOTE_READ)
2113 hw_access_flags |= MLX5_QP_BIT_RRE;
2114 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
2115 hw_access_flags |= (MLX5_QP_BIT_RAE | MLX5_ATOMIC_MODE_CX);
2116 if (access_flags & IB_ACCESS_REMOTE_WRITE)
2117 hw_access_flags |= MLX5_QP_BIT_RWE;
2118
2119 return cpu_to_be32(hw_access_flags);
2120 }
2121
2122 enum {
2123 MLX5_PATH_FLAG_FL = 1 << 0,
2124 MLX5_PATH_FLAG_FREE_AR = 1 << 1,
2125 MLX5_PATH_FLAG_COUNTER = 1 << 2,
2126 };
2127
2128 static int ib_rate_to_mlx5(struct mlx5_ib_dev *dev, u8 rate)
2129 {
2130 if (rate == IB_RATE_PORT_CURRENT) {
2131 return 0;
2132 } else if (rate < IB_RATE_2_5_GBPS || rate > IB_RATE_300_GBPS) {
2133 return -EINVAL;
2134 } else {
2135 while (rate != IB_RATE_2_5_GBPS &&
2136 !(1 << (rate + MLX5_STAT_RATE_OFFSET) &
2137 MLX5_CAP_GEN(dev->mdev, stat_rate_support)))
2138 --rate;
2139 }
2140
2141 return rate + MLX5_STAT_RATE_OFFSET;
2142 }
2143
2144 static int modify_raw_packet_eth_prio(struct mlx5_core_dev *dev,
2145 struct mlx5_ib_sq *sq, u8 sl)
2146 {
2147 void *in;
2148 void *tisc;
2149 int inlen;
2150 int err;
2151
2152 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2153 in = mlx5_vzalloc(inlen);
2154 if (!in)
2155 return -ENOMEM;
2156
2157 MLX5_SET(modify_tis_in, in, bitmask.prio, 1);
2158
2159 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2160 MLX5_SET(tisc, tisc, prio, ((sl & 0x7) << 1));
2161
2162 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2163
2164 kvfree(in);
2165
2166 return err;
2167 }
2168
2169 static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
2170 struct mlx5_ib_sq *sq, u8 tx_affinity)
2171 {
2172 void *in;
2173 void *tisc;
2174 int inlen;
2175 int err;
2176
2177 inlen = MLX5_ST_SZ_BYTES(modify_tis_in);
2178 in = mlx5_vzalloc(inlen);
2179 if (!in)
2180 return -ENOMEM;
2181
2182 MLX5_SET(modify_tis_in, in, bitmask.lag_tx_port_affinity, 1);
2183
2184 tisc = MLX5_ADDR_OF(modify_tis_in, in, ctx);
2185 MLX5_SET(tisc, tisc, lag_tx_port_affinity, tx_affinity);
2186
2187 err = mlx5_core_modify_tis(dev, sq->tisn, in, inlen);
2188
2189 kvfree(in);
2190
2191 return err;
2192 }
2193
2194 static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2195 const struct ib_ah_attr *ah,
2196 struct mlx5_qp_path *path, u8 port, int attr_mask,
2197 u32 path_flags, const struct ib_qp_attr *attr,
2198 bool alt)
2199 {
2200 enum rdma_link_layer ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2201 int err;
2202
2203 if (attr_mask & IB_QP_PKEY_INDEX)
2204 path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
2205 attr->pkey_index);
2206
2207 if (ah->ah_flags & IB_AH_GRH) {
2208 if (ah->grh.sgid_index >=
2209 dev->mdev->port_caps[port - 1].gid_table_len) {
2210 pr_err("sgid_index (%u) too large. max is %d\n",
2211 ah->grh.sgid_index,
2212 dev->mdev->port_caps[port - 1].gid_table_len);
2213 return -EINVAL;
2214 }
2215 }
2216
2217 if (ll == IB_LINK_LAYER_ETHERNET) {
2218 if (!(ah->ah_flags & IB_AH_GRH))
2219 return -EINVAL;
2220 memcpy(path->rmac, ah->dmac, sizeof(ah->dmac));
2221 path->udp_sport = mlx5_get_roce_udp_sport(dev, port,
2222 ah->grh.sgid_index);
2223 path->dci_cfi_prio_sl = (ah->sl & 0x7) << 4;
2224 } else {
2225 path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
2226 path->fl_free_ar |=
2227 (path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
2228 path->rlid = cpu_to_be16(ah->dlid);
2229 path->grh_mlid = ah->src_path_bits & 0x7f;
2230 if (ah->ah_flags & IB_AH_GRH)
2231 path->grh_mlid |= 1 << 7;
2232 path->dci_cfi_prio_sl = ah->sl & 0xf;
2233 }
2234
2235 if (ah->ah_flags & IB_AH_GRH) {
2236 path->mgid_index = ah->grh.sgid_index;
2237 path->hop_limit = ah->grh.hop_limit;
2238 path->tclass_flowlabel =
2239 cpu_to_be32((ah->grh.traffic_class << 20) |
2240 (ah->grh.flow_label));
2241 memcpy(path->rgid, ah->grh.dgid.raw, 16);
2242 }
2243
2244 err = ib_rate_to_mlx5(dev, ah->static_rate);
2245 if (err < 0)
2246 return err;
2247 path->static_rate = err;
2248 path->port = port;
2249
2250 if (attr_mask & IB_QP_TIMEOUT)
2251 path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
2252
2253 if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
2254 return modify_raw_packet_eth_prio(dev->mdev,
2255 &qp->raw_packet_qp.sq,
2256 ah->sl & 0xf);
2257
2258 return 0;
2259 }
2260
2261 static enum mlx5_qp_optpar opt_mask[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE][MLX5_QP_ST_MAX] = {
2262 [MLX5_QP_STATE_INIT] = {
2263 [MLX5_QP_STATE_INIT] = {
2264 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2265 MLX5_QP_OPTPAR_RAE |
2266 MLX5_QP_OPTPAR_RWE |
2267 MLX5_QP_OPTPAR_PKEY_INDEX |
2268 MLX5_QP_OPTPAR_PRI_PORT,
2269 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2270 MLX5_QP_OPTPAR_PKEY_INDEX |
2271 MLX5_QP_OPTPAR_PRI_PORT,
2272 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2273 MLX5_QP_OPTPAR_Q_KEY |
2274 MLX5_QP_OPTPAR_PRI_PORT,
2275 },
2276 [MLX5_QP_STATE_RTR] = {
2277 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2278 MLX5_QP_OPTPAR_RRE |
2279 MLX5_QP_OPTPAR_RAE |
2280 MLX5_QP_OPTPAR_RWE |
2281 MLX5_QP_OPTPAR_PKEY_INDEX,
2282 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2283 MLX5_QP_OPTPAR_RWE |
2284 MLX5_QP_OPTPAR_PKEY_INDEX,
2285 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_PKEY_INDEX |
2286 MLX5_QP_OPTPAR_Q_KEY,
2287 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_PKEY_INDEX |
2288 MLX5_QP_OPTPAR_Q_KEY,
2289 [MLX5_QP_ST_XRC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2290 MLX5_QP_OPTPAR_RRE |
2291 MLX5_QP_OPTPAR_RAE |
2292 MLX5_QP_OPTPAR_RWE |
2293 MLX5_QP_OPTPAR_PKEY_INDEX,
2294 },
2295 },
2296 [MLX5_QP_STATE_RTR] = {
2297 [MLX5_QP_STATE_RTS] = {
2298 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2299 MLX5_QP_OPTPAR_RRE |
2300 MLX5_QP_OPTPAR_RAE |
2301 MLX5_QP_OPTPAR_RWE |
2302 MLX5_QP_OPTPAR_PM_STATE |
2303 MLX5_QP_OPTPAR_RNR_TIMEOUT,
2304 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_ALT_ADDR_PATH |
2305 MLX5_QP_OPTPAR_RWE |
2306 MLX5_QP_OPTPAR_PM_STATE,
2307 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2308 },
2309 },
2310 [MLX5_QP_STATE_RTS] = {
2311 [MLX5_QP_STATE_RTS] = {
2312 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RRE |
2313 MLX5_QP_OPTPAR_RAE |
2314 MLX5_QP_OPTPAR_RWE |
2315 MLX5_QP_OPTPAR_RNR_TIMEOUT |
2316 MLX5_QP_OPTPAR_PM_STATE |
2317 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2318 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE |
2319 MLX5_QP_OPTPAR_PM_STATE |
2320 MLX5_QP_OPTPAR_ALT_ADDR_PATH,
2321 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY |
2322 MLX5_QP_OPTPAR_SRQN |
2323 MLX5_QP_OPTPAR_CQN_RCV,
2324 },
2325 },
2326 [MLX5_QP_STATE_SQER] = {
2327 [MLX5_QP_STATE_RTS] = {
2328 [MLX5_QP_ST_UD] = MLX5_QP_OPTPAR_Q_KEY,
2329 [MLX5_QP_ST_MLX] = MLX5_QP_OPTPAR_Q_KEY,
2330 [MLX5_QP_ST_UC] = MLX5_QP_OPTPAR_RWE,
2331 [MLX5_QP_ST_RC] = MLX5_QP_OPTPAR_RNR_TIMEOUT |
2332 MLX5_QP_OPTPAR_RWE |
2333 MLX5_QP_OPTPAR_RAE |
2334 MLX5_QP_OPTPAR_RRE,
2335 },
2336 },
2337 };
2338
2339 static int ib_nr_to_mlx5_nr(int ib_mask)
2340 {
2341 switch (ib_mask) {
2342 case IB_QP_STATE:
2343 return 0;
2344 case IB_QP_CUR_STATE:
2345 return 0;
2346 case IB_QP_EN_SQD_ASYNC_NOTIFY:
2347 return 0;
2348 case IB_QP_ACCESS_FLAGS:
2349 return MLX5_QP_OPTPAR_RWE | MLX5_QP_OPTPAR_RRE |
2350 MLX5_QP_OPTPAR_RAE;
2351 case IB_QP_PKEY_INDEX:
2352 return MLX5_QP_OPTPAR_PKEY_INDEX;
2353 case IB_QP_PORT:
2354 return MLX5_QP_OPTPAR_PRI_PORT;
2355 case IB_QP_QKEY:
2356 return MLX5_QP_OPTPAR_Q_KEY;
2357 case IB_QP_AV:
2358 return MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH |
2359 MLX5_QP_OPTPAR_PRI_PORT;
2360 case IB_QP_PATH_MTU:
2361 return 0;
2362 case IB_QP_TIMEOUT:
2363 return MLX5_QP_OPTPAR_ACK_TIMEOUT;
2364 case IB_QP_RETRY_CNT:
2365 return MLX5_QP_OPTPAR_RETRY_COUNT;
2366 case IB_QP_RNR_RETRY:
2367 return MLX5_QP_OPTPAR_RNR_RETRY;
2368 case IB_QP_RQ_PSN:
2369 return 0;
2370 case IB_QP_MAX_QP_RD_ATOMIC:
2371 return MLX5_QP_OPTPAR_SRA_MAX;
2372 case IB_QP_ALT_PATH:
2373 return MLX5_QP_OPTPAR_ALT_ADDR_PATH;
2374 case IB_QP_MIN_RNR_TIMER:
2375 return MLX5_QP_OPTPAR_RNR_TIMEOUT;
2376 case IB_QP_SQ_PSN:
2377 return 0;
2378 case IB_QP_MAX_DEST_RD_ATOMIC:
2379 return MLX5_QP_OPTPAR_RRA_MAX | MLX5_QP_OPTPAR_RWE |
2380 MLX5_QP_OPTPAR_RRE | MLX5_QP_OPTPAR_RAE;
2381 case IB_QP_PATH_MIG_STATE:
2382 return MLX5_QP_OPTPAR_PM_STATE;
2383 case IB_QP_CAP:
2384 return 0;
2385 case IB_QP_DEST_QPN:
2386 return 0;
2387 }
2388 return 0;
2389 }
2390
2391 static int ib_mask_to_mlx5_opt(int ib_mask)
2392 {
2393 int result = 0;
2394 int i;
2395
2396 for (i = 0; i < 8 * sizeof(int); i++) {
2397 if ((1 << i) & ib_mask)
2398 result |= ib_nr_to_mlx5_nr(1 << i);
2399 }
2400
2401 return result;
2402 }
2403
2404 static int modify_raw_packet_qp_rq(struct mlx5_ib_dev *dev,
2405 struct mlx5_ib_rq *rq, int new_state,
2406 const struct mlx5_modify_raw_qp_param *raw_qp_param)
2407 {
2408 void *in;
2409 void *rqc;
2410 int inlen;
2411 int err;
2412
2413 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
2414 in = mlx5_vzalloc(inlen);
2415 if (!in)
2416 return -ENOMEM;
2417
2418 MLX5_SET(modify_rq_in, in, rq_state, rq->state);
2419
2420 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
2421 MLX5_SET(rqc, rqc, state, new_state);
2422
2423 if (raw_qp_param->set_mask & MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID) {
2424 if (MLX5_CAP_GEN(dev->mdev, modify_rq_counter_set_id)) {
2425 MLX5_SET64(modify_rq_in, in, modify_bitmask,
2426 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_MODIFY_RQ_COUNTER_SET_ID);
2427 MLX5_SET(rqc, rqc, counter_set_id, raw_qp_param->rq_q_ctr_id);
2428 } else
2429 pr_info_once("%s: RAW PACKET QP counters are not supported on current FW\n",
2430 dev->ib_dev.name);
2431 }
2432
2433 err = mlx5_core_modify_rq(dev->mdev, rq->base.mqp.qpn, in, inlen);
2434 if (err)
2435 goto out;
2436
2437 rq->state = new_state;
2438
2439 out:
2440 kvfree(in);
2441 return err;
2442 }
2443
2444 static int modify_raw_packet_qp_sq(struct mlx5_core_dev *dev,
2445 struct mlx5_ib_sq *sq, int new_state)
2446 {
2447 void *in;
2448 void *sqc;
2449 int inlen;
2450 int err;
2451
2452 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
2453 in = mlx5_vzalloc(inlen);
2454 if (!in)
2455 return -ENOMEM;
2456
2457 MLX5_SET(modify_sq_in, in, sq_state, sq->state);
2458
2459 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
2460 MLX5_SET(sqc, sqc, state, new_state);
2461
2462 err = mlx5_core_modify_sq(dev, sq->base.mqp.qpn, in, inlen);
2463 if (err)
2464 goto out;
2465
2466 sq->state = new_state;
2467
2468 out:
2469 kvfree(in);
2470 return err;
2471 }
2472
2473 static int modify_raw_packet_qp(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
2474 const struct mlx5_modify_raw_qp_param *raw_qp_param,
2475 u8 tx_affinity)
2476 {
2477 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
2478 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
2479 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
2480 int rq_state;
2481 int sq_state;
2482 int err;
2483
2484 switch (raw_qp_param->operation) {
2485 case MLX5_CMD_OP_RST2INIT_QP:
2486 rq_state = MLX5_RQC_STATE_RDY;
2487 sq_state = MLX5_SQC_STATE_RDY;
2488 break;
2489 case MLX5_CMD_OP_2ERR_QP:
2490 rq_state = MLX5_RQC_STATE_ERR;
2491 sq_state = MLX5_SQC_STATE_ERR;
2492 break;
2493 case MLX5_CMD_OP_2RST_QP:
2494 rq_state = MLX5_RQC_STATE_RST;
2495 sq_state = MLX5_SQC_STATE_RST;
2496 break;
2497 case MLX5_CMD_OP_INIT2INIT_QP:
2498 case MLX5_CMD_OP_INIT2RTR_QP:
2499 case MLX5_CMD_OP_RTR2RTS_QP:
2500 case MLX5_CMD_OP_RTS2RTS_QP:
2501 if (raw_qp_param->set_mask)
2502 return -EINVAL;
2503 else
2504 return 0;
2505 default:
2506 WARN_ON(1);
2507 return -EINVAL;
2508 }
2509
2510 if (qp->rq.wqe_cnt) {
2511 err = modify_raw_packet_qp_rq(dev, rq, rq_state, raw_qp_param);
2512 if (err)
2513 return err;
2514 }
2515
2516 if (qp->sq.wqe_cnt) {
2517 if (tx_affinity) {
2518 err = modify_raw_packet_tx_affinity(dev->mdev, sq,
2519 tx_affinity);
2520 if (err)
2521 return err;
2522 }
2523
2524 return modify_raw_packet_qp_sq(dev->mdev, sq, sq_state);
2525 }
2526
2527 return 0;
2528 }
2529
2530 static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
2531 const struct ib_qp_attr *attr, int attr_mask,
2532 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2533 {
2534 static const u16 optab[MLX5_QP_NUM_STATE][MLX5_QP_NUM_STATE] = {
2535 [MLX5_QP_STATE_RST] = {
2536 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2537 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2538 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_RST2INIT_QP,
2539 },
2540 [MLX5_QP_STATE_INIT] = {
2541 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2542 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2543 [MLX5_QP_STATE_INIT] = MLX5_CMD_OP_INIT2INIT_QP,
2544 [MLX5_QP_STATE_RTR] = MLX5_CMD_OP_INIT2RTR_QP,
2545 },
2546 [MLX5_QP_STATE_RTR] = {
2547 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2548 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2549 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTR2RTS_QP,
2550 },
2551 [MLX5_QP_STATE_RTS] = {
2552 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2553 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2554 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_RTS2RTS_QP,
2555 },
2556 [MLX5_QP_STATE_SQD] = {
2557 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2558 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2559 },
2560 [MLX5_QP_STATE_SQER] = {
2561 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2562 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2563 [MLX5_QP_STATE_RTS] = MLX5_CMD_OP_SQERR2RTS_QP,
2564 },
2565 [MLX5_QP_STATE_ERR] = {
2566 [MLX5_QP_STATE_RST] = MLX5_CMD_OP_2RST_QP,
2567 [MLX5_QP_STATE_ERR] = MLX5_CMD_OP_2ERR_QP,
2568 }
2569 };
2570
2571 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2572 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2573 struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
2574 struct mlx5_ib_cq *send_cq, *recv_cq;
2575 struct mlx5_qp_context *context;
2576 struct mlx5_ib_pd *pd;
2577 struct mlx5_ib_port *mibport = NULL;
2578 enum mlx5_qp_state mlx5_cur, mlx5_new;
2579 enum mlx5_qp_optpar optpar;
2580 int sqd_event;
2581 int mlx5_st;
2582 int err;
2583 u16 op;
2584 u8 tx_affinity = 0;
2585
2586 context = kzalloc(sizeof(*context), GFP_KERNEL);
2587 if (!context)
2588 return -ENOMEM;
2589
2590 err = to_mlx5_st(ibqp->qp_type);
2591 if (err < 0) {
2592 mlx5_ib_dbg(dev, "unsupported qp type %d\n", ibqp->qp_type);
2593 goto out;
2594 }
2595
2596 context->flags = cpu_to_be32(err << 16);
2597
2598 if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
2599 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2600 } else {
2601 switch (attr->path_mig_state) {
2602 case IB_MIG_MIGRATED:
2603 context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
2604 break;
2605 case IB_MIG_REARM:
2606 context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
2607 break;
2608 case IB_MIG_ARMED:
2609 context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
2610 break;
2611 }
2612 }
2613
2614 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2615 if ((ibqp->qp_type == IB_QPT_RC) ||
2616 (ibqp->qp_type == IB_QPT_UD &&
2617 !(qp->flags & MLX5_IB_QP_SQPN_QP1)) ||
2618 (ibqp->qp_type == IB_QPT_UC) ||
2619 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2620 (ibqp->qp_type == IB_QPT_XRC_INI) ||
2621 (ibqp->qp_type == IB_QPT_XRC_TGT)) {
2622 if (mlx5_lag_is_active(dev->mdev)) {
2623 tx_affinity = (unsigned int)atomic_add_return(1,
2624 &dev->roce.next_port) %
2625 MLX5_MAX_PORTS + 1;
2626 context->flags |= cpu_to_be32(tx_affinity << 24);
2627 }
2628 }
2629 }
2630
2631 if (is_sqp(ibqp->qp_type)) {
2632 context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
2633 } else if (ibqp->qp_type == IB_QPT_UD ||
2634 ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
2635 context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
2636 } else if (attr_mask & IB_QP_PATH_MTU) {
2637 if (attr->path_mtu < IB_MTU_256 ||
2638 attr->path_mtu > IB_MTU_4096) {
2639 mlx5_ib_warn(dev, "invalid mtu %d\n", attr->path_mtu);
2640 err = -EINVAL;
2641 goto out;
2642 }
2643 context->mtu_msgmax = (attr->path_mtu << 5) |
2644 (u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
2645 }
2646
2647 if (attr_mask & IB_QP_DEST_QPN)
2648 context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
2649
2650 if (attr_mask & IB_QP_PKEY_INDEX)
2651 context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
2652
2653 /* todo implement counter_index functionality */
2654
2655 if (is_sqp(ibqp->qp_type))
2656 context->pri_path.port = qp->port;
2657
2658 if (attr_mask & IB_QP_PORT)
2659 context->pri_path.port = attr->port_num;
2660
2661 if (attr_mask & IB_QP_AV) {
2662 err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
2663 attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
2664 attr_mask, 0, attr, false);
2665 if (err)
2666 goto out;
2667 }
2668
2669 if (attr_mask & IB_QP_TIMEOUT)
2670 context->pri_path.ackto_lt |= attr->timeout << 3;
2671
2672 if (attr_mask & IB_QP_ALT_PATH) {
2673 err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
2674 &context->alt_path,
2675 attr->alt_port_num,
2676 attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
2677 0, attr, true);
2678 if (err)
2679 goto out;
2680 }
2681
2682 pd = get_pd(qp);
2683 get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
2684 &send_cq, &recv_cq);
2685
2686 context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
2687 context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
2688 context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
2689 context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
2690
2691 if (attr_mask & IB_QP_RNR_RETRY)
2692 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2693
2694 if (attr_mask & IB_QP_RETRY_CNT)
2695 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2696
2697 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2698 if (attr->max_rd_atomic)
2699 context->params1 |=
2700 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2701 }
2702
2703 if (attr_mask & IB_QP_SQ_PSN)
2704 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2705
2706 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2707 if (attr->max_dest_rd_atomic)
2708 context->params2 |=
2709 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2710 }
2711
2712 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC))
2713 context->params2 |= to_mlx5_access_flags(qp, attr, attr_mask);
2714
2715 if (attr_mask & IB_QP_MIN_RNR_TIMER)
2716 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2717
2718 if (attr_mask & IB_QP_RQ_PSN)
2719 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2720
2721 if (attr_mask & IB_QP_QKEY)
2722 context->qkey = cpu_to_be32(attr->qkey);
2723
2724 if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2725 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2726
2727 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2728 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2729 sqd_event = 1;
2730 else
2731 sqd_event = 0;
2732
2733 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2734 u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
2735 qp->port) - 1;
2736 mibport = &dev->port[port_num];
2737 context->qp_counter_set_usr_page |=
2738 cpu_to_be32((u32)(mibport->q_cnt_id) << 24);
2739 }
2740
2741 if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
2742 context->sq_crq_size |= cpu_to_be16(1 << 4);
2743
2744 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
2745 context->deth_sqpn = cpu_to_be32(1);
2746
2747 mlx5_cur = to_mlx5_state(cur_state);
2748 mlx5_new = to_mlx5_state(new_state);
2749 mlx5_st = to_mlx5_st(ibqp->qp_type);
2750 if (mlx5_st < 0)
2751 goto out;
2752
2753 /* If moving to a reset or error state, we must disable page faults on
2754 * this QP and flush all current page faults. Otherwise a stale page
2755 * fault may attempt to work on this QP after it is reset and moved
2756 * again to RTS, and may cause the driver and the device to get out of
2757 * sync. */
2758 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2759 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR) &&
2760 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2761 mlx5_ib_qp_disable_pagefaults(qp);
2762
2763 if (mlx5_cur >= MLX5_QP_NUM_STATE || mlx5_new >= MLX5_QP_NUM_STATE ||
2764 !optab[mlx5_cur][mlx5_new])
2765 goto out;
2766
2767 op = optab[mlx5_cur][mlx5_new];
2768 optpar = ib_mask_to_mlx5_opt(attr_mask);
2769 optpar &= opt_mask[mlx5_cur][mlx5_new][mlx5_st];
2770
2771 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
2772 struct mlx5_modify_raw_qp_param raw_qp_param = {};
2773
2774 raw_qp_param.operation = op;
2775 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2776 raw_qp_param.rq_q_ctr_id = mibport->q_cnt_id;
2777 raw_qp_param.set_mask |= MLX5_RAW_QP_MOD_SET_RQ_Q_CTR_ID;
2778 }
2779 err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
2780 } else {
2781 err = mlx5_core_qp_modify(dev->mdev, op, optpar, context,
2782 &base->mqp);
2783 }
2784
2785 if (err)
2786 goto out;
2787
2788 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT &&
2789 (qp->ibqp.qp_type != IB_QPT_RAW_PACKET))
2790 mlx5_ib_qp_enable_pagefaults(qp);
2791
2792 qp->state = new_state;
2793
2794 if (attr_mask & IB_QP_ACCESS_FLAGS)
2795 qp->trans_qp.atomic_rd_en = attr->qp_access_flags;
2796 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2797 qp->trans_qp.resp_depth = attr->max_dest_rd_atomic;
2798 if (attr_mask & IB_QP_PORT)
2799 qp->port = attr->port_num;
2800 if (attr_mask & IB_QP_ALT_PATH)
2801 qp->trans_qp.alt_port = attr->alt_port_num;
2802
2803 /*
2804 * If we moved a kernel QP to RESET, clean up all old CQ
2805 * entries and reinitialize the QP.
2806 */
2807 if (new_state == IB_QPS_RESET && !ibqp->uobject) {
2808 mlx5_ib_cq_clean(recv_cq, base->mqp.qpn,
2809 ibqp->srq ? to_msrq(ibqp->srq) : NULL);
2810 if (send_cq != recv_cq)
2811 mlx5_ib_cq_clean(send_cq, base->mqp.qpn, NULL);
2812
2813 qp->rq.head = 0;
2814 qp->rq.tail = 0;
2815 qp->sq.head = 0;
2816 qp->sq.tail = 0;
2817 qp->sq.cur_post = 0;
2818 qp->sq.last_poll = 0;
2819 qp->db.db[MLX5_RCV_DBR] = 0;
2820 qp->db.db[MLX5_SND_DBR] = 0;
2821 }
2822
2823 out:
2824 kfree(context);
2825 return err;
2826 }
2827
2828 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2829 int attr_mask, struct ib_udata *udata)
2830 {
2831 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
2832 struct mlx5_ib_qp *qp = to_mqp(ibqp);
2833 enum ib_qp_type qp_type;
2834 enum ib_qp_state cur_state, new_state;
2835 int err = -EINVAL;
2836 int port;
2837 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2838
2839 if (ibqp->rwq_ind_tbl)
2840 return -ENOSYS;
2841
2842 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
2843 return mlx5_ib_gsi_modify_qp(ibqp, attr, attr_mask);
2844
2845 qp_type = (unlikely(ibqp->qp_type == MLX5_IB_QPT_HW_GSI)) ?
2846 IB_QPT_GSI : ibqp->qp_type;
2847
2848 mutex_lock(&qp->mutex);
2849
2850 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2851 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2852
2853 if (!(cur_state == new_state && cur_state == IB_QPS_RESET)) {
2854 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2855 ll = dev->ib_dev.get_link_layer(&dev->ib_dev, port);
2856 }
2857
2858 if (qp_type != MLX5_IB_QPT_REG_UMR &&
2859 !ib_modify_qp_is_ok(cur_state, new_state, qp_type, attr_mask, ll)) {
2860 mlx5_ib_dbg(dev, "invalid QP state transition from %d to %d, qp_type %d, attr_mask 0x%x\n",
2861 cur_state, new_state, ibqp->qp_type, attr_mask);
2862 goto out;
2863 }
2864
2865 if ((attr_mask & IB_QP_PORT) &&
2866 (attr->port_num == 0 ||
2867 attr->port_num > MLX5_CAP_GEN(dev->mdev, num_ports))) {
2868 mlx5_ib_dbg(dev, "invalid port number %d. number of ports is %d\n",
2869 attr->port_num, dev->num_ports);
2870 goto out;
2871 }
2872
2873 if (attr_mask & IB_QP_PKEY_INDEX) {
2874 port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2875 if (attr->pkey_index >=
2876 dev->mdev->port_caps[port - 1].pkey_table_len) {
2877 mlx5_ib_dbg(dev, "invalid pkey index %d\n",
2878 attr->pkey_index);
2879 goto out;
2880 }
2881 }
2882
2883 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2884 attr->max_rd_atomic >
2885 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_res_qp))) {
2886 mlx5_ib_dbg(dev, "invalid max_rd_atomic value %d\n",
2887 attr->max_rd_atomic);
2888 goto out;
2889 }
2890
2891 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2892 attr->max_dest_rd_atomic >
2893 (1 << MLX5_CAP_GEN(dev->mdev, log_max_ra_req_qp))) {
2894 mlx5_ib_dbg(dev, "invalid max_dest_rd_atomic value %d\n",
2895 attr->max_dest_rd_atomic);
2896 goto out;
2897 }
2898
2899 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2900 err = 0;
2901 goto out;
2902 }
2903
2904 err = __mlx5_ib_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
2905
2906 out:
2907 mutex_unlock(&qp->mutex);
2908 return err;
2909 }
2910
2911 static int mlx5_wq_overflow(struct mlx5_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
2912 {
2913 struct mlx5_ib_cq *cq;
2914 unsigned cur;
2915
2916 cur = wq->head - wq->tail;
2917 if (likely(cur + nreq < wq->max_post))
2918 return 0;
2919
2920 cq = to_mcq(ib_cq);
2921 spin_lock(&cq->lock);
2922 cur = wq->head - wq->tail;
2923 spin_unlock(&cq->lock);
2924
2925 return cur + nreq >= wq->max_post;
2926 }
2927
2928 static __always_inline void set_raddr_seg(struct mlx5_wqe_raddr_seg *rseg,
2929 u64 remote_addr, u32 rkey)
2930 {
2931 rseg->raddr = cpu_to_be64(remote_addr);
2932 rseg->rkey = cpu_to_be32(rkey);
2933 rseg->reserved = 0;
2934 }
2935
2936 static void *set_eth_seg(struct mlx5_wqe_eth_seg *eseg,
2937 struct ib_send_wr *wr, void *qend,
2938 struct mlx5_ib_qp *qp, int *size)
2939 {
2940 void *seg = eseg;
2941
2942 memset(eseg, 0, sizeof(struct mlx5_wqe_eth_seg));
2943
2944 if (wr->send_flags & IB_SEND_IP_CSUM)
2945 eseg->cs_flags = MLX5_ETH_WQE_L3_CSUM |
2946 MLX5_ETH_WQE_L4_CSUM;
2947
2948 seg += sizeof(struct mlx5_wqe_eth_seg);
2949 *size += sizeof(struct mlx5_wqe_eth_seg) / 16;
2950
2951 if (wr->opcode == IB_WR_LSO) {
2952 struct ib_ud_wr *ud_wr = container_of(wr, struct ib_ud_wr, wr);
2953 int size_of_inl_hdr_start = sizeof(eseg->inline_hdr_start);
2954 u64 left, leftlen, copysz;
2955 void *pdata = ud_wr->header;
2956
2957 left = ud_wr->hlen;
2958 eseg->mss = cpu_to_be16(ud_wr->mss);
2959 eseg->inline_hdr_sz = cpu_to_be16(left);
2960
2961 /*
2962 * check if there is space till the end of queue, if yes,
2963 * copy all in one shot, otherwise copy till the end of queue,
2964 * rollback and than the copy the left
2965 */
2966 leftlen = qend - (void *)eseg->inline_hdr_start;
2967 copysz = min_t(u64, leftlen, left);
2968
2969 memcpy(seg - size_of_inl_hdr_start, pdata, copysz);
2970
2971 if (likely(copysz > size_of_inl_hdr_start)) {
2972 seg += ALIGN(copysz - size_of_inl_hdr_start, 16);
2973 *size += ALIGN(copysz - size_of_inl_hdr_start, 16) / 16;
2974 }
2975
2976 if (unlikely(copysz < left)) { /* the last wqe in the queue */
2977 seg = mlx5_get_send_wqe(qp, 0);
2978 left -= copysz;
2979 pdata += copysz;
2980 memcpy(seg, pdata, left);
2981 seg += ALIGN(left, 16);
2982 *size += ALIGN(left, 16) / 16;
2983 }
2984 }
2985
2986 return seg;
2987 }
2988
2989 static void set_datagram_seg(struct mlx5_wqe_datagram_seg *dseg,
2990 struct ib_send_wr *wr)
2991 {
2992 memcpy(&dseg->av, &to_mah(ud_wr(wr)->ah)->av, sizeof(struct mlx5_av));
2993 dseg->av.dqp_dct = cpu_to_be32(ud_wr(wr)->remote_qpn | MLX5_EXTENDED_UD_AV);
2994 dseg->av.key.qkey.qkey = cpu_to_be32(ud_wr(wr)->remote_qkey);
2995 }
2996
2997 static void set_data_ptr_seg(struct mlx5_wqe_data_seg *dseg, struct ib_sge *sg)
2998 {
2999 dseg->byte_count = cpu_to_be32(sg->length);
3000 dseg->lkey = cpu_to_be32(sg->lkey);
3001 dseg->addr = cpu_to_be64(sg->addr);
3002 }
3003
3004 static __be16 get_klm_octo(int npages)
3005 {
3006 return cpu_to_be16(ALIGN(npages, 8) / 2);
3007 }
3008
3009 static __be64 frwr_mkey_mask(void)
3010 {
3011 u64 result;
3012
3013 result = MLX5_MKEY_MASK_LEN |
3014 MLX5_MKEY_MASK_PAGE_SIZE |
3015 MLX5_MKEY_MASK_START_ADDR |
3016 MLX5_MKEY_MASK_EN_RINVAL |
3017 MLX5_MKEY_MASK_KEY |
3018 MLX5_MKEY_MASK_LR |
3019 MLX5_MKEY_MASK_LW |
3020 MLX5_MKEY_MASK_RR |
3021 MLX5_MKEY_MASK_RW |
3022 MLX5_MKEY_MASK_A |
3023 MLX5_MKEY_MASK_SMALL_FENCE |
3024 MLX5_MKEY_MASK_FREE;
3025
3026 return cpu_to_be64(result);
3027 }
3028
3029 static __be64 sig_mkey_mask(void)
3030 {
3031 u64 result;
3032
3033 result = MLX5_MKEY_MASK_LEN |
3034 MLX5_MKEY_MASK_PAGE_SIZE |
3035 MLX5_MKEY_MASK_START_ADDR |
3036 MLX5_MKEY_MASK_EN_SIGERR |
3037 MLX5_MKEY_MASK_EN_RINVAL |
3038 MLX5_MKEY_MASK_KEY |
3039 MLX5_MKEY_MASK_LR |
3040 MLX5_MKEY_MASK_LW |
3041 MLX5_MKEY_MASK_RR |
3042 MLX5_MKEY_MASK_RW |
3043 MLX5_MKEY_MASK_SMALL_FENCE |
3044 MLX5_MKEY_MASK_FREE |
3045 MLX5_MKEY_MASK_BSF_EN;
3046
3047 return cpu_to_be64(result);
3048 }
3049
3050 static void set_reg_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr,
3051 struct mlx5_ib_mr *mr)
3052 {
3053 int ndescs = mr->ndescs;
3054
3055 memset(umr, 0, sizeof(*umr));
3056
3057 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3058 /* KLMs take twice the size of MTTs */
3059 ndescs *= 2;
3060
3061 umr->flags = MLX5_UMR_CHECK_NOT_FREE;
3062 umr->klm_octowords = get_klm_octo(ndescs);
3063 umr->mkey_mask = frwr_mkey_mask();
3064 }
3065
3066 static void set_linv_umr_seg(struct mlx5_wqe_umr_ctrl_seg *umr)
3067 {
3068 memset(umr, 0, sizeof(*umr));
3069 umr->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
3070 umr->flags = 1 << 7;
3071 }
3072
3073 static __be64 get_umr_reg_mr_mask(void)
3074 {
3075 u64 result;
3076
3077 result = MLX5_MKEY_MASK_LEN |
3078 MLX5_MKEY_MASK_PAGE_SIZE |
3079 MLX5_MKEY_MASK_START_ADDR |
3080 MLX5_MKEY_MASK_PD |
3081 MLX5_MKEY_MASK_LR |
3082 MLX5_MKEY_MASK_LW |
3083 MLX5_MKEY_MASK_KEY |
3084 MLX5_MKEY_MASK_RR |
3085 MLX5_MKEY_MASK_RW |
3086 MLX5_MKEY_MASK_A |
3087 MLX5_MKEY_MASK_FREE;
3088
3089 return cpu_to_be64(result);
3090 }
3091
3092 static __be64 get_umr_unreg_mr_mask(void)
3093 {
3094 u64 result;
3095
3096 result = MLX5_MKEY_MASK_FREE;
3097
3098 return cpu_to_be64(result);
3099 }
3100
3101 static __be64 get_umr_update_mtt_mask(void)
3102 {
3103 u64 result;
3104
3105 result = MLX5_MKEY_MASK_FREE;
3106
3107 return cpu_to_be64(result);
3108 }
3109
3110 static __be64 get_umr_update_translation_mask(void)
3111 {
3112 u64 result;
3113
3114 result = MLX5_MKEY_MASK_LEN |
3115 MLX5_MKEY_MASK_PAGE_SIZE |
3116 MLX5_MKEY_MASK_START_ADDR |
3117 MLX5_MKEY_MASK_KEY |
3118 MLX5_MKEY_MASK_FREE;
3119
3120 return cpu_to_be64(result);
3121 }
3122
3123 static __be64 get_umr_update_access_mask(void)
3124 {
3125 u64 result;
3126
3127 result = MLX5_MKEY_MASK_LW |
3128 MLX5_MKEY_MASK_RR |
3129 MLX5_MKEY_MASK_RW |
3130 MLX5_MKEY_MASK_A |
3131 MLX5_MKEY_MASK_KEY |
3132 MLX5_MKEY_MASK_FREE;
3133
3134 return cpu_to_be64(result);
3135 }
3136
3137 static __be64 get_umr_update_pd_mask(void)
3138 {
3139 u64 result;
3140
3141 result = MLX5_MKEY_MASK_PD |
3142 MLX5_MKEY_MASK_KEY |
3143 MLX5_MKEY_MASK_FREE;
3144
3145 return cpu_to_be64(result);
3146 }
3147
3148 static void set_reg_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3149 struct ib_send_wr *wr)
3150 {
3151 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3152
3153 memset(umr, 0, sizeof(*umr));
3154
3155 if (wr->send_flags & MLX5_IB_SEND_UMR_FAIL_IF_FREE)
3156 umr->flags = MLX5_UMR_CHECK_FREE; /* fail if free */
3157 else
3158 umr->flags = MLX5_UMR_CHECK_NOT_FREE; /* fail if not free */
3159
3160 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UNREG)) {
3161 umr->klm_octowords = get_klm_octo(umrwr->npages);
3162 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT) {
3163 umr->mkey_mask = get_umr_update_mtt_mask();
3164 umr->bsf_octowords = get_klm_octo(umrwr->target.offset);
3165 umr->flags |= MLX5_UMR_TRANSLATION_OFFSET_EN;
3166 }
3167 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_TRANSLATION)
3168 umr->mkey_mask |= get_umr_update_translation_mask();
3169 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_ACCESS)
3170 umr->mkey_mask |= get_umr_update_access_mask();
3171 if (wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_PD)
3172 umr->mkey_mask |= get_umr_update_pd_mask();
3173 if (!umr->mkey_mask)
3174 umr->mkey_mask = get_umr_reg_mr_mask();
3175 } else {
3176 umr->mkey_mask = get_umr_unreg_mr_mask();
3177 }
3178
3179 if (!wr->num_sge)
3180 umr->flags |= MLX5_UMR_INLINE;
3181 }
3182
3183 static u8 get_umr_flags(int acc)
3184 {
3185 return (acc & IB_ACCESS_REMOTE_ATOMIC ? MLX5_PERM_ATOMIC : 0) |
3186 (acc & IB_ACCESS_REMOTE_WRITE ? MLX5_PERM_REMOTE_WRITE : 0) |
3187 (acc & IB_ACCESS_REMOTE_READ ? MLX5_PERM_REMOTE_READ : 0) |
3188 (acc & IB_ACCESS_LOCAL_WRITE ? MLX5_PERM_LOCAL_WRITE : 0) |
3189 MLX5_PERM_LOCAL_READ | MLX5_PERM_UMR_EN;
3190 }
3191
3192 static void set_reg_mkey_seg(struct mlx5_mkey_seg *seg,
3193 struct mlx5_ib_mr *mr,
3194 u32 key, int access)
3195 {
3196 int ndescs = ALIGN(mr->ndescs, 8) >> 1;
3197
3198 memset(seg, 0, sizeof(*seg));
3199
3200 if (mr->access_mode == MLX5_MKC_ACCESS_MODE_MTT)
3201 seg->log2_page_size = ilog2(mr->ibmr.page_size);
3202 else if (mr->access_mode == MLX5_MKC_ACCESS_MODE_KLMS)
3203 /* KLMs take twice the size of MTTs */
3204 ndescs *= 2;
3205
3206 seg->flags = get_umr_flags(access) | mr->access_mode;
3207 seg->qpn_mkey7_0 = cpu_to_be32((key & 0xff) | 0xffffff00);
3208 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL);
3209 seg->start_addr = cpu_to_be64(mr->ibmr.iova);
3210 seg->len = cpu_to_be64(mr->ibmr.length);
3211 seg->xlt_oct_size = cpu_to_be32(ndescs);
3212 }
3213
3214 static void set_linv_mkey_seg(struct mlx5_mkey_seg *seg)
3215 {
3216 memset(seg, 0, sizeof(*seg));
3217 seg->status = MLX5_MKEY_STATUS_FREE;
3218 }
3219
3220 static void set_reg_mkey_segment(struct mlx5_mkey_seg *seg, struct ib_send_wr *wr)
3221 {
3222 struct mlx5_umr_wr *umrwr = umr_wr(wr);
3223
3224 memset(seg, 0, sizeof(*seg));
3225 if (wr->send_flags & MLX5_IB_SEND_UMR_UNREG) {
3226 seg->status = MLX5_MKEY_STATUS_FREE;
3227 return;
3228 }
3229
3230 seg->flags = convert_access(umrwr->access_flags);
3231 if (!(wr->send_flags & MLX5_IB_SEND_UMR_UPDATE_MTT)) {
3232 if (umrwr->pd)
3233 seg->flags_pd = cpu_to_be32(to_mpd(umrwr->pd)->pdn);
3234 seg->start_addr = cpu_to_be64(umrwr->target.virt_addr);
3235 }
3236 seg->len = cpu_to_be64(umrwr->length);
3237 seg->log2_page_size = umrwr->page_shift;
3238 seg->qpn_mkey7_0 = cpu_to_be32(0xffffff00 |
3239 mlx5_mkey_variant(umrwr->mkey));
3240 }
3241
3242 static void set_reg_data_seg(struct mlx5_wqe_data_seg *dseg,
3243 struct mlx5_ib_mr *mr,
3244 struct mlx5_ib_pd *pd)
3245 {
3246 int bcount = mr->desc_size * mr->ndescs;
3247
3248 dseg->addr = cpu_to_be64(mr->desc_map);
3249 dseg->byte_count = cpu_to_be32(ALIGN(bcount, 64));
3250 dseg->lkey = cpu_to_be32(pd->ibpd.local_dma_lkey);
3251 }
3252
3253 static __be32 send_ieth(struct ib_send_wr *wr)
3254 {
3255 switch (wr->opcode) {
3256 case IB_WR_SEND_WITH_IMM:
3257 case IB_WR_RDMA_WRITE_WITH_IMM:
3258 return wr->ex.imm_data;
3259
3260 case IB_WR_SEND_WITH_INV:
3261 return cpu_to_be32(wr->ex.invalidate_rkey);
3262
3263 default:
3264 return 0;
3265 }
3266 }
3267
3268 static u8 calc_sig(void *wqe, int size)
3269 {
3270 u8 *p = wqe;
3271 u8 res = 0;
3272 int i;
3273
3274 for (i = 0; i < size; i++)
3275 res ^= p[i];
3276
3277 return ~res;
3278 }
3279
3280 static u8 wq_sig(void *wqe)
3281 {
3282 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4);
3283 }
3284
3285 static int set_data_inl_seg(struct mlx5_ib_qp *qp, struct ib_send_wr *wr,
3286 void *wqe, int *sz)
3287 {
3288 struct mlx5_wqe_inline_seg *seg;
3289 void *qend = qp->sq.qend;
3290 void *addr;
3291 int inl = 0;
3292 int copy;
3293 int len;
3294 int i;
3295
3296 seg = wqe;
3297 wqe += sizeof(*seg);
3298 for (i = 0; i < wr->num_sge; i++) {
3299 addr = (void *)(unsigned long)(wr->sg_list[i].addr);
3300 len = wr->sg_list[i].length;
3301 inl += len;
3302
3303 if (unlikely(inl > qp->max_inline_data))
3304 return -ENOMEM;
3305
3306 if (unlikely(wqe + len > qend)) {
3307 copy = qend - wqe;
3308 memcpy(wqe, addr, copy);
3309 addr += copy;
3310 len -= copy;
3311 wqe = mlx5_get_send_wqe(qp, 0);
3312 }
3313 memcpy(wqe, addr, len);
3314 wqe += len;
3315 }
3316
3317 seg->byte_count = cpu_to_be32(inl | MLX5_INLINE_SEG);
3318
3319 *sz = ALIGN(inl + sizeof(seg->byte_count), 16) / 16;
3320
3321 return 0;
3322 }
3323
3324 static u16 prot_field_size(enum ib_signature_type type)
3325 {
3326 switch (type) {
3327 case IB_SIG_TYPE_T10_DIF:
3328 return MLX5_DIF_SIZE;
3329 default:
3330 return 0;
3331 }
3332 }
3333
3334 static u8 bs_selector(int block_size)
3335 {
3336 switch (block_size) {
3337 case 512: return 0x1;
3338 case 520: return 0x2;
3339 case 4096: return 0x3;
3340 case 4160: return 0x4;
3341 case 1073741824: return 0x5;
3342 default: return 0;
3343 }
3344 }
3345
3346 static void mlx5_fill_inl_bsf(struct ib_sig_domain *domain,
3347 struct mlx5_bsf_inl *inl)
3348 {
3349 /* Valid inline section and allow BSF refresh */
3350 inl->vld_refresh = cpu_to_be16(MLX5_BSF_INL_VALID |
3351 MLX5_BSF_REFRESH_DIF);
3352 inl->dif_apptag = cpu_to_be16(domain->sig.dif.app_tag);
3353 inl->dif_reftag = cpu_to_be32(domain->sig.dif.ref_tag);
3354 /* repeating block */
3355 inl->rp_inv_seed = MLX5_BSF_REPEAT_BLOCK;
3356 inl->sig_type = domain->sig.dif.bg_type == IB_T10DIF_CRC ?
3357 MLX5_DIF_CRC : MLX5_DIF_IPCS;
3358
3359 if (domain->sig.dif.ref_remap)
3360 inl->dif_inc_ref_guard_check |= MLX5_BSF_INC_REFTAG;
3361
3362 if (domain->sig.dif.app_escape) {
3363 if (domain->sig.dif.ref_escape)
3364 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPREF_ESCAPE;
3365 else
3366 inl->dif_inc_ref_guard_check |= MLX5_BSF_APPTAG_ESCAPE;
3367 }
3368
3369 inl->dif_app_bitmask_check =
3370 cpu_to_be16(domain->sig.dif.apptag_check_mask);
3371 }
3372
3373 static int mlx5_set_bsf(struct ib_mr *sig_mr,
3374 struct ib_sig_attrs *sig_attrs,
3375 struct mlx5_bsf *bsf, u32 data_size)
3376 {
3377 struct mlx5_core_sig_ctx *msig = to_mmr(sig_mr)->sig;
3378 struct mlx5_bsf_basic *basic = &bsf->basic;
3379 struct ib_sig_domain *mem = &sig_attrs->mem;
3380 struct ib_sig_domain *wire = &sig_attrs->wire;
3381
3382 memset(bsf, 0, sizeof(*bsf));
3383
3384 /* Basic + Extended + Inline */
3385 basic->bsf_size_sbs = 1 << 7;
3386 /* Input domain check byte mask */
3387 basic->check_byte_mask = sig_attrs->check_mask;
3388 basic->raw_data_size = cpu_to_be32(data_size);
3389
3390 /* Memory domain */
3391 switch (sig_attrs->mem.sig_type) {
3392 case IB_SIG_TYPE_NONE:
3393 break;
3394 case IB_SIG_TYPE_T10_DIF:
3395 basic->mem.bs_selector = bs_selector(mem->sig.dif.pi_interval);
3396 basic->m_bfs_psv = cpu_to_be32(msig->psv_memory.psv_idx);
3397 mlx5_fill_inl_bsf(mem, &bsf->m_inl);
3398 break;
3399 default:
3400 return -EINVAL;
3401 }
3402
3403 /* Wire domain */
3404 switch (sig_attrs->wire.sig_type) {
3405 case IB_SIG_TYPE_NONE:
3406 break;
3407 case IB_SIG_TYPE_T10_DIF:
3408 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval &&
3409 mem->sig_type == wire->sig_type) {
3410 /* Same block structure */
3411 basic->bsf_size_sbs |= 1 << 4;
3412 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type)
3413 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK;
3414 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag)
3415 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK;
3416 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag)
3417 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK;
3418 } else
3419 basic->wire.bs_selector = bs_selector(wire->sig.dif.pi_interval);
3420
3421 basic->w_bfs_psv = cpu_to_be32(msig->psv_wire.psv_idx);
3422 mlx5_fill_inl_bsf(wire, &bsf->w_inl);
3423 break;
3424 default:
3425 return -EINVAL;
3426 }
3427
3428 return 0;
3429 }
3430
3431 static int set_sig_data_segment(struct ib_sig_handover_wr *wr,
3432 struct mlx5_ib_qp *qp, void **seg, int *size)
3433 {
3434 struct ib_sig_attrs *sig_attrs = wr->sig_attrs;
3435 struct ib_mr *sig_mr = wr->sig_mr;
3436 struct mlx5_bsf *bsf;
3437 u32 data_len = wr->wr.sg_list->length;
3438 u32 data_key = wr->wr.sg_list->lkey;
3439 u64 data_va = wr->wr.sg_list->addr;
3440 int ret;
3441 int wqe_size;
3442
3443 if (!wr->prot ||
3444 (data_key == wr->prot->lkey &&
3445 data_va == wr->prot->addr &&
3446 data_len == wr->prot->length)) {
3447 /**
3448 * Source domain doesn't contain signature information
3449 * or data and protection are interleaved in memory.
3450 * So need construct:
3451 * ------------------
3452 * | data_klm |
3453 * ------------------
3454 * | BSF |
3455 * ------------------
3456 **/
3457 struct mlx5_klm *data_klm = *seg;
3458
3459 data_klm->bcount = cpu_to_be32(data_len);
3460 data_klm->key = cpu_to_be32(data_key);
3461 data_klm->va = cpu_to_be64(data_va);
3462 wqe_size = ALIGN(sizeof(*data_klm), 64);
3463 } else {
3464 /**
3465 * Source domain contains signature information
3466 * So need construct a strided block format:
3467 * ---------------------------
3468 * | stride_block_ctrl |
3469 * ---------------------------
3470 * | data_klm |
3471 * ---------------------------
3472 * | prot_klm |
3473 * ---------------------------
3474 * | BSF |
3475 * ---------------------------
3476 **/
3477 struct mlx5_stride_block_ctrl_seg *sblock_ctrl;
3478 struct mlx5_stride_block_entry *data_sentry;
3479 struct mlx5_stride_block_entry *prot_sentry;
3480 u32 prot_key = wr->prot->lkey;
3481 u64 prot_va = wr->prot->addr;
3482 u16 block_size = sig_attrs->mem.sig.dif.pi_interval;
3483 int prot_size;
3484
3485 sblock_ctrl = *seg;
3486 data_sentry = (void *)sblock_ctrl + sizeof(*sblock_ctrl);
3487 prot_sentry = (void *)data_sentry + sizeof(*data_sentry);
3488
3489 prot_size = prot_field_size(sig_attrs->mem.sig_type);
3490 if (!prot_size) {
3491 pr_err("Bad block size given: %u\n", block_size);
3492 return -EINVAL;
3493 }
3494 sblock_ctrl->bcount_per_cycle = cpu_to_be32(block_size +
3495 prot_size);
3496 sblock_ctrl->op = cpu_to_be32(MLX5_STRIDE_BLOCK_OP);
3497 sblock_ctrl->repeat_count = cpu_to_be32(data_len / block_size);
3498 sblock_ctrl->num_entries = cpu_to_be16(2);
3499
3500 data_sentry->bcount = cpu_to_be16(block_size);
3501 data_sentry->key = cpu_to_be32(data_key);
3502 data_sentry->va = cpu_to_be64(data_va);
3503 data_sentry->stride = cpu_to_be16(block_size);
3504
3505 prot_sentry->bcount = cpu_to_be16(prot_size);
3506 prot_sentry->key = cpu_to_be32(prot_key);
3507 prot_sentry->va = cpu_to_be64(prot_va);
3508 prot_sentry->stride = cpu_to_be16(prot_size);
3509
3510 wqe_size = ALIGN(sizeof(*sblock_ctrl) + sizeof(*data_sentry) +
3511 sizeof(*prot_sentry), 64);
3512 }
3513
3514 *seg += wqe_size;
3515 *size += wqe_size / 16;
3516 if (unlikely((*seg == qp->sq.qend)))
3517 *seg = mlx5_get_send_wqe(qp, 0);
3518
3519 bsf = *seg;
3520 ret = mlx5_set_bsf(sig_mr, sig_attrs, bsf, data_len);
3521 if (ret)
3522 return -EINVAL;
3523
3524 *seg += sizeof(*bsf);
3525 *size += sizeof(*bsf) / 16;
3526 if (unlikely((*seg == qp->sq.qend)))
3527 *seg = mlx5_get_send_wqe(qp, 0);
3528
3529 return 0;
3530 }
3531
3532 static void set_sig_mkey_segment(struct mlx5_mkey_seg *seg,
3533 struct ib_sig_handover_wr *wr, u32 nelements,
3534 u32 length, u32 pdn)
3535 {
3536 struct ib_mr *sig_mr = wr->sig_mr;
3537 u32 sig_key = sig_mr->rkey;
3538 u8 sigerr = to_mmr(sig_mr)->sig->sigerr_count & 1;
3539
3540 memset(seg, 0, sizeof(*seg));
3541
3542 seg->flags = get_umr_flags(wr->access_flags) |
3543 MLX5_MKC_ACCESS_MODE_KLMS;
3544 seg->qpn_mkey7_0 = cpu_to_be32((sig_key & 0xff) | 0xffffff00);
3545 seg->flags_pd = cpu_to_be32(MLX5_MKEY_REMOTE_INVAL | sigerr << 26 |
3546 MLX5_MKEY_BSF_EN | pdn);
3547 seg->len = cpu_to_be64(length);
3548 seg->xlt_oct_size = cpu_to_be32(be16_to_cpu(get_klm_octo(nelements)));
3549 seg->bsfs_octo_size = cpu_to_be32(MLX5_MKEY_BSF_OCTO_SIZE);
3550 }
3551
3552 static void set_sig_umr_segment(struct mlx5_wqe_umr_ctrl_seg *umr,
3553 u32 nelements)
3554 {
3555 memset(umr, 0, sizeof(*umr));
3556
3557 umr->flags = MLX5_FLAGS_INLINE | MLX5_FLAGS_CHECK_FREE;
3558 umr->klm_octowords = get_klm_octo(nelements);
3559 umr->bsf_octowords = cpu_to_be16(MLX5_MKEY_BSF_OCTO_SIZE);
3560 umr->mkey_mask = sig_mkey_mask();
3561 }
3562
3563
3564 static int set_sig_umr_wr(struct ib_send_wr *send_wr, struct mlx5_ib_qp *qp,
3565 void **seg, int *size)
3566 {
3567 struct ib_sig_handover_wr *wr = sig_handover_wr(send_wr);
3568 struct mlx5_ib_mr *sig_mr = to_mmr(wr->sig_mr);
3569 u32 pdn = get_pd(qp)->pdn;
3570 u32 klm_oct_size;
3571 int region_len, ret;
3572
3573 if (unlikely(wr->wr.num_sge != 1) ||
3574 unlikely(wr->access_flags & IB_ACCESS_REMOTE_ATOMIC) ||
3575 unlikely(!sig_mr->sig) || unlikely(!qp->signature_en) ||
3576 unlikely(!sig_mr->sig->sig_status_checked))
3577 return -EINVAL;
3578
3579 /* length of the protected region, data + protection */
3580 region_len = wr->wr.sg_list->length;
3581 if (wr->prot &&
3582 (wr->prot->lkey != wr->wr.sg_list->lkey ||
3583 wr->prot->addr != wr->wr.sg_list->addr ||
3584 wr->prot->length != wr->wr.sg_list->length))
3585 region_len += wr->prot->length;
3586
3587 /**
3588 * KLM octoword size - if protection was provided
3589 * then we use strided block format (3 octowords),
3590 * else we use single KLM (1 octoword)
3591 **/
3592 klm_oct_size = wr->prot ? 3 : 1;
3593
3594 set_sig_umr_segment(*seg, klm_oct_size);
3595 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3596 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3597 if (unlikely((*seg == qp->sq.qend)))
3598 *seg = mlx5_get_send_wqe(qp, 0);
3599
3600 set_sig_mkey_segment(*seg, wr, klm_oct_size, region_len, pdn);
3601 *seg += sizeof(struct mlx5_mkey_seg);
3602 *size += sizeof(struct mlx5_mkey_seg) / 16;
3603 if (unlikely((*seg == qp->sq.qend)))
3604 *seg = mlx5_get_send_wqe(qp, 0);
3605
3606 ret = set_sig_data_segment(wr, qp, seg, size);
3607 if (ret)
3608 return ret;
3609
3610 sig_mr->sig->sig_status_checked = false;
3611 return 0;
3612 }
3613
3614 static int set_psv_wr(struct ib_sig_domain *domain,
3615 u32 psv_idx, void **seg, int *size)
3616 {
3617 struct mlx5_seg_set_psv *psv_seg = *seg;
3618
3619 memset(psv_seg, 0, sizeof(*psv_seg));
3620 psv_seg->psv_num = cpu_to_be32(psv_idx);
3621 switch (domain->sig_type) {
3622 case IB_SIG_TYPE_NONE:
3623 break;
3624 case IB_SIG_TYPE_T10_DIF:
3625 psv_seg->transient_sig = cpu_to_be32(domain->sig.dif.bg << 16 |
3626 domain->sig.dif.app_tag);
3627 psv_seg->ref_tag = cpu_to_be32(domain->sig.dif.ref_tag);
3628 break;
3629 default:
3630 pr_err("Bad signature type given.\n");
3631 return 1;
3632 }
3633
3634 *seg += sizeof(*psv_seg);
3635 *size += sizeof(*psv_seg) / 16;
3636
3637 return 0;
3638 }
3639
3640 static int set_reg_wr(struct mlx5_ib_qp *qp,
3641 struct ib_reg_wr *wr,
3642 void **seg, int *size)
3643 {
3644 struct mlx5_ib_mr *mr = to_mmr(wr->mr);
3645 struct mlx5_ib_pd *pd = to_mpd(qp->ibqp.pd);
3646
3647 if (unlikely(wr->wr.send_flags & IB_SEND_INLINE)) {
3648 mlx5_ib_warn(to_mdev(qp->ibqp.device),
3649 "Invalid IB_SEND_INLINE send flag\n");
3650 return -EINVAL;
3651 }
3652
3653 set_reg_umr_seg(*seg, mr);
3654 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3655 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3656 if (unlikely((*seg == qp->sq.qend)))
3657 *seg = mlx5_get_send_wqe(qp, 0);
3658
3659 set_reg_mkey_seg(*seg, mr, wr->key, wr->access);
3660 *seg += sizeof(struct mlx5_mkey_seg);
3661 *size += sizeof(struct mlx5_mkey_seg) / 16;
3662 if (unlikely((*seg == qp->sq.qend)))
3663 *seg = mlx5_get_send_wqe(qp, 0);
3664
3665 set_reg_data_seg(*seg, mr, pd);
3666 *seg += sizeof(struct mlx5_wqe_data_seg);
3667 *size += (sizeof(struct mlx5_wqe_data_seg) / 16);
3668
3669 return 0;
3670 }
3671
3672 static void set_linv_wr(struct mlx5_ib_qp *qp, void **seg, int *size)
3673 {
3674 set_linv_umr_seg(*seg);
3675 *seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
3676 *size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
3677 if (unlikely((*seg == qp->sq.qend)))
3678 *seg = mlx5_get_send_wqe(qp, 0);
3679 set_linv_mkey_seg(*seg);
3680 *seg += sizeof(struct mlx5_mkey_seg);
3681 *size += sizeof(struct mlx5_mkey_seg) / 16;
3682 if (unlikely((*seg == qp->sq.qend)))
3683 *seg = mlx5_get_send_wqe(qp, 0);
3684 }
3685
3686 static void dump_wqe(struct mlx5_ib_qp *qp, int idx, int size_16)
3687 {
3688 __be32 *p = NULL;
3689 int tidx = idx;
3690 int i, j;
3691
3692 pr_debug("dump wqe at %p\n", mlx5_get_send_wqe(qp, tidx));
3693 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) {
3694 if ((i & 0xf) == 0) {
3695 void *buf = mlx5_get_send_wqe(qp, tidx);
3696 tidx = (tidx + 1) & (qp->sq.wqe_cnt - 1);
3697 p = buf;
3698 j = 0;
3699 }
3700 pr_debug("%08x %08x %08x %08x\n", be32_to_cpu(p[j]),
3701 be32_to_cpu(p[j + 1]), be32_to_cpu(p[j + 2]),
3702 be32_to_cpu(p[j + 3]));
3703 }
3704 }
3705
3706 static void mlx5_bf_copy(u64 __iomem *dst, u64 *src,
3707 unsigned bytecnt, struct mlx5_ib_qp *qp)
3708 {
3709 while (bytecnt > 0) {
3710 __iowrite64_copy(dst++, src++, 8);
3711 __iowrite64_copy(dst++, src++, 8);
3712 __iowrite64_copy(dst++, src++, 8);
3713 __iowrite64_copy(dst++, src++, 8);
3714 __iowrite64_copy(dst++, src++, 8);
3715 __iowrite64_copy(dst++, src++, 8);
3716 __iowrite64_copy(dst++, src++, 8);
3717 __iowrite64_copy(dst++, src++, 8);
3718 bytecnt -= 64;
3719 if (unlikely(src == qp->sq.qend))
3720 src = mlx5_get_send_wqe(qp, 0);
3721 }
3722 }
3723
3724 static u8 get_fence(u8 fence, struct ib_send_wr *wr)
3725 {
3726 if (unlikely(wr->opcode == IB_WR_LOCAL_INV &&
3727 wr->send_flags & IB_SEND_FENCE))
3728 return MLX5_FENCE_MODE_STRONG_ORDERING;
3729
3730 if (unlikely(fence)) {
3731 if (wr->send_flags & IB_SEND_FENCE)
3732 return MLX5_FENCE_MODE_SMALL_AND_FENCE;
3733 else
3734 return fence;
3735 } else if (unlikely(wr->send_flags & IB_SEND_FENCE)) {
3736 return MLX5_FENCE_MODE_FENCE;
3737 }
3738
3739 return 0;
3740 }
3741
3742 static int begin_wqe(struct mlx5_ib_qp *qp, void **seg,
3743 struct mlx5_wqe_ctrl_seg **ctrl,
3744 struct ib_send_wr *wr, unsigned *idx,
3745 int *size, int nreq)
3746 {
3747 if (unlikely(mlx5_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)))
3748 return -ENOMEM;
3749
3750 *idx = qp->sq.cur_post & (qp->sq.wqe_cnt - 1);
3751 *seg = mlx5_get_send_wqe(qp, *idx);
3752 *ctrl = *seg;
3753 *(uint32_t *)(*seg + 8) = 0;
3754 (*ctrl)->imm = send_ieth(wr);
3755 (*ctrl)->fm_ce_se = qp->sq_signal_bits |
3756 (wr->send_flags & IB_SEND_SIGNALED ?
3757 MLX5_WQE_CTRL_CQ_UPDATE : 0) |
3758 (wr->send_flags & IB_SEND_SOLICITED ?
3759 MLX5_WQE_CTRL_SOLICITED : 0);
3760
3761 *seg += sizeof(**ctrl);
3762 *size = sizeof(**ctrl) / 16;
3763
3764 return 0;
3765 }
3766
3767 static void finish_wqe(struct mlx5_ib_qp *qp,
3768 struct mlx5_wqe_ctrl_seg *ctrl,
3769 u8 size, unsigned idx, u64 wr_id,
3770 int nreq, u8 fence, u8 next_fence,
3771 u32 mlx5_opcode)
3772 {
3773 u8 opmod = 0;
3774
3775 ctrl->opmod_idx_opcode = cpu_to_be32(((u32)(qp->sq.cur_post) << 8) |
3776 mlx5_opcode | ((u32)opmod << 24));
3777 ctrl->qpn_ds = cpu_to_be32(size | (qp->trans_qp.base.mqp.qpn << 8));
3778 ctrl->fm_ce_se |= fence;
3779 qp->fm_cache = next_fence;
3780 if (unlikely(qp->wq_sig))
3781 ctrl->signature = wq_sig(ctrl);
3782
3783 qp->sq.wrid[idx] = wr_id;
3784 qp->sq.w_list[idx].opcode = mlx5_opcode;
3785 qp->sq.wqe_head[idx] = qp->sq.head + nreq;
3786 qp->sq.cur_post += DIV_ROUND_UP(size * 16, MLX5_SEND_WQE_BB);
3787 qp->sq.w_list[idx].next = qp->sq.cur_post;
3788 }
3789
3790
3791 int mlx5_ib_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
3792 struct ib_send_wr **bad_wr)
3793 {
3794 struct mlx5_wqe_ctrl_seg *ctrl = NULL; /* compiler warning */
3795 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
3796 struct mlx5_core_dev *mdev = dev->mdev;
3797 struct mlx5_ib_qp *qp;
3798 struct mlx5_ib_mr *mr;
3799 struct mlx5_wqe_data_seg *dpseg;
3800 struct mlx5_wqe_xrc_seg *xrc;
3801 struct mlx5_bf *bf;
3802 int uninitialized_var(size);
3803 void *qend;
3804 unsigned long flags;
3805 unsigned idx;
3806 int err = 0;
3807 int inl = 0;
3808 int num_sge;
3809 void *seg;
3810 int nreq;
3811 int i;
3812 u8 next_fence = 0;
3813 u8 fence;
3814
3815 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
3816 return mlx5_ib_gsi_post_send(ibqp, wr, bad_wr);
3817
3818 qp = to_mqp(ibqp);
3819 bf = qp->bf;
3820 qend = qp->sq.qend;
3821
3822 spin_lock_irqsave(&qp->sq.lock, flags);
3823
3824 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
3825 err = -EIO;
3826 *bad_wr = wr;
3827 nreq = 0;
3828 goto out;
3829 }
3830
3831 for (nreq = 0; wr; nreq++, wr = wr->next) {
3832 if (unlikely(wr->opcode >= ARRAY_SIZE(mlx5_ib_opcode))) {
3833 mlx5_ib_warn(dev, "\n");
3834 err = -EINVAL;
3835 *bad_wr = wr;
3836 goto out;
3837 }
3838
3839 fence = qp->fm_cache;
3840 num_sge = wr->num_sge;
3841 if (unlikely(num_sge > qp->sq.max_gs)) {
3842 mlx5_ib_warn(dev, "\n");
3843 err = -EINVAL;
3844 *bad_wr = wr;
3845 goto out;
3846 }
3847
3848 err = begin_wqe(qp, &seg, &ctrl, wr, &idx, &size, nreq);
3849 if (err) {
3850 mlx5_ib_warn(dev, "\n");
3851 err = -ENOMEM;
3852 *bad_wr = wr;
3853 goto out;
3854 }
3855
3856 switch (ibqp->qp_type) {
3857 case IB_QPT_XRC_INI:
3858 xrc = seg;
3859 seg += sizeof(*xrc);
3860 size += sizeof(*xrc) / 16;
3861 /* fall through */
3862 case IB_QPT_RC:
3863 switch (wr->opcode) {
3864 case IB_WR_RDMA_READ:
3865 case IB_WR_RDMA_WRITE:
3866 case IB_WR_RDMA_WRITE_WITH_IMM:
3867 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3868 rdma_wr(wr)->rkey);
3869 seg += sizeof(struct mlx5_wqe_raddr_seg);
3870 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3871 break;
3872
3873 case IB_WR_ATOMIC_CMP_AND_SWP:
3874 case IB_WR_ATOMIC_FETCH_AND_ADD:
3875 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3876 mlx5_ib_warn(dev, "Atomic operations are not supported yet\n");
3877 err = -ENOSYS;
3878 *bad_wr = wr;
3879 goto out;
3880
3881 case IB_WR_LOCAL_INV:
3882 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3883 qp->sq.wr_data[idx] = IB_WR_LOCAL_INV;
3884 ctrl->imm = cpu_to_be32(wr->ex.invalidate_rkey);
3885 set_linv_wr(qp, &seg, &size);
3886 num_sge = 0;
3887 break;
3888
3889 case IB_WR_REG_MR:
3890 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3891 qp->sq.wr_data[idx] = IB_WR_REG_MR;
3892 ctrl->imm = cpu_to_be32(reg_wr(wr)->key);
3893 err = set_reg_wr(qp, reg_wr(wr), &seg, &size);
3894 if (err) {
3895 *bad_wr = wr;
3896 goto out;
3897 }
3898 num_sge = 0;
3899 break;
3900
3901 case IB_WR_REG_SIG_MR:
3902 qp->sq.wr_data[idx] = IB_WR_REG_SIG_MR;
3903 mr = to_mmr(sig_handover_wr(wr)->sig_mr);
3904
3905 ctrl->imm = cpu_to_be32(mr->ibmr.rkey);
3906 err = set_sig_umr_wr(wr, qp, &seg, &size);
3907 if (err) {
3908 mlx5_ib_warn(dev, "\n");
3909 *bad_wr = wr;
3910 goto out;
3911 }
3912
3913 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3914 nreq, get_fence(fence, wr),
3915 next_fence, MLX5_OPCODE_UMR);
3916 /*
3917 * SET_PSV WQEs are not signaled and solicited
3918 * on error
3919 */
3920 wr->send_flags &= ~IB_SEND_SIGNALED;
3921 wr->send_flags |= IB_SEND_SOLICITED;
3922 err = begin_wqe(qp, &seg, &ctrl, wr,
3923 &idx, &size, nreq);
3924 if (err) {
3925 mlx5_ib_warn(dev, "\n");
3926 err = -ENOMEM;
3927 *bad_wr = wr;
3928 goto out;
3929 }
3930
3931 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->mem,
3932 mr->sig->psv_memory.psv_idx, &seg,
3933 &size);
3934 if (err) {
3935 mlx5_ib_warn(dev, "\n");
3936 *bad_wr = wr;
3937 goto out;
3938 }
3939
3940 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3941 nreq, get_fence(fence, wr),
3942 next_fence, MLX5_OPCODE_SET_PSV);
3943 err = begin_wqe(qp, &seg, &ctrl, wr,
3944 &idx, &size, nreq);
3945 if (err) {
3946 mlx5_ib_warn(dev, "\n");
3947 err = -ENOMEM;
3948 *bad_wr = wr;
3949 goto out;
3950 }
3951
3952 next_fence = MLX5_FENCE_MODE_INITIATOR_SMALL;
3953 err = set_psv_wr(&sig_handover_wr(wr)->sig_attrs->wire,
3954 mr->sig->psv_wire.psv_idx, &seg,
3955 &size);
3956 if (err) {
3957 mlx5_ib_warn(dev, "\n");
3958 *bad_wr = wr;
3959 goto out;
3960 }
3961
3962 finish_wqe(qp, ctrl, size, idx, wr->wr_id,
3963 nreq, get_fence(fence, wr),
3964 next_fence, MLX5_OPCODE_SET_PSV);
3965 num_sge = 0;
3966 goto skip_psv;
3967
3968 default:
3969 break;
3970 }
3971 break;
3972
3973 case IB_QPT_UC:
3974 switch (wr->opcode) {
3975 case IB_WR_RDMA_WRITE:
3976 case IB_WR_RDMA_WRITE_WITH_IMM:
3977 set_raddr_seg(seg, rdma_wr(wr)->remote_addr,
3978 rdma_wr(wr)->rkey);
3979 seg += sizeof(struct mlx5_wqe_raddr_seg);
3980 size += sizeof(struct mlx5_wqe_raddr_seg) / 16;
3981 break;
3982
3983 default:
3984 break;
3985 }
3986 break;
3987
3988 case IB_QPT_SMI:
3989 case MLX5_IB_QPT_HW_GSI:
3990 set_datagram_seg(seg, wr);
3991 seg += sizeof(struct mlx5_wqe_datagram_seg);
3992 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
3993 if (unlikely((seg == qend)))
3994 seg = mlx5_get_send_wqe(qp, 0);
3995 break;
3996 case IB_QPT_UD:
3997 set_datagram_seg(seg, wr);
3998 seg += sizeof(struct mlx5_wqe_datagram_seg);
3999 size += sizeof(struct mlx5_wqe_datagram_seg) / 16;
4000
4001 if (unlikely((seg == qend)))
4002 seg = mlx5_get_send_wqe(qp, 0);
4003
4004 /* handle qp that supports ud offload */
4005 if (qp->flags & IB_QP_CREATE_IPOIB_UD_LSO) {
4006 struct mlx5_wqe_eth_pad *pad;
4007
4008 pad = seg;
4009 memset(pad, 0, sizeof(struct mlx5_wqe_eth_pad));
4010 seg += sizeof(struct mlx5_wqe_eth_pad);
4011 size += sizeof(struct mlx5_wqe_eth_pad) / 16;
4012
4013 seg = set_eth_seg(seg, wr, qend, qp, &size);
4014
4015 if (unlikely((seg == qend)))
4016 seg = mlx5_get_send_wqe(qp, 0);
4017 }
4018 break;
4019 case MLX5_IB_QPT_REG_UMR:
4020 if (wr->opcode != MLX5_IB_WR_UMR) {
4021 err = -EINVAL;
4022 mlx5_ib_warn(dev, "bad opcode\n");
4023 goto out;
4024 }
4025 qp->sq.wr_data[idx] = MLX5_IB_WR_UMR;
4026 ctrl->imm = cpu_to_be32(umr_wr(wr)->mkey);
4027 set_reg_umr_segment(seg, wr);
4028 seg += sizeof(struct mlx5_wqe_umr_ctrl_seg);
4029 size += sizeof(struct mlx5_wqe_umr_ctrl_seg) / 16;
4030 if (unlikely((seg == qend)))
4031 seg = mlx5_get_send_wqe(qp, 0);
4032 set_reg_mkey_segment(seg, wr);
4033 seg += sizeof(struct mlx5_mkey_seg);
4034 size += sizeof(struct mlx5_mkey_seg) / 16;
4035 if (unlikely((seg == qend)))
4036 seg = mlx5_get_send_wqe(qp, 0);
4037 break;
4038
4039 default:
4040 break;
4041 }
4042
4043 if (wr->send_flags & IB_SEND_INLINE && num_sge) {
4044 int uninitialized_var(sz);
4045
4046 err = set_data_inl_seg(qp, wr, seg, &sz);
4047 if (unlikely(err)) {
4048 mlx5_ib_warn(dev, "\n");
4049 *bad_wr = wr;
4050 goto out;
4051 }
4052 inl = 1;
4053 size += sz;
4054 } else {
4055 dpseg = seg;
4056 for (i = 0; i < num_sge; i++) {
4057 if (unlikely(dpseg == qend)) {
4058 seg = mlx5_get_send_wqe(qp, 0);
4059 dpseg = seg;
4060 }
4061 if (likely(wr->sg_list[i].length)) {
4062 set_data_ptr_seg(dpseg, wr->sg_list + i);
4063 size += sizeof(struct mlx5_wqe_data_seg) / 16;
4064 dpseg++;
4065 }
4066 }
4067 }
4068
4069 finish_wqe(qp, ctrl, size, idx, wr->wr_id, nreq,
4070 get_fence(fence, wr), next_fence,
4071 mlx5_ib_opcode[wr->opcode]);
4072 skip_psv:
4073 if (0)
4074 dump_wqe(qp, idx, size);
4075 }
4076
4077 out:
4078 if (likely(nreq)) {
4079 qp->sq.head += nreq;
4080
4081 /* Make sure that descriptors are written before
4082 * updating doorbell record and ringing the doorbell
4083 */
4084 wmb();
4085
4086 qp->db.db[MLX5_SND_DBR] = cpu_to_be32(qp->sq.cur_post);
4087
4088 /* Make sure doorbell record is visible to the HCA before
4089 * we hit doorbell */
4090 wmb();
4091
4092 if (bf->need_lock)
4093 spin_lock(&bf->lock);
4094 else
4095 __acquire(&bf->lock);
4096
4097 /* TBD enable WC */
4098 if (0 && nreq == 1 && bf->uuarn && inl && size > 1 && size <= bf->buf_size / 16) {
4099 mlx5_bf_copy(bf->reg + bf->offset, (u64 *)ctrl, ALIGN(size * 16, 64), qp);
4100 /* wc_wmb(); */
4101 } else {
4102 mlx5_write64((__be32 *)ctrl, bf->regreg + bf->offset,
4103 MLX5_GET_DOORBELL_LOCK(&bf->lock32));
4104 /* Make sure doorbells don't leak out of SQ spinlock
4105 * and reach the HCA out of order.
4106 */
4107 mmiowb();
4108 }
4109 bf->offset ^= bf->buf_size;
4110 if (bf->need_lock)
4111 spin_unlock(&bf->lock);
4112 else
4113 __release(&bf->lock);
4114 }
4115
4116 spin_unlock_irqrestore(&qp->sq.lock, flags);
4117
4118 return err;
4119 }
4120
4121 static void set_sig_seg(struct mlx5_rwqe_sig *sig, int size)
4122 {
4123 sig->signature = calc_sig(sig, size);
4124 }
4125
4126 int mlx5_ib_post_recv(struct ib_qp *ibqp, struct ib_recv_wr *wr,
4127 struct ib_recv_wr **bad_wr)
4128 {
4129 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4130 struct mlx5_wqe_data_seg *scat;
4131 struct mlx5_rwqe_sig *sig;
4132 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4133 struct mlx5_core_dev *mdev = dev->mdev;
4134 unsigned long flags;
4135 int err = 0;
4136 int nreq;
4137 int ind;
4138 int i;
4139
4140 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4141 return mlx5_ib_gsi_post_recv(ibqp, wr, bad_wr);
4142
4143 spin_lock_irqsave(&qp->rq.lock, flags);
4144
4145 if (mdev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
4146 err = -EIO;
4147 *bad_wr = wr;
4148 nreq = 0;
4149 goto out;
4150 }
4151
4152 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
4153
4154 for (nreq = 0; wr; nreq++, wr = wr->next) {
4155 if (mlx5_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
4156 err = -ENOMEM;
4157 *bad_wr = wr;
4158 goto out;
4159 }
4160
4161 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
4162 err = -EINVAL;
4163 *bad_wr = wr;
4164 goto out;
4165 }
4166
4167 scat = get_recv_wqe(qp, ind);
4168 if (qp->wq_sig)
4169 scat++;
4170
4171 for (i = 0; i < wr->num_sge; i++)
4172 set_data_ptr_seg(scat + i, wr->sg_list + i);
4173
4174 if (i < qp->rq.max_gs) {
4175 scat[i].byte_count = 0;
4176 scat[i].lkey = cpu_to_be32(MLX5_INVALID_LKEY);
4177 scat[i].addr = 0;
4178 }
4179
4180 if (qp->wq_sig) {
4181 sig = (struct mlx5_rwqe_sig *)scat;
4182 set_sig_seg(sig, (qp->rq.max_gs + 1) << 2);
4183 }
4184
4185 qp->rq.wrid[ind] = wr->wr_id;
4186
4187 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
4188 }
4189
4190 out:
4191 if (likely(nreq)) {
4192 qp->rq.head += nreq;
4193
4194 /* Make sure that descriptors are written before
4195 * doorbell record.
4196 */
4197 wmb();
4198
4199 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
4200 }
4201
4202 spin_unlock_irqrestore(&qp->rq.lock, flags);
4203
4204 return err;
4205 }
4206
4207 static inline enum ib_qp_state to_ib_qp_state(enum mlx5_qp_state mlx5_state)
4208 {
4209 switch (mlx5_state) {
4210 case MLX5_QP_STATE_RST: return IB_QPS_RESET;
4211 case MLX5_QP_STATE_INIT: return IB_QPS_INIT;
4212 case MLX5_QP_STATE_RTR: return IB_QPS_RTR;
4213 case MLX5_QP_STATE_RTS: return IB_QPS_RTS;
4214 case MLX5_QP_STATE_SQ_DRAINING:
4215 case MLX5_QP_STATE_SQD: return IB_QPS_SQD;
4216 case MLX5_QP_STATE_SQER: return IB_QPS_SQE;
4217 case MLX5_QP_STATE_ERR: return IB_QPS_ERR;
4218 default: return -1;
4219 }
4220 }
4221
4222 static inline enum ib_mig_state to_ib_mig_state(int mlx5_mig_state)
4223 {
4224 switch (mlx5_mig_state) {
4225 case MLX5_QP_PM_ARMED: return IB_MIG_ARMED;
4226 case MLX5_QP_PM_REARM: return IB_MIG_REARM;
4227 case MLX5_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
4228 default: return -1;
4229 }
4230 }
4231
4232 static int to_ib_qp_access_flags(int mlx5_flags)
4233 {
4234 int ib_flags = 0;
4235
4236 if (mlx5_flags & MLX5_QP_BIT_RRE)
4237 ib_flags |= IB_ACCESS_REMOTE_READ;
4238 if (mlx5_flags & MLX5_QP_BIT_RWE)
4239 ib_flags |= IB_ACCESS_REMOTE_WRITE;
4240 if (mlx5_flags & MLX5_QP_BIT_RAE)
4241 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
4242
4243 return ib_flags;
4244 }
4245
4246 static void to_ib_ah_attr(struct mlx5_ib_dev *ibdev, struct ib_ah_attr *ib_ah_attr,
4247 struct mlx5_qp_path *path)
4248 {
4249 struct mlx5_core_dev *dev = ibdev->mdev;
4250
4251 memset(ib_ah_attr, 0, sizeof(*ib_ah_attr));
4252 ib_ah_attr->port_num = path->port;
4253
4254 if (ib_ah_attr->port_num == 0 ||
4255 ib_ah_attr->port_num > MLX5_CAP_GEN(dev, num_ports))
4256 return;
4257
4258 ib_ah_attr->sl = path->dci_cfi_prio_sl & 0xf;
4259
4260 ib_ah_attr->dlid = be16_to_cpu(path->rlid);
4261 ib_ah_attr->src_path_bits = path->grh_mlid & 0x7f;
4262 ib_ah_attr->static_rate = path->static_rate ? path->static_rate - 5 : 0;
4263 ib_ah_attr->ah_flags = (path->grh_mlid & (1 << 7)) ? IB_AH_GRH : 0;
4264 if (ib_ah_attr->ah_flags) {
4265 ib_ah_attr->grh.sgid_index = path->mgid_index;
4266 ib_ah_attr->grh.hop_limit = path->hop_limit;
4267 ib_ah_attr->grh.traffic_class =
4268 (be32_to_cpu(path->tclass_flowlabel) >> 20) & 0xff;
4269 ib_ah_attr->grh.flow_label =
4270 be32_to_cpu(path->tclass_flowlabel) & 0xfffff;
4271 memcpy(ib_ah_attr->grh.dgid.raw,
4272 path->rgid, sizeof(ib_ah_attr->grh.dgid.raw));
4273 }
4274 }
4275
4276 static int query_raw_packet_qp_sq_state(struct mlx5_ib_dev *dev,
4277 struct mlx5_ib_sq *sq,
4278 u8 *sq_state)
4279 {
4280 void *out;
4281 void *sqc;
4282 int inlen;
4283 int err;
4284
4285 inlen = MLX5_ST_SZ_BYTES(query_sq_out);
4286 out = mlx5_vzalloc(inlen);
4287 if (!out)
4288 return -ENOMEM;
4289
4290 err = mlx5_core_query_sq(dev->mdev, sq->base.mqp.qpn, out);
4291 if (err)
4292 goto out;
4293
4294 sqc = MLX5_ADDR_OF(query_sq_out, out, sq_context);
4295 *sq_state = MLX5_GET(sqc, sqc, state);
4296 sq->state = *sq_state;
4297
4298 out:
4299 kvfree(out);
4300 return err;
4301 }
4302
4303 static int query_raw_packet_qp_rq_state(struct mlx5_ib_dev *dev,
4304 struct mlx5_ib_rq *rq,
4305 u8 *rq_state)
4306 {
4307 void *out;
4308 void *rqc;
4309 int inlen;
4310 int err;
4311
4312 inlen = MLX5_ST_SZ_BYTES(query_rq_out);
4313 out = mlx5_vzalloc(inlen);
4314 if (!out)
4315 return -ENOMEM;
4316
4317 err = mlx5_core_query_rq(dev->mdev, rq->base.mqp.qpn, out);
4318 if (err)
4319 goto out;
4320
4321 rqc = MLX5_ADDR_OF(query_rq_out, out, rq_context);
4322 *rq_state = MLX5_GET(rqc, rqc, state);
4323 rq->state = *rq_state;
4324
4325 out:
4326 kvfree(out);
4327 return err;
4328 }
4329
4330 static int sqrq_state_to_qp_state(u8 sq_state, u8 rq_state,
4331 struct mlx5_ib_qp *qp, u8 *qp_state)
4332 {
4333 static const u8 sqrq_trans[MLX5_RQ_NUM_STATE][MLX5_SQ_NUM_STATE] = {
4334 [MLX5_RQC_STATE_RST] = {
4335 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4336 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4337 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE_BAD,
4338 [MLX5_SQ_STATE_NA] = IB_QPS_RESET,
4339 },
4340 [MLX5_RQC_STATE_RDY] = {
4341 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4342 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4343 [MLX5_SQC_STATE_ERR] = IB_QPS_SQE,
4344 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE,
4345 },
4346 [MLX5_RQC_STATE_ERR] = {
4347 [MLX5_SQC_STATE_RST] = MLX5_QP_STATE_BAD,
4348 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE_BAD,
4349 [MLX5_SQC_STATE_ERR] = IB_QPS_ERR,
4350 [MLX5_SQ_STATE_NA] = IB_QPS_ERR,
4351 },
4352 [MLX5_RQ_STATE_NA] = {
4353 [MLX5_SQC_STATE_RST] = IB_QPS_RESET,
4354 [MLX5_SQC_STATE_RDY] = MLX5_QP_STATE,
4355 [MLX5_SQC_STATE_ERR] = MLX5_QP_STATE,
4356 [MLX5_SQ_STATE_NA] = MLX5_QP_STATE_BAD,
4357 },
4358 };
4359
4360 *qp_state = sqrq_trans[rq_state][sq_state];
4361
4362 if (*qp_state == MLX5_QP_STATE_BAD) {
4363 WARN(1, "Buggy Raw Packet QP state, SQ 0x%x state: 0x%x, RQ 0x%x state: 0x%x",
4364 qp->raw_packet_qp.sq.base.mqp.qpn, sq_state,
4365 qp->raw_packet_qp.rq.base.mqp.qpn, rq_state);
4366 return -EINVAL;
4367 }
4368
4369 if (*qp_state == MLX5_QP_STATE)
4370 *qp_state = qp->state;
4371
4372 return 0;
4373 }
4374
4375 static int query_raw_packet_qp_state(struct mlx5_ib_dev *dev,
4376 struct mlx5_ib_qp *qp,
4377 u8 *raw_packet_qp_state)
4378 {
4379 struct mlx5_ib_raw_packet_qp *raw_packet_qp = &qp->raw_packet_qp;
4380 struct mlx5_ib_sq *sq = &raw_packet_qp->sq;
4381 struct mlx5_ib_rq *rq = &raw_packet_qp->rq;
4382 int err;
4383 u8 sq_state = MLX5_SQ_STATE_NA;
4384 u8 rq_state = MLX5_RQ_STATE_NA;
4385
4386 if (qp->sq.wqe_cnt) {
4387 err = query_raw_packet_qp_sq_state(dev, sq, &sq_state);
4388 if (err)
4389 return err;
4390 }
4391
4392 if (qp->rq.wqe_cnt) {
4393 err = query_raw_packet_qp_rq_state(dev, rq, &rq_state);
4394 if (err)
4395 return err;
4396 }
4397
4398 return sqrq_state_to_qp_state(sq_state, rq_state, qp,
4399 raw_packet_qp_state);
4400 }
4401
4402 static int query_qp_attr(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
4403 struct ib_qp_attr *qp_attr)
4404 {
4405 int outlen = MLX5_ST_SZ_BYTES(query_qp_out);
4406 struct mlx5_qp_context *context;
4407 int mlx5_state;
4408 u32 *outb;
4409 int err = 0;
4410
4411 outb = kzalloc(outlen, GFP_KERNEL);
4412 if (!outb)
4413 return -ENOMEM;
4414
4415 err = mlx5_core_qp_query(dev->mdev, &qp->trans_qp.base.mqp, outb,
4416 outlen);
4417 if (err)
4418 goto out;
4419
4420 /* FIXME: use MLX5_GET rather than mlx5_qp_context manual struct */
4421 context = (struct mlx5_qp_context *)MLX5_ADDR_OF(query_qp_out, outb, qpc);
4422
4423 mlx5_state = be32_to_cpu(context->flags) >> 28;
4424
4425 qp->state = to_ib_qp_state(mlx5_state);
4426 qp_attr->path_mtu = context->mtu_msgmax >> 5;
4427 qp_attr->path_mig_state =
4428 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
4429 qp_attr->qkey = be32_to_cpu(context->qkey);
4430 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
4431 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
4432 qp_attr->dest_qp_num = be32_to_cpu(context->log_pg_sz_remote_qpn) & 0xffffff;
4433 qp_attr->qp_access_flags =
4434 to_ib_qp_access_flags(be32_to_cpu(context->params2));
4435
4436 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
4437 to_ib_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
4438 to_ib_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
4439 qp_attr->alt_pkey_index =
4440 be16_to_cpu(context->alt_path.pkey_index);
4441 qp_attr->alt_port_num = qp_attr->alt_ah_attr.port_num;
4442 }
4443
4444 qp_attr->pkey_index = be16_to_cpu(context->pri_path.pkey_index);
4445 qp_attr->port_num = context->pri_path.port;
4446
4447 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
4448 qp_attr->sq_draining = mlx5_state == MLX5_QP_STATE_SQ_DRAINING;
4449
4450 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
4451
4452 qp_attr->max_dest_rd_atomic =
4453 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
4454 qp_attr->min_rnr_timer =
4455 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
4456 qp_attr->timeout = context->pri_path.ackto_lt >> 3;
4457 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
4458 qp_attr->rnr_retry = (be32_to_cpu(context->params1) >> 13) & 0x7;
4459 qp_attr->alt_timeout = context->alt_path.ackto_lt >> 3;
4460
4461 out:
4462 kfree(outb);
4463 return err;
4464 }
4465
4466 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr,
4467 int qp_attr_mask, struct ib_qp_init_attr *qp_init_attr)
4468 {
4469 struct mlx5_ib_dev *dev = to_mdev(ibqp->device);
4470 struct mlx5_ib_qp *qp = to_mqp(ibqp);
4471 int err = 0;
4472 u8 raw_packet_qp_state;
4473
4474 if (ibqp->rwq_ind_tbl)
4475 return -ENOSYS;
4476
4477 if (unlikely(ibqp->qp_type == IB_QPT_GSI))
4478 return mlx5_ib_gsi_query_qp(ibqp, qp_attr, qp_attr_mask,
4479 qp_init_attr);
4480
4481 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
4482 /*
4483 * Wait for any outstanding page faults, in case the user frees memory
4484 * based upon this query's result.
4485 */
4486 flush_workqueue(mlx5_ib_page_fault_wq);
4487 #endif
4488
4489 mutex_lock(&qp->mutex);
4490
4491 if (qp->ibqp.qp_type == IB_QPT_RAW_PACKET) {
4492 err = query_raw_packet_qp_state(dev, qp, &raw_packet_qp_state);
4493 if (err)
4494 goto out;
4495 qp->state = raw_packet_qp_state;
4496 qp_attr->port_num = 1;
4497 } else {
4498 err = query_qp_attr(dev, qp, qp_attr);
4499 if (err)
4500 goto out;
4501 }
4502
4503 qp_attr->qp_state = qp->state;
4504 qp_attr->cur_qp_state = qp_attr->qp_state;
4505 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4506 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4507
4508 if (!ibqp->uobject) {
4509 qp_attr->cap.max_send_wr = qp->sq.max_post;
4510 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4511 qp_init_attr->qp_context = ibqp->qp_context;
4512 } else {
4513 qp_attr->cap.max_send_wr = 0;
4514 qp_attr->cap.max_send_sge = 0;
4515 }
4516
4517 qp_init_attr->qp_type = ibqp->qp_type;
4518 qp_init_attr->recv_cq = ibqp->recv_cq;
4519 qp_init_attr->send_cq = ibqp->send_cq;
4520 qp_init_attr->srq = ibqp->srq;
4521 qp_attr->cap.max_inline_data = qp->max_inline_data;
4522
4523 qp_init_attr->cap = qp_attr->cap;
4524
4525 qp_init_attr->create_flags = 0;
4526 if (qp->flags & MLX5_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4527 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4528
4529 if (qp->flags & MLX5_IB_QP_CROSS_CHANNEL)
4530 qp_init_attr->create_flags |= IB_QP_CREATE_CROSS_CHANNEL;
4531 if (qp->flags & MLX5_IB_QP_MANAGED_SEND)
4532 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_SEND;
4533 if (qp->flags & MLX5_IB_QP_MANAGED_RECV)
4534 qp_init_attr->create_flags |= IB_QP_CREATE_MANAGED_RECV;
4535 if (qp->flags & MLX5_IB_QP_SQPN_QP1)
4536 qp_init_attr->create_flags |= mlx5_ib_create_qp_sqpn_qp1();
4537
4538 qp_init_attr->sq_sig_type = qp->sq_signal_bits & MLX5_WQE_CTRL_CQ_UPDATE ?
4539 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4540
4541 out:
4542 mutex_unlock(&qp->mutex);
4543 return err;
4544 }
4545
4546 struct ib_xrcd *mlx5_ib_alloc_xrcd(struct ib_device *ibdev,
4547 struct ib_ucontext *context,
4548 struct ib_udata *udata)
4549 {
4550 struct mlx5_ib_dev *dev = to_mdev(ibdev);
4551 struct mlx5_ib_xrcd *xrcd;
4552 int err;
4553
4554 if (!MLX5_CAP_GEN(dev->mdev, xrc))
4555 return ERR_PTR(-ENOSYS);
4556
4557 xrcd = kmalloc(sizeof(*xrcd), GFP_KERNEL);
4558 if (!xrcd)
4559 return ERR_PTR(-ENOMEM);
4560
4561 err = mlx5_core_xrcd_alloc(dev->mdev, &xrcd->xrcdn);
4562 if (err) {
4563 kfree(xrcd);
4564 return ERR_PTR(-ENOMEM);
4565 }
4566
4567 return &xrcd->ibxrcd;
4568 }
4569
4570 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
4571 {
4572 struct mlx5_ib_dev *dev = to_mdev(xrcd->device);
4573 u32 xrcdn = to_mxrcd(xrcd)->xrcdn;
4574 int err;
4575
4576 err = mlx5_core_xrcd_dealloc(dev->mdev, xrcdn);
4577 if (err) {
4578 mlx5_ib_warn(dev, "failed to dealloc xrcdn 0x%x\n", xrcdn);
4579 return err;
4580 }
4581
4582 kfree(xrcd);
4583
4584 return 0;
4585 }
4586
4587 static void mlx5_ib_wq_event(struct mlx5_core_qp *core_qp, int type)
4588 {
4589 struct mlx5_ib_rwq *rwq = to_mibrwq(core_qp);
4590 struct mlx5_ib_dev *dev = to_mdev(rwq->ibwq.device);
4591 struct ib_event event;
4592
4593 if (rwq->ibwq.event_handler) {
4594 event.device = rwq->ibwq.device;
4595 event.element.wq = &rwq->ibwq;
4596 switch (type) {
4597 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR:
4598 event.event = IB_EVENT_WQ_FATAL;
4599 break;
4600 default:
4601 mlx5_ib_warn(dev, "Unexpected event type %d on WQ %06x\n", type, core_qp->qpn);
4602 return;
4603 }
4604
4605 rwq->ibwq.event_handler(&event, rwq->ibwq.wq_context);
4606 }
4607 }
4608
4609 static int create_rq(struct mlx5_ib_rwq *rwq, struct ib_pd *pd,
4610 struct ib_wq_init_attr *init_attr)
4611 {
4612 struct mlx5_ib_dev *dev;
4613 __be64 *rq_pas0;
4614 void *in;
4615 void *rqc;
4616 void *wq;
4617 int inlen;
4618 int err;
4619
4620 dev = to_mdev(pd->device);
4621
4622 inlen = MLX5_ST_SZ_BYTES(create_rq_in) + sizeof(u64) * rwq->rq_num_pas;
4623 in = mlx5_vzalloc(inlen);
4624 if (!in)
4625 return -ENOMEM;
4626
4627 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
4628 MLX5_SET(rqc, rqc, mem_rq_type,
4629 MLX5_RQC_MEM_RQ_TYPE_MEMORY_RQ_INLINE);
4630 MLX5_SET(rqc, rqc, user_index, rwq->user_index);
4631 MLX5_SET(rqc, rqc, cqn, to_mcq(init_attr->cq)->mcq.cqn);
4632 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
4633 MLX5_SET(rqc, rqc, flush_in_error_en, 1);
4634 wq = MLX5_ADDR_OF(rqc, rqc, wq);
4635 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
4636 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
4637 MLX5_SET(wq, wq, log_wq_stride, rwq->log_rq_stride);
4638 MLX5_SET(wq, wq, log_wq_sz, rwq->log_rq_size);
4639 MLX5_SET(wq, wq, pd, to_mpd(pd)->pdn);
4640 MLX5_SET(wq, wq, page_offset, rwq->rq_page_offset);
4641 MLX5_SET(wq, wq, log_wq_pg_sz, rwq->log_page_size);
4642 MLX5_SET(wq, wq, wq_signature, rwq->wq_sig);
4643 MLX5_SET64(wq, wq, dbr_addr, rwq->db.dma);
4644 rq_pas0 = (__be64 *)MLX5_ADDR_OF(wq, wq, pas);
4645 mlx5_ib_populate_pas(dev, rwq->umem, rwq->page_shift, rq_pas0, 0);
4646 err = mlx5_core_create_rq_tracked(dev->mdev, in, inlen, &rwq->core_qp);
4647 kvfree(in);
4648 return err;
4649 }
4650
4651 static int set_user_rq_size(struct mlx5_ib_dev *dev,
4652 struct ib_wq_init_attr *wq_init_attr,
4653 struct mlx5_ib_create_wq *ucmd,
4654 struct mlx5_ib_rwq *rwq)
4655 {
4656 /* Sanity check RQ size before proceeding */
4657 if (wq_init_attr->max_wr > (1 << MLX5_CAP_GEN(dev->mdev, log_max_wq_sz)))
4658 return -EINVAL;
4659
4660 if (!ucmd->rq_wqe_count)
4661 return -EINVAL;
4662
4663 rwq->wqe_count = ucmd->rq_wqe_count;
4664 rwq->wqe_shift = ucmd->rq_wqe_shift;
4665 rwq->buf_size = (rwq->wqe_count << rwq->wqe_shift);
4666 rwq->log_rq_stride = rwq->wqe_shift;
4667 rwq->log_rq_size = ilog2(rwq->wqe_count);
4668 return 0;
4669 }
4670
4671 static int prepare_user_rq(struct ib_pd *pd,
4672 struct ib_wq_init_attr *init_attr,
4673 struct ib_udata *udata,
4674 struct mlx5_ib_rwq *rwq)
4675 {
4676 struct mlx5_ib_dev *dev = to_mdev(pd->device);
4677 struct mlx5_ib_create_wq ucmd = {};
4678 int err;
4679 size_t required_cmd_sz;
4680
4681 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4682 if (udata->inlen < required_cmd_sz) {
4683 mlx5_ib_dbg(dev, "invalid inlen\n");
4684 return -EINVAL;
4685 }
4686
4687 if (udata->inlen > sizeof(ucmd) &&
4688 !ib_is_udata_cleared(udata, sizeof(ucmd),
4689 udata->inlen - sizeof(ucmd))) {
4690 mlx5_ib_dbg(dev, "inlen is not supported\n");
4691 return -EOPNOTSUPP;
4692 }
4693
4694 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
4695 mlx5_ib_dbg(dev, "copy failed\n");
4696 return -EFAULT;
4697 }
4698
4699 if (ucmd.comp_mask) {
4700 mlx5_ib_dbg(dev, "invalid comp mask\n");
4701 return -EOPNOTSUPP;
4702 }
4703
4704 if (ucmd.reserved) {
4705 mlx5_ib_dbg(dev, "invalid reserved\n");
4706 return -EOPNOTSUPP;
4707 }
4708
4709 err = set_user_rq_size(dev, init_attr, &ucmd, rwq);
4710 if (err) {
4711 mlx5_ib_dbg(dev, "err %d\n", err);
4712 return err;
4713 }
4714
4715 err = create_user_rq(dev, pd, rwq, &ucmd);
4716 if (err) {
4717 mlx5_ib_dbg(dev, "err %d\n", err);
4718 if (err)
4719 return err;
4720 }
4721
4722 rwq->user_index = ucmd.user_index;
4723 return 0;
4724 }
4725
4726 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
4727 struct ib_wq_init_attr *init_attr,
4728 struct ib_udata *udata)
4729 {
4730 struct mlx5_ib_dev *dev;
4731 struct mlx5_ib_rwq *rwq;
4732 struct mlx5_ib_create_wq_resp resp = {};
4733 size_t min_resp_len;
4734 int err;
4735
4736 if (!udata)
4737 return ERR_PTR(-ENOSYS);
4738
4739 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4740 if (udata->outlen && udata->outlen < min_resp_len)
4741 return ERR_PTR(-EINVAL);
4742
4743 dev = to_mdev(pd->device);
4744 switch (init_attr->wq_type) {
4745 case IB_WQT_RQ:
4746 rwq = kzalloc(sizeof(*rwq), GFP_KERNEL);
4747 if (!rwq)
4748 return ERR_PTR(-ENOMEM);
4749 err = prepare_user_rq(pd, init_attr, udata, rwq);
4750 if (err)
4751 goto err;
4752 err = create_rq(rwq, pd, init_attr);
4753 if (err)
4754 goto err_user_rq;
4755 break;
4756 default:
4757 mlx5_ib_dbg(dev, "unsupported wq type %d\n",
4758 init_attr->wq_type);
4759 return ERR_PTR(-EINVAL);
4760 }
4761
4762 rwq->ibwq.wq_num = rwq->core_qp.qpn;
4763 rwq->ibwq.state = IB_WQS_RESET;
4764 if (udata->outlen) {
4765 resp.response_length = offsetof(typeof(resp), response_length) +
4766 sizeof(resp.response_length);
4767 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4768 if (err)
4769 goto err_copy;
4770 }
4771
4772 rwq->core_qp.event = mlx5_ib_wq_event;
4773 rwq->ibwq.event_handler = init_attr->event_handler;
4774 return &rwq->ibwq;
4775
4776 err_copy:
4777 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4778 err_user_rq:
4779 destroy_user_rq(pd, rwq);
4780 err:
4781 kfree(rwq);
4782 return ERR_PTR(err);
4783 }
4784
4785 int mlx5_ib_destroy_wq(struct ib_wq *wq)
4786 {
4787 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4788 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4789
4790 mlx5_core_destroy_rq_tracked(dev->mdev, &rwq->core_qp);
4791 destroy_user_rq(wq->pd, rwq);
4792 kfree(rwq);
4793
4794 return 0;
4795 }
4796
4797 struct ib_rwq_ind_table *mlx5_ib_create_rwq_ind_table(struct ib_device *device,
4798 struct ib_rwq_ind_table_init_attr *init_attr,
4799 struct ib_udata *udata)
4800 {
4801 struct mlx5_ib_dev *dev = to_mdev(device);
4802 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl;
4803 int sz = 1 << init_attr->log_ind_tbl_size;
4804 struct mlx5_ib_create_rwq_ind_tbl_resp resp = {};
4805 size_t min_resp_len;
4806 int inlen;
4807 int err;
4808 int i;
4809 u32 *in;
4810 void *rqtc;
4811
4812 if (udata->inlen > 0 &&
4813 !ib_is_udata_cleared(udata, 0,
4814 udata->inlen))
4815 return ERR_PTR(-EOPNOTSUPP);
4816
4817 if (init_attr->log_ind_tbl_size >
4818 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size)) {
4819 mlx5_ib_dbg(dev, "log_ind_tbl_size = %d is bigger than supported = %d\n",
4820 init_attr->log_ind_tbl_size,
4821 MLX5_CAP_GEN(dev->mdev, log_max_rqt_size));
4822 return ERR_PTR(-EINVAL);
4823 }
4824
4825 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4826 if (udata->outlen && udata->outlen < min_resp_len)
4827 return ERR_PTR(-EINVAL);
4828
4829 rwq_ind_tbl = kzalloc(sizeof(*rwq_ind_tbl), GFP_KERNEL);
4830 if (!rwq_ind_tbl)
4831 return ERR_PTR(-ENOMEM);
4832
4833 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
4834 in = mlx5_vzalloc(inlen);
4835 if (!in) {
4836 err = -ENOMEM;
4837 goto err;
4838 }
4839
4840 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
4841
4842 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
4843 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
4844
4845 for (i = 0; i < sz; i++)
4846 MLX5_SET(rqtc, rqtc, rq_num[i], init_attr->ind_tbl[i]->wq_num);
4847
4848 err = mlx5_core_create_rqt(dev->mdev, in, inlen, &rwq_ind_tbl->rqtn);
4849 kvfree(in);
4850
4851 if (err)
4852 goto err;
4853
4854 rwq_ind_tbl->ib_rwq_ind_tbl.ind_tbl_num = rwq_ind_tbl->rqtn;
4855 if (udata->outlen) {
4856 resp.response_length = offsetof(typeof(resp), response_length) +
4857 sizeof(resp.response_length);
4858 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4859 if (err)
4860 goto err_copy;
4861 }
4862
4863 return &rwq_ind_tbl->ib_rwq_ind_tbl;
4864
4865 err_copy:
4866 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4867 err:
4868 kfree(rwq_ind_tbl);
4869 return ERR_PTR(err);
4870 }
4871
4872 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4873 {
4874 struct mlx5_ib_rwq_ind_table *rwq_ind_tbl = to_mrwq_ind_table(ib_rwq_ind_tbl);
4875 struct mlx5_ib_dev *dev = to_mdev(ib_rwq_ind_tbl->device);
4876
4877 mlx5_core_destroy_rqt(dev->mdev, rwq_ind_tbl->rqtn);
4878
4879 kfree(rwq_ind_tbl);
4880 return 0;
4881 }
4882
4883 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
4884 u32 wq_attr_mask, struct ib_udata *udata)
4885 {
4886 struct mlx5_ib_dev *dev = to_mdev(wq->device);
4887 struct mlx5_ib_rwq *rwq = to_mrwq(wq);
4888 struct mlx5_ib_modify_wq ucmd = {};
4889 size_t required_cmd_sz;
4890 int curr_wq_state;
4891 int wq_state;
4892 int inlen;
4893 int err;
4894 void *rqc;
4895 void *in;
4896
4897 required_cmd_sz = offsetof(typeof(ucmd), reserved) + sizeof(ucmd.reserved);
4898 if (udata->inlen < required_cmd_sz)
4899 return -EINVAL;
4900
4901 if (udata->inlen > sizeof(ucmd) &&
4902 !ib_is_udata_cleared(udata, sizeof(ucmd),
4903 udata->inlen - sizeof(ucmd)))
4904 return -EOPNOTSUPP;
4905
4906 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4907 return -EFAULT;
4908
4909 if (ucmd.comp_mask || ucmd.reserved)
4910 return -EOPNOTSUPP;
4911
4912 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
4913 in = mlx5_vzalloc(inlen);
4914 if (!in)
4915 return -ENOMEM;
4916
4917 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
4918
4919 curr_wq_state = (wq_attr_mask & IB_WQ_CUR_STATE) ?
4920 wq_attr->curr_wq_state : wq->state;
4921 wq_state = (wq_attr_mask & IB_WQ_STATE) ?
4922 wq_attr->wq_state : curr_wq_state;
4923 if (curr_wq_state == IB_WQS_ERR)
4924 curr_wq_state = MLX5_RQC_STATE_ERR;
4925 if (wq_state == IB_WQS_ERR)
4926 wq_state = MLX5_RQC_STATE_ERR;
4927 MLX5_SET(modify_rq_in, in, rq_state, curr_wq_state);
4928 MLX5_SET(rqc, rqc, state, wq_state);
4929
4930 err = mlx5_core_modify_rq(dev->mdev, rwq->core_qp.qpn, in, inlen);
4931 kvfree(in);
4932 if (!err)
4933 rwq->ibwq.state = (wq_state == MLX5_RQC_STATE_ERR) ? IB_WQS_ERR : wq_state;
4934
4935 return err;
4936 }
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