2 * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 * Copyright (c) 2005, 2006 Cisco Systems. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 * $Id: mthca_cmd.c 1349 2004-12-16 21:09:43Z roland $
37 #include <linux/completion.h>
38 #include <linux/pci.h>
39 #include <linux/errno.h>
40 #include <linux/sched.h>
42 #include <rdma/ib_mad.h>
44 #include "mthca_dev.h"
45 #include "mthca_config_reg.h"
46 #include "mthca_cmd.h"
47 #include "mthca_memfree.h"
49 #define CMD_POLL_TOKEN 0xffff
52 HCR_IN_PARAM_OFFSET
= 0x00,
53 HCR_IN_MODIFIER_OFFSET
= 0x08,
54 HCR_OUT_PARAM_OFFSET
= 0x0c,
55 HCR_TOKEN_OFFSET
= 0x14,
56 HCR_STATUS_OFFSET
= 0x18,
64 /* initialization and general commands */
70 CMD_MOD_STAT_CFG
= 0x34,
71 CMD_QUERY_DEV_LIM
= 0x3,
73 CMD_ENABLE_LAM
= 0xff8,
74 CMD_DISABLE_LAM
= 0xff7,
76 CMD_QUERY_ADAPTER
= 0x6,
83 CMD_ACCESS_DDR
= 0x2e,
85 CMD_UNMAP_ICM
= 0xff9,
86 CMD_MAP_ICM_AUX
= 0xffc,
87 CMD_UNMAP_ICM_AUX
= 0xffb,
88 CMD_SET_ICM_SIZE
= 0xffd,
108 CMD_RESIZE_CQ
= 0x2c,
111 CMD_SW2HW_SRQ
= 0x35,
112 CMD_HW2SW_SRQ
= 0x36,
113 CMD_QUERY_SRQ
= 0x37,
117 CMD_RST2INIT_QPEE
= 0x19,
118 CMD_INIT2RTR_QPEE
= 0x1a,
119 CMD_RTR2RTS_QPEE
= 0x1b,
120 CMD_RTS2RTS_QPEE
= 0x1c,
121 CMD_SQERR2RTS_QPEE
= 0x1d,
122 CMD_2ERR_QPEE
= 0x1e,
123 CMD_RTS2SQD_QPEE
= 0x1f,
124 CMD_SQD2SQD_QPEE
= 0x38,
125 CMD_SQD2RTS_QPEE
= 0x20,
126 CMD_ERR2RST_QPEE
= 0x21,
127 CMD_QUERY_QPEE
= 0x22,
128 CMD_INIT2INIT_QPEE
= 0x2d,
129 CMD_SUSPEND_QPEE
= 0x32,
130 CMD_UNSUSPEND_QPEE
= 0x33,
131 /* special QPs and management commands */
132 CMD_CONF_SPECIAL_QP
= 0x23,
135 /* multicast commands */
137 CMD_WRITE_MGM
= 0x26,
138 CMD_MGID_HASH
= 0x27,
140 /* miscellaneous commands */
141 CMD_DIAG_RPRT
= 0x30,
145 CMD_QUERY_DEBUG_MSG
= 0x2a,
146 CMD_SET_DEBUG_MSG
= 0x2b,
150 * According to Mellanox code, FW may be starved and never complete
151 * commands. So we can't use strict timeouts described in PRM -- we
152 * just arbitrarily select 60 seconds for now.
156 * Round up and add 1 to make sure we get the full wait time (since we
157 * will be starting in the middle of a jiffy)
160 CMD_TIME_CLASS_A
= (HZ
+ 999) / 1000 + 1,
161 CMD_TIME_CLASS_B
= (HZ
+ 99) / 100 + 1,
162 CMD_TIME_CLASS_C
= (HZ
+ 9) / 10 + 1
166 CMD_TIME_CLASS_A
= 60 * HZ
,
167 CMD_TIME_CLASS_B
= 60 * HZ
,
168 CMD_TIME_CLASS_C
= 60 * HZ
173 GO_BIT_TIMEOUT
= HZ
* 10
176 struct mthca_cmd_context
{
177 struct completion done
;
185 static int fw_cmd_doorbell
= 0;
186 module_param(fw_cmd_doorbell
, int, 0644);
187 MODULE_PARM_DESC(fw_cmd_doorbell
, "post FW commands through doorbell page if nonzero "
188 "(and supported by FW)");
190 static inline int go_bit(struct mthca_dev
*dev
)
192 return readl(dev
->hcr
+ HCR_STATUS_OFFSET
) &
193 swab32(1 << HCR_GO_BIT
);
196 static void mthca_cmd_post_dbell(struct mthca_dev
*dev
,
204 void __iomem
*ptr
= dev
->cmd
.dbell_map
;
205 u16
*offs
= dev
->cmd
.dbell_offsets
;
207 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), ptr
+ offs
[0]);
209 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), ptr
+ offs
[1]);
211 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), ptr
+ offs
[2]);
213 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), ptr
+ offs
[3]);
215 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), ptr
+ offs
[4]);
217 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), ptr
+ offs
[5]);
219 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
221 (op_modifier
<< HCR_OPMOD_SHIFT
) |
224 __raw_writel((__force u32
) 0, ptr
+ offs
[7]);
228 static int mthca_cmd_post_hcr(struct mthca_dev
*dev
,
238 unsigned long end
= jiffies
+ GO_BIT_TIMEOUT
;
240 while (go_bit(dev
) && time_before(jiffies
, end
)) {
241 set_current_state(TASK_RUNNING
);
250 * We use writel (instead of something like memcpy_toio)
251 * because writes of less than 32 bits to the HCR don't work
252 * (and some architectures such as ia64 implement memcpy_toio
253 * in terms of writeb).
255 __raw_writel((__force u32
) cpu_to_be32(in_param
>> 32), dev
->hcr
+ 0 * 4);
256 __raw_writel((__force u32
) cpu_to_be32(in_param
& 0xfffffffful
), dev
->hcr
+ 1 * 4);
257 __raw_writel((__force u32
) cpu_to_be32(in_modifier
), dev
->hcr
+ 2 * 4);
258 __raw_writel((__force u32
) cpu_to_be32(out_param
>> 32), dev
->hcr
+ 3 * 4);
259 __raw_writel((__force u32
) cpu_to_be32(out_param
& 0xfffffffful
), dev
->hcr
+ 4 * 4);
260 __raw_writel((__force u32
) cpu_to_be32(token
<< 16), dev
->hcr
+ 5 * 4);
262 /* __raw_writel may not order writes. */
265 __raw_writel((__force u32
) cpu_to_be32((1 << HCR_GO_BIT
) |
266 (event
? (1 << HCA_E_BIT
) : 0) |
267 (op_modifier
<< HCR_OPMOD_SHIFT
) |
268 op
), dev
->hcr
+ 6 * 4);
273 static int mthca_cmd_post(struct mthca_dev
*dev
,
284 mutex_lock(&dev
->cmd
.hcr_mutex
);
286 if (event
&& dev
->cmd
.flags
& MTHCA_CMD_POST_DOORBELLS
&& fw_cmd_doorbell
)
287 mthca_cmd_post_dbell(dev
, in_param
, out_param
, in_modifier
,
288 op_modifier
, op
, token
);
290 err
= mthca_cmd_post_hcr(dev
, in_param
, out_param
, in_modifier
,
291 op_modifier
, op
, token
, event
);
293 mutex_unlock(&dev
->cmd
.hcr_mutex
);
297 static int mthca_cmd_poll(struct mthca_dev
*dev
,
304 unsigned long timeout
,
310 down(&dev
->cmd
.poll_sem
);
312 err
= mthca_cmd_post(dev
, in_param
,
313 out_param
? *out_param
: 0,
314 in_modifier
, op_modifier
,
315 op
, CMD_POLL_TOKEN
, 0);
319 end
= timeout
+ jiffies
;
320 while (go_bit(dev
) && time_before(jiffies
, end
)) {
321 set_current_state(TASK_RUNNING
);
332 (u64
) be32_to_cpu((__force __be32
)
333 __raw_readl(dev
->hcr
+ HCR_OUT_PARAM_OFFSET
)) << 32 |
334 (u64
) be32_to_cpu((__force __be32
)
335 __raw_readl(dev
->hcr
+ HCR_OUT_PARAM_OFFSET
+ 4));
337 *status
= be32_to_cpu((__force __be32
) __raw_readl(dev
->hcr
+ HCR_STATUS_OFFSET
)) >> 24;
340 up(&dev
->cmd
.poll_sem
);
344 void mthca_cmd_event(struct mthca_dev
*dev
,
349 struct mthca_cmd_context
*context
=
350 &dev
->cmd
.context
[token
& dev
->cmd
.token_mask
];
352 /* previously timed out command completing at long last */
353 if (token
!= context
->token
)
357 context
->status
= status
;
358 context
->out_param
= out_param
;
360 context
->token
+= dev
->cmd
.token_mask
+ 1;
362 complete(&context
->done
);
365 static int mthca_cmd_wait(struct mthca_dev
*dev
,
372 unsigned long timeout
,
376 struct mthca_cmd_context
*context
;
378 down(&dev
->cmd
.event_sem
);
380 spin_lock(&dev
->cmd
.context_lock
);
381 BUG_ON(dev
->cmd
.free_head
< 0);
382 context
= &dev
->cmd
.context
[dev
->cmd
.free_head
];
383 dev
->cmd
.free_head
= context
->next
;
384 spin_unlock(&dev
->cmd
.context_lock
);
386 init_completion(&context
->done
);
388 err
= mthca_cmd_post(dev
, in_param
,
389 out_param
? *out_param
: 0,
390 in_modifier
, op_modifier
,
391 op
, context
->token
, 1);
395 if (!wait_for_completion_timeout(&context
->done
, timeout
)) {
400 err
= context
->result
;
404 *status
= context
->status
;
406 mthca_dbg(dev
, "Command %02x completed with status %02x\n",
410 *out_param
= context
->out_param
;
413 spin_lock(&dev
->cmd
.context_lock
);
414 context
->next
= dev
->cmd
.free_head
;
415 dev
->cmd
.free_head
= context
- dev
->cmd
.context
;
416 spin_unlock(&dev
->cmd
.context_lock
);
418 up(&dev
->cmd
.event_sem
);
422 /* Invoke a command with an output mailbox */
423 static int mthca_cmd_box(struct mthca_dev
*dev
,
429 unsigned long timeout
,
432 if (dev
->cmd
.flags
& MTHCA_CMD_USE_EVENTS
)
433 return mthca_cmd_wait(dev
, in_param
, &out_param
, 0,
434 in_modifier
, op_modifier
, op
,
437 return mthca_cmd_poll(dev
, in_param
, &out_param
, 0,
438 in_modifier
, op_modifier
, op
,
442 /* Invoke a command with no output parameter */
443 static int mthca_cmd(struct mthca_dev
*dev
,
448 unsigned long timeout
,
451 return mthca_cmd_box(dev
, in_param
, 0, in_modifier
,
452 op_modifier
, op
, timeout
, status
);
456 * Invoke a command with an immediate output parameter (and copy the
457 * output into the caller's out_param pointer after the command
460 static int mthca_cmd_imm(struct mthca_dev
*dev
,
466 unsigned long timeout
,
469 if (dev
->cmd
.flags
& MTHCA_CMD_USE_EVENTS
)
470 return mthca_cmd_wait(dev
, in_param
, out_param
, 1,
471 in_modifier
, op_modifier
, op
,
474 return mthca_cmd_poll(dev
, in_param
, out_param
, 1,
475 in_modifier
, op_modifier
, op
,
479 int mthca_cmd_init(struct mthca_dev
*dev
)
481 mutex_init(&dev
->cmd
.hcr_mutex
);
482 sema_init(&dev
->cmd
.poll_sem
, 1);
485 dev
->hcr
= ioremap(pci_resource_start(dev
->pdev
, 0) + MTHCA_HCR_BASE
,
488 mthca_err(dev
, "Couldn't map command register.");
492 dev
->cmd
.pool
= pci_pool_create("mthca_cmd", dev
->pdev
,
494 MTHCA_MAILBOX_SIZE
, 0);
495 if (!dev
->cmd
.pool
) {
503 void mthca_cmd_cleanup(struct mthca_dev
*dev
)
505 pci_pool_destroy(dev
->cmd
.pool
);
507 if (dev
->cmd
.flags
& MTHCA_CMD_POST_DOORBELLS
)
508 iounmap(dev
->cmd
.dbell_map
);
512 * Switch to using events to issue FW commands (should be called after
513 * event queue to command events has been initialized).
515 int mthca_cmd_use_events(struct mthca_dev
*dev
)
519 dev
->cmd
.context
= kmalloc(dev
->cmd
.max_cmds
*
520 sizeof (struct mthca_cmd_context
),
522 if (!dev
->cmd
.context
)
525 for (i
= 0; i
< dev
->cmd
.max_cmds
; ++i
) {
526 dev
->cmd
.context
[i
].token
= i
;
527 dev
->cmd
.context
[i
].next
= i
+ 1;
530 dev
->cmd
.context
[dev
->cmd
.max_cmds
- 1].next
= -1;
531 dev
->cmd
.free_head
= 0;
533 sema_init(&dev
->cmd
.event_sem
, dev
->cmd
.max_cmds
);
534 spin_lock_init(&dev
->cmd
.context_lock
);
536 for (dev
->cmd
.token_mask
= 1;
537 dev
->cmd
.token_mask
< dev
->cmd
.max_cmds
;
538 dev
->cmd
.token_mask
<<= 1)
540 --dev
->cmd
.token_mask
;
542 dev
->cmd
.flags
|= MTHCA_CMD_USE_EVENTS
;
544 down(&dev
->cmd
.poll_sem
);
550 * Switch back to polling (used when shutting down the device)
552 void mthca_cmd_use_polling(struct mthca_dev
*dev
)
556 dev
->cmd
.flags
&= ~MTHCA_CMD_USE_EVENTS
;
558 for (i
= 0; i
< dev
->cmd
.max_cmds
; ++i
)
559 down(&dev
->cmd
.event_sem
);
561 kfree(dev
->cmd
.context
);
563 up(&dev
->cmd
.poll_sem
);
566 struct mthca_mailbox
*mthca_alloc_mailbox(struct mthca_dev
*dev
,
569 struct mthca_mailbox
*mailbox
;
571 mailbox
= kmalloc(sizeof *mailbox
, gfp_mask
);
573 return ERR_PTR(-ENOMEM
);
575 mailbox
->buf
= pci_pool_alloc(dev
->cmd
.pool
, gfp_mask
, &mailbox
->dma
);
578 return ERR_PTR(-ENOMEM
);
584 void mthca_free_mailbox(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
)
589 pci_pool_free(dev
->cmd
.pool
, mailbox
->buf
, mailbox
->dma
);
593 int mthca_SYS_EN(struct mthca_dev
*dev
, u8
*status
)
598 ret
= mthca_cmd_imm(dev
, 0, &out
, 0, 0, CMD_SYS_EN
, HZ
, status
);
600 if (*status
== MTHCA_CMD_STAT_DDR_MEM_ERR
)
601 mthca_warn(dev
, "SYS_EN DDR error: syn=%x, sock=%d, "
602 "sladdr=%d, SPD source=%s\n",
603 (int) (out
>> 6) & 0xf, (int) (out
>> 4) & 3,
604 (int) (out
>> 1) & 7, (int) out
& 1 ? "NVMEM" : "DIMM");
609 int mthca_SYS_DIS(struct mthca_dev
*dev
, u8
*status
)
611 return mthca_cmd(dev
, 0, 0, 0, CMD_SYS_DIS
, HZ
, status
);
614 static int mthca_map_cmd(struct mthca_dev
*dev
, u16 op
, struct mthca_icm
*icm
,
615 u64 virt
, u8
*status
)
617 struct mthca_mailbox
*mailbox
;
618 struct mthca_icm_iter iter
;
626 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
628 return PTR_ERR(mailbox
);
629 memset(mailbox
->buf
, 0, MTHCA_MAILBOX_SIZE
);
630 pages
= mailbox
->buf
;
632 for (mthca_icm_first(icm
, &iter
);
633 !mthca_icm_last(&iter
);
634 mthca_icm_next(&iter
)) {
636 * We have to pass pages that are aligned to their
637 * size, so find the least significant 1 in the
638 * address or size and use that as our log2 size.
640 lg
= ffs(mthca_icm_addr(&iter
) | mthca_icm_size(&iter
)) - 1;
641 if (lg
< MTHCA_ICM_PAGE_SHIFT
) {
642 mthca_warn(dev
, "Got FW area not aligned to %d (%llx/%lx).\n",
644 (unsigned long long) mthca_icm_addr(&iter
),
645 mthca_icm_size(&iter
));
649 for (i
= 0; i
< mthca_icm_size(&iter
) >> lg
; ++i
) {
651 pages
[nent
* 2] = cpu_to_be64(virt
);
655 pages
[nent
* 2 + 1] =
656 cpu_to_be64((mthca_icm_addr(&iter
) + (i
<< lg
)) |
657 (lg
- MTHCA_ICM_PAGE_SHIFT
));
658 ts
+= 1 << (lg
- 10);
661 if (++nent
== MTHCA_MAILBOX_SIZE
/ 16) {
662 err
= mthca_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
663 CMD_TIME_CLASS_B
, status
);
672 err
= mthca_cmd(dev
, mailbox
->dma
, nent
, 0, op
,
673 CMD_TIME_CLASS_B
, status
);
677 mthca_dbg(dev
, "Mapped %d chunks/%d KB for FW.\n", tc
, ts
);
679 case CMD_MAP_ICM_AUX
:
680 mthca_dbg(dev
, "Mapped %d chunks/%d KB for ICM aux.\n", tc
, ts
);
683 mthca_dbg(dev
, "Mapped %d chunks/%d KB at %llx for ICM.\n",
684 tc
, ts
, (unsigned long long) virt
- (ts
<< 10));
689 mthca_free_mailbox(dev
, mailbox
);
693 int mthca_MAP_FA(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u8
*status
)
695 return mthca_map_cmd(dev
, CMD_MAP_FA
, icm
, -1, status
);
698 int mthca_UNMAP_FA(struct mthca_dev
*dev
, u8
*status
)
700 return mthca_cmd(dev
, 0, 0, 0, CMD_UNMAP_FA
, CMD_TIME_CLASS_B
, status
);
703 int mthca_RUN_FW(struct mthca_dev
*dev
, u8
*status
)
705 return mthca_cmd(dev
, 0, 0, 0, CMD_RUN_FW
, CMD_TIME_CLASS_A
, status
);
708 static void mthca_setup_cmd_doorbells(struct mthca_dev
*dev
, u64 base
)
714 for (i
= 0; i
< 8; ++i
)
715 max_off
= max(max_off
, dev
->cmd
.dbell_offsets
[i
]);
717 if ((base
& PAGE_MASK
) != ((base
+ max_off
) & PAGE_MASK
)) {
718 mthca_warn(dev
, "Firmware doorbell region at 0x%016llx, "
719 "length 0x%x crosses a page boundary\n",
720 (unsigned long long) base
, max_off
);
724 addr
= pci_resource_start(dev
->pdev
, 2) +
725 ((pci_resource_len(dev
->pdev
, 2) - 1) & base
);
726 dev
->cmd
.dbell_map
= ioremap(addr
, max_off
+ sizeof(u32
));
727 if (!dev
->cmd
.dbell_map
)
730 dev
->cmd
.flags
|= MTHCA_CMD_POST_DOORBELLS
;
731 mthca_dbg(dev
, "Mapped doorbell page for posting FW commands\n");
734 int mthca_QUERY_FW(struct mthca_dev
*dev
, u8
*status
)
736 struct mthca_mailbox
*mailbox
;
744 #define QUERY_FW_OUT_SIZE 0x100
745 #define QUERY_FW_VER_OFFSET 0x00
746 #define QUERY_FW_MAX_CMD_OFFSET 0x0f
747 #define QUERY_FW_ERR_START_OFFSET 0x30
748 #define QUERY_FW_ERR_SIZE_OFFSET 0x38
750 #define QUERY_FW_CMD_DB_EN_OFFSET 0x10
751 #define QUERY_FW_CMD_DB_OFFSET 0x50
752 #define QUERY_FW_CMD_DB_BASE 0x60
754 #define QUERY_FW_START_OFFSET 0x20
755 #define QUERY_FW_END_OFFSET 0x28
757 #define QUERY_FW_SIZE_OFFSET 0x00
758 #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20
759 #define QUERY_FW_EQ_ARM_BASE_OFFSET 0x40
760 #define QUERY_FW_EQ_SET_CI_BASE_OFFSET 0x48
762 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
764 return PTR_ERR(mailbox
);
765 outbox
= mailbox
->buf
;
767 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_FW
,
768 CMD_TIME_CLASS_A
, status
);
773 MTHCA_GET(dev
->fw_ver
, outbox
, QUERY_FW_VER_OFFSET
);
775 * FW subminor version is at more signifant bits than minor
776 * version, so swap here.
778 dev
->fw_ver
= (dev
->fw_ver
& 0xffff00000000ull
) |
779 ((dev
->fw_ver
& 0xffff0000ull
) >> 16) |
780 ((dev
->fw_ver
& 0x0000ffffull
) << 16);
782 MTHCA_GET(lg
, outbox
, QUERY_FW_MAX_CMD_OFFSET
);
783 dev
->cmd
.max_cmds
= 1 << lg
;
785 mthca_dbg(dev
, "FW version %012llx, max commands %d\n",
786 (unsigned long long) dev
->fw_ver
, dev
->cmd
.max_cmds
);
788 MTHCA_GET(dev
->catas_err
.addr
, outbox
, QUERY_FW_ERR_START_OFFSET
);
789 MTHCA_GET(dev
->catas_err
.size
, outbox
, QUERY_FW_ERR_SIZE_OFFSET
);
791 mthca_dbg(dev
, "Catastrophic error buffer at 0x%llx, size 0x%x\n",
792 (unsigned long long) dev
->catas_err
.addr
, dev
->catas_err
.size
);
794 MTHCA_GET(tmp
, outbox
, QUERY_FW_CMD_DB_EN_OFFSET
);
796 mthca_dbg(dev
, "FW supports commands through doorbells\n");
798 MTHCA_GET(base
, outbox
, QUERY_FW_CMD_DB_BASE
);
799 for (i
= 0; i
< MTHCA_CMD_NUM_DBELL_DWORDS
; ++i
)
800 MTHCA_GET(dev
->cmd
.dbell_offsets
[i
], outbox
,
801 QUERY_FW_CMD_DB_OFFSET
+ (i
<< 1));
803 mthca_setup_cmd_doorbells(dev
, base
);
806 if (mthca_is_memfree(dev
)) {
807 MTHCA_GET(dev
->fw
.arbel
.fw_pages
, outbox
, QUERY_FW_SIZE_OFFSET
);
808 MTHCA_GET(dev
->fw
.arbel
.clr_int_base
, outbox
, QUERY_FW_CLR_INT_BASE_OFFSET
);
809 MTHCA_GET(dev
->fw
.arbel
.eq_arm_base
, outbox
, QUERY_FW_EQ_ARM_BASE_OFFSET
);
810 MTHCA_GET(dev
->fw
.arbel
.eq_set_ci_base
, outbox
, QUERY_FW_EQ_SET_CI_BASE_OFFSET
);
811 mthca_dbg(dev
, "FW size %d KB\n", dev
->fw
.arbel
.fw_pages
<< 2);
814 * Round up number of system pages needed in case
815 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
817 dev
->fw
.arbel
.fw_pages
=
818 ALIGN(dev
->fw
.arbel
.fw_pages
, PAGE_SIZE
/ MTHCA_ICM_PAGE_SIZE
) >>
819 (PAGE_SHIFT
- MTHCA_ICM_PAGE_SHIFT
);
821 mthca_dbg(dev
, "Clear int @ %llx, EQ arm @ %llx, EQ set CI @ %llx\n",
822 (unsigned long long) dev
->fw
.arbel
.clr_int_base
,
823 (unsigned long long) dev
->fw
.arbel
.eq_arm_base
,
824 (unsigned long long) dev
->fw
.arbel
.eq_set_ci_base
);
826 MTHCA_GET(dev
->fw
.tavor
.fw_start
, outbox
, QUERY_FW_START_OFFSET
);
827 MTHCA_GET(dev
->fw
.tavor
.fw_end
, outbox
, QUERY_FW_END_OFFSET
);
829 mthca_dbg(dev
, "FW size %d KB (start %llx, end %llx)\n",
830 (int) ((dev
->fw
.tavor
.fw_end
- dev
->fw
.tavor
.fw_start
) >> 10),
831 (unsigned long long) dev
->fw
.tavor
.fw_start
,
832 (unsigned long long) dev
->fw
.tavor
.fw_end
);
836 mthca_free_mailbox(dev
, mailbox
);
840 int mthca_ENABLE_LAM(struct mthca_dev
*dev
, u8
*status
)
842 struct mthca_mailbox
*mailbox
;
847 #define ENABLE_LAM_OUT_SIZE 0x100
848 #define ENABLE_LAM_START_OFFSET 0x00
849 #define ENABLE_LAM_END_OFFSET 0x08
850 #define ENABLE_LAM_INFO_OFFSET 0x13
852 #define ENABLE_LAM_INFO_HIDDEN_FLAG (1 << 4)
853 #define ENABLE_LAM_INFO_ECC_MASK 0x3
855 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
857 return PTR_ERR(mailbox
);
858 outbox
= mailbox
->buf
;
860 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_ENABLE_LAM
,
861 CMD_TIME_CLASS_C
, status
);
866 if (*status
== MTHCA_CMD_STAT_LAM_NOT_PRE
)
869 MTHCA_GET(dev
->ddr_start
, outbox
, ENABLE_LAM_START_OFFSET
);
870 MTHCA_GET(dev
->ddr_end
, outbox
, ENABLE_LAM_END_OFFSET
);
871 MTHCA_GET(info
, outbox
, ENABLE_LAM_INFO_OFFSET
);
873 if (!!(info
& ENABLE_LAM_INFO_HIDDEN_FLAG
) !=
874 !!(dev
->mthca_flags
& MTHCA_FLAG_DDR_HIDDEN
)) {
875 mthca_info(dev
, "FW reports that HCA-attached memory "
876 "is %s hidden; does not match PCI config\n",
877 (info
& ENABLE_LAM_INFO_HIDDEN_FLAG
) ?
880 if (info
& ENABLE_LAM_INFO_HIDDEN_FLAG
)
881 mthca_dbg(dev
, "HCA-attached memory is hidden.\n");
883 mthca_dbg(dev
, "HCA memory size %d KB (start %llx, end %llx)\n",
884 (int) ((dev
->ddr_end
- dev
->ddr_start
) >> 10),
885 (unsigned long long) dev
->ddr_start
,
886 (unsigned long long) dev
->ddr_end
);
889 mthca_free_mailbox(dev
, mailbox
);
893 int mthca_DISABLE_LAM(struct mthca_dev
*dev
, u8
*status
)
895 return mthca_cmd(dev
, 0, 0, 0, CMD_SYS_DIS
, CMD_TIME_CLASS_C
, status
);
898 int mthca_QUERY_DDR(struct mthca_dev
*dev
, u8
*status
)
900 struct mthca_mailbox
*mailbox
;
905 #define QUERY_DDR_OUT_SIZE 0x100
906 #define QUERY_DDR_START_OFFSET 0x00
907 #define QUERY_DDR_END_OFFSET 0x08
908 #define QUERY_DDR_INFO_OFFSET 0x13
910 #define QUERY_DDR_INFO_HIDDEN_FLAG (1 << 4)
911 #define QUERY_DDR_INFO_ECC_MASK 0x3
913 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
915 return PTR_ERR(mailbox
);
916 outbox
= mailbox
->buf
;
918 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_DDR
,
919 CMD_TIME_CLASS_A
, status
);
924 MTHCA_GET(dev
->ddr_start
, outbox
, QUERY_DDR_START_OFFSET
);
925 MTHCA_GET(dev
->ddr_end
, outbox
, QUERY_DDR_END_OFFSET
);
926 MTHCA_GET(info
, outbox
, QUERY_DDR_INFO_OFFSET
);
928 if (!!(info
& QUERY_DDR_INFO_HIDDEN_FLAG
) !=
929 !!(dev
->mthca_flags
& MTHCA_FLAG_DDR_HIDDEN
)) {
930 mthca_info(dev
, "FW reports that HCA-attached memory "
931 "is %s hidden; does not match PCI config\n",
932 (info
& QUERY_DDR_INFO_HIDDEN_FLAG
) ?
935 if (info
& QUERY_DDR_INFO_HIDDEN_FLAG
)
936 mthca_dbg(dev
, "HCA-attached memory is hidden.\n");
938 mthca_dbg(dev
, "HCA memory size %d KB (start %llx, end %llx)\n",
939 (int) ((dev
->ddr_end
- dev
->ddr_start
) >> 10),
940 (unsigned long long) dev
->ddr_start
,
941 (unsigned long long) dev
->ddr_end
);
944 mthca_free_mailbox(dev
, mailbox
);
948 int mthca_QUERY_DEV_LIM(struct mthca_dev
*dev
,
949 struct mthca_dev_lim
*dev_lim
, u8
*status
)
951 struct mthca_mailbox
*mailbox
;
958 #define QUERY_DEV_LIM_OUT_SIZE 0x100
959 #define QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET 0x10
960 #define QUERY_DEV_LIM_MAX_QP_SZ_OFFSET 0x11
961 #define QUERY_DEV_LIM_RSVD_QP_OFFSET 0x12
962 #define QUERY_DEV_LIM_MAX_QP_OFFSET 0x13
963 #define QUERY_DEV_LIM_RSVD_SRQ_OFFSET 0x14
964 #define QUERY_DEV_LIM_MAX_SRQ_OFFSET 0x15
965 #define QUERY_DEV_LIM_RSVD_EEC_OFFSET 0x16
966 #define QUERY_DEV_LIM_MAX_EEC_OFFSET 0x17
967 #define QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET 0x19
968 #define QUERY_DEV_LIM_RSVD_CQ_OFFSET 0x1a
969 #define QUERY_DEV_LIM_MAX_CQ_OFFSET 0x1b
970 #define QUERY_DEV_LIM_MAX_MPT_OFFSET 0x1d
971 #define QUERY_DEV_LIM_RSVD_EQ_OFFSET 0x1e
972 #define QUERY_DEV_LIM_MAX_EQ_OFFSET 0x1f
973 #define QUERY_DEV_LIM_RSVD_MTT_OFFSET 0x20
974 #define QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET 0x21
975 #define QUERY_DEV_LIM_RSVD_MRW_OFFSET 0x22
976 #define QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET 0x23
977 #define QUERY_DEV_LIM_MAX_AV_OFFSET 0x27
978 #define QUERY_DEV_LIM_MAX_REQ_QP_OFFSET 0x29
979 #define QUERY_DEV_LIM_MAX_RES_QP_OFFSET 0x2b
980 #define QUERY_DEV_LIM_MAX_RDMA_OFFSET 0x2f
981 #define QUERY_DEV_LIM_RSZ_SRQ_OFFSET 0x33
982 #define QUERY_DEV_LIM_ACK_DELAY_OFFSET 0x35
983 #define QUERY_DEV_LIM_MTU_WIDTH_OFFSET 0x36
984 #define QUERY_DEV_LIM_VL_PORT_OFFSET 0x37
985 #define QUERY_DEV_LIM_MAX_GID_OFFSET 0x3b
986 #define QUERY_DEV_LIM_RATE_SUPPORT_OFFSET 0x3c
987 #define QUERY_DEV_LIM_MAX_PKEY_OFFSET 0x3f
988 #define QUERY_DEV_LIM_FLAGS_OFFSET 0x44
989 #define QUERY_DEV_LIM_RSVD_UAR_OFFSET 0x48
990 #define QUERY_DEV_LIM_UAR_SZ_OFFSET 0x49
991 #define QUERY_DEV_LIM_PAGE_SZ_OFFSET 0x4b
992 #define QUERY_DEV_LIM_MAX_SG_OFFSET 0x51
993 #define QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET 0x52
994 #define QUERY_DEV_LIM_MAX_SG_RQ_OFFSET 0x55
995 #define QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET 0x56
996 #define QUERY_DEV_LIM_MAX_QP_MCG_OFFSET 0x61
997 #define QUERY_DEV_LIM_RSVD_MCG_OFFSET 0x62
998 #define QUERY_DEV_LIM_MAX_MCG_OFFSET 0x63
999 #define QUERY_DEV_LIM_RSVD_PD_OFFSET 0x64
1000 #define QUERY_DEV_LIM_MAX_PD_OFFSET 0x65
1001 #define QUERY_DEV_LIM_RSVD_RDD_OFFSET 0x66
1002 #define QUERY_DEV_LIM_MAX_RDD_OFFSET 0x67
1003 #define QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET 0x80
1004 #define QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET 0x82
1005 #define QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET 0x84
1006 #define QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET 0x86
1007 #define QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET 0x88
1008 #define QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET 0x8a
1009 #define QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET 0x8c
1010 #define QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET 0x8e
1011 #define QUERY_DEV_LIM_MTT_ENTRY_SZ_OFFSET 0x90
1012 #define QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET 0x92
1013 #define QUERY_DEV_LIM_PBL_SZ_OFFSET 0x96
1014 #define QUERY_DEV_LIM_BMME_FLAGS_OFFSET 0x97
1015 #define QUERY_DEV_LIM_RSVD_LKEY_OFFSET 0x98
1016 #define QUERY_DEV_LIM_LAMR_OFFSET 0x9f
1017 #define QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET 0xa0
1019 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1020 if (IS_ERR(mailbox
))
1021 return PTR_ERR(mailbox
);
1022 outbox
= mailbox
->buf
;
1024 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_DEV_LIM
,
1025 CMD_TIME_CLASS_A
, status
);
1030 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_QP_OFFSET
);
1031 dev_lim
->reserved_qps
= 1 << (field
& 0xf);
1032 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_OFFSET
);
1033 dev_lim
->max_qps
= 1 << (field
& 0x1f);
1034 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_SRQ_OFFSET
);
1035 dev_lim
->reserved_srqs
= 1 << (field
>> 4);
1036 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_OFFSET
);
1037 dev_lim
->max_srqs
= 1 << (field
& 0x1f);
1038 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_EEC_OFFSET
);
1039 dev_lim
->reserved_eecs
= 1 << (field
& 0xf);
1040 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_EEC_OFFSET
);
1041 dev_lim
->max_eecs
= 1 << (field
& 0x1f);
1042 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_CQ_SZ_OFFSET
);
1043 dev_lim
->max_cq_sz
= 1 << field
;
1044 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_CQ_OFFSET
);
1045 dev_lim
->reserved_cqs
= 1 << (field
& 0xf);
1046 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_CQ_OFFSET
);
1047 dev_lim
->max_cqs
= 1 << (field
& 0x1f);
1048 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MPT_OFFSET
);
1049 dev_lim
->max_mpts
= 1 << (field
& 0x3f);
1050 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_EQ_OFFSET
);
1051 dev_lim
->reserved_eqs
= 1 << (field
& 0xf);
1052 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_EQ_OFFSET
);
1053 dev_lim
->max_eqs
= 1 << (field
& 0x7);
1054 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MTT_OFFSET
);
1055 if (mthca_is_memfree(dev
))
1056 dev_lim
->reserved_mtts
= ALIGN((1 << (field
>> 4)) * sizeof(u64
),
1057 MTHCA_MTT_SEG_SIZE
) / MTHCA_MTT_SEG_SIZE
;
1059 dev_lim
->reserved_mtts
= 1 << (field
>> 4);
1060 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MRW_SZ_OFFSET
);
1061 dev_lim
->max_mrw_sz
= 1 << field
;
1062 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MRW_OFFSET
);
1063 dev_lim
->reserved_mrws
= 1 << (field
& 0xf);
1064 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MTT_SEG_OFFSET
);
1065 dev_lim
->max_mtt_seg
= 1 << (field
& 0x3f);
1066 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_REQ_QP_OFFSET
);
1067 dev_lim
->max_requester_per_qp
= 1 << (field
& 0x3f);
1068 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RES_QP_OFFSET
);
1069 dev_lim
->max_responder_per_qp
= 1 << (field
& 0x3f);
1070 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RDMA_OFFSET
);
1071 dev_lim
->max_rdma_global
= 1 << (field
& 0x3f);
1072 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_ACK_DELAY_OFFSET
);
1073 dev_lim
->local_ca_ack_delay
= field
& 0x1f;
1074 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MTU_WIDTH_OFFSET
);
1075 dev_lim
->max_mtu
= field
>> 4;
1076 dev_lim
->max_port_width
= field
& 0xf;
1077 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_VL_PORT_OFFSET
);
1078 dev_lim
->max_vl
= field
>> 4;
1079 dev_lim
->num_ports
= field
& 0xf;
1080 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_GID_OFFSET
);
1081 dev_lim
->max_gids
= 1 << (field
& 0xf);
1082 MTHCA_GET(stat_rate
, outbox
, QUERY_DEV_LIM_RATE_SUPPORT_OFFSET
);
1083 dev_lim
->stat_rate_support
= stat_rate
;
1084 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_PKEY_OFFSET
);
1085 dev_lim
->max_pkeys
= 1 << (field
& 0xf);
1086 MTHCA_GET(dev_lim
->flags
, outbox
, QUERY_DEV_LIM_FLAGS_OFFSET
);
1087 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_UAR_OFFSET
);
1088 dev_lim
->reserved_uars
= field
>> 4;
1089 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_UAR_SZ_OFFSET
);
1090 dev_lim
->uar_size
= 1 << ((field
& 0x3f) + 20);
1091 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_PAGE_SZ_OFFSET
);
1092 dev_lim
->min_page_sz
= 1 << field
;
1093 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SG_OFFSET
);
1094 dev_lim
->max_sg
= field
;
1096 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MAX_DESC_SZ_OFFSET
);
1097 dev_lim
->max_desc_sz
= size
;
1099 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_MCG_OFFSET
);
1100 dev_lim
->max_qp_per_mcg
= 1 << field
;
1101 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_MCG_OFFSET
);
1102 dev_lim
->reserved_mgms
= field
& 0xf;
1103 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_MCG_OFFSET
);
1104 dev_lim
->max_mcgs
= 1 << field
;
1105 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_PD_OFFSET
);
1106 dev_lim
->reserved_pds
= field
>> 4;
1107 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_PD_OFFSET
);
1108 dev_lim
->max_pds
= 1 << (field
& 0x3f);
1109 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSVD_RDD_OFFSET
);
1110 dev_lim
->reserved_rdds
= field
>> 4;
1111 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_RDD_OFFSET
);
1112 dev_lim
->max_rdds
= 1 << (field
& 0x3f);
1114 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EEC_ENTRY_SZ_OFFSET
);
1115 dev_lim
->eec_entry_sz
= size
;
1116 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_QPC_ENTRY_SZ_OFFSET
);
1117 dev_lim
->qpc_entry_sz
= size
;
1118 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EEEC_ENTRY_SZ_OFFSET
);
1119 dev_lim
->eeec_entry_sz
= size
;
1120 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EQPC_ENTRY_SZ_OFFSET
);
1121 dev_lim
->eqpc_entry_sz
= size
;
1122 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_EQC_ENTRY_SZ_OFFSET
);
1123 dev_lim
->eqc_entry_sz
= size
;
1124 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_CQC_ENTRY_SZ_OFFSET
);
1125 dev_lim
->cqc_entry_sz
= size
;
1126 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_SRQ_ENTRY_SZ_OFFSET
);
1127 dev_lim
->srq_entry_sz
= size
;
1128 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_UAR_ENTRY_SZ_OFFSET
);
1129 dev_lim
->uar_scratch_entry_sz
= size
;
1131 if (mthca_is_memfree(dev
)) {
1132 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET
);
1133 dev_lim
->max_srq_sz
= 1 << field
;
1134 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET
);
1135 dev_lim
->max_qp_sz
= 1 << field
;
1136 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_RSZ_SRQ_OFFSET
);
1137 dev_lim
->hca
.arbel
.resize_srq
= field
& 1;
1138 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SG_RQ_OFFSET
);
1139 dev_lim
->max_sg
= min_t(int, field
, dev_lim
->max_sg
);
1140 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MAX_DESC_SZ_RQ_OFFSET
);
1141 dev_lim
->max_desc_sz
= min_t(int, size
, dev_lim
->max_desc_sz
);
1142 MTHCA_GET(size
, outbox
, QUERY_DEV_LIM_MPT_ENTRY_SZ_OFFSET
);
1143 dev_lim
->mpt_entry_sz
= size
;
1144 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_PBL_SZ_OFFSET
);
1145 dev_lim
->hca
.arbel
.max_pbl_sz
= 1 << (field
& 0x3f);
1146 MTHCA_GET(dev_lim
->hca
.arbel
.bmme_flags
, outbox
,
1147 QUERY_DEV_LIM_BMME_FLAGS_OFFSET
);
1148 MTHCA_GET(dev_lim
->hca
.arbel
.reserved_lkey
, outbox
,
1149 QUERY_DEV_LIM_RSVD_LKEY_OFFSET
);
1150 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_LAMR_OFFSET
);
1151 dev_lim
->hca
.arbel
.lam_required
= field
& 1;
1152 MTHCA_GET(dev_lim
->hca
.arbel
.max_icm_sz
, outbox
,
1153 QUERY_DEV_LIM_MAX_ICM_SZ_OFFSET
);
1155 if (dev_lim
->hca
.arbel
.bmme_flags
& 1)
1156 mthca_dbg(dev
, "Base MM extensions: yes "
1157 "(flags %d, max PBL %d, rsvd L_Key %08x)\n",
1158 dev_lim
->hca
.arbel
.bmme_flags
,
1159 dev_lim
->hca
.arbel
.max_pbl_sz
,
1160 dev_lim
->hca
.arbel
.reserved_lkey
);
1162 mthca_dbg(dev
, "Base MM extensions: no\n");
1164 mthca_dbg(dev
, "Max ICM size %lld MB\n",
1165 (unsigned long long) dev_lim
->hca
.arbel
.max_icm_sz
>> 20);
1167 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_SRQ_SZ_OFFSET
);
1168 dev_lim
->max_srq_sz
= (1 << field
) - 1;
1169 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_QP_SZ_OFFSET
);
1170 dev_lim
->max_qp_sz
= (1 << field
) - 1;
1171 MTHCA_GET(field
, outbox
, QUERY_DEV_LIM_MAX_AV_OFFSET
);
1172 dev_lim
->hca
.tavor
.max_avs
= 1 << (field
& 0x3f);
1173 dev_lim
->mpt_entry_sz
= MTHCA_MPT_ENTRY_SIZE
;
1176 mthca_dbg(dev
, "Max QPs: %d, reserved QPs: %d, entry size: %d\n",
1177 dev_lim
->max_qps
, dev_lim
->reserved_qps
, dev_lim
->qpc_entry_sz
);
1178 mthca_dbg(dev
, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n",
1179 dev_lim
->max_srqs
, dev_lim
->reserved_srqs
, dev_lim
->srq_entry_sz
);
1180 mthca_dbg(dev
, "Max CQs: %d, reserved CQs: %d, entry size: %d\n",
1181 dev_lim
->max_cqs
, dev_lim
->reserved_cqs
, dev_lim
->cqc_entry_sz
);
1182 mthca_dbg(dev
, "Max EQs: %d, reserved EQs: %d, entry size: %d\n",
1183 dev_lim
->max_eqs
, dev_lim
->reserved_eqs
, dev_lim
->eqc_entry_sz
);
1184 mthca_dbg(dev
, "reserved MPTs: %d, reserved MTTs: %d\n",
1185 dev_lim
->reserved_mrws
, dev_lim
->reserved_mtts
);
1186 mthca_dbg(dev
, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n",
1187 dev_lim
->max_pds
, dev_lim
->reserved_pds
, dev_lim
->reserved_uars
);
1188 mthca_dbg(dev
, "Max QP/MCG: %d, reserved MGMs: %d\n",
1189 dev_lim
->max_pds
, dev_lim
->reserved_mgms
);
1190 mthca_dbg(dev
, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n",
1191 dev_lim
->max_cq_sz
, dev_lim
->max_qp_sz
, dev_lim
->max_srq_sz
);
1193 mthca_dbg(dev
, "Flags: %08x\n", dev_lim
->flags
);
1196 mthca_free_mailbox(dev
, mailbox
);
1200 static void get_board_id(void *vsd
, char *board_id
)
1204 #define VSD_OFFSET_SIG1 0x00
1205 #define VSD_OFFSET_SIG2 0xde
1206 #define VSD_OFFSET_MLX_BOARD_ID 0xd0
1207 #define VSD_OFFSET_TS_BOARD_ID 0x20
1209 #define VSD_SIGNATURE_TOPSPIN 0x5ad
1211 memset(board_id
, 0, MTHCA_BOARD_ID_LEN
);
1213 if (be16_to_cpup(vsd
+ VSD_OFFSET_SIG1
) == VSD_SIGNATURE_TOPSPIN
&&
1214 be16_to_cpup(vsd
+ VSD_OFFSET_SIG2
) == VSD_SIGNATURE_TOPSPIN
) {
1215 strlcpy(board_id
, vsd
+ VSD_OFFSET_TS_BOARD_ID
, MTHCA_BOARD_ID_LEN
);
1218 * The board ID is a string but the firmware byte
1219 * swaps each 4-byte word before passing it back to
1220 * us. Therefore we need to swab it before printing.
1222 for (i
= 0; i
< 4; ++i
)
1223 ((u32
*) board_id
)[i
] =
1224 swab32(*(u32
*) (vsd
+ VSD_OFFSET_MLX_BOARD_ID
+ i
* 4));
1228 int mthca_QUERY_ADAPTER(struct mthca_dev
*dev
,
1229 struct mthca_adapter
*adapter
, u8
*status
)
1231 struct mthca_mailbox
*mailbox
;
1235 #define QUERY_ADAPTER_OUT_SIZE 0x100
1236 #define QUERY_ADAPTER_VENDOR_ID_OFFSET 0x00
1237 #define QUERY_ADAPTER_DEVICE_ID_OFFSET 0x04
1238 #define QUERY_ADAPTER_REVISION_ID_OFFSET 0x08
1239 #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10
1240 #define QUERY_ADAPTER_VSD_OFFSET 0x20
1242 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1243 if (IS_ERR(mailbox
))
1244 return PTR_ERR(mailbox
);
1245 outbox
= mailbox
->buf
;
1247 err
= mthca_cmd_box(dev
, 0, mailbox
->dma
, 0, 0, CMD_QUERY_ADAPTER
,
1248 CMD_TIME_CLASS_A
, status
);
1253 MTHCA_GET(adapter
->vendor_id
, outbox
, QUERY_ADAPTER_VENDOR_ID_OFFSET
);
1254 MTHCA_GET(adapter
->device_id
, outbox
, QUERY_ADAPTER_DEVICE_ID_OFFSET
);
1255 MTHCA_GET(adapter
->revision_id
, outbox
, QUERY_ADAPTER_REVISION_ID_OFFSET
);
1256 MTHCA_GET(adapter
->inta_pin
, outbox
, QUERY_ADAPTER_INTA_PIN_OFFSET
);
1258 get_board_id(outbox
+ QUERY_ADAPTER_VSD_OFFSET
/ 4,
1262 mthca_free_mailbox(dev
, mailbox
);
1266 int mthca_INIT_HCA(struct mthca_dev
*dev
,
1267 struct mthca_init_hca_param
*param
,
1270 struct mthca_mailbox
*mailbox
;
1274 #define INIT_HCA_IN_SIZE 0x200
1275 #define INIT_HCA_FLAGS1_OFFSET 0x00c
1276 #define INIT_HCA_FLAGS2_OFFSET 0x014
1277 #define INIT_HCA_QPC_OFFSET 0x020
1278 #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10)
1279 #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17)
1280 #define INIT_HCA_EEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x20)
1281 #define INIT_HCA_LOG_EEC_OFFSET (INIT_HCA_QPC_OFFSET + 0x27)
1282 #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28)
1283 #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f)
1284 #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30)
1285 #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37)
1286 #define INIT_HCA_EQPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40)
1287 #define INIT_HCA_EEEC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50)
1288 #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60)
1289 #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67)
1290 #define INIT_HCA_RDB_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70)
1291 #define INIT_HCA_UDAV_OFFSET 0x0b0
1292 #define INIT_HCA_UDAV_LKEY_OFFSET (INIT_HCA_UDAV_OFFSET + 0x0)
1293 #define INIT_HCA_UDAV_PD_OFFSET (INIT_HCA_UDAV_OFFSET + 0x4)
1294 #define INIT_HCA_MCAST_OFFSET 0x0c0
1295 #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00)
1296 #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12)
1297 #define INIT_HCA_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16)
1298 #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b)
1299 #define INIT_HCA_TPT_OFFSET 0x0f0
1300 #define INIT_HCA_MPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00)
1301 #define INIT_HCA_MTT_SEG_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x09)
1302 #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b)
1303 #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10)
1304 #define INIT_HCA_UAR_OFFSET 0x120
1305 #define INIT_HCA_UAR_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x00)
1306 #define INIT_HCA_UARC_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x09)
1307 #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a)
1308 #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b)
1309 #define INIT_HCA_UAR_SCATCH_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x10)
1310 #define INIT_HCA_UAR_CTX_BASE_OFFSET (INIT_HCA_UAR_OFFSET + 0x18)
1312 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1313 if (IS_ERR(mailbox
))
1314 return PTR_ERR(mailbox
);
1315 inbox
= mailbox
->buf
;
1317 memset(inbox
, 0, INIT_HCA_IN_SIZE
);
1319 if (dev
->mthca_flags
& MTHCA_FLAG_SINAI_OPT
)
1320 MTHCA_PUT(inbox
, 0x1, INIT_HCA_FLAGS1_OFFSET
);
1322 #if defined(__LITTLE_ENDIAN)
1323 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) &= ~cpu_to_be32(1 << 1);
1324 #elif defined(__BIG_ENDIAN)
1325 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) |= cpu_to_be32(1 << 1);
1327 #error Host endianness not defined
1329 /* Check port for UD address vector: */
1330 *(inbox
+ INIT_HCA_FLAGS2_OFFSET
/ 4) |= cpu_to_be32(1);
1332 /* We leave wqe_quota, responder_exu, etc as 0 (default) */
1334 /* QPC/EEC/CQC/EQC/RDB attributes */
1336 MTHCA_PUT(inbox
, param
->qpc_base
, INIT_HCA_QPC_BASE_OFFSET
);
1337 MTHCA_PUT(inbox
, param
->log_num_qps
, INIT_HCA_LOG_QP_OFFSET
);
1338 MTHCA_PUT(inbox
, param
->eec_base
, INIT_HCA_EEC_BASE_OFFSET
);
1339 MTHCA_PUT(inbox
, param
->log_num_eecs
, INIT_HCA_LOG_EEC_OFFSET
);
1340 MTHCA_PUT(inbox
, param
->srqc_base
, INIT_HCA_SRQC_BASE_OFFSET
);
1341 MTHCA_PUT(inbox
, param
->log_num_srqs
, INIT_HCA_LOG_SRQ_OFFSET
);
1342 MTHCA_PUT(inbox
, param
->cqc_base
, INIT_HCA_CQC_BASE_OFFSET
);
1343 MTHCA_PUT(inbox
, param
->log_num_cqs
, INIT_HCA_LOG_CQ_OFFSET
);
1344 MTHCA_PUT(inbox
, param
->eqpc_base
, INIT_HCA_EQPC_BASE_OFFSET
);
1345 MTHCA_PUT(inbox
, param
->eeec_base
, INIT_HCA_EEEC_BASE_OFFSET
);
1346 MTHCA_PUT(inbox
, param
->eqc_base
, INIT_HCA_EQC_BASE_OFFSET
);
1347 MTHCA_PUT(inbox
, param
->log_num_eqs
, INIT_HCA_LOG_EQ_OFFSET
);
1348 MTHCA_PUT(inbox
, param
->rdb_base
, INIT_HCA_RDB_BASE_OFFSET
);
1350 /* UD AV attributes */
1352 /* multicast attributes */
1354 MTHCA_PUT(inbox
, param
->mc_base
, INIT_HCA_MC_BASE_OFFSET
);
1355 MTHCA_PUT(inbox
, param
->log_mc_entry_sz
, INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET
);
1356 MTHCA_PUT(inbox
, param
->mc_hash_sz
, INIT_HCA_MC_HASH_SZ_OFFSET
);
1357 MTHCA_PUT(inbox
, param
->log_mc_table_sz
, INIT_HCA_LOG_MC_TABLE_SZ_OFFSET
);
1359 /* TPT attributes */
1361 MTHCA_PUT(inbox
, param
->mpt_base
, INIT_HCA_MPT_BASE_OFFSET
);
1362 if (!mthca_is_memfree(dev
))
1363 MTHCA_PUT(inbox
, param
->mtt_seg_sz
, INIT_HCA_MTT_SEG_SZ_OFFSET
);
1364 MTHCA_PUT(inbox
, param
->log_mpt_sz
, INIT_HCA_LOG_MPT_SZ_OFFSET
);
1365 MTHCA_PUT(inbox
, param
->mtt_base
, INIT_HCA_MTT_BASE_OFFSET
);
1367 /* UAR attributes */
1369 u8 uar_page_sz
= PAGE_SHIFT
- 12;
1370 MTHCA_PUT(inbox
, uar_page_sz
, INIT_HCA_UAR_PAGE_SZ_OFFSET
);
1373 MTHCA_PUT(inbox
, param
->uar_scratch_base
, INIT_HCA_UAR_SCATCH_BASE_OFFSET
);
1375 if (mthca_is_memfree(dev
)) {
1376 MTHCA_PUT(inbox
, param
->log_uarc_sz
, INIT_HCA_UARC_SZ_OFFSET
);
1377 MTHCA_PUT(inbox
, param
->log_uar_sz
, INIT_HCA_LOG_UAR_SZ_OFFSET
);
1378 MTHCA_PUT(inbox
, param
->uarc_base
, INIT_HCA_UAR_CTX_BASE_OFFSET
);
1381 err
= mthca_cmd(dev
, mailbox
->dma
, 0, 0, CMD_INIT_HCA
, HZ
, status
);
1383 mthca_free_mailbox(dev
, mailbox
);
1387 int mthca_INIT_IB(struct mthca_dev
*dev
,
1388 struct mthca_init_ib_param
*param
,
1389 int port
, u8
*status
)
1391 struct mthca_mailbox
*mailbox
;
1396 #define INIT_IB_IN_SIZE 56
1397 #define INIT_IB_FLAGS_OFFSET 0x00
1398 #define INIT_IB_FLAG_SIG (1 << 18)
1399 #define INIT_IB_FLAG_NG (1 << 17)
1400 #define INIT_IB_FLAG_G0 (1 << 16)
1401 #define INIT_IB_VL_SHIFT 4
1402 #define INIT_IB_PORT_WIDTH_SHIFT 8
1403 #define INIT_IB_MTU_SHIFT 12
1404 #define INIT_IB_MAX_GID_OFFSET 0x06
1405 #define INIT_IB_MAX_PKEY_OFFSET 0x0a
1406 #define INIT_IB_GUID0_OFFSET 0x10
1407 #define INIT_IB_NODE_GUID_OFFSET 0x18
1408 #define INIT_IB_SI_GUID_OFFSET 0x20
1410 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1411 if (IS_ERR(mailbox
))
1412 return PTR_ERR(mailbox
);
1413 inbox
= mailbox
->buf
;
1415 memset(inbox
, 0, INIT_IB_IN_SIZE
);
1418 flags
|= param
->set_guid0
? INIT_IB_FLAG_G0
: 0;
1419 flags
|= param
->set_node_guid
? INIT_IB_FLAG_NG
: 0;
1420 flags
|= param
->set_si_guid
? INIT_IB_FLAG_SIG
: 0;
1421 flags
|= param
->vl_cap
<< INIT_IB_VL_SHIFT
;
1422 flags
|= param
->port_width
<< INIT_IB_PORT_WIDTH_SHIFT
;
1423 flags
|= param
->mtu_cap
<< INIT_IB_MTU_SHIFT
;
1424 MTHCA_PUT(inbox
, flags
, INIT_IB_FLAGS_OFFSET
);
1426 MTHCA_PUT(inbox
, param
->gid_cap
, INIT_IB_MAX_GID_OFFSET
);
1427 MTHCA_PUT(inbox
, param
->pkey_cap
, INIT_IB_MAX_PKEY_OFFSET
);
1428 MTHCA_PUT(inbox
, param
->guid0
, INIT_IB_GUID0_OFFSET
);
1429 MTHCA_PUT(inbox
, param
->node_guid
, INIT_IB_NODE_GUID_OFFSET
);
1430 MTHCA_PUT(inbox
, param
->si_guid
, INIT_IB_SI_GUID_OFFSET
);
1432 err
= mthca_cmd(dev
, mailbox
->dma
, port
, 0, CMD_INIT_IB
,
1433 CMD_TIME_CLASS_A
, status
);
1435 mthca_free_mailbox(dev
, mailbox
);
1439 int mthca_CLOSE_IB(struct mthca_dev
*dev
, int port
, u8
*status
)
1441 return mthca_cmd(dev
, 0, port
, 0, CMD_CLOSE_IB
, HZ
, status
);
1444 int mthca_CLOSE_HCA(struct mthca_dev
*dev
, int panic
, u8
*status
)
1446 return mthca_cmd(dev
, 0, 0, panic
, CMD_CLOSE_HCA
, HZ
, status
);
1449 int mthca_SET_IB(struct mthca_dev
*dev
, struct mthca_set_ib_param
*param
,
1450 int port
, u8
*status
)
1452 struct mthca_mailbox
*mailbox
;
1457 #define SET_IB_IN_SIZE 0x40
1458 #define SET_IB_FLAGS_OFFSET 0x00
1459 #define SET_IB_FLAG_SIG (1 << 18)
1460 #define SET_IB_FLAG_RQK (1 << 0)
1461 #define SET_IB_CAP_MASK_OFFSET 0x04
1462 #define SET_IB_SI_GUID_OFFSET 0x08
1464 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1465 if (IS_ERR(mailbox
))
1466 return PTR_ERR(mailbox
);
1467 inbox
= mailbox
->buf
;
1469 memset(inbox
, 0, SET_IB_IN_SIZE
);
1471 flags
|= param
->set_si_guid
? SET_IB_FLAG_SIG
: 0;
1472 flags
|= param
->reset_qkey_viol
? SET_IB_FLAG_RQK
: 0;
1473 MTHCA_PUT(inbox
, flags
, SET_IB_FLAGS_OFFSET
);
1475 MTHCA_PUT(inbox
, param
->cap_mask
, SET_IB_CAP_MASK_OFFSET
);
1476 MTHCA_PUT(inbox
, param
->si_guid
, SET_IB_SI_GUID_OFFSET
);
1478 err
= mthca_cmd(dev
, mailbox
->dma
, port
, 0, CMD_SET_IB
,
1479 CMD_TIME_CLASS_B
, status
);
1481 mthca_free_mailbox(dev
, mailbox
);
1485 int mthca_MAP_ICM(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u64 virt
, u8
*status
)
1487 return mthca_map_cmd(dev
, CMD_MAP_ICM
, icm
, virt
, status
);
1490 int mthca_MAP_ICM_page(struct mthca_dev
*dev
, u64 dma_addr
, u64 virt
, u8
*status
)
1492 struct mthca_mailbox
*mailbox
;
1496 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1497 if (IS_ERR(mailbox
))
1498 return PTR_ERR(mailbox
);
1499 inbox
= mailbox
->buf
;
1501 inbox
[0] = cpu_to_be64(virt
);
1502 inbox
[1] = cpu_to_be64(dma_addr
);
1504 err
= mthca_cmd(dev
, mailbox
->dma
, 1, 0, CMD_MAP_ICM
,
1505 CMD_TIME_CLASS_B
, status
);
1507 mthca_free_mailbox(dev
, mailbox
);
1510 mthca_dbg(dev
, "Mapped page at %llx to %llx for ICM.\n",
1511 (unsigned long long) dma_addr
, (unsigned long long) virt
);
1516 int mthca_UNMAP_ICM(struct mthca_dev
*dev
, u64 virt
, u32 page_count
, u8
*status
)
1518 mthca_dbg(dev
, "Unmapping %d pages at %llx from ICM.\n",
1519 page_count
, (unsigned long long) virt
);
1521 return mthca_cmd(dev
, virt
, page_count
, 0, CMD_UNMAP_ICM
, CMD_TIME_CLASS_B
, status
);
1524 int mthca_MAP_ICM_AUX(struct mthca_dev
*dev
, struct mthca_icm
*icm
, u8
*status
)
1526 return mthca_map_cmd(dev
, CMD_MAP_ICM_AUX
, icm
, -1, status
);
1529 int mthca_UNMAP_ICM_AUX(struct mthca_dev
*dev
, u8
*status
)
1531 return mthca_cmd(dev
, 0, 0, 0, CMD_UNMAP_ICM_AUX
, CMD_TIME_CLASS_B
, status
);
1534 int mthca_SET_ICM_SIZE(struct mthca_dev
*dev
, u64 icm_size
, u64
*aux_pages
,
1537 int ret
= mthca_cmd_imm(dev
, icm_size
, aux_pages
, 0, 0, CMD_SET_ICM_SIZE
,
1538 CMD_TIME_CLASS_A
, status
);
1544 * Round up number of system pages needed in case
1545 * MTHCA_ICM_PAGE_SIZE < PAGE_SIZE.
1547 *aux_pages
= ALIGN(*aux_pages
, PAGE_SIZE
/ MTHCA_ICM_PAGE_SIZE
) >>
1548 (PAGE_SHIFT
- MTHCA_ICM_PAGE_SHIFT
);
1553 int mthca_SW2HW_MPT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1554 int mpt_index
, u8
*status
)
1556 return mthca_cmd(dev
, mailbox
->dma
, mpt_index
, 0, CMD_SW2HW_MPT
,
1557 CMD_TIME_CLASS_B
, status
);
1560 int mthca_HW2SW_MPT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1561 int mpt_index
, u8
*status
)
1563 return mthca_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0, mpt_index
,
1564 !mailbox
, CMD_HW2SW_MPT
,
1565 CMD_TIME_CLASS_B
, status
);
1568 int mthca_WRITE_MTT(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1569 int num_mtt
, u8
*status
)
1571 return mthca_cmd(dev
, mailbox
->dma
, num_mtt
, 0, CMD_WRITE_MTT
,
1572 CMD_TIME_CLASS_B
, status
);
1575 int mthca_SYNC_TPT(struct mthca_dev
*dev
, u8
*status
)
1577 return mthca_cmd(dev
, 0, 0, 0, CMD_SYNC_TPT
, CMD_TIME_CLASS_B
, status
);
1580 int mthca_MAP_EQ(struct mthca_dev
*dev
, u64 event_mask
, int unmap
,
1581 int eq_num
, u8
*status
)
1583 mthca_dbg(dev
, "%s mask %016llx for eqn %d\n",
1584 unmap
? "Clearing" : "Setting",
1585 (unsigned long long) event_mask
, eq_num
);
1586 return mthca_cmd(dev
, event_mask
, (unmap
<< 31) | eq_num
,
1587 0, CMD_MAP_EQ
, CMD_TIME_CLASS_B
, status
);
1590 int mthca_SW2HW_EQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1591 int eq_num
, u8
*status
)
1593 return mthca_cmd(dev
, mailbox
->dma
, eq_num
, 0, CMD_SW2HW_EQ
,
1594 CMD_TIME_CLASS_A
, status
);
1597 int mthca_HW2SW_EQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1598 int eq_num
, u8
*status
)
1600 return mthca_cmd_box(dev
, 0, mailbox
->dma
, eq_num
, 0,
1602 CMD_TIME_CLASS_A
, status
);
1605 int mthca_SW2HW_CQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1606 int cq_num
, u8
*status
)
1608 return mthca_cmd(dev
, mailbox
->dma
, cq_num
, 0, CMD_SW2HW_CQ
,
1609 CMD_TIME_CLASS_A
, status
);
1612 int mthca_HW2SW_CQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1613 int cq_num
, u8
*status
)
1615 return mthca_cmd_box(dev
, 0, mailbox
->dma
, cq_num
, 0,
1617 CMD_TIME_CLASS_A
, status
);
1620 int mthca_RESIZE_CQ(struct mthca_dev
*dev
, int cq_num
, u32 lkey
, u8 log_size
,
1623 struct mthca_mailbox
*mailbox
;
1627 #define RESIZE_CQ_IN_SIZE 0x40
1628 #define RESIZE_CQ_LOG_SIZE_OFFSET 0x0c
1629 #define RESIZE_CQ_LKEY_OFFSET 0x1c
1631 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1632 if (IS_ERR(mailbox
))
1633 return PTR_ERR(mailbox
);
1634 inbox
= mailbox
->buf
;
1636 memset(inbox
, 0, RESIZE_CQ_IN_SIZE
);
1638 * Leave start address fields zeroed out -- mthca assumes that
1639 * MRs for CQs always start at virtual address 0.
1641 MTHCA_PUT(inbox
, log_size
, RESIZE_CQ_LOG_SIZE_OFFSET
);
1642 MTHCA_PUT(inbox
, lkey
, RESIZE_CQ_LKEY_OFFSET
);
1644 err
= mthca_cmd(dev
, mailbox
->dma
, cq_num
, 1, CMD_RESIZE_CQ
,
1645 CMD_TIME_CLASS_B
, status
);
1647 mthca_free_mailbox(dev
, mailbox
);
1651 int mthca_SW2HW_SRQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1652 int srq_num
, u8
*status
)
1654 return mthca_cmd(dev
, mailbox
->dma
, srq_num
, 0, CMD_SW2HW_SRQ
,
1655 CMD_TIME_CLASS_A
, status
);
1658 int mthca_HW2SW_SRQ(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1659 int srq_num
, u8
*status
)
1661 return mthca_cmd_box(dev
, 0, mailbox
->dma
, srq_num
, 0,
1663 CMD_TIME_CLASS_A
, status
);
1666 int mthca_QUERY_SRQ(struct mthca_dev
*dev
, u32 num
,
1667 struct mthca_mailbox
*mailbox
, u8
*status
)
1669 return mthca_cmd_box(dev
, 0, mailbox
->dma
, num
, 0,
1670 CMD_QUERY_SRQ
, CMD_TIME_CLASS_A
, status
);
1673 int mthca_ARM_SRQ(struct mthca_dev
*dev
, int srq_num
, int limit
, u8
*status
)
1675 return mthca_cmd(dev
, limit
, srq_num
, 0, CMD_ARM_SRQ
,
1676 CMD_TIME_CLASS_B
, status
);
1679 int mthca_MODIFY_QP(struct mthca_dev
*dev
, enum ib_qp_state cur
,
1680 enum ib_qp_state next
, u32 num
, int is_ee
,
1681 struct mthca_mailbox
*mailbox
, u32 optmask
,
1684 static const u16 op
[IB_QPS_ERR
+ 1][IB_QPS_ERR
+ 1] = {
1686 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1687 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1688 [IB_QPS_INIT
] = CMD_RST2INIT_QPEE
,
1691 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1692 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1693 [IB_QPS_INIT
] = CMD_INIT2INIT_QPEE
,
1694 [IB_QPS_RTR
] = CMD_INIT2RTR_QPEE
,
1697 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1698 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1699 [IB_QPS_RTS
] = CMD_RTR2RTS_QPEE
,
1702 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1703 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1704 [IB_QPS_RTS
] = CMD_RTS2RTS_QPEE
,
1705 [IB_QPS_SQD
] = CMD_RTS2SQD_QPEE
,
1708 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1709 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1710 [IB_QPS_RTS
] = CMD_SQD2RTS_QPEE
,
1711 [IB_QPS_SQD
] = CMD_SQD2SQD_QPEE
,
1714 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1715 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1716 [IB_QPS_RTS
] = CMD_SQERR2RTS_QPEE
,
1719 [IB_QPS_RESET
] = CMD_ERR2RST_QPEE
,
1720 [IB_QPS_ERR
] = CMD_2ERR_QPEE
,
1728 if (op
[cur
][next
] == CMD_ERR2RST_QPEE
) {
1729 op_mod
= 3; /* don't write outbox, any->reset */
1733 mailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1734 if (!IS_ERR(mailbox
)) {
1736 op_mod
= 2; /* write outbox, any->reset */
1741 err
= mthca_cmd_box(dev
, 0, mailbox
? mailbox
->dma
: 0,
1742 (!!is_ee
<< 24) | num
, op_mod
,
1743 op
[cur
][next
], CMD_TIME_CLASS_C
, status
);
1747 mthca_dbg(dev
, "Dumping QP context:\n");
1748 printk(" %08x\n", be32_to_cpup(mailbox
->buf
));
1749 for (i
= 0; i
< 0x100 / 4; ++i
) {
1751 printk("[%02x] ", i
* 4);
1753 be32_to_cpu(((__be32
*) mailbox
->buf
)[i
+ 2]));
1754 if ((i
+ 1) % 8 == 0)
1760 mthca_free_mailbox(dev
, mailbox
);
1764 mthca_dbg(dev
, "Dumping QP context:\n");
1765 printk(" opt param mask: %08x\n", be32_to_cpup(mailbox
->buf
));
1766 for (i
= 0; i
< 0x100 / 4; ++i
) {
1768 printk(" [%02x] ", i
* 4);
1770 be32_to_cpu(((__be32
*) mailbox
->buf
)[i
+ 2]));
1771 if ((i
+ 1) % 8 == 0)
1776 err
= mthca_cmd(dev
, mailbox
->dma
, optmask
| (!!is_ee
<< 24) | num
,
1777 op_mod
, op
[cur
][next
], CMD_TIME_CLASS_C
, status
);
1783 int mthca_QUERY_QP(struct mthca_dev
*dev
, u32 num
, int is_ee
,
1784 struct mthca_mailbox
*mailbox
, u8
*status
)
1786 return mthca_cmd_box(dev
, 0, mailbox
->dma
, (!!is_ee
<< 24) | num
, 0,
1787 CMD_QUERY_QPEE
, CMD_TIME_CLASS_A
, status
);
1790 int mthca_CONF_SPECIAL_QP(struct mthca_dev
*dev
, int type
, u32 qpn
,
1802 case IB_QPT_RAW_IPV6
:
1805 case IB_QPT_RAW_ETY
:
1812 return mthca_cmd(dev
, 0, qpn
, op_mod
, CMD_CONF_SPECIAL_QP
,
1813 CMD_TIME_CLASS_B
, status
);
1816 int mthca_MAD_IFC(struct mthca_dev
*dev
, int ignore_mkey
, int ignore_bkey
,
1817 int port
, struct ib_wc
*in_wc
, struct ib_grh
*in_grh
,
1818 void *in_mad
, void *response_mad
, u8
*status
)
1820 struct mthca_mailbox
*inmailbox
, *outmailbox
;
1823 u32 in_modifier
= port
;
1826 #define MAD_IFC_BOX_SIZE 0x400
1827 #define MAD_IFC_MY_QPN_OFFSET 0x100
1828 #define MAD_IFC_RQPN_OFFSET 0x108
1829 #define MAD_IFC_SL_OFFSET 0x10c
1830 #define MAD_IFC_G_PATH_OFFSET 0x10d
1831 #define MAD_IFC_RLID_OFFSET 0x10e
1832 #define MAD_IFC_PKEY_OFFSET 0x112
1833 #define MAD_IFC_GRH_OFFSET 0x140
1835 inmailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1836 if (IS_ERR(inmailbox
))
1837 return PTR_ERR(inmailbox
);
1838 inbox
= inmailbox
->buf
;
1840 outmailbox
= mthca_alloc_mailbox(dev
, GFP_KERNEL
);
1841 if (IS_ERR(outmailbox
)) {
1842 mthca_free_mailbox(dev
, inmailbox
);
1843 return PTR_ERR(outmailbox
);
1846 memcpy(inbox
, in_mad
, 256);
1849 * Key check traps can't be generated unless we have in_wc to
1850 * tell us where to send the trap.
1852 if (ignore_mkey
|| !in_wc
)
1854 if (ignore_bkey
|| !in_wc
)
1860 memset(inbox
+ 256, 0, 256);
1862 MTHCA_PUT(inbox
, in_wc
->qp
->qp_num
, MAD_IFC_MY_QPN_OFFSET
);
1863 MTHCA_PUT(inbox
, in_wc
->src_qp
, MAD_IFC_RQPN_OFFSET
);
1865 val
= in_wc
->sl
<< 4;
1866 MTHCA_PUT(inbox
, val
, MAD_IFC_SL_OFFSET
);
1868 val
= in_wc
->dlid_path_bits
|
1869 (in_wc
->wc_flags
& IB_WC_GRH
? 0x80 : 0);
1870 MTHCA_PUT(inbox
, val
, MAD_IFC_G_PATH_OFFSET
);
1872 MTHCA_PUT(inbox
, in_wc
->slid
, MAD_IFC_RLID_OFFSET
);
1873 MTHCA_PUT(inbox
, in_wc
->pkey_index
, MAD_IFC_PKEY_OFFSET
);
1876 memcpy(inbox
+ MAD_IFC_GRH_OFFSET
, in_grh
, 40);
1880 in_modifier
|= in_wc
->slid
<< 16;
1883 err
= mthca_cmd_box(dev
, inmailbox
->dma
, outmailbox
->dma
,
1884 in_modifier
, op_modifier
,
1885 CMD_MAD_IFC
, CMD_TIME_CLASS_C
, status
);
1887 if (!err
&& !*status
)
1888 memcpy(response_mad
, outmailbox
->buf
, 256);
1890 mthca_free_mailbox(dev
, inmailbox
);
1891 mthca_free_mailbox(dev
, outmailbox
);
1895 int mthca_READ_MGM(struct mthca_dev
*dev
, int index
,
1896 struct mthca_mailbox
*mailbox
, u8
*status
)
1898 return mthca_cmd_box(dev
, 0, mailbox
->dma
, index
, 0,
1899 CMD_READ_MGM
, CMD_TIME_CLASS_A
, status
);
1902 int mthca_WRITE_MGM(struct mthca_dev
*dev
, int index
,
1903 struct mthca_mailbox
*mailbox
, u8
*status
)
1905 return mthca_cmd(dev
, mailbox
->dma
, index
, 0, CMD_WRITE_MGM
,
1906 CMD_TIME_CLASS_A
, status
);
1909 int mthca_MGID_HASH(struct mthca_dev
*dev
, struct mthca_mailbox
*mailbox
,
1910 u16
*hash
, u8
*status
)
1915 err
= mthca_cmd_imm(dev
, mailbox
->dma
, &imm
, 0, 0, CMD_MGID_HASH
,
1916 CMD_TIME_CLASS_A
, status
);
1922 int mthca_NOP(struct mthca_dev
*dev
, u8
*status
)
1924 return mthca_cmd(dev
, 0, 0x1f, 0, CMD_NOP
, msecs_to_jiffies(100), status
);