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[mirror_ubuntu-artful-kernel.git] / drivers / infiniband / hw / mthca / mthca_mr.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 *
33 * $Id: mthca_mr.c 1349 2004-12-16 21:09:43Z roland $
34 */
35
36 #include <linux/slab.h>
37 #include <linux/errno.h>
38
39 #include "mthca_dev.h"
40 #include "mthca_cmd.h"
41 #include "mthca_memfree.h"
42
43 struct mthca_mtt {
44 struct mthca_buddy *buddy;
45 int order;
46 u32 first_seg;
47 };
48
49 /*
50 * Must be packed because mtt_seg is 64 bits but only aligned to 32 bits.
51 */
52 struct mthca_mpt_entry {
53 __be32 flags;
54 __be32 page_size;
55 __be32 key;
56 __be32 pd;
57 __be64 start;
58 __be64 length;
59 __be32 lkey;
60 __be32 window_count;
61 __be32 window_count_limit;
62 __be64 mtt_seg;
63 __be32 mtt_sz; /* Arbel only */
64 u32 reserved[2];
65 } __attribute__((packed));
66
67 #define MTHCA_MPT_FLAG_SW_OWNS (0xfUL << 28)
68 #define MTHCA_MPT_FLAG_MIO (1 << 17)
69 #define MTHCA_MPT_FLAG_BIND_ENABLE (1 << 15)
70 #define MTHCA_MPT_FLAG_PHYSICAL (1 << 9)
71 #define MTHCA_MPT_FLAG_REGION (1 << 8)
72
73 #define MTHCA_MTT_FLAG_PRESENT 1
74
75 #define MTHCA_MPT_STATUS_SW 0xF0
76 #define MTHCA_MPT_STATUS_HW 0x00
77
78 #define SINAI_FMR_KEY_INC 0x1000000
79
80 /*
81 * Buddy allocator for MTT segments (currently not very efficient
82 * since it doesn't keep a free list and just searches linearly
83 * through the bitmaps)
84 */
85
86 static u32 mthca_buddy_alloc(struct mthca_buddy *buddy, int order)
87 {
88 int o;
89 int m;
90 u32 seg;
91
92 spin_lock(&buddy->lock);
93
94 for (o = order; o <= buddy->max_order; ++o) {
95 m = 1 << (buddy->max_order - o);
96 seg = find_first_bit(buddy->bits[o], m);
97 if (seg < m)
98 goto found;
99 }
100
101 spin_unlock(&buddy->lock);
102 return -1;
103
104 found:
105 clear_bit(seg, buddy->bits[o]);
106
107 while (o > order) {
108 --o;
109 seg <<= 1;
110 set_bit(seg ^ 1, buddy->bits[o]);
111 }
112
113 spin_unlock(&buddy->lock);
114
115 seg <<= order;
116
117 return seg;
118 }
119
120 static void mthca_buddy_free(struct mthca_buddy *buddy, u32 seg, int order)
121 {
122 seg >>= order;
123
124 spin_lock(&buddy->lock);
125
126 while (test_bit(seg ^ 1, buddy->bits[order])) {
127 clear_bit(seg ^ 1, buddy->bits[order]);
128 seg >>= 1;
129 ++order;
130 }
131
132 set_bit(seg, buddy->bits[order]);
133
134 spin_unlock(&buddy->lock);
135 }
136
137 static int mthca_buddy_init(struct mthca_buddy *buddy, int max_order)
138 {
139 int i, s;
140
141 buddy->max_order = max_order;
142 spin_lock_init(&buddy->lock);
143
144 buddy->bits = kzalloc((buddy->max_order + 1) * sizeof (long *),
145 GFP_KERNEL);
146 if (!buddy->bits)
147 goto err_out;
148
149 for (i = 0; i <= buddy->max_order; ++i) {
150 s = BITS_TO_LONGS(1 << (buddy->max_order - i));
151 buddy->bits[i] = kmalloc(s * sizeof (long), GFP_KERNEL);
152 if (!buddy->bits[i])
153 goto err_out_free;
154 bitmap_zero(buddy->bits[i],
155 1 << (buddy->max_order - i));
156 }
157
158 set_bit(0, buddy->bits[buddy->max_order]);
159
160 return 0;
161
162 err_out_free:
163 for (i = 0; i <= buddy->max_order; ++i)
164 kfree(buddy->bits[i]);
165
166 kfree(buddy->bits);
167
168 err_out:
169 return -ENOMEM;
170 }
171
172 static void mthca_buddy_cleanup(struct mthca_buddy *buddy)
173 {
174 int i;
175
176 for (i = 0; i <= buddy->max_order; ++i)
177 kfree(buddy->bits[i]);
178
179 kfree(buddy->bits);
180 }
181
182 static u32 mthca_alloc_mtt_range(struct mthca_dev *dev, int order,
183 struct mthca_buddy *buddy)
184 {
185 u32 seg = mthca_buddy_alloc(buddy, order);
186
187 if (seg == -1)
188 return -1;
189
190 if (mthca_is_memfree(dev))
191 if (mthca_table_get_range(dev, dev->mr_table.mtt_table, seg,
192 seg + (1 << order) - 1)) {
193 mthca_buddy_free(buddy, seg, order);
194 seg = -1;
195 }
196
197 return seg;
198 }
199
200 static struct mthca_mtt *__mthca_alloc_mtt(struct mthca_dev *dev, int size,
201 struct mthca_buddy *buddy)
202 {
203 struct mthca_mtt *mtt;
204 int i;
205
206 if (size <= 0)
207 return ERR_PTR(-EINVAL);
208
209 mtt = kmalloc(sizeof *mtt, GFP_KERNEL);
210 if (!mtt)
211 return ERR_PTR(-ENOMEM);
212
213 mtt->buddy = buddy;
214 mtt->order = 0;
215 for (i = MTHCA_MTT_SEG_SIZE / 8; i < size; i <<= 1)
216 ++mtt->order;
217
218 mtt->first_seg = mthca_alloc_mtt_range(dev, mtt->order, buddy);
219 if (mtt->first_seg == -1) {
220 kfree(mtt);
221 return ERR_PTR(-ENOMEM);
222 }
223
224 return mtt;
225 }
226
227 struct mthca_mtt *mthca_alloc_mtt(struct mthca_dev *dev, int size)
228 {
229 return __mthca_alloc_mtt(dev, size, &dev->mr_table.mtt_buddy);
230 }
231
232 void mthca_free_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt)
233 {
234 if (!mtt)
235 return;
236
237 mthca_buddy_free(mtt->buddy, mtt->first_seg, mtt->order);
238
239 mthca_table_put_range(dev, dev->mr_table.mtt_table,
240 mtt->first_seg,
241 mtt->first_seg + (1 << mtt->order) - 1);
242
243 kfree(mtt);
244 }
245
246 int mthca_write_mtt(struct mthca_dev *dev, struct mthca_mtt *mtt,
247 int start_index, u64 *buffer_list, int list_len)
248 {
249 struct mthca_mailbox *mailbox;
250 __be64 *mtt_entry;
251 int err = 0;
252 u8 status;
253 int i;
254
255 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
256 if (IS_ERR(mailbox))
257 return PTR_ERR(mailbox);
258 mtt_entry = mailbox->buf;
259
260 while (list_len > 0) {
261 mtt_entry[0] = cpu_to_be64(dev->mr_table.mtt_base +
262 mtt->first_seg * MTHCA_MTT_SEG_SIZE +
263 start_index * 8);
264 mtt_entry[1] = 0;
265 for (i = 0; i < list_len && i < MTHCA_MAILBOX_SIZE / 8 - 2; ++i)
266 mtt_entry[i + 2] = cpu_to_be64(buffer_list[i] |
267 MTHCA_MTT_FLAG_PRESENT);
268
269 /*
270 * If we have an odd number of entries to write, add
271 * one more dummy entry for firmware efficiency.
272 */
273 if (i & 1)
274 mtt_entry[i + 2] = 0;
275
276 err = mthca_WRITE_MTT(dev, mailbox, (i + 1) & ~1, &status);
277 if (err) {
278 mthca_warn(dev, "WRITE_MTT failed (%d)\n", err);
279 goto out;
280 }
281 if (status) {
282 mthca_warn(dev, "WRITE_MTT returned status 0x%02x\n",
283 status);
284 err = -EINVAL;
285 goto out;
286 }
287
288 list_len -= i;
289 start_index += i;
290 buffer_list += i;
291 }
292
293 out:
294 mthca_free_mailbox(dev, mailbox);
295 return err;
296 }
297
298 static inline u32 tavor_hw_index_to_key(u32 ind)
299 {
300 return ind;
301 }
302
303 static inline u32 tavor_key_to_hw_index(u32 key)
304 {
305 return key;
306 }
307
308 static inline u32 arbel_hw_index_to_key(u32 ind)
309 {
310 return (ind >> 24) | (ind << 8);
311 }
312
313 static inline u32 arbel_key_to_hw_index(u32 key)
314 {
315 return (key << 24) | (key >> 8);
316 }
317
318 static inline u32 hw_index_to_key(struct mthca_dev *dev, u32 ind)
319 {
320 if (mthca_is_memfree(dev))
321 return arbel_hw_index_to_key(ind);
322 else
323 return tavor_hw_index_to_key(ind);
324 }
325
326 static inline u32 key_to_hw_index(struct mthca_dev *dev, u32 key)
327 {
328 if (mthca_is_memfree(dev))
329 return arbel_key_to_hw_index(key);
330 else
331 return tavor_key_to_hw_index(key);
332 }
333
334 static inline u32 adjust_key(struct mthca_dev *dev, u32 key)
335 {
336 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
337 return ((key << 20) & 0x800000) | (key & 0x7fffff);
338 else
339 return key;
340 }
341
342 int mthca_mr_alloc(struct mthca_dev *dev, u32 pd, int buffer_size_shift,
343 u64 iova, u64 total_size, u32 access, struct mthca_mr *mr)
344 {
345 struct mthca_mailbox *mailbox;
346 struct mthca_mpt_entry *mpt_entry;
347 u32 key;
348 int i;
349 int err;
350 u8 status;
351
352 WARN_ON(buffer_size_shift >= 32);
353
354 key = mthca_alloc(&dev->mr_table.mpt_alloc);
355 if (key == -1)
356 return -ENOMEM;
357 key = adjust_key(dev, key);
358 mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
359
360 if (mthca_is_memfree(dev)) {
361 err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
362 if (err)
363 goto err_out_mpt_free;
364 }
365
366 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
367 if (IS_ERR(mailbox)) {
368 err = PTR_ERR(mailbox);
369 goto err_out_table;
370 }
371 mpt_entry = mailbox->buf;
372
373 mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
374 MTHCA_MPT_FLAG_MIO |
375 MTHCA_MPT_FLAG_REGION |
376 access);
377 if (!mr->mtt)
378 mpt_entry->flags |= cpu_to_be32(MTHCA_MPT_FLAG_PHYSICAL);
379
380 mpt_entry->page_size = cpu_to_be32(buffer_size_shift - 12);
381 mpt_entry->key = cpu_to_be32(key);
382 mpt_entry->pd = cpu_to_be32(pd);
383 mpt_entry->start = cpu_to_be64(iova);
384 mpt_entry->length = cpu_to_be64(total_size);
385
386 memset(&mpt_entry->lkey, 0,
387 sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, lkey));
388
389 if (mr->mtt)
390 mpt_entry->mtt_seg =
391 cpu_to_be64(dev->mr_table.mtt_base +
392 mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE);
393
394 if (0) {
395 mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
396 for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
397 if (i % 4 == 0)
398 printk("[%02x] ", i * 4);
399 printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
400 if ((i + 1) % 4 == 0)
401 printk("\n");
402 }
403 }
404
405 err = mthca_SW2HW_MPT(dev, mailbox,
406 key & (dev->limits.num_mpts - 1),
407 &status);
408 if (err) {
409 mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
410 goto err_out_mailbox;
411 } else if (status) {
412 mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
413 status);
414 err = -EINVAL;
415 goto err_out_mailbox;
416 }
417
418 mthca_free_mailbox(dev, mailbox);
419 return err;
420
421 err_out_mailbox:
422 mthca_free_mailbox(dev, mailbox);
423
424 err_out_table:
425 mthca_table_put(dev, dev->mr_table.mpt_table, key);
426
427 err_out_mpt_free:
428 mthca_free(&dev->mr_table.mpt_alloc, key);
429 return err;
430 }
431
432 int mthca_mr_alloc_notrans(struct mthca_dev *dev, u32 pd,
433 u32 access, struct mthca_mr *mr)
434 {
435 mr->mtt = NULL;
436 return mthca_mr_alloc(dev, pd, 12, 0, ~0ULL, access, mr);
437 }
438
439 int mthca_mr_alloc_phys(struct mthca_dev *dev, u32 pd,
440 u64 *buffer_list, int buffer_size_shift,
441 int list_len, u64 iova, u64 total_size,
442 u32 access, struct mthca_mr *mr)
443 {
444 int err;
445
446 mr->mtt = mthca_alloc_mtt(dev, list_len);
447 if (IS_ERR(mr->mtt))
448 return PTR_ERR(mr->mtt);
449
450 err = mthca_write_mtt(dev, mr->mtt, 0, buffer_list, list_len);
451 if (err) {
452 mthca_free_mtt(dev, mr->mtt);
453 return err;
454 }
455
456 err = mthca_mr_alloc(dev, pd, buffer_size_shift, iova,
457 total_size, access, mr);
458 if (err)
459 mthca_free_mtt(dev, mr->mtt);
460
461 return err;
462 }
463
464 /* Free mr or fmr */
465 static void mthca_free_region(struct mthca_dev *dev, u32 lkey)
466 {
467 mthca_table_put(dev, dev->mr_table.mpt_table,
468 key_to_hw_index(dev, lkey));
469
470 mthca_free(&dev->mr_table.mpt_alloc, key_to_hw_index(dev, lkey));
471 }
472
473 void mthca_free_mr(struct mthca_dev *dev, struct mthca_mr *mr)
474 {
475 int err;
476 u8 status;
477
478 err = mthca_HW2SW_MPT(dev, NULL,
479 key_to_hw_index(dev, mr->ibmr.lkey) &
480 (dev->limits.num_mpts - 1),
481 &status);
482 if (err)
483 mthca_warn(dev, "HW2SW_MPT failed (%d)\n", err);
484 else if (status)
485 mthca_warn(dev, "HW2SW_MPT returned status 0x%02x\n",
486 status);
487
488 mthca_free_region(dev, mr->ibmr.lkey);
489 mthca_free_mtt(dev, mr->mtt);
490 }
491
492 int mthca_fmr_alloc(struct mthca_dev *dev, u32 pd,
493 u32 access, struct mthca_fmr *mr)
494 {
495 struct mthca_mpt_entry *mpt_entry;
496 struct mthca_mailbox *mailbox;
497 u64 mtt_seg;
498 u32 key, idx;
499 u8 status;
500 int list_len = mr->attr.max_pages;
501 int err = -ENOMEM;
502 int i;
503
504 if (mr->attr.page_shift < 12 || mr->attr.page_shift >= 32)
505 return -EINVAL;
506
507 /* For Arbel, all MTTs must fit in the same page. */
508 if (mthca_is_memfree(dev) &&
509 mr->attr.max_pages * sizeof *mr->mem.arbel.mtts > PAGE_SIZE)
510 return -EINVAL;
511
512 mr->maps = 0;
513
514 key = mthca_alloc(&dev->mr_table.mpt_alloc);
515 if (key == -1)
516 return -ENOMEM;
517 key = adjust_key(dev, key);
518
519 idx = key & (dev->limits.num_mpts - 1);
520 mr->ibmr.rkey = mr->ibmr.lkey = hw_index_to_key(dev, key);
521
522 if (mthca_is_memfree(dev)) {
523 err = mthca_table_get(dev, dev->mr_table.mpt_table, key);
524 if (err)
525 goto err_out_mpt_free;
526
527 mr->mem.arbel.mpt = mthca_table_find(dev->mr_table.mpt_table, key, NULL);
528 BUG_ON(!mr->mem.arbel.mpt);
529 } else
530 mr->mem.tavor.mpt = dev->mr_table.tavor_fmr.mpt_base +
531 sizeof *(mr->mem.tavor.mpt) * idx;
532
533 mr->mtt = __mthca_alloc_mtt(dev, list_len, dev->mr_table.fmr_mtt_buddy);
534 if (IS_ERR(mr->mtt))
535 goto err_out_table;
536
537 mtt_seg = mr->mtt->first_seg * MTHCA_MTT_SEG_SIZE;
538
539 if (mthca_is_memfree(dev)) {
540 mr->mem.arbel.mtts = mthca_table_find(dev->mr_table.mtt_table,
541 mr->mtt->first_seg,
542 &mr->mem.arbel.dma_handle);
543 BUG_ON(!mr->mem.arbel.mtts);
544 } else
545 mr->mem.tavor.mtts = dev->mr_table.tavor_fmr.mtt_base + mtt_seg;
546
547 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
548 if (IS_ERR(mailbox))
549 goto err_out_free_mtt;
550
551 mpt_entry = mailbox->buf;
552
553 mpt_entry->flags = cpu_to_be32(MTHCA_MPT_FLAG_SW_OWNS |
554 MTHCA_MPT_FLAG_MIO |
555 MTHCA_MPT_FLAG_REGION |
556 access);
557
558 mpt_entry->page_size = cpu_to_be32(mr->attr.page_shift - 12);
559 mpt_entry->key = cpu_to_be32(key);
560 mpt_entry->pd = cpu_to_be32(pd);
561 memset(&mpt_entry->start, 0,
562 sizeof *mpt_entry - offsetof(struct mthca_mpt_entry, start));
563 mpt_entry->mtt_seg = cpu_to_be64(dev->mr_table.mtt_base + mtt_seg);
564
565 if (0) {
566 mthca_dbg(dev, "Dumping MPT entry %08x:\n", mr->ibmr.lkey);
567 for (i = 0; i < sizeof (struct mthca_mpt_entry) / 4; ++i) {
568 if (i % 4 == 0)
569 printk("[%02x] ", i * 4);
570 printk(" %08x", be32_to_cpu(((__be32 *) mpt_entry)[i]));
571 if ((i + 1) % 4 == 0)
572 printk("\n");
573 }
574 }
575
576 err = mthca_SW2HW_MPT(dev, mailbox,
577 key & (dev->limits.num_mpts - 1),
578 &status);
579 if (err) {
580 mthca_warn(dev, "SW2HW_MPT failed (%d)\n", err);
581 goto err_out_mailbox_free;
582 }
583 if (status) {
584 mthca_warn(dev, "SW2HW_MPT returned status 0x%02x\n",
585 status);
586 err = -EINVAL;
587 goto err_out_mailbox_free;
588 }
589
590 mthca_free_mailbox(dev, mailbox);
591 return 0;
592
593 err_out_mailbox_free:
594 mthca_free_mailbox(dev, mailbox);
595
596 err_out_free_mtt:
597 mthca_free_mtt(dev, mr->mtt);
598
599 err_out_table:
600 mthca_table_put(dev, dev->mr_table.mpt_table, key);
601
602 err_out_mpt_free:
603 mthca_free(&dev->mr_table.mpt_alloc, mr->ibmr.lkey);
604 return err;
605 }
606
607 int mthca_free_fmr(struct mthca_dev *dev, struct mthca_fmr *fmr)
608 {
609 if (fmr->maps)
610 return -EBUSY;
611
612 mthca_free_region(dev, fmr->ibmr.lkey);
613 mthca_free_mtt(dev, fmr->mtt);
614
615 return 0;
616 }
617
618 static inline int mthca_check_fmr(struct mthca_fmr *fmr, u64 *page_list,
619 int list_len, u64 iova)
620 {
621 int i, page_mask;
622
623 if (list_len > fmr->attr.max_pages)
624 return -EINVAL;
625
626 page_mask = (1 << fmr->attr.page_shift) - 1;
627
628 /* We are getting page lists, so va must be page aligned. */
629 if (iova & page_mask)
630 return -EINVAL;
631
632 /* Trust the user not to pass misaligned data in page_list */
633 if (0)
634 for (i = 0; i < list_len; ++i) {
635 if (page_list[i] & ~page_mask)
636 return -EINVAL;
637 }
638
639 if (fmr->maps >= fmr->attr.max_maps)
640 return -EINVAL;
641
642 return 0;
643 }
644
645
646 int mthca_tavor_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
647 int list_len, u64 iova)
648 {
649 struct mthca_fmr *fmr = to_mfmr(ibfmr);
650 struct mthca_dev *dev = to_mdev(ibfmr->device);
651 struct mthca_mpt_entry mpt_entry;
652 u32 key;
653 int i, err;
654
655 err = mthca_check_fmr(fmr, page_list, list_len, iova);
656 if (err)
657 return err;
658
659 ++fmr->maps;
660
661 key = tavor_key_to_hw_index(fmr->ibmr.lkey);
662 key += dev->limits.num_mpts;
663 fmr->ibmr.lkey = fmr->ibmr.rkey = tavor_hw_index_to_key(key);
664
665 writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
666
667 for (i = 0; i < list_len; ++i) {
668 __be64 mtt_entry = cpu_to_be64(page_list[i] |
669 MTHCA_MTT_FLAG_PRESENT);
670 mthca_write64_raw(mtt_entry, fmr->mem.tavor.mtts + i);
671 }
672
673 mpt_entry.lkey = cpu_to_be32(key);
674 mpt_entry.length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
675 mpt_entry.start = cpu_to_be64(iova);
676
677 __raw_writel((__force u32) mpt_entry.lkey, &fmr->mem.tavor.mpt->key);
678 memcpy_toio(&fmr->mem.tavor.mpt->start, &mpt_entry.start,
679 offsetof(struct mthca_mpt_entry, window_count) -
680 offsetof(struct mthca_mpt_entry, start));
681
682 writeb(MTHCA_MPT_STATUS_HW, fmr->mem.tavor.mpt);
683
684 return 0;
685 }
686
687 int mthca_arbel_map_phys_fmr(struct ib_fmr *ibfmr, u64 *page_list,
688 int list_len, u64 iova)
689 {
690 struct mthca_fmr *fmr = to_mfmr(ibfmr);
691 struct mthca_dev *dev = to_mdev(ibfmr->device);
692 u32 key;
693 int i, err;
694
695 err = mthca_check_fmr(fmr, page_list, list_len, iova);
696 if (err)
697 return err;
698
699 ++fmr->maps;
700
701 key = arbel_key_to_hw_index(fmr->ibmr.lkey);
702 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
703 key += SINAI_FMR_KEY_INC;
704 else
705 key += dev->limits.num_mpts;
706 fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
707
708 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
709
710 wmb();
711
712 for (i = 0; i < list_len; ++i)
713 fmr->mem.arbel.mtts[i] = cpu_to_be64(page_list[i] |
714 MTHCA_MTT_FLAG_PRESENT);
715
716 dma_sync_single(&dev->pdev->dev, fmr->mem.arbel.dma_handle,
717 list_len * sizeof(u64), DMA_TO_DEVICE);
718
719 fmr->mem.arbel.mpt->key = cpu_to_be32(key);
720 fmr->mem.arbel.mpt->lkey = cpu_to_be32(key);
721 fmr->mem.arbel.mpt->length = cpu_to_be64(list_len * (1ull << fmr->attr.page_shift));
722 fmr->mem.arbel.mpt->start = cpu_to_be64(iova);
723
724 wmb();
725
726 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_HW;
727
728 wmb();
729
730 return 0;
731 }
732
733 void mthca_tavor_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
734 {
735 u32 key;
736
737 if (!fmr->maps)
738 return;
739
740 key = tavor_key_to_hw_index(fmr->ibmr.lkey);
741 key &= dev->limits.num_mpts - 1;
742 fmr->ibmr.lkey = fmr->ibmr.rkey = tavor_hw_index_to_key(key);
743
744 fmr->maps = 0;
745
746 writeb(MTHCA_MPT_STATUS_SW, fmr->mem.tavor.mpt);
747 }
748
749 void mthca_arbel_fmr_unmap(struct mthca_dev *dev, struct mthca_fmr *fmr)
750 {
751 u32 key;
752
753 if (!fmr->maps)
754 return;
755
756 key = arbel_key_to_hw_index(fmr->ibmr.lkey);
757 key &= dev->limits.num_mpts - 1;
758 fmr->ibmr.lkey = fmr->ibmr.rkey = arbel_hw_index_to_key(key);
759
760 fmr->maps = 0;
761
762 *(u8 *) fmr->mem.arbel.mpt = MTHCA_MPT_STATUS_SW;
763 }
764
765 int mthca_init_mr_table(struct mthca_dev *dev)
766 {
767 unsigned long addr;
768 int err, i;
769
770 err = mthca_alloc_init(&dev->mr_table.mpt_alloc,
771 dev->limits.num_mpts,
772 ~0, dev->limits.reserved_mrws);
773 if (err)
774 return err;
775
776 if (!mthca_is_memfree(dev) &&
777 (dev->mthca_flags & MTHCA_FLAG_DDR_HIDDEN))
778 dev->limits.fmr_reserved_mtts = 0;
779 else
780 dev->mthca_flags |= MTHCA_FLAG_FMR;
781
782 if (dev->mthca_flags & MTHCA_FLAG_SINAI_OPT)
783 mthca_dbg(dev, "Memory key throughput optimization activated.\n");
784
785 err = mthca_buddy_init(&dev->mr_table.mtt_buddy,
786 fls(dev->limits.num_mtt_segs - 1));
787
788 if (err)
789 goto err_mtt_buddy;
790
791 dev->mr_table.tavor_fmr.mpt_base = NULL;
792 dev->mr_table.tavor_fmr.mtt_base = NULL;
793
794 if (dev->limits.fmr_reserved_mtts) {
795 i = fls(dev->limits.fmr_reserved_mtts - 1);
796
797 if (i >= 31) {
798 mthca_warn(dev, "Unable to reserve 2^31 FMR MTTs.\n");
799 err = -EINVAL;
800 goto err_fmr_mpt;
801 }
802
803 addr = pci_resource_start(dev->pdev, 4) +
804 ((pci_resource_len(dev->pdev, 4) - 1) &
805 dev->mr_table.mpt_base);
806
807 dev->mr_table.tavor_fmr.mpt_base =
808 ioremap(addr, (1 << i) * sizeof(struct mthca_mpt_entry));
809
810 if (!dev->mr_table.tavor_fmr.mpt_base) {
811 mthca_warn(dev, "MPT ioremap for FMR failed.\n");
812 err = -ENOMEM;
813 goto err_fmr_mpt;
814 }
815
816 addr = pci_resource_start(dev->pdev, 4) +
817 ((pci_resource_len(dev->pdev, 4) - 1) &
818 dev->mr_table.mtt_base);
819
820 dev->mr_table.tavor_fmr.mtt_base =
821 ioremap(addr, (1 << i) * MTHCA_MTT_SEG_SIZE);
822 if (!dev->mr_table.tavor_fmr.mtt_base) {
823 mthca_warn(dev, "MTT ioremap for FMR failed.\n");
824 err = -ENOMEM;
825 goto err_fmr_mtt;
826 }
827
828 err = mthca_buddy_init(&dev->mr_table.tavor_fmr.mtt_buddy, i);
829 if (err)
830 goto err_fmr_mtt_buddy;
831
832 /* Prevent regular MRs from using FMR keys */
833 err = mthca_buddy_alloc(&dev->mr_table.mtt_buddy, i);
834 if (err)
835 goto err_reserve_fmr;
836
837 dev->mr_table.fmr_mtt_buddy =
838 &dev->mr_table.tavor_fmr.mtt_buddy;
839 } else
840 dev->mr_table.fmr_mtt_buddy = &dev->mr_table.mtt_buddy;
841
842 /* FMR table is always the first, take reserved MTTs out of there */
843 if (dev->limits.reserved_mtts) {
844 i = fls(dev->limits.reserved_mtts - 1);
845
846 if (mthca_alloc_mtt_range(dev, i,
847 dev->mr_table.fmr_mtt_buddy) == -1) {
848 mthca_warn(dev, "MTT table of order %d is too small.\n",
849 dev->mr_table.fmr_mtt_buddy->max_order);
850 err = -ENOMEM;
851 goto err_reserve_mtts;
852 }
853 }
854
855 return 0;
856
857 err_reserve_mtts:
858 err_reserve_fmr:
859 if (dev->limits.fmr_reserved_mtts)
860 mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
861
862 err_fmr_mtt_buddy:
863 if (dev->mr_table.tavor_fmr.mtt_base)
864 iounmap(dev->mr_table.tavor_fmr.mtt_base);
865
866 err_fmr_mtt:
867 if (dev->mr_table.tavor_fmr.mpt_base)
868 iounmap(dev->mr_table.tavor_fmr.mpt_base);
869
870 err_fmr_mpt:
871 mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
872
873 err_mtt_buddy:
874 mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
875
876 return err;
877 }
878
879 void mthca_cleanup_mr_table(struct mthca_dev *dev)
880 {
881 /* XXX check if any MRs are still allocated? */
882 if (dev->limits.fmr_reserved_mtts)
883 mthca_buddy_cleanup(&dev->mr_table.tavor_fmr.mtt_buddy);
884
885 mthca_buddy_cleanup(&dev->mr_table.mtt_buddy);
886
887 if (dev->mr_table.tavor_fmr.mtt_base)
888 iounmap(dev->mr_table.tavor_fmr.mtt_base);
889 if (dev->mr_table.tavor_fmr.mpt_base)
890 iounmap(dev->mr_table.tavor_fmr.mpt_base);
891
892 mthca_alloc_cleanup(&dev->mr_table.mpt_alloc);
893 }
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