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[mirror_ubuntu-kernels.git] / drivers / infiniband / hw / mthca / mthca_qp.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45
46 #include "mthca_dev.h"
47 #include "mthca_cmd.h"
48 #include "mthca_memfree.h"
49 #include "mthca_wqe.h"
50
51 enum {
52 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
53 MTHCA_ACK_REQ_FREQ = 10,
54 MTHCA_FLIGHT_LIMIT = 9,
55 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
56 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
57 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
58 };
59
60 enum {
61 MTHCA_QP_STATE_RST = 0,
62 MTHCA_QP_STATE_INIT = 1,
63 MTHCA_QP_STATE_RTR = 2,
64 MTHCA_QP_STATE_RTS = 3,
65 MTHCA_QP_STATE_SQE = 4,
66 MTHCA_QP_STATE_SQD = 5,
67 MTHCA_QP_STATE_ERR = 6,
68 MTHCA_QP_STATE_DRAINING = 7
69 };
70
71 enum {
72 MTHCA_QP_ST_RC = 0x0,
73 MTHCA_QP_ST_UC = 0x1,
74 MTHCA_QP_ST_RD = 0x2,
75 MTHCA_QP_ST_UD = 0x3,
76 MTHCA_QP_ST_MLX = 0x7
77 };
78
79 enum {
80 MTHCA_QP_PM_MIGRATED = 0x3,
81 MTHCA_QP_PM_ARMED = 0x0,
82 MTHCA_QP_PM_REARM = 0x1
83 };
84
85 enum {
86 /* qp_context flags */
87 MTHCA_QP_BIT_DE = 1 << 8,
88 /* params1 */
89 MTHCA_QP_BIT_SRE = 1 << 15,
90 MTHCA_QP_BIT_SWE = 1 << 14,
91 MTHCA_QP_BIT_SAE = 1 << 13,
92 MTHCA_QP_BIT_SIC = 1 << 4,
93 MTHCA_QP_BIT_SSC = 1 << 3,
94 /* params2 */
95 MTHCA_QP_BIT_RRE = 1 << 15,
96 MTHCA_QP_BIT_RWE = 1 << 14,
97 MTHCA_QP_BIT_RAE = 1 << 13,
98 MTHCA_QP_BIT_RIC = 1 << 4,
99 MTHCA_QP_BIT_RSC = 1 << 3
100 };
101
102 enum {
103 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
104 };
105
106 struct mthca_qp_path {
107 __be32 port_pkey;
108 u8 rnr_retry;
109 u8 g_mylmc;
110 __be16 rlid;
111 u8 ackto;
112 u8 mgid_index;
113 u8 static_rate;
114 u8 hop_limit;
115 __be32 sl_tclass_flowlabel;
116 u8 rgid[16];
117 } __attribute__((packed));
118
119 struct mthca_qp_context {
120 __be32 flags;
121 __be32 tavor_sched_queue; /* Reserved on Arbel */
122 u8 mtu_msgmax;
123 u8 rq_size_stride; /* Reserved on Tavor */
124 u8 sq_size_stride; /* Reserved on Tavor */
125 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
126 __be32 usr_page;
127 __be32 local_qpn;
128 __be32 remote_qpn;
129 u32 reserved1[2];
130 struct mthca_qp_path pri_path;
131 struct mthca_qp_path alt_path;
132 __be32 rdd;
133 __be32 pd;
134 __be32 wqe_base;
135 __be32 wqe_lkey;
136 __be32 params1;
137 __be32 reserved2;
138 __be32 next_send_psn;
139 __be32 cqn_snd;
140 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
141 __be32 snd_db_index; /* (debugging only entries) */
142 __be32 last_acked_psn;
143 __be32 ssn;
144 __be32 params2;
145 __be32 rnr_nextrecvpsn;
146 __be32 ra_buff_indx;
147 __be32 cqn_rcv;
148 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
149 __be32 rcv_db_index; /* (debugging only entries) */
150 __be32 qkey;
151 __be32 srqn;
152 __be32 rmsn;
153 __be16 rq_wqe_counter; /* reserved on Tavor */
154 __be16 sq_wqe_counter; /* reserved on Tavor */
155 u32 reserved3[18];
156 } __attribute__((packed));
157
158 struct mthca_qp_param {
159 __be32 opt_param_mask;
160 u32 reserved1;
161 struct mthca_qp_context context;
162 u32 reserved2[62];
163 } __attribute__((packed));
164
165 enum {
166 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
167 MTHCA_QP_OPTPAR_RRE = 1 << 1,
168 MTHCA_QP_OPTPAR_RAE = 1 << 2,
169 MTHCA_QP_OPTPAR_RWE = 1 << 3,
170 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
171 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
172 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
173 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
174 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
175 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
176 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
177 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
178 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
179 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
180 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
181 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
182 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
183 };
184
185 static const u8 mthca_opcode[] = {
186 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
187 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
188 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
189 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
190 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
191 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
192 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
193 };
194
195 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
196 {
197 return qp->qpn >= dev->qp_table.sqp_start &&
198 qp->qpn <= dev->qp_table.sqp_start + 3;
199 }
200
201 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
202 {
203 return qp->qpn >= dev->qp_table.sqp_start &&
204 qp->qpn <= dev->qp_table.sqp_start + 1;
205 }
206
207 static void *get_recv_wqe(struct mthca_qp *qp, int n)
208 {
209 if (qp->is_direct)
210 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
211 else
212 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
213 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
214 }
215
216 static void *get_send_wqe(struct mthca_qp *qp, int n)
217 {
218 if (qp->is_direct)
219 return qp->queue.direct.buf + qp->send_wqe_offset +
220 (n << qp->sq.wqe_shift);
221 else
222 return qp->queue.page_list[(qp->send_wqe_offset +
223 (n << qp->sq.wqe_shift)) >>
224 PAGE_SHIFT].buf +
225 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
226 (PAGE_SIZE - 1));
227 }
228
229 static void mthca_wq_reset(struct mthca_wq *wq)
230 {
231 wq->next_ind = 0;
232 wq->last_comp = wq->max - 1;
233 wq->head = 0;
234 wq->tail = 0;
235 }
236
237 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
238 enum ib_event_type event_type)
239 {
240 struct mthca_qp *qp;
241 struct ib_event event;
242
243 spin_lock(&dev->qp_table.lock);
244 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
245 if (qp)
246 ++qp->refcount;
247 spin_unlock(&dev->qp_table.lock);
248
249 if (!qp) {
250 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
251 event_type, qpn);
252 return;
253 }
254
255 if (event_type == IB_EVENT_PATH_MIG)
256 qp->port = qp->alt_port;
257
258 event.device = &dev->ib_dev;
259 event.event = event_type;
260 event.element.qp = &qp->ibqp;
261 if (qp->ibqp.event_handler)
262 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
263
264 spin_lock(&dev->qp_table.lock);
265 if (!--qp->refcount)
266 wake_up(&qp->wait);
267 spin_unlock(&dev->qp_table.lock);
268 }
269
270 static int to_mthca_state(enum ib_qp_state ib_state)
271 {
272 switch (ib_state) {
273 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
274 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
275 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
276 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
277 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
278 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
279 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
280 default: return -1;
281 }
282 }
283
284 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
285
286 static int to_mthca_st(int transport)
287 {
288 switch (transport) {
289 case RC: return MTHCA_QP_ST_RC;
290 case UC: return MTHCA_QP_ST_UC;
291 case UD: return MTHCA_QP_ST_UD;
292 case RD: return MTHCA_QP_ST_RD;
293 case MLX: return MTHCA_QP_ST_MLX;
294 default: return -1;
295 }
296 }
297
298 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
299 int attr_mask)
300 {
301 if (attr_mask & IB_QP_PKEY_INDEX)
302 sqp->pkey_index = attr->pkey_index;
303 if (attr_mask & IB_QP_QKEY)
304 sqp->qkey = attr->qkey;
305 if (attr_mask & IB_QP_SQ_PSN)
306 sqp->send_psn = attr->sq_psn;
307 }
308
309 static void init_port(struct mthca_dev *dev, int port)
310 {
311 int err;
312 struct mthca_init_ib_param param;
313
314 memset(&param, 0, sizeof param);
315
316 param.port_width = dev->limits.port_width_cap;
317 param.vl_cap = dev->limits.vl_cap;
318 param.mtu_cap = dev->limits.mtu_cap;
319 param.gid_cap = dev->limits.gid_table_len;
320 param.pkey_cap = dev->limits.pkey_table_len;
321
322 err = mthca_INIT_IB(dev, &param, port);
323 if (err)
324 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
325 }
326
327 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
328 int attr_mask)
329 {
330 u8 dest_rd_atomic;
331 u32 access_flags;
332 u32 hw_access_flags = 0;
333
334 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
335 dest_rd_atomic = attr->max_dest_rd_atomic;
336 else
337 dest_rd_atomic = qp->resp_depth;
338
339 if (attr_mask & IB_QP_ACCESS_FLAGS)
340 access_flags = attr->qp_access_flags;
341 else
342 access_flags = qp->atomic_rd_en;
343
344 if (!dest_rd_atomic)
345 access_flags &= IB_ACCESS_REMOTE_WRITE;
346
347 if (access_flags & IB_ACCESS_REMOTE_READ)
348 hw_access_flags |= MTHCA_QP_BIT_RRE;
349 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
350 hw_access_flags |= MTHCA_QP_BIT_RAE;
351 if (access_flags & IB_ACCESS_REMOTE_WRITE)
352 hw_access_flags |= MTHCA_QP_BIT_RWE;
353
354 return cpu_to_be32(hw_access_flags);
355 }
356
357 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
358 {
359 switch (mthca_state) {
360 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
361 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
362 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
363 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
364 case MTHCA_QP_STATE_DRAINING:
365 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
366 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
367 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
368 default: return -1;
369 }
370 }
371
372 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
373 {
374 switch (mthca_mig_state) {
375 case 0: return IB_MIG_ARMED;
376 case 1: return IB_MIG_REARM;
377 case 3: return IB_MIG_MIGRATED;
378 default: return -1;
379 }
380 }
381
382 static int to_ib_qp_access_flags(int mthca_flags)
383 {
384 int ib_flags = 0;
385
386 if (mthca_flags & MTHCA_QP_BIT_RRE)
387 ib_flags |= IB_ACCESS_REMOTE_READ;
388 if (mthca_flags & MTHCA_QP_BIT_RWE)
389 ib_flags |= IB_ACCESS_REMOTE_WRITE;
390 if (mthca_flags & MTHCA_QP_BIT_RAE)
391 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
392
393 return ib_flags;
394 }
395
396 static void to_rdma_ah_attr(struct mthca_dev *dev,
397 struct rdma_ah_attr *ah_attr,
398 struct mthca_qp_path *path)
399 {
400 u8 port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
401
402 memset(ah_attr, 0, sizeof(*ah_attr));
403
404 if (port_num == 0 || port_num > dev->limits.num_ports)
405 return;
406 ah_attr->type = rdma_ah_find_type(&dev->ib_dev, port_num);
407 rdma_ah_set_port_num(ah_attr, port_num);
408
409 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
410 rdma_ah_set_sl(ah_attr, be32_to_cpu(path->sl_tclass_flowlabel) >> 28);
411 rdma_ah_set_path_bits(ah_attr, path->g_mylmc & 0x7f);
412 rdma_ah_set_static_rate(ah_attr,
413 mthca_rate_to_ib(dev,
414 path->static_rate & 0xf,
415 port_num));
416 if (path->g_mylmc & (1 << 7)) {
417 u32 tc_fl = be32_to_cpu(path->sl_tclass_flowlabel);
418
419 rdma_ah_set_grh(ah_attr, NULL,
420 tc_fl & 0xfffff,
421 path->mgid_index &
422 (dev->limits.gid_table_len - 1),
423 path->hop_limit,
424 (tc_fl >> 20) & 0xff);
425 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
426 }
427 }
428
429 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
430 struct ib_qp_init_attr *qp_init_attr)
431 {
432 struct mthca_dev *dev = to_mdev(ibqp->device);
433 struct mthca_qp *qp = to_mqp(ibqp);
434 int err = 0;
435 struct mthca_mailbox *mailbox = NULL;
436 struct mthca_qp_param *qp_param;
437 struct mthca_qp_context *context;
438 int mthca_state;
439
440 mutex_lock(&qp->mutex);
441
442 if (qp->state == IB_QPS_RESET) {
443 qp_attr->qp_state = IB_QPS_RESET;
444 goto done;
445 }
446
447 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
448 if (IS_ERR(mailbox)) {
449 err = PTR_ERR(mailbox);
450 goto out;
451 }
452
453 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox);
454 if (err) {
455 mthca_warn(dev, "QUERY_QP failed (%d)\n", err);
456 goto out_mailbox;
457 }
458
459 qp_param = mailbox->buf;
460 context = &qp_param->context;
461 mthca_state = be32_to_cpu(context->flags) >> 28;
462
463 qp->state = to_ib_qp_state(mthca_state);
464 qp_attr->qp_state = qp->state;
465 qp_attr->path_mtu = context->mtu_msgmax >> 5;
466 qp_attr->path_mig_state =
467 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
468 qp_attr->qkey = be32_to_cpu(context->qkey);
469 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
470 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
471 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
472 qp_attr->qp_access_flags =
473 to_ib_qp_access_flags(be32_to_cpu(context->params2));
474
475 if (qp->transport == RC || qp->transport == UC) {
476 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
477 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
478 qp_attr->alt_pkey_index =
479 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
480 qp_attr->alt_port_num =
481 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
482 }
483
484 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
485 qp_attr->port_num =
486 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
487
488 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
489 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
490
491 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
492
493 qp_attr->max_dest_rd_atomic =
494 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
495 qp_attr->min_rnr_timer =
496 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
497 qp_attr->timeout = context->pri_path.ackto >> 3;
498 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
499 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
500 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
501
502 done:
503 qp_attr->cur_qp_state = qp_attr->qp_state;
504 qp_attr->cap.max_send_wr = qp->sq.max;
505 qp_attr->cap.max_recv_wr = qp->rq.max;
506 qp_attr->cap.max_send_sge = qp->sq.max_gs;
507 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
508 qp_attr->cap.max_inline_data = qp->max_inline_data;
509
510 qp_init_attr->cap = qp_attr->cap;
511 qp_init_attr->sq_sig_type = qp->sq_policy;
512
513 out_mailbox:
514 mthca_free_mailbox(dev, mailbox);
515
516 out:
517 mutex_unlock(&qp->mutex);
518 return err;
519 }
520
521 static int mthca_path_set(struct mthca_dev *dev, const struct rdma_ah_attr *ah,
522 struct mthca_qp_path *path, u8 port)
523 {
524 path->g_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
525 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
526 path->static_rate = mthca_get_rate(dev, rdma_ah_get_static_rate(ah),
527 port);
528
529 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
530 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
531
532 if (grh->sgid_index >= dev->limits.gid_table_len) {
533 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
534 grh->sgid_index,
535 dev->limits.gid_table_len - 1);
536 return -1;
537 }
538
539 path->g_mylmc |= 1 << 7;
540 path->mgid_index = grh->sgid_index;
541 path->hop_limit = grh->hop_limit;
542 path->sl_tclass_flowlabel =
543 cpu_to_be32((rdma_ah_get_sl(ah) << 28) |
544 (grh->traffic_class << 20) |
545 (grh->flow_label));
546 memcpy(path->rgid, grh->dgid.raw, 16);
547 } else {
548 path->sl_tclass_flowlabel = cpu_to_be32(rdma_ah_get_sl(ah) <<
549 28);
550 }
551
552 return 0;
553 }
554
555 static int __mthca_modify_qp(struct ib_qp *ibqp,
556 const struct ib_qp_attr *attr, int attr_mask,
557 enum ib_qp_state cur_state, enum ib_qp_state new_state)
558 {
559 struct mthca_dev *dev = to_mdev(ibqp->device);
560 struct mthca_qp *qp = to_mqp(ibqp);
561 struct mthca_mailbox *mailbox;
562 struct mthca_qp_param *qp_param;
563 struct mthca_qp_context *qp_context;
564 u32 sqd_event = 0;
565 int err = -EINVAL;
566
567 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
568 if (IS_ERR(mailbox)) {
569 err = PTR_ERR(mailbox);
570 goto out;
571 }
572 qp_param = mailbox->buf;
573 qp_context = &qp_param->context;
574 memset(qp_param, 0, sizeof *qp_param);
575
576 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
577 (to_mthca_st(qp->transport) << 16));
578 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
579 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
580 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
581 else {
582 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
583 switch (attr->path_mig_state) {
584 case IB_MIG_MIGRATED:
585 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
586 break;
587 case IB_MIG_REARM:
588 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
589 break;
590 case IB_MIG_ARMED:
591 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
592 break;
593 }
594 }
595
596 /* leave tavor_sched_queue as 0 */
597
598 if (qp->transport == MLX || qp->transport == UD)
599 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
600 else if (attr_mask & IB_QP_PATH_MTU) {
601 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
602 mthca_dbg(dev, "path MTU (%u) is invalid\n",
603 attr->path_mtu);
604 goto out_mailbox;
605 }
606 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
607 }
608
609 if (mthca_is_memfree(dev)) {
610 if (qp->rq.max)
611 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
612 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
613
614 if (qp->sq.max)
615 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
616 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
617 }
618
619 /* leave arbel_sched_queue as 0 */
620
621 if (qp->ibqp.uobject)
622 qp_context->usr_page =
623 cpu_to_be32(to_mucontext(qp->ibqp.uobject->context)->uar.index);
624 else
625 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
626 qp_context->local_qpn = cpu_to_be32(qp->qpn);
627 if (attr_mask & IB_QP_DEST_QPN) {
628 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
629 }
630
631 if (qp->transport == MLX)
632 qp_context->pri_path.port_pkey |=
633 cpu_to_be32(qp->port << 24);
634 else {
635 if (attr_mask & IB_QP_PORT) {
636 qp_context->pri_path.port_pkey |=
637 cpu_to_be32(attr->port_num << 24);
638 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
639 }
640 }
641
642 if (attr_mask & IB_QP_PKEY_INDEX) {
643 qp_context->pri_path.port_pkey |=
644 cpu_to_be32(attr->pkey_index);
645 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
646 }
647
648 if (attr_mask & IB_QP_RNR_RETRY) {
649 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
650 attr->rnr_retry << 5;
651 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
652 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
653 }
654
655 if (attr_mask & IB_QP_AV) {
656 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
657 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
658 goto out_mailbox;
659
660 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
661 }
662
663 if (ibqp->qp_type == IB_QPT_RC &&
664 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
665 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
666
667 if (mthca_is_memfree(dev))
668 qp_context->rlkey_arbel_sched_queue |= sched_queue;
669 else
670 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
671
672 qp_param->opt_param_mask |=
673 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
674 }
675
676 if (attr_mask & IB_QP_TIMEOUT) {
677 qp_context->pri_path.ackto = attr->timeout << 3;
678 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
679 }
680
681 if (attr_mask & IB_QP_ALT_PATH) {
682 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
683 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
684 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
685 goto out_mailbox;
686 }
687
688 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
689 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
690 attr->alt_port_num);
691 goto out_mailbox;
692 }
693
694 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
695 rdma_ah_get_port_num(&attr->alt_ah_attr)))
696 goto out_mailbox;
697
698 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
699 attr->alt_port_num << 24);
700 qp_context->alt_path.ackto = attr->alt_timeout << 3;
701 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
702 }
703
704 /* leave rdd as 0 */
705 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
706 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
707 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
708 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
709 (MTHCA_FLIGHT_LIMIT << 24) |
710 MTHCA_QP_BIT_SWE);
711 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
712 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
713 if (attr_mask & IB_QP_RETRY_CNT) {
714 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
715 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
716 }
717
718 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
719 if (attr->max_rd_atomic) {
720 qp_context->params1 |=
721 cpu_to_be32(MTHCA_QP_BIT_SRE |
722 MTHCA_QP_BIT_SAE);
723 qp_context->params1 |=
724 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
725 }
726 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
727 }
728
729 if (attr_mask & IB_QP_SQ_PSN)
730 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
731 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
732
733 if (mthca_is_memfree(dev)) {
734 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
735 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
736 }
737
738 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
739 if (attr->max_dest_rd_atomic)
740 qp_context->params2 |=
741 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
742
743 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
744 }
745
746 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
747 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
748 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
749 MTHCA_QP_OPTPAR_RRE |
750 MTHCA_QP_OPTPAR_RAE);
751 }
752
753 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
754
755 if (ibqp->srq)
756 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
757
758 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
759 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
760 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
761 }
762 if (attr_mask & IB_QP_RQ_PSN)
763 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
764
765 qp_context->ra_buff_indx =
766 cpu_to_be32(dev->qp_table.rdb_base +
767 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
768 dev->qp_table.rdb_shift));
769
770 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
771
772 if (mthca_is_memfree(dev))
773 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
774
775 if (attr_mask & IB_QP_QKEY) {
776 qp_context->qkey = cpu_to_be32(attr->qkey);
777 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
778 }
779
780 if (ibqp->srq)
781 qp_context->srqn = cpu_to_be32(1 << 24 |
782 to_msrq(ibqp->srq)->srqn);
783
784 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
785 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
786 attr->en_sqd_async_notify)
787 sqd_event = 1 << 31;
788
789 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
790 mailbox, sqd_event);
791 if (err) {
792 mthca_warn(dev, "modify QP %d->%d returned %d.\n",
793 cur_state, new_state, err);
794 goto out_mailbox;
795 }
796
797 qp->state = new_state;
798 if (attr_mask & IB_QP_ACCESS_FLAGS)
799 qp->atomic_rd_en = attr->qp_access_flags;
800 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
801 qp->resp_depth = attr->max_dest_rd_atomic;
802 if (attr_mask & IB_QP_PORT)
803 qp->port = attr->port_num;
804 if (attr_mask & IB_QP_ALT_PATH)
805 qp->alt_port = attr->alt_port_num;
806
807 if (is_sqp(dev, qp))
808 store_attrs(to_msqp(qp), attr, attr_mask);
809
810 /*
811 * If we moved QP0 to RTR, bring the IB link up; if we moved
812 * QP0 to RESET or ERROR, bring the link back down.
813 */
814 if (is_qp0(dev, qp)) {
815 if (cur_state != IB_QPS_RTR &&
816 new_state == IB_QPS_RTR)
817 init_port(dev, qp->port);
818
819 if (cur_state != IB_QPS_RESET &&
820 cur_state != IB_QPS_ERR &&
821 (new_state == IB_QPS_RESET ||
822 new_state == IB_QPS_ERR))
823 mthca_CLOSE_IB(dev, qp->port);
824 }
825
826 /*
827 * If we moved a kernel QP to RESET, clean up all old CQ
828 * entries and reinitialize the QP.
829 */
830 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
831 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
832 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
833 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
834 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
835
836 mthca_wq_reset(&qp->sq);
837 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
838
839 mthca_wq_reset(&qp->rq);
840 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
841
842 if (mthca_is_memfree(dev)) {
843 *qp->sq.db = 0;
844 *qp->rq.db = 0;
845 }
846 }
847
848 out_mailbox:
849 mthca_free_mailbox(dev, mailbox);
850 out:
851 return err;
852 }
853
854 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
855 struct ib_udata *udata)
856 {
857 struct mthca_dev *dev = to_mdev(ibqp->device);
858 struct mthca_qp *qp = to_mqp(ibqp);
859 enum ib_qp_state cur_state, new_state;
860 int err = -EINVAL;
861
862 mutex_lock(&qp->mutex);
863 if (attr_mask & IB_QP_CUR_STATE) {
864 cur_state = attr->cur_qp_state;
865 } else {
866 spin_lock_irq(&qp->sq.lock);
867 spin_lock(&qp->rq.lock);
868 cur_state = qp->state;
869 spin_unlock(&qp->rq.lock);
870 spin_unlock_irq(&qp->sq.lock);
871 }
872
873 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
874
875 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
876 attr_mask)) {
877 mthca_dbg(dev, "Bad QP transition (transport %d) "
878 "%d->%d with attr 0x%08x\n",
879 qp->transport, cur_state, new_state,
880 attr_mask);
881 goto out;
882 }
883
884 if ((attr_mask & IB_QP_PKEY_INDEX) &&
885 attr->pkey_index >= dev->limits.pkey_table_len) {
886 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
887 attr->pkey_index, dev->limits.pkey_table_len-1);
888 goto out;
889 }
890
891 if ((attr_mask & IB_QP_PORT) &&
892 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
893 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
894 goto out;
895 }
896
897 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
898 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
899 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
900 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
901 goto out;
902 }
903
904 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
905 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
906 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
907 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
908 goto out;
909 }
910
911 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
912 err = 0;
913 goto out;
914 }
915
916 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state);
917
918 out:
919 mutex_unlock(&qp->mutex);
920 return err;
921 }
922
923 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
924 {
925 /*
926 * Calculate the maximum size of WQE s/g segments, excluding
927 * the next segment and other non-data segments.
928 */
929 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
930
931 switch (qp->transport) {
932 case MLX:
933 max_data_size -= 2 * sizeof (struct mthca_data_seg);
934 break;
935
936 case UD:
937 if (mthca_is_memfree(dev))
938 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
939 else
940 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
941 break;
942
943 default:
944 max_data_size -= sizeof (struct mthca_raddr_seg);
945 break;
946 }
947
948 return max_data_size;
949 }
950
951 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
952 {
953 /* We don't support inline data for kernel QPs (yet). */
954 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
955 }
956
957 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
958 struct mthca_pd *pd,
959 struct mthca_qp *qp)
960 {
961 int max_data_size = mthca_max_data_size(dev, qp,
962 min(dev->limits.max_desc_sz,
963 1 << qp->sq.wqe_shift));
964
965 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
966
967 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
968 max_data_size / sizeof (struct mthca_data_seg));
969 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
970 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
971 sizeof (struct mthca_next_seg)) /
972 sizeof (struct mthca_data_seg));
973 }
974
975 /*
976 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
977 * rq.max_gs and sq.max_gs must all be assigned.
978 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
979 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
980 * queue)
981 */
982 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
983 struct mthca_pd *pd,
984 struct mthca_qp *qp,
985 struct ib_udata *udata)
986 {
987 int size;
988 int err = -ENOMEM;
989
990 size = sizeof (struct mthca_next_seg) +
991 qp->rq.max_gs * sizeof (struct mthca_data_seg);
992
993 if (size > dev->limits.max_desc_sz)
994 return -EINVAL;
995
996 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
997 qp->rq.wqe_shift++)
998 ; /* nothing */
999
1000 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1001 switch (qp->transport) {
1002 case MLX:
1003 size += 2 * sizeof (struct mthca_data_seg);
1004 break;
1005
1006 case UD:
1007 size += mthca_is_memfree(dev) ?
1008 sizeof (struct mthca_arbel_ud_seg) :
1009 sizeof (struct mthca_tavor_ud_seg);
1010 break;
1011
1012 case UC:
1013 size += sizeof (struct mthca_raddr_seg);
1014 break;
1015
1016 case RC:
1017 size += sizeof (struct mthca_raddr_seg);
1018 /*
1019 * An atomic op will require an atomic segment, a
1020 * remote address segment and one scatter entry.
1021 */
1022 size = max_t(int, size,
1023 sizeof (struct mthca_atomic_seg) +
1024 sizeof (struct mthca_raddr_seg) +
1025 sizeof (struct mthca_data_seg));
1026 break;
1027
1028 default:
1029 break;
1030 }
1031
1032 /* Make sure that we have enough space for a bind request */
1033 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1034
1035 size += sizeof (struct mthca_next_seg);
1036
1037 if (size > dev->limits.max_desc_sz)
1038 return -EINVAL;
1039
1040 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1041 qp->sq.wqe_shift++)
1042 ; /* nothing */
1043
1044 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1045 1 << qp->sq.wqe_shift);
1046
1047 /*
1048 * If this is a userspace QP, we don't actually have to
1049 * allocate anything. All we need is to calculate the WQE
1050 * sizes and the send_wqe_offset, so we're done now.
1051 */
1052 if (udata)
1053 return 0;
1054
1055 size = PAGE_ALIGN(qp->send_wqe_offset +
1056 (qp->sq.max << qp->sq.wqe_shift));
1057
1058 qp->wrid = kmalloc_array(qp->rq.max + qp->sq.max, sizeof(u64),
1059 GFP_KERNEL);
1060 if (!qp->wrid)
1061 goto err_out;
1062
1063 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1064 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1065 if (err)
1066 goto err_out;
1067
1068 return 0;
1069
1070 err_out:
1071 kfree(qp->wrid);
1072 return err;
1073 }
1074
1075 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1076 struct mthca_qp *qp)
1077 {
1078 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1079 (qp->sq.max << qp->sq.wqe_shift)),
1080 &qp->queue, qp->is_direct, &qp->mr);
1081 kfree(qp->wrid);
1082 }
1083
1084 static int mthca_map_memfree(struct mthca_dev *dev,
1085 struct mthca_qp *qp)
1086 {
1087 int ret;
1088
1089 if (mthca_is_memfree(dev)) {
1090 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1091 if (ret)
1092 return ret;
1093
1094 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1095 if (ret)
1096 goto err_qpc;
1097
1098 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1099 qp->qpn << dev->qp_table.rdb_shift);
1100 if (ret)
1101 goto err_eqpc;
1102
1103 }
1104
1105 return 0;
1106
1107 err_eqpc:
1108 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1109
1110 err_qpc:
1111 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1112
1113 return ret;
1114 }
1115
1116 static void mthca_unmap_memfree(struct mthca_dev *dev,
1117 struct mthca_qp *qp)
1118 {
1119 mthca_table_put(dev, dev->qp_table.rdb_table,
1120 qp->qpn << dev->qp_table.rdb_shift);
1121 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1122 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1123 }
1124
1125 static int mthca_alloc_memfree(struct mthca_dev *dev,
1126 struct mthca_qp *qp)
1127 {
1128 if (mthca_is_memfree(dev)) {
1129 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1130 qp->qpn, &qp->rq.db);
1131 if (qp->rq.db_index < 0)
1132 return -ENOMEM;
1133
1134 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1135 qp->qpn, &qp->sq.db);
1136 if (qp->sq.db_index < 0) {
1137 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1138 return -ENOMEM;
1139 }
1140 }
1141
1142 return 0;
1143 }
1144
1145 static void mthca_free_memfree(struct mthca_dev *dev,
1146 struct mthca_qp *qp)
1147 {
1148 if (mthca_is_memfree(dev)) {
1149 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1150 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1151 }
1152 }
1153
1154 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1155 struct mthca_pd *pd,
1156 struct mthca_cq *send_cq,
1157 struct mthca_cq *recv_cq,
1158 enum ib_sig_type send_policy,
1159 struct mthca_qp *qp,
1160 struct ib_udata *udata)
1161 {
1162 int ret;
1163 int i;
1164 struct mthca_next_seg *next;
1165
1166 qp->refcount = 1;
1167 init_waitqueue_head(&qp->wait);
1168 mutex_init(&qp->mutex);
1169 qp->state = IB_QPS_RESET;
1170 qp->atomic_rd_en = 0;
1171 qp->resp_depth = 0;
1172 qp->sq_policy = send_policy;
1173 mthca_wq_reset(&qp->sq);
1174 mthca_wq_reset(&qp->rq);
1175
1176 spin_lock_init(&qp->sq.lock);
1177 spin_lock_init(&qp->rq.lock);
1178
1179 ret = mthca_map_memfree(dev, qp);
1180 if (ret)
1181 return ret;
1182
1183 ret = mthca_alloc_wqe_buf(dev, pd, qp, udata);
1184 if (ret) {
1185 mthca_unmap_memfree(dev, qp);
1186 return ret;
1187 }
1188
1189 mthca_adjust_qp_caps(dev, pd, qp);
1190
1191 /*
1192 * If this is a userspace QP, we're done now. The doorbells
1193 * will be allocated and buffers will be initialized in
1194 * userspace.
1195 */
1196 if (udata)
1197 return 0;
1198
1199 ret = mthca_alloc_memfree(dev, qp);
1200 if (ret) {
1201 mthca_free_wqe_buf(dev, qp);
1202 mthca_unmap_memfree(dev, qp);
1203 return ret;
1204 }
1205
1206 if (mthca_is_memfree(dev)) {
1207 struct mthca_data_seg *scatter;
1208 int size = (sizeof (struct mthca_next_seg) +
1209 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1210
1211 for (i = 0; i < qp->rq.max; ++i) {
1212 next = get_recv_wqe(qp, i);
1213 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1214 qp->rq.wqe_shift);
1215 next->ee_nds = cpu_to_be32(size);
1216
1217 for (scatter = (void *) (next + 1);
1218 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1219 ++scatter)
1220 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1221 }
1222
1223 for (i = 0; i < qp->sq.max; ++i) {
1224 next = get_send_wqe(qp, i);
1225 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1226 qp->sq.wqe_shift) +
1227 qp->send_wqe_offset);
1228 }
1229 } else {
1230 for (i = 0; i < qp->rq.max; ++i) {
1231 next = get_recv_wqe(qp, i);
1232 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1233 qp->rq.wqe_shift) | 1);
1234 }
1235
1236 }
1237
1238 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1239 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1240
1241 return 0;
1242 }
1243
1244 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1245 struct mthca_pd *pd, struct mthca_qp *qp)
1246 {
1247 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1248
1249 /* Sanity check QP size before proceeding */
1250 if (cap->max_send_wr > dev->limits.max_wqes ||
1251 cap->max_recv_wr > dev->limits.max_wqes ||
1252 cap->max_send_sge > dev->limits.max_sg ||
1253 cap->max_recv_sge > dev->limits.max_sg ||
1254 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1255 return -EINVAL;
1256
1257 /*
1258 * For MLX transport we need 2 extra send gather entries:
1259 * one for the header and one for the checksum at the end
1260 */
1261 if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1262 return -EINVAL;
1263
1264 if (mthca_is_memfree(dev)) {
1265 qp->rq.max = cap->max_recv_wr ?
1266 roundup_pow_of_two(cap->max_recv_wr) : 0;
1267 qp->sq.max = cap->max_send_wr ?
1268 roundup_pow_of_two(cap->max_send_wr) : 0;
1269 } else {
1270 qp->rq.max = cap->max_recv_wr;
1271 qp->sq.max = cap->max_send_wr;
1272 }
1273
1274 qp->rq.max_gs = cap->max_recv_sge;
1275 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1276 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1277 MTHCA_INLINE_CHUNK_SIZE) /
1278 sizeof (struct mthca_data_seg));
1279
1280 return 0;
1281 }
1282
1283 int mthca_alloc_qp(struct mthca_dev *dev,
1284 struct mthca_pd *pd,
1285 struct mthca_cq *send_cq,
1286 struct mthca_cq *recv_cq,
1287 enum ib_qp_type type,
1288 enum ib_sig_type send_policy,
1289 struct ib_qp_cap *cap,
1290 struct mthca_qp *qp,
1291 struct ib_udata *udata)
1292 {
1293 int err;
1294
1295 switch (type) {
1296 case IB_QPT_RC: qp->transport = RC; break;
1297 case IB_QPT_UC: qp->transport = UC; break;
1298 case IB_QPT_UD: qp->transport = UD; break;
1299 default: return -EINVAL;
1300 }
1301
1302 err = mthca_set_qp_size(dev, cap, pd, qp);
1303 if (err)
1304 return err;
1305
1306 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1307 if (qp->qpn == -1)
1308 return -ENOMEM;
1309
1310 /* initialize port to zero for error-catching. */
1311 qp->port = 0;
1312
1313 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1314 send_policy, qp, udata);
1315 if (err) {
1316 mthca_free(&dev->qp_table.alloc, qp->qpn);
1317 return err;
1318 }
1319
1320 spin_lock_irq(&dev->qp_table.lock);
1321 mthca_array_set(&dev->qp_table.qp,
1322 qp->qpn & (dev->limits.num_qps - 1), qp);
1323 spin_unlock_irq(&dev->qp_table.lock);
1324
1325 return 0;
1326 }
1327
1328 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1329 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1330 {
1331 if (send_cq == recv_cq) {
1332 spin_lock_irq(&send_cq->lock);
1333 __acquire(&recv_cq->lock);
1334 } else if (send_cq->cqn < recv_cq->cqn) {
1335 spin_lock_irq(&send_cq->lock);
1336 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1337 } else {
1338 spin_lock_irq(&recv_cq->lock);
1339 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1340 }
1341 }
1342
1343 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1344 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1345 {
1346 if (send_cq == recv_cq) {
1347 __release(&recv_cq->lock);
1348 spin_unlock_irq(&send_cq->lock);
1349 } else if (send_cq->cqn < recv_cq->cqn) {
1350 spin_unlock(&recv_cq->lock);
1351 spin_unlock_irq(&send_cq->lock);
1352 } else {
1353 spin_unlock(&send_cq->lock);
1354 spin_unlock_irq(&recv_cq->lock);
1355 }
1356 }
1357
1358 int mthca_alloc_sqp(struct mthca_dev *dev,
1359 struct mthca_pd *pd,
1360 struct mthca_cq *send_cq,
1361 struct mthca_cq *recv_cq,
1362 enum ib_sig_type send_policy,
1363 struct ib_qp_cap *cap,
1364 int qpn,
1365 int port,
1366 struct mthca_sqp *sqp,
1367 struct ib_udata *udata)
1368 {
1369 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1370 int err;
1371
1372 sqp->qp.transport = MLX;
1373 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1374 if (err)
1375 return err;
1376
1377 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1378 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1379 &sqp->header_dma, GFP_KERNEL);
1380 if (!sqp->header_buf)
1381 return -ENOMEM;
1382
1383 spin_lock_irq(&dev->qp_table.lock);
1384 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1385 err = -EBUSY;
1386 else
1387 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1388 spin_unlock_irq(&dev->qp_table.lock);
1389
1390 if (err)
1391 goto err_out;
1392
1393 sqp->qp.port = port;
1394 sqp->qp.qpn = mqpn;
1395 sqp->qp.transport = MLX;
1396
1397 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1398 send_policy, &sqp->qp, udata);
1399 if (err)
1400 goto err_out_free;
1401
1402 atomic_inc(&pd->sqp_count);
1403
1404 return 0;
1405
1406 err_out_free:
1407 /*
1408 * Lock CQs here, so that CQ polling code can do QP lookup
1409 * without taking a lock.
1410 */
1411 mthca_lock_cqs(send_cq, recv_cq);
1412
1413 spin_lock(&dev->qp_table.lock);
1414 mthca_array_clear(&dev->qp_table.qp, mqpn);
1415 spin_unlock(&dev->qp_table.lock);
1416
1417 mthca_unlock_cqs(send_cq, recv_cq);
1418
1419 err_out:
1420 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1421 sqp->header_buf, sqp->header_dma);
1422
1423 return err;
1424 }
1425
1426 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1427 {
1428 int c;
1429
1430 spin_lock_irq(&dev->qp_table.lock);
1431 c = qp->refcount;
1432 spin_unlock_irq(&dev->qp_table.lock);
1433
1434 return c;
1435 }
1436
1437 void mthca_free_qp(struct mthca_dev *dev,
1438 struct mthca_qp *qp)
1439 {
1440 struct mthca_cq *send_cq;
1441 struct mthca_cq *recv_cq;
1442
1443 send_cq = to_mcq(qp->ibqp.send_cq);
1444 recv_cq = to_mcq(qp->ibqp.recv_cq);
1445
1446 /*
1447 * Lock CQs here, so that CQ polling code can do QP lookup
1448 * without taking a lock.
1449 */
1450 mthca_lock_cqs(send_cq, recv_cq);
1451
1452 spin_lock(&dev->qp_table.lock);
1453 mthca_array_clear(&dev->qp_table.qp,
1454 qp->qpn & (dev->limits.num_qps - 1));
1455 --qp->refcount;
1456 spin_unlock(&dev->qp_table.lock);
1457
1458 mthca_unlock_cqs(send_cq, recv_cq);
1459
1460 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1461
1462 if (qp->state != IB_QPS_RESET)
1463 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1464 NULL, 0);
1465
1466 /*
1467 * If this is a userspace QP, the buffers, MR, CQs and so on
1468 * will be cleaned up in userspace, so all we have to do is
1469 * unref the mem-free tables and free the QPN in our table.
1470 */
1471 if (!qp->ibqp.uobject) {
1472 mthca_cq_clean(dev, recv_cq, qp->qpn,
1473 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1474 if (send_cq != recv_cq)
1475 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1476
1477 mthca_free_memfree(dev, qp);
1478 mthca_free_wqe_buf(dev, qp);
1479 }
1480
1481 mthca_unmap_memfree(dev, qp);
1482
1483 if (is_sqp(dev, qp)) {
1484 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1485 dma_free_coherent(&dev->pdev->dev,
1486 to_msqp(qp)->header_buf_size,
1487 to_msqp(qp)->header_buf,
1488 to_msqp(qp)->header_dma);
1489 } else
1490 mthca_free(&dev->qp_table.alloc, qp->qpn);
1491 }
1492
1493 /* Create UD header for an MLX send and build a data segment for it */
1494 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1495 int ind, const struct ib_ud_wr *wr,
1496 struct mthca_mlx_seg *mlx,
1497 struct mthca_data_seg *data)
1498 {
1499 int header_size;
1500 int err;
1501 u16 pkey;
1502
1503 ib_ud_header_init(256, /* assume a MAD */ 1, 0, 0,
1504 mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1505 &sqp->ud_header);
1506
1507 err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1508 if (err)
1509 return err;
1510 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1511 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1512 (sqp->ud_header.lrh.destination_lid ==
1513 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1514 (sqp->ud_header.lrh.service_level << 8));
1515 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1516 mlx->vcrc = 0;
1517
1518 switch (wr->wr.opcode) {
1519 case IB_WR_SEND:
1520 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1521 sqp->ud_header.immediate_present = 0;
1522 break;
1523 case IB_WR_SEND_WITH_IMM:
1524 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1525 sqp->ud_header.immediate_present = 1;
1526 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1527 break;
1528 default:
1529 return -EINVAL;
1530 }
1531
1532 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1533 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1534 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1535 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1536 if (!sqp->qp.ibqp.qp_num)
1537 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1538 sqp->pkey_index, &pkey);
1539 else
1540 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1541 wr->pkey_index, &pkey);
1542 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1543 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1544 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1545 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1546 sqp->qkey : wr->remote_qkey);
1547 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1548
1549 header_size = ib_ud_header_pack(&sqp->ud_header,
1550 sqp->header_buf +
1551 ind * MTHCA_UD_HEADER_SIZE);
1552
1553 data->byte_count = cpu_to_be32(header_size);
1554 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1555 data->addr = cpu_to_be64(sqp->header_dma +
1556 ind * MTHCA_UD_HEADER_SIZE);
1557
1558 return 0;
1559 }
1560
1561 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1562 struct ib_cq *ib_cq)
1563 {
1564 unsigned cur;
1565 struct mthca_cq *cq;
1566
1567 cur = wq->head - wq->tail;
1568 if (likely(cur + nreq < wq->max))
1569 return 0;
1570
1571 cq = to_mcq(ib_cq);
1572 spin_lock(&cq->lock);
1573 cur = wq->head - wq->tail;
1574 spin_unlock(&cq->lock);
1575
1576 return cur + nreq >= wq->max;
1577 }
1578
1579 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1580 u64 remote_addr, u32 rkey)
1581 {
1582 rseg->raddr = cpu_to_be64(remote_addr);
1583 rseg->rkey = cpu_to_be32(rkey);
1584 rseg->reserved = 0;
1585 }
1586
1587 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1588 const struct ib_atomic_wr *wr)
1589 {
1590 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1591 aseg->swap_add = cpu_to_be64(wr->swap);
1592 aseg->compare = cpu_to_be64(wr->compare_add);
1593 } else {
1594 aseg->swap_add = cpu_to_be64(wr->compare_add);
1595 aseg->compare = 0;
1596 }
1597
1598 }
1599
1600 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1601 const struct ib_ud_wr *wr)
1602 {
1603 useg->lkey = cpu_to_be32(to_mah(wr->ah)->key);
1604 useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);
1605 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1606 useg->qkey = cpu_to_be32(wr->remote_qkey);
1607
1608 }
1609
1610 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1611 const struct ib_ud_wr *wr)
1612 {
1613 memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1614 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1615 useg->qkey = cpu_to_be32(wr->remote_qkey);
1616 }
1617
1618 int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1619 const struct ib_send_wr **bad_wr)
1620 {
1621 struct mthca_dev *dev = to_mdev(ibqp->device);
1622 struct mthca_qp *qp = to_mqp(ibqp);
1623 void *wqe;
1624 void *prev_wqe;
1625 unsigned long flags;
1626 int err = 0;
1627 int nreq;
1628 int i;
1629 int size;
1630 /*
1631 * f0 and size0 are only used if nreq != 0, and they will
1632 * always be initialized the first time through the main loop
1633 * before nreq is incremented. So nreq cannot become non-zero
1634 * without initializing f0 and size0, and they are in fact
1635 * never used uninitialized.
1636 */
1637 int uninitialized_var(size0);
1638 u32 uninitialized_var(f0);
1639 int ind;
1640 u8 op0 = 0;
1641
1642 spin_lock_irqsave(&qp->sq.lock, flags);
1643
1644 /* XXX check that state is OK to post send */
1645
1646 ind = qp->sq.next_ind;
1647
1648 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1649 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1650 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1651 " %d max, %d nreq)\n", qp->qpn,
1652 qp->sq.head, qp->sq.tail,
1653 qp->sq.max, nreq);
1654 err = -ENOMEM;
1655 *bad_wr = wr;
1656 goto out;
1657 }
1658
1659 wqe = get_send_wqe(qp, ind);
1660 prev_wqe = qp->sq.last;
1661 qp->sq.last = wqe;
1662
1663 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1664 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1665 ((struct mthca_next_seg *) wqe)->flags =
1666 ((wr->send_flags & IB_SEND_SIGNALED) ?
1667 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1668 ((wr->send_flags & IB_SEND_SOLICITED) ?
1669 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1670 cpu_to_be32(1);
1671 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1672 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1673 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1674
1675 wqe += sizeof (struct mthca_next_seg);
1676 size = sizeof (struct mthca_next_seg) / 16;
1677
1678 switch (qp->transport) {
1679 case RC:
1680 switch (wr->opcode) {
1681 case IB_WR_ATOMIC_CMP_AND_SWP:
1682 case IB_WR_ATOMIC_FETCH_AND_ADD:
1683 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1684 atomic_wr(wr)->rkey);
1685 wqe += sizeof (struct mthca_raddr_seg);
1686
1687 set_atomic_seg(wqe, atomic_wr(wr));
1688 wqe += sizeof (struct mthca_atomic_seg);
1689 size += (sizeof (struct mthca_raddr_seg) +
1690 sizeof (struct mthca_atomic_seg)) / 16;
1691 break;
1692
1693 case IB_WR_RDMA_WRITE:
1694 case IB_WR_RDMA_WRITE_WITH_IMM:
1695 case IB_WR_RDMA_READ:
1696 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1697 rdma_wr(wr)->rkey);
1698 wqe += sizeof (struct mthca_raddr_seg);
1699 size += sizeof (struct mthca_raddr_seg) / 16;
1700 break;
1701
1702 default:
1703 /* No extra segments required for sends */
1704 break;
1705 }
1706
1707 break;
1708
1709 case UC:
1710 switch (wr->opcode) {
1711 case IB_WR_RDMA_WRITE:
1712 case IB_WR_RDMA_WRITE_WITH_IMM:
1713 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1714 rdma_wr(wr)->rkey);
1715 wqe += sizeof (struct mthca_raddr_seg);
1716 size += sizeof (struct mthca_raddr_seg) / 16;
1717 break;
1718
1719 default:
1720 /* No extra segments required for sends */
1721 break;
1722 }
1723
1724 break;
1725
1726 case UD:
1727 set_tavor_ud_seg(wqe, ud_wr(wr));
1728 wqe += sizeof (struct mthca_tavor_ud_seg);
1729 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1730 break;
1731
1732 case MLX:
1733 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1734 wqe - sizeof (struct mthca_next_seg),
1735 wqe);
1736 if (err) {
1737 *bad_wr = wr;
1738 goto out;
1739 }
1740 wqe += sizeof (struct mthca_data_seg);
1741 size += sizeof (struct mthca_data_seg) / 16;
1742 break;
1743 }
1744
1745 if (wr->num_sge > qp->sq.max_gs) {
1746 mthca_err(dev, "too many gathers\n");
1747 err = -EINVAL;
1748 *bad_wr = wr;
1749 goto out;
1750 }
1751
1752 for (i = 0; i < wr->num_sge; ++i) {
1753 mthca_set_data_seg(wqe, wr->sg_list + i);
1754 wqe += sizeof (struct mthca_data_seg);
1755 size += sizeof (struct mthca_data_seg) / 16;
1756 }
1757
1758 /* Add one more inline data segment for ICRC */
1759 if (qp->transport == MLX) {
1760 ((struct mthca_data_seg *) wqe)->byte_count =
1761 cpu_to_be32((1 << 31) | 4);
1762 ((u32 *) wqe)[1] = 0;
1763 wqe += sizeof (struct mthca_data_seg);
1764 size += sizeof (struct mthca_data_seg) / 16;
1765 }
1766
1767 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1768
1769 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1770 mthca_err(dev, "opcode invalid\n");
1771 err = -EINVAL;
1772 *bad_wr = wr;
1773 goto out;
1774 }
1775
1776 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1777 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1778 qp->send_wqe_offset) |
1779 mthca_opcode[wr->opcode]);
1780 wmb();
1781 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1782 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1783 ((wr->send_flags & IB_SEND_FENCE) ?
1784 MTHCA_NEXT_FENCE : 0));
1785
1786 if (!nreq) {
1787 size0 = size;
1788 op0 = mthca_opcode[wr->opcode];
1789 f0 = wr->send_flags & IB_SEND_FENCE ?
1790 MTHCA_SEND_DOORBELL_FENCE : 0;
1791 }
1792
1793 ++ind;
1794 if (unlikely(ind >= qp->sq.max))
1795 ind -= qp->sq.max;
1796 }
1797
1798 out:
1799 if (likely(nreq)) {
1800 wmb();
1801
1802 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1803 qp->send_wqe_offset) | f0 | op0,
1804 (qp->qpn << 8) | size0,
1805 dev->kar + MTHCA_SEND_DOORBELL,
1806 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1807 /*
1808 * Make sure doorbells don't leak out of SQ spinlock
1809 * and reach the HCA out of order:
1810 */
1811 mmiowb();
1812 }
1813
1814 qp->sq.next_ind = ind;
1815 qp->sq.head += nreq;
1816
1817 spin_unlock_irqrestore(&qp->sq.lock, flags);
1818 return err;
1819 }
1820
1821 int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1822 const struct ib_recv_wr **bad_wr)
1823 {
1824 struct mthca_dev *dev = to_mdev(ibqp->device);
1825 struct mthca_qp *qp = to_mqp(ibqp);
1826 unsigned long flags;
1827 int err = 0;
1828 int nreq;
1829 int i;
1830 int size;
1831 /*
1832 * size0 is only used if nreq != 0, and it will always be
1833 * initialized the first time through the main loop before
1834 * nreq is incremented. So nreq cannot become non-zero
1835 * without initializing size0, and it is in fact never used
1836 * uninitialized.
1837 */
1838 int uninitialized_var(size0);
1839 int ind;
1840 void *wqe;
1841 void *prev_wqe;
1842
1843 spin_lock_irqsave(&qp->rq.lock, flags);
1844
1845 /* XXX check that state is OK to post receive */
1846
1847 ind = qp->rq.next_ind;
1848
1849 for (nreq = 0; wr; wr = wr->next) {
1850 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1851 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1852 " %d max, %d nreq)\n", qp->qpn,
1853 qp->rq.head, qp->rq.tail,
1854 qp->rq.max, nreq);
1855 err = -ENOMEM;
1856 *bad_wr = wr;
1857 goto out;
1858 }
1859
1860 wqe = get_recv_wqe(qp, ind);
1861 prev_wqe = qp->rq.last;
1862 qp->rq.last = wqe;
1863
1864 ((struct mthca_next_seg *) wqe)->ee_nds =
1865 cpu_to_be32(MTHCA_NEXT_DBD);
1866 ((struct mthca_next_seg *) wqe)->flags = 0;
1867
1868 wqe += sizeof (struct mthca_next_seg);
1869 size = sizeof (struct mthca_next_seg) / 16;
1870
1871 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1872 err = -EINVAL;
1873 *bad_wr = wr;
1874 goto out;
1875 }
1876
1877 for (i = 0; i < wr->num_sge; ++i) {
1878 mthca_set_data_seg(wqe, wr->sg_list + i);
1879 wqe += sizeof (struct mthca_data_seg);
1880 size += sizeof (struct mthca_data_seg) / 16;
1881 }
1882
1883 qp->wrid[ind] = wr->wr_id;
1884
1885 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1886 cpu_to_be32(MTHCA_NEXT_DBD | size);
1887
1888 if (!nreq)
1889 size0 = size;
1890
1891 ++ind;
1892 if (unlikely(ind >= qp->rq.max))
1893 ind -= qp->rq.max;
1894
1895 ++nreq;
1896 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1897 nreq = 0;
1898
1899 wmb();
1900
1901 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1902 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1903 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1904
1905 qp->rq.next_ind = ind;
1906 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1907 }
1908 }
1909
1910 out:
1911 if (likely(nreq)) {
1912 wmb();
1913
1914 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1915 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1916 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1917 }
1918
1919 qp->rq.next_ind = ind;
1920 qp->rq.head += nreq;
1921
1922 /*
1923 * Make sure doorbells don't leak out of RQ spinlock and reach
1924 * the HCA out of order:
1925 */
1926 mmiowb();
1927
1928 spin_unlock_irqrestore(&qp->rq.lock, flags);
1929 return err;
1930 }
1931
1932 int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1933 const struct ib_send_wr **bad_wr)
1934 {
1935 struct mthca_dev *dev = to_mdev(ibqp->device);
1936 struct mthca_qp *qp = to_mqp(ibqp);
1937 u32 dbhi;
1938 void *wqe;
1939 void *prev_wqe;
1940 unsigned long flags;
1941 int err = 0;
1942 int nreq;
1943 int i;
1944 int size;
1945 /*
1946 * f0 and size0 are only used if nreq != 0, and they will
1947 * always be initialized the first time through the main loop
1948 * before nreq is incremented. So nreq cannot become non-zero
1949 * without initializing f0 and size0, and they are in fact
1950 * never used uninitialized.
1951 */
1952 int uninitialized_var(size0);
1953 u32 uninitialized_var(f0);
1954 int ind;
1955 u8 op0 = 0;
1956
1957 spin_lock_irqsave(&qp->sq.lock, flags);
1958
1959 /* XXX check that state is OK to post send */
1960
1961 ind = qp->sq.head & (qp->sq.max - 1);
1962
1963 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1964 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1965 nreq = 0;
1966
1967 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1968 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1969
1970 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1971
1972 /*
1973 * Make sure that descriptors are written before
1974 * doorbell record.
1975 */
1976 wmb();
1977 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1978
1979 /*
1980 * Make sure doorbell record is written before we
1981 * write MMIO send doorbell.
1982 */
1983 wmb();
1984
1985 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1986 dev->kar + MTHCA_SEND_DOORBELL,
1987 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1988 }
1989
1990 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1991 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1992 " %d max, %d nreq)\n", qp->qpn,
1993 qp->sq.head, qp->sq.tail,
1994 qp->sq.max, nreq);
1995 err = -ENOMEM;
1996 *bad_wr = wr;
1997 goto out;
1998 }
1999
2000 wqe = get_send_wqe(qp, ind);
2001 prev_wqe = qp->sq.last;
2002 qp->sq.last = wqe;
2003
2004 ((struct mthca_next_seg *) wqe)->flags =
2005 ((wr->send_flags & IB_SEND_SIGNALED) ?
2006 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2007 ((wr->send_flags & IB_SEND_SOLICITED) ?
2008 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2009 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2010 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2011 cpu_to_be32(1);
2012 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2013 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2014 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2015
2016 wqe += sizeof (struct mthca_next_seg);
2017 size = sizeof (struct mthca_next_seg) / 16;
2018
2019 switch (qp->transport) {
2020 case RC:
2021 switch (wr->opcode) {
2022 case IB_WR_ATOMIC_CMP_AND_SWP:
2023 case IB_WR_ATOMIC_FETCH_AND_ADD:
2024 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2025 atomic_wr(wr)->rkey);
2026 wqe += sizeof (struct mthca_raddr_seg);
2027
2028 set_atomic_seg(wqe, atomic_wr(wr));
2029 wqe += sizeof (struct mthca_atomic_seg);
2030 size += (sizeof (struct mthca_raddr_seg) +
2031 sizeof (struct mthca_atomic_seg)) / 16;
2032 break;
2033
2034 case IB_WR_RDMA_READ:
2035 case IB_WR_RDMA_WRITE:
2036 case IB_WR_RDMA_WRITE_WITH_IMM:
2037 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2038 rdma_wr(wr)->rkey);
2039 wqe += sizeof (struct mthca_raddr_seg);
2040 size += sizeof (struct mthca_raddr_seg) / 16;
2041 break;
2042
2043 default:
2044 /* No extra segments required for sends */
2045 break;
2046 }
2047
2048 break;
2049
2050 case UC:
2051 switch (wr->opcode) {
2052 case IB_WR_RDMA_WRITE:
2053 case IB_WR_RDMA_WRITE_WITH_IMM:
2054 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2055 rdma_wr(wr)->rkey);
2056 wqe += sizeof (struct mthca_raddr_seg);
2057 size += sizeof (struct mthca_raddr_seg) / 16;
2058 break;
2059
2060 default:
2061 /* No extra segments required for sends */
2062 break;
2063 }
2064
2065 break;
2066
2067 case UD:
2068 set_arbel_ud_seg(wqe, ud_wr(wr));
2069 wqe += sizeof (struct mthca_arbel_ud_seg);
2070 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2071 break;
2072
2073 case MLX:
2074 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2075 wqe - sizeof (struct mthca_next_seg),
2076 wqe);
2077 if (err) {
2078 *bad_wr = wr;
2079 goto out;
2080 }
2081 wqe += sizeof (struct mthca_data_seg);
2082 size += sizeof (struct mthca_data_seg) / 16;
2083 break;
2084 }
2085
2086 if (wr->num_sge > qp->sq.max_gs) {
2087 mthca_err(dev, "too many gathers\n");
2088 err = -EINVAL;
2089 *bad_wr = wr;
2090 goto out;
2091 }
2092
2093 for (i = 0; i < wr->num_sge; ++i) {
2094 mthca_set_data_seg(wqe, wr->sg_list + i);
2095 wqe += sizeof (struct mthca_data_seg);
2096 size += sizeof (struct mthca_data_seg) / 16;
2097 }
2098
2099 /* Add one more inline data segment for ICRC */
2100 if (qp->transport == MLX) {
2101 ((struct mthca_data_seg *) wqe)->byte_count =
2102 cpu_to_be32((1 << 31) | 4);
2103 ((u32 *) wqe)[1] = 0;
2104 wqe += sizeof (struct mthca_data_seg);
2105 size += sizeof (struct mthca_data_seg) / 16;
2106 }
2107
2108 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2109
2110 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2111 mthca_err(dev, "opcode invalid\n");
2112 err = -EINVAL;
2113 *bad_wr = wr;
2114 goto out;
2115 }
2116
2117 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2118 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2119 qp->send_wqe_offset) |
2120 mthca_opcode[wr->opcode]);
2121 wmb();
2122 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2123 cpu_to_be32(MTHCA_NEXT_DBD | size |
2124 ((wr->send_flags & IB_SEND_FENCE) ?
2125 MTHCA_NEXT_FENCE : 0));
2126
2127 if (!nreq) {
2128 size0 = size;
2129 op0 = mthca_opcode[wr->opcode];
2130 f0 = wr->send_flags & IB_SEND_FENCE ?
2131 MTHCA_SEND_DOORBELL_FENCE : 0;
2132 }
2133
2134 ++ind;
2135 if (unlikely(ind >= qp->sq.max))
2136 ind -= qp->sq.max;
2137 }
2138
2139 out:
2140 if (likely(nreq)) {
2141 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2142
2143 qp->sq.head += nreq;
2144
2145 /*
2146 * Make sure that descriptors are written before
2147 * doorbell record.
2148 */
2149 wmb();
2150 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2151
2152 /*
2153 * Make sure doorbell record is written before we
2154 * write MMIO send doorbell.
2155 */
2156 wmb();
2157
2158 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2159 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2160 }
2161
2162 /*
2163 * Make sure doorbells don't leak out of SQ spinlock and reach
2164 * the HCA out of order:
2165 */
2166 mmiowb();
2167
2168 spin_unlock_irqrestore(&qp->sq.lock, flags);
2169 return err;
2170 }
2171
2172 int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
2173 const struct ib_recv_wr **bad_wr)
2174 {
2175 struct mthca_dev *dev = to_mdev(ibqp->device);
2176 struct mthca_qp *qp = to_mqp(ibqp);
2177 unsigned long flags;
2178 int err = 0;
2179 int nreq;
2180 int ind;
2181 int i;
2182 void *wqe;
2183
2184 spin_lock_irqsave(&qp->rq.lock, flags);
2185
2186 /* XXX check that state is OK to post receive */
2187
2188 ind = qp->rq.head & (qp->rq.max - 1);
2189
2190 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2191 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2192 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2193 " %d max, %d nreq)\n", qp->qpn,
2194 qp->rq.head, qp->rq.tail,
2195 qp->rq.max, nreq);
2196 err = -ENOMEM;
2197 *bad_wr = wr;
2198 goto out;
2199 }
2200
2201 wqe = get_recv_wqe(qp, ind);
2202
2203 ((struct mthca_next_seg *) wqe)->flags = 0;
2204
2205 wqe += sizeof (struct mthca_next_seg);
2206
2207 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2208 err = -EINVAL;
2209 *bad_wr = wr;
2210 goto out;
2211 }
2212
2213 for (i = 0; i < wr->num_sge; ++i) {
2214 mthca_set_data_seg(wqe, wr->sg_list + i);
2215 wqe += sizeof (struct mthca_data_seg);
2216 }
2217
2218 if (i < qp->rq.max_gs)
2219 mthca_set_data_seg_inval(wqe);
2220
2221 qp->wrid[ind] = wr->wr_id;
2222
2223 ++ind;
2224 if (unlikely(ind >= qp->rq.max))
2225 ind -= qp->rq.max;
2226 }
2227 out:
2228 if (likely(nreq)) {
2229 qp->rq.head += nreq;
2230
2231 /*
2232 * Make sure that descriptors are written before
2233 * doorbell record.
2234 */
2235 wmb();
2236 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2237 }
2238
2239 spin_unlock_irqrestore(&qp->rq.lock, flags);
2240 return err;
2241 }
2242
2243 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2244 int index, int *dbd, __be32 *new_wqe)
2245 {
2246 struct mthca_next_seg *next;
2247
2248 /*
2249 * For SRQs, all receive WQEs generate a CQE, so we're always
2250 * at the end of the doorbell chain.
2251 */
2252 if (qp->ibqp.srq && !is_send) {
2253 *new_wqe = 0;
2254 return;
2255 }
2256
2257 if (is_send)
2258 next = get_send_wqe(qp, index);
2259 else
2260 next = get_recv_wqe(qp, index);
2261
2262 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2263 if (next->ee_nds & cpu_to_be32(0x3f))
2264 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2265 (next->ee_nds & cpu_to_be32(0x3f));
2266 else
2267 *new_wqe = 0;
2268 }
2269
2270 int mthca_init_qp_table(struct mthca_dev *dev)
2271 {
2272 int err;
2273 int i;
2274
2275 spin_lock_init(&dev->qp_table.lock);
2276
2277 /*
2278 * We reserve 2 extra QPs per port for the special QPs. The
2279 * special QP for port 1 has to be even, so round up.
2280 */
2281 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2282 err = mthca_alloc_init(&dev->qp_table.alloc,
2283 dev->limits.num_qps,
2284 (1 << 24) - 1,
2285 dev->qp_table.sqp_start +
2286 MTHCA_MAX_PORTS * 2);
2287 if (err)
2288 return err;
2289
2290 err = mthca_array_init(&dev->qp_table.qp,
2291 dev->limits.num_qps);
2292 if (err) {
2293 mthca_alloc_cleanup(&dev->qp_table.alloc);
2294 return err;
2295 }
2296
2297 for (i = 0; i < 2; ++i) {
2298 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2299 dev->qp_table.sqp_start + i * 2);
2300 if (err) {
2301 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2302 "%d, aborting.\n", err);
2303 goto err_out;
2304 }
2305 }
2306 return 0;
2307
2308 err_out:
2309 for (i = 0; i < 2; ++i)
2310 mthca_CONF_SPECIAL_QP(dev, i, 0);
2311
2312 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2313 mthca_alloc_cleanup(&dev->qp_table.alloc);
2314
2315 return err;
2316 }
2317
2318 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2319 {
2320 int i;
2321
2322 for (i = 0; i < 2; ++i)
2323 mthca_CONF_SPECIAL_QP(dev, i, 0);
2324
2325 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2326 mthca_alloc_cleanup(&dev->qp_table.alloc);
2327 }
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