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Merge tag 'regulator-fix-v5.2-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git...
[mirror_ubuntu-hirsute-kernel.git] / drivers / infiniband / hw / mthca / mthca_qp.c
1 /*
2 * Copyright (c) 2004 Topspin Communications. All rights reserved.
3 * Copyright (c) 2005 Cisco Systems. All rights reserved.
4 * Copyright (c) 2005 Mellanox Technologies. All rights reserved.
5 * Copyright (c) 2004 Voltaire, Inc. All rights reserved.
6 *
7 * This software is available to you under a choice of one of two
8 * licenses. You may choose to be licensed under the terms of the GNU
9 * General Public License (GPL) Version 2, available from the file
10 * COPYING in the main directory of this source tree, or the
11 * OpenIB.org BSD license below:
12 *
13 * Redistribution and use in source and binary forms, with or
14 * without modification, are permitted provided that the following
15 * conditions are met:
16 *
17 * - Redistributions of source code must retain the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer.
20 *
21 * - Redistributions in binary form must reproduce the above
22 * copyright notice, this list of conditions and the following
23 * disclaimer in the documentation and/or other materials
24 * provided with the distribution.
25 *
26 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
27 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
28 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
29 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
30 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
31 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
32 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 * SOFTWARE.
34 */
35
36 #include <linux/string.h>
37 #include <linux/slab.h>
38 #include <linux/sched.h>
39
40 #include <asm/io.h>
41
42 #include <rdma/ib_verbs.h>
43 #include <rdma/ib_cache.h>
44 #include <rdma/ib_pack.h>
45 #include <rdma/uverbs_ioctl.h>
46
47 #include "mthca_dev.h"
48 #include "mthca_cmd.h"
49 #include "mthca_memfree.h"
50 #include "mthca_wqe.h"
51
52 enum {
53 MTHCA_MAX_DIRECT_QP_SIZE = 4 * PAGE_SIZE,
54 MTHCA_ACK_REQ_FREQ = 10,
55 MTHCA_FLIGHT_LIMIT = 9,
56 MTHCA_UD_HEADER_SIZE = 72, /* largest UD header possible */
57 MTHCA_INLINE_HEADER_SIZE = 4, /* data segment overhead for inline */
58 MTHCA_INLINE_CHUNK_SIZE = 16 /* inline data segment chunk */
59 };
60
61 enum {
62 MTHCA_QP_STATE_RST = 0,
63 MTHCA_QP_STATE_INIT = 1,
64 MTHCA_QP_STATE_RTR = 2,
65 MTHCA_QP_STATE_RTS = 3,
66 MTHCA_QP_STATE_SQE = 4,
67 MTHCA_QP_STATE_SQD = 5,
68 MTHCA_QP_STATE_ERR = 6,
69 MTHCA_QP_STATE_DRAINING = 7
70 };
71
72 enum {
73 MTHCA_QP_ST_RC = 0x0,
74 MTHCA_QP_ST_UC = 0x1,
75 MTHCA_QP_ST_RD = 0x2,
76 MTHCA_QP_ST_UD = 0x3,
77 MTHCA_QP_ST_MLX = 0x7
78 };
79
80 enum {
81 MTHCA_QP_PM_MIGRATED = 0x3,
82 MTHCA_QP_PM_ARMED = 0x0,
83 MTHCA_QP_PM_REARM = 0x1
84 };
85
86 enum {
87 /* qp_context flags */
88 MTHCA_QP_BIT_DE = 1 << 8,
89 /* params1 */
90 MTHCA_QP_BIT_SRE = 1 << 15,
91 MTHCA_QP_BIT_SWE = 1 << 14,
92 MTHCA_QP_BIT_SAE = 1 << 13,
93 MTHCA_QP_BIT_SIC = 1 << 4,
94 MTHCA_QP_BIT_SSC = 1 << 3,
95 /* params2 */
96 MTHCA_QP_BIT_RRE = 1 << 15,
97 MTHCA_QP_BIT_RWE = 1 << 14,
98 MTHCA_QP_BIT_RAE = 1 << 13,
99 MTHCA_QP_BIT_RIC = 1 << 4,
100 MTHCA_QP_BIT_RSC = 1 << 3
101 };
102
103 enum {
104 MTHCA_SEND_DOORBELL_FENCE = 1 << 5
105 };
106
107 struct mthca_qp_path {
108 __be32 port_pkey;
109 u8 rnr_retry;
110 u8 g_mylmc;
111 __be16 rlid;
112 u8 ackto;
113 u8 mgid_index;
114 u8 static_rate;
115 u8 hop_limit;
116 __be32 sl_tclass_flowlabel;
117 u8 rgid[16];
118 } __packed;
119
120 struct mthca_qp_context {
121 __be32 flags;
122 __be32 tavor_sched_queue; /* Reserved on Arbel */
123 u8 mtu_msgmax;
124 u8 rq_size_stride; /* Reserved on Tavor */
125 u8 sq_size_stride; /* Reserved on Tavor */
126 u8 rlkey_arbel_sched_queue; /* Reserved on Tavor */
127 __be32 usr_page;
128 __be32 local_qpn;
129 __be32 remote_qpn;
130 u32 reserved1[2];
131 struct mthca_qp_path pri_path;
132 struct mthca_qp_path alt_path;
133 __be32 rdd;
134 __be32 pd;
135 __be32 wqe_base;
136 __be32 wqe_lkey;
137 __be32 params1;
138 __be32 reserved2;
139 __be32 next_send_psn;
140 __be32 cqn_snd;
141 __be32 snd_wqe_base_l; /* Next send WQE on Tavor */
142 __be32 snd_db_index; /* (debugging only entries) */
143 __be32 last_acked_psn;
144 __be32 ssn;
145 __be32 params2;
146 __be32 rnr_nextrecvpsn;
147 __be32 ra_buff_indx;
148 __be32 cqn_rcv;
149 __be32 rcv_wqe_base_l; /* Next recv WQE on Tavor */
150 __be32 rcv_db_index; /* (debugging only entries) */
151 __be32 qkey;
152 __be32 srqn;
153 __be32 rmsn;
154 __be16 rq_wqe_counter; /* reserved on Tavor */
155 __be16 sq_wqe_counter; /* reserved on Tavor */
156 u32 reserved3[18];
157 } __packed;
158
159 struct mthca_qp_param {
160 __be32 opt_param_mask;
161 u32 reserved1;
162 struct mthca_qp_context context;
163 u32 reserved2[62];
164 } __packed;
165
166 enum {
167 MTHCA_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0,
168 MTHCA_QP_OPTPAR_RRE = 1 << 1,
169 MTHCA_QP_OPTPAR_RAE = 1 << 2,
170 MTHCA_QP_OPTPAR_RWE = 1 << 3,
171 MTHCA_QP_OPTPAR_PKEY_INDEX = 1 << 4,
172 MTHCA_QP_OPTPAR_Q_KEY = 1 << 5,
173 MTHCA_QP_OPTPAR_RNR_TIMEOUT = 1 << 6,
174 MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7,
175 MTHCA_QP_OPTPAR_SRA_MAX = 1 << 8,
176 MTHCA_QP_OPTPAR_RRA_MAX = 1 << 9,
177 MTHCA_QP_OPTPAR_PM_STATE = 1 << 10,
178 MTHCA_QP_OPTPAR_PORT_NUM = 1 << 11,
179 MTHCA_QP_OPTPAR_RETRY_COUNT = 1 << 12,
180 MTHCA_QP_OPTPAR_ALT_RNR_RETRY = 1 << 13,
181 MTHCA_QP_OPTPAR_ACK_TIMEOUT = 1 << 14,
182 MTHCA_QP_OPTPAR_RNR_RETRY = 1 << 15,
183 MTHCA_QP_OPTPAR_SCHED_QUEUE = 1 << 16
184 };
185
186 static const u8 mthca_opcode[] = {
187 [IB_WR_SEND] = MTHCA_OPCODE_SEND,
188 [IB_WR_SEND_WITH_IMM] = MTHCA_OPCODE_SEND_IMM,
189 [IB_WR_RDMA_WRITE] = MTHCA_OPCODE_RDMA_WRITE,
190 [IB_WR_RDMA_WRITE_WITH_IMM] = MTHCA_OPCODE_RDMA_WRITE_IMM,
191 [IB_WR_RDMA_READ] = MTHCA_OPCODE_RDMA_READ,
192 [IB_WR_ATOMIC_CMP_AND_SWP] = MTHCA_OPCODE_ATOMIC_CS,
193 [IB_WR_ATOMIC_FETCH_AND_ADD] = MTHCA_OPCODE_ATOMIC_FA,
194 };
195
196 static int is_sqp(struct mthca_dev *dev, struct mthca_qp *qp)
197 {
198 return qp->qpn >= dev->qp_table.sqp_start &&
199 qp->qpn <= dev->qp_table.sqp_start + 3;
200 }
201
202 static int is_qp0(struct mthca_dev *dev, struct mthca_qp *qp)
203 {
204 return qp->qpn >= dev->qp_table.sqp_start &&
205 qp->qpn <= dev->qp_table.sqp_start + 1;
206 }
207
208 static void *get_recv_wqe(struct mthca_qp *qp, int n)
209 {
210 if (qp->is_direct)
211 return qp->queue.direct.buf + (n << qp->rq.wqe_shift);
212 else
213 return qp->queue.page_list[(n << qp->rq.wqe_shift) >> PAGE_SHIFT].buf +
214 ((n << qp->rq.wqe_shift) & (PAGE_SIZE - 1));
215 }
216
217 static void *get_send_wqe(struct mthca_qp *qp, int n)
218 {
219 if (qp->is_direct)
220 return qp->queue.direct.buf + qp->send_wqe_offset +
221 (n << qp->sq.wqe_shift);
222 else
223 return qp->queue.page_list[(qp->send_wqe_offset +
224 (n << qp->sq.wqe_shift)) >>
225 PAGE_SHIFT].buf +
226 ((qp->send_wqe_offset + (n << qp->sq.wqe_shift)) &
227 (PAGE_SIZE - 1));
228 }
229
230 static void mthca_wq_reset(struct mthca_wq *wq)
231 {
232 wq->next_ind = 0;
233 wq->last_comp = wq->max - 1;
234 wq->head = 0;
235 wq->tail = 0;
236 }
237
238 void mthca_qp_event(struct mthca_dev *dev, u32 qpn,
239 enum ib_event_type event_type)
240 {
241 struct mthca_qp *qp;
242 struct ib_event event;
243
244 spin_lock(&dev->qp_table.lock);
245 qp = mthca_array_get(&dev->qp_table.qp, qpn & (dev->limits.num_qps - 1));
246 if (qp)
247 ++qp->refcount;
248 spin_unlock(&dev->qp_table.lock);
249
250 if (!qp) {
251 mthca_warn(dev, "Async event %d for bogus QP %08x\n",
252 event_type, qpn);
253 return;
254 }
255
256 if (event_type == IB_EVENT_PATH_MIG)
257 qp->port = qp->alt_port;
258
259 event.device = &dev->ib_dev;
260 event.event = event_type;
261 event.element.qp = &qp->ibqp;
262 if (qp->ibqp.event_handler)
263 qp->ibqp.event_handler(&event, qp->ibqp.qp_context);
264
265 spin_lock(&dev->qp_table.lock);
266 if (!--qp->refcount)
267 wake_up(&qp->wait);
268 spin_unlock(&dev->qp_table.lock);
269 }
270
271 static int to_mthca_state(enum ib_qp_state ib_state)
272 {
273 switch (ib_state) {
274 case IB_QPS_RESET: return MTHCA_QP_STATE_RST;
275 case IB_QPS_INIT: return MTHCA_QP_STATE_INIT;
276 case IB_QPS_RTR: return MTHCA_QP_STATE_RTR;
277 case IB_QPS_RTS: return MTHCA_QP_STATE_RTS;
278 case IB_QPS_SQD: return MTHCA_QP_STATE_SQD;
279 case IB_QPS_SQE: return MTHCA_QP_STATE_SQE;
280 case IB_QPS_ERR: return MTHCA_QP_STATE_ERR;
281 default: return -1;
282 }
283 }
284
285 enum { RC, UC, UD, RD, RDEE, MLX, NUM_TRANS };
286
287 static int to_mthca_st(int transport)
288 {
289 switch (transport) {
290 case RC: return MTHCA_QP_ST_RC;
291 case UC: return MTHCA_QP_ST_UC;
292 case UD: return MTHCA_QP_ST_UD;
293 case RD: return MTHCA_QP_ST_RD;
294 case MLX: return MTHCA_QP_ST_MLX;
295 default: return -1;
296 }
297 }
298
299 static void store_attrs(struct mthca_sqp *sqp, const struct ib_qp_attr *attr,
300 int attr_mask)
301 {
302 if (attr_mask & IB_QP_PKEY_INDEX)
303 sqp->pkey_index = attr->pkey_index;
304 if (attr_mask & IB_QP_QKEY)
305 sqp->qkey = attr->qkey;
306 if (attr_mask & IB_QP_SQ_PSN)
307 sqp->send_psn = attr->sq_psn;
308 }
309
310 static void init_port(struct mthca_dev *dev, int port)
311 {
312 int err;
313 struct mthca_init_ib_param param;
314
315 memset(&param, 0, sizeof param);
316
317 param.port_width = dev->limits.port_width_cap;
318 param.vl_cap = dev->limits.vl_cap;
319 param.mtu_cap = dev->limits.mtu_cap;
320 param.gid_cap = dev->limits.gid_table_len;
321 param.pkey_cap = dev->limits.pkey_table_len;
322
323 err = mthca_INIT_IB(dev, &param, port);
324 if (err)
325 mthca_warn(dev, "INIT_IB failed, return code %d.\n", err);
326 }
327
328 static __be32 get_hw_access_flags(struct mthca_qp *qp, const struct ib_qp_attr *attr,
329 int attr_mask)
330 {
331 u8 dest_rd_atomic;
332 u32 access_flags;
333 u32 hw_access_flags = 0;
334
335 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
336 dest_rd_atomic = attr->max_dest_rd_atomic;
337 else
338 dest_rd_atomic = qp->resp_depth;
339
340 if (attr_mask & IB_QP_ACCESS_FLAGS)
341 access_flags = attr->qp_access_flags;
342 else
343 access_flags = qp->atomic_rd_en;
344
345 if (!dest_rd_atomic)
346 access_flags &= IB_ACCESS_REMOTE_WRITE;
347
348 if (access_flags & IB_ACCESS_REMOTE_READ)
349 hw_access_flags |= MTHCA_QP_BIT_RRE;
350 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
351 hw_access_flags |= MTHCA_QP_BIT_RAE;
352 if (access_flags & IB_ACCESS_REMOTE_WRITE)
353 hw_access_flags |= MTHCA_QP_BIT_RWE;
354
355 return cpu_to_be32(hw_access_flags);
356 }
357
358 static inline enum ib_qp_state to_ib_qp_state(int mthca_state)
359 {
360 switch (mthca_state) {
361 case MTHCA_QP_STATE_RST: return IB_QPS_RESET;
362 case MTHCA_QP_STATE_INIT: return IB_QPS_INIT;
363 case MTHCA_QP_STATE_RTR: return IB_QPS_RTR;
364 case MTHCA_QP_STATE_RTS: return IB_QPS_RTS;
365 case MTHCA_QP_STATE_DRAINING:
366 case MTHCA_QP_STATE_SQD: return IB_QPS_SQD;
367 case MTHCA_QP_STATE_SQE: return IB_QPS_SQE;
368 case MTHCA_QP_STATE_ERR: return IB_QPS_ERR;
369 default: return -1;
370 }
371 }
372
373 static inline enum ib_mig_state to_ib_mig_state(int mthca_mig_state)
374 {
375 switch (mthca_mig_state) {
376 case 0: return IB_MIG_ARMED;
377 case 1: return IB_MIG_REARM;
378 case 3: return IB_MIG_MIGRATED;
379 default: return -1;
380 }
381 }
382
383 static int to_ib_qp_access_flags(int mthca_flags)
384 {
385 int ib_flags = 0;
386
387 if (mthca_flags & MTHCA_QP_BIT_RRE)
388 ib_flags |= IB_ACCESS_REMOTE_READ;
389 if (mthca_flags & MTHCA_QP_BIT_RWE)
390 ib_flags |= IB_ACCESS_REMOTE_WRITE;
391 if (mthca_flags & MTHCA_QP_BIT_RAE)
392 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
393
394 return ib_flags;
395 }
396
397 static void to_rdma_ah_attr(struct mthca_dev *dev,
398 struct rdma_ah_attr *ah_attr,
399 struct mthca_qp_path *path)
400 {
401 u8 port_num = (be32_to_cpu(path->port_pkey) >> 24) & 0x3;
402
403 memset(ah_attr, 0, sizeof(*ah_attr));
404
405 if (port_num == 0 || port_num > dev->limits.num_ports)
406 return;
407 ah_attr->type = rdma_ah_find_type(&dev->ib_dev, port_num);
408 rdma_ah_set_port_num(ah_attr, port_num);
409
410 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
411 rdma_ah_set_sl(ah_attr, be32_to_cpu(path->sl_tclass_flowlabel) >> 28);
412 rdma_ah_set_path_bits(ah_attr, path->g_mylmc & 0x7f);
413 rdma_ah_set_static_rate(ah_attr,
414 mthca_rate_to_ib(dev,
415 path->static_rate & 0xf,
416 port_num));
417 if (path->g_mylmc & (1 << 7)) {
418 u32 tc_fl = be32_to_cpu(path->sl_tclass_flowlabel);
419
420 rdma_ah_set_grh(ah_attr, NULL,
421 tc_fl & 0xfffff,
422 path->mgid_index &
423 (dev->limits.gid_table_len - 1),
424 path->hop_limit,
425 (tc_fl >> 20) & 0xff);
426 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
427 }
428 }
429
430 int mthca_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
431 struct ib_qp_init_attr *qp_init_attr)
432 {
433 struct mthca_dev *dev = to_mdev(ibqp->device);
434 struct mthca_qp *qp = to_mqp(ibqp);
435 int err = 0;
436 struct mthca_mailbox *mailbox = NULL;
437 struct mthca_qp_param *qp_param;
438 struct mthca_qp_context *context;
439 int mthca_state;
440
441 mutex_lock(&qp->mutex);
442
443 if (qp->state == IB_QPS_RESET) {
444 qp_attr->qp_state = IB_QPS_RESET;
445 goto done;
446 }
447
448 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
449 if (IS_ERR(mailbox)) {
450 err = PTR_ERR(mailbox);
451 goto out;
452 }
453
454 err = mthca_QUERY_QP(dev, qp->qpn, 0, mailbox);
455 if (err) {
456 mthca_warn(dev, "QUERY_QP failed (%d)\n", err);
457 goto out_mailbox;
458 }
459
460 qp_param = mailbox->buf;
461 context = &qp_param->context;
462 mthca_state = be32_to_cpu(context->flags) >> 28;
463
464 qp->state = to_ib_qp_state(mthca_state);
465 qp_attr->qp_state = qp->state;
466 qp_attr->path_mtu = context->mtu_msgmax >> 5;
467 qp_attr->path_mig_state =
468 to_ib_mig_state((be32_to_cpu(context->flags) >> 11) & 0x3);
469 qp_attr->qkey = be32_to_cpu(context->qkey);
470 qp_attr->rq_psn = be32_to_cpu(context->rnr_nextrecvpsn) & 0xffffff;
471 qp_attr->sq_psn = be32_to_cpu(context->next_send_psn) & 0xffffff;
472 qp_attr->dest_qp_num = be32_to_cpu(context->remote_qpn) & 0xffffff;
473 qp_attr->qp_access_flags =
474 to_ib_qp_access_flags(be32_to_cpu(context->params2));
475
476 if (qp->transport == RC || qp->transport == UC) {
477 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context->pri_path);
478 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context->alt_path);
479 qp_attr->alt_pkey_index =
480 be32_to_cpu(context->alt_path.port_pkey) & 0x7f;
481 qp_attr->alt_port_num =
482 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
483 }
484
485 qp_attr->pkey_index = be32_to_cpu(context->pri_path.port_pkey) & 0x7f;
486 qp_attr->port_num =
487 (be32_to_cpu(context->pri_path.port_pkey) >> 24) & 0x3;
488
489 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
490 qp_attr->sq_draining = mthca_state == MTHCA_QP_STATE_DRAINING;
491
492 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context->params1) >> 21) & 0x7);
493
494 qp_attr->max_dest_rd_atomic =
495 1 << ((be32_to_cpu(context->params2) >> 21) & 0x7);
496 qp_attr->min_rnr_timer =
497 (be32_to_cpu(context->rnr_nextrecvpsn) >> 24) & 0x1f;
498 qp_attr->timeout = context->pri_path.ackto >> 3;
499 qp_attr->retry_cnt = (be32_to_cpu(context->params1) >> 16) & 0x7;
500 qp_attr->rnr_retry = context->pri_path.rnr_retry >> 5;
501 qp_attr->alt_timeout = context->alt_path.ackto >> 3;
502
503 done:
504 qp_attr->cur_qp_state = qp_attr->qp_state;
505 qp_attr->cap.max_send_wr = qp->sq.max;
506 qp_attr->cap.max_recv_wr = qp->rq.max;
507 qp_attr->cap.max_send_sge = qp->sq.max_gs;
508 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
509 qp_attr->cap.max_inline_data = qp->max_inline_data;
510
511 qp_init_attr->cap = qp_attr->cap;
512 qp_init_attr->sq_sig_type = qp->sq_policy;
513
514 out_mailbox:
515 mthca_free_mailbox(dev, mailbox);
516
517 out:
518 mutex_unlock(&qp->mutex);
519 return err;
520 }
521
522 static int mthca_path_set(struct mthca_dev *dev, const struct rdma_ah_attr *ah,
523 struct mthca_qp_path *path, u8 port)
524 {
525 path->g_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
526 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
527 path->static_rate = mthca_get_rate(dev, rdma_ah_get_static_rate(ah),
528 port);
529
530 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
531 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
532
533 if (grh->sgid_index >= dev->limits.gid_table_len) {
534 mthca_dbg(dev, "sgid_index (%u) too large. max is %d\n",
535 grh->sgid_index,
536 dev->limits.gid_table_len - 1);
537 return -1;
538 }
539
540 path->g_mylmc |= 1 << 7;
541 path->mgid_index = grh->sgid_index;
542 path->hop_limit = grh->hop_limit;
543 path->sl_tclass_flowlabel =
544 cpu_to_be32((rdma_ah_get_sl(ah) << 28) |
545 (grh->traffic_class << 20) |
546 (grh->flow_label));
547 memcpy(path->rgid, grh->dgid.raw, 16);
548 } else {
549 path->sl_tclass_flowlabel = cpu_to_be32(rdma_ah_get_sl(ah) <<
550 28);
551 }
552
553 return 0;
554 }
555
556 static int __mthca_modify_qp(struct ib_qp *ibqp,
557 const struct ib_qp_attr *attr, int attr_mask,
558 enum ib_qp_state cur_state,
559 enum ib_qp_state new_state,
560 struct ib_udata *udata)
561 {
562 struct mthca_dev *dev = to_mdev(ibqp->device);
563 struct mthca_qp *qp = to_mqp(ibqp);
564 struct mthca_ucontext *context = rdma_udata_to_drv_context(
565 udata, struct mthca_ucontext, ibucontext);
566 struct mthca_mailbox *mailbox;
567 struct mthca_qp_param *qp_param;
568 struct mthca_qp_context *qp_context;
569 u32 sqd_event = 0;
570 int err = -EINVAL;
571
572 mailbox = mthca_alloc_mailbox(dev, GFP_KERNEL);
573 if (IS_ERR(mailbox)) {
574 err = PTR_ERR(mailbox);
575 goto out;
576 }
577 qp_param = mailbox->buf;
578 qp_context = &qp_param->context;
579 memset(qp_param, 0, sizeof *qp_param);
580
581 qp_context->flags = cpu_to_be32((to_mthca_state(new_state) << 28) |
582 (to_mthca_st(qp->transport) << 16));
583 qp_context->flags |= cpu_to_be32(MTHCA_QP_BIT_DE);
584 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
585 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
586 else {
587 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PM_STATE);
588 switch (attr->path_mig_state) {
589 case IB_MIG_MIGRATED:
590 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_MIGRATED << 11);
591 break;
592 case IB_MIG_REARM:
593 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_REARM << 11);
594 break;
595 case IB_MIG_ARMED:
596 qp_context->flags |= cpu_to_be32(MTHCA_QP_PM_ARMED << 11);
597 break;
598 }
599 }
600
601 /* leave tavor_sched_queue as 0 */
602
603 if (qp->transport == MLX || qp->transport == UD)
604 qp_context->mtu_msgmax = (IB_MTU_2048 << 5) | 11;
605 else if (attr_mask & IB_QP_PATH_MTU) {
606 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_2048) {
607 mthca_dbg(dev, "path MTU (%u) is invalid\n",
608 attr->path_mtu);
609 goto out_mailbox;
610 }
611 qp_context->mtu_msgmax = (attr->path_mtu << 5) | 31;
612 }
613
614 if (mthca_is_memfree(dev)) {
615 if (qp->rq.max)
616 qp_context->rq_size_stride = ilog2(qp->rq.max) << 3;
617 qp_context->rq_size_stride |= qp->rq.wqe_shift - 4;
618
619 if (qp->sq.max)
620 qp_context->sq_size_stride = ilog2(qp->sq.max) << 3;
621 qp_context->sq_size_stride |= qp->sq.wqe_shift - 4;
622 }
623
624 /* leave arbel_sched_queue as 0 */
625
626 if (qp->ibqp.uobject)
627 qp_context->usr_page = cpu_to_be32(context->uar.index);
628 else
629 qp_context->usr_page = cpu_to_be32(dev->driver_uar.index);
630 qp_context->local_qpn = cpu_to_be32(qp->qpn);
631 if (attr_mask & IB_QP_DEST_QPN) {
632 qp_context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
633 }
634
635 if (qp->transport == MLX)
636 qp_context->pri_path.port_pkey |=
637 cpu_to_be32(qp->port << 24);
638 else {
639 if (attr_mask & IB_QP_PORT) {
640 qp_context->pri_path.port_pkey |=
641 cpu_to_be32(attr->port_num << 24);
642 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PORT_NUM);
643 }
644 }
645
646 if (attr_mask & IB_QP_PKEY_INDEX) {
647 qp_context->pri_path.port_pkey |=
648 cpu_to_be32(attr->pkey_index);
649 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PKEY_INDEX);
650 }
651
652 if (attr_mask & IB_QP_RNR_RETRY) {
653 qp_context->alt_path.rnr_retry = qp_context->pri_path.rnr_retry =
654 attr->rnr_retry << 5;
655 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_RETRY |
656 MTHCA_QP_OPTPAR_ALT_RNR_RETRY);
657 }
658
659 if (attr_mask & IB_QP_AV) {
660 if (mthca_path_set(dev, &attr->ah_attr, &qp_context->pri_path,
661 attr_mask & IB_QP_PORT ? attr->port_num : qp->port))
662 goto out_mailbox;
663
664 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_PRIMARY_ADDR_PATH);
665 }
666
667 if (ibqp->qp_type == IB_QPT_RC &&
668 cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
669 u8 sched_queue = ibqp->uobject ? 0x2 : 0x1;
670
671 if (mthca_is_memfree(dev))
672 qp_context->rlkey_arbel_sched_queue |= sched_queue;
673 else
674 qp_context->tavor_sched_queue |= cpu_to_be32(sched_queue);
675
676 qp_param->opt_param_mask |=
677 cpu_to_be32(MTHCA_QP_OPTPAR_SCHED_QUEUE);
678 }
679
680 if (attr_mask & IB_QP_TIMEOUT) {
681 qp_context->pri_path.ackto = attr->timeout << 3;
682 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ACK_TIMEOUT);
683 }
684
685 if (attr_mask & IB_QP_ALT_PATH) {
686 if (attr->alt_pkey_index >= dev->limits.pkey_table_len) {
687 mthca_dbg(dev, "Alternate P_Key index (%u) too large. max is %d\n",
688 attr->alt_pkey_index, dev->limits.pkey_table_len-1);
689 goto out_mailbox;
690 }
691
692 if (attr->alt_port_num == 0 || attr->alt_port_num > dev->limits.num_ports) {
693 mthca_dbg(dev, "Alternate port number (%u) is invalid\n",
694 attr->alt_port_num);
695 goto out_mailbox;
696 }
697
698 if (mthca_path_set(dev, &attr->alt_ah_attr, &qp_context->alt_path,
699 rdma_ah_get_port_num(&attr->alt_ah_attr)))
700 goto out_mailbox;
701
702 qp_context->alt_path.port_pkey |= cpu_to_be32(attr->alt_pkey_index |
703 attr->alt_port_num << 24);
704 qp_context->alt_path.ackto = attr->alt_timeout << 3;
705 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_ALT_ADDR_PATH);
706 }
707
708 /* leave rdd as 0 */
709 qp_context->pd = cpu_to_be32(to_mpd(ibqp->pd)->pd_num);
710 /* leave wqe_base as 0 (we always create an MR based at 0 for WQs) */
711 qp_context->wqe_lkey = cpu_to_be32(qp->mr.ibmr.lkey);
712 qp_context->params1 = cpu_to_be32((MTHCA_ACK_REQ_FREQ << 28) |
713 (MTHCA_FLIGHT_LIMIT << 24) |
714 MTHCA_QP_BIT_SWE);
715 if (qp->sq_policy == IB_SIGNAL_ALL_WR)
716 qp_context->params1 |= cpu_to_be32(MTHCA_QP_BIT_SSC);
717 if (attr_mask & IB_QP_RETRY_CNT) {
718 qp_context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
719 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RETRY_COUNT);
720 }
721
722 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
723 if (attr->max_rd_atomic) {
724 qp_context->params1 |=
725 cpu_to_be32(MTHCA_QP_BIT_SRE |
726 MTHCA_QP_BIT_SAE);
727 qp_context->params1 |=
728 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
729 }
730 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_SRA_MAX);
731 }
732
733 if (attr_mask & IB_QP_SQ_PSN)
734 qp_context->next_send_psn = cpu_to_be32(attr->sq_psn);
735 qp_context->cqn_snd = cpu_to_be32(to_mcq(ibqp->send_cq)->cqn);
736
737 if (mthca_is_memfree(dev)) {
738 qp_context->snd_wqe_base_l = cpu_to_be32(qp->send_wqe_offset);
739 qp_context->snd_db_index = cpu_to_be32(qp->sq.db_index);
740 }
741
742 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
743 if (attr->max_dest_rd_atomic)
744 qp_context->params2 |=
745 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
746
747 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RRA_MAX);
748 }
749
750 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
751 qp_context->params2 |= get_hw_access_flags(qp, attr, attr_mask);
752 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RWE |
753 MTHCA_QP_OPTPAR_RRE |
754 MTHCA_QP_OPTPAR_RAE);
755 }
756
757 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RSC);
758
759 if (ibqp->srq)
760 qp_context->params2 |= cpu_to_be32(MTHCA_QP_BIT_RIC);
761
762 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
763 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
764 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_RNR_TIMEOUT);
765 }
766 if (attr_mask & IB_QP_RQ_PSN)
767 qp_context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
768
769 qp_context->ra_buff_indx =
770 cpu_to_be32(dev->qp_table.rdb_base +
771 ((qp->qpn & (dev->limits.num_qps - 1)) * MTHCA_RDB_ENTRY_SIZE <<
772 dev->qp_table.rdb_shift));
773
774 qp_context->cqn_rcv = cpu_to_be32(to_mcq(ibqp->recv_cq)->cqn);
775
776 if (mthca_is_memfree(dev))
777 qp_context->rcv_db_index = cpu_to_be32(qp->rq.db_index);
778
779 if (attr_mask & IB_QP_QKEY) {
780 qp_context->qkey = cpu_to_be32(attr->qkey);
781 qp_param->opt_param_mask |= cpu_to_be32(MTHCA_QP_OPTPAR_Q_KEY);
782 }
783
784 if (ibqp->srq)
785 qp_context->srqn = cpu_to_be32(1 << 24 |
786 to_msrq(ibqp->srq)->srqn);
787
788 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
789 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY &&
790 attr->en_sqd_async_notify)
791 sqd_event = 1 << 31;
792
793 err = mthca_MODIFY_QP(dev, cur_state, new_state, qp->qpn, 0,
794 mailbox, sqd_event);
795 if (err) {
796 mthca_warn(dev, "modify QP %d->%d returned %d.\n",
797 cur_state, new_state, err);
798 goto out_mailbox;
799 }
800
801 qp->state = new_state;
802 if (attr_mask & IB_QP_ACCESS_FLAGS)
803 qp->atomic_rd_en = attr->qp_access_flags;
804 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
805 qp->resp_depth = attr->max_dest_rd_atomic;
806 if (attr_mask & IB_QP_PORT)
807 qp->port = attr->port_num;
808 if (attr_mask & IB_QP_ALT_PATH)
809 qp->alt_port = attr->alt_port_num;
810
811 if (is_sqp(dev, qp))
812 store_attrs(to_msqp(qp), attr, attr_mask);
813
814 /*
815 * If we moved QP0 to RTR, bring the IB link up; if we moved
816 * QP0 to RESET or ERROR, bring the link back down.
817 */
818 if (is_qp0(dev, qp)) {
819 if (cur_state != IB_QPS_RTR &&
820 new_state == IB_QPS_RTR)
821 init_port(dev, qp->port);
822
823 if (cur_state != IB_QPS_RESET &&
824 cur_state != IB_QPS_ERR &&
825 (new_state == IB_QPS_RESET ||
826 new_state == IB_QPS_ERR))
827 mthca_CLOSE_IB(dev, qp->port);
828 }
829
830 /*
831 * If we moved a kernel QP to RESET, clean up all old CQ
832 * entries and reinitialize the QP.
833 */
834 if (new_state == IB_QPS_RESET && !qp->ibqp.uobject) {
835 mthca_cq_clean(dev, to_mcq(qp->ibqp.recv_cq), qp->qpn,
836 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
837 if (qp->ibqp.send_cq != qp->ibqp.recv_cq)
838 mthca_cq_clean(dev, to_mcq(qp->ibqp.send_cq), qp->qpn, NULL);
839
840 mthca_wq_reset(&qp->sq);
841 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
842
843 mthca_wq_reset(&qp->rq);
844 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
845
846 if (mthca_is_memfree(dev)) {
847 *qp->sq.db = 0;
848 *qp->rq.db = 0;
849 }
850 }
851
852 out_mailbox:
853 mthca_free_mailbox(dev, mailbox);
854 out:
855 return err;
856 }
857
858 int mthca_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask,
859 struct ib_udata *udata)
860 {
861 struct mthca_dev *dev = to_mdev(ibqp->device);
862 struct mthca_qp *qp = to_mqp(ibqp);
863 enum ib_qp_state cur_state, new_state;
864 int err = -EINVAL;
865
866 mutex_lock(&qp->mutex);
867 if (attr_mask & IB_QP_CUR_STATE) {
868 cur_state = attr->cur_qp_state;
869 } else {
870 spin_lock_irq(&qp->sq.lock);
871 spin_lock(&qp->rq.lock);
872 cur_state = qp->state;
873 spin_unlock(&qp->rq.lock);
874 spin_unlock_irq(&qp->sq.lock);
875 }
876
877 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
878
879 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
880 attr_mask)) {
881 mthca_dbg(dev, "Bad QP transition (transport %d) "
882 "%d->%d with attr 0x%08x\n",
883 qp->transport, cur_state, new_state,
884 attr_mask);
885 goto out;
886 }
887
888 if ((attr_mask & IB_QP_PKEY_INDEX) &&
889 attr->pkey_index >= dev->limits.pkey_table_len) {
890 mthca_dbg(dev, "P_Key index (%u) too large. max is %d\n",
891 attr->pkey_index, dev->limits.pkey_table_len-1);
892 goto out;
893 }
894
895 if ((attr_mask & IB_QP_PORT) &&
896 (attr->port_num == 0 || attr->port_num > dev->limits.num_ports)) {
897 mthca_dbg(dev, "Port number (%u) is invalid\n", attr->port_num);
898 goto out;
899 }
900
901 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
902 attr->max_rd_atomic > dev->limits.max_qp_init_rdma) {
903 mthca_dbg(dev, "Max rdma_atomic as initiator %u too large (max is %d)\n",
904 attr->max_rd_atomic, dev->limits.max_qp_init_rdma);
905 goto out;
906 }
907
908 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
909 attr->max_dest_rd_atomic > 1 << dev->qp_table.rdb_shift) {
910 mthca_dbg(dev, "Max rdma_atomic as responder %u too large (max %d)\n",
911 attr->max_dest_rd_atomic, 1 << dev->qp_table.rdb_shift);
912 goto out;
913 }
914
915 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
916 err = 0;
917 goto out;
918 }
919
920 err = __mthca_modify_qp(ibqp, attr, attr_mask, cur_state, new_state,
921 udata);
922
923 out:
924 mutex_unlock(&qp->mutex);
925 return err;
926 }
927
928 static int mthca_max_data_size(struct mthca_dev *dev, struct mthca_qp *qp, int desc_sz)
929 {
930 /*
931 * Calculate the maximum size of WQE s/g segments, excluding
932 * the next segment and other non-data segments.
933 */
934 int max_data_size = desc_sz - sizeof (struct mthca_next_seg);
935
936 switch (qp->transport) {
937 case MLX:
938 max_data_size -= 2 * sizeof (struct mthca_data_seg);
939 break;
940
941 case UD:
942 if (mthca_is_memfree(dev))
943 max_data_size -= sizeof (struct mthca_arbel_ud_seg);
944 else
945 max_data_size -= sizeof (struct mthca_tavor_ud_seg);
946 break;
947
948 default:
949 max_data_size -= sizeof (struct mthca_raddr_seg);
950 break;
951 }
952
953 return max_data_size;
954 }
955
956 static inline int mthca_max_inline_data(struct mthca_pd *pd, int max_data_size)
957 {
958 /* We don't support inline data for kernel QPs (yet). */
959 return pd->ibpd.uobject ? max_data_size - MTHCA_INLINE_HEADER_SIZE : 0;
960 }
961
962 static void mthca_adjust_qp_caps(struct mthca_dev *dev,
963 struct mthca_pd *pd,
964 struct mthca_qp *qp)
965 {
966 int max_data_size = mthca_max_data_size(dev, qp,
967 min(dev->limits.max_desc_sz,
968 1 << qp->sq.wqe_shift));
969
970 qp->max_inline_data = mthca_max_inline_data(pd, max_data_size);
971
972 qp->sq.max_gs = min_t(int, dev->limits.max_sg,
973 max_data_size / sizeof (struct mthca_data_seg));
974 qp->rq.max_gs = min_t(int, dev->limits.max_sg,
975 (min(dev->limits.max_desc_sz, 1 << qp->rq.wqe_shift) -
976 sizeof (struct mthca_next_seg)) /
977 sizeof (struct mthca_data_seg));
978 }
979
980 /*
981 * Allocate and register buffer for WQEs. qp->rq.max, sq.max,
982 * rq.max_gs and sq.max_gs must all be assigned.
983 * mthca_alloc_wqe_buf will calculate rq.wqe_shift and
984 * sq.wqe_shift (as well as send_wqe_offset, is_direct, and
985 * queue)
986 */
987 static int mthca_alloc_wqe_buf(struct mthca_dev *dev,
988 struct mthca_pd *pd,
989 struct mthca_qp *qp,
990 struct ib_udata *udata)
991 {
992 int size;
993 int err = -ENOMEM;
994
995 size = sizeof (struct mthca_next_seg) +
996 qp->rq.max_gs * sizeof (struct mthca_data_seg);
997
998 if (size > dev->limits.max_desc_sz)
999 return -EINVAL;
1000
1001 for (qp->rq.wqe_shift = 6; 1 << qp->rq.wqe_shift < size;
1002 qp->rq.wqe_shift++)
1003 ; /* nothing */
1004
1005 size = qp->sq.max_gs * sizeof (struct mthca_data_seg);
1006 switch (qp->transport) {
1007 case MLX:
1008 size += 2 * sizeof (struct mthca_data_seg);
1009 break;
1010
1011 case UD:
1012 size += mthca_is_memfree(dev) ?
1013 sizeof (struct mthca_arbel_ud_seg) :
1014 sizeof (struct mthca_tavor_ud_seg);
1015 break;
1016
1017 case UC:
1018 size += sizeof (struct mthca_raddr_seg);
1019 break;
1020
1021 case RC:
1022 size += sizeof (struct mthca_raddr_seg);
1023 /*
1024 * An atomic op will require an atomic segment, a
1025 * remote address segment and one scatter entry.
1026 */
1027 size = max_t(int, size,
1028 sizeof (struct mthca_atomic_seg) +
1029 sizeof (struct mthca_raddr_seg) +
1030 sizeof (struct mthca_data_seg));
1031 break;
1032
1033 default:
1034 break;
1035 }
1036
1037 /* Make sure that we have enough space for a bind request */
1038 size = max_t(int, size, sizeof (struct mthca_bind_seg));
1039
1040 size += sizeof (struct mthca_next_seg);
1041
1042 if (size > dev->limits.max_desc_sz)
1043 return -EINVAL;
1044
1045 for (qp->sq.wqe_shift = 6; 1 << qp->sq.wqe_shift < size;
1046 qp->sq.wqe_shift++)
1047 ; /* nothing */
1048
1049 qp->send_wqe_offset = ALIGN(qp->rq.max << qp->rq.wqe_shift,
1050 1 << qp->sq.wqe_shift);
1051
1052 /*
1053 * If this is a userspace QP, we don't actually have to
1054 * allocate anything. All we need is to calculate the WQE
1055 * sizes and the send_wqe_offset, so we're done now.
1056 */
1057 if (udata)
1058 return 0;
1059
1060 size = PAGE_ALIGN(qp->send_wqe_offset +
1061 (qp->sq.max << qp->sq.wqe_shift));
1062
1063 qp->wrid = kmalloc_array(qp->rq.max + qp->sq.max, sizeof(u64),
1064 GFP_KERNEL);
1065 if (!qp->wrid)
1066 goto err_out;
1067
1068 err = mthca_buf_alloc(dev, size, MTHCA_MAX_DIRECT_QP_SIZE,
1069 &qp->queue, &qp->is_direct, pd, 0, &qp->mr);
1070 if (err)
1071 goto err_out;
1072
1073 return 0;
1074
1075 err_out:
1076 kfree(qp->wrid);
1077 return err;
1078 }
1079
1080 static void mthca_free_wqe_buf(struct mthca_dev *dev,
1081 struct mthca_qp *qp)
1082 {
1083 mthca_buf_free(dev, PAGE_ALIGN(qp->send_wqe_offset +
1084 (qp->sq.max << qp->sq.wqe_shift)),
1085 &qp->queue, qp->is_direct, &qp->mr);
1086 kfree(qp->wrid);
1087 }
1088
1089 static int mthca_map_memfree(struct mthca_dev *dev,
1090 struct mthca_qp *qp)
1091 {
1092 int ret;
1093
1094 if (mthca_is_memfree(dev)) {
1095 ret = mthca_table_get(dev, dev->qp_table.qp_table, qp->qpn);
1096 if (ret)
1097 return ret;
1098
1099 ret = mthca_table_get(dev, dev->qp_table.eqp_table, qp->qpn);
1100 if (ret)
1101 goto err_qpc;
1102
1103 ret = mthca_table_get(dev, dev->qp_table.rdb_table,
1104 qp->qpn << dev->qp_table.rdb_shift);
1105 if (ret)
1106 goto err_eqpc;
1107
1108 }
1109
1110 return 0;
1111
1112 err_eqpc:
1113 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1114
1115 err_qpc:
1116 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1117
1118 return ret;
1119 }
1120
1121 static void mthca_unmap_memfree(struct mthca_dev *dev,
1122 struct mthca_qp *qp)
1123 {
1124 mthca_table_put(dev, dev->qp_table.rdb_table,
1125 qp->qpn << dev->qp_table.rdb_shift);
1126 mthca_table_put(dev, dev->qp_table.eqp_table, qp->qpn);
1127 mthca_table_put(dev, dev->qp_table.qp_table, qp->qpn);
1128 }
1129
1130 static int mthca_alloc_memfree(struct mthca_dev *dev,
1131 struct mthca_qp *qp)
1132 {
1133 if (mthca_is_memfree(dev)) {
1134 qp->rq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_RQ,
1135 qp->qpn, &qp->rq.db);
1136 if (qp->rq.db_index < 0)
1137 return -ENOMEM;
1138
1139 qp->sq.db_index = mthca_alloc_db(dev, MTHCA_DB_TYPE_SQ,
1140 qp->qpn, &qp->sq.db);
1141 if (qp->sq.db_index < 0) {
1142 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1143 return -ENOMEM;
1144 }
1145 }
1146
1147 return 0;
1148 }
1149
1150 static void mthca_free_memfree(struct mthca_dev *dev,
1151 struct mthca_qp *qp)
1152 {
1153 if (mthca_is_memfree(dev)) {
1154 mthca_free_db(dev, MTHCA_DB_TYPE_SQ, qp->sq.db_index);
1155 mthca_free_db(dev, MTHCA_DB_TYPE_RQ, qp->rq.db_index);
1156 }
1157 }
1158
1159 static int mthca_alloc_qp_common(struct mthca_dev *dev,
1160 struct mthca_pd *pd,
1161 struct mthca_cq *send_cq,
1162 struct mthca_cq *recv_cq,
1163 enum ib_sig_type send_policy,
1164 struct mthca_qp *qp,
1165 struct ib_udata *udata)
1166 {
1167 int ret;
1168 int i;
1169 struct mthca_next_seg *next;
1170
1171 qp->refcount = 1;
1172 init_waitqueue_head(&qp->wait);
1173 mutex_init(&qp->mutex);
1174 qp->state = IB_QPS_RESET;
1175 qp->atomic_rd_en = 0;
1176 qp->resp_depth = 0;
1177 qp->sq_policy = send_policy;
1178 mthca_wq_reset(&qp->sq);
1179 mthca_wq_reset(&qp->rq);
1180
1181 spin_lock_init(&qp->sq.lock);
1182 spin_lock_init(&qp->rq.lock);
1183
1184 ret = mthca_map_memfree(dev, qp);
1185 if (ret)
1186 return ret;
1187
1188 ret = mthca_alloc_wqe_buf(dev, pd, qp, udata);
1189 if (ret) {
1190 mthca_unmap_memfree(dev, qp);
1191 return ret;
1192 }
1193
1194 mthca_adjust_qp_caps(dev, pd, qp);
1195
1196 /*
1197 * If this is a userspace QP, we're done now. The doorbells
1198 * will be allocated and buffers will be initialized in
1199 * userspace.
1200 */
1201 if (udata)
1202 return 0;
1203
1204 ret = mthca_alloc_memfree(dev, qp);
1205 if (ret) {
1206 mthca_free_wqe_buf(dev, qp);
1207 mthca_unmap_memfree(dev, qp);
1208 return ret;
1209 }
1210
1211 if (mthca_is_memfree(dev)) {
1212 struct mthca_data_seg *scatter;
1213 int size = (sizeof (struct mthca_next_seg) +
1214 qp->rq.max_gs * sizeof (struct mthca_data_seg)) / 16;
1215
1216 for (i = 0; i < qp->rq.max; ++i) {
1217 next = get_recv_wqe(qp, i);
1218 next->nda_op = cpu_to_be32(((i + 1) & (qp->rq.max - 1)) <<
1219 qp->rq.wqe_shift);
1220 next->ee_nds = cpu_to_be32(size);
1221
1222 for (scatter = (void *) (next + 1);
1223 (void *) scatter < (void *) next + (1 << qp->rq.wqe_shift);
1224 ++scatter)
1225 scatter->lkey = cpu_to_be32(MTHCA_INVAL_LKEY);
1226 }
1227
1228 for (i = 0; i < qp->sq.max; ++i) {
1229 next = get_send_wqe(qp, i);
1230 next->nda_op = cpu_to_be32((((i + 1) & (qp->sq.max - 1)) <<
1231 qp->sq.wqe_shift) +
1232 qp->send_wqe_offset);
1233 }
1234 } else {
1235 for (i = 0; i < qp->rq.max; ++i) {
1236 next = get_recv_wqe(qp, i);
1237 next->nda_op = htonl((((i + 1) % qp->rq.max) <<
1238 qp->rq.wqe_shift) | 1);
1239 }
1240
1241 }
1242
1243 qp->sq.last = get_send_wqe(qp, qp->sq.max - 1);
1244 qp->rq.last = get_recv_wqe(qp, qp->rq.max - 1);
1245
1246 return 0;
1247 }
1248
1249 static int mthca_set_qp_size(struct mthca_dev *dev, struct ib_qp_cap *cap,
1250 struct mthca_pd *pd, struct mthca_qp *qp)
1251 {
1252 int max_data_size = mthca_max_data_size(dev, qp, dev->limits.max_desc_sz);
1253
1254 /* Sanity check QP size before proceeding */
1255 if (cap->max_send_wr > dev->limits.max_wqes ||
1256 cap->max_recv_wr > dev->limits.max_wqes ||
1257 cap->max_send_sge > dev->limits.max_sg ||
1258 cap->max_recv_sge > dev->limits.max_sg ||
1259 cap->max_inline_data > mthca_max_inline_data(pd, max_data_size))
1260 return -EINVAL;
1261
1262 /*
1263 * For MLX transport we need 2 extra send gather entries:
1264 * one for the header and one for the checksum at the end
1265 */
1266 if (qp->transport == MLX && cap->max_send_sge + 2 > dev->limits.max_sg)
1267 return -EINVAL;
1268
1269 if (mthca_is_memfree(dev)) {
1270 qp->rq.max = cap->max_recv_wr ?
1271 roundup_pow_of_two(cap->max_recv_wr) : 0;
1272 qp->sq.max = cap->max_send_wr ?
1273 roundup_pow_of_two(cap->max_send_wr) : 0;
1274 } else {
1275 qp->rq.max = cap->max_recv_wr;
1276 qp->sq.max = cap->max_send_wr;
1277 }
1278
1279 qp->rq.max_gs = cap->max_recv_sge;
1280 qp->sq.max_gs = max_t(int, cap->max_send_sge,
1281 ALIGN(cap->max_inline_data + MTHCA_INLINE_HEADER_SIZE,
1282 MTHCA_INLINE_CHUNK_SIZE) /
1283 sizeof (struct mthca_data_seg));
1284
1285 return 0;
1286 }
1287
1288 int mthca_alloc_qp(struct mthca_dev *dev,
1289 struct mthca_pd *pd,
1290 struct mthca_cq *send_cq,
1291 struct mthca_cq *recv_cq,
1292 enum ib_qp_type type,
1293 enum ib_sig_type send_policy,
1294 struct ib_qp_cap *cap,
1295 struct mthca_qp *qp,
1296 struct ib_udata *udata)
1297 {
1298 int err;
1299
1300 switch (type) {
1301 case IB_QPT_RC: qp->transport = RC; break;
1302 case IB_QPT_UC: qp->transport = UC; break;
1303 case IB_QPT_UD: qp->transport = UD; break;
1304 default: return -EINVAL;
1305 }
1306
1307 err = mthca_set_qp_size(dev, cap, pd, qp);
1308 if (err)
1309 return err;
1310
1311 qp->qpn = mthca_alloc(&dev->qp_table.alloc);
1312 if (qp->qpn == -1)
1313 return -ENOMEM;
1314
1315 /* initialize port to zero for error-catching. */
1316 qp->port = 0;
1317
1318 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1319 send_policy, qp, udata);
1320 if (err) {
1321 mthca_free(&dev->qp_table.alloc, qp->qpn);
1322 return err;
1323 }
1324
1325 spin_lock_irq(&dev->qp_table.lock);
1326 mthca_array_set(&dev->qp_table.qp,
1327 qp->qpn & (dev->limits.num_qps - 1), qp);
1328 spin_unlock_irq(&dev->qp_table.lock);
1329
1330 return 0;
1331 }
1332
1333 static void mthca_lock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1334 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1335 {
1336 if (send_cq == recv_cq) {
1337 spin_lock_irq(&send_cq->lock);
1338 __acquire(&recv_cq->lock);
1339 } else if (send_cq->cqn < recv_cq->cqn) {
1340 spin_lock_irq(&send_cq->lock);
1341 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1342 } else {
1343 spin_lock_irq(&recv_cq->lock);
1344 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1345 }
1346 }
1347
1348 static void mthca_unlock_cqs(struct mthca_cq *send_cq, struct mthca_cq *recv_cq)
1349 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1350 {
1351 if (send_cq == recv_cq) {
1352 __release(&recv_cq->lock);
1353 spin_unlock_irq(&send_cq->lock);
1354 } else if (send_cq->cqn < recv_cq->cqn) {
1355 spin_unlock(&recv_cq->lock);
1356 spin_unlock_irq(&send_cq->lock);
1357 } else {
1358 spin_unlock(&send_cq->lock);
1359 spin_unlock_irq(&recv_cq->lock);
1360 }
1361 }
1362
1363 int mthca_alloc_sqp(struct mthca_dev *dev,
1364 struct mthca_pd *pd,
1365 struct mthca_cq *send_cq,
1366 struct mthca_cq *recv_cq,
1367 enum ib_sig_type send_policy,
1368 struct ib_qp_cap *cap,
1369 int qpn,
1370 int port,
1371 struct mthca_sqp *sqp,
1372 struct ib_udata *udata)
1373 {
1374 u32 mqpn = qpn * 2 + dev->qp_table.sqp_start + port - 1;
1375 int err;
1376
1377 sqp->qp.transport = MLX;
1378 err = mthca_set_qp_size(dev, cap, pd, &sqp->qp);
1379 if (err)
1380 return err;
1381
1382 sqp->header_buf_size = sqp->qp.sq.max * MTHCA_UD_HEADER_SIZE;
1383 sqp->header_buf = dma_alloc_coherent(&dev->pdev->dev, sqp->header_buf_size,
1384 &sqp->header_dma, GFP_KERNEL);
1385 if (!sqp->header_buf)
1386 return -ENOMEM;
1387
1388 spin_lock_irq(&dev->qp_table.lock);
1389 if (mthca_array_get(&dev->qp_table.qp, mqpn))
1390 err = -EBUSY;
1391 else
1392 mthca_array_set(&dev->qp_table.qp, mqpn, sqp);
1393 spin_unlock_irq(&dev->qp_table.lock);
1394
1395 if (err)
1396 goto err_out;
1397
1398 sqp->qp.port = port;
1399 sqp->qp.qpn = mqpn;
1400 sqp->qp.transport = MLX;
1401
1402 err = mthca_alloc_qp_common(dev, pd, send_cq, recv_cq,
1403 send_policy, &sqp->qp, udata);
1404 if (err)
1405 goto err_out_free;
1406
1407 atomic_inc(&pd->sqp_count);
1408
1409 return 0;
1410
1411 err_out_free:
1412 /*
1413 * Lock CQs here, so that CQ polling code can do QP lookup
1414 * without taking a lock.
1415 */
1416 mthca_lock_cqs(send_cq, recv_cq);
1417
1418 spin_lock(&dev->qp_table.lock);
1419 mthca_array_clear(&dev->qp_table.qp, mqpn);
1420 spin_unlock(&dev->qp_table.lock);
1421
1422 mthca_unlock_cqs(send_cq, recv_cq);
1423
1424 err_out:
1425 dma_free_coherent(&dev->pdev->dev, sqp->header_buf_size,
1426 sqp->header_buf, sqp->header_dma);
1427
1428 return err;
1429 }
1430
1431 static inline int get_qp_refcount(struct mthca_dev *dev, struct mthca_qp *qp)
1432 {
1433 int c;
1434
1435 spin_lock_irq(&dev->qp_table.lock);
1436 c = qp->refcount;
1437 spin_unlock_irq(&dev->qp_table.lock);
1438
1439 return c;
1440 }
1441
1442 void mthca_free_qp(struct mthca_dev *dev,
1443 struct mthca_qp *qp)
1444 {
1445 struct mthca_cq *send_cq;
1446 struct mthca_cq *recv_cq;
1447
1448 send_cq = to_mcq(qp->ibqp.send_cq);
1449 recv_cq = to_mcq(qp->ibqp.recv_cq);
1450
1451 /*
1452 * Lock CQs here, so that CQ polling code can do QP lookup
1453 * without taking a lock.
1454 */
1455 mthca_lock_cqs(send_cq, recv_cq);
1456
1457 spin_lock(&dev->qp_table.lock);
1458 mthca_array_clear(&dev->qp_table.qp,
1459 qp->qpn & (dev->limits.num_qps - 1));
1460 --qp->refcount;
1461 spin_unlock(&dev->qp_table.lock);
1462
1463 mthca_unlock_cqs(send_cq, recv_cq);
1464
1465 wait_event(qp->wait, !get_qp_refcount(dev, qp));
1466
1467 if (qp->state != IB_QPS_RESET)
1468 mthca_MODIFY_QP(dev, qp->state, IB_QPS_RESET, qp->qpn, 0,
1469 NULL, 0);
1470
1471 /*
1472 * If this is a userspace QP, the buffers, MR, CQs and so on
1473 * will be cleaned up in userspace, so all we have to do is
1474 * unref the mem-free tables and free the QPN in our table.
1475 */
1476 if (!qp->ibqp.uobject) {
1477 mthca_cq_clean(dev, recv_cq, qp->qpn,
1478 qp->ibqp.srq ? to_msrq(qp->ibqp.srq) : NULL);
1479 if (send_cq != recv_cq)
1480 mthca_cq_clean(dev, send_cq, qp->qpn, NULL);
1481
1482 mthca_free_memfree(dev, qp);
1483 mthca_free_wqe_buf(dev, qp);
1484 }
1485
1486 mthca_unmap_memfree(dev, qp);
1487
1488 if (is_sqp(dev, qp)) {
1489 atomic_dec(&(to_mpd(qp->ibqp.pd)->sqp_count));
1490 dma_free_coherent(&dev->pdev->dev,
1491 to_msqp(qp)->header_buf_size,
1492 to_msqp(qp)->header_buf,
1493 to_msqp(qp)->header_dma);
1494 } else
1495 mthca_free(&dev->qp_table.alloc, qp->qpn);
1496 }
1497
1498 /* Create UD header for an MLX send and build a data segment for it */
1499 static int build_mlx_header(struct mthca_dev *dev, struct mthca_sqp *sqp,
1500 int ind, const struct ib_ud_wr *wr,
1501 struct mthca_mlx_seg *mlx,
1502 struct mthca_data_seg *data)
1503 {
1504 int header_size;
1505 int err;
1506 u16 pkey;
1507
1508 ib_ud_header_init(256, /* assume a MAD */ 1, 0, 0,
1509 mthca_ah_grh_present(to_mah(wr->ah)), 0, 0, 0,
1510 &sqp->ud_header);
1511
1512 err = mthca_read_ah(dev, to_mah(wr->ah), &sqp->ud_header);
1513 if (err)
1514 return err;
1515 mlx->flags &= ~cpu_to_be32(MTHCA_NEXT_SOLICIT | 1);
1516 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MTHCA_MLX_VL15 : 0) |
1517 (sqp->ud_header.lrh.destination_lid ==
1518 IB_LID_PERMISSIVE ? MTHCA_MLX_SLR : 0) |
1519 (sqp->ud_header.lrh.service_level << 8));
1520 mlx->rlid = sqp->ud_header.lrh.destination_lid;
1521 mlx->vcrc = 0;
1522
1523 switch (wr->wr.opcode) {
1524 case IB_WR_SEND:
1525 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
1526 sqp->ud_header.immediate_present = 0;
1527 break;
1528 case IB_WR_SEND_WITH_IMM:
1529 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
1530 sqp->ud_header.immediate_present = 1;
1531 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
1532 break;
1533 default:
1534 return -EINVAL;
1535 }
1536
1537 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 : 0;
1538 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
1539 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
1540 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
1541 if (!sqp->qp.ibqp.qp_num)
1542 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1543 sqp->pkey_index, &pkey);
1544 else
1545 ib_get_cached_pkey(&dev->ib_dev, sqp->qp.port,
1546 wr->pkey_index, &pkey);
1547 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
1548 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
1549 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
1550 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
1551 sqp->qkey : wr->remote_qkey);
1552 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
1553
1554 header_size = ib_ud_header_pack(&sqp->ud_header,
1555 sqp->header_buf +
1556 ind * MTHCA_UD_HEADER_SIZE);
1557
1558 data->byte_count = cpu_to_be32(header_size);
1559 data->lkey = cpu_to_be32(to_mpd(sqp->qp.ibqp.pd)->ntmr.ibmr.lkey);
1560 data->addr = cpu_to_be64(sqp->header_dma +
1561 ind * MTHCA_UD_HEADER_SIZE);
1562
1563 return 0;
1564 }
1565
1566 static inline int mthca_wq_overflow(struct mthca_wq *wq, int nreq,
1567 struct ib_cq *ib_cq)
1568 {
1569 unsigned cur;
1570 struct mthca_cq *cq;
1571
1572 cur = wq->head - wq->tail;
1573 if (likely(cur + nreq < wq->max))
1574 return 0;
1575
1576 cq = to_mcq(ib_cq);
1577 spin_lock(&cq->lock);
1578 cur = wq->head - wq->tail;
1579 spin_unlock(&cq->lock);
1580
1581 return cur + nreq >= wq->max;
1582 }
1583
1584 static __always_inline void set_raddr_seg(struct mthca_raddr_seg *rseg,
1585 u64 remote_addr, u32 rkey)
1586 {
1587 rseg->raddr = cpu_to_be64(remote_addr);
1588 rseg->rkey = cpu_to_be32(rkey);
1589 rseg->reserved = 0;
1590 }
1591
1592 static __always_inline void set_atomic_seg(struct mthca_atomic_seg *aseg,
1593 const struct ib_atomic_wr *wr)
1594 {
1595 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
1596 aseg->swap_add = cpu_to_be64(wr->swap);
1597 aseg->compare = cpu_to_be64(wr->compare_add);
1598 } else {
1599 aseg->swap_add = cpu_to_be64(wr->compare_add);
1600 aseg->compare = 0;
1601 }
1602
1603 }
1604
1605 static void set_tavor_ud_seg(struct mthca_tavor_ud_seg *useg,
1606 const struct ib_ud_wr *wr)
1607 {
1608 useg->lkey = cpu_to_be32(to_mah(wr->ah)->key);
1609 useg->av_addr = cpu_to_be64(to_mah(wr->ah)->avdma);
1610 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1611 useg->qkey = cpu_to_be32(wr->remote_qkey);
1612
1613 }
1614
1615 static void set_arbel_ud_seg(struct mthca_arbel_ud_seg *useg,
1616 const struct ib_ud_wr *wr)
1617 {
1618 memcpy(useg->av, to_mah(wr->ah)->av, MTHCA_AV_SIZE);
1619 useg->dqpn = cpu_to_be32(wr->remote_qpn);
1620 useg->qkey = cpu_to_be32(wr->remote_qkey);
1621 }
1622
1623 int mthca_tavor_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1624 const struct ib_send_wr **bad_wr)
1625 {
1626 struct mthca_dev *dev = to_mdev(ibqp->device);
1627 struct mthca_qp *qp = to_mqp(ibqp);
1628 void *wqe;
1629 void *prev_wqe;
1630 unsigned long flags;
1631 int err = 0;
1632 int nreq;
1633 int i;
1634 int size;
1635 /*
1636 * f0 and size0 are only used if nreq != 0, and they will
1637 * always be initialized the first time through the main loop
1638 * before nreq is incremented. So nreq cannot become non-zero
1639 * without initializing f0 and size0, and they are in fact
1640 * never used uninitialized.
1641 */
1642 int uninitialized_var(size0);
1643 u32 uninitialized_var(f0);
1644 int ind;
1645 u8 op0 = 0;
1646
1647 spin_lock_irqsave(&qp->sq.lock, flags);
1648
1649 /* XXX check that state is OK to post send */
1650
1651 ind = qp->sq.next_ind;
1652
1653 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1654 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1655 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1656 " %d max, %d nreq)\n", qp->qpn,
1657 qp->sq.head, qp->sq.tail,
1658 qp->sq.max, nreq);
1659 err = -ENOMEM;
1660 *bad_wr = wr;
1661 goto out;
1662 }
1663
1664 wqe = get_send_wqe(qp, ind);
1665 prev_wqe = qp->sq.last;
1666 qp->sq.last = wqe;
1667
1668 ((struct mthca_next_seg *) wqe)->nda_op = 0;
1669 ((struct mthca_next_seg *) wqe)->ee_nds = 0;
1670 ((struct mthca_next_seg *) wqe)->flags =
1671 ((wr->send_flags & IB_SEND_SIGNALED) ?
1672 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
1673 ((wr->send_flags & IB_SEND_SOLICITED) ?
1674 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
1675 cpu_to_be32(1);
1676 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
1677 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
1678 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
1679
1680 wqe += sizeof (struct mthca_next_seg);
1681 size = sizeof (struct mthca_next_seg) / 16;
1682
1683 switch (qp->transport) {
1684 case RC:
1685 switch (wr->opcode) {
1686 case IB_WR_ATOMIC_CMP_AND_SWP:
1687 case IB_WR_ATOMIC_FETCH_AND_ADD:
1688 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
1689 atomic_wr(wr)->rkey);
1690 wqe += sizeof (struct mthca_raddr_seg);
1691
1692 set_atomic_seg(wqe, atomic_wr(wr));
1693 wqe += sizeof (struct mthca_atomic_seg);
1694 size += (sizeof (struct mthca_raddr_seg) +
1695 sizeof (struct mthca_atomic_seg)) / 16;
1696 break;
1697
1698 case IB_WR_RDMA_WRITE:
1699 case IB_WR_RDMA_WRITE_WITH_IMM:
1700 case IB_WR_RDMA_READ:
1701 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1702 rdma_wr(wr)->rkey);
1703 wqe += sizeof (struct mthca_raddr_seg);
1704 size += sizeof (struct mthca_raddr_seg) / 16;
1705 break;
1706
1707 default:
1708 /* No extra segments required for sends */
1709 break;
1710 }
1711
1712 break;
1713
1714 case UC:
1715 switch (wr->opcode) {
1716 case IB_WR_RDMA_WRITE:
1717 case IB_WR_RDMA_WRITE_WITH_IMM:
1718 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
1719 rdma_wr(wr)->rkey);
1720 wqe += sizeof (struct mthca_raddr_seg);
1721 size += sizeof (struct mthca_raddr_seg) / 16;
1722 break;
1723
1724 default:
1725 /* No extra segments required for sends */
1726 break;
1727 }
1728
1729 break;
1730
1731 case UD:
1732 set_tavor_ud_seg(wqe, ud_wr(wr));
1733 wqe += sizeof (struct mthca_tavor_ud_seg);
1734 size += sizeof (struct mthca_tavor_ud_seg) / 16;
1735 break;
1736
1737 case MLX:
1738 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
1739 wqe - sizeof (struct mthca_next_seg),
1740 wqe);
1741 if (err) {
1742 *bad_wr = wr;
1743 goto out;
1744 }
1745 wqe += sizeof (struct mthca_data_seg);
1746 size += sizeof (struct mthca_data_seg) / 16;
1747 break;
1748 }
1749
1750 if (wr->num_sge > qp->sq.max_gs) {
1751 mthca_err(dev, "too many gathers\n");
1752 err = -EINVAL;
1753 *bad_wr = wr;
1754 goto out;
1755 }
1756
1757 for (i = 0; i < wr->num_sge; ++i) {
1758 mthca_set_data_seg(wqe, wr->sg_list + i);
1759 wqe += sizeof (struct mthca_data_seg);
1760 size += sizeof (struct mthca_data_seg) / 16;
1761 }
1762
1763 /* Add one more inline data segment for ICRC */
1764 if (qp->transport == MLX) {
1765 ((struct mthca_data_seg *) wqe)->byte_count =
1766 cpu_to_be32((1 << 31) | 4);
1767 ((u32 *) wqe)[1] = 0;
1768 wqe += sizeof (struct mthca_data_seg);
1769 size += sizeof (struct mthca_data_seg) / 16;
1770 }
1771
1772 qp->wrid[ind + qp->rq.max] = wr->wr_id;
1773
1774 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
1775 mthca_err(dev, "opcode invalid\n");
1776 err = -EINVAL;
1777 *bad_wr = wr;
1778 goto out;
1779 }
1780
1781 ((struct mthca_next_seg *) prev_wqe)->nda_op =
1782 cpu_to_be32(((ind << qp->sq.wqe_shift) +
1783 qp->send_wqe_offset) |
1784 mthca_opcode[wr->opcode]);
1785 wmb();
1786 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1787 cpu_to_be32((nreq ? 0 : MTHCA_NEXT_DBD) | size |
1788 ((wr->send_flags & IB_SEND_FENCE) ?
1789 MTHCA_NEXT_FENCE : 0));
1790
1791 if (!nreq) {
1792 size0 = size;
1793 op0 = mthca_opcode[wr->opcode];
1794 f0 = wr->send_flags & IB_SEND_FENCE ?
1795 MTHCA_SEND_DOORBELL_FENCE : 0;
1796 }
1797
1798 ++ind;
1799 if (unlikely(ind >= qp->sq.max))
1800 ind -= qp->sq.max;
1801 }
1802
1803 out:
1804 if (likely(nreq)) {
1805 wmb();
1806
1807 mthca_write64(((qp->sq.next_ind << qp->sq.wqe_shift) +
1808 qp->send_wqe_offset) | f0 | op0,
1809 (qp->qpn << 8) | size0,
1810 dev->kar + MTHCA_SEND_DOORBELL,
1811 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1812 }
1813
1814 qp->sq.next_ind = ind;
1815 qp->sq.head += nreq;
1816
1817 spin_unlock_irqrestore(&qp->sq.lock, flags);
1818 return err;
1819 }
1820
1821 int mthca_tavor_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
1822 const struct ib_recv_wr **bad_wr)
1823 {
1824 struct mthca_dev *dev = to_mdev(ibqp->device);
1825 struct mthca_qp *qp = to_mqp(ibqp);
1826 unsigned long flags;
1827 int err = 0;
1828 int nreq;
1829 int i;
1830 int size;
1831 /*
1832 * size0 is only used if nreq != 0, and it will always be
1833 * initialized the first time through the main loop before
1834 * nreq is incremented. So nreq cannot become non-zero
1835 * without initializing size0, and it is in fact never used
1836 * uninitialized.
1837 */
1838 int uninitialized_var(size0);
1839 int ind;
1840 void *wqe;
1841 void *prev_wqe;
1842
1843 spin_lock_irqsave(&qp->rq.lock, flags);
1844
1845 /* XXX check that state is OK to post receive */
1846
1847 ind = qp->rq.next_ind;
1848
1849 for (nreq = 0; wr; wr = wr->next) {
1850 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
1851 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
1852 " %d max, %d nreq)\n", qp->qpn,
1853 qp->rq.head, qp->rq.tail,
1854 qp->rq.max, nreq);
1855 err = -ENOMEM;
1856 *bad_wr = wr;
1857 goto out;
1858 }
1859
1860 wqe = get_recv_wqe(qp, ind);
1861 prev_wqe = qp->rq.last;
1862 qp->rq.last = wqe;
1863
1864 ((struct mthca_next_seg *) wqe)->ee_nds =
1865 cpu_to_be32(MTHCA_NEXT_DBD);
1866 ((struct mthca_next_seg *) wqe)->flags = 0;
1867
1868 wqe += sizeof (struct mthca_next_seg);
1869 size = sizeof (struct mthca_next_seg) / 16;
1870
1871 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
1872 err = -EINVAL;
1873 *bad_wr = wr;
1874 goto out;
1875 }
1876
1877 for (i = 0; i < wr->num_sge; ++i) {
1878 mthca_set_data_seg(wqe, wr->sg_list + i);
1879 wqe += sizeof (struct mthca_data_seg);
1880 size += sizeof (struct mthca_data_seg) / 16;
1881 }
1882
1883 qp->wrid[ind] = wr->wr_id;
1884
1885 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
1886 cpu_to_be32(MTHCA_NEXT_DBD | size);
1887
1888 if (!nreq)
1889 size0 = size;
1890
1891 ++ind;
1892 if (unlikely(ind >= qp->rq.max))
1893 ind -= qp->rq.max;
1894
1895 ++nreq;
1896 if (unlikely(nreq == MTHCA_TAVOR_MAX_WQES_PER_RECV_DB)) {
1897 nreq = 0;
1898
1899 wmb();
1900
1901 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1902 qp->qpn << 8, dev->kar + MTHCA_RECEIVE_DOORBELL,
1903 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1904
1905 qp->rq.next_ind = ind;
1906 qp->rq.head += MTHCA_TAVOR_MAX_WQES_PER_RECV_DB;
1907 }
1908 }
1909
1910 out:
1911 if (likely(nreq)) {
1912 wmb();
1913
1914 mthca_write64((qp->rq.next_ind << qp->rq.wqe_shift) | size0,
1915 qp->qpn << 8 | nreq, dev->kar + MTHCA_RECEIVE_DOORBELL,
1916 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1917 }
1918
1919 qp->rq.next_ind = ind;
1920 qp->rq.head += nreq;
1921
1922 spin_unlock_irqrestore(&qp->rq.lock, flags);
1923 return err;
1924 }
1925
1926 int mthca_arbel_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
1927 const struct ib_send_wr **bad_wr)
1928 {
1929 struct mthca_dev *dev = to_mdev(ibqp->device);
1930 struct mthca_qp *qp = to_mqp(ibqp);
1931 u32 dbhi;
1932 void *wqe;
1933 void *prev_wqe;
1934 unsigned long flags;
1935 int err = 0;
1936 int nreq;
1937 int i;
1938 int size;
1939 /*
1940 * f0 and size0 are only used if nreq != 0, and they will
1941 * always be initialized the first time through the main loop
1942 * before nreq is incremented. So nreq cannot become non-zero
1943 * without initializing f0 and size0, and they are in fact
1944 * never used uninitialized.
1945 */
1946 int uninitialized_var(size0);
1947 u32 uninitialized_var(f0);
1948 int ind;
1949 u8 op0 = 0;
1950
1951 spin_lock_irqsave(&qp->sq.lock, flags);
1952
1953 /* XXX check that state is OK to post send */
1954
1955 ind = qp->sq.head & (qp->sq.max - 1);
1956
1957 for (nreq = 0; wr; ++nreq, wr = wr->next) {
1958 if (unlikely(nreq == MTHCA_ARBEL_MAX_WQES_PER_SEND_DB)) {
1959 nreq = 0;
1960
1961 dbhi = (MTHCA_ARBEL_MAX_WQES_PER_SEND_DB << 24) |
1962 ((qp->sq.head & 0xffff) << 8) | f0 | op0;
1963
1964 qp->sq.head += MTHCA_ARBEL_MAX_WQES_PER_SEND_DB;
1965
1966 /*
1967 * Make sure that descriptors are written before
1968 * doorbell record.
1969 */
1970 wmb();
1971 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
1972
1973 /*
1974 * Make sure doorbell record is written before we
1975 * write MMIO send doorbell.
1976 */
1977 wmb();
1978
1979 mthca_write64(dbhi, (qp->qpn << 8) | size0,
1980 dev->kar + MTHCA_SEND_DOORBELL,
1981 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
1982 }
1983
1984 if (mthca_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
1985 mthca_err(dev, "SQ %06x full (%u head, %u tail,"
1986 " %d max, %d nreq)\n", qp->qpn,
1987 qp->sq.head, qp->sq.tail,
1988 qp->sq.max, nreq);
1989 err = -ENOMEM;
1990 *bad_wr = wr;
1991 goto out;
1992 }
1993
1994 wqe = get_send_wqe(qp, ind);
1995 prev_wqe = qp->sq.last;
1996 qp->sq.last = wqe;
1997
1998 ((struct mthca_next_seg *) wqe)->flags =
1999 ((wr->send_flags & IB_SEND_SIGNALED) ?
2000 cpu_to_be32(MTHCA_NEXT_CQ_UPDATE) : 0) |
2001 ((wr->send_flags & IB_SEND_SOLICITED) ?
2002 cpu_to_be32(MTHCA_NEXT_SOLICIT) : 0) |
2003 ((wr->send_flags & IB_SEND_IP_CSUM) ?
2004 cpu_to_be32(MTHCA_NEXT_IP_CSUM | MTHCA_NEXT_TCP_UDP_CSUM) : 0) |
2005 cpu_to_be32(1);
2006 if (wr->opcode == IB_WR_SEND_WITH_IMM ||
2007 wr->opcode == IB_WR_RDMA_WRITE_WITH_IMM)
2008 ((struct mthca_next_seg *) wqe)->imm = wr->ex.imm_data;
2009
2010 wqe += sizeof (struct mthca_next_seg);
2011 size = sizeof (struct mthca_next_seg) / 16;
2012
2013 switch (qp->transport) {
2014 case RC:
2015 switch (wr->opcode) {
2016 case IB_WR_ATOMIC_CMP_AND_SWP:
2017 case IB_WR_ATOMIC_FETCH_AND_ADD:
2018 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
2019 atomic_wr(wr)->rkey);
2020 wqe += sizeof (struct mthca_raddr_seg);
2021
2022 set_atomic_seg(wqe, atomic_wr(wr));
2023 wqe += sizeof (struct mthca_atomic_seg);
2024 size += (sizeof (struct mthca_raddr_seg) +
2025 sizeof (struct mthca_atomic_seg)) / 16;
2026 break;
2027
2028 case IB_WR_RDMA_READ:
2029 case IB_WR_RDMA_WRITE:
2030 case IB_WR_RDMA_WRITE_WITH_IMM:
2031 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2032 rdma_wr(wr)->rkey);
2033 wqe += sizeof (struct mthca_raddr_seg);
2034 size += sizeof (struct mthca_raddr_seg) / 16;
2035 break;
2036
2037 default:
2038 /* No extra segments required for sends */
2039 break;
2040 }
2041
2042 break;
2043
2044 case UC:
2045 switch (wr->opcode) {
2046 case IB_WR_RDMA_WRITE:
2047 case IB_WR_RDMA_WRITE_WITH_IMM:
2048 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
2049 rdma_wr(wr)->rkey);
2050 wqe += sizeof (struct mthca_raddr_seg);
2051 size += sizeof (struct mthca_raddr_seg) / 16;
2052 break;
2053
2054 default:
2055 /* No extra segments required for sends */
2056 break;
2057 }
2058
2059 break;
2060
2061 case UD:
2062 set_arbel_ud_seg(wqe, ud_wr(wr));
2063 wqe += sizeof (struct mthca_arbel_ud_seg);
2064 size += sizeof (struct mthca_arbel_ud_seg) / 16;
2065 break;
2066
2067 case MLX:
2068 err = build_mlx_header(dev, to_msqp(qp), ind, ud_wr(wr),
2069 wqe - sizeof (struct mthca_next_seg),
2070 wqe);
2071 if (err) {
2072 *bad_wr = wr;
2073 goto out;
2074 }
2075 wqe += sizeof (struct mthca_data_seg);
2076 size += sizeof (struct mthca_data_seg) / 16;
2077 break;
2078 }
2079
2080 if (wr->num_sge > qp->sq.max_gs) {
2081 mthca_err(dev, "too many gathers\n");
2082 err = -EINVAL;
2083 *bad_wr = wr;
2084 goto out;
2085 }
2086
2087 for (i = 0; i < wr->num_sge; ++i) {
2088 mthca_set_data_seg(wqe, wr->sg_list + i);
2089 wqe += sizeof (struct mthca_data_seg);
2090 size += sizeof (struct mthca_data_seg) / 16;
2091 }
2092
2093 /* Add one more inline data segment for ICRC */
2094 if (qp->transport == MLX) {
2095 ((struct mthca_data_seg *) wqe)->byte_count =
2096 cpu_to_be32((1 << 31) | 4);
2097 ((u32 *) wqe)[1] = 0;
2098 wqe += sizeof (struct mthca_data_seg);
2099 size += sizeof (struct mthca_data_seg) / 16;
2100 }
2101
2102 qp->wrid[ind + qp->rq.max] = wr->wr_id;
2103
2104 if (wr->opcode >= ARRAY_SIZE(mthca_opcode)) {
2105 mthca_err(dev, "opcode invalid\n");
2106 err = -EINVAL;
2107 *bad_wr = wr;
2108 goto out;
2109 }
2110
2111 ((struct mthca_next_seg *) prev_wqe)->nda_op =
2112 cpu_to_be32(((ind << qp->sq.wqe_shift) +
2113 qp->send_wqe_offset) |
2114 mthca_opcode[wr->opcode]);
2115 wmb();
2116 ((struct mthca_next_seg *) prev_wqe)->ee_nds =
2117 cpu_to_be32(MTHCA_NEXT_DBD | size |
2118 ((wr->send_flags & IB_SEND_FENCE) ?
2119 MTHCA_NEXT_FENCE : 0));
2120
2121 if (!nreq) {
2122 size0 = size;
2123 op0 = mthca_opcode[wr->opcode];
2124 f0 = wr->send_flags & IB_SEND_FENCE ?
2125 MTHCA_SEND_DOORBELL_FENCE : 0;
2126 }
2127
2128 ++ind;
2129 if (unlikely(ind >= qp->sq.max))
2130 ind -= qp->sq.max;
2131 }
2132
2133 out:
2134 if (likely(nreq)) {
2135 dbhi = (nreq << 24) | ((qp->sq.head & 0xffff) << 8) | f0 | op0;
2136
2137 qp->sq.head += nreq;
2138
2139 /*
2140 * Make sure that descriptors are written before
2141 * doorbell record.
2142 */
2143 wmb();
2144 *qp->sq.db = cpu_to_be32(qp->sq.head & 0xffff);
2145
2146 /*
2147 * Make sure doorbell record is written before we
2148 * write MMIO send doorbell.
2149 */
2150 wmb();
2151
2152 mthca_write64(dbhi, (qp->qpn << 8) | size0, dev->kar + MTHCA_SEND_DOORBELL,
2153 MTHCA_GET_DOORBELL_LOCK(&dev->doorbell_lock));
2154 }
2155
2156 spin_unlock_irqrestore(&qp->sq.lock, flags);
2157 return err;
2158 }
2159
2160 int mthca_arbel_post_receive(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
2161 const struct ib_recv_wr **bad_wr)
2162 {
2163 struct mthca_dev *dev = to_mdev(ibqp->device);
2164 struct mthca_qp *qp = to_mqp(ibqp);
2165 unsigned long flags;
2166 int err = 0;
2167 int nreq;
2168 int ind;
2169 int i;
2170 void *wqe;
2171
2172 spin_lock_irqsave(&qp->rq.lock, flags);
2173
2174 /* XXX check that state is OK to post receive */
2175
2176 ind = qp->rq.head & (qp->rq.max - 1);
2177
2178 for (nreq = 0; wr; ++nreq, wr = wr->next) {
2179 if (mthca_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
2180 mthca_err(dev, "RQ %06x full (%u head, %u tail,"
2181 " %d max, %d nreq)\n", qp->qpn,
2182 qp->rq.head, qp->rq.tail,
2183 qp->rq.max, nreq);
2184 err = -ENOMEM;
2185 *bad_wr = wr;
2186 goto out;
2187 }
2188
2189 wqe = get_recv_wqe(qp, ind);
2190
2191 ((struct mthca_next_seg *) wqe)->flags = 0;
2192
2193 wqe += sizeof (struct mthca_next_seg);
2194
2195 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
2196 err = -EINVAL;
2197 *bad_wr = wr;
2198 goto out;
2199 }
2200
2201 for (i = 0; i < wr->num_sge; ++i) {
2202 mthca_set_data_seg(wqe, wr->sg_list + i);
2203 wqe += sizeof (struct mthca_data_seg);
2204 }
2205
2206 if (i < qp->rq.max_gs)
2207 mthca_set_data_seg_inval(wqe);
2208
2209 qp->wrid[ind] = wr->wr_id;
2210
2211 ++ind;
2212 if (unlikely(ind >= qp->rq.max))
2213 ind -= qp->rq.max;
2214 }
2215 out:
2216 if (likely(nreq)) {
2217 qp->rq.head += nreq;
2218
2219 /*
2220 * Make sure that descriptors are written before
2221 * doorbell record.
2222 */
2223 wmb();
2224 *qp->rq.db = cpu_to_be32(qp->rq.head & 0xffff);
2225 }
2226
2227 spin_unlock_irqrestore(&qp->rq.lock, flags);
2228 return err;
2229 }
2230
2231 void mthca_free_err_wqe(struct mthca_dev *dev, struct mthca_qp *qp, int is_send,
2232 int index, int *dbd, __be32 *new_wqe)
2233 {
2234 struct mthca_next_seg *next;
2235
2236 /*
2237 * For SRQs, all receive WQEs generate a CQE, so we're always
2238 * at the end of the doorbell chain.
2239 */
2240 if (qp->ibqp.srq && !is_send) {
2241 *new_wqe = 0;
2242 return;
2243 }
2244
2245 if (is_send)
2246 next = get_send_wqe(qp, index);
2247 else
2248 next = get_recv_wqe(qp, index);
2249
2250 *dbd = !!(next->ee_nds & cpu_to_be32(MTHCA_NEXT_DBD));
2251 if (next->ee_nds & cpu_to_be32(0x3f))
2252 *new_wqe = (next->nda_op & cpu_to_be32(~0x3f)) |
2253 (next->ee_nds & cpu_to_be32(0x3f));
2254 else
2255 *new_wqe = 0;
2256 }
2257
2258 int mthca_init_qp_table(struct mthca_dev *dev)
2259 {
2260 int err;
2261 int i;
2262
2263 spin_lock_init(&dev->qp_table.lock);
2264
2265 /*
2266 * We reserve 2 extra QPs per port for the special QPs. The
2267 * special QP for port 1 has to be even, so round up.
2268 */
2269 dev->qp_table.sqp_start = (dev->limits.reserved_qps + 1) & ~1UL;
2270 err = mthca_alloc_init(&dev->qp_table.alloc,
2271 dev->limits.num_qps,
2272 (1 << 24) - 1,
2273 dev->qp_table.sqp_start +
2274 MTHCA_MAX_PORTS * 2);
2275 if (err)
2276 return err;
2277
2278 err = mthca_array_init(&dev->qp_table.qp,
2279 dev->limits.num_qps);
2280 if (err) {
2281 mthca_alloc_cleanup(&dev->qp_table.alloc);
2282 return err;
2283 }
2284
2285 for (i = 0; i < 2; ++i) {
2286 err = mthca_CONF_SPECIAL_QP(dev, i ? IB_QPT_GSI : IB_QPT_SMI,
2287 dev->qp_table.sqp_start + i * 2);
2288 if (err) {
2289 mthca_warn(dev, "CONF_SPECIAL_QP returned "
2290 "%d, aborting.\n", err);
2291 goto err_out;
2292 }
2293 }
2294 return 0;
2295
2296 err_out:
2297 for (i = 0; i < 2; ++i)
2298 mthca_CONF_SPECIAL_QP(dev, i, 0);
2299
2300 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2301 mthca_alloc_cleanup(&dev->qp_table.alloc);
2302
2303 return err;
2304 }
2305
2306 void mthca_cleanup_qp_table(struct mthca_dev *dev)
2307 {
2308 int i;
2309
2310 for (i = 0; i < 2; ++i)
2311 mthca_CONF_SPECIAL_QP(dev, i, 0);
2312
2313 mthca_array_cleanup(&dev->qp_table.qp, dev->limits.num_qps);
2314 mthca_alloc_cleanup(&dev->qp_table.alloc);
2315 }
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