2 * Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
34 #include <linux/module.h>
35 #include <linux/moduleparam.h>
36 #include <linux/netdevice.h>
37 #include <linux/etherdevice.h>
38 #include <linux/if_vlan.h>
39 #include <linux/slab.h>
43 static int wide_ppm_offset
;
44 module_param(wide_ppm_offset
, int, 0644);
45 MODULE_PARM_DESC(wide_ppm_offset
, "Increase CX4 interface clock ppm offset, 0=100ppm (default), 1=300ppm");
47 static u32 crit_err_count
;
48 u32 int_mod_timer_init
;
49 u32 int_mod_cq_depth_256
;
50 u32 int_mod_cq_depth_128
;
51 u32 int_mod_cq_depth_32
;
52 u32 int_mod_cq_depth_24
;
53 u32 int_mod_cq_depth_16
;
54 u32 int_mod_cq_depth_4
;
55 u32 int_mod_cq_depth_1
;
56 static const u8 nes_max_critical_error_count
= 100;
59 static void nes_cqp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*cq
);
60 static void nes_init_csr_ne020(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
);
61 static int nes_init_serdes(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
,
62 struct nes_adapter
*nesadapter
, u8 OneG_Mode
);
63 static void nes_nic_napi_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
);
64 static void nes_process_aeq(struct nes_device
*nesdev
, struct nes_hw_aeq
*aeq
);
65 static void nes_process_ceq(struct nes_device
*nesdev
, struct nes_hw_ceq
*ceq
);
66 static void nes_process_iwarp_aeqe(struct nes_device
*nesdev
,
67 struct nes_hw_aeqe
*aeqe
);
68 static void process_critical_error(struct nes_device
*nesdev
);
69 static void nes_process_mac_intr(struct nes_device
*nesdev
, u32 mac_number
);
70 static unsigned int nes_reset_adapter_ne020(struct nes_device
*nesdev
, u8
*OneG_Mode
);
71 static void nes_terminate_start_timer(struct nes_qp
*nesqp
);
73 #ifdef CONFIG_INFINIBAND_NES_DEBUG
74 static unsigned char *nes_iwarp_state_str
[] = {
85 static unsigned char *nes_tcp_state_str
[] = {
105 static inline void print_ip(struct nes_cm_node
*cm_node
)
107 unsigned char *rem_addr
;
109 rem_addr
= (unsigned char *)&cm_node
->rem_addr
;
110 printk(KERN_ERR PFX
"Remote IP addr: %pI4\n", rem_addr
);
115 * nes_nic_init_timer_defaults
117 void nes_nic_init_timer_defaults(struct nes_device
*nesdev
, u8 jumbomode
)
120 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
121 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
123 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
125 shared_timer
->timer_in_use_min
= NES_NIC_FAST_TIMER_LOW
;
126 shared_timer
->timer_in_use_max
= NES_NIC_FAST_TIMER_HIGH
;
128 shared_timer
->threshold_low
= DEFAULT_JUMBO_NES_QL_LOW
;
129 shared_timer
->threshold_target
= DEFAULT_JUMBO_NES_QL_TARGET
;
130 shared_timer
->threshold_high
= DEFAULT_JUMBO_NES_QL_HIGH
;
132 shared_timer
->threshold_low
= DEFAULT_NES_QL_LOW
;
133 shared_timer
->threshold_target
= DEFAULT_NES_QL_TARGET
;
134 shared_timer
->threshold_high
= DEFAULT_NES_QL_HIGH
;
137 /* todo use netdev->mtu to set thresholds */
138 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
145 static void nes_nic_init_timer(struct nes_device
*nesdev
)
148 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
149 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
151 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
153 if (shared_timer
->timer_in_use_old
== 0) {
154 nesdev
->deepcq_count
= 0;
155 shared_timer
->timer_direction_upward
= 0;
156 shared_timer
->timer_direction_downward
= 0;
157 shared_timer
->timer_in_use
= NES_NIC_FAST_TIMER
;
158 shared_timer
->timer_in_use_old
= 0;
161 if (shared_timer
->timer_in_use
!= shared_timer
->timer_in_use_old
) {
162 shared_timer
->timer_in_use_old
= shared_timer
->timer_in_use
;
163 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
,
164 0x80000000 | ((u32
)(shared_timer
->timer_in_use
*8)));
166 /* todo use netdev->mtu to set thresholds */
167 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
174 static void nes_nic_tune_timer(struct nes_device
*nesdev
)
177 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
178 struct nes_hw_tune_timer
*shared_timer
= &nesadapter
->tune_timer
;
179 u16 cq_count
= nesdev
->currcq_count
;
181 spin_lock_irqsave(&nesadapter
->periodic_timer_lock
, flags
);
183 if (shared_timer
->cq_count_old
<= cq_count
)
184 shared_timer
->cq_direction_downward
= 0;
186 shared_timer
->cq_direction_downward
++;
187 shared_timer
->cq_count_old
= cq_count
;
188 if (shared_timer
->cq_direction_downward
> NES_NIC_CQ_DOWNWARD_TREND
) {
189 if (cq_count
<= shared_timer
->threshold_low
&&
190 shared_timer
->threshold_low
> 4) {
191 shared_timer
->threshold_low
= shared_timer
->threshold_low
/2;
192 shared_timer
->cq_direction_downward
=0;
193 nesdev
->currcq_count
= 0;
194 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
200 nesdev
->deepcq_count
+= cq_count
;
201 if (cq_count
<= shared_timer
->threshold_low
) { /* increase timer gently */
202 shared_timer
->timer_direction_upward
++;
203 shared_timer
->timer_direction_downward
= 0;
204 } else if (cq_count
<= shared_timer
->threshold_target
) { /* balanced */
205 shared_timer
->timer_direction_upward
= 0;
206 shared_timer
->timer_direction_downward
= 0;
207 } else if (cq_count
<= shared_timer
->threshold_high
) { /* decrease timer gently */
208 shared_timer
->timer_direction_downward
++;
209 shared_timer
->timer_direction_upward
= 0;
210 } else if (cq_count
<= (shared_timer
->threshold_high
) * 2) {
211 shared_timer
->timer_in_use
-= 2;
212 shared_timer
->timer_direction_upward
= 0;
213 shared_timer
->timer_direction_downward
++;
215 shared_timer
->timer_in_use
-= 4;
216 shared_timer
->timer_direction_upward
= 0;
217 shared_timer
->timer_direction_downward
++;
220 if (shared_timer
->timer_direction_upward
> 3 ) { /* using history */
221 shared_timer
->timer_in_use
+= 3;
222 shared_timer
->timer_direction_upward
= 0;
223 shared_timer
->timer_direction_downward
= 0;
225 if (shared_timer
->timer_direction_downward
> 5) { /* using history */
226 shared_timer
->timer_in_use
-= 4 ;
227 shared_timer
->timer_direction_downward
= 0;
228 shared_timer
->timer_direction_upward
= 0;
232 /* boundary checking */
233 if (shared_timer
->timer_in_use
> shared_timer
->threshold_high
)
234 shared_timer
->timer_in_use
= shared_timer
->threshold_high
;
235 else if (shared_timer
->timer_in_use
< shared_timer
->threshold_low
)
236 shared_timer
->timer_in_use
= shared_timer
->threshold_low
;
238 nesdev
->currcq_count
= 0;
240 spin_unlock_irqrestore(&nesadapter
->periodic_timer_lock
, flags
);
245 * nes_init_adapter - initialize adapter
247 struct nes_adapter
*nes_init_adapter(struct nes_device
*nesdev
, u8 hw_rev
) {
248 struct nes_adapter
*nesadapter
= NULL
;
249 unsigned long num_pds
;
268 /* search the list of existing adapters */
269 list_for_each_entry(nesadapter
, &nes_adapter_list
, list
) {
270 nes_debug(NES_DBG_INIT
, "Searching Adapter list for PCI devfn = 0x%X,"
271 " adapter PCI slot/bus = %u/%u, pci devices PCI slot/bus = %u/%u, .\n",
272 nesdev
->pcidev
->devfn
,
273 PCI_SLOT(nesadapter
->devfn
),
274 nesadapter
->bus_number
,
275 PCI_SLOT(nesdev
->pcidev
->devfn
),
276 nesdev
->pcidev
->bus
->number
);
277 if ((PCI_SLOT(nesadapter
->devfn
) == PCI_SLOT(nesdev
->pcidev
->devfn
)) &&
278 (nesadapter
->bus_number
== nesdev
->pcidev
->bus
->number
)) {
279 nesadapter
->ref_count
++;
284 /* no adapter found */
285 num_pds
= pci_resource_len(nesdev
->pcidev
, BAR_1
) >> PAGE_SHIFT
;
286 if ((hw_rev
!= NE020_REV
) && (hw_rev
!= NE020_REV1
)) {
287 nes_debug(NES_DBG_INIT
, "NE020 driver detected unknown hardware revision 0x%x\n",
292 nes_debug(NES_DBG_INIT
, "Determine Soft Reset, QP_control=0x%x, CPU0=0x%x, CPU1=0x%x, CPU2=0x%x\n",
293 nes_read_indexed(nesdev
, NES_IDX_QP_CONTROL
+ PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
294 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
),
295 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
+ 4),
296 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
+ 8));
298 nes_debug(NES_DBG_INIT
, "Reset and init NE020\n");
301 if ((port_count
= nes_reset_adapter_ne020(nesdev
, &OneG_Mode
)) == 0)
304 max_qp
= nes_read_indexed(nesdev
, NES_IDX_QP_CTX_SIZE
);
305 nes_debug(NES_DBG_INIT
, "QP_CTX_SIZE=%u\n", max_qp
);
307 u32temp
= nes_read_indexed(nesdev
, NES_IDX_QUAD_HASH_TABLE_SIZE
);
308 if (max_qp
> ((u32
)1 << (u32temp
& 0x001f))) {
309 nes_debug(NES_DBG_INIT
, "Reducing Max QPs to %u due to hash table size = 0x%08X\n",
311 max_qp
= (u32
)1 << (u32temp
& 0x001f);
314 hte_index_mask
= ((u32
)1 << ((u32temp
& 0x001f)+1))-1;
315 nes_debug(NES_DBG_INIT
, "Max QP = %u, hte_index_mask = 0x%08X.\n",
316 max_qp
, hte_index_mask
);
318 u32temp
= nes_read_indexed(nesdev
, NES_IDX_IRRQ_COUNT
);
320 max_irrq
= 1 << (u32temp
& 0x001f);
322 if (max_qp
> max_irrq
) {
324 nes_debug(NES_DBG_INIT
, "Reducing Max QPs to %u due to Available Q1s.\n",
328 /* there should be no reason to allocate more pds than qps */
329 if (num_pds
> max_qp
)
332 u32temp
= nes_read_indexed(nesdev
, NES_IDX_MRT_SIZE
);
333 max_mr
= (u32
)8192 << (u32temp
& 0x7);
335 u32temp
= nes_read_indexed(nesdev
, NES_IDX_PBL_REGION_SIZE
);
336 max_256pbl
= (u32
)1 << (u32temp
& 0x0000001f);
337 max_4kpbl
= (u32
)1 << ((u32temp
>> 16) & 0x0000001f);
338 max_cq
= nes_read_indexed(nesdev
, NES_IDX_CQ_CTX_SIZE
);
340 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ARP_CACHE_SIZE
);
341 arp_table_size
= 1 << u32temp
;
343 adapter_size
= (sizeof(struct nes_adapter
) +
344 (sizeof(unsigned long)-1)) & (~(sizeof(unsigned long)-1));
345 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_qp
);
346 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_mr
);
347 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(max_cq
);
348 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(num_pds
);
349 adapter_size
+= sizeof(unsigned long) * BITS_TO_LONGS(arp_table_size
);
350 adapter_size
+= sizeof(struct nes_qp
**) * max_qp
;
352 /* allocate a new adapter struct */
353 nesadapter
= kzalloc(adapter_size
, GFP_KERNEL
);
357 nes_debug(NES_DBG_INIT
, "Allocating new nesadapter @ %p, size = %u (actual size = %u).\n",
358 nesadapter
, (u32
)sizeof(struct nes_adapter
), adapter_size
);
360 if (nes_read_eeprom_values(nesdev
, nesadapter
)) {
361 printk(KERN_ERR PFX
"Unable to read EEPROM data.\n");
366 nesadapter
->vendor_id
= (((u32
) nesadapter
->mac_addr_high
) << 8) |
367 (nesadapter
->mac_addr_low
>> 24);
369 pci_bus_read_config_word(nesdev
->pcidev
->bus
, nesdev
->pcidev
->devfn
,
370 PCI_DEVICE_ID
, &device_id
);
371 nesadapter
->vendor_part_id
= device_id
;
373 if (nes_init_serdes(nesdev
, hw_rev
, port_count
, nesadapter
,
378 nes_init_csr_ne020(nesdev
, hw_rev
, port_count
);
380 memset(nesadapter
->pft_mcast_map
, 255,
381 sizeof nesadapter
->pft_mcast_map
);
383 /* populate the new nesadapter */
384 nesadapter
->devfn
= nesdev
->pcidev
->devfn
;
385 nesadapter
->bus_number
= nesdev
->pcidev
->bus
->number
;
386 nesadapter
->ref_count
= 1;
387 nesadapter
->timer_int_req
= 0xffff0000;
388 nesadapter
->OneG_Mode
= OneG_Mode
;
389 nesadapter
->doorbell_start
= nesdev
->doorbell_region
;
391 /* nesadapter->tick_delta = clk_divisor; */
392 nesadapter
->hw_rev
= hw_rev
;
393 nesadapter
->port_count
= port_count
;
395 nesadapter
->max_qp
= max_qp
;
396 nesadapter
->hte_index_mask
= hte_index_mask
;
397 nesadapter
->max_irrq
= max_irrq
;
398 nesadapter
->max_mr
= max_mr
;
399 nesadapter
->max_256pbl
= max_256pbl
- 1;
400 nesadapter
->max_4kpbl
= max_4kpbl
- 1;
401 nesadapter
->max_cq
= max_cq
;
402 nesadapter
->free_256pbl
= max_256pbl
- 1;
403 nesadapter
->free_4kpbl
= max_4kpbl
- 1;
404 nesadapter
->max_pd
= num_pds
;
405 nesadapter
->arp_table_size
= arp_table_size
;
407 nesadapter
->et_pkt_rate_low
= NES_TIMER_ENABLE_LIMIT
;
408 if (nes_drv_opt
& NES_DRV_OPT_DISABLE_INT_MOD
) {
409 nesadapter
->et_use_adaptive_rx_coalesce
= 0;
410 nesadapter
->timer_int_limit
= NES_TIMER_INT_LIMIT
;
411 nesadapter
->et_rx_coalesce_usecs_irq
= interrupt_mod_interval
;
413 nesadapter
->et_use_adaptive_rx_coalesce
= 1;
414 nesadapter
->timer_int_limit
= NES_TIMER_INT_LIMIT_DYNAMIC
;
415 nesadapter
->et_rx_coalesce_usecs_irq
= 0;
416 printk(PFX
"%s: Using Adaptive Interrupt Moderation\n", __func__
);
418 /* Setup and enable the periodic timer */
419 if (nesadapter
->et_rx_coalesce_usecs_irq
)
420 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
, 0x80000000 |
421 ((u32
)(nesadapter
->et_rx_coalesce_usecs_irq
* 8)));
423 nes_write32(nesdev
->regs
+NES_PERIODIC_CONTROL
, 0x00000000);
425 nesadapter
->base_pd
= 1;
427 nesadapter
->device_cap_flags
= IB_DEVICE_LOCAL_DMA_LKEY
|
428 IB_DEVICE_MEM_WINDOW
|
429 IB_DEVICE_MEM_MGT_EXTENSIONS
;
431 nesadapter
->allocated_qps
= (unsigned long *)&(((unsigned char *)nesadapter
)
432 [(sizeof(struct nes_adapter
)+(sizeof(unsigned long)-1))&(~(sizeof(unsigned long)-1))]);
433 nesadapter
->allocated_cqs
= &nesadapter
->allocated_qps
[BITS_TO_LONGS(max_qp
)];
434 nesadapter
->allocated_mrs
= &nesadapter
->allocated_cqs
[BITS_TO_LONGS(max_cq
)];
435 nesadapter
->allocated_pds
= &nesadapter
->allocated_mrs
[BITS_TO_LONGS(max_mr
)];
436 nesadapter
->allocated_arps
= &nesadapter
->allocated_pds
[BITS_TO_LONGS(num_pds
)];
437 nesadapter
->qp_table
= (struct nes_qp
**)(&nesadapter
->allocated_arps
[BITS_TO_LONGS(arp_table_size
)]);
440 /* mark the usual suspect QPs, MR and CQs as in use */
441 for (u32temp
= 0; u32temp
< NES_FIRST_QPN
; u32temp
++) {
442 set_bit(u32temp
, nesadapter
->allocated_qps
);
443 set_bit(u32temp
, nesadapter
->allocated_cqs
);
445 set_bit(0, nesadapter
->allocated_mrs
);
447 for (u32temp
= 0; u32temp
< 20; u32temp
++)
448 set_bit(u32temp
, nesadapter
->allocated_pds
);
449 u32temp
= nes_read_indexed(nesdev
, NES_IDX_QP_MAX_CFG_SIZES
);
451 max_rq_wrs
= ((u32temp
>> 8) & 3);
452 switch (max_rq_wrs
) {
467 max_sq_wrs
= (u32temp
& 3);
468 switch (max_sq_wrs
) {
482 nesadapter
->max_qp_wr
= min(max_rq_wrs
, max_sq_wrs
);
483 nesadapter
->max_irrq_wr
= (u32temp
>> 16) & 3;
485 nesadapter
->max_sge
= 4;
486 nesadapter
->max_cqe
= 32766;
488 if (nes_read_eeprom_values(nesdev
, nesadapter
)) {
489 printk(KERN_ERR PFX
"Unable to read EEPROM data.\n");
494 u32temp
= nes_read_indexed(nesdev
, NES_IDX_TCP_TIMER_CONFIG
);
495 nes_write_indexed(nesdev
, NES_IDX_TCP_TIMER_CONFIG
,
496 (u32temp
& 0xff000000) | (nesadapter
->tcp_timer_core_clk_divisor
& 0x00ffffff));
498 /* setup port configuration */
499 if (nesadapter
->port_count
== 1) {
500 nesadapter
->log_port
= 0x00000000;
501 if (nes_drv_opt
& NES_DRV_OPT_DUAL_LOGICAL_PORT
)
502 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000002);
504 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000003);
506 if (nesadapter
->phy_type
[0] == NES_PHY_TYPE_PUMA_1G
) {
507 nesadapter
->log_port
= 0x000000D8;
509 if (nesadapter
->port_count
== 2)
510 nesadapter
->log_port
= 0x00000044;
512 nesadapter
->log_port
= 0x000000e4;
514 nes_write_indexed(nesdev
, NES_IDX_TX_POOL_SIZE
, 0x00000003);
517 nes_write_indexed(nesdev
, NES_IDX_NIC_LOGPORT_TO_PHYPORT
,
518 nesadapter
->log_port
);
519 nes_debug(NES_DBG_INIT
, "Probe time, LOG2PHY=%u\n",
520 nes_read_indexed(nesdev
, NES_IDX_NIC_LOGPORT_TO_PHYPORT
));
522 spin_lock_init(&nesadapter
->resource_lock
);
523 spin_lock_init(&nesadapter
->phy_lock
);
524 spin_lock_init(&nesadapter
->pbl_lock
);
525 spin_lock_init(&nesadapter
->periodic_timer_lock
);
527 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[0]);
528 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[1]);
529 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[2]);
530 INIT_LIST_HEAD(&nesadapter
->nesvnic_list
[3]);
532 if ((!nesadapter
->OneG_Mode
) && (nesadapter
->port_count
== 2)) {
533 u32 pcs_control_status0
, pcs_control_status1
;
541 pcs_control_status0
= nes_read_indexed(nesdev
,
542 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
543 pcs_control_status1
= nes_read_indexed(nesdev
,
544 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
546 for (i
= 0; i
< NES_MAX_LINK_CHECK
; i
++) {
547 pcs_control_status0
= nes_read_indexed(nesdev
,
548 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
549 pcs_control_status1
= nes_read_indexed(nesdev
,
550 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
551 if ((0x0F000100 == (pcs_control_status0
& 0x0F000100))
552 || (0x0F000100 == (pcs_control_status1
& 0x0F000100)))
554 usleep_range(1000, 2000);
557 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
558 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F0C8);
560 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
561 reset_value
|= 0x0000003d;
562 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
564 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
565 & 0x00000040) != 0x00000040) && (j
++ < 5000));
566 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
568 pcs_control_status0
= nes_read_indexed(nesdev
,
569 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
570 pcs_control_status1
= nes_read_indexed(nesdev
,
571 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
573 for (i
= 0; i
< NES_MAX_LINK_CHECK
; i
++) {
574 pcs_control_status0
= nes_read_indexed(nesdev
,
575 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
576 pcs_control_status1
= nes_read_indexed(nesdev
,
577 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
578 if ((0x0F000100 == (pcs_control_status0
& 0x0F000100))
579 || (0x0F000100 == (pcs_control_status1
& 0x0F000100))) {
580 if (++ext_cnt
> int_cnt
) {
581 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
582 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
,
585 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
586 reset_value
|= 0x0000003d;
587 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
589 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
590 & 0x00000040) != 0x00000040) && (j
++ < 5000));
591 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
595 usleep_range(1000, 2000);
600 if (nesadapter
->hw_rev
== NE020_REV
) {
601 init_timer(&nesadapter
->mh_timer
);
602 nesadapter
->mh_timer
.function
= nes_mh_fix
;
603 nesadapter
->mh_timer
.expires
= jiffies
+ (HZ
/5); /* 1 second */
604 nesadapter
->mh_timer
.data
= (unsigned long)nesdev
;
605 add_timer(&nesadapter
->mh_timer
);
607 nes_write32(nesdev
->regs
+NES_INTF_INT_STAT
, 0x0f000000);
610 init_timer(&nesadapter
->lc_timer
);
611 nesadapter
->lc_timer
.function
= nes_clc
;
612 nesadapter
->lc_timer
.expires
= jiffies
+ 3600 * HZ
; /* 1 hour */
613 nesadapter
->lc_timer
.data
= (unsigned long)nesdev
;
614 add_timer(&nesadapter
->lc_timer
);
616 list_add_tail(&nesadapter
->list
, &nes_adapter_list
);
618 for (func_index
= 0; func_index
< 8; func_index
++) {
619 pci_bus_read_config_word(nesdev
->pcidev
->bus
,
620 PCI_DEVFN(PCI_SLOT(nesdev
->pcidev
->devfn
),
621 func_index
), 0, &vendor_id
);
622 if (vendor_id
== 0xffff)
625 nes_debug(NES_DBG_INIT
, "%s %d functions found for %s.\n", __func__
,
626 func_index
, pci_name(nesdev
->pcidev
));
627 nesadapter
->adapter_fcn_count
= func_index
;
634 * nes_reset_adapter_ne020
636 static unsigned int nes_reset_adapter_ne020(struct nes_device
*nesdev
, u8
*OneG_Mode
)
642 u32temp
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
643 port_count
= ((u32temp
& 0x00000300) >> 8) + 1;
644 /* TODO: assuming that both SERDES are set the same for now */
645 *OneG_Mode
= (u32temp
& 0x00003c00) ? 0 : 1;
646 nes_debug(NES_DBG_INIT
, "Initial Software Reset = 0x%08X, port_count=%u\n",
647 u32temp
, port_count
);
649 nes_debug(NES_DBG_INIT
, "Running in 1G mode.\n");
650 u32temp
&= 0xff00ffc0;
651 switch (port_count
) {
653 u32temp
|= 0x00ee0000;
656 u32temp
|= 0x00cc0000;
659 u32temp
|= 0x00000000;
666 /* check and do full reset if needed */
667 if (nes_read_indexed(nesdev
, NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8))) {
668 nes_debug(NES_DBG_INIT
, "Issuing Full Soft reset = 0x%08X\n", u32temp
| 0xd);
669 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, u32temp
| 0xd);
672 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
) & 0x00000040) == 0) && i
++ < 10000)
675 nes_debug(NES_DBG_INIT
, "Did not see full soft reset done.\n");
680 while ((nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
) != 0x80) && i
++ < 10000)
683 printk(KERN_ERR PFX
"Internal CPU not ready, status = %02X\n",
684 nes_read_indexed(nesdev
, NES_IDX_INT_CPU_STATUS
));
690 switch (port_count
) {
692 u32temp
|= 0x00ee0010;
695 u32temp
|= 0x00cc0030;
698 u32temp
|= 0x00000030;
702 nes_debug(NES_DBG_INIT
, "Issuing Port Soft reset = 0x%08X\n", u32temp
| 0xd);
703 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, u32temp
| 0xd);
706 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
) & 0x00000040) == 0) && i
++ < 10000)
709 nes_debug(NES_DBG_INIT
, "Did not see port soft reset done.\n");
715 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
)
716 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
719 nes_debug(NES_DBG_INIT
, "Serdes 0 not ready, status=%x\n", u32temp
);
724 if (port_count
> 1) {
726 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS1
)
727 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
730 nes_debug(NES_DBG_INIT
, "Serdes 1 not ready, status=%x\n", u32temp
);
742 static int nes_init_serdes(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
,
743 struct nes_adapter
*nesadapter
, u8 OneG_Mode
)
749 if (hw_rev
!= NE020_REV
) {
751 switch (nesadapter
->phy_type
[0]) {
752 case NES_PHY_TYPE_CX4
:
754 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000FFFAA);
756 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000FF);
758 case NES_PHY_TYPE_KR
:
759 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000FF);
760 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP0
, 0x00000000);
762 case NES_PHY_TYPE_PUMA_1G
:
763 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000FF);
764 sds
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
);
766 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
, sds
);
769 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000FF);
774 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE0
, 0x11110000);
780 if (!(OneG_Mode
&& (nesadapter
->phy_type
[1] != NES_PHY_TYPE_PUMA_1G
)))
781 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL1
, 0x000000FF);
783 switch (nesadapter
->phy_type
[1]) {
784 case NES_PHY_TYPE_ARGUS
:
785 case NES_PHY_TYPE_SFP_D
:
786 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP0
, 0x00000000);
787 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP1
, 0x00000000);
789 case NES_PHY_TYPE_CX4
:
791 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL1
, 0x000FFFAA);
793 case NES_PHY_TYPE_KR
:
794 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP1
, 0x00000000);
796 case NES_PHY_TYPE_PUMA_1G
:
797 sds
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
799 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, sds
);
802 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_HIGHZ_LANE_MODE1
, 0x11110000);
803 sds
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
805 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, sds
);
809 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
, 0x00000008);
811 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
)
812 & 0x0000000f)) != 0x0000000f) && i
++ < 5000)
815 nes_debug(NES_DBG_PHY
, "Init: serdes 0 not ready, status=%x\n", u32temp
);
818 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP0
, 0x000bdef7);
819 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_DRIVE0
, 0x9ce73000);
820 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_MODE0
, 0x0ff00000);
821 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_SIGDET0
, 0x00000000);
822 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_BYPASS0
, 0x00000000);
823 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0
, 0x00000000);
825 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0
, 0xf0182222);
827 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0
, 0xf0042222);
829 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL0
, 0x000000ff);
830 if (port_count
> 1) {
832 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x00000048);
834 while (((u32temp
= (nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS1
)
835 & 0x0000000f)) != 0x0000000f) && (i
++ < 5000))
838 printk("%s: Init: serdes 1 not ready, status=%x\n", __func__
, u32temp
);
841 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_EMP1
, 0x000bdef7);
842 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_TX_DRIVE1
, 0x9ce73000);
843 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_MODE1
, 0x0ff00000);
844 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_SIGDET1
, 0x00000000);
845 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_BYPASS1
, 0x00000000);
846 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL1
, 0x00000000);
847 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_RX_EQ_CONTROL1
, 0xf0002222);
848 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_CDR_CONTROL1
, 0x000000ff);
857 * Initialize registers for ne020 hardware
859 static void nes_init_csr_ne020(struct nes_device
*nesdev
, u8 hw_rev
, u8 port_count
)
863 nes_debug(NES_DBG_INIT
, "port_count=%d\n", port_count
);
865 nes_write_indexed(nesdev
, 0x000001E4, 0x00000007);
866 /* nes_write_indexed(nesdev, 0x000001E8, 0x000208C4); */
867 nes_write_indexed(nesdev
, 0x000001E8, 0x00020874);
868 nes_write_indexed(nesdev
, 0x000001D8, 0x00048002);
869 /* nes_write_indexed(nesdev, 0x000001D8, 0x0004B002); */
870 nes_write_indexed(nesdev
, 0x000001FC, 0x00050005);
871 nes_write_indexed(nesdev
, 0x00000600, 0x55555555);
872 nes_write_indexed(nesdev
, 0x00000604, 0x55555555);
874 /* TODO: move these MAC register settings to NIC bringup */
875 nes_write_indexed(nesdev
, 0x00002000, 0x00000001);
876 nes_write_indexed(nesdev
, 0x00002004, 0x00000001);
877 nes_write_indexed(nesdev
, 0x00002008, 0x0000FFFF);
878 nes_write_indexed(nesdev
, 0x0000200C, 0x00000001);
879 nes_write_indexed(nesdev
, 0x00002010, 0x000003c1);
880 nes_write_indexed(nesdev
, 0x0000201C, 0x75345678);
881 if (port_count
> 1) {
882 nes_write_indexed(nesdev
, 0x00002200, 0x00000001);
883 nes_write_indexed(nesdev
, 0x00002204, 0x00000001);
884 nes_write_indexed(nesdev
, 0x00002208, 0x0000FFFF);
885 nes_write_indexed(nesdev
, 0x0000220C, 0x00000001);
886 nes_write_indexed(nesdev
, 0x00002210, 0x000003c1);
887 nes_write_indexed(nesdev
, 0x0000221C, 0x75345678);
888 nes_write_indexed(nesdev
, 0x00000908, 0x20000001);
890 if (port_count
> 2) {
891 nes_write_indexed(nesdev
, 0x00002400, 0x00000001);
892 nes_write_indexed(nesdev
, 0x00002404, 0x00000001);
893 nes_write_indexed(nesdev
, 0x00002408, 0x0000FFFF);
894 nes_write_indexed(nesdev
, 0x0000240C, 0x00000001);
895 nes_write_indexed(nesdev
, 0x00002410, 0x000003c1);
896 nes_write_indexed(nesdev
, 0x0000241C, 0x75345678);
897 nes_write_indexed(nesdev
, 0x00000910, 0x20000001);
899 nes_write_indexed(nesdev
, 0x00002600, 0x00000001);
900 nes_write_indexed(nesdev
, 0x00002604, 0x00000001);
901 nes_write_indexed(nesdev
, 0x00002608, 0x0000FFFF);
902 nes_write_indexed(nesdev
, 0x0000260C, 0x00000001);
903 nes_write_indexed(nesdev
, 0x00002610, 0x000003c1);
904 nes_write_indexed(nesdev
, 0x0000261C, 0x75345678);
905 nes_write_indexed(nesdev
, 0x00000918, 0x20000001);
908 nes_write_indexed(nesdev
, 0x00005000, 0x00018000);
909 /* nes_write_indexed(nesdev, 0x00005000, 0x00010000); */
910 nes_write_indexed(nesdev
, NES_IDX_WQM_CONFIG1
, (wqm_quanta
<< 1) |
912 nes_write_indexed(nesdev
, 0x00005008, 0x1F1F1F1F);
913 nes_write_indexed(nesdev
, 0x00005010, 0x1F1F1F1F);
914 nes_write_indexed(nesdev
, 0x00005018, 0x1F1F1F1F);
915 nes_write_indexed(nesdev
, 0x00005020, 0x1F1F1F1F);
916 nes_write_indexed(nesdev
, 0x00006090, 0xFFFFFFFF);
918 /* TODO: move this to code, get from EEPROM */
919 nes_write_indexed(nesdev
, 0x00000900, 0x20000001);
920 nes_write_indexed(nesdev
, 0x000060C0, 0x0000028e);
921 nes_write_indexed(nesdev
, 0x000060C8, 0x00000020);
923 nes_write_indexed(nesdev
, 0x000001EC, 0x7b2625a0);
924 /* nes_write_indexed(nesdev, 0x000001EC, 0x5f2625a0); */
926 if (hw_rev
!= NE020_REV
) {
927 u32temp
= nes_read_indexed(nesdev
, 0x000008e8);
928 u32temp
|= 0x80000000;
929 nes_write_indexed(nesdev
, 0x000008e8, u32temp
);
930 u32temp
= nes_read_indexed(nesdev
, 0x000021f8);
931 u32temp
&= 0x7fffffff;
932 u32temp
|= 0x7fff0010;
933 nes_write_indexed(nesdev
, 0x000021f8, u32temp
);
934 if (port_count
> 1) {
935 u32temp
= nes_read_indexed(nesdev
, 0x000023f8);
936 u32temp
&= 0x7fffffff;
937 u32temp
|= 0x7fff0010;
938 nes_write_indexed(nesdev
, 0x000023f8, u32temp
);
945 * nes_destroy_adapter - destroy the adapter structure
947 void nes_destroy_adapter(struct nes_adapter
*nesadapter
)
949 struct nes_adapter
*tmp_adapter
;
951 list_for_each_entry(tmp_adapter
, &nes_adapter_list
, list
) {
952 nes_debug(NES_DBG_SHUTDOWN
, "Nes Adapter list entry = 0x%p.\n",
956 nesadapter
->ref_count
--;
957 if (!nesadapter
->ref_count
) {
958 if (nesadapter
->hw_rev
== NE020_REV
) {
959 del_timer(&nesadapter
->mh_timer
);
961 del_timer(&nesadapter
->lc_timer
);
963 list_del(&nesadapter
->list
);
972 int nes_init_cqp(struct nes_device
*nesdev
)
974 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
975 struct nes_hw_cqp_qp_context
*cqp_qp_context
;
976 struct nes_hw_cqp_wqe
*cqp_wqe
;
977 struct nes_hw_ceq
*ceq
;
978 struct nes_hw_ceq
*nic_ceq
;
979 struct nes_hw_aeq
*aeq
;
987 /* allocate CQP memory */
988 /* Need to add max_cq to the aeq size once cq overflow checking is added back */
989 /* SQ is 512 byte aligned, others are 256 byte aligned */
990 nesdev
->cqp_mem_size
= 512 +
991 (sizeof(struct nes_hw_cqp_wqe
) * NES_CQP_SQ_SIZE
) +
992 (sizeof(struct nes_hw_cqe
) * NES_CCQ_SIZE
) +
993 max(((u32
)sizeof(struct nes_hw_ceqe
) * NES_CCEQ_SIZE
), (u32
)256) +
994 max(((u32
)sizeof(struct nes_hw_ceqe
) * NES_NIC_CEQ_SIZE
), (u32
)256) +
995 (sizeof(struct nes_hw_aeqe
) * nesadapter
->max_qp
) +
996 sizeof(struct nes_hw_cqp_qp_context
);
998 nesdev
->cqp_vbase
= pci_zalloc_consistent(nesdev
->pcidev
,
999 nesdev
->cqp_mem_size
,
1000 &nesdev
->cqp_pbase
);
1001 if (!nesdev
->cqp_vbase
) {
1002 nes_debug(NES_DBG_INIT
, "Unable to allocate memory for host descriptor rings\n");
1006 /* Allocate a twice the number of CQP requests as the SQ size */
1007 nesdev
->nes_cqp_requests
= kzalloc(sizeof(struct nes_cqp_request
) *
1008 2 * NES_CQP_SQ_SIZE
, GFP_KERNEL
);
1009 if (!nesdev
->nes_cqp_requests
) {
1010 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
, nesdev
->cqp
.sq_vbase
,
1011 nesdev
->cqp
.sq_pbase
);
1015 nes_debug(NES_DBG_INIT
, "Allocated CQP structures at %p (phys = %016lX), size = %u.\n",
1016 nesdev
->cqp_vbase
, (unsigned long)nesdev
->cqp_pbase
, nesdev
->cqp_mem_size
);
1018 spin_lock_init(&nesdev
->cqp
.lock
);
1019 init_waitqueue_head(&nesdev
->cqp
.waitq
);
1021 /* Setup Various Structures */
1022 vmem
= (void *)(((unsigned long)nesdev
->cqp_vbase
+ (512 - 1)) &
1023 ~(unsigned long)(512 - 1));
1024 pmem
= (dma_addr_t
)(((unsigned long long)nesdev
->cqp_pbase
+ (512 - 1)) &
1025 ~(unsigned long long)(512 - 1));
1027 nesdev
->cqp
.sq_vbase
= vmem
;
1028 nesdev
->cqp
.sq_pbase
= pmem
;
1029 nesdev
->cqp
.sq_size
= NES_CQP_SQ_SIZE
;
1030 nesdev
->cqp
.sq_head
= 0;
1031 nesdev
->cqp
.sq_tail
= 0;
1032 nesdev
->cqp
.qp_id
= PCI_FUNC(nesdev
->pcidev
->devfn
);
1034 vmem
+= (sizeof(struct nes_hw_cqp_wqe
) * nesdev
->cqp
.sq_size
);
1035 pmem
+= (sizeof(struct nes_hw_cqp_wqe
) * nesdev
->cqp
.sq_size
);
1037 nesdev
->ccq
.cq_vbase
= vmem
;
1038 nesdev
->ccq
.cq_pbase
= pmem
;
1039 nesdev
->ccq
.cq_size
= NES_CCQ_SIZE
;
1040 nesdev
->ccq
.cq_head
= 0;
1041 nesdev
->ccq
.ce_handler
= nes_cqp_ce_handler
;
1042 nesdev
->ccq
.cq_number
= PCI_FUNC(nesdev
->pcidev
->devfn
);
1044 vmem
+= (sizeof(struct nes_hw_cqe
) * nesdev
->ccq
.cq_size
);
1045 pmem
+= (sizeof(struct nes_hw_cqe
) * nesdev
->ccq
.cq_size
);
1047 nesdev
->ceq_index
= PCI_FUNC(nesdev
->pcidev
->devfn
);
1048 ceq
= &nesadapter
->ceq
[nesdev
->ceq_index
];
1049 ceq
->ceq_vbase
= vmem
;
1050 ceq
->ceq_pbase
= pmem
;
1051 ceq
->ceq_size
= NES_CCEQ_SIZE
;
1054 vmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * ceq
->ceq_size
), (u32
)256);
1055 pmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * ceq
->ceq_size
), (u32
)256);
1057 nesdev
->nic_ceq_index
= PCI_FUNC(nesdev
->pcidev
->devfn
) + 8;
1058 nic_ceq
= &nesadapter
->ceq
[nesdev
->nic_ceq_index
];
1059 nic_ceq
->ceq_vbase
= vmem
;
1060 nic_ceq
->ceq_pbase
= pmem
;
1061 nic_ceq
->ceq_size
= NES_NIC_CEQ_SIZE
;
1062 nic_ceq
->ceq_head
= 0;
1064 vmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * nic_ceq
->ceq_size
), (u32
)256);
1065 pmem
+= max(((u32
)sizeof(struct nes_hw_ceqe
) * nic_ceq
->ceq_size
), (u32
)256);
1067 aeq
= &nesadapter
->aeq
[PCI_FUNC(nesdev
->pcidev
->devfn
)];
1068 aeq
->aeq_vbase
= vmem
;
1069 aeq
->aeq_pbase
= pmem
;
1070 aeq
->aeq_size
= nesadapter
->max_qp
;
1073 /* Setup QP Context */
1074 vmem
+= (sizeof(struct nes_hw_aeqe
) * aeq
->aeq_size
);
1075 pmem
+= (sizeof(struct nes_hw_aeqe
) * aeq
->aeq_size
);
1077 cqp_qp_context
= vmem
;
1078 cqp_qp_context
->context_words
[0] =
1079 cpu_to_le32((PCI_FUNC(nesdev
->pcidev
->devfn
) << 12) + (2 << 10));
1080 cqp_qp_context
->context_words
[1] = 0;
1081 cqp_qp_context
->context_words
[2] = cpu_to_le32((u32
)nesdev
->cqp
.sq_pbase
);
1082 cqp_qp_context
->context_words
[3] = cpu_to_le32(((u64
)nesdev
->cqp
.sq_pbase
) >> 32);
1085 /* Write the address to Create CQP */
1086 if ((sizeof(dma_addr_t
) > 4)) {
1087 nes_write_indexed(nesdev
,
1088 NES_IDX_CREATE_CQP_HIGH
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
1091 nes_write_indexed(nesdev
,
1092 NES_IDX_CREATE_CQP_HIGH
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8), 0);
1094 nes_write_indexed(nesdev
,
1095 NES_IDX_CREATE_CQP_LOW
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8),
1098 INIT_LIST_HEAD(&nesdev
->cqp_avail_reqs
);
1099 INIT_LIST_HEAD(&nesdev
->cqp_pending_reqs
);
1101 for (count
= 0; count
< 2*NES_CQP_SQ_SIZE
; count
++) {
1102 init_waitqueue_head(&nesdev
->nes_cqp_requests
[count
].waitq
);
1103 list_add_tail(&nesdev
->nes_cqp_requests
[count
].list
, &nesdev
->cqp_avail_reqs
);
1106 /* Write Create CCQ WQE */
1107 cqp_head
= nesdev
->cqp
.sq_head
++;
1108 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1109 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1110 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1111 (NES_CQP_CREATE_CQ
| NES_CQP_CQ_CEQ_VALID
|
1112 NES_CQP_CQ_CHK_OVERFLOW
| ((u32
)nesdev
->ccq
.cq_size
<< 16)));
1113 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1114 (nesdev
->ccq
.cq_number
|
1115 ((u32
)nesdev
->ceq_index
<< 16)));
1116 u64temp
= (u64
)nesdev
->ccq
.cq_pbase
;
1117 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1118 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] = 0;
1119 u64temp
= (unsigned long)&nesdev
->ccq
;
1120 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX
] =
1121 cpu_to_le32((u32
)(u64temp
>> 1));
1122 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] =
1123 cpu_to_le32(((u32
)((u64temp
) >> 33)) & 0x7FFFFFFF);
1124 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX
] = 0;
1126 /* Write Create CEQ WQE */
1127 cqp_head
= nesdev
->cqp
.sq_head
++;
1128 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1129 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1130 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1131 (NES_CQP_CREATE_CEQ
+ ((u32
)nesdev
->ceq_index
<< 8)));
1132 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX
, ceq
->ceq_size
);
1133 u64temp
= (u64
)ceq
->ceq_pbase
;
1134 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1136 /* Write Create AEQ WQE */
1137 cqp_head
= nesdev
->cqp
.sq_head
++;
1138 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1139 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1140 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1141 (NES_CQP_CREATE_AEQ
+ ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 8)));
1142 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_AEQ_WQE_ELEMENT_COUNT_IDX
, aeq
->aeq_size
);
1143 u64temp
= (u64
)aeq
->aeq_pbase
;
1144 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1146 /* Write Create NIC CEQ WQE */
1147 cqp_head
= nesdev
->cqp
.sq_head
++;
1148 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1149 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1150 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1151 (NES_CQP_CREATE_CEQ
+ ((u32
)nesdev
->nic_ceq_index
<< 8)));
1152 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_CEQ_WQE_ELEMENT_COUNT_IDX
, nic_ceq
->ceq_size
);
1153 u64temp
= (u64
)nic_ceq
->ceq_pbase
;
1154 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1156 /* Poll until CCQP done */
1159 if (count
++ > 1000) {
1160 printk(KERN_ERR PFX
"Error creating CQP\n");
1161 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
,
1162 nesdev
->cqp_vbase
, nesdev
->cqp_pbase
);
1166 } while (!(nes_read_indexed(nesdev
,
1167 NES_IDX_QP_CONTROL
+ (PCI_FUNC(nesdev
->pcidev
->devfn
) * 8)) & (1 << 8)));
1169 nes_debug(NES_DBG_INIT
, "CQP Status = 0x%08X\n", nes_read_indexed(nesdev
,
1170 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1172 u32temp
= 0x04800000;
1173 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, u32temp
| nesdev
->cqp
.qp_id
);
1175 /* wait for the CCQ, CEQ, and AEQ to get created */
1178 if (count
++ > 1000) {
1179 printk(KERN_ERR PFX
"Error creating CCQ, CEQ, and AEQ\n");
1180 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
,
1181 nesdev
->cqp_vbase
, nesdev
->cqp_pbase
);
1185 } while (((nes_read_indexed(nesdev
,
1186 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)) & (15<<8)) != (15<<8)));
1188 /* dump the QP status value */
1189 nes_debug(NES_DBG_INIT
, "QP Status = 0x%08X\n", nes_read_indexed(nesdev
,
1190 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1192 nesdev
->cqp
.sq_tail
++;
1201 int nes_destroy_cqp(struct nes_device
*nesdev
)
1203 struct nes_hw_cqp_wqe
*cqp_wqe
;
1206 unsigned long flags
;
1212 } while (!(nesdev
->cqp
.sq_head
== nesdev
->cqp
.sq_tail
));
1215 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
, NES_CQE_ALLOC_RESET
|
1216 nesdev
->ccq
.cq_number
);
1218 /* Disable device interrupts */
1219 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x7fffffff);
1221 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1223 /* Destroy the AEQ */
1224 cqp_head
= nesdev
->cqp
.sq_head
++;
1225 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1226 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1227 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_AEQ
|
1228 ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 8));
1229 cqp_wqe
->wqe_words
[NES_CQP_WQE_COMP_CTX_HIGH_IDX
] = 0;
1231 /* Destroy the NIC CEQ */
1232 cqp_head
= nesdev
->cqp
.sq_head
++;
1233 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1234 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1235 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CEQ
|
1236 ((u32
)nesdev
->nic_ceq_index
<< 8));
1238 /* Destroy the CEQ */
1239 cqp_head
= nesdev
->cqp
.sq_head
++;
1240 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1241 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1242 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CEQ
|
1243 (nesdev
->ceq_index
<< 8));
1245 /* Destroy the CCQ */
1246 cqp_head
= nesdev
->cqp
.sq_head
++;
1247 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1248 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1249 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_CQ
);
1250 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesdev
->ccq
.cq_number
|
1251 ((u32
)nesdev
->ceq_index
<< 16));
1254 cqp_head
= nesdev
->cqp
.sq_head
++;
1255 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
1256 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1257 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_DESTROY_QP
|
1258 NES_CQP_QP_TYPE_CQP
);
1259 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesdev
->cqp
.qp_id
);
1262 /* Ring doorbell (5 WQEs) */
1263 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x05800000 | nesdev
->cqp
.qp_id
);
1265 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1267 /* wait for the CCQ, CEQ, and AEQ to get destroyed */
1270 if (count
++ > 1000) {
1271 printk(KERN_ERR PFX
"Function%d: Error destroying CCQ, CEQ, and AEQ\n",
1272 PCI_FUNC(nesdev
->pcidev
->devfn
));
1276 } while (((nes_read_indexed(nesdev
,
1277 NES_IDX_QP_CONTROL
+ (PCI_FUNC(nesdev
->pcidev
->devfn
)*8)) & (15 << 8)) != 0));
1279 /* dump the QP status value */
1280 nes_debug(NES_DBG_SHUTDOWN
, "Function%d: QP Status = 0x%08X\n",
1281 PCI_FUNC(nesdev
->pcidev
->devfn
),
1282 nes_read_indexed(nesdev
,
1283 NES_IDX_QP_CONTROL
+(PCI_FUNC(nesdev
->pcidev
->devfn
)*8)));
1285 kfree(nesdev
->nes_cqp_requests
);
1287 /* Free the control structures */
1288 pci_free_consistent(nesdev
->pcidev
, nesdev
->cqp_mem_size
, nesdev
->cqp
.sq_vbase
,
1289 nesdev
->cqp
.sq_pbase
);
1298 static int nes_init_1g_phy(struct nes_device
*nesdev
, u8 phy_type
, u8 phy_index
)
1304 nes_read_1G_phy_reg(nesdev
, 1, phy_index
, &phy_data
);
1305 nes_write_1G_phy_reg(nesdev
, 23, phy_index
, 0xb000);
1308 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, 0x8000);
1312 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1313 if (counter
++ > 100) {
1317 } while (phy_data
& 0x8000);
1319 /* Setting no phy loopback */
1322 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, phy_data
);
1323 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1324 nes_read_1G_phy_reg(nesdev
, 0x17, phy_index
, &phy_data
);
1325 nes_read_1G_phy_reg(nesdev
, 0x1e, phy_index
, &phy_data
);
1327 /* Setting the interrupt mask */
1328 nes_read_1G_phy_reg(nesdev
, 0x19, phy_index
, &phy_data
);
1329 nes_write_1G_phy_reg(nesdev
, 0x19, phy_index
, 0xffee);
1330 nes_read_1G_phy_reg(nesdev
, 0x19, phy_index
, &phy_data
);
1332 /* turning on flow control */
1333 nes_read_1G_phy_reg(nesdev
, 4, phy_index
, &phy_data
);
1334 nes_write_1G_phy_reg(nesdev
, 4, phy_index
, (phy_data
& ~(0x03E0)) | 0xc00);
1335 nes_read_1G_phy_reg(nesdev
, 4, phy_index
, &phy_data
);
1337 /* Clear Half duplex */
1338 nes_read_1G_phy_reg(nesdev
, 9, phy_index
, &phy_data
);
1339 nes_write_1G_phy_reg(nesdev
, 9, phy_index
, phy_data
& ~(0x0100));
1340 nes_read_1G_phy_reg(nesdev
, 9, phy_index
, &phy_data
);
1342 nes_read_1G_phy_reg(nesdev
, 0, phy_index
, &phy_data
);
1343 nes_write_1G_phy_reg(nesdev
, 0, phy_index
, phy_data
| 0x0300);
1352 static int nes_init_2025_phy(struct nes_device
*nesdev
, u8 phy_type
, u8 phy_index
)
1354 u32 temp_phy_data
= 0;
1355 u32 temp_phy_data2
= 0;
1358 u32 mac_index
= nesdev
->mac_index
;
1360 unsigned int first_attempt
= 1;
1362 /* Check firmware heartbeat */
1363 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1364 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1366 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1367 temp_phy_data2
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1369 if (temp_phy_data
!= temp_phy_data2
) {
1370 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7fd);
1371 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1372 if ((temp_phy_data
& 0xff) > 0x20)
1374 printk(PFX
"Reinitialize external PHY\n");
1377 /* no heartbeat, configure the PHY */
1378 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0x0000, 0x8000);
1379 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc300, 0x0000);
1380 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc316, 0x000A);
1381 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc318, 0x0052);
1384 case NES_PHY_TYPE_ARGUS
:
1385 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc316, 0x000A);
1386 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc318, 0x0052);
1387 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc302, 0x000C);
1388 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc319, 0x0008);
1389 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0027, 0x0001);
1390 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc31a, 0x0098);
1391 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0026, 0x0E00);
1394 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd006, 0x0007);
1395 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd007, 0x000A);
1396 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd008, 0x0009);
1399 case NES_PHY_TYPE_SFP_D
:
1400 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc316, 0x000A);
1401 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc318, 0x0052);
1402 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc302, 0x0004);
1403 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc319, 0x0038);
1404 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0027, 0x0013);
1405 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc31a, 0x0098);
1406 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0026, 0x0E00);
1409 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd006, 0x0007);
1410 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd007, 0x000A);
1411 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd008, 0x0009);
1414 case NES_PHY_TYPE_KR
:
1415 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc316, 0x000A);
1416 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc318, 0x0052);
1417 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc302, 0x000C);
1418 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc319, 0x0010);
1419 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0027, 0x0013);
1420 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc31a, 0x0080);
1421 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0026, 0x0E00);
1424 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd006, 0x000B);
1425 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd007, 0x0003);
1426 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd008, 0x0004);
1428 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0022, 0x406D);
1429 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0023, 0x0020);
1433 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0x0028, 0xA528);
1435 /* Bring PHY out of reset */
1436 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc300, 0x0002);
1438 /* Check for heartbeat */
1441 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1442 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1444 if (counter
++ > 150) {
1445 printk(PFX
"No PHY heartbeat\n");
1449 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7ee);
1450 temp_phy_data2
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1451 } while ((temp_phy_data2
== temp_phy_data
));
1453 /* wait for tracking */
1456 nes_read_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xd7fd);
1457 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
1458 if (counter
++ > 300) {
1459 if (((temp_phy_data
& 0xff) == 0x0) && first_attempt
) {
1462 /* reset AMCC PHY and try again */
1463 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xe854, 0x00c0);
1464 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x3, 0xe854, 0x0040);
1472 } while ((temp_phy_data
& 0xff) < 0x30);
1474 /* setup signal integrity */
1475 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xd003, 0x0000);
1476 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00D, 0x00FE);
1477 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00E, 0x0032);
1478 if (phy_type
== NES_PHY_TYPE_KR
) {
1479 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00F, 0x000C);
1481 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xF00F, 0x0002);
1482 nes_write_10G_phy_reg(nesdev
, phy_index
, 0x1, 0xc314, 0x0063);
1486 sds
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+ mac_index
* 0x200);
1488 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+ mac_index
* 0x200, sds
);
1490 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL0
+ mac_index
* 0x200, sds
);
1493 while (((nes_read32(nesdev
->regs
+ NES_SOFTWARE_RESET
) & 0x00000040) != 0x00000040)
1494 && (counter
++ < 5000))
1504 int nes_init_phy(struct nes_device
*nesdev
)
1506 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
1507 u32 mac_index
= nesdev
->mac_index
;
1509 unsigned long flags
;
1510 u8 phy_type
= nesadapter
->phy_type
[mac_index
];
1511 u8 phy_index
= nesadapter
->phy_index
[mac_index
];
1514 tx_config
= nes_read_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
);
1515 if (phy_type
== NES_PHY_TYPE_1G
) {
1516 /* setup 1G MDIO operation */
1517 tx_config
&= 0xFFFFFFE3;
1520 /* setup 10G MDIO operation */
1521 tx_config
&= 0xFFFFFFE3;
1524 nes_write_indexed(nesdev
, NES_IDX_MAC_TX_CONFIG
, tx_config
);
1526 spin_lock_irqsave(&nesdev
->nesadapter
->phy_lock
, flags
);
1529 case NES_PHY_TYPE_1G
:
1530 ret
= nes_init_1g_phy(nesdev
, phy_type
, phy_index
);
1532 case NES_PHY_TYPE_ARGUS
:
1533 case NES_PHY_TYPE_SFP_D
:
1534 case NES_PHY_TYPE_KR
:
1535 ret
= nes_init_2025_phy(nesdev
, phy_type
, phy_index
);
1539 spin_unlock_irqrestore(&nesdev
->nesadapter
->phy_lock
, flags
);
1546 * nes_replenish_nic_rq
1548 static void nes_replenish_nic_rq(struct nes_vnic
*nesvnic
)
1550 unsigned long flags
;
1551 dma_addr_t bus_address
;
1552 struct sk_buff
*skb
;
1553 struct nes_hw_nic_rq_wqe
*nic_rqe
;
1554 struct nes_hw_nic
*nesnic
;
1555 struct nes_device
*nesdev
;
1556 struct nes_rskb_cb
*cb
;
1557 u32 rx_wqes_posted
= 0;
1559 nesnic
= &nesvnic
->nic
;
1560 nesdev
= nesvnic
->nesdev
;
1561 spin_lock_irqsave(&nesnic
->rq_lock
, flags
);
1562 if (nesnic
->replenishing_rq
!=0) {
1563 if (((nesnic
->rq_size
-1) == atomic_read(&nesvnic
->rx_skbs_needed
)) &&
1564 (atomic_read(&nesvnic
->rx_skb_timer_running
) == 0)) {
1565 atomic_set(&nesvnic
->rx_skb_timer_running
, 1);
1566 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1567 nesvnic
->rq_wqes_timer
.expires
= jiffies
+ (HZ
/2); /* 1/2 second */
1568 add_timer(&nesvnic
->rq_wqes_timer
);
1570 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1573 nesnic
->replenishing_rq
= 1;
1574 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1576 skb
= dev_alloc_skb(nesvnic
->max_frame_size
);
1578 skb
->dev
= nesvnic
->netdev
;
1580 bus_address
= pci_map_single(nesdev
->pcidev
,
1581 skb
->data
, nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
1582 cb
= (struct nes_rskb_cb
*)&skb
->cb
[0];
1583 cb
->busaddr
= bus_address
;
1584 cb
->maplen
= nesvnic
->max_frame_size
;
1586 nic_rqe
= &nesnic
->rq_vbase
[nesvnic
->nic
.rq_head
];
1587 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_1_0_IDX
] =
1588 cpu_to_le32(nesvnic
->max_frame_size
);
1589 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_3_2_IDX
] = 0;
1590 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
] =
1591 cpu_to_le32((u32
)bus_address
);
1592 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
] =
1593 cpu_to_le32((u32
)((u64
)bus_address
>> 32));
1594 nesnic
->rx_skb
[nesnic
->rq_head
] = skb
;
1596 nesnic
->rq_head
&= nesnic
->rq_size
- 1;
1597 atomic_dec(&nesvnic
->rx_skbs_needed
);
1599 if (++rx_wqes_posted
== 255) {
1600 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (rx_wqes_posted
<< 24) | nesnic
->qp_id
);
1604 spin_lock_irqsave(&nesnic
->rq_lock
, flags
);
1605 if (((nesnic
->rq_size
-1) == atomic_read(&nesvnic
->rx_skbs_needed
)) &&
1606 (atomic_read(&nesvnic
->rx_skb_timer_running
) == 0)) {
1607 atomic_set(&nesvnic
->rx_skb_timer_running
, 1);
1608 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1609 nesvnic
->rq_wqes_timer
.expires
= jiffies
+ (HZ
/2); /* 1/2 second */
1610 add_timer(&nesvnic
->rq_wqes_timer
);
1612 spin_unlock_irqrestore(&nesnic
->rq_lock
, flags
);
1615 } while (atomic_read(&nesvnic
->rx_skbs_needed
));
1618 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (rx_wqes_posted
<< 24) | nesnic
->qp_id
);
1619 nesnic
->replenishing_rq
= 0;
1624 * nes_rq_wqes_timeout
1626 static void nes_rq_wqes_timeout(unsigned long parm
)
1628 struct nes_vnic
*nesvnic
= (struct nes_vnic
*)parm
;
1629 printk("%s: Timer fired.\n", __func__
);
1630 atomic_set(&nesvnic
->rx_skb_timer_running
, 0);
1631 if (atomic_read(&nesvnic
->rx_skbs_needed
))
1632 nes_replenish_nic_rq(nesvnic
);
1639 int nes_init_nic_qp(struct nes_device
*nesdev
, struct net_device
*netdev
)
1641 struct nes_hw_cqp_wqe
*cqp_wqe
;
1642 struct nes_hw_nic_sq_wqe
*nic_sqe
;
1643 struct nes_hw_nic_qp_context
*nic_context
;
1644 struct sk_buff
*skb
;
1645 struct nes_hw_nic_rq_wqe
*nic_rqe
;
1646 struct nes_vnic
*nesvnic
= netdev_priv(netdev
);
1647 unsigned long flags
;
1655 struct nes_rskb_cb
*cb
;
1658 /* Allocate fragment, SQ, RQ, and CQ; Reuse CEQ based on the PCI function */
1659 nesvnic
->nic_mem_size
= 256 +
1660 (NES_NIC_WQ_SIZE
* sizeof(struct nes_first_frag
)) +
1661 (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
)) +
1662 (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
)) +
1663 (NES_NIC_WQ_SIZE
* 2 * sizeof(struct nes_hw_nic_cqe
)) +
1664 sizeof(struct nes_hw_nic_qp_context
);
1666 nesvnic
->nic_vbase
= pci_zalloc_consistent(nesdev
->pcidev
,
1667 nesvnic
->nic_mem_size
,
1668 &nesvnic
->nic_pbase
);
1669 if (!nesvnic
->nic_vbase
) {
1670 nes_debug(NES_DBG_INIT
, "Unable to allocate memory for NIC host descriptor rings\n");
1673 nes_debug(NES_DBG_INIT
, "Allocated NIC QP structures at %p (phys = %016lX), size = %u.\n",
1674 nesvnic
->nic_vbase
, (unsigned long)nesvnic
->nic_pbase
, nesvnic
->nic_mem_size
);
1676 vmem
= (void *)(((unsigned long)nesvnic
->nic_vbase
+ (256 - 1)) &
1677 ~(unsigned long)(256 - 1));
1678 pmem
= (dma_addr_t
)(((unsigned long long)nesvnic
->nic_pbase
+ (256 - 1)) &
1679 ~(unsigned long long)(256 - 1));
1681 /* Setup the first Fragment buffers */
1682 nesvnic
->nic
.first_frag_vbase
= vmem
;
1684 for (counter
= 0; counter
< NES_NIC_WQ_SIZE
; counter
++) {
1685 nesvnic
->nic
.frag_paddr
[counter
] = pmem
;
1686 pmem
+= sizeof(struct nes_first_frag
);
1690 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_first_frag
));
1692 nesvnic
->nic
.sq_vbase
= (void *)vmem
;
1693 nesvnic
->nic
.sq_pbase
= pmem
;
1694 nesvnic
->nic
.sq_head
= 0;
1695 nesvnic
->nic
.sq_tail
= 0;
1696 nesvnic
->nic
.sq_size
= NES_NIC_WQ_SIZE
;
1697 for (counter
= 0; counter
< NES_NIC_WQ_SIZE
; counter
++) {
1698 nic_sqe
= &nesvnic
->nic
.sq_vbase
[counter
];
1699 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_MISC_IDX
] =
1700 cpu_to_le32(NES_NIC_SQ_WQE_DISABLE_CHKSUM
|
1701 NES_NIC_SQ_WQE_COMPLETION
);
1702 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
] =
1703 cpu_to_le32((u32
)NES_FIRST_FRAG_SIZE
<< 16);
1704 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
] =
1705 cpu_to_le32((u32
)nesvnic
->nic
.frag_paddr
[counter
]);
1706 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
] =
1707 cpu_to_le32((u32
)((u64
)nesvnic
->nic
.frag_paddr
[counter
] >> 32));
1710 nesvnic
->get_cqp_request
= nes_get_cqp_request
;
1711 nesvnic
->post_cqp_request
= nes_post_cqp_request
;
1712 nesvnic
->mcrq_mcast_filter
= NULL
;
1714 spin_lock_init(&nesvnic
->nic
.rq_lock
);
1717 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
));
1718 pmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_sq_wqe
));
1721 nesvnic
->nic
.rq_vbase
= vmem
;
1722 nesvnic
->nic
.rq_pbase
= pmem
;
1723 nesvnic
->nic
.rq_head
= 0;
1724 nesvnic
->nic
.rq_tail
= 0;
1725 nesvnic
->nic
.rq_size
= NES_NIC_WQ_SIZE
;
1728 vmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
));
1729 pmem
+= (NES_NIC_WQ_SIZE
* sizeof(struct nes_hw_nic_rq_wqe
));
1731 if (nesdev
->nesadapter
->netdev_count
> 2)
1732 nesvnic
->mcrq_qp_id
= nesvnic
->nic_index
+ 32;
1734 nesvnic
->mcrq_qp_id
= nesvnic
->nic
.qp_id
+ 4;
1736 nesvnic
->nic_cq
.cq_vbase
= vmem
;
1737 nesvnic
->nic_cq
.cq_pbase
= pmem
;
1738 nesvnic
->nic_cq
.cq_head
= 0;
1739 nesvnic
->nic_cq
.cq_size
= NES_NIC_WQ_SIZE
* 2;
1741 nesvnic
->nic_cq
.ce_handler
= nes_nic_napi_ce_handler
;
1743 /* Send CreateCQ request to CQP */
1744 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1745 cqp_head
= nesdev
->cqp
.sq_head
;
1747 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1748 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1750 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(
1751 NES_CQP_CREATE_CQ
| NES_CQP_CQ_CEQ_VALID
|
1752 ((u32
)nesvnic
->nic_cq
.cq_size
<< 16));
1753 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(
1754 nesvnic
->nic_cq
.cq_number
| ((u32
)nesdev
->nic_ceq_index
<< 16));
1755 u64temp
= (u64
)nesvnic
->nic_cq
.cq_pbase
;
1756 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_CQ_WQE_PBL_LOW_IDX
, u64temp
);
1757 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] = 0;
1758 u64temp
= (unsigned long)&nesvnic
->nic_cq
;
1759 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_LOW_IDX
] = cpu_to_le32((u32
)(u64temp
>> 1));
1760 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_CQ_CONTEXT_HIGH_IDX
] =
1761 cpu_to_le32(((u32
)((u64temp
) >> 33)) & 0x7FFFFFFF);
1762 cqp_wqe
->wqe_words
[NES_CQP_CQ_WQE_DOORBELL_INDEX_HIGH_IDX
] = 0;
1763 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1765 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1766 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1768 /* Send CreateQP request to CQP */
1769 nic_context
= (void *)(&nesvnic
->nic_cq
.cq_vbase
[nesvnic
->nic_cq
.cq_size
]);
1770 nic_context
->context_words
[NES_NIC_CTX_MISC_IDX
] =
1771 cpu_to_le32((u32
)NES_NIC_CTX_SIZE
|
1772 ((u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << 12));
1773 nes_debug(NES_DBG_INIT
, "RX_WINDOW_BUFFER_PAGE_TABLE_SIZE = 0x%08X, RX_WINDOW_BUFFER_SIZE = 0x%08X\n",
1774 nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_PAGE_TABLE_SIZE
),
1775 nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_SIZE
));
1776 if (nes_read_indexed(nesdev
, NES_IDX_RX_WINDOW_BUFFER_SIZE
) != 0) {
1777 nic_context
->context_words
[NES_NIC_CTX_MISC_IDX
] |= cpu_to_le32(NES_NIC_BACK_STORE
);
1780 u64temp
= (u64
)nesvnic
->nic
.sq_pbase
;
1781 nic_context
->context_words
[NES_NIC_CTX_SQ_LOW_IDX
] = cpu_to_le32((u32
)u64temp
);
1782 nic_context
->context_words
[NES_NIC_CTX_SQ_HIGH_IDX
] = cpu_to_le32((u32
)(u64temp
>> 32));
1783 u64temp
= (u64
)nesvnic
->nic
.rq_pbase
;
1784 nic_context
->context_words
[NES_NIC_CTX_RQ_LOW_IDX
] = cpu_to_le32((u32
)u64temp
);
1785 nic_context
->context_words
[NES_NIC_CTX_RQ_HIGH_IDX
] = cpu_to_le32((u32
)(u64temp
>> 32));
1787 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(NES_CQP_CREATE_QP
|
1788 NES_CQP_QP_TYPE_NIC
);
1789 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesvnic
->nic
.qp_id
);
1790 u64temp
= (u64
)nesvnic
->nic_cq
.cq_pbase
+
1791 (nesvnic
->nic_cq
.cq_size
* sizeof(struct nes_hw_nic_cqe
));
1792 set_wqe_64bit_value(cqp_wqe
->wqe_words
, NES_CQP_QP_WQE_CONTEXT_LOW_IDX
, u64temp
);
1794 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1796 nesdev
->cqp
.sq_head
= cqp_head
;
1800 /* Ring doorbell (2 WQEs) */
1801 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x02800000 | nesdev
->cqp
.qp_id
);
1803 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1804 nes_debug(NES_DBG_INIT
, "Waiting for create NIC QP%u to complete.\n",
1805 nesvnic
->nic
.qp_id
);
1807 ret
= wait_event_timeout(nesdev
->cqp
.waitq
, (nesdev
->cqp
.sq_tail
== cqp_head
),
1809 nes_debug(NES_DBG_INIT
, "Create NIC QP%u completed, wait_event_timeout ret = %u.\n",
1810 nesvnic
->nic
.qp_id
, ret
);
1812 nes_debug(NES_DBG_INIT
, "NIC QP%u create timeout expired\n", nesvnic
->nic
.qp_id
);
1813 pci_free_consistent(nesdev
->pcidev
, nesvnic
->nic_mem_size
, nesvnic
->nic_vbase
,
1814 nesvnic
->nic_pbase
);
1818 /* Populate the RQ */
1819 for (counter
= 0; counter
< (NES_NIC_WQ_SIZE
- 1); counter
++) {
1820 skb
= dev_alloc_skb(nesvnic
->max_frame_size
);
1822 nes_debug(NES_DBG_INIT
, "%s: out of memory for receive skb\n", netdev
->name
);
1824 nes_destroy_nic_qp(nesvnic
);
1830 pmem
= pci_map_single(nesdev
->pcidev
, skb
->data
,
1831 nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
1832 cb
= (struct nes_rskb_cb
*)&skb
->cb
[0];
1834 cb
->maplen
= nesvnic
->max_frame_size
;
1836 nic_rqe
= &nesvnic
->nic
.rq_vbase
[counter
];
1837 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_1_0_IDX
] = cpu_to_le32(nesvnic
->max_frame_size
);
1838 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_LENGTH_3_2_IDX
] = 0;
1839 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
] = cpu_to_le32((u32
)pmem
);
1840 nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
] = cpu_to_le32((u32
)((u64
)pmem
>> 32));
1841 nesvnic
->nic
.rx_skb
[counter
] = skb
;
1844 wqe_count
= NES_NIC_WQ_SIZE
- 1;
1845 nesvnic
->nic
.rq_head
= wqe_count
;
1848 counter
= min(wqe_count
, ((u32
)255));
1849 wqe_count
-= counter
;
1850 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, (counter
<< 24) | nesvnic
->nic
.qp_id
);
1851 } while (wqe_count
);
1852 setup_timer(&nesvnic
->rq_wqes_timer
, nes_rq_wqes_timeout
,
1853 (unsigned long)nesvnic
);
1854 nes_debug(NES_DBG_INIT
, "NAPI support Enabled\n");
1855 if (nesdev
->nesadapter
->et_use_adaptive_rx_coalesce
)
1857 nes_nic_init_timer(nesdev
);
1858 if (netdev
->mtu
> 1500)
1860 nes_nic_init_timer_defaults(nesdev
, jumbomode
);
1862 if ((nesdev
->nesadapter
->allow_unaligned_fpdus
) &&
1863 (nes_init_mgt_qp(nesdev
, netdev
, nesvnic
))) {
1864 nes_debug(NES_DBG_INIT
, "%s: Out of memory for pau nic\n", netdev
->name
);
1865 nes_destroy_nic_qp(nesvnic
);
1874 * nes_destroy_nic_qp
1876 void nes_destroy_nic_qp(struct nes_vnic
*nesvnic
)
1879 dma_addr_t bus_address
;
1880 struct nes_device
*nesdev
= nesvnic
->nesdev
;
1881 struct nes_hw_cqp_wqe
*cqp_wqe
;
1882 struct nes_hw_nic_sq_wqe
*nic_sqe
;
1883 __le16
*wqe_fragment_length
;
1884 u16 wqe_fragment_index
;
1887 unsigned long flags
;
1888 struct sk_buff
*rx_skb
;
1889 struct nes_rskb_cb
*cb
;
1892 if (nesdev
->nesadapter
->allow_unaligned_fpdus
)
1893 nes_destroy_mgt(nesvnic
);
1895 /* clear wqe stall before destroying NIC QP */
1896 wqm_cfg0
= nes_read_indexed(nesdev
, NES_IDX_WQM_CONFIG0
);
1897 nes_write_indexed(nesdev
, NES_IDX_WQM_CONFIG0
, wqm_cfg0
& 0xFFFF7FFF);
1899 /* Free remaining NIC receive buffers */
1900 while (nesvnic
->nic
.rq_head
!= nesvnic
->nic
.rq_tail
) {
1901 rx_skb
= nesvnic
->nic
.rx_skb
[nesvnic
->nic
.rq_tail
];
1902 cb
= (struct nes_rskb_cb
*)&rx_skb
->cb
[0];
1903 pci_unmap_single(nesdev
->pcidev
, cb
->busaddr
, cb
->maplen
,
1904 PCI_DMA_FROMDEVICE
);
1906 dev_kfree_skb(nesvnic
->nic
.rx_skb
[nesvnic
->nic
.rq_tail
++]);
1907 nesvnic
->nic
.rq_tail
&= (nesvnic
->nic
.rq_size
- 1);
1910 /* Free remaining NIC transmit buffers */
1911 while (nesvnic
->nic
.sq_head
!= nesvnic
->nic
.sq_tail
) {
1912 nic_sqe
= &nesvnic
->nic
.sq_vbase
[nesvnic
->nic
.sq_tail
];
1913 wqe_fragment_index
= 1;
1914 wqe_fragment_length
= (__le16
*)
1915 &nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
];
1916 /* bump past the vlan tag */
1917 wqe_fragment_length
++;
1918 if (le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]) != 0) {
1919 u64temp
= (u64
)le32_to_cpu(
1920 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
1921 wqe_fragment_index
*2]);
1922 u64temp
+= ((u64
)le32_to_cpu(
1923 nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
1924 + wqe_fragment_index
*2]))<<32;
1925 bus_address
= (dma_addr_t
)u64temp
;
1926 if (test_and_clear_bit(nesvnic
->nic
.sq_tail
,
1927 nesvnic
->nic
.first_frag_overflow
)) {
1928 pci_unmap_single(nesdev
->pcidev
,
1930 le16_to_cpu(wqe_fragment_length
[
1931 wqe_fragment_index
++]),
1934 for (; wqe_fragment_index
< 5; wqe_fragment_index
++) {
1935 if (wqe_fragment_length
[wqe_fragment_index
]) {
1936 u64temp
= le32_to_cpu(
1938 NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
1939 wqe_fragment_index
*2]);
1940 u64temp
+= ((u64
)le32_to_cpu(
1942 NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
+
1943 wqe_fragment_index
*2]))<<32;
1944 bus_address
= (dma_addr_t
)u64temp
;
1945 pci_unmap_page(nesdev
->pcidev
,
1948 wqe_fragment_length
[
1949 wqe_fragment_index
]),
1955 if (nesvnic
->nic
.tx_skb
[nesvnic
->nic
.sq_tail
])
1957 nesvnic
->nic
.tx_skb
[nesvnic
->nic
.sq_tail
]);
1959 nesvnic
->nic
.sq_tail
= (nesvnic
->nic
.sq_tail
+ 1)
1960 & (nesvnic
->nic
.sq_size
- 1);
1963 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
1965 /* Destroy NIC QP */
1966 cqp_head
= nesdev
->cqp
.sq_head
;
1967 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1968 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1970 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1971 (NES_CQP_DESTROY_QP
| NES_CQP_QP_TYPE_NIC
));
1972 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1973 nesvnic
->nic
.qp_id
);
1975 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1978 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[cqp_head
];
1980 /* Destroy NIC CQ */
1981 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
1982 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
,
1983 (NES_CQP_DESTROY_CQ
| ((u32
)nesvnic
->nic_cq
.cq_size
<< 16)));
1984 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
1985 (nesvnic
->nic_cq
.cq_number
| ((u32
)nesdev
->nic_ceq_index
<< 16)));
1987 if (++cqp_head
>= nesdev
->cqp
.sq_size
)
1990 nesdev
->cqp
.sq_head
= cqp_head
;
1993 /* Ring doorbell (2 WQEs) */
1994 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x02800000 | nesdev
->cqp
.qp_id
);
1996 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
1997 nes_debug(NES_DBG_SHUTDOWN
, "Waiting for CQP, cqp_head=%u, cqp.sq_head=%u,"
1998 " cqp.sq_tail=%u, cqp.sq_size=%u\n",
1999 cqp_head
, nesdev
->cqp
.sq_head
,
2000 nesdev
->cqp
.sq_tail
, nesdev
->cqp
.sq_size
);
2002 ret
= wait_event_timeout(nesdev
->cqp
.waitq
, (nesdev
->cqp
.sq_tail
== cqp_head
),
2005 nes_debug(NES_DBG_SHUTDOWN
, "Destroy NIC QP returned, wait_event_timeout ret = %u, cqp_head=%u,"
2006 " cqp.sq_head=%u, cqp.sq_tail=%u\n",
2007 ret
, cqp_head
, nesdev
->cqp
.sq_head
, nesdev
->cqp
.sq_tail
);
2009 nes_debug(NES_DBG_SHUTDOWN
, "NIC QP%u destroy timeout expired\n",
2010 nesvnic
->nic
.qp_id
);
2013 pci_free_consistent(nesdev
->pcidev
, nesvnic
->nic_mem_size
, nesvnic
->nic_vbase
,
2014 nesvnic
->nic_pbase
);
2016 /* restore old wqm_cfg0 value */
2017 nes_write_indexed(nesdev
, NES_IDX_WQM_CONFIG0
, wqm_cfg0
);
2023 int nes_napi_isr(struct nes_device
*nesdev
)
2025 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2028 if (nesdev
->napi_isr_ran
) {
2029 /* interrupt status has already been read in ISR */
2030 int_stat
= nesdev
->int_stat
;
2032 int_stat
= nes_read32(nesdev
->regs
+ NES_INT_STAT
);
2033 nesdev
->int_stat
= int_stat
;
2034 nesdev
->napi_isr_ran
= 1;
2037 int_stat
&= nesdev
->int_req
;
2038 /* iff NIC, process here, else wait for DPC */
2039 if ((int_stat
) && ((int_stat
& 0x0000ff00) == int_stat
)) {
2040 nesdev
->napi_isr_ran
= 0;
2041 nes_write32(nesdev
->regs
+ NES_INT_STAT
,
2043 ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
| NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
)));
2045 /* Process the CEQs */
2046 nes_process_ceq(nesdev
, &nesdev
->nesadapter
->ceq
[nesdev
->nic_ceq_index
]);
2048 if (unlikely((((nesadapter
->et_rx_coalesce_usecs_irq
) &&
2049 (!nesadapter
->et_use_adaptive_rx_coalesce
)) ||
2050 ((nesadapter
->et_use_adaptive_rx_coalesce
) &&
2051 (nesdev
->deepcq_count
> nesadapter
->et_pkt_rate_low
))))) {
2052 if ((nesdev
->int_req
& NES_INT_TIMER
) == 0) {
2053 /* Enable Periodic timer interrupts */
2054 nesdev
->int_req
|= NES_INT_TIMER
;
2055 /* ack any pending periodic timer interrupts so we don't get an immediate interrupt */
2056 /* TODO: need to also ack other unused periodic timer values, get from nesadapter */
2057 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
2058 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
2059 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
,
2060 ~(nesdev
->intf_int_req
| NES_INTF_PERIODIC_TIMER
));
2063 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
2065 nes_nic_init_timer(nesdev
);
2067 /* Enable interrupts, except CEQs */
2068 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2070 /* Enable interrupts, make sure timer is off */
2071 nesdev
->int_req
&= ~NES_INT_TIMER
;
2072 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
2073 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
2075 nesdev
->deepcq_count
= 0;
2082 static void process_critical_error(struct nes_device
*nesdev
)
2085 u32 nes_idx_debug_error_masks0
= 0;
2086 u16 error_module
= 0;
2088 debug_error
= nes_read_indexed(nesdev
, NES_IDX_DEBUG_ERROR_CONTROL_STATUS
);
2089 printk(KERN_ERR PFX
"Critical Error reported by device!!! 0x%02X\n",
2091 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_CONTROL_STATUS
,
2092 0x01010000 | (debug_error
& 0x0000ffff));
2093 if (crit_err_count
++ > 10)
2094 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_MASKS1
, 1 << 0x17);
2095 error_module
= (u16
) (debug_error
& 0x1F00) >> 8;
2096 if (++nesdev
->nesadapter
->crit_error_count
[error_module
-1] >=
2097 nes_max_critical_error_count
) {
2098 printk(KERN_ERR PFX
"Masking off critical error for module "
2099 "0x%02X\n", (u16
)error_module
);
2100 nes_idx_debug_error_masks0
= nes_read_indexed(nesdev
,
2101 NES_IDX_DEBUG_ERROR_MASKS0
);
2102 nes_write_indexed(nesdev
, NES_IDX_DEBUG_ERROR_MASKS0
,
2103 nes_idx_debug_error_masks0
| (1 << error_module
));
2109 void nes_dpc(unsigned long param
)
2111 struct nes_device
*nesdev
= (struct nes_device
*)param
;
2112 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2114 u32 loop_counter
= 0;
2120 u32 processed_intf_int
= 0;
2121 u16 processed_timer_int
= 0;
2122 u16 completion_ints
= 0;
2125 /* nes_debug(NES_DBG_ISR, "\n"); */
2129 if (nesdev
->napi_isr_ran
) {
2130 nesdev
->napi_isr_ran
= 0;
2131 int_stat
= nesdev
->int_stat
;
2133 int_stat
= nes_read32(nesdev
->regs
+NES_INT_STAT
);
2134 if (processed_intf_int
!= 0)
2135 int_stat
&= nesdev
->int_req
& ~NES_INT_INTF
;
2137 int_stat
&= nesdev
->int_req
;
2138 if (processed_timer_int
== 0) {
2139 processed_timer_int
= 1;
2140 if (int_stat
& NES_INT_TIMER
) {
2141 timer_stat
= nes_read32(nesdev
->regs
+ NES_TIMER_STAT
);
2142 if ((timer_stat
& nesdev
->timer_int_req
) == 0) {
2143 int_stat
&= ~NES_INT_TIMER
;
2147 int_stat
&= ~NES_INT_TIMER
;
2151 if (int_stat
& ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2152 NES_INT_MAC1
|NES_INT_MAC2
| NES_INT_MAC3
)) {
2153 /* Ack the interrupts */
2154 nes_write32(nesdev
->regs
+NES_INT_STAT
,
2155 (int_stat
& ~(NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2156 NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
)));
2159 temp_int_stat
= int_stat
;
2160 for (counter
= 0, int_status_bit
= 1; counter
< 16; counter
++) {
2161 if (int_stat
& int_status_bit
) {
2162 nes_process_ceq(nesdev
, &nesadapter
->ceq
[counter
]);
2163 temp_int_stat
&= ~int_status_bit
;
2164 completion_ints
= 1;
2166 if (!(temp_int_stat
& 0x0000ffff))
2168 int_status_bit
<<= 1;
2171 /* Process the AEQ for this pci function */
2172 int_status_bit
= 1 << (16 + PCI_FUNC(nesdev
->pcidev
->devfn
));
2173 if (int_stat
& int_status_bit
) {
2174 nes_process_aeq(nesdev
, &nesadapter
->aeq
[PCI_FUNC(nesdev
->pcidev
->devfn
)]);
2177 /* Process the MAC interrupt for this pci function */
2178 int_status_bit
= 1 << (24 + nesdev
->mac_index
);
2179 if (int_stat
& int_status_bit
) {
2180 nes_process_mac_intr(nesdev
, nesdev
->mac_index
);
2183 if (int_stat
& NES_INT_TIMER
) {
2184 if (timer_stat
& nesdev
->timer_int_req
) {
2185 nes_write32(nesdev
->regs
+ NES_TIMER_STAT
,
2186 (timer_stat
& nesdev
->timer_int_req
) |
2187 ~(nesdev
->nesadapter
->timer_int_req
));
2192 if (int_stat
& NES_INT_INTF
) {
2193 processed_intf_int
= 1;
2194 intf_int_stat
= nes_read32(nesdev
->regs
+NES_INTF_INT_STAT
);
2195 intf_int_stat
&= nesdev
->intf_int_req
;
2196 if (NES_INTF_INT_CRITERR
& intf_int_stat
) {
2197 process_critical_error(nesdev
);
2199 if (NES_INTF_INT_PCIERR
& intf_int_stat
) {
2200 printk(KERN_ERR PFX
"PCI Error reported by device!!!\n");
2203 if (NES_INTF_INT_AEQ_OFLOW
& intf_int_stat
) {
2204 printk(KERN_ERR PFX
"AEQ Overflow reported by device!!!\n");
2207 nes_write32(nesdev
->regs
+NES_INTF_INT_STAT
, intf_int_stat
);
2210 if (int_stat
& NES_INT_TSW
) {
2213 /* Don't use the interface interrupt bit stay in loop */
2214 int_stat
&= ~NES_INT_INTF
| NES_INT_TIMER
| NES_INT_MAC0
|
2215 NES_INT_MAC1
| NES_INT_MAC2
| NES_INT_MAC3
;
2216 } while ((int_stat
!= 0) && (loop_counter
++ < MAX_DPC_ITERATIONS
));
2218 if (timer_ints
== 1) {
2219 if ((nesadapter
->et_rx_coalesce_usecs_irq
) || (nesadapter
->et_use_adaptive_rx_coalesce
)) {
2220 if (completion_ints
== 0) {
2221 nesdev
->timer_only_int_count
++;
2222 if (nesdev
->timer_only_int_count
>=nesadapter
->timer_int_limit
) {
2223 nesdev
->timer_only_int_count
= 0;
2224 nesdev
->int_req
&= ~NES_INT_TIMER
;
2225 nes_write32(nesdev
->regs
+ NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
2226 nes_write32(nesdev
->regs
+ NES_INT_MASK
, ~nesdev
->int_req
);
2228 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2231 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
2233 nes_nic_init_timer(nesdev
);
2235 nesdev
->timer_only_int_count
= 0;
2236 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2239 nesdev
->timer_only_int_count
= 0;
2240 nesdev
->int_req
&= ~NES_INT_TIMER
;
2241 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
, ~(nesdev
->intf_int_req
));
2242 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
2243 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
2244 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
2247 if ( (completion_ints
== 1) &&
2248 (((nesadapter
->et_rx_coalesce_usecs_irq
) &&
2249 (!nesadapter
->et_use_adaptive_rx_coalesce
)) ||
2250 ((nesdev
->deepcq_count
> nesadapter
->et_pkt_rate_low
) &&
2251 (nesadapter
->et_use_adaptive_rx_coalesce
) )) ) {
2252 /* nes_debug(NES_DBG_ISR, "Enabling periodic timer interrupt.\n" ); */
2253 nesdev
->timer_only_int_count
= 0;
2254 nesdev
->int_req
|= NES_INT_TIMER
;
2255 nes_write32(nesdev
->regs
+NES_TIMER_STAT
,
2256 nesdev
->timer_int_req
| ~(nesdev
->nesadapter
->timer_int_req
));
2257 nes_write32(nesdev
->regs
+NES_INTF_INT_MASK
,
2258 ~(nesdev
->intf_int_req
| NES_INTF_PERIODIC_TIMER
));
2259 nes_write32(nesdev
->regs
+NES_INT_MASK
, 0x0000ffff | (~nesdev
->int_req
));
2261 nes_write32(nesdev
->regs
+NES_INT_MASK
, ~nesdev
->int_req
);
2264 nesdev
->deepcq_count
= 0;
2271 static void nes_process_ceq(struct nes_device
*nesdev
, struct nes_hw_ceq
*ceq
)
2274 struct nes_hw_cq
*cq
;
2278 /* nes_debug(NES_DBG_CQ, "\n"); */
2279 head
= ceq
->ceq_head
;
2280 ceq_size
= ceq
->ceq_size
;
2283 if (le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
]) &
2285 u64temp
= (((u64
)(le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
]))) << 32) |
2286 ((u64
)(le32_to_cpu(ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_LOW_IDX
])));
2288 cq
= *((struct nes_hw_cq
**)&u64temp
);
2289 /* nes_debug(NES_DBG_CQ, "pCQ = %p\n", cq); */
2291 ceq
->ceq_vbase
[head
].ceqe_words
[NES_CEQE_CQ_CTX_HIGH_IDX
] = 0;
2293 /* call the event handler */
2294 cq
->ce_handler(nesdev
, cq
);
2296 if (++head
>= ceq_size
)
2304 ceq
->ceq_head
= head
;
2311 static void nes_process_aeq(struct nes_device
*nesdev
, struct nes_hw_aeq
*aeq
)
2318 struct nes_hw_aeqe
volatile *aeqe
;
2320 head
= aeq
->aeq_head
;
2321 aeq_size
= aeq
->aeq_size
;
2324 aeqe
= &aeq
->aeq_vbase
[head
];
2325 if ((le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]) & NES_AEQE_VALID
) == 0)
2327 aeqe_misc
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
2328 aeqe_cq_id
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]);
2329 if (aeqe_misc
& (NES_AEQE_QP
|NES_AEQE_CQ
)) {
2330 if (aeqe_cq_id
>= NES_FIRST_QPN
) {
2331 /* dealing with an accelerated QP related AE */
2333 * u64temp = (((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_HIGH_IDX]))) << 32) |
2334 * ((u64)(le32_to_cpu(aeqe->aeqe_words[NES_AEQE_COMP_CTXT_LOW_IDX])));
2336 nes_process_iwarp_aeqe(nesdev
, (struct nes_hw_aeqe
*)aeqe
);
2338 /* TODO: dealing with a CQP related AE */
2339 nes_debug(NES_DBG_AEQ
, "Processing CQP related AE, misc = 0x%04X\n",
2340 (u16
)(aeqe_misc
>> 16));
2344 aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
] = 0;
2346 if (++head
>= aeq_size
)
2349 nes_write32(nesdev
->regs
+ NES_AEQ_ALLOC
, 1 << 16);
2352 aeq
->aeq_head
= head
;
2355 static void nes_reset_link(struct nes_device
*nesdev
, u32 mac_index
)
2357 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2362 if (nesadapter
->hw_rev
== NE020_REV
) {
2367 reset_value
= nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
);
2369 if ((mac_index
== 0) || ((mac_index
== 1) && (nesadapter
->OneG_Mode
)))
2370 reset_value
|= 0x0000001d;
2372 reset_value
|= 0x0000002d;
2374 if (4 <= (nesadapter
->link_interrupt_count
[mac_index
] / ((u16
)NES_MAX_LINK_INTERRUPTS
))) {
2375 if ((!nesadapter
->OneG_Mode
) && (nesadapter
->port_count
== 2)) {
2376 nesadapter
->link_interrupt_count
[0] = 0;
2377 nesadapter
->link_interrupt_count
[1] = 0;
2378 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
2379 if (0x00000040 & u32temp
)
2380 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F088);
2382 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F0C8);
2384 reset_value
|= 0x0000003d;
2386 nesadapter
->link_interrupt_count
[mac_index
] = 0;
2389 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
2391 while (((nes_read32(nesdev
->regs
+NES_SOFTWARE_RESET
)
2392 & 0x00000040) != 0x00000040) && (i
++ < 5000));
2394 if (0x0000003d == (reset_value
& 0x0000003d)) {
2395 u32 pcs_control_status0
, pcs_control_status1
;
2397 for (i
= 0; i
< 10; i
++) {
2398 pcs_control_status0
= nes_read_indexed(nesdev
, NES_IDX_PHY_PCS_CONTROL_STATUS0
);
2399 pcs_control_status1
= nes_read_indexed(nesdev
, NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
2400 if (((0x0F000000 == (pcs_control_status0
& 0x0F000000))
2401 && (pcs_control_status0
& 0x00100000))
2402 || ((0x0F000000 == (pcs_control_status1
& 0x0F000000))
2403 && (pcs_control_status1
& 0x00100000)))
2409 u32temp
= nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
);
2410 if (0x00000040 & u32temp
)
2411 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F088);
2413 nes_write_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_CONTROL1
, 0x0000F0C8);
2415 nes_write32(nesdev
->regs
+NES_SOFTWARE_RESET
, reset_value
);
2417 while (((nes_read32(nesdev
->regs
+ NES_SOFTWARE_RESET
)
2418 & 0x00000040) != 0x00000040) && (i
++ < 5000));
2424 * nes_process_mac_intr
2426 static void nes_process_mac_intr(struct nes_device
*nesdev
, u32 mac_number
)
2428 unsigned long flags
;
2429 u32 pcs_control_status
;
2430 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2431 struct nes_vnic
*nesvnic
;
2433 u32 mac_index
= nesdev
->mac_index
;
2437 u32 pcs_val
= 0x0f0f0000;
2438 u32 pcs_mask
= 0x0f1f0000;
2441 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
2442 if (nesadapter
->mac_sw_state
[mac_number
] != NES_MAC_SW_IDLE
) {
2443 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2446 nesadapter
->mac_sw_state
[mac_number
] = NES_MAC_SW_INTERRUPT
;
2448 /* ack the MAC interrupt */
2449 mac_status
= nes_read_indexed(nesdev
, NES_IDX_MAC_INT_STATUS
+ (mac_index
* 0x200));
2450 /* Clear the interrupt */
2451 nes_write_indexed(nesdev
, NES_IDX_MAC_INT_STATUS
+ (mac_index
* 0x200), mac_status
);
2453 nes_debug(NES_DBG_PHY
, "MAC%u interrupt status = 0x%X.\n", mac_number
, mac_status
);
2455 if (mac_status
& (NES_MAC_INT_LINK_STAT_CHG
| NES_MAC_INT_XGMII_EXT
)) {
2456 nesdev
->link_status_interrupts
++;
2457 if (0 == (++nesadapter
->link_interrupt_count
[mac_index
] % ((u16
)NES_MAX_LINK_INTERRUPTS
)))
2458 nes_reset_link(nesdev
, mac_index
);
2460 /* read the PHY interrupt status register */
2461 if ((nesadapter
->OneG_Mode
) &&
2462 (nesadapter
->phy_type
[mac_index
] != NES_PHY_TYPE_PUMA_1G
)) {
2464 nes_read_1G_phy_reg(nesdev
, 0x1a,
2465 nesadapter
->phy_index
[mac_index
], &phy_data
);
2466 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x1a = 0x%X.\n",
2467 nesadapter
->phy_index
[mac_index
], phy_data
);
2468 } while (phy_data
&0x8000);
2472 nes_read_1G_phy_reg(nesdev
, 0x11,
2473 nesadapter
->phy_index
[mac_index
], &phy_data
);
2474 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x11 = 0x%X.\n",
2475 nesadapter
->phy_index
[mac_index
], phy_data
);
2476 if (temp_phy_data
== phy_data
)
2478 temp_phy_data
= phy_data
;
2481 nes_read_1G_phy_reg(nesdev
, 0x1e,
2482 nesadapter
->phy_index
[mac_index
], &phy_data
);
2483 nes_debug(NES_DBG_PHY
, "Phy%d data from register 0x1e = 0x%X.\n",
2484 nesadapter
->phy_index
[mac_index
], phy_data
);
2486 nes_read_1G_phy_reg(nesdev
, 1,
2487 nesadapter
->phy_index
[mac_index
], &phy_data
);
2488 nes_debug(NES_DBG_PHY
, "1G phy%u data from register 1 = 0x%X\n",
2489 nesadapter
->phy_index
[mac_index
], phy_data
);
2491 if (temp_phy_data
& 0x1000) {
2492 nes_debug(NES_DBG_PHY
, "The Link is up according to the PHY\n");
2495 nes_debug(NES_DBG_PHY
, "The Link is down according to the PHY\n");
2498 nes_debug(NES_DBG_PHY
, "Eth SERDES Common Status: 0=0x%08X, 1=0x%08X\n",
2499 nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
),
2500 nes_read_indexed(nesdev
, NES_IDX_ETH_SERDES_COMMON_STATUS0
+0x200));
2502 if (nesadapter
->phy_type
[mac_index
] == NES_PHY_TYPE_PUMA_1G
) {
2503 switch (mac_index
) {
2506 pcs_control_status
= nes_read_indexed(nesdev
,
2507 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ 0x200);
2510 pcs_control_status
= nes_read_indexed(nesdev
,
2511 NES_IDX_PHY_PCS_CONTROL_STATUS0
);
2515 pcs_control_status
= nes_read_indexed(nesdev
,
2516 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ ((mac_index
& 1) * 0x200));
2517 pcs_control_status
= nes_read_indexed(nesdev
,
2518 NES_IDX_PHY_PCS_CONTROL_STATUS0
+ ((mac_index
& 1) * 0x200));
2521 nes_debug(NES_DBG_PHY
, "PCS PHY Control/Status%u: 0x%08X\n",
2522 mac_index
, pcs_control_status
);
2523 if ((nesadapter
->OneG_Mode
) &&
2524 (nesadapter
->phy_type
[mac_index
] != NES_PHY_TYPE_PUMA_1G
)) {
2525 u32temp
= 0x01010000;
2526 if (nesadapter
->port_count
> 2) {
2527 u32temp
|= 0x02020000;
2529 if ((pcs_control_status
& u32temp
)!= u32temp
) {
2531 nes_debug(NES_DBG_PHY
, "PCS says the link is down\n");
2534 switch (nesadapter
->phy_type
[mac_index
]) {
2535 case NES_PHY_TYPE_ARGUS
:
2536 case NES_PHY_TYPE_SFP_D
:
2537 case NES_PHY_TYPE_KR
:
2538 /* clear the alarms */
2539 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0x0008);
2540 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc001);
2541 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc002);
2542 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc005);
2543 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 4, 0xc006);
2544 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9003);
2545 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9004);
2546 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9005);
2547 /* check link status */
2548 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9003);
2549 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2551 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2552 nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2553 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2554 phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2556 phy_data
= (!temp_phy_data
&& (phy_data
== 0x8000)) ? 0x4 : 0x0;
2558 nes_debug(NES_DBG_PHY
, "%s: Phy data = 0x%04X, link was %s.\n",
2559 __func__
, phy_data
, nesadapter
->mac_link_down
[mac_index
] ? "DOWN" : "UP");
2562 case NES_PHY_TYPE_PUMA_1G
:
2564 pcs_val
= pcs_mask
= 0x01010000;
2566 pcs_val
= pcs_mask
= 0x02020000;
2569 phy_data
= (pcs_val
== (pcs_control_status
& pcs_mask
)) ? 0x4 : 0x0;
2574 if (phy_data
& 0x0004) {
2575 if (wide_ppm_offset
&&
2576 (nesadapter
->phy_type
[mac_index
] == NES_PHY_TYPE_CX4
) &&
2577 (nesadapter
->hw_rev
!= NE020_REV
)) {
2578 cdr_ctrl
= nes_read_indexed(nesdev
,
2579 NES_IDX_ETH_SERDES_CDR_CONTROL0
+
2581 nes_write_indexed(nesdev
,
2582 NES_IDX_ETH_SERDES_CDR_CONTROL0
+
2584 cdr_ctrl
| 0x000F0000);
2586 nesadapter
->mac_link_down
[mac_index
] = 0;
2587 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2588 nes_debug(NES_DBG_PHY
, "The Link is UP!!. linkup was %d\n",
2590 if (nesvnic
->linkup
== 0) {
2591 printk(PFX
"The Link is now up for port %s, netdev %p.\n",
2592 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2593 if (netif_queue_stopped(nesvnic
->netdev
))
2594 netif_start_queue(nesvnic
->netdev
);
2595 nesvnic
->linkup
= 1;
2596 netif_carrier_on(nesvnic
->netdev
);
2598 spin_lock(&nesvnic
->port_ibevent_lock
);
2599 if (nesvnic
->of_device_registered
) {
2600 if (nesdev
->iw_status
== 0) {
2601 nesdev
->iw_status
= 1;
2602 nes_port_ibevent(nesvnic
);
2605 spin_unlock(&nesvnic
->port_ibevent_lock
);
2609 if (wide_ppm_offset
&&
2610 (nesadapter
->phy_type
[mac_index
] == NES_PHY_TYPE_CX4
) &&
2611 (nesadapter
->hw_rev
!= NE020_REV
)) {
2612 cdr_ctrl
= nes_read_indexed(nesdev
,
2613 NES_IDX_ETH_SERDES_CDR_CONTROL0
+
2615 nes_write_indexed(nesdev
,
2616 NES_IDX_ETH_SERDES_CDR_CONTROL0
+
2618 cdr_ctrl
& 0xFFF0FFFF);
2620 nesadapter
->mac_link_down
[mac_index
] = 1;
2621 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2622 nes_debug(NES_DBG_PHY
, "The Link is Down!!. linkup was %d\n",
2624 if (nesvnic
->linkup
== 1) {
2625 printk(PFX
"The Link is now down for port %s, netdev %p.\n",
2626 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2627 if (!(netif_queue_stopped(nesvnic
->netdev
)))
2628 netif_stop_queue(nesvnic
->netdev
);
2629 nesvnic
->linkup
= 0;
2630 netif_carrier_off(nesvnic
->netdev
);
2632 spin_lock(&nesvnic
->port_ibevent_lock
);
2633 if (nesvnic
->of_device_registered
) {
2634 if (nesdev
->iw_status
== 1) {
2635 nesdev
->iw_status
= 0;
2636 nes_port_ibevent(nesvnic
);
2639 spin_unlock(&nesvnic
->port_ibevent_lock
);
2643 if (nesadapter
->phy_type
[mac_index
] == NES_PHY_TYPE_SFP_D
) {
2644 nesdev
->link_recheck
= 1;
2645 mod_delayed_work(system_wq
, &nesdev
->work
,
2646 NES_LINK_RECHECK_DELAY
);
2650 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2652 nesadapter
->mac_sw_state
[mac_number
] = NES_MAC_SW_IDLE
;
2655 void nes_recheck_link_status(struct work_struct
*work
)
2657 unsigned long flags
;
2658 struct nes_device
*nesdev
= container_of(work
, struct nes_device
, work
.work
);
2659 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2660 struct nes_vnic
*nesvnic
;
2661 u32 mac_index
= nesdev
->mac_index
;
2665 spin_lock_irqsave(&nesadapter
->phy_lock
, flags
);
2667 /* check link status */
2668 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 1, 0x9003);
2669 temp_phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2671 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2672 nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2673 nes_read_10G_phy_reg(nesdev
, nesadapter
->phy_index
[mac_index
], 3, 0x0021);
2674 phy_data
= (u16
)nes_read_indexed(nesdev
, NES_IDX_MAC_MDIO_CONTROL
);
2676 phy_data
= (!temp_phy_data
&& (phy_data
== 0x8000)) ? 0x4 : 0x0;
2678 nes_debug(NES_DBG_PHY
, "%s: Phy data = 0x%04X, link was %s.\n",
2680 nesadapter
->mac_link_down
[mac_index
] ? "DOWN" : "UP");
2682 if (phy_data
& 0x0004) {
2683 nesadapter
->mac_link_down
[mac_index
] = 0;
2684 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2685 if (nesvnic
->linkup
== 0) {
2686 printk(PFX
"The Link is now up for port %s, netdev %p.\n",
2687 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2688 if (netif_queue_stopped(nesvnic
->netdev
))
2689 netif_start_queue(nesvnic
->netdev
);
2690 nesvnic
->linkup
= 1;
2691 netif_carrier_on(nesvnic
->netdev
);
2693 spin_lock(&nesvnic
->port_ibevent_lock
);
2694 if (nesvnic
->of_device_registered
) {
2695 if (nesdev
->iw_status
== 0) {
2696 nesdev
->iw_status
= 1;
2697 nes_port_ibevent(nesvnic
);
2700 spin_unlock(&nesvnic
->port_ibevent_lock
);
2705 nesadapter
->mac_link_down
[mac_index
] = 1;
2706 list_for_each_entry(nesvnic
, &nesadapter
->nesvnic_list
[mac_index
], list
) {
2707 if (nesvnic
->linkup
== 1) {
2708 printk(PFX
"The Link is now down for port %s, netdev %p.\n",
2709 nesvnic
->netdev
->name
, nesvnic
->netdev
);
2710 if (!(netif_queue_stopped(nesvnic
->netdev
)))
2711 netif_stop_queue(nesvnic
->netdev
);
2712 nesvnic
->linkup
= 0;
2713 netif_carrier_off(nesvnic
->netdev
);
2715 spin_lock(&nesvnic
->port_ibevent_lock
);
2716 if (nesvnic
->of_device_registered
) {
2717 if (nesdev
->iw_status
== 1) {
2718 nesdev
->iw_status
= 0;
2719 nes_port_ibevent(nesvnic
);
2722 spin_unlock(&nesvnic
->port_ibevent_lock
);
2726 if (nesdev
->link_recheck
++ < NES_LINK_RECHECK_MAX
)
2727 schedule_delayed_work(&nesdev
->work
, NES_LINK_RECHECK_DELAY
);
2729 nesdev
->link_recheck
= 0;
2731 spin_unlock_irqrestore(&nesadapter
->phy_lock
, flags
);
2735 static void nes_nic_napi_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
)
2737 struct nes_vnic
*nesvnic
= container_of(cq
, struct nes_vnic
, nic_cq
);
2739 napi_schedule(&nesvnic
->napi
);
2743 /* The MAX_RQES_TO_PROCESS defines how many max read requests to complete before
2744 * getting out of nic_ce_handler
2746 #define MAX_RQES_TO_PROCESS 384
2749 * nes_nic_ce_handler
2751 void nes_nic_ce_handler(struct nes_device
*nesdev
, struct nes_hw_nic_cq
*cq
)
2754 dma_addr_t bus_address
;
2755 struct nes_hw_nic
*nesnic
;
2756 struct nes_vnic
*nesvnic
= container_of(cq
, struct nes_vnic
, nic_cq
);
2757 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
2758 struct nes_hw_nic_rq_wqe
*nic_rqe
;
2759 struct nes_hw_nic_sq_wqe
*nic_sqe
;
2760 struct sk_buff
*skb
;
2761 struct sk_buff
*rx_skb
;
2762 struct nes_rskb_cb
*cb
;
2763 __le16
*wqe_fragment_length
;
2770 u16 wqe_fragment_index
= 1; /* first fragment (0) is used by copy buffer */
2773 u16 rqes_processed
= 0;
2777 cq_size
= cq
->cq_size
;
2778 cq
->cqes_pending
= 1;
2780 if (le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
]) &
2781 NES_NIC_CQE_VALID
) {
2782 nesnic
= &nesvnic
->nic
;
2783 cqe_misc
= le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
]);
2784 if (cqe_misc
& NES_NIC_CQE_SQ
) {
2786 wqe_fragment_index
= 1;
2787 nic_sqe
= &nesnic
->sq_vbase
[nesnic
->sq_tail
];
2788 skb
= nesnic
->tx_skb
[nesnic
->sq_tail
];
2789 wqe_fragment_length
= (__le16
*)&nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_LENGTH_0_TAG_IDX
];
2790 /* bump past the vlan tag */
2791 wqe_fragment_length
++;
2792 if (le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]) != 0) {
2793 u64temp
= (u64
) le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
2794 wqe_fragment_index
* 2]);
2795 u64temp
+= ((u64
)le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
+
2796 wqe_fragment_index
* 2])) << 32;
2797 bus_address
= (dma_addr_t
)u64temp
;
2798 if (test_and_clear_bit(nesnic
->sq_tail
, nesnic
->first_frag_overflow
)) {
2799 pci_unmap_single(nesdev
->pcidev
,
2801 le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
++]),
2804 for (; wqe_fragment_index
< 5; wqe_fragment_index
++) {
2805 if (wqe_fragment_length
[wqe_fragment_index
]) {
2806 u64temp
= le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_LOW_IDX
+
2807 wqe_fragment_index
* 2]);
2808 u64temp
+= ((u64
)le32_to_cpu(nic_sqe
->wqe_words
[NES_NIC_SQ_WQE_FRAG0_HIGH_IDX
2809 + wqe_fragment_index
* 2])) <<32;
2810 bus_address
= (dma_addr_t
)u64temp
;
2811 pci_unmap_page(nesdev
->pcidev
,
2813 le16_to_cpu(wqe_fragment_length
[wqe_fragment_index
]),
2820 dev_kfree_skb_any(skb
);
2822 nesnic
->sq_tail
&= nesnic
->sq_size
-1;
2823 if (sq_cqes
> 128) {
2825 /* restart the queue if it had been stopped */
2826 if (netif_queue_stopped(nesvnic
->netdev
))
2827 netif_wake_queue(nesvnic
->netdev
);
2833 cq
->rx_cqes_completed
++;
2834 cq
->rx_pkts_indicated
++;
2835 rx_pkt_size
= cqe_misc
& 0x0000ffff;
2836 nic_rqe
= &nesnic
->rq_vbase
[nesnic
->rq_tail
];
2838 rx_skb
= nesnic
->rx_skb
[nesnic
->rq_tail
];
2839 nic_rqe
= &nesnic
->rq_vbase
[nesvnic
->nic
.rq_tail
];
2840 bus_address
= (dma_addr_t
)le32_to_cpu(nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_LOW_IDX
]);
2841 bus_address
+= ((u64
)le32_to_cpu(nic_rqe
->wqe_words
[NES_NIC_RQ_WQE_FRAG0_HIGH_IDX
])) << 32;
2842 pci_unmap_single(nesdev
->pcidev
, bus_address
,
2843 nesvnic
->max_frame_size
, PCI_DMA_FROMDEVICE
);
2844 cb
= (struct nes_rskb_cb
*)&rx_skb
->cb
[0];
2846 /* rx_skb->tail = rx_skb->data + rx_pkt_size; */
2847 /* rx_skb->len = rx_pkt_size; */
2848 rx_skb
->len
= 0; /* TODO: see if this is necessary */
2849 skb_put(rx_skb
, rx_pkt_size
);
2850 rx_skb
->protocol
= eth_type_trans(rx_skb
, nesvnic
->netdev
);
2852 nesnic
->rq_tail
&= nesnic
->rq_size
- 1;
2854 atomic_inc(&nesvnic
->rx_skbs_needed
);
2855 if (atomic_read(&nesvnic
->rx_skbs_needed
) > (nesvnic
->nic
.rq_size
>>1)) {
2856 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
,
2857 cq
->cq_number
| (cqe_count
<< 16));
2858 /* nesadapter->tune_timer.cq_count += cqe_count; */
2859 nesdev
->currcq_count
+= cqe_count
;
2861 nes_replenish_nic_rq(nesvnic
);
2863 pkt_type
= (u16
)(le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_TAG_PKT_TYPE_IDX
]));
2864 cqe_errv
= (cqe_misc
& NES_NIC_CQE_ERRV_MASK
) >> NES_NIC_CQE_ERRV_SHIFT
;
2865 rx_skb
->ip_summed
= CHECKSUM_NONE
;
2867 if ((NES_PKT_TYPE_TCPV4_BITS
== (pkt_type
& NES_PKT_TYPE_TCPV4_MASK
)) ||
2868 (NES_PKT_TYPE_UDPV4_BITS
== (pkt_type
& NES_PKT_TYPE_UDPV4_MASK
))) {
2870 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR
| NES_NIC_ERRV_BITS_TCPUDP_CSUM_ERR
|
2871 NES_NIC_ERRV_BITS_IPH_ERR
| NES_NIC_ERRV_BITS_WQE_OVERRUN
)) == 0) {
2872 if (nesvnic
->netdev
->features
& NETIF_F_RXCSUM
)
2873 rx_skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2875 nes_debug(NES_DBG_CQ
, "%s: unsuccessfully checksummed TCP or UDP packet."
2876 " errv = 0x%X, pkt_type = 0x%X.\n",
2877 nesvnic
->netdev
->name
, cqe_errv
, pkt_type
);
2879 } else if ((pkt_type
& NES_PKT_TYPE_IPV4_MASK
) == NES_PKT_TYPE_IPV4_BITS
) {
2881 (NES_NIC_ERRV_BITS_IPV4_CSUM_ERR
| NES_NIC_ERRV_BITS_IPH_ERR
|
2882 NES_NIC_ERRV_BITS_WQE_OVERRUN
)) == 0) {
2883 if (nesvnic
->netdev
->features
& NETIF_F_RXCSUM
) {
2884 rx_skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
2885 /* nes_debug(NES_DBG_CQ, "%s: Reporting successfully checksummed IPv4 packet.\n",
2886 nesvnic->netdev->name); */
2889 nes_debug(NES_DBG_CQ
, "%s: unsuccessfully checksummed TCP or UDP packet."
2890 " errv = 0x%X, pkt_type = 0x%X.\n",
2891 nesvnic
->netdev
->name
, cqe_errv
, pkt_type
);
2893 /* nes_debug(NES_DBG_CQ, "pkt_type=%x, APBVT_MASK=%x\n",
2894 pkt_type, (pkt_type & NES_PKT_TYPE_APBVT_MASK)); */
2896 if ((pkt_type
& NES_PKT_TYPE_APBVT_MASK
) == NES_PKT_TYPE_APBVT_BITS
) {
2897 if (nes_cm_recv(rx_skb
, nesvnic
->netdev
))
2901 goto skip_rx_indicate0
;
2904 if (cqe_misc
& NES_NIC_CQE_TAG_VALID
) {
2905 vlan_tag
= (u16
)(le32_to_cpu(
2906 cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_TAG_PKT_TYPE_IDX
])
2908 nes_debug(NES_DBG_CQ
, "%s: Reporting stripped VLAN packet. Tag = 0x%04X\n",
2909 nesvnic
->netdev
->name
, vlan_tag
);
2911 __vlan_hwaccel_put_tag(rx_skb
, htons(ETH_P_8021Q
), vlan_tag
);
2913 napi_gro_receive(&nesvnic
->napi
, rx_skb
);
2917 /* nesvnic->netstats.rx_packets++; */
2918 /* nesvnic->netstats.rx_bytes += rx_pkt_size; */
2921 cq
->cq_vbase
[head
].cqe_words
[NES_NIC_CQE_MISC_IDX
] = 0;
2924 if (++head
>= cq_size
)
2926 if (cqe_count
== 255) {
2927 /* Replenish Nic CQ */
2928 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
,
2929 cq
->cq_number
| (cqe_count
<< 16));
2930 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2931 nesdev
->currcq_count
+= cqe_count
;
2935 if (cq
->rx_cqes_completed
>= nesvnic
->budget
)
2938 cq
->cqes_pending
= 0;
2946 /* restart the queue if it had been stopped */
2947 if (netif_queue_stopped(nesvnic
->netdev
))
2948 netif_wake_queue(nesvnic
->netdev
);
2951 /* nes_debug(NES_DBG_CQ, "CQ%u Processed = %u cqes, new head = %u.\n",
2952 cq->cq_number, cqe_count, cq->cq_head); */
2953 cq
->cqe_allocs_pending
= cqe_count
;
2954 if (unlikely(nesadapter
->et_use_adaptive_rx_coalesce
))
2956 /* nesdev->nesadapter->tune_timer.cq_count += cqe_count; */
2957 nesdev
->currcq_count
+= cqe_count
;
2958 nes_nic_tune_timer(nesdev
);
2960 if (atomic_read(&nesvnic
->rx_skbs_needed
))
2961 nes_replenish_nic_rq(nesvnic
);
2967 * nes_cqp_ce_handler
2969 static void nes_cqp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*cq
)
2972 unsigned long flags
;
2973 struct nes_hw_cqp
*cqp
= NULL
;
2974 struct nes_cqp_request
*cqp_request
;
2975 struct nes_hw_cqp_wqe
*cqp_wqe
;
2985 cq_size
= cq
->cq_size
;
2988 /* process the CQE */
2989 /* nes_debug(NES_DBG_CQP, "head=%u cqe_words=%08X\n", head,
2990 le32_to_cpu(cq->cq_vbase[head].cqe_words[NES_CQE_OPCODE_IDX])); */
2992 opcode
= le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
]);
2993 if (opcode
& NES_CQE_VALID
) {
2996 error_code
= le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_ERROR_CODE_IDX
]);
2998 nes_debug(NES_DBG_CQP
, "Bad Completion code for opcode 0x%02X from CQP,"
2999 " Major/Minor codes = 0x%04X:%04X.\n",
3000 le32_to_cpu(cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
])&0x3f,
3001 (u16
)(error_code
>> 16),
3005 u64temp
= (((u64
)(le32_to_cpu(cq
->cq_vbase
[head
].
3006 cqe_words
[NES_CQE_COMP_COMP_CTX_HIGH_IDX
]))) << 32) |
3007 ((u64
)(le32_to_cpu(cq
->cq_vbase
[head
].
3008 cqe_words
[NES_CQE_COMP_COMP_CTX_LOW_IDX
])));
3010 cqp_request
= (struct nes_cqp_request
*)(unsigned long)u64temp
;
3012 if (cqp_request
->waiting
) {
3013 /* nes_debug(NES_DBG_CQP, "%s: Waking up requestor\n"); */
3014 cqp_request
->major_code
= (u16
)(error_code
>> 16);
3015 cqp_request
->minor_code
= (u16
)error_code
;
3017 cqp_request
->request_done
= 1;
3018 wake_up(&cqp_request
->waitq
);
3019 nes_put_cqp_request(nesdev
, cqp_request
);
3021 if (cqp_request
->callback
)
3022 cqp_request
->cqp_callback(nesdev
, cqp_request
);
3023 nes_free_cqp_request(nesdev
, cqp_request
);
3026 wake_up(&nesdev
->cqp
.waitq
);
3029 cq
->cq_vbase
[head
].cqe_words
[NES_CQE_OPCODE_IDX
] = 0;
3030 nes_write32(nesdev
->regs
+ NES_CQE_ALLOC
, cq
->cq_number
| (1 << 16));
3031 if (++cqp
->sq_tail
>= cqp
->sq_size
)
3036 if (++head
>= cq_size
)
3044 spin_lock_irqsave(&nesdev
->cqp
.lock
, flags
);
3045 while ((!list_empty(&nesdev
->cqp_pending_reqs
)) &&
3046 ((((nesdev
->cqp
.sq_tail
+nesdev
->cqp
.sq_size
)-nesdev
->cqp
.sq_head
) &
3047 (nesdev
->cqp
.sq_size
- 1)) != 1)) {
3048 cqp_request
= list_entry(nesdev
->cqp_pending_reqs
.next
,
3049 struct nes_cqp_request
, list
);
3050 list_del_init(&cqp_request
->list
);
3051 head
= nesdev
->cqp
.sq_head
++;
3052 nesdev
->cqp
.sq_head
&= nesdev
->cqp
.sq_size
-1;
3053 cqp_wqe
= &nesdev
->cqp
.sq_vbase
[head
];
3054 memcpy(cqp_wqe
, &cqp_request
->cqp_wqe
, sizeof(*cqp_wqe
));
3057 opcode
= le32_to_cpu(cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
]);
3058 if ((opcode
& NES_CQP_OPCODE_MASK
) == NES_CQP_DOWNLOAD_SEGMENT
)
3059 ctx_index
= NES_CQP_WQE_DL_COMP_CTX_LOW_IDX
;
3061 ctx_index
= NES_CQP_WQE_COMP_CTX_LOW_IDX
;
3062 cqp_wqe
->wqe_words
[ctx_index
] =
3063 cpu_to_le32((u32
)((unsigned long)cqp_request
));
3064 cqp_wqe
->wqe_words
[ctx_index
+ 1] =
3065 cpu_to_le32((u32
)(upper_32_bits((unsigned long)cqp_request
)));
3066 nes_debug(NES_DBG_CQP
, "CQP request %p (opcode 0x%02X) put on CQPs SQ wqe%u.\n",
3067 cqp_request
, le32_to_cpu(cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
])&0x3f, head
);
3068 /* Ring doorbell (1 WQEs) */
3070 nes_write32(nesdev
->regs
+NES_WQE_ALLOC
, 0x01800000 | nesdev
->cqp
.qp_id
);
3072 spin_unlock_irqrestore(&nesdev
->cqp
.lock
, flags
);
3075 nes_write32(nesdev
->regs
+NES_CQE_ALLOC
, NES_CQE_ALLOC_NOTIFY_NEXT
|
3077 nes_read32(nesdev
->regs
+NES_CQE_ALLOC
);
3080 static u8
*locate_mpa(u8
*pkt
, u32 aeq_info
)
3082 if (aeq_info
& NES_AEQE_Q2_DATA_ETHERNET
) {
3083 /* skip over ethernet header */
3086 /* Skip over IP and TCP headers */
3087 pkt
+= 4 * (pkt
[0] & 0x0f);
3088 pkt
+= 4 * ((pkt
[12] >> 4) & 0x0f);
3093 /* Determine if incoming error pkt is rdma layer */
3094 static u32
iwarp_opcode(struct nes_qp
*nesqp
, u32 aeq_info
)
3098 u32 opcode
= 0xffffffff;
3100 if (aeq_info
& NES_AEQE_Q2_DATA_WRITTEN
) {
3101 pkt
= nesqp
->hwqp
.q2_vbase
+ BAD_FRAME_OFFSET
;
3102 mpa
= (u16
*)locate_mpa(pkt
, aeq_info
);
3103 opcode
= be16_to_cpu(mpa
[1]) & 0xf;
3109 /* Build iWARP terminate header */
3110 static int nes_bld_terminate_hdr(struct nes_qp
*nesqp
, u16 async_event_id
, u32 aeq_info
)
3112 u8
*pkt
= nesqp
->hwqp
.q2_vbase
+ BAD_FRAME_OFFSET
;
3117 struct nes_terminate_hdr
*termhdr
;
3119 termhdr
= (struct nes_terminate_hdr
*)nesqp
->hwqp
.q2_vbase
;
3120 memset(termhdr
, 0, 64);
3122 if (aeq_info
& NES_AEQE_Q2_DATA_WRITTEN
) {
3124 /* Use data from offending packet to fill in ddp & rdma hdrs */
3125 pkt
= locate_mpa(pkt
, aeq_info
);
3126 ddp_seg_len
= be16_to_cpu(*(u16
*)pkt
);
3129 termhdr
->hdrct
= DDP_LEN_FLAG
;
3130 if (pkt
[2] & 0x80) {
3132 if (ddp_seg_len
>= TERM_DDP_LEN_TAGGED
) {
3133 copy_len
+= TERM_DDP_LEN_TAGGED
;
3134 termhdr
->hdrct
|= DDP_HDR_FLAG
;
3137 if (ddp_seg_len
>= TERM_DDP_LEN_UNTAGGED
) {
3138 copy_len
+= TERM_DDP_LEN_UNTAGGED
;
3139 termhdr
->hdrct
|= DDP_HDR_FLAG
;
3142 if (ddp_seg_len
>= (TERM_DDP_LEN_UNTAGGED
+ TERM_RDMA_LEN
)) {
3143 if ((pkt
[3] & RDMA_OPCODE_MASK
) == RDMA_READ_REQ_OPCODE
) {
3144 copy_len
+= TERM_RDMA_LEN
;
3145 termhdr
->hdrct
|= RDMA_HDR_FLAG
;
3152 switch (async_event_id
) {
3153 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG
:
3154 switch (iwarp_opcode(nesqp
, aeq_info
)) {
3155 case IWARP_OPCODE_WRITE
:
3156 flush_code
= IB_WC_LOC_PROT_ERR
;
3157 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_TAGGED_BUFFER
;
3158 termhdr
->error_code
= DDP_TAGGED_INV_STAG
;
3161 flush_code
= IB_WC_REM_ACCESS_ERR
;
3162 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3163 termhdr
->error_code
= RDMAP_INV_STAG
;
3166 case NES_AEQE_AEID_AMP_INVALID_STAG
:
3167 flush_code
= IB_WC_REM_ACCESS_ERR
;
3168 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3169 termhdr
->error_code
= RDMAP_INV_STAG
;
3171 case NES_AEQE_AEID_AMP_BAD_QP
:
3172 flush_code
= IB_WC_LOC_QP_OP_ERR
;
3173 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3174 termhdr
->error_code
= DDP_UNTAGGED_INV_QN
;
3176 case NES_AEQE_AEID_AMP_BAD_STAG_KEY
:
3177 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX
:
3178 switch (iwarp_opcode(nesqp
, aeq_info
)) {
3179 case IWARP_OPCODE_SEND_INV
:
3180 case IWARP_OPCODE_SEND_SE_INV
:
3181 flush_code
= IB_WC_REM_OP_ERR
;
3182 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_OP
;
3183 termhdr
->error_code
= RDMAP_CANT_INV_STAG
;
3186 flush_code
= IB_WC_REM_ACCESS_ERR
;
3187 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3188 termhdr
->error_code
= RDMAP_INV_STAG
;
3191 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION
:
3192 if (aeq_info
& (NES_AEQE_Q2_DATA_ETHERNET
| NES_AEQE_Q2_DATA_MPA
)) {
3193 flush_code
= IB_WC_LOC_PROT_ERR
;
3194 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_TAGGED_BUFFER
;
3195 termhdr
->error_code
= DDP_TAGGED_BOUNDS
;
3197 flush_code
= IB_WC_REM_ACCESS_ERR
;
3198 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3199 termhdr
->error_code
= RDMAP_INV_BOUNDS
;
3202 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION
:
3203 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS
:
3204 case NES_AEQE_AEID_PRIV_OPERATION_DENIED
:
3205 flush_code
= IB_WC_REM_ACCESS_ERR
;
3206 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3207 termhdr
->error_code
= RDMAP_ACCESS
;
3209 case NES_AEQE_AEID_AMP_TO_WRAP
:
3210 flush_code
= IB_WC_REM_ACCESS_ERR
;
3211 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3212 termhdr
->error_code
= RDMAP_TO_WRAP
;
3214 case NES_AEQE_AEID_AMP_BAD_PD
:
3215 switch (iwarp_opcode(nesqp
, aeq_info
)) {
3216 case IWARP_OPCODE_WRITE
:
3217 flush_code
= IB_WC_LOC_PROT_ERR
;
3218 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_TAGGED_BUFFER
;
3219 termhdr
->error_code
= DDP_TAGGED_UNASSOC_STAG
;
3221 case IWARP_OPCODE_SEND_INV
:
3222 case IWARP_OPCODE_SEND_SE_INV
:
3223 flush_code
= IB_WC_REM_ACCESS_ERR
;
3224 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3225 termhdr
->error_code
= RDMAP_CANT_INV_STAG
;
3228 flush_code
= IB_WC_REM_ACCESS_ERR
;
3229 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_PROT
;
3230 termhdr
->error_code
= RDMAP_UNASSOC_STAG
;
3233 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH
:
3234 flush_code
= IB_WC_LOC_LEN_ERR
;
3235 termhdr
->layer_etype
= (LAYER_MPA
<< 4) | DDP_LLP
;
3236 termhdr
->error_code
= MPA_MARKER
;
3238 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR
:
3239 flush_code
= IB_WC_GENERAL_ERR
;
3240 termhdr
->layer_etype
= (LAYER_MPA
<< 4) | DDP_LLP
;
3241 termhdr
->error_code
= MPA_CRC
;
3243 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE
:
3244 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL
:
3245 flush_code
= IB_WC_LOC_LEN_ERR
;
3246 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_CATASTROPHIC
;
3247 termhdr
->error_code
= DDP_CATASTROPHIC_LOCAL
;
3249 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC
:
3250 case NES_AEQE_AEID_DDP_NO_L_BIT
:
3251 flush_code
= IB_WC_FATAL_ERR
;
3252 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_CATASTROPHIC
;
3253 termhdr
->error_code
= DDP_CATASTROPHIC_LOCAL
;
3255 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN
:
3256 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID
:
3257 flush_code
= IB_WC_GENERAL_ERR
;
3258 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3259 termhdr
->error_code
= DDP_UNTAGGED_INV_MSN_RANGE
;
3261 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER
:
3262 flush_code
= IB_WC_LOC_LEN_ERR
;
3263 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3264 termhdr
->error_code
= DDP_UNTAGGED_INV_TOO_LONG
;
3266 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION
:
3267 flush_code
= IB_WC_GENERAL_ERR
;
3269 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_TAGGED_BUFFER
;
3270 termhdr
->error_code
= DDP_TAGGED_INV_DDP_VER
;
3272 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3273 termhdr
->error_code
= DDP_UNTAGGED_INV_DDP_VER
;
3276 case NES_AEQE_AEID_DDP_UBE_INVALID_MO
:
3277 flush_code
= IB_WC_GENERAL_ERR
;
3278 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3279 termhdr
->error_code
= DDP_UNTAGGED_INV_MO
;
3281 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE
:
3282 flush_code
= IB_WC_REM_OP_ERR
;
3283 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3284 termhdr
->error_code
= DDP_UNTAGGED_INV_MSN_NO_BUF
;
3286 case NES_AEQE_AEID_DDP_UBE_INVALID_QN
:
3287 flush_code
= IB_WC_GENERAL_ERR
;
3288 termhdr
->layer_etype
= (LAYER_DDP
<< 4) | DDP_UNTAGGED_BUFFER
;
3289 termhdr
->error_code
= DDP_UNTAGGED_INV_QN
;
3291 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION
:
3292 flush_code
= IB_WC_GENERAL_ERR
;
3293 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_OP
;
3294 termhdr
->error_code
= RDMAP_INV_RDMAP_VER
;
3296 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE
:
3297 flush_code
= IB_WC_LOC_QP_OP_ERR
;
3298 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_OP
;
3299 termhdr
->error_code
= RDMAP_UNEXPECTED_OP
;
3302 flush_code
= IB_WC_FATAL_ERR
;
3303 termhdr
->layer_etype
= (LAYER_RDMA
<< 4) | RDMAP_REMOTE_OP
;
3304 termhdr
->error_code
= RDMAP_UNSPECIFIED
;
3309 memcpy(termhdr
+ 1, pkt
, copy_len
);
3311 if ((flush_code
) && ((NES_AEQE_INBOUND_RDMA
& aeq_info
) == 0)) {
3312 if (aeq_info
& NES_AEQE_SQ
)
3313 nesqp
->term_sq_flush_code
= flush_code
;
3315 nesqp
->term_rq_flush_code
= flush_code
;
3318 return sizeof(struct nes_terminate_hdr
) + copy_len
;
3321 static void nes_terminate_connection(struct nes_device
*nesdev
, struct nes_qp
*nesqp
,
3322 struct nes_hw_aeqe
*aeqe
, enum ib_event_type eventtype
)
3325 unsigned long flags
;
3331 u32 mod_qp_flags
= NES_CQP_QP_IWARP_STATE_TERMINATE
|
3332 NES_CQP_QP_TERM_DONT_SEND_FIN
;
3333 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
3335 if (nesqp
->term_flags
& NES_TERM_SENT
)
3336 return; /* Sanity check */
3338 aeq_info
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
3339 tcp_state
= (aeq_info
& NES_AEQE_TCP_STATE_MASK
) >> NES_AEQE_TCP_STATE_SHIFT
;
3340 iwarp_state
= (aeq_info
& NES_AEQE_IWARP_STATE_MASK
) >> NES_AEQE_IWARP_STATE_SHIFT
;
3341 async_event_id
= (u16
)aeq_info
;
3343 context
= (unsigned long)nesadapter
->qp_table
[le32_to_cpu(
3344 aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]) - NES_FIRST_QPN
];
3350 nesqp
= (struct nes_qp
*)(unsigned long)context
;
3351 spin_lock_irqsave(&nesqp
->lock
, flags
);
3352 nesqp
->hw_iwarp_state
= iwarp_state
;
3353 nesqp
->hw_tcp_state
= tcp_state
;
3354 nesqp
->last_aeq
= async_event_id
;
3355 nesqp
->terminate_eventtype
= eventtype
;
3356 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3358 if (nesadapter
->send_term_ok
)
3359 termlen
= nes_bld_terminate_hdr(nesqp
, async_event_id
, aeq_info
);
3361 mod_qp_flags
|= NES_CQP_QP_TERM_DONT_SEND_TERM_MSG
;
3363 if (!nesdev
->iw_status
) {
3364 nesqp
->term_flags
= NES_TERM_DONE
;
3365 nes_hw_modify_qp(nesdev
, nesqp
, NES_CQP_QP_IWARP_STATE_ERROR
, 0, 0);
3366 nes_cm_disconn(nesqp
);
3368 nes_terminate_start_timer(nesqp
);
3369 nesqp
->term_flags
|= NES_TERM_SENT
;
3370 nes_hw_modify_qp(nesdev
, nesqp
, mod_qp_flags
, termlen
, 0);
3374 static void nes_terminate_send_fin(struct nes_device
*nesdev
,
3375 struct nes_qp
*nesqp
, struct nes_hw_aeqe
*aeqe
)
3381 unsigned long flags
;
3383 aeq_info
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
3384 tcp_state
= (aeq_info
& NES_AEQE_TCP_STATE_MASK
) >> NES_AEQE_TCP_STATE_SHIFT
;
3385 iwarp_state
= (aeq_info
& NES_AEQE_IWARP_STATE_MASK
) >> NES_AEQE_IWARP_STATE_SHIFT
;
3386 async_event_id
= (u16
)aeq_info
;
3388 spin_lock_irqsave(&nesqp
->lock
, flags
);
3389 nesqp
->hw_iwarp_state
= iwarp_state
;
3390 nesqp
->hw_tcp_state
= tcp_state
;
3391 nesqp
->last_aeq
= async_event_id
;
3392 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3394 /* Send the fin only */
3395 nes_hw_modify_qp(nesdev
, nesqp
, NES_CQP_QP_IWARP_STATE_TERMINATE
|
3396 NES_CQP_QP_TERM_DONT_SEND_TERM_MSG
, 0, 0);
3399 /* Cleanup after a terminate sent or received */
3400 static void nes_terminate_done(struct nes_qp
*nesqp
, int timeout_occurred
)
3402 u32 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_ERROR
;
3403 unsigned long flags
;
3404 struct nes_vnic
*nesvnic
= to_nesvnic(nesqp
->ibqp
.device
);
3405 struct nes_device
*nesdev
= nesvnic
->nesdev
;
3408 spin_lock_irqsave(&nesqp
->lock
, flags
);
3409 if (nesqp
->hte_added
) {
3410 nesqp
->hte_added
= 0;
3411 next_iwarp_state
|= NES_CQP_QP_DEL_HTE
;
3414 first_time
= (nesqp
->term_flags
& NES_TERM_DONE
) == 0;
3415 nesqp
->term_flags
|= NES_TERM_DONE
;
3416 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3418 /* Make sure we go through this only once */
3420 if (timeout_occurred
== 0)
3421 del_timer(&nesqp
->terminate_timer
);
3423 next_iwarp_state
|= NES_CQP_QP_RESET
;
3425 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0, 0);
3426 nes_cm_disconn(nesqp
);
3430 static void nes_terminate_received(struct nes_device
*nesdev
,
3431 struct nes_qp
*nesqp
, struct nes_hw_aeqe
*aeqe
)
3440 aeq_info
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
3441 if (aeq_info
& NES_AEQE_Q2_DATA_WRITTEN
) {
3442 /* Terminate is not a performance path so the silicon */
3443 /* did not validate the frame - do it now */
3444 pkt
= nesqp
->hwqp
.q2_vbase
+ BAD_FRAME_OFFSET
;
3445 mpa
= (u32
*)locate_mpa(pkt
, aeq_info
);
3446 ddp_ctl
= (be32_to_cpu(mpa
[0]) >> 8) & 0xff;
3447 rdma_ctl
= be32_to_cpu(mpa
[0]) & 0xff;
3448 if ((ddp_ctl
& 0xc0) != 0x40)
3449 aeq_id
= NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC
;
3450 else if ((ddp_ctl
& 0x03) != 1)
3451 aeq_id
= NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION
;
3452 else if (be32_to_cpu(mpa
[2]) != 2)
3453 aeq_id
= NES_AEQE_AEID_DDP_UBE_INVALID_QN
;
3454 else if (be32_to_cpu(mpa
[3]) != 1)
3455 aeq_id
= NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN
;
3456 else if (be32_to_cpu(mpa
[4]) != 0)
3457 aeq_id
= NES_AEQE_AEID_DDP_UBE_INVALID_MO
;
3458 else if ((rdma_ctl
& 0xc0) != 0x40)
3459 aeq_id
= NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION
;
3462 /* Bad terminate recvd - send back a terminate */
3463 aeq_info
= (aeq_info
& 0xffff0000) | aeq_id
;
3464 aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
] = cpu_to_le32(aeq_info
);
3465 nes_terminate_connection(nesdev
, nesqp
, aeqe
, IB_EVENT_QP_FATAL
);
3470 nesqp
->term_flags
|= NES_TERM_RCVD
;
3471 nesqp
->terminate_eventtype
= IB_EVENT_QP_FATAL
;
3472 nes_terminate_start_timer(nesqp
);
3473 nes_terminate_send_fin(nesdev
, nesqp
, aeqe
);
3476 /* Timeout routine in case terminate fails to complete */
3477 void nes_terminate_timeout(unsigned long context
)
3479 struct nes_qp
*nesqp
= (struct nes_qp
*)(unsigned long)context
;
3481 nes_terminate_done(nesqp
, 1);
3484 /* Set a timer in case hw cannot complete the terminate sequence */
3485 static void nes_terminate_start_timer(struct nes_qp
*nesqp
)
3487 mod_timer(&nesqp
->terminate_timer
, (jiffies
+ HZ
));
3491 * nes_process_iwarp_aeqe
3493 static void nes_process_iwarp_aeqe(struct nes_device
*nesdev
,
3494 struct nes_hw_aeqe
*aeqe
)
3497 unsigned long flags
;
3498 struct nes_qp
*nesqp
;
3499 struct nes_hw_cq
*hw_cq
;
3500 struct nes_cq
*nescq
;
3501 int resource_allocated
;
3502 struct nes_adapter
*nesadapter
= nesdev
->nesadapter
;
3504 u32 next_iwarp_state
= 0;
3509 struct ib_event ibevent
;
3511 nes_debug(NES_DBG_AEQ
, "\n");
3512 aeq_info
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
]);
3513 if ((NES_AEQE_INBOUND_RDMA
& aeq_info
) || (!(NES_AEQE_QP
& aeq_info
))) {
3514 context
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_LOW_IDX
]);
3515 context
+= ((u64
)le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_CTXT_HIGH_IDX
])) << 32;
3517 context
= (unsigned long)nesadapter
->qp_table
[le32_to_cpu(
3518 aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]) - NES_FIRST_QPN
];
3522 /* context is nesqp unless async_event_id == CQ ERROR */
3523 nesqp
= (struct nes_qp
*)(unsigned long)context
;
3524 async_event_id
= (u16
)aeq_info
;
3525 tcp_state
= (aeq_info
& NES_AEQE_TCP_STATE_MASK
) >> NES_AEQE_TCP_STATE_SHIFT
;
3526 iwarp_state
= (aeq_info
& NES_AEQE_IWARP_STATE_MASK
) >> NES_AEQE_IWARP_STATE_SHIFT
;
3527 nes_debug(NES_DBG_AEQ
, "aeid = 0x%04X, qp-cq id = %d, aeqe = %p,"
3528 " Tcp state = %s, iWARP state = %s\n",
3530 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]), aeqe
,
3531 nes_tcp_state_str
[tcp_state
], nes_iwarp_state_str
[iwarp_state
]);
3533 aeqe_cq_id
= le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]);
3534 if (aeq_info
& NES_AEQE_QP
) {
3535 if (!nes_is_resource_allocated(nesadapter
,
3536 nesadapter
->allocated_qps
,
3541 switch (async_event_id
) {
3542 case NES_AEQE_AEID_LLP_FIN_RECEIVED
:
3543 if (nesqp
->term_flags
)
3544 return; /* Ignore it, wait for close complete */
3546 if (atomic_inc_return(&nesqp
->close_timer_started
) == 1) {
3547 if ((tcp_state
== NES_AEQE_TCP_STATE_CLOSE_WAIT
) &&
3548 (nesqp
->ibqp_state
== IB_QPS_RTS
)) {
3549 spin_lock_irqsave(&nesqp
->lock
, flags
);
3550 nesqp
->hw_iwarp_state
= iwarp_state
;
3551 nesqp
->hw_tcp_state
= tcp_state
;
3552 nesqp
->last_aeq
= async_event_id
;
3553 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_CLOSING
;
3554 nesqp
->hw_iwarp_state
= NES_AEQE_IWARP_STATE_CLOSING
;
3555 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3556 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0, 0);
3557 nes_cm_disconn(nesqp
);
3559 nesqp
->cm_id
->add_ref(nesqp
->cm_id
);
3560 schedule_nes_timer(nesqp
->cm_node
, (struct sk_buff
*)nesqp
,
3561 NES_TIMER_TYPE_CLOSE
, 1, 0);
3562 nes_debug(NES_DBG_AEQ
, "QP%u Not decrementing QP refcount (%d),"
3563 " need ae to finish up, original_last_aeq = 0x%04X."
3564 " last_aeq = 0x%04X, scheduling timer. TCP state = %d\n",
3565 nesqp
->hwqp
.qp_id
, atomic_read(&nesqp
->refcount
),
3566 async_event_id
, nesqp
->last_aeq
, tcp_state
);
3569 case NES_AEQE_AEID_LLP_CLOSE_COMPLETE
:
3570 spin_lock_irqsave(&nesqp
->lock
, flags
);
3571 nesqp
->hw_iwarp_state
= iwarp_state
;
3572 nesqp
->hw_tcp_state
= tcp_state
;
3573 nesqp
->last_aeq
= async_event_id
;
3574 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3575 nes_cm_disconn(nesqp
);
3578 case NES_AEQE_AEID_RESET_SENT
:
3579 tcp_state
= NES_AEQE_TCP_STATE_CLOSED
;
3580 spin_lock_irqsave(&nesqp
->lock
, flags
);
3581 nesqp
->hw_iwarp_state
= iwarp_state
;
3582 nesqp
->hw_tcp_state
= tcp_state
;
3583 nesqp
->last_aeq
= async_event_id
;
3584 nesqp
->hte_added
= 0;
3585 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3586 next_iwarp_state
= NES_CQP_QP_IWARP_STATE_ERROR
| NES_CQP_QP_DEL_HTE
;
3587 nes_hw_modify_qp(nesdev
, nesqp
, next_iwarp_state
, 0, 0);
3588 nes_cm_disconn(nesqp
);
3591 case NES_AEQE_AEID_LLP_CONNECTION_RESET
:
3592 if (atomic_read(&nesqp
->close_timer_started
))
3594 spin_lock_irqsave(&nesqp
->lock
, flags
);
3595 nesqp
->hw_iwarp_state
= iwarp_state
;
3596 nesqp
->hw_tcp_state
= tcp_state
;
3597 nesqp
->last_aeq
= async_event_id
;
3598 spin_unlock_irqrestore(&nesqp
->lock
, flags
);
3599 nes_cm_disconn(nesqp
);
3602 case NES_AEQE_AEID_TERMINATE_SENT
:
3603 nes_terminate_send_fin(nesdev
, nesqp
, aeqe
);
3606 case NES_AEQE_AEID_LLP_TERMINATE_RECEIVED
:
3607 nes_terminate_received(nesdev
, nesqp
, aeqe
);
3610 case NES_AEQE_AEID_AMP_BAD_STAG_KEY
:
3611 case NES_AEQE_AEID_AMP_BAD_STAG_INDEX
:
3612 case NES_AEQE_AEID_AMP_UNALLOCATED_STAG
:
3613 case NES_AEQE_AEID_AMP_INVALID_STAG
:
3614 case NES_AEQE_AEID_AMP_RIGHTS_VIOLATION
:
3615 case NES_AEQE_AEID_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS
:
3616 case NES_AEQE_AEID_PRIV_OPERATION_DENIED
:
3617 case NES_AEQE_AEID_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER
:
3618 case NES_AEQE_AEID_AMP_BOUNDS_VIOLATION
:
3619 case NES_AEQE_AEID_AMP_TO_WRAP
:
3620 printk(KERN_ERR PFX
"QP[%u] async_event_id=0x%04X IB_EVENT_QP_ACCESS_ERR\n",
3621 nesqp
->hwqp
.qp_id
, async_event_id
);
3622 nes_terminate_connection(nesdev
, nesqp
, aeqe
, IB_EVENT_QP_ACCESS_ERR
);
3625 case NES_AEQE_AEID_LLP_SEGMENT_TOO_LARGE
:
3626 case NES_AEQE_AEID_LLP_SEGMENT_TOO_SMALL
:
3627 case NES_AEQE_AEID_DDP_UBE_INVALID_MO
:
3628 case NES_AEQE_AEID_DDP_UBE_INVALID_QN
:
3629 if (iwarp_opcode(nesqp
, aeq_info
) > IWARP_OPCODE_TERM
) {
3630 aeq_info
&= 0xffff0000;
3631 aeq_info
|= NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE
;
3632 aeqe
->aeqe_words
[NES_AEQE_MISC_IDX
] = cpu_to_le32(aeq_info
);
3635 case NES_AEQE_AEID_RDMAP_ROE_BAD_LLP_CLOSE
:
3636 case NES_AEQE_AEID_LLP_TOO_MANY_RETRIES
:
3637 case NES_AEQE_AEID_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE
:
3638 case NES_AEQE_AEID_LLP_RECEIVED_MPA_CRC_ERROR
:
3639 case NES_AEQE_AEID_AMP_BAD_QP
:
3640 case NES_AEQE_AEID_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH
:
3641 case NES_AEQE_AEID_DDP_LCE_LOCAL_CATASTROPHIC
:
3642 case NES_AEQE_AEID_DDP_NO_L_BIT
:
3643 case NES_AEQE_AEID_DDP_INVALID_MSN_GAP_IN_MSN
:
3644 case NES_AEQE_AEID_DDP_INVALID_MSN_RANGE_IS_NOT_VALID
:
3645 case NES_AEQE_AEID_DDP_UBE_INVALID_DDP_VERSION
:
3646 case NES_AEQE_AEID_RDMAP_ROE_INVALID_RDMAP_VERSION
:
3647 case NES_AEQE_AEID_RDMAP_ROE_UNEXPECTED_OPCODE
:
3648 case NES_AEQE_AEID_AMP_BAD_PD
:
3649 case NES_AEQE_AEID_AMP_FASTREG_SHARED
:
3650 case NES_AEQE_AEID_AMP_FASTREG_VALID_STAG
:
3651 case NES_AEQE_AEID_AMP_FASTREG_MW_STAG
:
3652 case NES_AEQE_AEID_AMP_FASTREG_INVALID_RIGHTS
:
3653 case NES_AEQE_AEID_AMP_FASTREG_PBL_TABLE_OVERFLOW
:
3654 case NES_AEQE_AEID_AMP_FASTREG_INVALID_LENGTH
:
3655 case NES_AEQE_AEID_AMP_INVALIDATE_SHARED
:
3656 case NES_AEQE_AEID_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS
:
3657 case NES_AEQE_AEID_AMP_MWBIND_VALID_STAG
:
3658 case NES_AEQE_AEID_AMP_MWBIND_OF_MR_STAG
:
3659 case NES_AEQE_AEID_AMP_MWBIND_TO_ZERO_BASED_STAG
:
3660 case NES_AEQE_AEID_AMP_MWBIND_TO_MW_STAG
:
3661 case NES_AEQE_AEID_AMP_MWBIND_INVALID_RIGHTS
:
3662 case NES_AEQE_AEID_AMP_MWBIND_INVALID_BOUNDS
:
3663 case NES_AEQE_AEID_AMP_MWBIND_TO_INVALID_PARENT
:
3664 case NES_AEQE_AEID_AMP_MWBIND_BIND_DISABLED
:
3665 case NES_AEQE_AEID_BAD_CLOSE
:
3666 case NES_AEQE_AEID_RDMA_READ_WHILE_ORD_ZERO
:
3667 case NES_AEQE_AEID_STAG_ZERO_INVALID
:
3668 case NES_AEQE_AEID_ROE_INVALID_RDMA_READ_REQUEST
:
3669 case NES_AEQE_AEID_ROE_INVALID_RDMA_WRITE_OR_READ_RESP
:
3670 printk(KERN_ERR PFX
"QP[%u] async_event_id=0x%04X IB_EVENT_QP_FATAL\n",
3671 nesqp
->hwqp
.qp_id
, async_event_id
);
3672 print_ip(nesqp
->cm_node
);
3673 if (!atomic_read(&nesqp
->close_timer_started
))
3674 nes_terminate_connection(nesdev
, nesqp
, aeqe
, IB_EVENT_QP_FATAL
);
3677 case NES_AEQE_AEID_CQ_OPERATION_ERROR
:
3679 nes_debug(NES_DBG_AEQ
, "Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u, %p\n",
3680 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]), (void *)(unsigned long)context
);
3681 resource_allocated
= nes_is_resource_allocated(nesadapter
, nesadapter
->allocated_cqs
,
3682 le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]));
3683 if (resource_allocated
) {
3684 printk(KERN_ERR PFX
"%s: Processing an NES_AEQE_AEID_CQ_OPERATION_ERROR event on CQ%u\n",
3685 __func__
, le32_to_cpu(aeqe
->aeqe_words
[NES_AEQE_COMP_QP_CQ_ID_IDX
]));
3686 hw_cq
= (struct nes_hw_cq
*)(unsigned long)context
;
3688 nescq
= container_of(hw_cq
, struct nes_cq
, hw_cq
);
3689 if (nescq
->ibcq
.event_handler
) {
3690 ibevent
.device
= nescq
->ibcq
.device
;
3691 ibevent
.event
= IB_EVENT_CQ_ERR
;
3692 ibevent
.element
.cq
= &nescq
->ibcq
;
3693 nescq
->ibcq
.event_handler(&ibevent
, nescq
->ibcq
.cq_context
);
3700 nes_debug(NES_DBG_AEQ
, "Processing an iWARP related AE for QP, misc = 0x%04X\n",
3708 * nes_iwarp_ce_handler
3710 void nes_iwarp_ce_handler(struct nes_device
*nesdev
, struct nes_hw_cq
*hw_cq
)
3712 struct nes_cq
*nescq
= container_of(hw_cq
, struct nes_cq
, hw_cq
);
3714 /* nes_debug(NES_DBG_CQ, "Processing completion event for iWARP CQ%u.\n",
3715 nescq->hw_cq.cq_number); */
3716 nes_write32(nesdev
->regs
+NES_CQ_ACK
, nescq
->hw_cq
.cq_number
);
3718 if (nescq
->ibcq
.comp_handler
)
3719 nescq
->ibcq
.comp_handler(&nescq
->ibcq
, nescq
->ibcq
.cq_context
);
3726 * nes_manage_apbvt()
3728 int nes_manage_apbvt(struct nes_vnic
*nesvnic
, u32 accel_local_port
,
3729 u32 nic_index
, u32 add_port
)
3731 struct nes_device
*nesdev
= nesvnic
->nesdev
;
3732 struct nes_hw_cqp_wqe
*cqp_wqe
;
3733 struct nes_cqp_request
*cqp_request
;
3737 /* Send manage APBVT request to CQP */
3738 cqp_request
= nes_get_cqp_request(nesdev
);
3739 if (cqp_request
== NULL
) {
3740 nes_debug(NES_DBG_QP
, "Failed to get a cqp_request.\n");
3743 cqp_request
->waiting
= 1;
3744 cqp_wqe
= &cqp_request
->cqp_wqe
;
3746 nes_debug(NES_DBG_QP
, "%s APBV for local port=%u(0x%04x), nic_index=%u\n",
3747 (add_port
== NES_MANAGE_APBVT_ADD
) ? "ADD" : "DEL",
3748 accel_local_port
, accel_local_port
, nic_index
);
3750 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3751 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_OPCODE_IDX
, (NES_CQP_MANAGE_APBVT
|
3752 ((add_port
== NES_MANAGE_APBVT_ADD
) ? NES_CQP_APBVT_ADD
: 0)));
3753 set_wqe_32bit_value(cqp_wqe
->wqe_words
, NES_CQP_WQE_ID_IDX
,
3754 ((nic_index
<< NES_CQP_APBVT_NIC_SHIFT
) | accel_local_port
));
3756 nes_debug(NES_DBG_QP
, "Waiting for CQP completion for APBVT.\n");
3758 atomic_set(&cqp_request
->refcount
, 2);
3759 nes_post_cqp_request(nesdev
, cqp_request
);
3761 if (add_port
== NES_MANAGE_APBVT_ADD
)
3762 ret
= wait_event_timeout(cqp_request
->waitq
, (cqp_request
->request_done
!= 0),
3764 nes_debug(NES_DBG_QP
, "Completed, ret=%u, CQP Major:Minor codes = 0x%04X:0x%04X\n",
3765 ret
, cqp_request
->major_code
, cqp_request
->minor_code
);
3766 major_code
= cqp_request
->major_code
;
3768 nes_put_cqp_request(nesdev
, cqp_request
);
3772 else if (major_code
)
3780 * nes_manage_arp_cache
3782 void nes_manage_arp_cache(struct net_device
*netdev
, unsigned char *mac_addr
,
3783 u32 ip_addr
, u32 action
)
3785 struct nes_hw_cqp_wqe
*cqp_wqe
;
3786 struct nes_vnic
*nesvnic
= netdev_priv(netdev
);
3787 struct nes_device
*nesdev
;
3788 struct nes_cqp_request
*cqp_request
;
3791 nesdev
= nesvnic
->nesdev
;
3792 arp_index
= nes_arp_table(nesdev
, ip_addr
, mac_addr
, action
);
3793 if (arp_index
== -1) {
3797 /* update the ARP entry */
3798 cqp_request
= nes_get_cqp_request(nesdev
);
3799 if (cqp_request
== NULL
) {
3800 nes_debug(NES_DBG_NETDEV
, "Failed to get a cqp_request.\n");
3803 cqp_request
->waiting
= 0;
3804 cqp_wqe
= &cqp_request
->cqp_wqe
;
3805 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3807 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] = cpu_to_le32(
3808 NES_CQP_MANAGE_ARP_CACHE
| NES_CQP_ARP_PERM
);
3809 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] |= cpu_to_le32(
3810 (u32
)PCI_FUNC(nesdev
->pcidev
->devfn
) << NES_CQP_ARP_AEQ_INDEX_SHIFT
);
3811 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(arp_index
);
3813 if (action
== NES_ARP_ADD
) {
3814 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] |= cpu_to_le32(NES_CQP_ARP_VALID
);
3815 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX
] = cpu_to_le32(
3816 (((u32
)mac_addr
[2]) << 24) | (((u32
)mac_addr
[3]) << 16) |
3817 (((u32
)mac_addr
[4]) << 8) | (u32
)mac_addr
[5]);
3818 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_HIGH_IDX
] = cpu_to_le32(
3819 (((u32
)mac_addr
[0]) << 8) | (u32
)mac_addr
[1]);
3821 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_ADDR_LOW_IDX
] = 0;
3822 cqp_wqe
->wqe_words
[NES_CQP_ARP_WQE_MAC_HIGH_IDX
] = 0;
3825 nes_debug(NES_DBG_NETDEV
, "Not waiting for CQP, cqp.sq_head=%u, cqp.sq_tail=%u\n",
3826 nesdev
->cqp
.sq_head
, nesdev
->cqp
.sq_tail
);
3828 atomic_set(&cqp_request
->refcount
, 1);
3829 nes_post_cqp_request(nesdev
, cqp_request
);
3836 void flush_wqes(struct nes_device
*nesdev
, struct nes_qp
*nesqp
,
3837 u32 which_wq
, u32 wait_completion
)
3839 struct nes_cqp_request
*cqp_request
;
3840 struct nes_hw_cqp_wqe
*cqp_wqe
;
3841 u32 sq_code
= (NES_IWARP_CQE_MAJOR_FLUSH
<< 16) | NES_IWARP_CQE_MINOR_FLUSH
;
3842 u32 rq_code
= (NES_IWARP_CQE_MAJOR_FLUSH
<< 16) | NES_IWARP_CQE_MINOR_FLUSH
;
3845 cqp_request
= nes_get_cqp_request(nesdev
);
3846 if (cqp_request
== NULL
) {
3847 nes_debug(NES_DBG_QP
, "Failed to get a cqp_request.\n");
3850 if (wait_completion
) {
3851 cqp_request
->waiting
= 1;
3852 atomic_set(&cqp_request
->refcount
, 2);
3854 cqp_request
->waiting
= 0;
3856 cqp_wqe
= &cqp_request
->cqp_wqe
;
3857 nes_fill_init_cqp_wqe(cqp_wqe
, nesdev
);
3859 /* If wqe in error was identified, set code to be put into cqe */
3860 if ((nesqp
->term_sq_flush_code
) && (which_wq
& NES_CQP_FLUSH_SQ
)) {
3861 which_wq
|= NES_CQP_FLUSH_MAJ_MIN
;
3862 sq_code
= (CQE_MAJOR_DRV
<< 16) | nesqp
->term_sq_flush_code
;
3863 nesqp
->term_sq_flush_code
= 0;
3866 if ((nesqp
->term_rq_flush_code
) && (which_wq
& NES_CQP_FLUSH_RQ
)) {
3867 which_wq
|= NES_CQP_FLUSH_MAJ_MIN
;
3868 rq_code
= (CQE_MAJOR_DRV
<< 16) | nesqp
->term_rq_flush_code
;
3869 nesqp
->term_rq_flush_code
= 0;
3872 if (which_wq
& NES_CQP_FLUSH_MAJ_MIN
) {
3873 cqp_wqe
->wqe_words
[NES_CQP_QP_WQE_FLUSH_SQ_CODE
] = cpu_to_le32(sq_code
);
3874 cqp_wqe
->wqe_words
[NES_CQP_QP_WQE_FLUSH_RQ_CODE
] = cpu_to_le32(rq_code
);
3877 cqp_wqe
->wqe_words
[NES_CQP_WQE_OPCODE_IDX
] =
3878 cpu_to_le32(NES_CQP_FLUSH_WQES
| which_wq
);
3879 cqp_wqe
->wqe_words
[NES_CQP_WQE_ID_IDX
] = cpu_to_le32(nesqp
->hwqp
.qp_id
);
3881 nes_post_cqp_request(nesdev
, cqp_request
);
3883 if (wait_completion
) {
3885 ret
= wait_event_timeout(cqp_request
->waitq
, (cqp_request
->request_done
!= 0),
3887 nes_debug(NES_DBG_QP
, "Flush SQ QP WQEs completed, ret=%u,"
3888 " CQP Major:Minor codes = 0x%04X:0x%04X\n",
3889 ret
, cqp_request
->major_code
, cqp_request
->minor_code
);
3890 nes_put_cqp_request(nesdev
, cqp_request
);