1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 * Contact Information:
36 * linux-drivers@emulex.com
40 * Costa Mesa, CA 92626
46 #include <linux/mutex.h>
47 #include <linux/list.h>
48 #include <linux/spinlock.h>
49 #include <linux/pci.h>
51 #include <rdma/ib_verbs.h>
52 #include <rdma/ib_user_verbs.h>
53 #include <rdma/ib_addr.h>
56 #include "ocrdma_sli.h"
58 #define OCRDMA_ROCE_DRV_VERSION "10.6.0.0"
60 #define OCRDMA_ROCE_DRV_DESC "Emulex OneConnect RoCE Driver"
61 #define OCRDMA_NODE_DESC "Emulex OneConnect RoCE HCA"
63 #define OC_NAME_SH OCRDMA_NODE_DESC "(Skyhawk)"
64 #define OC_NAME_UNKNOWN OCRDMA_NODE_DESC "(Unknown)"
66 #define OC_SKH_DEVICE_PF 0x720
67 #define OC_SKH_DEVICE_VF 0x728
68 #define OCRDMA_MAX_AH 512
70 #define OCRDMA_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
72 #define convert_to_64bit(lo, hi) ((u64)hi << 32 | (u64)lo)
73 #define EQ_INTR_PER_SEC_THRSH_HI 150000
74 #define EQ_INTR_PER_SEC_THRSH_LOW 100000
75 #define EQ_AIC_MAX_EQD 20
76 #define EQ_AIC_MIN_EQD 0
78 void ocrdma_eqd_set_task(struct work_struct
*work
);
80 struct ocrdma_dev_attr
{
103 int max_pages_per_frmr
;
107 int device_cap_flags
;
108 u8 cq_overflow_detect
;
114 u8 local_ca_ack_delay
;
119 struct ocrdma_dma_mem
{
130 struct ocrdma_queue_info
{
135 u16 entry_size
; /* Size of an element in the queue */
136 u16 id
; /* qid, where to ring the doorbell. */
141 struct ocrdma_aic_obj
{ /* Adaptive interrupt coalescing (AIC) info */
144 u64 prev_eq_intr_cnt
;
148 struct ocrdma_queue_info q
;
151 struct ocrdma_dev
*dev
;
153 struct ocrdma_aic_obj aic_obj
;
157 struct ocrdma_queue_info sq
;
158 struct ocrdma_queue_info cq
;
163 struct mutex lock
; /* for serializing mailbox commands on MQ */
164 wait_queue_head_t cmd_wait
;
172 struct ocrdma_hw_mr
{
183 struct ocrdma_pbl
*pbl_table
;
194 struct ib_umem
*umem
;
195 struct ocrdma_hw_mr hwmr
;
198 struct ocrdma_stats
{
200 struct ocrdma_dev
*dev
;
203 struct ocrdma_pd_resource_mgr
{
213 unsigned long *pd_norm_bitmap
;
214 unsigned long *pd_dpp_bitmap
;
215 bool pd_prealloc_valid
;
219 struct ocrdma_mqe mqe
;
227 u16 auto_speeds_supported
;
228 u16 fixed_speeds_supported
;
234 struct ib_device ibdev
;
235 struct ocrdma_dev_attr attr
;
237 struct mutex dev_lock
; /* provides syncronise access to device data */
238 spinlock_t flush_q_lock ____cacheline_aligned
;
240 struct ocrdma_cq
**cq_tbl
;
241 struct ocrdma_qp
**qp_tbl
;
243 struct ocrdma_eq
*eq_tbl
;
245 struct delayed_work eqd_work
;
249 union ib_gid
*sgid_tbl
;
250 /* provided synchronization to sgid table for
251 * updating gid entries triggered by notifier.
253 spinlock_t sgid_lock
;
256 struct ocrdma_cq
*gsi_sqcq
;
257 struct ocrdma_cq
*gsi_rqcq
;
260 struct ocrdma_av
*va
;
264 /* provide synchronization for av
269 struct ocrdma_pbl pbl
;
274 struct mqe_ctx mqe_ctx
;
276 struct be_dev_info nic_info
;
278 char model_number
[32];
281 struct list_head entry
;
285 u8 sl
; /* service level */
291 ulong last_stats_time
;
292 struct mutex stats_lock
; /* provide synch for debugfs operations */
293 struct stats_mem stats_mem
;
294 struct ocrdma_stats rsrc_stats
;
295 struct ocrdma_stats rx_stats
;
296 struct ocrdma_stats wqe_stats
;
297 struct ocrdma_stats tx_stats
;
298 struct ocrdma_stats db_err_stats
;
299 struct ocrdma_stats tx_qp_err_stats
;
300 struct ocrdma_stats rx_qp_err_stats
;
301 struct ocrdma_stats tx_dbg_stats
;
302 struct ocrdma_stats rx_dbg_stats
;
303 struct ocrdma_stats driver_stats
;
304 struct ocrdma_stats reset_stats
;
306 atomic_t async_err_stats
[OCRDMA_MAX_ASYNC_ERRORS
];
307 atomic_t cqe_err_stats
[OCRDMA_MAX_CQE_ERR
];
308 struct ocrdma_pd_resource_mgr
*pd_mgr
;
313 struct ocrdma_cqe
*va
;
315 u32 getp
; /* pointer to pending wrs to
316 * return to stack, wrap arounds
321 bool deferred_arm
, deferred_sol
;
324 spinlock_t cq_lock ____cacheline_aligned
; /* provide synchronization
327 /* syncronizes cq completion handler invoked from multiple context */
328 spinlock_t comp_handler_lock ____cacheline_aligned
;
332 struct ocrdma_ucontext
*ucontext
;
337 /* head of all qp's sq and rq for which cqes need to be flushed
340 struct list_head sq_head
, rq_head
;
345 struct ocrdma_ucontext
*uctx
;
354 struct ocrdma_av
*av
;
359 struct ocrdma_qp_hwq_info
{
360 u8
*va
; /* virtual address */
366 u16 dbid
; /* qid, where to ring the doorbell. */
374 struct ocrdma_qp_hwq_info rq
;
379 /* provide synchronization to multiple context(s) posting rqe */
380 spinlock_t q_lock ____cacheline_aligned
;
382 struct ocrdma_pd
*pd
;
390 struct ocrdma_qp_hwq_info sq
;
393 uint16_t dpp_wqe_idx
;
400 /* provide synchronization to multiple context(s) posting wqe, rqe */
401 spinlock_t q_lock ____cacheline_aligned
;
402 struct ocrdma_cq
*sq_cq
;
403 /* list maintained per CQ to flush SQ errors */
404 struct list_head sq_entry
;
407 struct ocrdma_qp_hwq_info rq
;
409 struct ocrdma_cq
*rq_cq
;
410 struct ocrdma_srq
*srq
;
411 /* list maintained per CQ to flush RQ errors */
412 struct list_head rq_entry
;
414 enum ocrdma_qp_state state
; /* QP state */
416 u32 max_ord
, max_ird
;
419 struct ocrdma_pd
*pd
;
421 enum ib_qp_type qp_type
;
430 struct ocrdma_ucontext
{
431 struct ib_ucontext ibucontext
;
433 struct list_head mm_head
;
434 struct mutex mm_list_lock
; /* protects list entries of mm type */
435 struct ocrdma_pd
*cntxt_pd
;
450 struct list_head entry
;
453 static inline struct ocrdma_dev
*get_ocrdma_dev(struct ib_device
*ibdev
)
455 return container_of(ibdev
, struct ocrdma_dev
, ibdev
);
458 static inline struct ocrdma_ucontext
*get_ocrdma_ucontext(struct ib_ucontext
461 return container_of(ibucontext
, struct ocrdma_ucontext
, ibucontext
);
464 static inline struct ocrdma_pd
*get_ocrdma_pd(struct ib_pd
*ibpd
)
466 return container_of(ibpd
, struct ocrdma_pd
, ibpd
);
469 static inline struct ocrdma_cq
*get_ocrdma_cq(struct ib_cq
*ibcq
)
471 return container_of(ibcq
, struct ocrdma_cq
, ibcq
);
474 static inline struct ocrdma_qp
*get_ocrdma_qp(struct ib_qp
*ibqp
)
476 return container_of(ibqp
, struct ocrdma_qp
, ibqp
);
479 static inline struct ocrdma_mr
*get_ocrdma_mr(struct ib_mr
*ibmr
)
481 return container_of(ibmr
, struct ocrdma_mr
, ibmr
);
484 static inline struct ocrdma_ah
*get_ocrdma_ah(struct ib_ah
*ibah
)
486 return container_of(ibah
, struct ocrdma_ah
, ibah
);
489 static inline struct ocrdma_srq
*get_ocrdma_srq(struct ib_srq
*ibsrq
)
491 return container_of(ibsrq
, struct ocrdma_srq
, ibsrq
);
494 static inline int is_cqe_valid(struct ocrdma_cq
*cq
, struct ocrdma_cqe
*cqe
)
497 cqe_valid
= le32_to_cpu(cqe
->flags_status_srcqpn
) & OCRDMA_CQE_VALID
;
498 return (cqe_valid
== cq
->phase
);
501 static inline int is_cqe_for_sq(struct ocrdma_cqe
*cqe
)
503 return (le32_to_cpu(cqe
->flags_status_srcqpn
) &
504 OCRDMA_CQE_QTYPE
) ? 0 : 1;
507 static inline int is_cqe_invalidated(struct ocrdma_cqe
*cqe
)
509 return (le32_to_cpu(cqe
->flags_status_srcqpn
) &
510 OCRDMA_CQE_INVALIDATE
) ? 1 : 0;
513 static inline int is_cqe_imm(struct ocrdma_cqe
*cqe
)
515 return (le32_to_cpu(cqe
->flags_status_srcqpn
) &
516 OCRDMA_CQE_IMM
) ? 1 : 0;
519 static inline int is_cqe_wr_imm(struct ocrdma_cqe
*cqe
)
521 return (le32_to_cpu(cqe
->flags_status_srcqpn
) &
522 OCRDMA_CQE_WRITE_IMM
) ? 1 : 0;
525 static inline int ocrdma_resolve_dmac(struct ocrdma_dev
*dev
,
526 struct ib_ah_attr
*ah_attr
, u8
*mac_addr
)
530 memcpy(&in6
, ah_attr
->grh
.dgid
.raw
, sizeof(in6
));
531 if (rdma_is_multicast_addr(&in6
))
532 rdma_get_mcast_mac(&in6
, mac_addr
);
533 else if (rdma_link_local_addr(&in6
))
534 rdma_get_ll_mac(&in6
, mac_addr
);
536 memcpy(mac_addr
, ah_attr
->dmac
, ETH_ALEN
);
540 static inline char *hca_name(struct ocrdma_dev
*dev
)
542 switch (dev
->nic_info
.pdev
->device
) {
543 case OC_SKH_DEVICE_PF
:
544 case OC_SKH_DEVICE_VF
:
547 return OC_NAME_UNKNOWN
;
551 static inline int ocrdma_get_eq_table_index(struct ocrdma_dev
*dev
,
556 for (indx
= 0; indx
< dev
->eq_cnt
; indx
++) {
557 if (dev
->eq_tbl
[indx
].q
.id
== eqid
)
564 static inline u8
ocrdma_get_asic_type(struct ocrdma_dev
*dev
)
566 if (dev
->nic_info
.dev_family
== 0xF && !dev
->asic_id
) {
567 pci_read_config_dword(
569 OCRDMA_SLI_ASIC_ID_OFFSET
, &dev
->asic_id
);
572 return (dev
->asic_id
& OCRDMA_SLI_ASIC_GEN_NUM_MASK
) >>
573 OCRDMA_SLI_ASIC_GEN_NUM_SHIFT
;
576 static inline u8
ocrdma_get_pfc_prio(u8
*pfc
, u8 prio
)
578 return *(pfc
+ prio
);
581 static inline u8
ocrdma_get_app_prio(u8
*app_prio
, u8 prio
)
583 return *(app_prio
+ prio
);
586 static inline u8
ocrdma_is_enabled_and_synced(u32 state
)
587 { /* May also be used to interpret TC-state, QCN-state
588 * Appl-state and Logical-link-state in future.
590 return (state
& OCRDMA_STATE_FLAG_ENABLED
) &&
591 (state
& OCRDMA_STATE_FLAG_SYNC
);