drivers/infiniband/hw/qedr/qedr.h

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __QEDR_H__
  33 #define __QEDR_H__
  34
  35 #include <linux/pci.h>
  36 #include <rdma/ib_addr.h>
  37 #include <linux/qed/qed_if.h>
  38 #include <linux/qed/qed_chain.h>
  39 #include <linux/qed/qed_roce_if.h>
  40 #include <linux/qed/qede_roce.h>
  41 #include "qedr_hsi.h"
  42
  43 #define QEDR_MODULE_VERSION     "8.10.10.0"
  44 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
  45 #define DP_NAME(dev) ((dev)->ibdev.name)
  46
  47 #define DP_DEBUG(dev, module, fmt, ...)                                 \
  48         pr_debug("(%s) " module ": " fmt,                               \
  49                  DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
  50
  51 #define QEDR_MSG_INIT "INIT"
  52 #define QEDR_MSG_MISC "MISC"
  53 #define QEDR_MSG_CQ   "  CQ"
  54 #define QEDR_MSG_MR   "  MR"
  55 #define QEDR_MSG_RQ   "  RQ"
  56 #define QEDR_MSG_SQ   "  SQ"
  57 #define QEDR_MSG_QP   "  QP"
  58 #define QEDR_MSG_GSI  " GSI"
  59
  60 #define QEDR_CQ_MAGIC_NUMBER   (0x11223344)
  61
  62 struct qedr_dev;
  63
  64 struct qedr_cnq {
  65         struct qedr_dev         *dev;
  66         struct qed_chain        pbl;
  67         struct qed_sb_info      *sb;
  68         char                    name[32];
  69         u64                     n_comp;
  70         __le16                  *hw_cons_ptr;
  71         u8                      index;
  72 };
  73
  74 #define QEDR_MAX_SGID 128
  75
  76 struct qedr_device_attr {
  77         u32     vendor_id;
  78         u32     vendor_part_id;
  79         u32     hw_ver;
  80         u64     fw_ver;
  81         u64     node_guid;
  82         u64     sys_image_guid;
  83         u8      max_cnq;
  84         u8      max_sge;
  85         u16     max_inline;
  86         u32     max_sqe;
  87         u32     max_rqe;
  88         u8      max_qp_resp_rd_atomic_resc;
  89         u8      max_qp_req_rd_atomic_resc;
  90         u64     max_dev_resp_rd_atomic_resc;
  91         u32     max_cq;
  92         u32     max_qp;
  93         u32     max_mr;
  94         u64     max_mr_size;
  95         u32     max_cqe;
  96         u32     max_mw;
  97         u32     max_fmr;
  98         u32     max_mr_mw_fmr_pbl;
  99         u64     max_mr_mw_fmr_size;
 100         u32     max_pd;
 101         u32     max_ah;
 102         u8      max_pkey;
 103         u32     max_srq;
 104         u32     max_srq_wr;
 105         u8      max_srq_sge;
 106         u8      max_stats_queues;
 107         u32     dev_caps;
 108
 109         u64     page_size_caps;
 110         u8      dev_ack_delay;
 111         u32     reserved_lkey;
 112         u32     bad_pkey_counter;
 113         struct qed_rdma_events events;
 114 };
 115
 116 struct qedr_dev {
 117         struct ib_device        ibdev;
 118         struct qed_dev          *cdev;
 119         struct pci_dev          *pdev;
 120         struct net_device       *ndev;
 121
 122         enum ib_atomic_cap      atomic_cap;
 123
 124         void *rdma_ctx;
 125         struct qedr_device_attr attr;
 126
 127         const struct qed_rdma_ops *ops;
 128         struct qed_int_info     int_info;
 129
 130         struct qed_sb_info      *sb_array;
 131         struct qedr_cnq         *cnq_array;
 132         int                     num_cnq;
 133         int                     sb_start;
 134
 135         void __iomem            *db_addr;
 136         u64                     db_phys_addr;
 137         u32                     db_size;
 138         u16                     dpi;
 139
 140         union ib_gid *sgid_tbl;
 141
 142         /* Lock for sgid table */
 143         spinlock_t sgid_lock;
 144
 145         u64                     guid;
 146
 147         u32                     dp_module;
 148         u8                      dp_level;
 149         u8                      num_hwfns;
 150         uint                    wq_multiplier;
 151         u8                      gsi_ll2_mac_address[ETH_ALEN];
 152         int                     gsi_qp_created;
 153         struct qedr_cq          *gsi_sqcq;
 154         struct qedr_cq          *gsi_rqcq;
 155         struct qedr_qp          *gsi_qp;
 156 };
 157
 158 #define QEDR_MAX_SQ_PBL                 (0x8000)
 159 #define QEDR_MAX_SQ_PBL_ENTRIES         (0x10000 / sizeof(void *))
 160 #define QEDR_SQE_ELEMENT_SIZE           (sizeof(struct rdma_sq_sge))
 161 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE   (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
 162                                          QEDR_SQE_ELEMENT_SIZE)
 163 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE  ((RDMA_RING_PAGE_SIZE) / \
 164                                          QEDR_SQE_ELEMENT_SIZE)
 165 #define QEDR_MAX_SQE                    ((QEDR_MAX_SQ_PBL_ENTRIES) *\
 166                                          (RDMA_RING_PAGE_SIZE) / \
 167                                          (QEDR_SQE_ELEMENT_SIZE) /\
 168                                          (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
 169 /* RQ */
 170 #define QEDR_MAX_RQ_PBL                 (0x2000)
 171 #define QEDR_MAX_RQ_PBL_ENTRIES         (0x10000 / sizeof(void *))
 172 #define QEDR_RQE_ELEMENT_SIZE           (sizeof(struct rdma_rq_sge))
 173 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE   (RDMA_MAX_SGE_PER_RQ_WQE)
 174 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE  ((RDMA_RING_PAGE_SIZE) / \
 175                                          QEDR_RQE_ELEMENT_SIZE)
 176 #define QEDR_MAX_RQE                    ((QEDR_MAX_RQ_PBL_ENTRIES) *\
 177                                          (RDMA_RING_PAGE_SIZE) / \
 178                                          (QEDR_RQE_ELEMENT_SIZE) /\
 179                                          (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
 180
 181 #define QEDR_CQE_SIZE   (sizeof(union rdma_cqe))
 182 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
 183 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
 184                                   sizeof(u64)) - 1)
 185 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
 186                              (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
 187
 188 #define QEDR_ROCE_MAX_CNQ_SIZE          (0x4000)
 189
 190 #define QEDR_MAX_PORT                   (1)
 191
 192 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
 193
 194 #define QEDR_ROCE_PKEY_MAX 1
 195 #define QEDR_ROCE_PKEY_TABLE_LEN 1
 196 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
 197
 198 struct qedr_pbl {
 199         struct list_head list_entry;
 200         void *va;
 201         dma_addr_t pa;
 202 };
 203
 204 struct qedr_ucontext {
 205         struct ib_ucontext ibucontext;
 206         struct qedr_dev *dev;
 207         struct qedr_pd *pd;
 208         u64 dpi_addr;
 209         u64 dpi_phys_addr;
 210         u32 dpi_size;
 211         u16 dpi;
 212
 213         struct list_head mm_head;
 214
 215         /* Lock to protect mm list */
 216         struct mutex mm_list_lock;
 217 };
 218
 219 union db_prod64 {
 220         struct rdma_pwm_val32_data data;
 221         u64 raw;
 222 };
 223
 224 enum qedr_cq_type {
 225         QEDR_CQ_TYPE_GSI,
 226         QEDR_CQ_TYPE_KERNEL,
 227         QEDR_CQ_TYPE_USER,
 228 };
 229
 230 struct qedr_pbl_info {
 231         u32 num_pbls;
 232         u32 num_pbes;
 233         u32 pbl_size;
 234         u32 pbe_size;
 235         bool two_layered;
 236 };
 237
 238 struct qedr_userq {
 239         struct ib_umem *umem;
 240         struct qedr_pbl_info pbl_info;
 241         struct qedr_pbl *pbl_tbl;
 242         u64 buf_addr;
 243         size_t buf_len;
 244 };
 245
 246 struct qedr_cq {
 247         struct ib_cq ibcq;
 248
 249         enum qedr_cq_type cq_type;
 250         u32 sig;
 251
 252         u16 icid;
 253
 254         /* Lock to protect completion handler */
 255         spinlock_t comp_handler_lock;
 256
 257         /* Lock to protect multiplem CQ's */
 258         spinlock_t cq_lock;
 259         u8 arm_flags;
 260         struct qed_chain pbl;
 261
 262         void __iomem *db_addr;
 263         union db_prod64 db;
 264
 265         u8 pbl_toggle;
 266         union rdma_cqe *latest_cqe;
 267         union rdma_cqe *toggle_cqe;
 268
 269         u32 cq_cons;
 270
 271         struct qedr_userq q;
 272 };
 273
 274 struct qedr_pd {
 275         struct ib_pd ibpd;
 276         u32 pd_id;
 277         struct qedr_ucontext *uctx;
 278 };
 279
 280 struct qedr_mm {
 281         struct {
 282                 u64 phy_addr;
 283                 unsigned long len;
 284         } key;
 285         struct list_head entry;
 286 };
 287
 288 union db_prod32 {
 289         struct rdma_pwm_val16_data data;
 290         u32 raw;
 291 };
 292
 293 struct qedr_qp_hwq_info {
 294         /* WQE Elements */
 295         struct qed_chain pbl;
 296         u64 p_phys_addr_tbl;
 297         u32 max_sges;
 298
 299         /* WQE */
 300         u16 prod;
 301         u16 cons;
 302         u16 wqe_cons;
 303         u16 gsi_cons;
 304         u16 max_wr;
 305
 306         /* DB */
 307         void __iomem *db;
 308         union db_prod32 db_data;
 309 };
 310
 311 #define QEDR_INC_SW_IDX(p_info, index)                                  \
 312         do {                                                            \
 313                 p_info->index = (p_info->index + 1) &                   \
 314                                 qed_chain_get_capacity(p_info->pbl)     \
 315         } while (0)
 316
 317 enum qedr_qp_err_bitmap {
 318         QEDR_QP_ERR_SQ_FULL = 1,
 319         QEDR_QP_ERR_RQ_FULL = 2,
 320         QEDR_QP_ERR_BAD_SR = 4,
 321         QEDR_QP_ERR_BAD_RR = 8,
 322         QEDR_QP_ERR_SQ_PBL_FULL = 16,
 323         QEDR_QP_ERR_RQ_PBL_FULL = 32,
 324 };
 325
 326 struct qedr_qp {
 327         struct ib_qp ibqp;      /* must be first */
 328         struct qedr_dev *dev;
 329
 330         struct qedr_qp_hwq_info sq;
 331         struct qedr_qp_hwq_info rq;
 332
 333         u32 max_inline_data;
 334
 335         /* Lock for QP's */
 336         spinlock_t q_lock;
 337         struct qedr_cq *sq_cq;
 338         struct qedr_cq *rq_cq;
 339         struct qedr_srq *srq;
 340         enum qed_roce_qp_state state;
 341         u32 id;
 342         struct qedr_pd *pd;
 343         enum ib_qp_type qp_type;
 344         struct qed_rdma_qp *qed_qp;
 345         u32 qp_id;
 346         u16 icid;
 347         u16 mtu;
 348         int sgid_idx;
 349         u32 rq_psn;
 350         u32 sq_psn;
 351         u32 qkey;
 352         u32 dest_qp_num;
 353
 354         /* Relevant to qps created from kernel space only (ULPs) */
 355         u8 prev_wqe_size;
 356         u16 wqe_cons;
 357         u32 err_bitmap;
 358         bool signaled;
 359
 360         /* SQ shadow */
 361         struct {
 362                 u64 wr_id;
 363                 enum ib_wc_opcode opcode;
 364                 u32 bytes_len;
 365                 u8 wqe_size;
 366                 bool signaled;
 367                 dma_addr_t icrc_mapping;
 368                 u32 *icrc;
 369                 struct qedr_mr *mr;
 370         } *wqe_wr_id;
 371
 372         /* RQ shadow */
 373         struct {
 374                 u64 wr_id;
 375                 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
 376                 u8 wqe_size;
 377
 378                 u8 smac[ETH_ALEN];
 379                 u16 vlan_id;
 380                 int rc;
 381         } *rqe_wr_id;
 382
 383         /* Relevant to qps created from user space only (applications) */
 384         struct qedr_userq usq;
 385         struct qedr_userq urq;
 386 };
 387
 388 struct qedr_ah {
 389         struct ib_ah ibah;
 390         struct ib_ah_attr attr;
 391 };
 392
 393 enum qedr_mr_type {
 394         QEDR_MR_USER,
 395         QEDR_MR_KERNEL,
 396         QEDR_MR_DMA,
 397         QEDR_MR_FRMR,
 398 };
 399
 400 struct mr_info {
 401         struct qedr_pbl *pbl_table;
 402         struct qedr_pbl_info pbl_info;
 403         struct list_head free_pbl_list;
 404         struct list_head inuse_pbl_list;
 405         u32 completed;
 406         u32 completed_handled;
 407 };
 408
 409 struct qedr_mr {
 410         struct ib_mr ibmr;
 411         struct ib_umem *umem;
 412
 413         struct qed_rdma_register_tid_in_params hw_mr;
 414         enum qedr_mr_type type;
 415
 416         struct qedr_dev *dev;
 417         struct mr_info info;
 418
 419         u64 *pages;
 420         u32 npages;
 421 };
 422
 423 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
 424
 425 #define QEDR_RESP_IMM   (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
 426                          RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
 427 #define QEDR_RESP_RDMA  (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
 428                          RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
 429 #define QEDR_RESP_RDMA_IMM (QEDR_RESP_IMM | QEDR_RESP_RDMA)
 430
 431 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
 432 {
 433         info->cons = (info->cons + 1) % info->max_wr;
 434         info->wqe_cons++;
 435 }
 436
 437 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
 438 {
 439         info->prod = (info->prod + 1) % info->max_wr;
 440 }
 441
 442 static inline int qedr_get_dmac(struct qedr_dev *dev,
 443                                 struct ib_ah_attr *ah_attr, u8 *mac_addr)
 444 {
 445         union ib_gid zero_sgid = { { 0 } };
 446         struct in6_addr in6;
 447
 448         if (!memcmp(&ah_attr->grh.dgid, &zero_sgid, sizeof(union ib_gid))) {
 449                 DP_ERR(dev, "Local port GID not supported\n");
 450                 eth_zero_addr(mac_addr);
 451                 return -EINVAL;
 452         }
 453
 454         memcpy(&in6, ah_attr->grh.dgid.raw, sizeof(in6));
 455         ether_addr_copy(mac_addr, ah_attr->dmac);
 456
 457         return 0;
 458 }
 459
 460 static inline
 461 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
 462 {
 463         return container_of(ibucontext, struct qedr_ucontext, ibucontext);
 464 }
 465
 466 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
 467 {
 468         return container_of(ibdev, struct qedr_dev, ibdev);
 469 }
 470
 471 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
 472 {
 473         return container_of(ibpd, struct qedr_pd, ibpd);
 474 }
 475
 476 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
 477 {
 478         return container_of(ibcq, struct qedr_cq, ibcq);
 479 }
 480
 481 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
 482 {
 483         return container_of(ibqp, struct qedr_qp, ibqp);
 484 }
 485
 486 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
 487 {
 488         return container_of(ibah, struct qedr_ah, ibah);
 489 }
 490
 491 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
 492 {
 493         return container_of(ibmr, struct qedr_mr, ibmr);
 494 }
 495 #endif