drivers/infiniband/hw/qedr/qedr.h

   1 /* QLogic qedr NIC Driver
   2  * Copyright (c) 2015-2016  QLogic Corporation
   3  *
   4  * This software is available to you under a choice of one of two
   5  * licenses.  You may choose to be licensed under the terms of the GNU
   6  * General Public License (GPL) Version 2, available from the file
   7  * COPYING in the main directory of this source tree, or the
   8  * OpenIB.org BSD license below:
   9  *
  10  *     Redistribution and use in source and binary forms, with or
  11  *     without modification, are permitted provided that the following
  12  *     conditions are met:
  13  *
  14  *      - Redistributions of source code must retain the above
  15  *        copyright notice, this list of conditions and the following
  16  *        disclaimer.
  17  *
  18  *      - Redistributions in binary form must reproduce the above
  19  *        copyright notice, this list of conditions and the following
  20  *        disclaimer in the documentation and /or other materials
  21  *        provided with the distribution.
  22  *
  23  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30  * SOFTWARE.
  31  */
  32 #ifndef __QEDR_H__
  33 #define __QEDR_H__
  34
  35 #include <linux/pci.h>
  36 #include <rdma/ib_addr.h>
  37 #include <linux/qed/qed_if.h>
  38 #include <linux/qed/qed_chain.h>
  39 #include <linux/qed/qed_roce_if.h>
  40 #include <linux/qed/qede_roce.h>
  41 #include <linux/qed/roce_common.h>
  42 #include "qedr_hsi_rdma.h"
  43
  44 #define QEDR_MODULE_VERSION     "8.10.10.0"
  45 #define QEDR_NODE_DESC "QLogic 579xx RoCE HCA"
  46 #define DP_NAME(dev) ((dev)->ibdev.name)
  47
  48 #define DP_DEBUG(dev, module, fmt, ...)                                 \
  49         pr_debug("(%s) " module ": " fmt,                               \
  50                  DP_NAME(dev) ? DP_NAME(dev) : "", ## __VA_ARGS__)
  51
  52 #define QEDR_MSG_INIT "INIT"
  53 #define QEDR_MSG_MISC "MISC"
  54 #define QEDR_MSG_CQ   "  CQ"
  55 #define QEDR_MSG_MR   "  MR"
  56 #define QEDR_MSG_RQ   "  RQ"
  57 #define QEDR_MSG_SQ   "  SQ"
  58 #define QEDR_MSG_QP   "  QP"
  59 #define QEDR_MSG_GSI  " GSI"
  60
  61 #define QEDR_CQ_MAGIC_NUMBER   (0x11223344)
  62
  63 struct qedr_dev;
  64
  65 struct qedr_cnq {
  66         struct qedr_dev         *dev;
  67         struct qed_chain        pbl;
  68         struct qed_sb_info      *sb;
  69         char                    name[32];
  70         u64                     n_comp;
  71         __le16                  *hw_cons_ptr;
  72         u8                      index;
  73 };
  74
  75 #define QEDR_MAX_SGID 128
  76
  77 struct qedr_device_attr {
  78         u32     vendor_id;
  79         u32     vendor_part_id;
  80         u32     hw_ver;
  81         u64     fw_ver;
  82         u64     node_guid;
  83         u64     sys_image_guid;
  84         u8      max_cnq;
  85         u8      max_sge;
  86         u16     max_inline;
  87         u32     max_sqe;
  88         u32     max_rqe;
  89         u8      max_qp_resp_rd_atomic_resc;
  90         u8      max_qp_req_rd_atomic_resc;
  91         u64     max_dev_resp_rd_atomic_resc;
  92         u32     max_cq;
  93         u32     max_qp;
  94         u32     max_mr;
  95         u64     max_mr_size;
  96         u32     max_cqe;
  97         u32     max_mw;
  98         u32     max_fmr;
  99         u32     max_mr_mw_fmr_pbl;
 100         u64     max_mr_mw_fmr_size;
 101         u32     max_pd;
 102         u32     max_ah;
 103         u8      max_pkey;
 104         u32     max_srq;
 105         u32     max_srq_wr;
 106         u8      max_srq_sge;
 107         u8      max_stats_queues;
 108         u32     dev_caps;
 109
 110         u64     page_size_caps;
 111         u8      dev_ack_delay;
 112         u32     reserved_lkey;
 113         u32     bad_pkey_counter;
 114         struct qed_rdma_events events;
 115 };
 116
 117 #define QEDR_ENET_STATE_BIT     (0)
 118
 119 struct qedr_dev {
 120         struct ib_device        ibdev;
 121         struct qed_dev          *cdev;
 122         struct pci_dev          *pdev;
 123         struct net_device       *ndev;
 124
 125         enum ib_atomic_cap      atomic_cap;
 126
 127         void *rdma_ctx;
 128         struct qedr_device_attr attr;
 129
 130         const struct qed_rdma_ops *ops;
 131         struct qed_int_info     int_info;
 132
 133         struct qed_sb_info      *sb_array;
 134         struct qedr_cnq         *cnq_array;
 135         int                     num_cnq;
 136         int                     sb_start;
 137
 138         void __iomem            *db_addr;
 139         u64                     db_phys_addr;
 140         u32                     db_size;
 141         u16                     dpi;
 142
 143         union ib_gid *sgid_tbl;
 144
 145         /* Lock for sgid table */
 146         spinlock_t sgid_lock;
 147
 148         u64                     guid;
 149
 150         u32                     dp_module;
 151         u8                      dp_level;
 152         u8                      num_hwfns;
 153         uint                    wq_multiplier;
 154         u8                      gsi_ll2_mac_address[ETH_ALEN];
 155         int                     gsi_qp_created;
 156         struct qedr_cq          *gsi_sqcq;
 157         struct qedr_cq          *gsi_rqcq;
 158         struct qedr_qp          *gsi_qp;
 159
 160         unsigned long enet_state;
 161 };
 162
 163 #define QEDR_MAX_SQ_PBL                 (0x8000)
 164 #define QEDR_MAX_SQ_PBL_ENTRIES         (0x10000 / sizeof(void *))
 165 #define QEDR_SQE_ELEMENT_SIZE           (sizeof(struct rdma_sq_sge))
 166 #define QEDR_MAX_SQE_ELEMENTS_PER_SQE   (ROCE_REQ_MAX_SINGLE_SQ_WQE_SIZE / \
 167                                          QEDR_SQE_ELEMENT_SIZE)
 168 #define QEDR_MAX_SQE_ELEMENTS_PER_PAGE  ((RDMA_RING_PAGE_SIZE) / \
 169                                          QEDR_SQE_ELEMENT_SIZE)
 170 #define QEDR_MAX_SQE                    ((QEDR_MAX_SQ_PBL_ENTRIES) *\
 171                                          (RDMA_RING_PAGE_SIZE) / \
 172                                          (QEDR_SQE_ELEMENT_SIZE) /\
 173                                          (QEDR_MAX_SQE_ELEMENTS_PER_SQE))
 174 /* RQ */
 175 #define QEDR_MAX_RQ_PBL                 (0x2000)
 176 #define QEDR_MAX_RQ_PBL_ENTRIES         (0x10000 / sizeof(void *))
 177 #define QEDR_RQE_ELEMENT_SIZE           (sizeof(struct rdma_rq_sge))
 178 #define QEDR_MAX_RQE_ELEMENTS_PER_RQE   (RDMA_MAX_SGE_PER_RQ_WQE)
 179 #define QEDR_MAX_RQE_ELEMENTS_PER_PAGE  ((RDMA_RING_PAGE_SIZE) / \
 180                                          QEDR_RQE_ELEMENT_SIZE)
 181 #define QEDR_MAX_RQE                    ((QEDR_MAX_RQ_PBL_ENTRIES) *\
 182                                          (RDMA_RING_PAGE_SIZE) / \
 183                                          (QEDR_RQE_ELEMENT_SIZE) /\
 184                                          (QEDR_MAX_RQE_ELEMENTS_PER_RQE))
 185
 186 #define QEDR_CQE_SIZE   (sizeof(union rdma_cqe))
 187 #define QEDR_MAX_CQE_PBL_SIZE (512 * 1024)
 188 #define QEDR_MAX_CQE_PBL_ENTRIES (((QEDR_MAX_CQE_PBL_SIZE) / \
 189                                   sizeof(u64)) - 1)
 190 #define QEDR_MAX_CQES ((u32)((QEDR_MAX_CQE_PBL_ENTRIES) * \
 191                              (QED_CHAIN_PAGE_SIZE) / QEDR_CQE_SIZE))
 192
 193 #define QEDR_ROCE_MAX_CNQ_SIZE          (0x4000)
 194
 195 #define QEDR_MAX_PORT                   (1)
 196 #define QEDR_PORT                       (1)
 197
 198 #define QEDR_UVERBS(CMD_NAME) (1ull << IB_USER_VERBS_CMD_##CMD_NAME)
 199
 200 #define QEDR_ROCE_PKEY_MAX 1
 201 #define QEDR_ROCE_PKEY_TABLE_LEN 1
 202 #define QEDR_ROCE_PKEY_DEFAULT 0xffff
 203
 204 struct qedr_pbl {
 205         struct list_head list_entry;
 206         void *va;
 207         dma_addr_t pa;
 208 };
 209
 210 struct qedr_ucontext {
 211         struct ib_ucontext ibucontext;
 212         struct qedr_dev *dev;
 213         struct qedr_pd *pd;
 214         u64 dpi_addr;
 215         u64 dpi_phys_addr;
 216         u32 dpi_size;
 217         u16 dpi;
 218
 219         struct list_head mm_head;
 220
 221         /* Lock to protect mm list */
 222         struct mutex mm_list_lock;
 223 };
 224
 225 union db_prod64 {
 226         struct rdma_pwm_val32_data data;
 227         u64 raw;
 228 };
 229
 230 enum qedr_cq_type {
 231         QEDR_CQ_TYPE_GSI,
 232         QEDR_CQ_TYPE_KERNEL,
 233         QEDR_CQ_TYPE_USER,
 234 };
 235
 236 struct qedr_pbl_info {
 237         u32 num_pbls;
 238         u32 num_pbes;
 239         u32 pbl_size;
 240         u32 pbe_size;
 241         bool two_layered;
 242 };
 243
 244 struct qedr_userq {
 245         struct ib_umem *umem;
 246         struct qedr_pbl_info pbl_info;
 247         struct qedr_pbl *pbl_tbl;
 248         u64 buf_addr;
 249         size_t buf_len;
 250 };
 251
 252 struct qedr_cq {
 253         struct ib_cq ibcq;
 254
 255         enum qedr_cq_type cq_type;
 256         u32 sig;
 257
 258         u16 icid;
 259
 260         /* Lock to protect multiplem CQ's */
 261         spinlock_t cq_lock;
 262         u8 arm_flags;
 263         struct qed_chain pbl;
 264
 265         void __iomem *db_addr;
 266         union db_prod64 db;
 267
 268         u8 pbl_toggle;
 269         union rdma_cqe *latest_cqe;
 270         union rdma_cqe *toggle_cqe;
 271
 272         u32 cq_cons;
 273
 274         struct qedr_userq q;
 275         u8 destroyed;
 276         u16 cnq_notif;
 277 };
 278
 279 struct qedr_pd {
 280         struct ib_pd ibpd;
 281         u32 pd_id;
 282         struct qedr_ucontext *uctx;
 283 };
 284
 285 struct qedr_mm {
 286         struct {
 287                 u64 phy_addr;
 288                 unsigned long len;
 289         } key;
 290         struct list_head entry;
 291 };
 292
 293 union db_prod32 {
 294         struct rdma_pwm_val16_data data;
 295         u32 raw;
 296 };
 297
 298 struct qedr_qp_hwq_info {
 299         /* WQE Elements */
 300         struct qed_chain pbl;
 301         u64 p_phys_addr_tbl;
 302         u32 max_sges;
 303
 304         /* WQE */
 305         u16 prod;
 306         u16 cons;
 307         u16 wqe_cons;
 308         u16 gsi_cons;
 309         u16 max_wr;
 310
 311         /* DB */
 312         void __iomem *db;
 313         union db_prod32 db_data;
 314 };
 315
 316 #define QEDR_INC_SW_IDX(p_info, index)                                  \
 317         do {                                                            \
 318                 p_info->index = (p_info->index + 1) &                   \
 319                                 qed_chain_get_capacity(p_info->pbl)     \
 320         } while (0)
 321
 322 enum qedr_qp_err_bitmap {
 323         QEDR_QP_ERR_SQ_FULL = 1,
 324         QEDR_QP_ERR_RQ_FULL = 2,
 325         QEDR_QP_ERR_BAD_SR = 4,
 326         QEDR_QP_ERR_BAD_RR = 8,
 327         QEDR_QP_ERR_SQ_PBL_FULL = 16,
 328         QEDR_QP_ERR_RQ_PBL_FULL = 32,
 329 };
 330
 331 struct qedr_qp {
 332         struct ib_qp ibqp;      /* must be first */
 333         struct qedr_dev *dev;
 334
 335         struct qedr_qp_hwq_info sq;
 336         struct qedr_qp_hwq_info rq;
 337
 338         u32 max_inline_data;
 339
 340         /* Lock for QP's */
 341         spinlock_t q_lock;
 342         struct qedr_cq *sq_cq;
 343         struct qedr_cq *rq_cq;
 344         struct qedr_srq *srq;
 345         enum qed_roce_qp_state state;
 346         u32 id;
 347         struct qedr_pd *pd;
 348         enum ib_qp_type qp_type;
 349         struct qed_rdma_qp *qed_qp;
 350         u32 qp_id;
 351         u16 icid;
 352         u16 mtu;
 353         int sgid_idx;
 354         u32 rq_psn;
 355         u32 sq_psn;
 356         u32 qkey;
 357         u32 dest_qp_num;
 358
 359         /* Relevant to qps created from kernel space only (ULPs) */
 360         u8 prev_wqe_size;
 361         u16 wqe_cons;
 362         u32 err_bitmap;
 363         bool signaled;
 364
 365         /* SQ shadow */
 366         struct {
 367                 u64 wr_id;
 368                 enum ib_wc_opcode opcode;
 369                 u32 bytes_len;
 370                 u8 wqe_size;
 371                 bool signaled;
 372                 dma_addr_t icrc_mapping;
 373                 u32 *icrc;
 374                 struct qedr_mr *mr;
 375         } *wqe_wr_id;
 376
 377         /* RQ shadow */
 378         struct {
 379                 u64 wr_id;
 380                 struct ib_sge sg_list[RDMA_MAX_SGE_PER_RQ_WQE];
 381                 u8 wqe_size;
 382
 383                 u8 smac[ETH_ALEN];
 384                 u16 vlan_id;
 385                 int rc;
 386         } *rqe_wr_id;
 387
 388         /* Relevant to qps created from user space only (applications) */
 389         struct qedr_userq usq;
 390         struct qedr_userq urq;
 391 };
 392
 393 struct qedr_ah {
 394         struct ib_ah ibah;
 395         struct rdma_ah_attr attr;
 396 };
 397
 398 enum qedr_mr_type {
 399         QEDR_MR_USER,
 400         QEDR_MR_KERNEL,
 401         QEDR_MR_DMA,
 402         QEDR_MR_FRMR,
 403 };
 404
 405 struct mr_info {
 406         struct qedr_pbl *pbl_table;
 407         struct qedr_pbl_info pbl_info;
 408         struct list_head free_pbl_list;
 409         struct list_head inuse_pbl_list;
 410         u32 completed;
 411         u32 completed_handled;
 412 };
 413
 414 struct qedr_mr {
 415         struct ib_mr ibmr;
 416         struct ib_umem *umem;
 417
 418         struct qed_rdma_register_tid_in_params hw_mr;
 419         enum qedr_mr_type type;
 420
 421         struct qedr_dev *dev;
 422         struct mr_info info;
 423
 424         u64 *pages;
 425         u32 npages;
 426 };
 427
 428 #define SET_FIELD2(value, name, flag) ((value) |= ((flag) << (name ## _SHIFT)))
 429
 430 #define QEDR_RESP_IMM   (RDMA_CQE_RESPONDER_IMM_FLG_MASK << \
 431                          RDMA_CQE_RESPONDER_IMM_FLG_SHIFT)
 432 #define QEDR_RESP_RDMA  (RDMA_CQE_RESPONDER_RDMA_FLG_MASK << \
 433                          RDMA_CQE_RESPONDER_RDMA_FLG_SHIFT)
 434 #define QEDR_RESP_INV   (RDMA_CQE_RESPONDER_INV_FLG_MASK << \
 435                          RDMA_CQE_RESPONDER_INV_FLG_SHIFT)
 436
 437 static inline void qedr_inc_sw_cons(struct qedr_qp_hwq_info *info)
 438 {
 439         info->cons = (info->cons + 1) % info->max_wr;
 440         info->wqe_cons++;
 441 }
 442
 443 static inline void qedr_inc_sw_prod(struct qedr_qp_hwq_info *info)
 444 {
 445         info->prod = (info->prod + 1) % info->max_wr;
 446 }
 447
 448 static inline int qedr_get_dmac(struct qedr_dev *dev,
 449                                 struct rdma_ah_attr *ah_attr, u8 *mac_addr)
 450 {
 451         union ib_gid zero_sgid = { { 0 } };
 452         struct in6_addr in6;
 453         const struct ib_global_route *grh = rdma_ah_read_grh(ah_attr);
 454         u8 *dmac;
 455
 456         if (!memcmp(&grh->dgid, &zero_sgid, sizeof(union ib_gid))) {
 457                 DP_ERR(dev, "Local port GID not supported\n");
 458                 eth_zero_addr(mac_addr);
 459                 return -EINVAL;
 460         }
 461
 462         memcpy(&in6, grh->dgid.raw, sizeof(in6));
 463         dmac = rdma_ah_retrieve_dmac(ah_attr);
 464         if (!dmac)
 465                 return -EINVAL;
 466         ether_addr_copy(mac_addr, dmac);
 467
 468         return 0;
 469 }
 470
 471 static inline
 472 struct qedr_ucontext *get_qedr_ucontext(struct ib_ucontext *ibucontext)
 473 {
 474         return container_of(ibucontext, struct qedr_ucontext, ibucontext);
 475 }
 476
 477 static inline struct qedr_dev *get_qedr_dev(struct ib_device *ibdev)
 478 {
 479         return container_of(ibdev, struct qedr_dev, ibdev);
 480 }
 481
 482 static inline struct qedr_pd *get_qedr_pd(struct ib_pd *ibpd)
 483 {
 484         return container_of(ibpd, struct qedr_pd, ibpd);
 485 }
 486
 487 static inline struct qedr_cq *get_qedr_cq(struct ib_cq *ibcq)
 488 {
 489         return container_of(ibcq, struct qedr_cq, ibcq);
 490 }
 491
 492 static inline struct qedr_qp *get_qedr_qp(struct ib_qp *ibqp)
 493 {
 494         return container_of(ibqp, struct qedr_qp, ibqp);
 495 }
 496
 497 static inline struct qedr_ah *get_qedr_ah(struct ib_ah *ibah)
 498 {
 499         return container_of(ibah, struct qedr_ah, ibah);
 500 }
 501
 502 static inline struct qedr_mr *get_qedr_mr(struct ib_mr *ibmr)
 503 {
 504         return container_of(ibmr, struct qedr_mr, ibmr);
 505 }
 506 #endif