2 * Copyright (c) 2006, 2007, 2008, 2009, 2010 QLogic Corporation.
4 * Copyright (c) 2003, 2004, 2005, 2006 PathScale, Inc. All rights reserved.
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
35 * This file contains all of the code that is specific to the
36 * QLogic_IB 7220 chip (except that specific to the SerDes)
39 #include <linux/interrupt.h>
40 #include <linux/pci.h>
41 #include <linux/delay.h>
42 #include <linux/module.h>
44 #include <rdma/ib_verbs.h>
49 static void qib_setup_7220_setextled(struct qib_pportdata
*, u32
);
50 static void qib_7220_handle_hwerrors(struct qib_devdata
*, char *, size_t);
51 static void sendctrl_7220_mod(struct qib_pportdata
*ppd
, u32 op
);
52 static u32
qib_7220_iblink_state(u64
);
53 static u8
qib_7220_phys_portstate(u64
);
54 static void qib_sdma_update_7220_tail(struct qib_pportdata
*, u16
);
55 static void qib_set_ib_7220_lstate(struct qib_pportdata
*, u16
, u16
);
58 * This file contains almost all the chip-specific register information and
59 * access functions for the QLogic QLogic_IB 7220 PCI-Express chip, with the
60 * exception of SerDes support, which in in qib_sd7220.c.
63 /* Below uses machine-generated qib_chipnum_regs.h file */
64 #define KREG_IDX(regname) (QIB_7220_##regname##_OFFS / sizeof(u64))
66 /* Use defines to tie machine-generated names to lower-case names */
67 #define kr_control KREG_IDX(Control)
68 #define kr_counterregbase KREG_IDX(CntrRegBase)
69 #define kr_errclear KREG_IDX(ErrClear)
70 #define kr_errmask KREG_IDX(ErrMask)
71 #define kr_errstatus KREG_IDX(ErrStatus)
72 #define kr_extctrl KREG_IDX(EXTCtrl)
73 #define kr_extstatus KREG_IDX(EXTStatus)
74 #define kr_gpio_clear KREG_IDX(GPIOClear)
75 #define kr_gpio_mask KREG_IDX(GPIOMask)
76 #define kr_gpio_out KREG_IDX(GPIOOut)
77 #define kr_gpio_status KREG_IDX(GPIOStatus)
78 #define kr_hrtbt_guid KREG_IDX(HRTBT_GUID)
79 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
80 #define kr_hwerrclear KREG_IDX(HwErrClear)
81 #define kr_hwerrmask KREG_IDX(HwErrMask)
82 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
83 #define kr_ibcctrl KREG_IDX(IBCCtrl)
84 #define kr_ibcddrctrl KREG_IDX(IBCDDRCtrl)
85 #define kr_ibcddrstatus KREG_IDX(IBCDDRStatus)
86 #define kr_ibcstatus KREG_IDX(IBCStatus)
87 #define kr_ibserdesctrl KREG_IDX(IBSerDesCtrl)
88 #define kr_intclear KREG_IDX(IntClear)
89 #define kr_intmask KREG_IDX(IntMask)
90 #define kr_intstatus KREG_IDX(IntStatus)
91 #define kr_ncmodectrl KREG_IDX(IBNCModeCtrl)
92 #define kr_palign KREG_IDX(PageAlign)
93 #define kr_partitionkey KREG_IDX(RcvPartitionKey)
94 #define kr_portcnt KREG_IDX(PortCnt)
95 #define kr_rcvbthqp KREG_IDX(RcvBTHQP)
96 #define kr_rcvctrl KREG_IDX(RcvCtrl)
97 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
98 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
99 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
100 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
101 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
102 #define kr_rcvpktledcnt KREG_IDX(RcvPktLEDCnt)
103 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
104 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
105 #define kr_revision KREG_IDX(Revision)
106 #define kr_scratch KREG_IDX(Scratch)
107 #define kr_sendbuffererror KREG_IDX(SendBufErr0)
108 #define kr_sendctrl KREG_IDX(SendCtrl)
109 #define kr_senddmabase KREG_IDX(SendDmaBase)
110 #define kr_senddmabufmask0 KREG_IDX(SendDmaBufMask0)
111 #define kr_senddmabufmask1 (KREG_IDX(SendDmaBufMask0) + 1)
112 #define kr_senddmabufmask2 (KREG_IDX(SendDmaBufMask0) + 2)
113 #define kr_senddmahead KREG_IDX(SendDmaHead)
114 #define kr_senddmaheadaddr KREG_IDX(SendDmaHeadAddr)
115 #define kr_senddmalengen KREG_IDX(SendDmaLenGen)
116 #define kr_senddmastatus KREG_IDX(SendDmaStatus)
117 #define kr_senddmatail KREG_IDX(SendDmaTail)
118 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
119 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
120 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
121 #define kr_sendpiosize KREG_IDX(SendBufSize)
122 #define kr_sendregbase KREG_IDX(SendRegBase)
123 #define kr_userregbase KREG_IDX(UserRegBase)
124 #define kr_xgxs_cfg KREG_IDX(XGXSCfg)
126 /* These must only be written via qib_write_kreg_ctxt() */
127 #define kr_rcvhdraddr KREG_IDX(RcvHdrAddr0)
128 #define kr_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
131 #define CREG_IDX(regname) ((QIB_7220_##regname##_OFFS - \
132 QIB_7220_LBIntCnt_OFFS) / sizeof(u64))
134 #define cr_badformat CREG_IDX(RxVersionErrCnt)
135 #define cr_erricrc CREG_IDX(RxICRCErrCnt)
136 #define cr_errlink CREG_IDX(RxLinkMalformCnt)
137 #define cr_errlpcrc CREG_IDX(RxLPCRCErrCnt)
138 #define cr_errpkey CREG_IDX(RxPKeyMismatchCnt)
139 #define cr_rcvflowctrl_err CREG_IDX(RxFlowCtrlViolCnt)
140 #define cr_err_rlen CREG_IDX(RxLenErrCnt)
141 #define cr_errslen CREG_IDX(TxLenErrCnt)
142 #define cr_errtidfull CREG_IDX(RxTIDFullErrCnt)
143 #define cr_errtidvalid CREG_IDX(RxTIDValidErrCnt)
144 #define cr_errvcrc CREG_IDX(RxVCRCErrCnt)
145 #define cr_ibstatuschange CREG_IDX(IBStatusChangeCnt)
146 #define cr_lbint CREG_IDX(LBIntCnt)
147 #define cr_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
148 #define cr_invalidslen CREG_IDX(TxMaxMinLenErrCnt)
149 #define cr_lbflowstall CREG_IDX(LBFlowStallCnt)
150 #define cr_pktrcv CREG_IDX(RxDataPktCnt)
151 #define cr_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
152 #define cr_pktsend CREG_IDX(TxDataPktCnt)
153 #define cr_pktsendflow CREG_IDX(TxFlowPktCnt)
154 #define cr_portovfl CREG_IDX(RxP0HdrEgrOvflCnt)
155 #define cr_rcvebp CREG_IDX(RxEBPCnt)
156 #define cr_rcvovfl CREG_IDX(RxBufOvflCnt)
157 #define cr_senddropped CREG_IDX(TxDroppedPktCnt)
158 #define cr_sendstall CREG_IDX(TxFlowStallCnt)
159 #define cr_sendunderrun CREG_IDX(TxUnderrunCnt)
160 #define cr_wordrcv CREG_IDX(RxDwordCnt)
161 #define cr_wordsend CREG_IDX(TxDwordCnt)
162 #define cr_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
163 #define cr_rxdroppkt CREG_IDX(RxDroppedPktCnt)
164 #define cr_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
165 #define cr_iblinkdown CREG_IDX(IBLinkDownedCnt)
166 #define cr_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
167 #define cr_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
168 #define cr_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
169 #define cr_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
170 #define cr_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
171 #define cr_rxvlerr CREG_IDX(RxVlErrCnt)
172 #define cr_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
173 #define cr_psstat CREG_IDX(PSStat)
174 #define cr_psstart CREG_IDX(PSStart)
175 #define cr_psinterval CREG_IDX(PSInterval)
176 #define cr_psrcvdatacount CREG_IDX(PSRcvDataCount)
177 #define cr_psrcvpktscount CREG_IDX(PSRcvPktsCount)
178 #define cr_psxmitdatacount CREG_IDX(PSXmitDataCount)
179 #define cr_psxmitpktscount CREG_IDX(PSXmitPktsCount)
180 #define cr_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
181 #define cr_txsdmadesc CREG_IDX(TxSDmaDescCnt)
182 #define cr_pcieretrydiag CREG_IDX(PcieRetryBufDiagQwordCnt)
184 #define SYM_RMASK(regname, fldname) ((u64) \
185 QIB_7220_##regname##_##fldname##_RMASK)
186 #define SYM_MASK(regname, fldname) ((u64) \
187 QIB_7220_##regname##_##fldname##_RMASK << \
188 QIB_7220_##regname##_##fldname##_LSB)
189 #define SYM_LSB(regname, fldname) (QIB_7220_##regname##_##fldname##_LSB)
190 #define SYM_FIELD(value, regname, fldname) ((u64) \
191 (((value) >> SYM_LSB(regname, fldname)) & \
192 SYM_RMASK(regname, fldname)))
193 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
194 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
197 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
198 /* cycle through TS1/TS2 till OK */
199 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
200 /* wait for TS1, then go on */
201 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
202 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
204 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
205 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
206 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
208 #define BLOB_7220_IBCHG 0x81
211 * We could have a single register get/put routine, that takes a group type,
212 * but this is somewhat clearer and cleaner. It also gives us some error
213 * checking. 64 bit register reads should always work, but are inefficient
214 * on opteron (the northbridge always generates 2 separate HT 32 bit reads),
215 * so we use kreg32 wherever possible. User register and counter register
216 * reads are always 32 bit reads, so only one form of those routines.
220 * qib_read_ureg32 - read 32-bit virtualized per-context register
222 * @regno: register number
223 * @ctxt: context number
225 * Return the contents of a register that is virtualized to be per context.
226 * Returns -1 on errors (not distinguishable from valid contents at
227 * runtime; we may add a separate error variable at some point).
229 static inline u32
qib_read_ureg32(const struct qib_devdata
*dd
,
230 enum qib_ureg regno
, int ctxt
)
232 if (!dd
->kregbase
|| !(dd
->flags
& QIB_PRESENT
))
236 return readl(regno
+ (u64 __iomem
*)
237 ((char __iomem
*)dd
->userbase
+
238 dd
->ureg_align
* ctxt
));
240 return readl(regno
+ (u64 __iomem
*)
242 (char __iomem
*)dd
->kregbase
+
243 dd
->ureg_align
* ctxt
));
247 * qib_write_ureg - write 32-bit virtualized per-context register
249 * @regno: register number
253 * Write the contents of a register that is virtualized to be per context.
255 static inline void qib_write_ureg(const struct qib_devdata
*dd
,
256 enum qib_ureg regno
, u64 value
, int ctxt
)
261 ubase
= (u64 __iomem
*)
262 ((char __iomem
*) dd
->userbase
+
263 dd
->ureg_align
* ctxt
);
265 ubase
= (u64 __iomem
*)
267 (char __iomem
*) dd
->kregbase
+
268 dd
->ureg_align
* ctxt
);
270 if (dd
->kregbase
&& (dd
->flags
& QIB_PRESENT
))
271 writeq(value
, &ubase
[regno
]);
275 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
276 * @dd: the qlogic_ib device
277 * @regno: the register number to write
278 * @ctxt: the context containing the register
279 * @value: the value to write
281 static inline void qib_write_kreg_ctxt(const struct qib_devdata
*dd
,
282 const u16 regno
, unsigned ctxt
,
285 qib_write_kreg(dd
, regno
+ ctxt
, value
);
288 static inline void write_7220_creg(const struct qib_devdata
*dd
,
289 u16 regno
, u64 value
)
291 if (dd
->cspec
->cregbase
&& (dd
->flags
& QIB_PRESENT
))
292 writeq(value
, &dd
->cspec
->cregbase
[regno
]);
295 static inline u64
read_7220_creg(const struct qib_devdata
*dd
, u16 regno
)
297 if (!dd
->cspec
->cregbase
|| !(dd
->flags
& QIB_PRESENT
))
299 return readq(&dd
->cspec
->cregbase
[regno
]);
302 static inline u32
read_7220_creg32(const struct qib_devdata
*dd
, u16 regno
)
304 if (!dd
->cspec
->cregbase
|| !(dd
->flags
& QIB_PRESENT
))
306 return readl(&dd
->cspec
->cregbase
[regno
]);
309 /* kr_revision bits */
310 #define QLOGIC_IB_R_EMULATORREV_MASK ((1ULL << 22) - 1)
311 #define QLOGIC_IB_R_EMULATORREV_SHIFT 40
313 /* kr_control bits */
314 #define QLOGIC_IB_C_RESET (1U << 7)
316 /* kr_intstatus, kr_intclear, kr_intmask bits */
317 #define QLOGIC_IB_I_RCVURG_MASK ((1ULL << 17) - 1)
318 #define QLOGIC_IB_I_RCVURG_SHIFT 32
319 #define QLOGIC_IB_I_RCVAVAIL_MASK ((1ULL << 17) - 1)
320 #define QLOGIC_IB_I_RCVAVAIL_SHIFT 0
321 #define QLOGIC_IB_I_SERDESTRIMDONE (1ULL << 27)
323 #define QLOGIC_IB_C_FREEZEMODE 0x00000002
324 #define QLOGIC_IB_C_LINKENABLE 0x00000004
326 #define QLOGIC_IB_I_SDMAINT 0x8000000000000000ULL
327 #define QLOGIC_IB_I_SDMADISABLED 0x4000000000000000ULL
328 #define QLOGIC_IB_I_ERROR 0x0000000080000000ULL
329 #define QLOGIC_IB_I_SPIOSENT 0x0000000040000000ULL
330 #define QLOGIC_IB_I_SPIOBUFAVAIL 0x0000000020000000ULL
331 #define QLOGIC_IB_I_GPIO 0x0000000010000000ULL
333 /* variables for sanity checking interrupt and errors */
334 #define QLOGIC_IB_I_BITSEXTANT \
335 (QLOGIC_IB_I_SDMAINT | QLOGIC_IB_I_SDMADISABLED | \
336 (QLOGIC_IB_I_RCVURG_MASK << QLOGIC_IB_I_RCVURG_SHIFT) | \
337 (QLOGIC_IB_I_RCVAVAIL_MASK << \
338 QLOGIC_IB_I_RCVAVAIL_SHIFT) | \
339 QLOGIC_IB_I_ERROR | QLOGIC_IB_I_SPIOSENT | \
340 QLOGIC_IB_I_SPIOBUFAVAIL | QLOGIC_IB_I_GPIO | \
341 QLOGIC_IB_I_SERDESTRIMDONE)
343 #define IB_HWE_BITSEXTANT \
344 (HWE_MASK(RXEMemParityErr) | \
345 HWE_MASK(TXEMemParityErr) | \
346 (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK << \
347 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT) | \
348 QLOGIC_IB_HWE_PCIE1PLLFAILED | \
349 QLOGIC_IB_HWE_PCIE0PLLFAILED | \
350 QLOGIC_IB_HWE_PCIEPOISONEDTLP | \
351 QLOGIC_IB_HWE_PCIECPLTIMEOUT | \
352 QLOGIC_IB_HWE_PCIEBUSPARITYXTLH | \
353 QLOGIC_IB_HWE_PCIEBUSPARITYXADM | \
354 QLOGIC_IB_HWE_PCIEBUSPARITYRADM | \
355 HWE_MASK(PowerOnBISTFailed) | \
356 QLOGIC_IB_HWE_COREPLL_FBSLIP | \
357 QLOGIC_IB_HWE_COREPLL_RFSLIP | \
358 QLOGIC_IB_HWE_SERDESPLLFAILED | \
359 HWE_MASK(IBCBusToSPCParityErr) | \
360 HWE_MASK(IBCBusFromSPCParityErr) | \
361 QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR | \
362 QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR | \
363 QLOGIC_IB_HWE_SDMAMEMREADERR | \
364 QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED | \
365 QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT | \
366 QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT | \
367 QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT | \
368 QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT | \
369 QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR | \
370 QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR | \
371 QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR | \
372 QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR)
374 #define IB_E_BITSEXTANT \
375 (ERR_MASK(RcvFormatErr) | ERR_MASK(RcvVCRCErr) | \
376 ERR_MASK(RcvICRCErr) | ERR_MASK(RcvMinPktLenErr) | \
377 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvLongPktLenErr) | \
378 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvUnexpectedCharErr) | \
379 ERR_MASK(RcvUnsupportedVLErr) | ERR_MASK(RcvEBPErr) | \
380 ERR_MASK(RcvIBFlowErr) | ERR_MASK(RcvBadVersionErr) | \
381 ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr) | \
382 ERR_MASK(RcvBadTidErr) | ERR_MASK(RcvHdrLenErr) | \
383 ERR_MASK(RcvHdrErr) | ERR_MASK(RcvIBLostLinkErr) | \
384 ERR_MASK(SendSpecialTriggerErr) | \
385 ERR_MASK(SDmaDisabledErr) | ERR_MASK(SendMinPktLenErr) | \
386 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnderRunErr) | \
387 ERR_MASK(SendPktLenErr) | ERR_MASK(SendDroppedSmpPktErr) | \
388 ERR_MASK(SendDroppedDataPktErr) | \
389 ERR_MASK(SendPioArmLaunchErr) | \
390 ERR_MASK(SendUnexpectedPktNumErr) | \
391 ERR_MASK(SendUnsupportedVLErr) | ERR_MASK(SendBufMisuseErr) | \
392 ERR_MASK(SDmaGenMismatchErr) | ERR_MASK(SDmaOutOfBoundErr) | \
393 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
394 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
395 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
396 ERR_MASK(SDmaUnexpDataErr) | \
397 ERR_MASK(IBStatusChanged) | ERR_MASK(InvalidAddrErr) | \
398 ERR_MASK(ResetNegated) | ERR_MASK(HardwareErr) | \
399 ERR_MASK(SDmaDescAddrMisalignErr) | \
400 ERR_MASK(InvalidEEPCmd))
402 /* kr_hwerrclear, kr_hwerrmask, kr_hwerrstatus, bits */
403 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK 0x00000000000000ffULL
404 #define QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT 0
405 #define QLOGIC_IB_HWE_PCIEPOISONEDTLP 0x0000000010000000ULL
406 #define QLOGIC_IB_HWE_PCIECPLTIMEOUT 0x0000000020000000ULL
407 #define QLOGIC_IB_HWE_PCIEBUSPARITYXTLH 0x0000000040000000ULL
408 #define QLOGIC_IB_HWE_PCIEBUSPARITYXADM 0x0000000080000000ULL
409 #define QLOGIC_IB_HWE_PCIEBUSPARITYRADM 0x0000000100000000ULL
410 #define QLOGIC_IB_HWE_COREPLL_FBSLIP 0x0080000000000000ULL
411 #define QLOGIC_IB_HWE_COREPLL_RFSLIP 0x0100000000000000ULL
412 #define QLOGIC_IB_HWE_PCIE1PLLFAILED 0x0400000000000000ULL
413 #define QLOGIC_IB_HWE_PCIE0PLLFAILED 0x0800000000000000ULL
414 #define QLOGIC_IB_HWE_SERDESPLLFAILED 0x1000000000000000ULL
415 /* specific to this chip */
416 #define QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR 0x0000000000000040ULL
417 #define QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR 0x0000000000000080ULL
418 #define QLOGIC_IB_HWE_SDMAMEMREADERR 0x0000000010000000ULL
419 #define QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED 0x2000000000000000ULL
420 #define QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT 0x0100000000000000ULL
421 #define QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT 0x0200000000000000ULL
422 #define QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT 0x0400000000000000ULL
423 #define QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT 0x0800000000000000ULL
424 #define QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR 0x0000008000000000ULL
425 #define QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR 0x0000004000000000ULL
426 #define QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR 0x0000001000000000ULL
427 #define QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR 0x0000002000000000ULL
429 #define IBA7220_IBCC_LINKCMD_SHIFT 19
431 /* kr_ibcddrctrl bits */
432 #define IBA7220_IBC_DLIDLMC_MASK 0xFFFFFFFFUL
433 #define IBA7220_IBC_DLIDLMC_SHIFT 32
435 #define IBA7220_IBC_HRTBT_MASK (SYM_RMASK(IBCDDRCtrl, HRTBT_AUTO) | \
436 SYM_RMASK(IBCDDRCtrl, HRTBT_ENB))
437 #define IBA7220_IBC_HRTBT_SHIFT SYM_LSB(IBCDDRCtrl, HRTBT_ENB)
439 #define IBA7220_IBC_LANE_REV_SUPPORTED (1<<8)
440 #define IBA7220_IBC_LREV_MASK 1
441 #define IBA7220_IBC_LREV_SHIFT 8
442 #define IBA7220_IBC_RXPOL_MASK 1
443 #define IBA7220_IBC_RXPOL_SHIFT 7
444 #define IBA7220_IBC_WIDTH_SHIFT 5
445 #define IBA7220_IBC_WIDTH_MASK 0x3
446 #define IBA7220_IBC_WIDTH_1X_ONLY (0 << IBA7220_IBC_WIDTH_SHIFT)
447 #define IBA7220_IBC_WIDTH_4X_ONLY (1 << IBA7220_IBC_WIDTH_SHIFT)
448 #define IBA7220_IBC_WIDTH_AUTONEG (2 << IBA7220_IBC_WIDTH_SHIFT)
449 #define IBA7220_IBC_SPEED_AUTONEG (1 << 1)
450 #define IBA7220_IBC_SPEED_SDR (1 << 2)
451 #define IBA7220_IBC_SPEED_DDR (1 << 3)
452 #define IBA7220_IBC_SPEED_AUTONEG_MASK (0x7 << 1)
453 #define IBA7220_IBC_IBTA_1_2_MASK (1)
455 /* kr_ibcddrstatus */
456 /* link latency shift is 0, don't bother defining */
457 #define IBA7220_DDRSTAT_LINKLAT_MASK 0x3ffffff
459 /* kr_extstatus bits */
460 #define QLOGIC_IB_EXTS_FREQSEL 0x2
461 #define QLOGIC_IB_EXTS_SERDESSEL 0x4
462 #define QLOGIC_IB_EXTS_MEMBIST_ENDTEST 0x0000000000004000
463 #define QLOGIC_IB_EXTS_MEMBIST_DISABLED 0x0000000000008000
465 /* kr_xgxsconfig bits */
466 #define QLOGIC_IB_XGXS_RESET 0x5ULL
467 #define QLOGIC_IB_XGXS_FC_SAFE (1ULL << 63)
469 /* kr_rcvpktledcnt */
470 #define IBA7220_LEDBLINK_ON_SHIFT 32 /* 4ns period on after packet */
471 #define IBA7220_LEDBLINK_OFF_SHIFT 0 /* 4ns period off before next on */
473 #define _QIB_GPIO_SDA_NUM 1
474 #define _QIB_GPIO_SCL_NUM 0
475 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7220 cards. */
476 #define QIB_TWSI_TEMP_DEV 0x98
478 /* HW counter clock is at 4nsec */
479 #define QIB_7220_PSXMITWAIT_CHECK_RATE 4000
481 #define IBA7220_R_INTRAVAIL_SHIFT 17
482 #define IBA7220_R_PKEY_DIS_SHIFT 34
483 #define IBA7220_R_TAILUPD_SHIFT 35
484 #define IBA7220_R_CTXTCFG_SHIFT 36
486 #define IBA7220_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
489 * the size bits give us 2^N, in KB units. 0 marks as invalid,
490 * and 7 is reserved. We currently use only 2KB and 4KB
492 #define IBA7220_TID_SZ_SHIFT 37 /* shift to 3bit size selector */
493 #define IBA7220_TID_SZ_2K (1UL << IBA7220_TID_SZ_SHIFT) /* 2KB */
494 #define IBA7220_TID_SZ_4K (2UL << IBA7220_TID_SZ_SHIFT) /* 4KB */
495 #define IBA7220_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
496 #define PBC_7220_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
497 #define PBC_7220_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
499 #define AUTONEG_TRIES 5 /* sequential retries to negotiate DDR */
501 /* packet rate matching delay multiplier */
502 static u8 rate_to_delay
[2][2] = {
508 static u8 ib_rate_to_delay
[IB_RATE_120_GBPS
+ 1] = {
509 [IB_RATE_2_5_GBPS
] = 8,
510 [IB_RATE_5_GBPS
] = 4,
511 [IB_RATE_10_GBPS
] = 2,
512 [IB_RATE_20_GBPS
] = 1
515 #define IBA7220_LINKSPEED_SHIFT SYM_LSB(IBCStatus, LinkSpeedActive)
516 #define IBA7220_LINKWIDTH_SHIFT SYM_LSB(IBCStatus, LinkWidthActive)
518 /* link training states, from IBC */
519 #define IB_7220_LT_STATE_DISABLED 0x00
520 #define IB_7220_LT_STATE_LINKUP 0x01
521 #define IB_7220_LT_STATE_POLLACTIVE 0x02
522 #define IB_7220_LT_STATE_POLLQUIET 0x03
523 #define IB_7220_LT_STATE_SLEEPDELAY 0x04
524 #define IB_7220_LT_STATE_SLEEPQUIET 0x05
525 #define IB_7220_LT_STATE_CFGDEBOUNCE 0x08
526 #define IB_7220_LT_STATE_CFGRCVFCFG 0x09
527 #define IB_7220_LT_STATE_CFGWAITRMT 0x0a
528 #define IB_7220_LT_STATE_CFGIDLE 0x0b
529 #define IB_7220_LT_STATE_RECOVERRETRAIN 0x0c
530 #define IB_7220_LT_STATE_RECOVERWAITRMT 0x0e
531 #define IB_7220_LT_STATE_RECOVERIDLE 0x0f
533 /* link state machine states from IBC */
534 #define IB_7220_L_STATE_DOWN 0x0
535 #define IB_7220_L_STATE_INIT 0x1
536 #define IB_7220_L_STATE_ARM 0x2
537 #define IB_7220_L_STATE_ACTIVE 0x3
538 #define IB_7220_L_STATE_ACT_DEFER 0x4
540 static const u8 qib_7220_physportstate
[0x20] = {
541 [IB_7220_LT_STATE_DISABLED
] = IB_PHYSPORTSTATE_DISABLED
,
542 [IB_7220_LT_STATE_LINKUP
] = IB_PHYSPORTSTATE_LINKUP
,
543 [IB_7220_LT_STATE_POLLACTIVE
] = IB_PHYSPORTSTATE_POLL
,
544 [IB_7220_LT_STATE_POLLQUIET
] = IB_PHYSPORTSTATE_POLL
,
545 [IB_7220_LT_STATE_SLEEPDELAY
] = IB_PHYSPORTSTATE_SLEEP
,
546 [IB_7220_LT_STATE_SLEEPQUIET
] = IB_PHYSPORTSTATE_SLEEP
,
547 [IB_7220_LT_STATE_CFGDEBOUNCE
] =
548 IB_PHYSPORTSTATE_CFG_TRAIN
,
549 [IB_7220_LT_STATE_CFGRCVFCFG
] =
550 IB_PHYSPORTSTATE_CFG_TRAIN
,
551 [IB_7220_LT_STATE_CFGWAITRMT
] =
552 IB_PHYSPORTSTATE_CFG_TRAIN
,
553 [IB_7220_LT_STATE_CFGIDLE
] = IB_PHYSPORTSTATE_CFG_TRAIN
,
554 [IB_7220_LT_STATE_RECOVERRETRAIN
] =
555 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
556 [IB_7220_LT_STATE_RECOVERWAITRMT
] =
557 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
558 [IB_7220_LT_STATE_RECOVERIDLE
] =
559 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
,
560 [0x10] = IB_PHYSPORTSTATE_CFG_TRAIN
,
561 [0x11] = IB_PHYSPORTSTATE_CFG_TRAIN
,
562 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN
,
563 [0x13] = IB_PHYSPORTSTATE_CFG_TRAIN
,
564 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN
,
565 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN
,
566 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN
,
567 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
570 int qib_special_trigger
;
571 module_param_named(special_trigger
, qib_special_trigger
, int, S_IRUGO
);
572 MODULE_PARM_DESC(special_trigger
, "Enable SpecialTrigger arm/launch");
574 #define IBCBUSFRSPCPARITYERR HWE_MASK(IBCBusFromSPCParityErr)
575 #define IBCBUSTOSPCPARITYERR HWE_MASK(IBCBusToSPCParityErr)
577 #define SYM_MASK_BIT(regname, fldname, bit) ((u64) \
578 (1ULL << (SYM_LSB(regname, fldname) + (bit))))
580 #define TXEMEMPARITYERR_PIOBUF \
581 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 0)
582 #define TXEMEMPARITYERR_PIOPBC \
583 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 1)
584 #define TXEMEMPARITYERR_PIOLAUNCHFIFO \
585 SYM_MASK_BIT(HwErrMask, TXEMemParityErrMask, 2)
587 #define RXEMEMPARITYERR_RCVBUF \
588 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 0)
589 #define RXEMEMPARITYERR_LOOKUPQ \
590 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 1)
591 #define RXEMEMPARITYERR_EXPTID \
592 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 2)
593 #define RXEMEMPARITYERR_EAGERTID \
594 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 3)
595 #define RXEMEMPARITYERR_FLAGBUF \
596 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 4)
597 #define RXEMEMPARITYERR_DATAINFO \
598 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 5)
599 #define RXEMEMPARITYERR_HDRINFO \
600 SYM_MASK_BIT(HwErrMask, RXEMemParityErrMask, 6)
602 /* 7220 specific hardware errors... */
603 static const struct qib_hwerror_msgs qib_7220_hwerror_msgs
[] = {
604 /* generic hardware errors */
605 QLOGIC_IB_HWE_MSG(IBCBUSFRSPCPARITYERR
, "QIB2IB Parity"),
606 QLOGIC_IB_HWE_MSG(IBCBUSTOSPCPARITYERR
, "IB2QIB Parity"),
608 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOBUF
,
609 "TXE PIOBUF Memory Parity"),
610 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOPBC
,
611 "TXE PIOPBC Memory Parity"),
612 QLOGIC_IB_HWE_MSG(TXEMEMPARITYERR_PIOLAUNCHFIFO
,
613 "TXE PIOLAUNCHFIFO Memory Parity"),
615 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_RCVBUF
,
616 "RXE RCVBUF Memory Parity"),
617 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_LOOKUPQ
,
618 "RXE LOOKUPQ Memory Parity"),
619 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EAGERTID
,
620 "RXE EAGERTID Memory Parity"),
621 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_EXPTID
,
622 "RXE EXPTID Memory Parity"),
623 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_FLAGBUF
,
624 "RXE FLAGBUF Memory Parity"),
625 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_DATAINFO
,
626 "RXE DATAINFO Memory Parity"),
627 QLOGIC_IB_HWE_MSG(RXEMEMPARITYERR_HDRINFO
,
628 "RXE HDRINFO Memory Parity"),
630 /* chip-specific hardware errors */
631 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEPOISONEDTLP
,
632 "PCIe Poisoned TLP"),
633 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLTIMEOUT
,
634 "PCIe completion timeout"),
636 * In practice, it's unlikely wthat we'll see PCIe PLL, or bus
637 * parity or memory parity error failures, because most likely we
638 * won't be able to talk to the core of the chip. Nonetheless, we
639 * might see them, if they are in parts of the PCIe core that aren't
642 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE1PLLFAILED
,
644 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE0PLLFAILED
,
646 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXTLH
,
647 "PCIe XTLH core parity"),
648 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYXADM
,
649 "PCIe ADM TX core parity"),
650 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIEBUSPARITYRADM
,
651 "PCIe ADM RX core parity"),
652 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SERDESPLLFAILED
,
654 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLDATAQUEUEERR
,
655 "PCIe cpl header queue"),
656 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIECPLHDRQUEUEERR
,
657 "PCIe cpl data queue"),
658 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_SDMAMEMREADERR
,
659 "Send DMA memory read"),
660 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_CLK_UC_PLLNOTLOCKED
,
661 "uC PLL clock not locked"),
662 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ0PCLKNOTDETECT
,
663 "PCIe serdes Q0 no clock"),
664 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ1PCLKNOTDETECT
,
665 "PCIe serdes Q1 no clock"),
666 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ2PCLKNOTDETECT
,
667 "PCIe serdes Q2 no clock"),
668 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIESERDESQ3PCLKNOTDETECT
,
669 "PCIe serdes Q3 no clock"),
670 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_DDSRXEQMEMORYPARITYERR
,
671 "DDS RXEQ memory parity"),
672 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR
,
673 "IB uC memory parity"),
674 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT0MEMORYPARITYERR
,
675 "PCIe uC oct0 memory parity"),
676 QLOGIC_IB_HWE_MSG(QLOGIC_IB_HWE_PCIE_UC_OCT1MEMORYPARITYERR
,
677 "PCIe uC oct1 memory parity"),
680 #define RXE_PARITY (RXEMEMPARITYERR_EAGERTID|RXEMEMPARITYERR_EXPTID)
682 #define QLOGIC_IB_E_PKTERRS (\
683 ERR_MASK(SendPktLenErr) | \
684 ERR_MASK(SendDroppedDataPktErr) | \
685 ERR_MASK(RcvVCRCErr) | \
686 ERR_MASK(RcvICRCErr) | \
687 ERR_MASK(RcvShortPktLenErr) | \
690 /* Convenience for decoding Send DMA errors */
691 #define QLOGIC_IB_E_SDMAERRS ( \
692 ERR_MASK(SDmaGenMismatchErr) | \
693 ERR_MASK(SDmaOutOfBoundErr) | \
694 ERR_MASK(SDmaTailOutOfBoundErr) | ERR_MASK(SDmaBaseErr) | \
695 ERR_MASK(SDma1stDescErr) | ERR_MASK(SDmaRpyTagErr) | \
696 ERR_MASK(SDmaDwEnErr) | ERR_MASK(SDmaMissingDwErr) | \
697 ERR_MASK(SDmaUnexpDataErr) | \
698 ERR_MASK(SDmaDescAddrMisalignErr) | \
699 ERR_MASK(SDmaDisabledErr) | \
700 ERR_MASK(SendBufMisuseErr))
702 /* These are all rcv-related errors which we want to count for stats */
703 #define E_SUM_PKTERRS \
704 (ERR_MASK(RcvHdrLenErr) | ERR_MASK(RcvBadTidErr) | \
705 ERR_MASK(RcvBadVersionErr) | ERR_MASK(RcvHdrErr) | \
706 ERR_MASK(RcvLongPktLenErr) | ERR_MASK(RcvShortPktLenErr) | \
707 ERR_MASK(RcvMaxPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
708 ERR_MASK(RcvFormatErr) | ERR_MASK(RcvUnsupportedVLErr) | \
709 ERR_MASK(RcvUnexpectedCharErr) | ERR_MASK(RcvEBPErr))
711 /* These are all send-related errors which we want to count for stats */
713 (ERR_MASK(SendPioArmLaunchErr) | ERR_MASK(SendUnexpectedPktNumErr) | \
714 ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
715 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendUnsupportedVLErr) | \
716 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
717 ERR_MASK(InvalidAddrErr))
720 * this is similar to E_SUM_ERRS, but can't ignore armlaunch, don't ignore
721 * errors not related to freeze and cancelling buffers. Can't ignore
722 * armlaunch because could get more while still cleaning up, and need
723 * to cancel those as they happen.
725 #define E_SPKT_ERRS_IGNORE \
726 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
727 ERR_MASK(SendMaxPktLenErr) | ERR_MASK(SendMinPktLenErr) | \
728 ERR_MASK(SendPktLenErr))
731 * these are errors that can occur when the link changes state while
732 * a packet is being sent or received. This doesn't cover things
733 * like EBP or VCRC that can be the result of a sending having the
734 * link change state, so we receive a "known bad" packet.
736 #define E_SUM_LINK_PKTERRS \
737 (ERR_MASK(SendDroppedDataPktErr) | ERR_MASK(SendDroppedSmpPktErr) | \
738 ERR_MASK(SendMinPktLenErr) | ERR_MASK(SendPktLenErr) | \
739 ERR_MASK(RcvShortPktLenErr) | ERR_MASK(RcvMinPktLenErr) | \
740 ERR_MASK(RcvUnexpectedCharErr))
742 static void autoneg_7220_work(struct work_struct
*);
743 static u32 __iomem
*qib_7220_getsendbuf(struct qib_pportdata
*, u64
, u32
*);
746 * Called when we might have an error that is specific to a particular
747 * PIO buffer, and may need to cancel that buffer, so it can be re-used.
748 * because we don't need to force the update of pioavail.
750 static void qib_disarm_7220_senderrbufs(struct qib_pportdata
*ppd
)
752 unsigned long sbuf
[3];
753 struct qib_devdata
*dd
= ppd
->dd
;
756 * It's possible that sendbuffererror could have bits set; might
757 * have already done this as a result of hardware error handling.
759 /* read these before writing errorclear */
760 sbuf
[0] = qib_read_kreg64(dd
, kr_sendbuffererror
);
761 sbuf
[1] = qib_read_kreg64(dd
, kr_sendbuffererror
+ 1);
762 sbuf
[2] = qib_read_kreg64(dd
, kr_sendbuffererror
+ 2);
764 if (sbuf
[0] || sbuf
[1] || sbuf
[2])
765 qib_disarm_piobufs_set(dd
, sbuf
,
766 dd
->piobcnt2k
+ dd
->piobcnt4k
);
769 static void qib_7220_txe_recover(struct qib_devdata
*dd
)
771 qib_devinfo(dd
->pcidev
, "Recovering from TXE PIO parity error\n");
772 qib_disarm_7220_senderrbufs(dd
->pport
);
776 * This is called with interrupts disabled and sdma_lock held.
778 static void qib_7220_sdma_sendctrl(struct qib_pportdata
*ppd
, unsigned op
)
780 struct qib_devdata
*dd
= ppd
->dd
;
781 u64 set_sendctrl
= 0;
782 u64 clr_sendctrl
= 0;
784 if (op
& QIB_SDMA_SENDCTRL_OP_ENABLE
)
785 set_sendctrl
|= SYM_MASK(SendCtrl
, SDmaEnable
);
787 clr_sendctrl
|= SYM_MASK(SendCtrl
, SDmaEnable
);
789 if (op
& QIB_SDMA_SENDCTRL_OP_INTENABLE
)
790 set_sendctrl
|= SYM_MASK(SendCtrl
, SDmaIntEnable
);
792 clr_sendctrl
|= SYM_MASK(SendCtrl
, SDmaIntEnable
);
794 if (op
& QIB_SDMA_SENDCTRL_OP_HALT
)
795 set_sendctrl
|= SYM_MASK(SendCtrl
, SDmaHalt
);
797 clr_sendctrl
|= SYM_MASK(SendCtrl
, SDmaHalt
);
799 spin_lock(&dd
->sendctrl_lock
);
801 dd
->sendctrl
|= set_sendctrl
;
802 dd
->sendctrl
&= ~clr_sendctrl
;
804 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
);
805 qib_write_kreg(dd
, kr_scratch
, 0);
807 spin_unlock(&dd
->sendctrl_lock
);
810 static void qib_decode_7220_sdma_errs(struct qib_pportdata
*ppd
,
811 u64 err
, char *buf
, size_t blen
)
813 static const struct {
817 { ERR_MASK(SDmaGenMismatchErr
),
819 { ERR_MASK(SDmaOutOfBoundErr
),
821 { ERR_MASK(SDmaTailOutOfBoundErr
),
822 "SDmaTailOutOfBound" },
823 { ERR_MASK(SDmaBaseErr
),
825 { ERR_MASK(SDma1stDescErr
),
827 { ERR_MASK(SDmaRpyTagErr
),
829 { ERR_MASK(SDmaDwEnErr
),
831 { ERR_MASK(SDmaMissingDwErr
),
833 { ERR_MASK(SDmaUnexpDataErr
),
835 { ERR_MASK(SDmaDescAddrMisalignErr
),
836 "SDmaDescAddrMisalign" },
837 { ERR_MASK(SendBufMisuseErr
),
839 { ERR_MASK(SDmaDisabledErr
),
845 for (i
= 0; i
< ARRAY_SIZE(errs
); i
++) {
846 if (err
& errs
[i
].err
)
847 bidx
+= scnprintf(buf
+ bidx
, blen
- bidx
,
853 * This is called as part of link down clean up so disarm and flush
854 * all send buffers so that SMP packets can be sent.
856 static void qib_7220_sdma_hw_clean_up(struct qib_pportdata
*ppd
)
858 /* This will trigger the Abort interrupt */
859 sendctrl_7220_mod(ppd
, QIB_SENDCTRL_DISARM_ALL
| QIB_SENDCTRL_FLUSH
|
860 QIB_SENDCTRL_AVAIL_BLIP
);
861 ppd
->dd
->upd_pio_shadow
= 1; /* update our idea of what's busy */
864 static void qib_sdma_7220_setlengen(struct qib_pportdata
*ppd
)
867 * Set SendDmaLenGen and clear and set
868 * the MSB of the generation count to enable generation checking
869 * and load the internal generation counter.
871 qib_write_kreg(ppd
->dd
, kr_senddmalengen
, ppd
->sdma_descq_cnt
);
872 qib_write_kreg(ppd
->dd
, kr_senddmalengen
,
873 ppd
->sdma_descq_cnt
|
874 (1ULL << QIB_7220_SendDmaLenGen_Generation_MSB
));
877 static void qib_7220_sdma_hw_start_up(struct qib_pportdata
*ppd
)
879 qib_sdma_7220_setlengen(ppd
);
880 qib_sdma_update_7220_tail(ppd
, 0); /* Set SendDmaTail */
881 ppd
->sdma_head_dma
[0] = 0;
884 #define DISABLES_SDMA ( \
885 ERR_MASK(SDmaDisabledErr) | \
886 ERR_MASK(SDmaBaseErr) | \
887 ERR_MASK(SDmaTailOutOfBoundErr) | \
888 ERR_MASK(SDmaOutOfBoundErr) | \
889 ERR_MASK(SDma1stDescErr) | \
890 ERR_MASK(SDmaRpyTagErr) | \
891 ERR_MASK(SDmaGenMismatchErr) | \
892 ERR_MASK(SDmaDescAddrMisalignErr) | \
893 ERR_MASK(SDmaMissingDwErr) | \
894 ERR_MASK(SDmaDwEnErr))
896 static void sdma_7220_errors(struct qib_pportdata
*ppd
, u64 errs
)
899 struct qib_devdata
*dd
= ppd
->dd
;
902 errs
&= QLOGIC_IB_E_SDMAERRS
;
904 msg
= dd
->cspec
->sdmamsgbuf
;
905 qib_decode_7220_sdma_errs(ppd
, errs
, msg
,
906 sizeof(dd
->cspec
->sdmamsgbuf
));
907 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
909 if (errs
& ERR_MASK(SendBufMisuseErr
)) {
910 unsigned long sbuf
[3];
912 sbuf
[0] = qib_read_kreg64(dd
, kr_sendbuffererror
);
913 sbuf
[1] = qib_read_kreg64(dd
, kr_sendbuffererror
+ 1);
914 sbuf
[2] = qib_read_kreg64(dd
, kr_sendbuffererror
+ 2);
917 "IB%u:%u SendBufMisuse: %04lx %016lx %016lx\n",
918 ppd
->dd
->unit
, ppd
->port
, sbuf
[2], sbuf
[1],
922 if (errs
& ERR_MASK(SDmaUnexpDataErr
))
923 qib_dev_err(dd
, "IB%u:%u SDmaUnexpData\n", ppd
->dd
->unit
,
926 switch (ppd
->sdma_state
.current_state
) {
927 case qib_sdma_state_s00_hw_down
:
928 /* not expecting any interrupts */
931 case qib_sdma_state_s10_hw_start_up_wait
:
932 /* handled in intr path */
935 case qib_sdma_state_s20_idle
:
936 /* not expecting any interrupts */
939 case qib_sdma_state_s30_sw_clean_up_wait
:
940 /* not expecting any interrupts */
943 case qib_sdma_state_s40_hw_clean_up_wait
:
944 if (errs
& ERR_MASK(SDmaDisabledErr
))
945 __qib_sdma_process_event(ppd
,
946 qib_sdma_event_e50_hw_cleaned
);
949 case qib_sdma_state_s50_hw_halt_wait
:
950 /* handled in intr path */
953 case qib_sdma_state_s99_running
:
954 if (errs
& DISABLES_SDMA
)
955 __qib_sdma_process_event(ppd
,
956 qib_sdma_event_e7220_err_halted
);
960 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
964 * Decode the error status into strings, deciding whether to always
965 * print * it or not depending on "normal packet errors" vs everything
966 * else. Return 1 if "real" errors, otherwise 0 if only packet
967 * errors, so caller can decide what to print with the string.
969 static int qib_decode_7220_err(struct qib_devdata
*dd
, char *buf
, size_t blen
,
975 if (err
& QLOGIC_IB_E_PKTERRS
) {
976 if (!(err
& ~QLOGIC_IB_E_PKTERRS
))
978 if ((err
& ERR_MASK(RcvICRCErr
)) &&
979 !(err
& (ERR_MASK(RcvVCRCErr
) | ERR_MASK(RcvEBPErr
))))
980 strlcat(buf
, "CRC ", blen
);
984 if (err
& ERR_MASK(RcvHdrLenErr
))
985 strlcat(buf
, "rhdrlen ", blen
);
986 if (err
& ERR_MASK(RcvBadTidErr
))
987 strlcat(buf
, "rbadtid ", blen
);
988 if (err
& ERR_MASK(RcvBadVersionErr
))
989 strlcat(buf
, "rbadversion ", blen
);
990 if (err
& ERR_MASK(RcvHdrErr
))
991 strlcat(buf
, "rhdr ", blen
);
992 if (err
& ERR_MASK(SendSpecialTriggerErr
))
993 strlcat(buf
, "sendspecialtrigger ", blen
);
994 if (err
& ERR_MASK(RcvLongPktLenErr
))
995 strlcat(buf
, "rlongpktlen ", blen
);
996 if (err
& ERR_MASK(RcvMaxPktLenErr
))
997 strlcat(buf
, "rmaxpktlen ", blen
);
998 if (err
& ERR_MASK(RcvMinPktLenErr
))
999 strlcat(buf
, "rminpktlen ", blen
);
1000 if (err
& ERR_MASK(SendMinPktLenErr
))
1001 strlcat(buf
, "sminpktlen ", blen
);
1002 if (err
& ERR_MASK(RcvFormatErr
))
1003 strlcat(buf
, "rformaterr ", blen
);
1004 if (err
& ERR_MASK(RcvUnsupportedVLErr
))
1005 strlcat(buf
, "runsupvl ", blen
);
1006 if (err
& ERR_MASK(RcvUnexpectedCharErr
))
1007 strlcat(buf
, "runexpchar ", blen
);
1008 if (err
& ERR_MASK(RcvIBFlowErr
))
1009 strlcat(buf
, "ribflow ", blen
);
1010 if (err
& ERR_MASK(SendUnderRunErr
))
1011 strlcat(buf
, "sunderrun ", blen
);
1012 if (err
& ERR_MASK(SendPioArmLaunchErr
))
1013 strlcat(buf
, "spioarmlaunch ", blen
);
1014 if (err
& ERR_MASK(SendUnexpectedPktNumErr
))
1015 strlcat(buf
, "sunexperrpktnum ", blen
);
1016 if (err
& ERR_MASK(SendDroppedSmpPktErr
))
1017 strlcat(buf
, "sdroppedsmppkt ", blen
);
1018 if (err
& ERR_MASK(SendMaxPktLenErr
))
1019 strlcat(buf
, "smaxpktlen ", blen
);
1020 if (err
& ERR_MASK(SendUnsupportedVLErr
))
1021 strlcat(buf
, "sunsupVL ", blen
);
1022 if (err
& ERR_MASK(InvalidAddrErr
))
1023 strlcat(buf
, "invalidaddr ", blen
);
1024 if (err
& ERR_MASK(RcvEgrFullErr
))
1025 strlcat(buf
, "rcvegrfull ", blen
);
1026 if (err
& ERR_MASK(RcvHdrFullErr
))
1027 strlcat(buf
, "rcvhdrfull ", blen
);
1028 if (err
& ERR_MASK(IBStatusChanged
))
1029 strlcat(buf
, "ibcstatuschg ", blen
);
1030 if (err
& ERR_MASK(RcvIBLostLinkErr
))
1031 strlcat(buf
, "riblostlink ", blen
);
1032 if (err
& ERR_MASK(HardwareErr
))
1033 strlcat(buf
, "hardware ", blen
);
1034 if (err
& ERR_MASK(ResetNegated
))
1035 strlcat(buf
, "reset ", blen
);
1036 if (err
& QLOGIC_IB_E_SDMAERRS
)
1037 qib_decode_7220_sdma_errs(dd
->pport
, err
, buf
, blen
);
1038 if (err
& ERR_MASK(InvalidEEPCmd
))
1039 strlcat(buf
, "invalideepromcmd ", blen
);
1044 static void reenable_7220_chase(unsigned long opaque
)
1046 struct qib_pportdata
*ppd
= (struct qib_pportdata
*)opaque
;
1048 ppd
->cpspec
->chase_timer
.expires
= 0;
1049 qib_set_ib_7220_lstate(ppd
, QLOGIC_IB_IBCC_LINKCMD_DOWN
,
1050 QLOGIC_IB_IBCC_LINKINITCMD_POLL
);
1053 static void handle_7220_chase(struct qib_pportdata
*ppd
, u64 ibcst
)
1058 ibclt
= (u8
)SYM_FIELD(ibcst
, IBCStatus
, LinkTrainingState
);
1061 * Detect and handle the state chase issue, where we can
1062 * get stuck if we are unlucky on timing on both sides of
1063 * the link. If we are, we disable, set a timer, and
1067 case IB_7220_LT_STATE_CFGRCVFCFG
:
1068 case IB_7220_LT_STATE_CFGWAITRMT
:
1069 case IB_7220_LT_STATE_TXREVLANES
:
1070 case IB_7220_LT_STATE_CFGENH
:
1072 if (ppd
->cpspec
->chase_end
&&
1073 time_after(tnow
, ppd
->cpspec
->chase_end
)) {
1074 ppd
->cpspec
->chase_end
= 0;
1075 qib_set_ib_7220_lstate(ppd
,
1076 QLOGIC_IB_IBCC_LINKCMD_DOWN
,
1077 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
1078 ppd
->cpspec
->chase_timer
.expires
= jiffies
+
1080 add_timer(&ppd
->cpspec
->chase_timer
);
1081 } else if (!ppd
->cpspec
->chase_end
)
1082 ppd
->cpspec
->chase_end
= tnow
+ QIB_CHASE_TIME
;
1086 ppd
->cpspec
->chase_end
= 0;
1091 static void handle_7220_errors(struct qib_devdata
*dd
, u64 errs
)
1094 u64 ignore_this_time
= 0;
1097 struct qib_pportdata
*ppd
= dd
->pport
;
1100 /* don't report errors that are masked */
1101 errs
&= dd
->cspec
->errormask
;
1102 msg
= dd
->cspec
->emsgbuf
;
1104 /* do these first, they are most important */
1105 if (errs
& ERR_MASK(HardwareErr
))
1106 qib_7220_handle_hwerrors(dd
, msg
, sizeof(dd
->cspec
->emsgbuf
));
1108 for (log_idx
= 0; log_idx
< QIB_EEP_LOG_CNT
; ++log_idx
)
1109 if (errs
& dd
->eep_st_masks
[log_idx
].errs_to_log
)
1110 qib_inc_eeprom_err(dd
, log_idx
, 1);
1112 if (errs
& QLOGIC_IB_E_SDMAERRS
)
1113 sdma_7220_errors(ppd
, errs
);
1115 if (errs
& ~IB_E_BITSEXTANT
)
1117 "error interrupt with unknown errors %llx set\n",
1118 (unsigned long long) (errs
& ~IB_E_BITSEXTANT
));
1120 if (errs
& E_SUM_ERRS
) {
1121 qib_disarm_7220_senderrbufs(ppd
);
1122 if ((errs
& E_SUM_LINK_PKTERRS
) &&
1123 !(ppd
->lflags
& QIBL_LINKACTIVE
)) {
1125 * This can happen when trying to bring the link
1126 * up, but the IB link changes state at the "wrong"
1127 * time. The IB logic then complains that the packet
1128 * isn't valid. We don't want to confuse people, so
1129 * we just don't print them, except at debug
1131 ignore_this_time
= errs
& E_SUM_LINK_PKTERRS
;
1133 } else if ((errs
& E_SUM_LINK_PKTERRS
) &&
1134 !(ppd
->lflags
& QIBL_LINKACTIVE
)) {
1136 * This can happen when SMA is trying to bring the link
1137 * up, but the IB link changes state at the "wrong" time.
1138 * The IB logic then complains that the packet isn't
1139 * valid. We don't want to confuse people, so we just
1140 * don't print them, except at debug
1142 ignore_this_time
= errs
& E_SUM_LINK_PKTERRS
;
1145 qib_write_kreg(dd
, kr_errclear
, errs
);
1147 errs
&= ~ignore_this_time
;
1152 * The ones we mask off are handled specially below
1153 * or above. Also mask SDMADISABLED by default as it
1156 mask
= ERR_MASK(IBStatusChanged
) |
1157 ERR_MASK(RcvEgrFullErr
) | ERR_MASK(RcvHdrFullErr
) |
1158 ERR_MASK(HardwareErr
) | ERR_MASK(SDmaDisabledErr
);
1160 qib_decode_7220_err(dd
, msg
, sizeof(dd
->cspec
->emsgbuf
), errs
& ~mask
);
1162 if (errs
& E_SUM_PKTERRS
)
1163 qib_stats
.sps_rcverrs
++;
1164 if (errs
& E_SUM_ERRS
)
1165 qib_stats
.sps_txerrs
++;
1166 iserr
= errs
& ~(E_SUM_PKTERRS
| QLOGIC_IB_E_PKTERRS
|
1167 ERR_MASK(SDmaDisabledErr
));
1169 if (errs
& ERR_MASK(IBStatusChanged
)) {
1172 ibcs
= qib_read_kreg64(dd
, kr_ibcstatus
);
1173 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
))
1174 handle_7220_chase(ppd
, ibcs
);
1176 /* Update our picture of width and speed from chip */
1177 ppd
->link_width_active
=
1178 ((ibcs
>> IBA7220_LINKWIDTH_SHIFT
) & 1) ?
1179 IB_WIDTH_4X
: IB_WIDTH_1X
;
1180 ppd
->link_speed_active
=
1181 ((ibcs
>> IBA7220_LINKSPEED_SHIFT
) & 1) ?
1182 QIB_IB_DDR
: QIB_IB_SDR
;
1185 * Since going into a recovery state causes the link state
1186 * to go down and since recovery is transitory, it is better
1187 * if we "miss" ever seeing the link training state go into
1188 * recovery (i.e., ignore this transition for link state
1189 * special handling purposes) without updating lastibcstat.
1191 if (qib_7220_phys_portstate(ibcs
) !=
1192 IB_PHYSPORTSTATE_LINK_ERR_RECOVER
)
1193 qib_handle_e_ibstatuschanged(ppd
, ibcs
);
1196 if (errs
& ERR_MASK(ResetNegated
)) {
1198 "Got reset, requires re-init (unload and reload driver)\n");
1199 dd
->flags
&= ~QIB_INITTED
; /* needs re-init */
1200 /* mark as having had error */
1201 *dd
->devstatusp
|= QIB_STATUS_HWERROR
;
1202 *dd
->pport
->statusp
&= ~QIB_STATUS_IB_CONF
;
1206 qib_dev_porterr(dd
, ppd
->port
, "%s error\n", msg
);
1208 if (ppd
->state_wanted
& ppd
->lflags
)
1209 wake_up_interruptible(&ppd
->state_wait
);
1212 * If there were hdrq or egrfull errors, wake up any processes
1213 * waiting in poll. We used to try to check which contexts had
1214 * the overflow, but given the cost of that and the chip reads
1215 * to support it, it's better to just wake everybody up if we
1216 * get an overflow; waiters can poll again if it's not them.
1218 if (errs
& (ERR_MASK(RcvEgrFullErr
) | ERR_MASK(RcvHdrFullErr
))) {
1219 qib_handle_urcv(dd
, ~0U);
1220 if (errs
& ERR_MASK(RcvEgrFullErr
))
1221 qib_stats
.sps_buffull
++;
1223 qib_stats
.sps_hdrfull
++;
1229 /* enable/disable chip from delivering interrupts */
1230 static void qib_7220_set_intr_state(struct qib_devdata
*dd
, u32 enable
)
1233 if (dd
->flags
& QIB_BADINTR
)
1235 qib_write_kreg(dd
, kr_intmask
, ~0ULL);
1236 /* force re-interrupt of any pending interrupts. */
1237 qib_write_kreg(dd
, kr_intclear
, 0ULL);
1239 qib_write_kreg(dd
, kr_intmask
, 0ULL);
1243 * Try to cleanup as much as possible for anything that might have gone
1244 * wrong while in freeze mode, such as pio buffers being written by user
1245 * processes (causing armlaunch), send errors due to going into freeze mode,
1246 * etc., and try to avoid causing extra interrupts while doing so.
1247 * Forcibly update the in-memory pioavail register copies after cleanup
1248 * because the chip won't do it while in freeze mode (the register values
1249 * themselves are kept correct).
1250 * Make sure that we don't lose any important interrupts by using the chip
1251 * feature that says that writing 0 to a bit in *clear that is set in
1252 * *status will cause an interrupt to be generated again (if allowed by
1254 * This is in chip-specific code because of all of the register accesses,
1255 * even though the details are similar on most chips.
1257 static void qib_7220_clear_freeze(struct qib_devdata
*dd
)
1259 /* disable error interrupts, to avoid confusion */
1260 qib_write_kreg(dd
, kr_errmask
, 0ULL);
1262 /* also disable interrupts; errormask is sometimes overwriten */
1263 qib_7220_set_intr_state(dd
, 0);
1265 qib_cancel_sends(dd
->pport
);
1267 /* clear the freeze, and be sure chip saw it */
1268 qib_write_kreg(dd
, kr_control
, dd
->control
);
1269 qib_read_kreg32(dd
, kr_scratch
);
1271 /* force in-memory update now we are out of freeze */
1272 qib_force_pio_avail_update(dd
);
1275 * force new interrupt if any hwerr, error or interrupt bits are
1276 * still set, and clear "safe" send packet errors related to freeze
1277 * and cancelling sends. Re-enable error interrupts before possible
1278 * force of re-interrupt on pending interrupts.
1280 qib_write_kreg(dd
, kr_hwerrclear
, 0ULL);
1281 qib_write_kreg(dd
, kr_errclear
, E_SPKT_ERRS_IGNORE
);
1282 qib_write_kreg(dd
, kr_errmask
, dd
->cspec
->errormask
);
1283 qib_7220_set_intr_state(dd
, 1);
1287 * qib_7220_handle_hwerrors - display hardware errors.
1288 * @dd: the qlogic_ib device
1289 * @msg: the output buffer
1290 * @msgl: the size of the output buffer
1292 * Use same msg buffer as regular errors to avoid excessive stack
1293 * use. Most hardware errors are catastrophic, but for right now,
1294 * we'll print them and continue. We reuse the same message buffer as
1295 * handle_7220_errors() to avoid excessive stack usage.
1297 static void qib_7220_handle_hwerrors(struct qib_devdata
*dd
, char *msg
,
1306 hwerrs
= qib_read_kreg64(dd
, kr_hwerrstatus
);
1309 if (hwerrs
== ~0ULL) {
1311 "Read of hardware error status failed (all bits set); ignoring\n");
1314 qib_stats
.sps_hwerrs
++;
1317 * Always clear the error status register, except MEMBISTFAIL,
1318 * regardless of whether we continue or stop using the chip.
1319 * We want that set so we know it failed, even across driver reload.
1320 * We'll still ignore it in the hwerrmask. We do this partly for
1321 * diagnostics, but also for support.
1323 qib_write_kreg(dd
, kr_hwerrclear
,
1324 hwerrs
& ~HWE_MASK(PowerOnBISTFailed
));
1326 hwerrs
&= dd
->cspec
->hwerrmask
;
1328 /* We log some errors to EEPROM, check if we have any of those. */
1329 for (log_idx
= 0; log_idx
< QIB_EEP_LOG_CNT
; ++log_idx
)
1330 if (hwerrs
& dd
->eep_st_masks
[log_idx
].hwerrs_to_log
)
1331 qib_inc_eeprom_err(dd
, log_idx
, 1);
1332 if (hwerrs
& ~(TXEMEMPARITYERR_PIOBUF
| TXEMEMPARITYERR_PIOPBC
|
1334 qib_devinfo(dd
->pcidev
,
1335 "Hardware error: hwerr=0x%llx (cleared)\n",
1336 (unsigned long long) hwerrs
);
1338 if (hwerrs
& ~IB_HWE_BITSEXTANT
)
1340 "hwerror interrupt with unknown errors %llx set\n",
1341 (unsigned long long) (hwerrs
& ~IB_HWE_BITSEXTANT
));
1343 if (hwerrs
& QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR
)
1344 qib_sd7220_clr_ibpar(dd
);
1346 ctrl
= qib_read_kreg32(dd
, kr_control
);
1347 if ((ctrl
& QLOGIC_IB_C_FREEZEMODE
) && !dd
->diag_client
) {
1349 * Parity errors in send memory are recoverable by h/w
1350 * just do housekeeping, exit freeze mode and continue.
1352 if (hwerrs
& (TXEMEMPARITYERR_PIOBUF
|
1353 TXEMEMPARITYERR_PIOPBC
)) {
1354 qib_7220_txe_recover(dd
);
1355 hwerrs
&= ~(TXEMEMPARITYERR_PIOBUF
|
1356 TXEMEMPARITYERR_PIOPBC
);
1361 qib_7220_clear_freeze(dd
);
1366 if (hwerrs
& HWE_MASK(PowerOnBISTFailed
)) {
1369 "[Memory BIST test failed, InfiniPath hardware unusable]",
1371 /* ignore from now on, so disable until driver reloaded */
1372 dd
->cspec
->hwerrmask
&= ~HWE_MASK(PowerOnBISTFailed
);
1373 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
1376 qib_format_hwerrors(hwerrs
, qib_7220_hwerror_msgs
,
1377 ARRAY_SIZE(qib_7220_hwerror_msgs
), msg
, msgl
);
1379 bitsmsg
= dd
->cspec
->bitsmsgbuf
;
1380 if (hwerrs
& (QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK
<<
1381 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT
)) {
1382 bits
= (u32
) ((hwerrs
>>
1383 QLOGIC_IB_HWE_PCIEMEMPARITYERR_SHIFT
) &
1384 QLOGIC_IB_HWE_PCIEMEMPARITYERR_MASK
);
1385 snprintf(bitsmsg
, sizeof(dd
->cspec
->bitsmsgbuf
),
1386 "[PCIe Mem Parity Errs %x] ", bits
);
1387 strlcat(msg
, bitsmsg
, msgl
);
1390 #define _QIB_PLL_FAIL (QLOGIC_IB_HWE_COREPLL_FBSLIP | \
1391 QLOGIC_IB_HWE_COREPLL_RFSLIP)
1393 if (hwerrs
& _QIB_PLL_FAIL
) {
1395 snprintf(bitsmsg
, sizeof(dd
->cspec
->bitsmsgbuf
),
1396 "[PLL failed (%llx), InfiniPath hardware unusable]",
1397 (unsigned long long) hwerrs
& _QIB_PLL_FAIL
);
1398 strlcat(msg
, bitsmsg
, msgl
);
1399 /* ignore from now on, so disable until driver reloaded */
1400 dd
->cspec
->hwerrmask
&= ~(hwerrs
& _QIB_PLL_FAIL
);
1401 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
1404 if (hwerrs
& QLOGIC_IB_HWE_SERDESPLLFAILED
) {
1406 * If it occurs, it is left masked since the eternal
1407 * interface is unused.
1409 dd
->cspec
->hwerrmask
&= ~QLOGIC_IB_HWE_SERDESPLLFAILED
;
1410 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
1413 qib_dev_err(dd
, "%s hardware error\n", msg
);
1415 if (isfatal
&& !dd
->diag_client
) {
1417 "Fatal Hardware Error, no longer usable, SN %.16s\n",
1420 * For /sys status file and user programs to print; if no
1421 * trailing brace is copied, we'll know it was truncated.
1424 snprintf(dd
->freezemsg
, dd
->freezelen
,
1426 qib_disable_after_error(dd
);
1432 * qib_7220_init_hwerrors - enable hardware errors
1433 * @dd: the qlogic_ib device
1435 * now that we have finished initializing everything that might reasonably
1436 * cause a hardware error, and cleared those errors bits as they occur,
1437 * we can enable hardware errors in the mask (potentially enabling
1438 * freeze mode), and enable hardware errors as errors (along with
1439 * everything else) in errormask
1441 static void qib_7220_init_hwerrors(struct qib_devdata
*dd
)
1446 extsval
= qib_read_kreg64(dd
, kr_extstatus
);
1448 if (!(extsval
& (QLOGIC_IB_EXTS_MEMBIST_ENDTEST
|
1449 QLOGIC_IB_EXTS_MEMBIST_DISABLED
)))
1450 qib_dev_err(dd
, "MemBIST did not complete!\n");
1451 if (extsval
& QLOGIC_IB_EXTS_MEMBIST_DISABLED
)
1452 qib_devinfo(dd
->pcidev
, "MemBIST is disabled.\n");
1454 val
= ~0ULL; /* default to all hwerrors become interrupts, */
1456 val
&= ~QLOGIC_IB_HWE_IB_UC_MEMORYPARITYERR
;
1457 dd
->cspec
->hwerrmask
= val
;
1459 qib_write_kreg(dd
, kr_hwerrclear
, ~HWE_MASK(PowerOnBISTFailed
));
1460 qib_write_kreg(dd
, kr_hwerrmask
, dd
->cspec
->hwerrmask
);
1463 qib_write_kreg(dd
, kr_errclear
, ~0ULL);
1464 /* enable errors that are masked, at least this first time. */
1465 qib_write_kreg(dd
, kr_errmask
, ~0ULL);
1466 dd
->cspec
->errormask
= qib_read_kreg64(dd
, kr_errmask
);
1467 /* clear any interrupts up to this point (ints still not enabled) */
1468 qib_write_kreg(dd
, kr_intclear
, ~0ULL);
1472 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
1473 * on chips that are count-based, rather than trigger-based. There is no
1474 * reference counting, but that's also fine, given the intended use.
1475 * Only chip-specific because it's all register accesses
1477 static void qib_set_7220_armlaunch(struct qib_devdata
*dd
, u32 enable
)
1480 qib_write_kreg(dd
, kr_errclear
, ERR_MASK(SendPioArmLaunchErr
));
1481 dd
->cspec
->errormask
|= ERR_MASK(SendPioArmLaunchErr
);
1483 dd
->cspec
->errormask
&= ~ERR_MASK(SendPioArmLaunchErr
);
1484 qib_write_kreg(dd
, kr_errmask
, dd
->cspec
->errormask
);
1488 * Formerly took parameter <which> in pre-shifted,
1489 * pre-merged form with LinkCmd and LinkInitCmd
1490 * together, and assuming the zero was NOP.
1492 static void qib_set_ib_7220_lstate(struct qib_pportdata
*ppd
, u16 linkcmd
,
1496 struct qib_devdata
*dd
= ppd
->dd
;
1497 unsigned long flags
;
1499 if (linitcmd
== QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
) {
1501 * If we are told to disable, note that so link-recovery
1502 * code does not attempt to bring us back up.
1504 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
1505 ppd
->lflags
|= QIBL_IB_LINK_DISABLED
;
1506 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
1507 } else if (linitcmd
|| linkcmd
== QLOGIC_IB_IBCC_LINKCMD_DOWN
) {
1509 * Any other linkinitcmd will lead to LINKDOWN and then
1510 * to INIT (if all is well), so clear flag to let
1511 * link-recovery code attempt to bring us back up.
1513 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
1514 ppd
->lflags
&= ~QIBL_IB_LINK_DISABLED
;
1515 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
1518 mod_wd
= (linkcmd
<< IBA7220_IBCC_LINKCMD_SHIFT
) |
1519 (linitcmd
<< QLOGIC_IB_IBCC_LINKINITCMD_SHIFT
);
1521 qib_write_kreg(dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
| mod_wd
);
1522 /* write to chip to prevent back-to-back writes of ibc reg */
1523 qib_write_kreg(dd
, kr_scratch
, 0);
1527 * All detailed interaction with the SerDes has been moved to qib_sd7220.c
1529 * The portion of IBA7220-specific bringup_serdes() that actually deals with
1530 * registers and memory within the SerDes itself is qib_sd7220_init().
1534 * qib_7220_bringup_serdes - bring up the serdes
1535 * @ppd: physical port on the qlogic_ib device
1537 static int qib_7220_bringup_serdes(struct qib_pportdata
*ppd
)
1539 struct qib_devdata
*dd
= ppd
->dd
;
1540 u64 val
, prev_val
, guid
, ibc
;
1543 /* Put IBC in reset, sends disabled */
1544 dd
->control
&= ~QLOGIC_IB_C_LINKENABLE
;
1545 qib_write_kreg(dd
, kr_control
, 0ULL);
1547 if (qib_compat_ddr_negotiate
) {
1548 ppd
->cpspec
->ibdeltainprog
= 1;
1549 ppd
->cpspec
->ibsymsnap
= read_7220_creg32(dd
, cr_ibsymbolerr
);
1550 ppd
->cpspec
->iblnkerrsnap
=
1551 read_7220_creg32(dd
, cr_iblinkerrrecov
);
1554 /* flowcontrolwatermark is in units of KBytes */
1555 ibc
= 0x5ULL
<< SYM_LSB(IBCCtrl
, FlowCtrlWaterMark
);
1557 * How often flowctrl sent. More or less in usecs; balance against
1558 * watermark value, so that in theory senders always get a flow
1559 * control update in time to not let the IB link go idle.
1561 ibc
|= 0x3ULL
<< SYM_LSB(IBCCtrl
, FlowCtrlPeriod
);
1562 /* max error tolerance */
1563 ibc
|= 0xfULL
<< SYM_LSB(IBCCtrl
, PhyerrThreshold
);
1564 /* use "real" buffer space for */
1565 ibc
|= 4ULL << SYM_LSB(IBCCtrl
, CreditScale
);
1566 /* IB credit flow control. */
1567 ibc
|= 0xfULL
<< SYM_LSB(IBCCtrl
, OverrunThreshold
);
1569 * set initial max size pkt IBC will send, including ICRC; it's the
1570 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
1572 ibc
|= ((u64
)(ppd
->ibmaxlen
>> 2) + 1) << SYM_LSB(IBCCtrl
, MaxPktLen
);
1573 ppd
->cpspec
->ibcctrl
= ibc
; /* without linkcmd or linkinitcmd! */
1575 /* initially come up waiting for TS1, without sending anything. */
1576 val
= ppd
->cpspec
->ibcctrl
| (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
<<
1577 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT
);
1578 qib_write_kreg(dd
, kr_ibcctrl
, val
);
1580 if (!ppd
->cpspec
->ibcddrctrl
) {
1581 /* not on re-init after reset */
1582 ppd
->cpspec
->ibcddrctrl
= qib_read_kreg64(dd
, kr_ibcddrctrl
);
1584 if (ppd
->link_speed_enabled
== (QIB_IB_SDR
| QIB_IB_DDR
))
1585 ppd
->cpspec
->ibcddrctrl
|=
1586 IBA7220_IBC_SPEED_AUTONEG_MASK
|
1587 IBA7220_IBC_IBTA_1_2_MASK
;
1589 ppd
->cpspec
->ibcddrctrl
|=
1590 ppd
->link_speed_enabled
== QIB_IB_DDR
?
1591 IBA7220_IBC_SPEED_DDR
: IBA7220_IBC_SPEED_SDR
;
1592 if ((ppd
->link_width_enabled
& (IB_WIDTH_1X
| IB_WIDTH_4X
)) ==
1593 (IB_WIDTH_1X
| IB_WIDTH_4X
))
1594 ppd
->cpspec
->ibcddrctrl
|= IBA7220_IBC_WIDTH_AUTONEG
;
1596 ppd
->cpspec
->ibcddrctrl
|=
1597 ppd
->link_width_enabled
== IB_WIDTH_4X
?
1598 IBA7220_IBC_WIDTH_4X_ONLY
:
1599 IBA7220_IBC_WIDTH_1X_ONLY
;
1601 /* always enable these on driver reload, not sticky */
1602 ppd
->cpspec
->ibcddrctrl
|=
1603 IBA7220_IBC_RXPOL_MASK
<< IBA7220_IBC_RXPOL_SHIFT
;
1604 ppd
->cpspec
->ibcddrctrl
|=
1605 IBA7220_IBC_HRTBT_MASK
<< IBA7220_IBC_HRTBT_SHIFT
;
1607 /* enable automatic lane reversal detection for receive */
1608 ppd
->cpspec
->ibcddrctrl
|= IBA7220_IBC_LANE_REV_SUPPORTED
;
1610 /* write to chip to prevent back-to-back writes of ibc reg */
1611 qib_write_kreg(dd
, kr_scratch
, 0);
1613 qib_write_kreg(dd
, kr_ibcddrctrl
, ppd
->cpspec
->ibcddrctrl
);
1614 qib_write_kreg(dd
, kr_scratch
, 0);
1616 qib_write_kreg(dd
, kr_ncmodectrl
, 0Ull);
1617 qib_write_kreg(dd
, kr_scratch
, 0);
1619 ret
= qib_sd7220_init(dd
);
1621 val
= qib_read_kreg64(dd
, kr_xgxs_cfg
);
1623 val
|= QLOGIC_IB_XGXS_FC_SAFE
;
1624 if (val
!= prev_val
) {
1625 qib_write_kreg(dd
, kr_xgxs_cfg
, val
);
1626 qib_read_kreg32(dd
, kr_scratch
);
1628 if (val
& QLOGIC_IB_XGXS_RESET
)
1629 val
&= ~QLOGIC_IB_XGXS_RESET
;
1630 if (val
!= prev_val
)
1631 qib_write_kreg(dd
, kr_xgxs_cfg
, val
);
1633 /* first time through, set port guid */
1635 ppd
->guid
= dd
->base_guid
;
1636 guid
= be64_to_cpu(ppd
->guid
);
1638 qib_write_kreg(dd
, kr_hrtbt_guid
, guid
);
1640 dd
->control
|= QLOGIC_IB_C_LINKENABLE
;
1641 qib_write_kreg(dd
, kr_control
, dd
->control
);
1643 /* write to chip to prevent back-to-back writes of ibc reg */
1644 qib_write_kreg(dd
, kr_scratch
, 0);
1649 * qib_7220_quiet_serdes - set serdes to txidle
1650 * @ppd: physical port of the qlogic_ib device
1651 * Called when driver is being unloaded
1653 static void qib_7220_quiet_serdes(struct qib_pportdata
*ppd
)
1656 struct qib_devdata
*dd
= ppd
->dd
;
1657 unsigned long flags
;
1660 dd
->control
&= ~QLOGIC_IB_C_LINKENABLE
;
1661 qib_write_kreg(dd
, kr_control
,
1662 dd
->control
| QLOGIC_IB_C_FREEZEMODE
);
1664 ppd
->cpspec
->chase_end
= 0;
1665 if (ppd
->cpspec
->chase_timer
.data
) /* if initted */
1666 del_timer_sync(&ppd
->cpspec
->chase_timer
);
1668 if (ppd
->cpspec
->ibsymdelta
|| ppd
->cpspec
->iblnkerrdelta
||
1669 ppd
->cpspec
->ibdeltainprog
) {
1672 /* enable counter writes */
1673 diagc
= qib_read_kreg64(dd
, kr_hwdiagctrl
);
1674 qib_write_kreg(dd
, kr_hwdiagctrl
,
1675 diagc
| SYM_MASK(HwDiagCtrl
, CounterWrEnable
));
1677 if (ppd
->cpspec
->ibsymdelta
|| ppd
->cpspec
->ibdeltainprog
) {
1678 val
= read_7220_creg32(dd
, cr_ibsymbolerr
);
1679 if (ppd
->cpspec
->ibdeltainprog
)
1680 val
-= val
- ppd
->cpspec
->ibsymsnap
;
1681 val
-= ppd
->cpspec
->ibsymdelta
;
1682 write_7220_creg(dd
, cr_ibsymbolerr
, val
);
1684 if (ppd
->cpspec
->iblnkerrdelta
|| ppd
->cpspec
->ibdeltainprog
) {
1685 val
= read_7220_creg32(dd
, cr_iblinkerrrecov
);
1686 if (ppd
->cpspec
->ibdeltainprog
)
1687 val
-= val
- ppd
->cpspec
->iblnkerrsnap
;
1688 val
-= ppd
->cpspec
->iblnkerrdelta
;
1689 write_7220_creg(dd
, cr_iblinkerrrecov
, val
);
1692 /* and disable counter writes */
1693 qib_write_kreg(dd
, kr_hwdiagctrl
, diagc
);
1695 qib_set_ib_7220_lstate(ppd
, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
);
1697 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
1698 ppd
->lflags
&= ~QIBL_IB_AUTONEG_INPROG
;
1699 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
1700 wake_up(&ppd
->cpspec
->autoneg_wait
);
1701 cancel_delayed_work_sync(&ppd
->cpspec
->autoneg_work
);
1703 shutdown_7220_relock_poll(ppd
->dd
);
1704 val
= qib_read_kreg64(ppd
->dd
, kr_xgxs_cfg
);
1705 val
|= QLOGIC_IB_XGXS_RESET
;
1706 qib_write_kreg(ppd
->dd
, kr_xgxs_cfg
, val
);
1710 * qib_setup_7220_setextled - set the state of the two external LEDs
1711 * @dd: the qlogic_ib device
1712 * @on: whether the link is up or not
1714 * The exact combo of LEDs if on is true is determined by looking
1717 * These LEDs indicate the physical and logical state of IB link.
1718 * For this chip (at least with recommended board pinouts), LED1
1719 * is Yellow (logical state) and LED2 is Green (physical state),
1721 * Note: We try to match the Mellanox HCA LED behavior as best
1722 * we can. Green indicates physical link state is OK (something is
1723 * plugged in, and we can train).
1724 * Amber indicates the link is logically up (ACTIVE).
1725 * Mellanox further blinks the amber LED to indicate data packet
1726 * activity, but we have no hardware support for that, so it would
1727 * require waking up every 10-20 msecs and checking the counters
1728 * on the chip, and then turning the LED off if appropriate. That's
1729 * visible overhead, so not something we will do.
1732 static void qib_setup_7220_setextled(struct qib_pportdata
*ppd
, u32 on
)
1734 struct qib_devdata
*dd
= ppd
->dd
;
1735 u64 extctl
, ledblink
= 0, val
, lst
, ltst
;
1736 unsigned long flags
;
1739 * The diags use the LED to indicate diag info, so we leave
1740 * the external LED alone when the diags are running.
1742 if (dd
->diag_client
)
1745 if (ppd
->led_override
) {
1746 ltst
= (ppd
->led_override
& QIB_LED_PHYS
) ?
1747 IB_PHYSPORTSTATE_LINKUP
: IB_PHYSPORTSTATE_DISABLED
,
1748 lst
= (ppd
->led_override
& QIB_LED_LOG
) ?
1749 IB_PORT_ACTIVE
: IB_PORT_DOWN
;
1751 val
= qib_read_kreg64(dd
, kr_ibcstatus
);
1752 ltst
= qib_7220_phys_portstate(val
);
1753 lst
= qib_7220_iblink_state(val
);
1759 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
1760 extctl
= dd
->cspec
->extctrl
& ~(SYM_MASK(EXTCtrl
, LEDPriPortGreenOn
) |
1761 SYM_MASK(EXTCtrl
, LEDPriPortYellowOn
));
1762 if (ltst
== IB_PHYSPORTSTATE_LINKUP
) {
1763 extctl
|= SYM_MASK(EXTCtrl
, LEDPriPortGreenOn
);
1765 * counts are in chip clock (4ns) periods.
1766 * This is 1/16 sec (66.6ms) on,
1767 * 3/16 sec (187.5 ms) off, with packets rcvd
1769 ledblink
= ((66600 * 1000UL / 4) << IBA7220_LEDBLINK_ON_SHIFT
)
1770 | ((187500 * 1000UL / 4) << IBA7220_LEDBLINK_OFF_SHIFT
);
1772 if (lst
== IB_PORT_ACTIVE
)
1773 extctl
|= SYM_MASK(EXTCtrl
, LEDPriPortYellowOn
);
1774 dd
->cspec
->extctrl
= extctl
;
1775 qib_write_kreg(dd
, kr_extctrl
, extctl
);
1776 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
1778 if (ledblink
) /* blink the LED on packet receive */
1779 qib_write_kreg(dd
, kr_rcvpktledcnt
, ledblink
);
1782 static void qib_7220_free_irq(struct qib_devdata
*dd
)
1784 if (dd
->cspec
->irq
) {
1785 free_irq(dd
->cspec
->irq
, dd
);
1792 * qib_setup_7220_cleanup - clean up any per-chip chip-specific stuff
1793 * @dd: the qlogic_ib device
1795 * This is called during driver unload.
1798 static void qib_setup_7220_cleanup(struct qib_devdata
*dd
)
1800 qib_7220_free_irq(dd
);
1801 kfree(dd
->cspec
->cntrs
);
1802 kfree(dd
->cspec
->portcntrs
);
1806 * This is only called for SDmaInt.
1807 * SDmaDisabled is handled on the error path.
1809 static void sdma_7220_intr(struct qib_pportdata
*ppd
, u64 istat
)
1811 unsigned long flags
;
1813 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
1815 switch (ppd
->sdma_state
.current_state
) {
1816 case qib_sdma_state_s00_hw_down
:
1819 case qib_sdma_state_s10_hw_start_up_wait
:
1820 __qib_sdma_process_event(ppd
, qib_sdma_event_e20_hw_started
);
1823 case qib_sdma_state_s20_idle
:
1826 case qib_sdma_state_s30_sw_clean_up_wait
:
1829 case qib_sdma_state_s40_hw_clean_up_wait
:
1832 case qib_sdma_state_s50_hw_halt_wait
:
1833 __qib_sdma_process_event(ppd
, qib_sdma_event_e60_hw_halted
);
1836 case qib_sdma_state_s99_running
:
1837 /* too chatty to print here */
1838 __qib_sdma_intr(ppd
);
1841 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
1844 static void qib_wantpiobuf_7220_intr(struct qib_devdata
*dd
, u32 needint
)
1846 unsigned long flags
;
1848 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
1850 if (!(dd
->sendctrl
& SYM_MASK(SendCtrl
, SendBufAvailUpd
)))
1853 * blip the availupd off, next write will be on, so
1854 * we ensure an avail update, regardless of threshold or
1855 * buffers becoming free, whenever we want an interrupt
1857 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
&
1858 ~SYM_MASK(SendCtrl
, SendBufAvailUpd
));
1859 qib_write_kreg(dd
, kr_scratch
, 0ULL);
1860 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SendIntBufAvail
);
1862 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, SendIntBufAvail
);
1863 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
);
1864 qib_write_kreg(dd
, kr_scratch
, 0ULL);
1866 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
1870 * Handle errors and unusual events first, separate function
1871 * to improve cache hits for fast path interrupt handling.
1873 static noinline
void unlikely_7220_intr(struct qib_devdata
*dd
, u64 istat
)
1875 if (unlikely(istat
& ~QLOGIC_IB_I_BITSEXTANT
))
1877 "interrupt with unknown interrupts %Lx set\n",
1878 istat
& ~QLOGIC_IB_I_BITSEXTANT
);
1880 if (istat
& QLOGIC_IB_I_GPIO
) {
1884 * Boards for this chip currently don't use GPIO interrupts,
1885 * so clear by writing GPIOstatus to GPIOclear, and complain
1886 * to alert developer. To avoid endless repeats, clear
1887 * the bits in the mask, since there is some kind of
1888 * programming error or chip problem.
1890 gpiostatus
= qib_read_kreg32(dd
, kr_gpio_status
);
1892 * In theory, writing GPIOstatus to GPIOclear could
1893 * have a bad side-effect on some diagnostic that wanted
1894 * to poll for a status-change, but the various shadows
1895 * make that problematic at best. Diags will just suppress
1896 * all GPIO interrupts during such tests.
1898 qib_write_kreg(dd
, kr_gpio_clear
, gpiostatus
);
1901 const u32 mask
= qib_read_kreg32(dd
, kr_gpio_mask
);
1902 u32 gpio_irq
= mask
& gpiostatus
;
1905 * A bit set in status and (chip) Mask register
1906 * would cause an interrupt. Since we are not
1907 * expecting any, report it. Also check that the
1908 * chip reflects our shadow, report issues,
1909 * and refresh from the shadow.
1912 * Clear any troublemakers, and update chip
1915 dd
->cspec
->gpio_mask
&= ~gpio_irq
;
1916 qib_write_kreg(dd
, kr_gpio_mask
, dd
->cspec
->gpio_mask
);
1920 if (istat
& QLOGIC_IB_I_ERROR
) {
1923 qib_stats
.sps_errints
++;
1924 estat
= qib_read_kreg64(dd
, kr_errstatus
);
1926 qib_devinfo(dd
->pcidev
,
1927 "error interrupt (%Lx), but no error bits set!\n",
1930 handle_7220_errors(dd
, estat
);
1934 static irqreturn_t
qib_7220intr(int irq
, void *data
)
1936 struct qib_devdata
*dd
= data
;
1943 if ((dd
->flags
& (QIB_PRESENT
| QIB_BADINTR
)) != QIB_PRESENT
) {
1945 * This return value is not great, but we do not want the
1946 * interrupt core code to remove our interrupt handler
1947 * because we don't appear to be handling an interrupt
1948 * during a chip reset.
1954 istat
= qib_read_kreg64(dd
, kr_intstatus
);
1956 if (unlikely(!istat
)) {
1957 ret
= IRQ_NONE
; /* not our interrupt, or already handled */
1960 if (unlikely(istat
== -1)) {
1961 qib_bad_intrstatus(dd
);
1962 /* don't know if it was our interrupt or not */
1967 this_cpu_inc(*dd
->int_counter
);
1968 if (unlikely(istat
& (~QLOGIC_IB_I_BITSEXTANT
|
1969 QLOGIC_IB_I_GPIO
| QLOGIC_IB_I_ERROR
)))
1970 unlikely_7220_intr(dd
, istat
);
1973 * Clear the interrupt bits we found set, relatively early, so we
1974 * "know" know the chip will have seen this by the time we process
1975 * the queue, and will re-interrupt if necessary. The processor
1976 * itself won't take the interrupt again until we return.
1978 qib_write_kreg(dd
, kr_intclear
, istat
);
1981 * Handle kernel receive queues before checking for pio buffers
1982 * available since receives can overflow; piobuf waiters can afford
1983 * a few extra cycles, since they were waiting anyway.
1986 ((QLOGIC_IB_I_RCVAVAIL_MASK
<< QLOGIC_IB_I_RCVAVAIL_SHIFT
) |
1987 (QLOGIC_IB_I_RCVURG_MASK
<< QLOGIC_IB_I_RCVURG_SHIFT
));
1989 rmask
= (1ULL << QLOGIC_IB_I_RCVAVAIL_SHIFT
) |
1990 (1ULL << QLOGIC_IB_I_RCVURG_SHIFT
);
1991 for (i
= 0; i
< dd
->first_user_ctxt
; i
++) {
1992 if (ctxtrbits
& rmask
) {
1993 ctxtrbits
&= ~rmask
;
1994 qib_kreceive(dd
->rcd
[i
], NULL
, NULL
);
2000 (ctxtrbits
>> QLOGIC_IB_I_RCVAVAIL_SHIFT
) |
2001 (ctxtrbits
>> QLOGIC_IB_I_RCVURG_SHIFT
);
2002 qib_handle_urcv(dd
, ctxtrbits
);
2006 /* only call for SDmaInt */
2007 if (istat
& QLOGIC_IB_I_SDMAINT
)
2008 sdma_7220_intr(dd
->pport
, istat
);
2010 if ((istat
& QLOGIC_IB_I_SPIOBUFAVAIL
) && (dd
->flags
& QIB_INITTED
))
2011 qib_ib_piobufavail(dd
);
2019 * Set up our chip-specific interrupt handler.
2020 * The interrupt type has already been setup, so
2021 * we just need to do the registration and error checking.
2022 * If we are using MSI interrupts, we may fall back to
2023 * INTx later, if the interrupt handler doesn't get called
2024 * within 1/2 second (see verify_interrupt()).
2026 static void qib_setup_7220_interrupt(struct qib_devdata
*dd
)
2028 if (!dd
->cspec
->irq
)
2030 "irq is 0, BIOS error? Interrupts won't work\n");
2032 int ret
= request_irq(dd
->cspec
->irq
, qib_7220intr
,
2033 dd
->msi_lo
? 0 : IRQF_SHARED
,
2038 "Couldn't setup %s interrupt (irq=%d): %d\n",
2039 dd
->msi_lo
? "MSI" : "INTx",
2040 dd
->cspec
->irq
, ret
);
2045 * qib_7220_boardname - fill in the board name
2046 * @dd: the qlogic_ib device
2048 * info is based on the board revision register
2050 static void qib_7220_boardname(struct qib_devdata
*dd
)
2053 u32 boardid
, namelen
;
2055 boardid
= SYM_FIELD(dd
->revision
, Revision
,
2060 n
= "InfiniPath_QLE7240";
2063 n
= "InfiniPath_QLE7280";
2066 qib_dev_err(dd
, "Unknown 7220 board with ID %u\n", boardid
);
2067 n
= "Unknown_InfiniPath_7220";
2071 namelen
= strlen(n
) + 1;
2072 dd
->boardname
= kmalloc(namelen
, GFP_KERNEL
);
2074 snprintf(dd
->boardname
, namelen
, "%s", n
);
2076 if (dd
->majrev
!= 5 || !dd
->minrev
|| dd
->minrev
> 2)
2078 "Unsupported InfiniPath hardware revision %u.%u!\n",
2079 dd
->majrev
, dd
->minrev
);
2081 snprintf(dd
->boardversion
, sizeof(dd
->boardversion
),
2082 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
2083 QIB_CHIP_VERS_MAJ
, QIB_CHIP_VERS_MIN
, dd
->boardname
,
2084 (unsigned)SYM_FIELD(dd
->revision
, Revision_R
, Arch
),
2085 dd
->majrev
, dd
->minrev
,
2086 (unsigned)SYM_FIELD(dd
->revision
, Revision_R
, SW
));
2090 * This routine sleeps, so it can only be called from user context, not
2091 * from interrupt context.
2093 static int qib_setup_7220_reset(struct qib_devdata
*dd
)
2099 u8 int_line
, clinesz
;
2100 unsigned long flags
;
2102 qib_pcie_getcmd(dd
, &cmdval
, &int_line
, &clinesz
);
2104 /* Use dev_err so it shows up in logs, etc. */
2105 qib_dev_err(dd
, "Resetting InfiniPath unit %u\n", dd
->unit
);
2107 /* no interrupts till re-initted */
2108 qib_7220_set_intr_state(dd
, 0);
2110 dd
->pport
->cpspec
->ibdeltainprog
= 0;
2111 dd
->pport
->cpspec
->ibsymdelta
= 0;
2112 dd
->pport
->cpspec
->iblnkerrdelta
= 0;
2115 * Keep chip from being accessed until we are ready. Use
2116 * writeq() directly, to allow the write even though QIB_PRESENT
2119 dd
->flags
&= ~(QIB_INITTED
| QIB_PRESENT
);
2120 /* so we check interrupts work again */
2121 dd
->z_int_counter
= qib_int_counter(dd
);
2122 val
= dd
->control
| QLOGIC_IB_C_RESET
;
2123 writeq(val
, &dd
->kregbase
[kr_control
]);
2124 mb(); /* prevent compiler reordering around actual reset */
2126 for (i
= 1; i
<= 5; i
++) {
2128 * Allow MBIST, etc. to complete; longer on each retry.
2129 * We sometimes get machine checks from bus timeout if no
2130 * response, so for now, make it *really* long.
2132 msleep(1000 + (1 + i
) * 2000);
2134 qib_pcie_reenable(dd
, cmdval
, int_line
, clinesz
);
2137 * Use readq directly, so we don't need to mark it as PRESENT
2138 * until we get a successful indication that all is well.
2140 val
= readq(&dd
->kregbase
[kr_revision
]);
2141 if (val
== dd
->revision
) {
2142 dd
->flags
|= QIB_PRESENT
; /* it's back */
2143 ret
= qib_reinit_intr(dd
);
2147 ret
= 0; /* failed */
2151 if (qib_pcie_params(dd
, dd
->lbus_width
, NULL
, NULL
))
2153 "Reset failed to setup PCIe or interrupts; continuing anyway\n");
2155 /* hold IBC in reset, no sends, etc till later */
2156 qib_write_kreg(dd
, kr_control
, 0ULL);
2158 /* clear the reset error, init error/hwerror mask */
2159 qib_7220_init_hwerrors(dd
);
2161 /* do setup similar to speed or link-width changes */
2162 if (dd
->pport
->cpspec
->ibcddrctrl
& IBA7220_IBC_IBTA_1_2_MASK
)
2163 dd
->cspec
->presets_needed
= 1;
2164 spin_lock_irqsave(&dd
->pport
->lflags_lock
, flags
);
2165 dd
->pport
->lflags
|= QIBL_IB_FORCE_NOTIFY
;
2166 dd
->pport
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
2167 spin_unlock_irqrestore(&dd
->pport
->lflags_lock
, flags
);
2174 * qib_7220_put_tid - write a TID to the chip
2175 * @dd: the qlogic_ib device
2176 * @tidptr: pointer to the expected TID (in chip) to update
2177 * @tidtype: 0 for eager, 1 for expected
2178 * @pa: physical address of in memory buffer; tidinvalid if freeing
2180 static void qib_7220_put_tid(struct qib_devdata
*dd
, u64 __iomem
*tidptr
,
2181 u32 type
, unsigned long pa
)
2183 if (pa
!= dd
->tidinvalid
) {
2184 u64 chippa
= pa
>> IBA7220_TID_PA_SHIFT
;
2186 /* paranoia checks */
2187 if (pa
!= (chippa
<< IBA7220_TID_PA_SHIFT
)) {
2188 qib_dev_err(dd
, "Physaddr %lx not 2KB aligned!\n",
2192 if (chippa
>= (1UL << IBA7220_TID_SZ_SHIFT
)) {
2194 "Physical page address 0x%lx larger than supported\n",
2199 if (type
== RCVHQ_RCV_TYPE_EAGER
)
2200 chippa
|= dd
->tidtemplate
;
2201 else /* for now, always full 4KB page */
2202 chippa
|= IBA7220_TID_SZ_4K
;
2210 * qib_7220_clear_tids - clear all TID entries for a ctxt, expected and eager
2211 * @dd: the qlogic_ib device
2214 * clear all TID entries for a ctxt, expected and eager.
2215 * Used from qib_close(). On this chip, TIDs are only 32 bits,
2216 * not 64, but they are still on 64 bit boundaries, so tidbase
2217 * is declared as u64 * for the pointer math, even though we write 32 bits
2219 static void qib_7220_clear_tids(struct qib_devdata
*dd
,
2220 struct qib_ctxtdata
*rcd
)
2222 u64 __iomem
*tidbase
;
2223 unsigned long tidinv
;
2227 if (!dd
->kregbase
|| !rcd
)
2232 tidinv
= dd
->tidinvalid
;
2233 tidbase
= (u64 __iomem
*)
2234 ((char __iomem
*)(dd
->kregbase
) +
2236 ctxt
* dd
->rcvtidcnt
* sizeof(*tidbase
));
2238 for (i
= 0; i
< dd
->rcvtidcnt
; i
++)
2239 qib_7220_put_tid(dd
, &tidbase
[i
], RCVHQ_RCV_TYPE_EXPECTED
,
2242 tidbase
= (u64 __iomem
*)
2243 ((char __iomem
*)(dd
->kregbase
) +
2245 rcd
->rcvegr_tid_base
* sizeof(*tidbase
));
2247 for (i
= 0; i
< rcd
->rcvegrcnt
; i
++)
2248 qib_7220_put_tid(dd
, &tidbase
[i
], RCVHQ_RCV_TYPE_EAGER
,
2253 * qib_7220_tidtemplate - setup constants for TID updates
2254 * @dd: the qlogic_ib device
2256 * We setup stuff that we use a lot, to avoid calculating each time
2258 static void qib_7220_tidtemplate(struct qib_devdata
*dd
)
2260 if (dd
->rcvegrbufsize
== 2048)
2261 dd
->tidtemplate
= IBA7220_TID_SZ_2K
;
2262 else if (dd
->rcvegrbufsize
== 4096)
2263 dd
->tidtemplate
= IBA7220_TID_SZ_4K
;
2268 * qib_init_7220_get_base_info - set chip-specific flags for user code
2269 * @rcd: the qlogic_ib ctxt
2270 * @kbase: qib_base_info pointer
2272 * We set the PCIE flag because the lower bandwidth on PCIe vs
2273 * HyperTransport can affect some user packet algorithims.
2275 static int qib_7220_get_base_info(struct qib_ctxtdata
*rcd
,
2276 struct qib_base_info
*kinfo
)
2278 kinfo
->spi_runtime_flags
|= QIB_RUNTIME_PCIE
|
2279 QIB_RUNTIME_NODMA_RTAIL
| QIB_RUNTIME_SDMA
;
2281 if (rcd
->dd
->flags
& QIB_USE_SPCL_TRIG
)
2282 kinfo
->spi_runtime_flags
|= QIB_RUNTIME_SPECIAL_TRIGGER
;
2287 static struct qib_message_header
*
2288 qib_7220_get_msgheader(struct qib_devdata
*dd
, __le32
*rhf_addr
)
2290 u32 offset
= qib_hdrget_offset(rhf_addr
);
2292 return (struct qib_message_header
*)
2293 (rhf_addr
- dd
->rhf_offset
+ offset
);
2296 static void qib_7220_config_ctxts(struct qib_devdata
*dd
)
2298 unsigned long flags
;
2301 nchipctxts
= qib_read_kreg32(dd
, kr_portcnt
);
2302 dd
->cspec
->numctxts
= nchipctxts
;
2303 if (qib_n_krcv_queues
> 1) {
2304 dd
->qpn_mask
= 0x3e;
2305 dd
->first_user_ctxt
= qib_n_krcv_queues
* dd
->num_pports
;
2306 if (dd
->first_user_ctxt
> nchipctxts
)
2307 dd
->first_user_ctxt
= nchipctxts
;
2309 dd
->first_user_ctxt
= dd
->num_pports
;
2310 dd
->n_krcv_queues
= dd
->first_user_ctxt
;
2312 if (!qib_cfgctxts
) {
2313 int nctxts
= dd
->first_user_ctxt
+ num_online_cpus();
2317 else if (nctxts
<= 9)
2319 else if (nctxts
<= nchipctxts
)
2320 dd
->ctxtcnt
= nchipctxts
;
2321 } else if (qib_cfgctxts
<= nchipctxts
)
2322 dd
->ctxtcnt
= qib_cfgctxts
;
2323 if (!dd
->ctxtcnt
) /* none of the above, set to max */
2324 dd
->ctxtcnt
= nchipctxts
;
2327 * Chip can be configured for 5, 9, or 17 ctxts, and choice
2328 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
2329 * Lock to be paranoid about later motion, etc.
2331 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
2332 if (dd
->ctxtcnt
> 9)
2333 dd
->rcvctrl
|= 2ULL << IBA7220_R_CTXTCFG_SHIFT
;
2334 else if (dd
->ctxtcnt
> 5)
2335 dd
->rcvctrl
|= 1ULL << IBA7220_R_CTXTCFG_SHIFT
;
2336 /* else configure for default 5 receive ctxts */
2338 dd
->rcvctrl
|= 1ULL << QIB_7220_RcvCtrl_RcvQPMapEnable_LSB
;
2339 qib_write_kreg(dd
, kr_rcvctrl
, dd
->rcvctrl
);
2340 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
2342 /* kr_rcvegrcnt changes based on the number of contexts enabled */
2343 dd
->cspec
->rcvegrcnt
= qib_read_kreg32(dd
, kr_rcvegrcnt
);
2344 dd
->rcvhdrcnt
= max(dd
->cspec
->rcvegrcnt
, IBA7220_KRCVEGRCNT
);
2347 static int qib_7220_get_ib_cfg(struct qib_pportdata
*ppd
, int which
)
2350 u64 maskr
; /* right-justified mask */
2353 case QIB_IB_CFG_LWID_ENB
: /* Get allowed Link-width */
2354 ret
= ppd
->link_width_enabled
;
2357 case QIB_IB_CFG_LWID
: /* Get currently active Link-width */
2358 ret
= ppd
->link_width_active
;
2361 case QIB_IB_CFG_SPD_ENB
: /* Get allowed Link speeds */
2362 ret
= ppd
->link_speed_enabled
;
2365 case QIB_IB_CFG_SPD
: /* Get current Link spd */
2366 ret
= ppd
->link_speed_active
;
2369 case QIB_IB_CFG_RXPOL_ENB
: /* Get Auto-RX-polarity enable */
2370 lsb
= IBA7220_IBC_RXPOL_SHIFT
;
2371 maskr
= IBA7220_IBC_RXPOL_MASK
;
2374 case QIB_IB_CFG_LREV_ENB
: /* Get Auto-Lane-reversal enable */
2375 lsb
= IBA7220_IBC_LREV_SHIFT
;
2376 maskr
= IBA7220_IBC_LREV_MASK
;
2379 case QIB_IB_CFG_LINKLATENCY
:
2380 ret
= qib_read_kreg64(ppd
->dd
, kr_ibcddrstatus
)
2381 & IBA7220_DDRSTAT_LINKLAT_MASK
;
2384 case QIB_IB_CFG_OP_VLS
:
2385 ret
= ppd
->vls_operational
;
2388 case QIB_IB_CFG_VL_HIGH_CAP
:
2392 case QIB_IB_CFG_VL_LOW_CAP
:
2396 case QIB_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
2397 ret
= SYM_FIELD(ppd
->cpspec
->ibcctrl
, IBCCtrl
,
2401 case QIB_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
2402 ret
= SYM_FIELD(ppd
->cpspec
->ibcctrl
, IBCCtrl
,
2406 case QIB_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
2407 /* will only take effect when the link state changes */
2408 ret
= (ppd
->cpspec
->ibcctrl
&
2409 SYM_MASK(IBCCtrl
, LinkDownDefaultState
)) ?
2410 IB_LINKINITCMD_SLEEP
: IB_LINKINITCMD_POLL
;
2413 case QIB_IB_CFG_HRTBT
: /* Get Heartbeat off/enable/auto */
2414 lsb
= IBA7220_IBC_HRTBT_SHIFT
;
2415 maskr
= IBA7220_IBC_HRTBT_MASK
;
2418 case QIB_IB_CFG_PMA_TICKS
:
2420 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
2421 * Since the clock is always 250MHz, the value is 1 or 0.
2423 ret
= (ppd
->link_speed_active
== QIB_IB_DDR
);
2430 ret
= (int)((ppd
->cpspec
->ibcddrctrl
>> lsb
) & maskr
);
2435 static int qib_7220_set_ib_cfg(struct qib_pportdata
*ppd
, int which
, u32 val
)
2437 struct qib_devdata
*dd
= ppd
->dd
;
2438 u64 maskr
; /* right-justified mask */
2439 int lsb
, ret
= 0, setforce
= 0;
2441 unsigned long flags
;
2445 case QIB_IB_CFG_LIDLMC
:
2447 * Set LID and LMC. Combined to avoid possible hazard
2448 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
2450 lsb
= IBA7220_IBC_DLIDLMC_SHIFT
;
2451 maskr
= IBA7220_IBC_DLIDLMC_MASK
;
2454 case QIB_IB_CFG_LWID_ENB
: /* set allowed Link-width */
2456 * As with speed, only write the actual register if
2457 * the link is currently down, otherwise takes effect
2458 * on next link change.
2460 ppd
->link_width_enabled
= val
;
2461 if (!(ppd
->lflags
& QIBL_LINKDOWN
))
2464 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2465 * will get called because we want update
2466 * link_width_active, and the change may not take
2467 * effect for some time (if we are in POLL), so this
2468 * flag will force the updown routine to be called
2469 * on the next ibstatuschange down interrupt, even
2470 * if it's not an down->up transition.
2472 val
--; /* convert from IB to chip */
2473 maskr
= IBA7220_IBC_WIDTH_MASK
;
2474 lsb
= IBA7220_IBC_WIDTH_SHIFT
;
2478 case QIB_IB_CFG_SPD_ENB
: /* set allowed Link speeds */
2480 * If we turn off IB1.2, need to preset SerDes defaults,
2481 * but not right now. Set a flag for the next time
2482 * we command the link down. As with width, only write the
2483 * actual register if the link is currently down, otherwise
2484 * takes effect on next link change. Since setting is being
2485 * explicitly requested (via MAD or sysfs), clear autoneg
2486 * failure status if speed autoneg is enabled.
2488 ppd
->link_speed_enabled
= val
;
2489 if ((ppd
->cpspec
->ibcddrctrl
& IBA7220_IBC_IBTA_1_2_MASK
) &&
2491 dd
->cspec
->presets_needed
= 1;
2492 if (!(ppd
->lflags
& QIBL_LINKDOWN
))
2495 * We set the QIBL_IB_FORCE_NOTIFY bit so updown
2496 * will get called because we want update
2497 * link_speed_active, and the change may not take
2498 * effect for some time (if we are in POLL), so this
2499 * flag will force the updown routine to be called
2500 * on the next ibstatuschange down interrupt, even
2501 * if it's not an down->up transition.
2503 if (val
== (QIB_IB_SDR
| QIB_IB_DDR
)) {
2504 val
= IBA7220_IBC_SPEED_AUTONEG_MASK
|
2505 IBA7220_IBC_IBTA_1_2_MASK
;
2506 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2507 ppd
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
2508 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2510 val
= val
== QIB_IB_DDR
?
2511 IBA7220_IBC_SPEED_DDR
: IBA7220_IBC_SPEED_SDR
;
2512 maskr
= IBA7220_IBC_SPEED_AUTONEG_MASK
|
2513 IBA7220_IBC_IBTA_1_2_MASK
;
2514 /* IBTA 1.2 mode + speed bits are contiguous */
2515 lsb
= SYM_LSB(IBCDDRCtrl
, IB_ENHANCED_MODE
);
2519 case QIB_IB_CFG_RXPOL_ENB
: /* set Auto-RX-polarity enable */
2520 lsb
= IBA7220_IBC_RXPOL_SHIFT
;
2521 maskr
= IBA7220_IBC_RXPOL_MASK
;
2524 case QIB_IB_CFG_LREV_ENB
: /* set Auto-Lane-reversal enable */
2525 lsb
= IBA7220_IBC_LREV_SHIFT
;
2526 maskr
= IBA7220_IBC_LREV_MASK
;
2529 case QIB_IB_CFG_OVERRUN_THRESH
: /* IB overrun threshold */
2530 maskr
= SYM_FIELD(ppd
->cpspec
->ibcctrl
, IBCCtrl
,
2533 ppd
->cpspec
->ibcctrl
&=
2534 ~SYM_MASK(IBCCtrl
, OverrunThreshold
);
2535 ppd
->cpspec
->ibcctrl
|= (u64
) val
<<
2536 SYM_LSB(IBCCtrl
, OverrunThreshold
);
2537 qib_write_kreg(dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
);
2538 qib_write_kreg(dd
, kr_scratch
, 0);
2542 case QIB_IB_CFG_PHYERR_THRESH
: /* IB PHY error threshold */
2543 maskr
= SYM_FIELD(ppd
->cpspec
->ibcctrl
, IBCCtrl
,
2546 ppd
->cpspec
->ibcctrl
&=
2547 ~SYM_MASK(IBCCtrl
, PhyerrThreshold
);
2548 ppd
->cpspec
->ibcctrl
|= (u64
) val
<<
2549 SYM_LSB(IBCCtrl
, PhyerrThreshold
);
2550 qib_write_kreg(dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
);
2551 qib_write_kreg(dd
, kr_scratch
, 0);
2555 case QIB_IB_CFG_PKEYS
: /* update pkeys */
2556 maskr
= (u64
) ppd
->pkeys
[0] | ((u64
) ppd
->pkeys
[1] << 16) |
2557 ((u64
) ppd
->pkeys
[2] << 32) |
2558 ((u64
) ppd
->pkeys
[3] << 48);
2559 qib_write_kreg(dd
, kr_partitionkey
, maskr
);
2562 case QIB_IB_CFG_LINKDEFAULT
: /* IB link default (sleep/poll) */
2563 /* will only take effect when the link state changes */
2564 if (val
== IB_LINKINITCMD_POLL
)
2565 ppd
->cpspec
->ibcctrl
&=
2566 ~SYM_MASK(IBCCtrl
, LinkDownDefaultState
);
2568 ppd
->cpspec
->ibcctrl
|=
2569 SYM_MASK(IBCCtrl
, LinkDownDefaultState
);
2570 qib_write_kreg(dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
);
2571 qib_write_kreg(dd
, kr_scratch
, 0);
2574 case QIB_IB_CFG_MTU
: /* update the MTU in IBC */
2576 * Update our housekeeping variables, and set IBC max
2577 * size, same as init code; max IBC is max we allow in
2578 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
2579 * Set even if it's unchanged, print debug message only
2582 val
= (ppd
->ibmaxlen
>> 2) + 1;
2583 ppd
->cpspec
->ibcctrl
&= ~SYM_MASK(IBCCtrl
, MaxPktLen
);
2584 ppd
->cpspec
->ibcctrl
|= (u64
)val
<< SYM_LSB(IBCCtrl
, MaxPktLen
);
2585 qib_write_kreg(dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
);
2586 qib_write_kreg(dd
, kr_scratch
, 0);
2589 case QIB_IB_CFG_LSTATE
: /* set the IB link state */
2590 switch (val
& 0xffff0000) {
2591 case IB_LINKCMD_DOWN
:
2592 lcmd
= QLOGIC_IB_IBCC_LINKCMD_DOWN
;
2593 if (!ppd
->cpspec
->ibdeltainprog
&&
2594 qib_compat_ddr_negotiate
) {
2595 ppd
->cpspec
->ibdeltainprog
= 1;
2596 ppd
->cpspec
->ibsymsnap
=
2597 read_7220_creg32(dd
, cr_ibsymbolerr
);
2598 ppd
->cpspec
->iblnkerrsnap
=
2599 read_7220_creg32(dd
, cr_iblinkerrrecov
);
2603 case IB_LINKCMD_ARMED
:
2604 lcmd
= QLOGIC_IB_IBCC_LINKCMD_ARMED
;
2607 case IB_LINKCMD_ACTIVE
:
2608 lcmd
= QLOGIC_IB_IBCC_LINKCMD_ACTIVE
;
2613 qib_dev_err(dd
, "bad linkcmd req 0x%x\n", val
>> 16);
2616 switch (val
& 0xffff) {
2617 case IB_LINKINITCMD_NOP
:
2621 case IB_LINKINITCMD_POLL
:
2622 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_POLL
;
2625 case IB_LINKINITCMD_SLEEP
:
2626 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_SLEEP
;
2629 case IB_LINKINITCMD_DISABLE
:
2630 licmd
= QLOGIC_IB_IBCC_LINKINITCMD_DISABLE
;
2631 ppd
->cpspec
->chase_end
= 0;
2633 * stop state chase counter and timer, if running.
2634 * wait forpending timer, but don't clear .data (ppd)!
2636 if (ppd
->cpspec
->chase_timer
.expires
) {
2637 del_timer_sync(&ppd
->cpspec
->chase_timer
);
2638 ppd
->cpspec
->chase_timer
.expires
= 0;
2644 qib_dev_err(dd
, "bad linkinitcmd req 0x%x\n",
2648 qib_set_ib_7220_lstate(ppd
, lcmd
, licmd
);
2650 maskr
= IBA7220_IBC_WIDTH_MASK
;
2651 lsb
= IBA7220_IBC_WIDTH_SHIFT
;
2652 tmp
= (ppd
->cpspec
->ibcddrctrl
>> lsb
) & maskr
;
2653 /* If the width active on the chip does not match the
2654 * width in the shadow register, write the new active
2655 * width to the chip.
2656 * We don't have to worry about speed as the speed is taken
2657 * care of by set_7220_ibspeed_fast called by ib_updown.
2659 if (ppd
->link_width_enabled
-1 != tmp
) {
2660 ppd
->cpspec
->ibcddrctrl
&= ~(maskr
<< lsb
);
2661 ppd
->cpspec
->ibcddrctrl
|=
2662 (((u64
)(ppd
->link_width_enabled
-1) & maskr
) <<
2664 qib_write_kreg(dd
, kr_ibcddrctrl
,
2665 ppd
->cpspec
->ibcddrctrl
);
2666 qib_write_kreg(dd
, kr_scratch
, 0);
2667 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2668 ppd
->lflags
|= QIBL_IB_FORCE_NOTIFY
;
2669 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2673 case QIB_IB_CFG_HRTBT
: /* set Heartbeat off/enable/auto */
2674 if (val
> IBA7220_IBC_HRTBT_MASK
) {
2678 lsb
= IBA7220_IBC_HRTBT_SHIFT
;
2679 maskr
= IBA7220_IBC_HRTBT_MASK
;
2686 ppd
->cpspec
->ibcddrctrl
&= ~(maskr
<< lsb
);
2687 ppd
->cpspec
->ibcddrctrl
|= (((u64
) val
& maskr
) << lsb
);
2688 qib_write_kreg(dd
, kr_ibcddrctrl
, ppd
->cpspec
->ibcddrctrl
);
2689 qib_write_kreg(dd
, kr_scratch
, 0);
2691 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
2692 ppd
->lflags
|= QIBL_IB_FORCE_NOTIFY
;
2693 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
2699 static int qib_7220_set_loopback(struct qib_pportdata
*ppd
, const char *what
)
2704 if (!strncmp(what
, "ibc", 3)) {
2705 ppd
->cpspec
->ibcctrl
|= SYM_MASK(IBCCtrl
, Loopback
);
2706 val
= 0; /* disable heart beat, so link will come up */
2707 qib_devinfo(ppd
->dd
->pcidev
, "Enabling IB%u:%u IBC loopback\n",
2708 ppd
->dd
->unit
, ppd
->port
);
2709 } else if (!strncmp(what
, "off", 3)) {
2710 ppd
->cpspec
->ibcctrl
&= ~SYM_MASK(IBCCtrl
, Loopback
);
2711 /* enable heart beat again */
2712 val
= IBA7220_IBC_HRTBT_MASK
<< IBA7220_IBC_HRTBT_SHIFT
;
2713 qib_devinfo(ppd
->dd
->pcidev
,
2714 "Disabling IB%u:%u IBC loopback (normal)\n",
2715 ppd
->dd
->unit
, ppd
->port
);
2719 qib_write_kreg(ppd
->dd
, kr_ibcctrl
, ppd
->cpspec
->ibcctrl
);
2720 ddr
= ppd
->cpspec
->ibcddrctrl
& ~(IBA7220_IBC_HRTBT_MASK
2721 << IBA7220_IBC_HRTBT_SHIFT
);
2722 ppd
->cpspec
->ibcddrctrl
= ddr
| val
;
2723 qib_write_kreg(ppd
->dd
, kr_ibcddrctrl
,
2724 ppd
->cpspec
->ibcddrctrl
);
2725 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
2730 static void qib_update_7220_usrhead(struct qib_ctxtdata
*rcd
, u64 hd
,
2731 u32 updegr
, u32 egrhd
, u32 npkts
)
2734 qib_write_ureg(rcd
->dd
, ur_rcvegrindexhead
, egrhd
, rcd
->ctxt
);
2736 qib_write_ureg(rcd
->dd
, ur_rcvhdrhead
, hd
, rcd
->ctxt
);
2740 static u32
qib_7220_hdrqempty(struct qib_ctxtdata
*rcd
)
2744 head
= qib_read_ureg32(rcd
->dd
, ur_rcvhdrhead
, rcd
->ctxt
);
2745 if (rcd
->rcvhdrtail_kvaddr
)
2746 tail
= qib_get_rcvhdrtail(rcd
);
2748 tail
= qib_read_ureg32(rcd
->dd
, ur_rcvhdrtail
, rcd
->ctxt
);
2749 return head
== tail
;
2753 * Modify the RCVCTRL register in chip-specific way. This
2754 * is a function because bit positions and (future) register
2755 * location is chip-specifc, but the needed operations are
2756 * generic. <op> is a bit-mask because we often want to
2757 * do multiple modifications.
2759 static void rcvctrl_7220_mod(struct qib_pportdata
*ppd
, unsigned int op
,
2762 struct qib_devdata
*dd
= ppd
->dd
;
2764 unsigned long flags
;
2766 spin_lock_irqsave(&dd
->cspec
->rcvmod_lock
, flags
);
2767 if (op
& QIB_RCVCTRL_TAILUPD_ENB
)
2768 dd
->rcvctrl
|= (1ULL << IBA7220_R_TAILUPD_SHIFT
);
2769 if (op
& QIB_RCVCTRL_TAILUPD_DIS
)
2770 dd
->rcvctrl
&= ~(1ULL << IBA7220_R_TAILUPD_SHIFT
);
2771 if (op
& QIB_RCVCTRL_PKEY_ENB
)
2772 dd
->rcvctrl
&= ~(1ULL << IBA7220_R_PKEY_DIS_SHIFT
);
2773 if (op
& QIB_RCVCTRL_PKEY_DIS
)
2774 dd
->rcvctrl
|= (1ULL << IBA7220_R_PKEY_DIS_SHIFT
);
2776 mask
= (1ULL << dd
->ctxtcnt
) - 1;
2778 mask
= (1ULL << ctxt
);
2779 if (op
& QIB_RCVCTRL_CTXT_ENB
) {
2780 /* always done for specific ctxt */
2781 dd
->rcvctrl
|= (mask
<< SYM_LSB(RcvCtrl
, PortEnable
));
2782 if (!(dd
->flags
& QIB_NODMA_RTAIL
))
2783 dd
->rcvctrl
|= 1ULL << IBA7220_R_TAILUPD_SHIFT
;
2784 /* Write these registers before the context is enabled. */
2785 qib_write_kreg_ctxt(dd
, kr_rcvhdrtailaddr
, ctxt
,
2786 dd
->rcd
[ctxt
]->rcvhdrqtailaddr_phys
);
2787 qib_write_kreg_ctxt(dd
, kr_rcvhdraddr
, ctxt
,
2788 dd
->rcd
[ctxt
]->rcvhdrq_phys
);
2789 dd
->rcd
[ctxt
]->seq_cnt
= 1;
2791 if (op
& QIB_RCVCTRL_CTXT_DIS
)
2792 dd
->rcvctrl
&= ~(mask
<< SYM_LSB(RcvCtrl
, PortEnable
));
2793 if (op
& QIB_RCVCTRL_INTRAVAIL_ENB
)
2794 dd
->rcvctrl
|= (mask
<< IBA7220_R_INTRAVAIL_SHIFT
);
2795 if (op
& QIB_RCVCTRL_INTRAVAIL_DIS
)
2796 dd
->rcvctrl
&= ~(mask
<< IBA7220_R_INTRAVAIL_SHIFT
);
2797 qib_write_kreg(dd
, kr_rcvctrl
, dd
->rcvctrl
);
2798 if ((op
& QIB_RCVCTRL_INTRAVAIL_ENB
) && dd
->rhdrhead_intr_off
) {
2799 /* arm rcv interrupt */
2800 val
= qib_read_ureg32(dd
, ur_rcvhdrhead
, ctxt
) |
2801 dd
->rhdrhead_intr_off
;
2802 qib_write_ureg(dd
, ur_rcvhdrhead
, val
, ctxt
);
2804 if (op
& QIB_RCVCTRL_CTXT_ENB
) {
2806 * Init the context registers also; if we were
2807 * disabled, tail and head should both be zero
2808 * already from the enable, but since we don't
2809 * know, we have to do it explicitly.
2811 val
= qib_read_ureg32(dd
, ur_rcvegrindextail
, ctxt
);
2812 qib_write_ureg(dd
, ur_rcvegrindexhead
, val
, ctxt
);
2814 val
= qib_read_ureg32(dd
, ur_rcvhdrtail
, ctxt
);
2815 dd
->rcd
[ctxt
]->head
= val
;
2816 /* If kctxt, interrupt on next receive. */
2817 if (ctxt
< dd
->first_user_ctxt
)
2818 val
|= dd
->rhdrhead_intr_off
;
2819 qib_write_ureg(dd
, ur_rcvhdrhead
, val
, ctxt
);
2821 if (op
& QIB_RCVCTRL_CTXT_DIS
) {
2823 qib_write_kreg_ctxt(dd
, kr_rcvhdrtailaddr
, ctxt
, 0);
2824 qib_write_kreg_ctxt(dd
, kr_rcvhdraddr
, ctxt
, 0);
2828 for (i
= 0; i
< dd
->cfgctxts
; i
++) {
2829 qib_write_kreg_ctxt(dd
, kr_rcvhdrtailaddr
,
2831 qib_write_kreg_ctxt(dd
, kr_rcvhdraddr
, i
, 0);
2835 spin_unlock_irqrestore(&dd
->cspec
->rcvmod_lock
, flags
);
2839 * Modify the SENDCTRL register in chip-specific way. This
2840 * is a function there may be multiple such registers with
2841 * slightly different layouts. To start, we assume the
2842 * "canonical" register layout of the first chips.
2843 * Chip requires no back-back sendctrl writes, so write
2844 * scratch register after writing sendctrl
2846 static void sendctrl_7220_mod(struct qib_pportdata
*ppd
, u32 op
)
2848 struct qib_devdata
*dd
= ppd
->dd
;
2849 u64 tmp_dd_sendctrl
;
2850 unsigned long flags
;
2852 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
2854 /* First the ones that are "sticky", saved in shadow */
2855 if (op
& QIB_SENDCTRL_CLEAR
)
2857 if (op
& QIB_SENDCTRL_SEND_DIS
)
2858 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, SPioEnable
);
2859 else if (op
& QIB_SENDCTRL_SEND_ENB
) {
2860 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SPioEnable
);
2861 if (dd
->flags
& QIB_USE_SPCL_TRIG
)
2862 dd
->sendctrl
|= SYM_MASK(SendCtrl
,
2865 if (op
& QIB_SENDCTRL_AVAIL_DIS
)
2866 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, SendBufAvailUpd
);
2867 else if (op
& QIB_SENDCTRL_AVAIL_ENB
)
2868 dd
->sendctrl
|= SYM_MASK(SendCtrl
, SendBufAvailUpd
);
2870 if (op
& QIB_SENDCTRL_DISARM_ALL
) {
2873 tmp_dd_sendctrl
= dd
->sendctrl
;
2875 * disarm any that are not yet launched, disabling sends
2876 * and updates until done.
2878 last
= dd
->piobcnt2k
+ dd
->piobcnt4k
;
2880 ~(SYM_MASK(SendCtrl
, SPioEnable
) |
2881 SYM_MASK(SendCtrl
, SendBufAvailUpd
));
2882 for (i
= 0; i
< last
; i
++) {
2883 qib_write_kreg(dd
, kr_sendctrl
,
2885 SYM_MASK(SendCtrl
, Disarm
) | i
);
2886 qib_write_kreg(dd
, kr_scratch
, 0);
2890 tmp_dd_sendctrl
= dd
->sendctrl
;
2892 if (op
& QIB_SENDCTRL_FLUSH
)
2893 tmp_dd_sendctrl
|= SYM_MASK(SendCtrl
, Abort
);
2894 if (op
& QIB_SENDCTRL_DISARM
)
2895 tmp_dd_sendctrl
|= SYM_MASK(SendCtrl
, Disarm
) |
2896 ((op
& QIB_7220_SendCtrl_DisarmPIOBuf_RMASK
) <<
2897 SYM_LSB(SendCtrl
, DisarmPIOBuf
));
2898 if ((op
& QIB_SENDCTRL_AVAIL_BLIP
) &&
2899 (dd
->sendctrl
& SYM_MASK(SendCtrl
, SendBufAvailUpd
)))
2900 tmp_dd_sendctrl
&= ~SYM_MASK(SendCtrl
, SendBufAvailUpd
);
2902 qib_write_kreg(dd
, kr_sendctrl
, tmp_dd_sendctrl
);
2903 qib_write_kreg(dd
, kr_scratch
, 0);
2905 if (op
& QIB_SENDCTRL_AVAIL_BLIP
) {
2906 qib_write_kreg(dd
, kr_sendctrl
, dd
->sendctrl
);
2907 qib_write_kreg(dd
, kr_scratch
, 0);
2910 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
2912 if (op
& QIB_SENDCTRL_FLUSH
) {
2915 * ensure writes have hit chip, then do a few
2916 * more reads, to allow DMA of pioavail registers
2917 * to occur, so in-memory copy is in sync with
2918 * the chip. Not always safe to sleep.
2920 v
= qib_read_kreg32(dd
, kr_scratch
);
2921 qib_write_kreg(dd
, kr_scratch
, v
);
2922 v
= qib_read_kreg32(dd
, kr_scratch
);
2923 qib_write_kreg(dd
, kr_scratch
, v
);
2924 qib_read_kreg32(dd
, kr_scratch
);
2929 * qib_portcntr_7220 - read a per-port counter
2930 * @dd: the qlogic_ib device
2931 * @creg: the counter to snapshot
2933 static u64
qib_portcntr_7220(struct qib_pportdata
*ppd
, u32 reg
)
2936 struct qib_devdata
*dd
= ppd
->dd
;
2938 /* 0xffff for unimplemented or synthesized counters */
2939 static const u16 xlator
[] = {
2940 [QIBPORTCNTR_PKTSEND
] = cr_pktsend
,
2941 [QIBPORTCNTR_WORDSEND
] = cr_wordsend
,
2942 [QIBPORTCNTR_PSXMITDATA
] = cr_psxmitdatacount
,
2943 [QIBPORTCNTR_PSXMITPKTS
] = cr_psxmitpktscount
,
2944 [QIBPORTCNTR_PSXMITWAIT
] = cr_psxmitwaitcount
,
2945 [QIBPORTCNTR_SENDSTALL
] = cr_sendstall
,
2946 [QIBPORTCNTR_PKTRCV
] = cr_pktrcv
,
2947 [QIBPORTCNTR_PSRCVDATA
] = cr_psrcvdatacount
,
2948 [QIBPORTCNTR_PSRCVPKTS
] = cr_psrcvpktscount
,
2949 [QIBPORTCNTR_RCVEBP
] = cr_rcvebp
,
2950 [QIBPORTCNTR_RCVOVFL
] = cr_rcvovfl
,
2951 [QIBPORTCNTR_WORDRCV
] = cr_wordrcv
,
2952 [QIBPORTCNTR_RXDROPPKT
] = cr_rxdroppkt
,
2953 [QIBPORTCNTR_RXLOCALPHYERR
] = cr_rxotherlocalphyerr
,
2954 [QIBPORTCNTR_RXVLERR
] = cr_rxvlerr
,
2955 [QIBPORTCNTR_ERRICRC
] = cr_erricrc
,
2956 [QIBPORTCNTR_ERRVCRC
] = cr_errvcrc
,
2957 [QIBPORTCNTR_ERRLPCRC
] = cr_errlpcrc
,
2958 [QIBPORTCNTR_BADFORMAT
] = cr_badformat
,
2959 [QIBPORTCNTR_ERR_RLEN
] = cr_err_rlen
,
2960 [QIBPORTCNTR_IBSYMBOLERR
] = cr_ibsymbolerr
,
2961 [QIBPORTCNTR_INVALIDRLEN
] = cr_invalidrlen
,
2962 [QIBPORTCNTR_UNSUPVL
] = cr_txunsupvl
,
2963 [QIBPORTCNTR_EXCESSBUFOVFL
] = cr_excessbufferovfl
,
2964 [QIBPORTCNTR_ERRLINK
] = cr_errlink
,
2965 [QIBPORTCNTR_IBLINKDOWN
] = cr_iblinkdown
,
2966 [QIBPORTCNTR_IBLINKERRRECOV
] = cr_iblinkerrrecov
,
2967 [QIBPORTCNTR_LLI
] = cr_locallinkintegrityerr
,
2968 [QIBPORTCNTR_PSINTERVAL
] = cr_psinterval
,
2969 [QIBPORTCNTR_PSSTART
] = cr_psstart
,
2970 [QIBPORTCNTR_PSSTAT
] = cr_psstat
,
2971 [QIBPORTCNTR_VL15PKTDROP
] = cr_vl15droppedpkt
,
2972 [QIBPORTCNTR_ERRPKEY
] = cr_errpkey
,
2973 [QIBPORTCNTR_KHDROVFL
] = 0xffff,
2976 if (reg
>= ARRAY_SIZE(xlator
)) {
2977 qib_devinfo(ppd
->dd
->pcidev
,
2978 "Unimplemented portcounter %u\n", reg
);
2983 if (reg
== QIBPORTCNTR_KHDROVFL
) {
2986 /* sum over all kernel contexts */
2987 for (i
= 0; i
< dd
->first_user_ctxt
; i
++)
2988 ret
+= read_7220_creg32(dd
, cr_portovfl
+ i
);
2994 * only fast incrementing counters are 64bit; use 32 bit reads to
2995 * avoid two independent reads when on opteron
2997 if ((creg
== cr_wordsend
|| creg
== cr_wordrcv
||
2998 creg
== cr_pktsend
|| creg
== cr_pktrcv
))
2999 ret
= read_7220_creg(dd
, creg
);
3001 ret
= read_7220_creg32(dd
, creg
);
3002 if (creg
== cr_ibsymbolerr
) {
3003 if (dd
->pport
->cpspec
->ibdeltainprog
)
3004 ret
-= ret
- ppd
->cpspec
->ibsymsnap
;
3005 ret
-= dd
->pport
->cpspec
->ibsymdelta
;
3006 } else if (creg
== cr_iblinkerrrecov
) {
3007 if (dd
->pport
->cpspec
->ibdeltainprog
)
3008 ret
-= ret
- ppd
->cpspec
->iblnkerrsnap
;
3009 ret
-= dd
->pport
->cpspec
->iblnkerrdelta
;
3016 * Device counter names (not port-specific), one line per stat,
3017 * single string. Used by utilities like ipathstats to print the stats
3018 * in a way which works for different versions of drivers, without changing
3019 * the utility. Names need to be 12 chars or less (w/o newline), for proper
3020 * display by utility.
3021 * Non-error counters are first.
3022 * Start of "error" conters is indicated by a leading "E " on the first
3023 * "error" counter, and doesn't count in label length.
3024 * The EgrOvfl list needs to be last so we truncate them at the configured
3025 * context count for the device.
3026 * cntr7220indices contains the corresponding register indices.
3028 static const char cntr7220names
[] =
3051 static const size_t cntr7220indices
[] = {
3076 * same as cntr7220names and cntr7220indices, but for port-specific counters.
3077 * portcntr7220indices is somewhat complicated by some registers needing
3078 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
3080 static const char portcntr7220names
[] =
3088 "TxDmaDesc\n" /* 7220 and 7322-only */
3089 "E RxDlidFltr\n" /* 7220 and 7322-only */
3112 "RxLclPhyErr\n" /* 7220 and 7322-only */
3113 "RxVL15Drop\n" /* 7220 and 7322-only */
3114 "RxVlErr\n" /* 7220 and 7322-only */
3115 "XcessBufOvfl\n" /* 7220 and 7322-only */
3118 #define _PORT_VIRT_FLAG 0x8000 /* "virtual", need adjustments */
3119 static const size_t portcntr7220indices
[] = {
3120 QIBPORTCNTR_PKTSEND
| _PORT_VIRT_FLAG
,
3122 QIBPORTCNTR_WORDSEND
| _PORT_VIRT_FLAG
,
3123 QIBPORTCNTR_PKTRCV
| _PORT_VIRT_FLAG
,
3125 QIBPORTCNTR_WORDRCV
| _PORT_VIRT_FLAG
,
3126 QIBPORTCNTR_SENDSTALL
| _PORT_VIRT_FLAG
,
3130 QIBPORTCNTR_IBLINKDOWN
| _PORT_VIRT_FLAG
,
3131 QIBPORTCNTR_IBLINKERRRECOV
| _PORT_VIRT_FLAG
,
3132 QIBPORTCNTR_ERRLINK
| _PORT_VIRT_FLAG
,
3133 QIBPORTCNTR_IBSYMBOLERR
| _PORT_VIRT_FLAG
,
3134 QIBPORTCNTR_LLI
| _PORT_VIRT_FLAG
,
3135 QIBPORTCNTR_BADFORMAT
| _PORT_VIRT_FLAG
,
3136 QIBPORTCNTR_ERR_RLEN
| _PORT_VIRT_FLAG
,
3137 QIBPORTCNTR_RCVOVFL
| _PORT_VIRT_FLAG
,
3138 QIBPORTCNTR_RCVEBP
| _PORT_VIRT_FLAG
,
3140 QIBPORTCNTR_ERRICRC
| _PORT_VIRT_FLAG
,
3141 QIBPORTCNTR_ERRLPCRC
| _PORT_VIRT_FLAG
,
3142 QIBPORTCNTR_ERRVCRC
| _PORT_VIRT_FLAG
,
3143 QIBPORTCNTR_INVALIDRLEN
| _PORT_VIRT_FLAG
,
3144 QIBPORTCNTR_ERRPKEY
| _PORT_VIRT_FLAG
,
3145 QIBPORTCNTR_RXDROPPKT
| _PORT_VIRT_FLAG
,
3151 QIBPORTCNTR_RXLOCALPHYERR
| _PORT_VIRT_FLAG
,
3152 QIBPORTCNTR_VL15PKTDROP
| _PORT_VIRT_FLAG
,
3153 QIBPORTCNTR_RXVLERR
| _PORT_VIRT_FLAG
,
3154 QIBPORTCNTR_EXCESSBUFOVFL
| _PORT_VIRT_FLAG
,
3157 /* do all the setup to make the counter reads efficient later */
3158 static void init_7220_cntrnames(struct qib_devdata
*dd
)
3163 for (i
= 0, s
= (char *)cntr7220names
; s
&& j
<= dd
->cfgctxts
;
3165 /* we always have at least one counter before the egrovfl */
3166 if (!j
&& !strncmp("Ctxt0EgrOvfl", s
+ 1, 12))
3168 s
= strchr(s
+ 1, '\n');
3172 dd
->cspec
->ncntrs
= i
;
3174 /* full list; size is without terminating null */
3175 dd
->cspec
->cntrnamelen
= sizeof(cntr7220names
) - 1;
3177 dd
->cspec
->cntrnamelen
= 1 + s
- cntr7220names
;
3178 dd
->cspec
->cntrs
= kmalloc(dd
->cspec
->ncntrs
3179 * sizeof(u64
), GFP_KERNEL
);
3181 for (i
= 0, s
= (char *)portcntr7220names
; s
; i
++)
3182 s
= strchr(s
+ 1, '\n');
3183 dd
->cspec
->nportcntrs
= i
- 1;
3184 dd
->cspec
->portcntrnamelen
= sizeof(portcntr7220names
) - 1;
3185 dd
->cspec
->portcntrs
= kmalloc(dd
->cspec
->nportcntrs
3186 * sizeof(u64
), GFP_KERNEL
);
3189 static u32
qib_read_7220cntrs(struct qib_devdata
*dd
, loff_t pos
, char **namep
,
3194 if (!dd
->cspec
->cntrs
) {
3200 *namep
= (char *)cntr7220names
;
3201 ret
= dd
->cspec
->cntrnamelen
;
3203 ret
= 0; /* final read after getting everything */
3205 u64
*cntr
= dd
->cspec
->cntrs
;
3208 ret
= dd
->cspec
->ncntrs
* sizeof(u64
);
3209 if (!cntr
|| pos
>= ret
) {
3210 /* everything read, or couldn't get memory */
3216 for (i
= 0; i
< dd
->cspec
->ncntrs
; i
++)
3217 *cntr
++ = read_7220_creg32(dd
, cntr7220indices
[i
]);
3223 static u32
qib_read_7220portcntrs(struct qib_devdata
*dd
, loff_t pos
, u32 port
,
3224 char **namep
, u64
**cntrp
)
3228 if (!dd
->cspec
->portcntrs
) {
3233 *namep
= (char *)portcntr7220names
;
3234 ret
= dd
->cspec
->portcntrnamelen
;
3236 ret
= 0; /* final read after getting everything */
3238 u64
*cntr
= dd
->cspec
->portcntrs
;
3239 struct qib_pportdata
*ppd
= &dd
->pport
[port
];
3242 ret
= dd
->cspec
->nportcntrs
* sizeof(u64
);
3243 if (!cntr
|| pos
>= ret
) {
3244 /* everything read, or couldn't get memory */
3249 for (i
= 0; i
< dd
->cspec
->nportcntrs
; i
++) {
3250 if (portcntr7220indices
[i
] & _PORT_VIRT_FLAG
)
3251 *cntr
++ = qib_portcntr_7220(ppd
,
3252 portcntr7220indices
[i
] &
3255 *cntr
++ = read_7220_creg32(dd
,
3256 portcntr7220indices
[i
]);
3264 * qib_get_7220_faststats - get word counters from chip before they overflow
3265 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
3267 * This needs more work; in particular, decision on whether we really
3268 * need traffic_wds done the way it is
3269 * called from add_timer
3271 static void qib_get_7220_faststats(unsigned long opaque
)
3273 struct qib_devdata
*dd
= (struct qib_devdata
*) opaque
;
3274 struct qib_pportdata
*ppd
= dd
->pport
;
3275 unsigned long flags
;
3279 * don't access the chip while running diags, or memory diags can
3282 if (!(dd
->flags
& QIB_INITTED
) || dd
->diag_client
)
3283 /* but re-arm the timer, for diags case; won't hurt other */
3287 * We now try to maintain an activity timer, based on traffic
3288 * exceeding a threshold, so we need to check the word-counts
3289 * even if they are 64-bit.
3291 traffic_wds
= qib_portcntr_7220(ppd
, cr_wordsend
) +
3292 qib_portcntr_7220(ppd
, cr_wordrcv
);
3293 spin_lock_irqsave(&dd
->eep_st_lock
, flags
);
3294 traffic_wds
-= dd
->traffic_wds
;
3295 dd
->traffic_wds
+= traffic_wds
;
3296 spin_unlock_irqrestore(&dd
->eep_st_lock
, flags
);
3298 mod_timer(&dd
->stats_timer
, jiffies
+ HZ
* ACTIVITY_TIMER
);
3302 * If we are using MSI, try to fallback to INTx.
3304 static int qib_7220_intr_fallback(struct qib_devdata
*dd
)
3309 qib_devinfo(dd
->pcidev
,
3310 "MSI interrupt not detected, trying INTx interrupts\n");
3311 qib_7220_free_irq(dd
);
3312 qib_enable_intx(dd
->pcidev
);
3314 * Some newer kernels require free_irq before disable_msi,
3315 * and irq can be changed during disable and INTx enable
3316 * and we need to therefore use the pcidev->irq value,
3317 * not our saved MSI value.
3319 dd
->cspec
->irq
= dd
->pcidev
->irq
;
3320 qib_setup_7220_interrupt(dd
);
3325 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
3326 * than resetting the IBC or external link state, and useful in some
3327 * cases to cause some retraining. To do this right, we reset IBC
3330 static void qib_7220_xgxs_reset(struct qib_pportdata
*ppd
)
3333 struct qib_devdata
*dd
= ppd
->dd
;
3335 prev_val
= qib_read_kreg64(dd
, kr_xgxs_cfg
);
3336 val
= prev_val
| QLOGIC_IB_XGXS_RESET
;
3337 prev_val
&= ~QLOGIC_IB_XGXS_RESET
; /* be sure */
3338 qib_write_kreg(dd
, kr_control
,
3339 dd
->control
& ~QLOGIC_IB_C_LINKENABLE
);
3340 qib_write_kreg(dd
, kr_xgxs_cfg
, val
);
3341 qib_read_kreg32(dd
, kr_scratch
);
3342 qib_write_kreg(dd
, kr_xgxs_cfg
, prev_val
);
3343 qib_write_kreg(dd
, kr_control
, dd
->control
);
3347 * For this chip, we want to use the same buffer every time
3348 * when we are trying to bring the link up (they are always VL15
3349 * packets). At that link state the packet should always go out immediately
3350 * (or at least be discarded at the tx interface if the link is down).
3351 * If it doesn't, and the buffer isn't available, that means some other
3352 * sender has gotten ahead of us, and is preventing our packet from going
3353 * out. In that case, we flush all packets, and try again. If that still
3354 * fails, we fail the request, and hope things work the next time around.
3356 * We don't need very complicated heuristics on whether the packet had
3357 * time to go out or not, since even at SDR 1X, it goes out in very short
3358 * time periods, covered by the chip reads done here and as part of the
3361 static u32 __iomem
*get_7220_link_buf(struct qib_pportdata
*ppd
, u32
*bnum
)
3364 u32 lbuf
= ppd
->dd
->cspec
->lastbuf_for_pio
;
3366 unsigned long flags
;
3369 * always blip to get avail list updated, since it's almost
3370 * always needed, and is fairly cheap.
3372 sendctrl_7220_mod(ppd
->dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
3373 qib_read_kreg64(ppd
->dd
, kr_scratch
); /* extra chip flush */
3374 buf
= qib_getsendbuf_range(ppd
->dd
, bnum
, lbuf
, lbuf
);
3378 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
3379 if (ppd
->sdma_state
.current_state
== qib_sdma_state_s20_idle
&&
3380 ppd
->sdma_state
.current_state
!= qib_sdma_state_s00_hw_down
) {
3381 __qib_sdma_process_event(ppd
, qib_sdma_event_e00_go_hw_down
);
3385 qib_7220_sdma_hw_clean_up(ppd
);
3387 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
3390 qib_read_kreg64(ppd
->dd
, kr_scratch
); /* extra chip flush */
3391 buf
= qib_getsendbuf_range(ppd
->dd
, bnum
, lbuf
, lbuf
);
3398 * This code for non-IBTA-compliant IB speed negotiation is only known to
3399 * work for the SDR to DDR transition, and only between an HCA and a switch
3400 * with recent firmware. It is based on observed heuristics, rather than
3401 * actual knowledge of the non-compliant speed negotiation.
3402 * It has a number of hard-coded fields, since the hope is to rewrite this
3403 * when a spec is available on how the negoation is intended to work.
3405 static void autoneg_7220_sendpkt(struct qib_pportdata
*ppd
, u32
*hdr
,
3406 u32 dcnt
, u32
*data
)
3410 u32 __iomem
*piobuf
;
3412 struct qib_devdata
*dd
= ppd
->dd
;
3415 pbc
= 7 + dcnt
+ 1; /* 7 dword header, dword data, icrc */
3416 pbc
|= PBC_7220_VL15_SEND
;
3417 while (!(piobuf
= get_7220_link_buf(ppd
, &pnum
))) {
3422 sendctrl_7220_mod(dd
->pport
, QIB_SENDCTRL_DISARM_BUF(pnum
));
3423 writeq(pbc
, piobuf
);
3425 qib_pio_copy(piobuf
+ 2, hdr
, 7);
3426 qib_pio_copy(piobuf
+ 9, data
, dcnt
);
3427 if (dd
->flags
& QIB_USE_SPCL_TRIG
) {
3428 u32 spcl_off
= (pnum
>= dd
->piobcnt2k
) ? 2047 : 1023;
3431 __raw_writel(0xaebecede, piobuf
+ spcl_off
);
3434 qib_sendbuf_done(dd
, pnum
);
3438 * _start packet gets sent twice at start, _done gets sent twice at end
3440 static void autoneg_7220_send(struct qib_pportdata
*ppd
, int which
)
3442 struct qib_devdata
*dd
= ppd
->dd
;
3444 u32 dw
, i
, hcnt
, dcnt
, *data
;
3445 static u32 hdr
[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
3446 static u32 madpayload_start
[0x40] = {
3447 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3448 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3449 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
3451 static u32 madpayload_done
[0x40] = {
3452 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
3453 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
3454 0x40000001, 0x1388, 0x15e, /* rest 0's */
3457 dcnt
= ARRAY_SIZE(madpayload_start
);
3458 hcnt
= ARRAY_SIZE(hdr
);
3460 /* for maintainability, do it at runtime */
3461 for (i
= 0; i
< hcnt
; i
++) {
3462 dw
= (__force u32
) cpu_to_be32(hdr
[i
]);
3465 for (i
= 0; i
< dcnt
; i
++) {
3466 dw
= (__force u32
) cpu_to_be32(madpayload_start
[i
]);
3467 madpayload_start
[i
] = dw
;
3468 dw
= (__force u32
) cpu_to_be32(madpayload_done
[i
]);
3469 madpayload_done
[i
] = dw
;
3474 data
= which
? madpayload_done
: madpayload_start
;
3476 autoneg_7220_sendpkt(ppd
, hdr
, dcnt
, data
);
3477 qib_read_kreg64(dd
, kr_scratch
);
3479 autoneg_7220_sendpkt(ppd
, hdr
, dcnt
, data
);
3480 qib_read_kreg64(dd
, kr_scratch
);
3485 * Do the absolute minimum to cause an IB speed change, and make it
3486 * ready, but don't actually trigger the change. The caller will
3487 * do that when ready (if link is in Polling training state, it will
3488 * happen immediately, otherwise when link next goes down)
3490 * This routine should only be used as part of the DDR autonegotation
3491 * code for devices that are not compliant with IB 1.2 (or code that
3492 * fixes things up for same).
3494 * When link has gone down, and autoneg enabled, or autoneg has
3495 * failed and we give up until next time we set both speeds, and
3496 * then we want IBTA enabled as well as "use max enabled speed.
3498 static void set_7220_ibspeed_fast(struct qib_pportdata
*ppd
, u32 speed
)
3500 ppd
->cpspec
->ibcddrctrl
&= ~(IBA7220_IBC_SPEED_AUTONEG_MASK
|
3501 IBA7220_IBC_IBTA_1_2_MASK
);
3503 if (speed
== (QIB_IB_SDR
| QIB_IB_DDR
))
3504 ppd
->cpspec
->ibcddrctrl
|= IBA7220_IBC_SPEED_AUTONEG_MASK
|
3505 IBA7220_IBC_IBTA_1_2_MASK
;
3507 ppd
->cpspec
->ibcddrctrl
|= speed
== QIB_IB_DDR
?
3508 IBA7220_IBC_SPEED_DDR
: IBA7220_IBC_SPEED_SDR
;
3510 qib_write_kreg(ppd
->dd
, kr_ibcddrctrl
, ppd
->cpspec
->ibcddrctrl
);
3511 qib_write_kreg(ppd
->dd
, kr_scratch
, 0);
3515 * This routine is only used when we are not talking to another
3516 * IB 1.2-compliant device that we think can do DDR.
3517 * (This includes all existing switch chips as of Oct 2007.)
3518 * 1.2-compliant devices go directly to DDR prior to reaching INIT
3520 static void try_7220_autoneg(struct qib_pportdata
*ppd
)
3522 unsigned long flags
;
3525 * Required for older non-IB1.2 DDR switches. Newer
3526 * non-IB-compliant switches don't need it, but so far,
3527 * aren't bothered by it either. "Magic constant"
3529 qib_write_kreg(ppd
->dd
, kr_ncmodectrl
, 0x3b9dc07);
3531 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3532 ppd
->lflags
|= QIBL_IB_AUTONEG_INPROG
;
3533 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
3534 autoneg_7220_send(ppd
, 0);
3535 set_7220_ibspeed_fast(ppd
, QIB_IB_DDR
);
3537 toggle_7220_rclkrls(ppd
->dd
);
3538 /* 2 msec is minimum length of a poll cycle */
3539 queue_delayed_work(ib_wq
, &ppd
->cpspec
->autoneg_work
,
3540 msecs_to_jiffies(2));
3544 * Handle the empirically determined mechanism for auto-negotiation
3545 * of DDR speed with switches.
3547 static void autoneg_7220_work(struct work_struct
*work
)
3549 struct qib_pportdata
*ppd
;
3550 struct qib_devdata
*dd
;
3553 unsigned long flags
;
3555 ppd
= &container_of(work
, struct qib_chippport_specific
,
3556 autoneg_work
.work
)->pportdata
;
3559 startms
= jiffies_to_msecs(jiffies
);
3562 * Busy wait for this first part, it should be at most a
3563 * few hundred usec, since we scheduled ourselves for 2msec.
3565 for (i
= 0; i
< 25; i
++) {
3566 if (SYM_FIELD(ppd
->lastibcstat
, IBCStatus
, LinkTrainingState
)
3567 == IB_7220_LT_STATE_POLLQUIET
) {
3568 qib_set_linkstate(ppd
, QIB_IB_LINKDOWN_DISABLE
);
3574 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
))
3575 goto done
; /* we got there early or told to stop */
3577 /* we expect this to timeout */
3578 if (wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
3579 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
3580 msecs_to_jiffies(90)))
3583 toggle_7220_rclkrls(dd
);
3585 /* we expect this to timeout */
3586 if (wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
3587 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
3588 msecs_to_jiffies(1700)))
3591 set_7220_ibspeed_fast(ppd
, QIB_IB_SDR
);
3592 toggle_7220_rclkrls(dd
);
3595 * Wait up to 250 msec for link to train and get to INIT at DDR;
3596 * this should terminate early.
3598 wait_event_timeout(ppd
->cpspec
->autoneg_wait
,
3599 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
),
3600 msecs_to_jiffies(250));
3602 if (ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) {
3603 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3604 ppd
->lflags
&= ~QIBL_IB_AUTONEG_INPROG
;
3605 if (dd
->cspec
->autoneg_tries
== AUTONEG_TRIES
) {
3606 ppd
->lflags
|= QIBL_IB_AUTONEG_FAILED
;
3607 dd
->cspec
->autoneg_tries
= 0;
3609 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
3610 set_7220_ibspeed_fast(ppd
, ppd
->link_speed_enabled
);
3614 static u32
qib_7220_iblink_state(u64 ibcs
)
3616 u32 state
= (u32
)SYM_FIELD(ibcs
, IBCStatus
, LinkState
);
3619 case IB_7220_L_STATE_INIT
:
3620 state
= IB_PORT_INIT
;
3622 case IB_7220_L_STATE_ARM
:
3623 state
= IB_PORT_ARMED
;
3625 case IB_7220_L_STATE_ACTIVE
:
3627 case IB_7220_L_STATE_ACT_DEFER
:
3628 state
= IB_PORT_ACTIVE
;
3630 default: /* fall through */
3631 case IB_7220_L_STATE_DOWN
:
3632 state
= IB_PORT_DOWN
;
3638 /* returns the IBTA port state, rather than the IBC link training state */
3639 static u8
qib_7220_phys_portstate(u64 ibcs
)
3641 u8 state
= (u8
)SYM_FIELD(ibcs
, IBCStatus
, LinkTrainingState
);
3642 return qib_7220_physportstate
[state
];
3645 static int qib_7220_ib_updown(struct qib_pportdata
*ppd
, int ibup
, u64 ibcs
)
3647 int ret
= 0, symadj
= 0;
3648 struct qib_devdata
*dd
= ppd
->dd
;
3649 unsigned long flags
;
3651 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3652 ppd
->lflags
&= ~QIBL_IB_FORCE_NOTIFY
;
3653 spin_unlock_irqrestore(&ppd
->lflags_lock
, flags
);
3657 * When the link goes down we don't want AEQ running, so it
3658 * won't interfere with IBC training, etc., and we need
3659 * to go back to the static SerDes preset values.
3661 if (!(ppd
->lflags
& (QIBL_IB_AUTONEG_FAILED
|
3662 QIBL_IB_AUTONEG_INPROG
)))
3663 set_7220_ibspeed_fast(ppd
, ppd
->link_speed_enabled
);
3664 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
)) {
3665 qib_sd7220_presets(dd
);
3666 qib_cancel_sends(ppd
); /* initial disarm, etc. */
3667 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
3668 if (__qib_sdma_running(ppd
))
3669 __qib_sdma_process_event(ppd
,
3670 qib_sdma_event_e70_go_idle
);
3671 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
3673 /* this might better in qib_sd7220_presets() */
3674 set_7220_relock_poll(dd
, ibup
);
3676 if (qib_compat_ddr_negotiate
&&
3677 !(ppd
->lflags
& (QIBL_IB_AUTONEG_FAILED
|
3678 QIBL_IB_AUTONEG_INPROG
)) &&
3679 ppd
->link_speed_active
== QIB_IB_SDR
&&
3680 (ppd
->link_speed_enabled
& (QIB_IB_DDR
| QIB_IB_SDR
)) ==
3681 (QIB_IB_DDR
| QIB_IB_SDR
) &&
3682 dd
->cspec
->autoneg_tries
< AUTONEG_TRIES
) {
3683 /* we are SDR, and DDR auto-negotiation enabled */
3684 ++dd
->cspec
->autoneg_tries
;
3685 if (!ppd
->cpspec
->ibdeltainprog
) {
3686 ppd
->cpspec
->ibdeltainprog
= 1;
3687 ppd
->cpspec
->ibsymsnap
= read_7220_creg32(dd
,
3689 ppd
->cpspec
->iblnkerrsnap
= read_7220_creg32(dd
,
3692 try_7220_autoneg(ppd
);
3693 ret
= 1; /* no other IB status change processing */
3694 } else if ((ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) &&
3695 ppd
->link_speed_active
== QIB_IB_SDR
) {
3696 autoneg_7220_send(ppd
, 1);
3697 set_7220_ibspeed_fast(ppd
, QIB_IB_DDR
);
3699 toggle_7220_rclkrls(dd
);
3700 ret
= 1; /* no other IB status change processing */
3702 if ((ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
) &&
3703 (ppd
->link_speed_active
& QIB_IB_DDR
)) {
3704 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3705 ppd
->lflags
&= ~(QIBL_IB_AUTONEG_INPROG
|
3706 QIBL_IB_AUTONEG_FAILED
);
3707 spin_unlock_irqrestore(&ppd
->lflags_lock
,
3709 dd
->cspec
->autoneg_tries
= 0;
3710 /* re-enable SDR, for next link down */
3711 set_7220_ibspeed_fast(ppd
,
3712 ppd
->link_speed_enabled
);
3713 wake_up(&ppd
->cpspec
->autoneg_wait
);
3715 } else if (ppd
->lflags
& QIBL_IB_AUTONEG_FAILED
) {
3717 * Clear autoneg failure flag, and do setup
3718 * so we'll try next time link goes down and
3719 * back to INIT (possibly connected to a
3720 * different device).
3722 spin_lock_irqsave(&ppd
->lflags_lock
, flags
);
3723 ppd
->lflags
&= ~QIBL_IB_AUTONEG_FAILED
;
3724 spin_unlock_irqrestore(&ppd
->lflags_lock
,
3726 ppd
->cpspec
->ibcddrctrl
|=
3727 IBA7220_IBC_IBTA_1_2_MASK
;
3728 qib_write_kreg(dd
, kr_ncmodectrl
, 0);
3733 if (!(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
))
3737 ppd
->delay_mult
= rate_to_delay
3738 [(ibcs
>> IBA7220_LINKSPEED_SHIFT
) & 1]
3739 [(ibcs
>> IBA7220_LINKWIDTH_SHIFT
) & 1];
3741 set_7220_relock_poll(dd
, ibup
);
3742 spin_lock_irqsave(&ppd
->sdma_lock
, flags
);
3744 * Unlike 7322, the 7220 needs this, due to lack of
3745 * interrupt in some cases when we have sdma active
3746 * when the link goes down.
3748 if (ppd
->sdma_state
.current_state
!=
3749 qib_sdma_state_s20_idle
)
3750 __qib_sdma_process_event(ppd
,
3751 qib_sdma_event_e00_go_hw_down
);
3752 spin_unlock_irqrestore(&ppd
->sdma_lock
, flags
);
3757 if (ppd
->cpspec
->ibdeltainprog
) {
3758 ppd
->cpspec
->ibdeltainprog
= 0;
3759 ppd
->cpspec
->ibsymdelta
+= read_7220_creg32(ppd
->dd
,
3760 cr_ibsymbolerr
) - ppd
->cpspec
->ibsymsnap
;
3761 ppd
->cpspec
->iblnkerrdelta
+= read_7220_creg32(ppd
->dd
,
3762 cr_iblinkerrrecov
) - ppd
->cpspec
->iblnkerrsnap
;
3764 } else if (!ibup
&& qib_compat_ddr_negotiate
&&
3765 !ppd
->cpspec
->ibdeltainprog
&&
3766 !(ppd
->lflags
& QIBL_IB_AUTONEG_INPROG
)) {
3767 ppd
->cpspec
->ibdeltainprog
= 1;
3768 ppd
->cpspec
->ibsymsnap
= read_7220_creg32(ppd
->dd
,
3770 ppd
->cpspec
->iblnkerrsnap
= read_7220_creg32(ppd
->dd
,
3775 qib_setup_7220_setextled(ppd
, ibup
);
3780 * Does read/modify/write to appropriate registers to
3781 * set output and direction bits selected by mask.
3782 * these are in their canonical postions (e.g. lsb of
3783 * dir will end up in D48 of extctrl on existing chips).
3784 * returns contents of GP Inputs.
3786 static int gpio_7220_mod(struct qib_devdata
*dd
, u32 out
, u32 dir
, u32 mask
)
3788 u64 read_val
, new_out
;
3789 unsigned long flags
;
3792 /* some bits being written, lock access to GPIO */
3795 spin_lock_irqsave(&dd
->cspec
->gpio_lock
, flags
);
3796 dd
->cspec
->extctrl
&= ~((u64
)mask
<< SYM_LSB(EXTCtrl
, GPIOOe
));
3797 dd
->cspec
->extctrl
|= ((u64
) dir
<< SYM_LSB(EXTCtrl
, GPIOOe
));
3798 new_out
= (dd
->cspec
->gpio_out
& ~mask
) | out
;
3800 qib_write_kreg(dd
, kr_extctrl
, dd
->cspec
->extctrl
);
3801 qib_write_kreg(dd
, kr_gpio_out
, new_out
);
3802 dd
->cspec
->gpio_out
= new_out
;
3803 spin_unlock_irqrestore(&dd
->cspec
->gpio_lock
, flags
);
3806 * It is unlikely that a read at this time would get valid
3807 * data on a pin whose direction line was set in the same
3808 * call to this function. We include the read here because
3809 * that allows us to potentially combine a change on one pin with
3810 * a read on another, and because the old code did something like
3813 read_val
= qib_read_kreg64(dd
, kr_extstatus
);
3814 return SYM_FIELD(read_val
, EXTStatus
, GPIOIn
);
3818 * Read fundamental info we need to use the chip. These are
3819 * the registers that describe chip capabilities, and are
3820 * saved in shadow registers.
3822 static void get_7220_chip_params(struct qib_devdata
*dd
)
3828 dd
->uregbase
= qib_read_kreg32(dd
, kr_userregbase
);
3830 dd
->rcvtidcnt
= qib_read_kreg32(dd
, kr_rcvtidcnt
);
3831 dd
->rcvtidbase
= qib_read_kreg32(dd
, kr_rcvtidbase
);
3832 dd
->rcvegrbase
= qib_read_kreg32(dd
, kr_rcvegrbase
);
3833 dd
->palign
= qib_read_kreg32(dd
, kr_palign
);
3834 dd
->piobufbase
= qib_read_kreg64(dd
, kr_sendpiobufbase
);
3835 dd
->pio2k_bufbase
= dd
->piobufbase
& 0xffffffff;
3837 val
= qib_read_kreg64(dd
, kr_sendpiosize
);
3838 dd
->piosize2k
= val
& ~0U;
3839 dd
->piosize4k
= val
>> 32;
3841 mtu
= ib_mtu_enum_to_int(qib_ibmtu
);
3843 mtu
= QIB_DEFAULT_MTU
;
3844 dd
->pport
->ibmtu
= (u32
)mtu
;
3846 val
= qib_read_kreg64(dd
, kr_sendpiobufcnt
);
3847 dd
->piobcnt2k
= val
& ~0U;
3848 dd
->piobcnt4k
= val
>> 32;
3849 /* these may be adjusted in init_chip_wc_pat() */
3850 dd
->pio2kbase
= (u32 __iomem
*)
3851 ((char __iomem
*) dd
->kregbase
+ dd
->pio2k_bufbase
);
3852 if (dd
->piobcnt4k
) {
3853 dd
->pio4kbase
= (u32 __iomem
*)
3854 ((char __iomem
*) dd
->kregbase
+
3855 (dd
->piobufbase
>> 32));
3857 * 4K buffers take 2 pages; we use roundup just to be
3858 * paranoid; we calculate it once here, rather than on
3861 dd
->align4k
= ALIGN(dd
->piosize4k
, dd
->palign
);
3864 piobufs
= dd
->piobcnt4k
+ dd
->piobcnt2k
;
3866 dd
->pioavregs
= ALIGN(piobufs
, sizeof(u64
) * BITS_PER_BYTE
/ 2) /
3867 (sizeof(u64
) * BITS_PER_BYTE
/ 2);
3871 * The chip base addresses in cspec and cpspec have to be set
3872 * after possible init_chip_wc_pat(), rather than in
3873 * qib_get_7220_chip_params(), so split out as separate function
3875 static void set_7220_baseaddrs(struct qib_devdata
*dd
)
3878 /* init after possible re-map in init_chip_wc_pat() */
3879 cregbase
= qib_read_kreg32(dd
, kr_counterregbase
);
3880 dd
->cspec
->cregbase
= (u64 __iomem
*)
3881 ((char __iomem
*) dd
->kregbase
+ cregbase
);
3883 dd
->egrtidbase
= (u64 __iomem
*)
3884 ((char __iomem
*) dd
->kregbase
+ dd
->rcvegrbase
);
3888 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl, SendIntBufAvail) | \
3889 SYM_MASK(SendCtrl, SPioEnable) | \
3890 SYM_MASK(SendCtrl, SSpecialTriggerEn) | \
3891 SYM_MASK(SendCtrl, SendBufAvailUpd) | \
3892 SYM_MASK(SendCtrl, AvailUpdThld) | \
3893 SYM_MASK(SendCtrl, SDmaEnable) | \
3894 SYM_MASK(SendCtrl, SDmaIntEnable) | \
3895 SYM_MASK(SendCtrl, SDmaHalt) | \
3896 SYM_MASK(SendCtrl, SDmaSingleDescriptor))
3898 static int sendctrl_hook(struct qib_devdata
*dd
,
3899 const struct diag_observer
*op
,
3900 u32 offs
, u64
*data
, u64 mask
, int only_32
)
3902 unsigned long flags
;
3903 unsigned idx
= offs
/ sizeof(u64
);
3904 u64 local_data
, all_bits
;
3906 if (idx
!= kr_sendctrl
) {
3907 qib_dev_err(dd
, "SendCtrl Hook called with offs %X, %s-bit\n",
3908 offs
, only_32
? "32" : "64");
3915 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
3916 if ((mask
& all_bits
) != all_bits
) {
3918 * At least some mask bits are zero, so we need
3919 * to read. The judgement call is whether from
3920 * reg or shadow. First-cut: read reg, and complain
3921 * if any bits which should be shadowed are different
3922 * from their shadowed value.
3925 local_data
= (u64
)qib_read_kreg32(dd
, idx
);
3927 local_data
= qib_read_kreg64(dd
, idx
);
3928 qib_dev_err(dd
, "Sendctrl -> %X, Shad -> %X\n",
3929 (u32
)local_data
, (u32
)dd
->sendctrl
);
3930 if ((local_data
& SENDCTRL_SHADOWED
) !=
3931 (dd
->sendctrl
& SENDCTRL_SHADOWED
))
3932 qib_dev_err(dd
, "Sendctrl read: %X shadow is %X\n",
3933 (u32
)local_data
, (u32
) dd
->sendctrl
);
3934 *data
= (local_data
& ~mask
) | (*data
& mask
);
3938 * At least some mask bits are one, so we need
3939 * to write, but only shadow some bits.
3941 u64 sval
, tval
; /* Shadowed, transient */
3944 * New shadow val is bits we don't want to touch,
3945 * ORed with bits we do, that are intended for shadow.
3947 sval
= (dd
->sendctrl
& ~mask
);
3948 sval
|= *data
& SENDCTRL_SHADOWED
& mask
;
3949 dd
->sendctrl
= sval
;
3950 tval
= sval
| (*data
& ~SENDCTRL_SHADOWED
& mask
);
3951 qib_dev_err(dd
, "Sendctrl <- %X, Shad <- %X\n",
3952 (u32
)tval
, (u32
)sval
);
3953 qib_write_kreg(dd
, kr_sendctrl
, tval
);
3954 qib_write_kreg(dd
, kr_scratch
, 0Ull);
3956 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
3958 return only_32
? 4 : 8;
3961 static const struct diag_observer sendctrl_observer
= {
3962 sendctrl_hook
, kr_sendctrl
* sizeof(u64
),
3963 kr_sendctrl
* sizeof(u64
)
3967 * write the final few registers that depend on some of the
3968 * init setup. Done late in init, just before bringing up
3971 static int qib_late_7220_initreg(struct qib_devdata
*dd
)
3976 qib_write_kreg(dd
, kr_rcvhdrentsize
, dd
->rcvhdrentsize
);
3977 qib_write_kreg(dd
, kr_rcvhdrsize
, dd
->rcvhdrsize
);
3978 qib_write_kreg(dd
, kr_rcvhdrcnt
, dd
->rcvhdrcnt
);
3979 qib_write_kreg(dd
, kr_sendpioavailaddr
, dd
->pioavailregs_phys
);
3980 val
= qib_read_kreg64(dd
, kr_sendpioavailaddr
);
3981 if (val
!= dd
->pioavailregs_phys
) {
3983 "Catastrophic software error, SendPIOAvailAddr written as %lx, read back as %llx\n",
3984 (unsigned long) dd
->pioavailregs_phys
,
3985 (unsigned long long) val
);
3988 qib_register_observer(dd
, &sendctrl_observer
);
3992 static int qib_init_7220_variables(struct qib_devdata
*dd
)
3994 struct qib_chippport_specific
*cpspec
;
3995 struct qib_pportdata
*ppd
;
3997 u32 sbufs
, updthresh
;
3999 cpspec
= (struct qib_chippport_specific
*)(dd
+ 1);
4000 ppd
= &cpspec
->pportdata
;
4004 dd
->cspec
= (struct qib_chip_specific
*)(cpspec
+ dd
->num_pports
);
4005 ppd
->cpspec
= cpspec
;
4007 spin_lock_init(&dd
->cspec
->sdepb_lock
);
4008 spin_lock_init(&dd
->cspec
->rcvmod_lock
);
4009 spin_lock_init(&dd
->cspec
->gpio_lock
);
4011 /* we haven't yet set QIB_PRESENT, so use read directly */
4012 dd
->revision
= readq(&dd
->kregbase
[kr_revision
]);
4014 if ((dd
->revision
& 0xffffffffU
) == 0xffffffffU
) {
4016 "Revision register read failure, giving up initialization\n");
4020 dd
->flags
|= QIB_PRESENT
; /* now register routines work */
4022 dd
->majrev
= (u8
) SYM_FIELD(dd
->revision
, Revision_R
,
4024 dd
->minrev
= (u8
) SYM_FIELD(dd
->revision
, Revision_R
,
4027 get_7220_chip_params(dd
);
4028 qib_7220_boardname(dd
);
4031 * GPIO bits for TWSI data and clock,
4032 * used for serial EEPROM.
4034 dd
->gpio_sda_num
= _QIB_GPIO_SDA_NUM
;
4035 dd
->gpio_scl_num
= _QIB_GPIO_SCL_NUM
;
4036 dd
->twsi_eeprom_dev
= QIB_TWSI_EEPROM_DEV
;
4038 dd
->flags
|= QIB_HAS_INTX
| QIB_HAS_LINK_LATENCY
|
4039 QIB_NODMA_RTAIL
| QIB_HAS_THRESH_UPDATE
;
4040 dd
->flags
|= qib_special_trigger
?
4041 QIB_USE_SPCL_TRIG
: QIB_HAS_SEND_DMA
;
4044 * EEPROM error log 0 is TXE Parity errors. 1 is RXE Parity.
4045 * 2 is Some Misc, 3 is reserved for future.
4047 dd
->eep_st_masks
[0].hwerrs_to_log
= HWE_MASK(TXEMemParityErr
);
4049 dd
->eep_st_masks
[1].hwerrs_to_log
= HWE_MASK(RXEMemParityErr
);
4051 dd
->eep_st_masks
[2].errs_to_log
= ERR_MASK(ResetNegated
);
4053 init_waitqueue_head(&cpspec
->autoneg_wait
);
4054 INIT_DELAYED_WORK(&cpspec
->autoneg_work
, autoneg_7220_work
);
4056 ret
= qib_init_pportdata(ppd
, dd
, 0, 1);
4059 ppd
->link_width_supported
= IB_WIDTH_1X
| IB_WIDTH_4X
;
4060 ppd
->link_speed_supported
= QIB_IB_SDR
| QIB_IB_DDR
;
4062 ppd
->link_width_enabled
= ppd
->link_width_supported
;
4063 ppd
->link_speed_enabled
= ppd
->link_speed_supported
;
4065 * Set the initial values to reasonable default, will be set
4066 * for real when link is up.
4068 ppd
->link_width_active
= IB_WIDTH_4X
;
4069 ppd
->link_speed_active
= QIB_IB_SDR
;
4070 ppd
->delay_mult
= rate_to_delay
[0][1];
4071 ppd
->vls_supported
= IB_VL_VL0
;
4072 ppd
->vls_operational
= ppd
->vls_supported
;
4075 qib_write_kreg(dd
, kr_rcvbthqp
, QIB_KD_QP
);
4077 init_timer(&ppd
->cpspec
->chase_timer
);
4078 ppd
->cpspec
->chase_timer
.function
= reenable_7220_chase
;
4079 ppd
->cpspec
->chase_timer
.data
= (unsigned long)ppd
;
4081 qib_num_cfg_vls
= 1; /* if any 7220's, only one VL */
4083 dd
->rcvhdrentsize
= QIB_RCVHDR_ENTSIZE
;
4084 dd
->rcvhdrsize
= QIB_DFLT_RCVHDRSIZE
;
4086 dd
->rcvhdrentsize
- sizeof(u64
) / sizeof(u32
);
4088 /* we always allocate at least 2048 bytes for eager buffers */
4089 ret
= ib_mtu_enum_to_int(qib_ibmtu
);
4090 dd
->rcvegrbufsize
= ret
!= -1 ? max(ret
, 2048) : QIB_DEFAULT_MTU
;
4091 BUG_ON(!is_power_of_2(dd
->rcvegrbufsize
));
4092 dd
->rcvegrbufsize_shift
= ilog2(dd
->rcvegrbufsize
);
4094 qib_7220_tidtemplate(dd
);
4097 * We can request a receive interrupt for 1 or
4098 * more packets from current offset. For now, we set this
4099 * up for a single packet.
4101 dd
->rhdrhead_intr_off
= 1ULL << 32;
4103 /* setup the stats timer; the add_timer is done at end of init */
4104 init_timer(&dd
->stats_timer
);
4105 dd
->stats_timer
.function
= qib_get_7220_faststats
;
4106 dd
->stats_timer
.data
= (unsigned long) dd
;
4107 dd
->stats_timer
.expires
= jiffies
+ ACTIVITY_TIMER
* HZ
;
4110 * Control[4] has been added to change the arbitration within
4111 * the SDMA engine between favoring data fetches over descriptor
4112 * fetches. qib_sdma_fetch_arb==0 gives data fetches priority.
4114 if (qib_sdma_fetch_arb
)
4115 dd
->control
|= 1 << 4;
4117 dd
->ureg_align
= 0x10000; /* 64KB alignment */
4119 dd
->piosize2kmax_dwords
= (dd
->piosize2k
>> 2)-1;
4120 qib_7220_config_ctxts(dd
);
4121 qib_set_ctxtcnt(dd
); /* needed for PAT setup */
4123 ret
= init_chip_wc_pat(dd
, 0);
4126 set_7220_baseaddrs(dd
); /* set chip access pointers now */
4132 ret
= qib_create_ctxts(dd
);
4133 init_7220_cntrnames(dd
);
4135 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
4136 * reserve the update threshold amount for other kernel use, such
4137 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
4138 * unless we aren't enabling SDMA, in which case we want to use
4139 * all the 4k bufs for the kernel.
4140 * if this was less than the update threshold, we could wait
4141 * a long time for an update. Coded this way because we
4142 * sometimes change the update threshold for various reasons,
4143 * and we want this to remain robust.
4145 updthresh
= 8U; /* update threshold */
4146 if (dd
->flags
& QIB_HAS_SEND_DMA
) {
4147 dd
->cspec
->sdmabufcnt
= dd
->piobcnt4k
;
4148 sbufs
= updthresh
> 3 ? updthresh
: 3;
4150 dd
->cspec
->sdmabufcnt
= 0;
4151 sbufs
= dd
->piobcnt4k
;
4154 dd
->cspec
->lastbuf_for_pio
= dd
->piobcnt2k
+ dd
->piobcnt4k
-
4155 dd
->cspec
->sdmabufcnt
;
4156 dd
->lastctxt_piobuf
= dd
->cspec
->lastbuf_for_pio
- sbufs
;
4157 dd
->cspec
->lastbuf_for_pio
--; /* range is <= , not < */
4158 dd
->last_pio
= dd
->cspec
->lastbuf_for_pio
;
4159 dd
->pbufsctxt
= dd
->lastctxt_piobuf
/
4160 (dd
->cfgctxts
- dd
->first_user_ctxt
);
4163 * if we are at 16 user contexts, we will have one 7 sbufs
4164 * per context, so drop the update threshold to match. We
4165 * want to update before we actually run out, at low pbufs/ctxt
4166 * so give ourselves some margin
4168 if ((dd
->pbufsctxt
- 2) < updthresh
)
4169 updthresh
= dd
->pbufsctxt
- 2;
4171 dd
->cspec
->updthresh_dflt
= updthresh
;
4172 dd
->cspec
->updthresh
= updthresh
;
4174 /* before full enable, no interrupts, no locking needed */
4175 dd
->sendctrl
|= (updthresh
& SYM_RMASK(SendCtrl
, AvailUpdThld
))
4176 << SYM_LSB(SendCtrl
, AvailUpdThld
);
4178 dd
->psxmitwait_supported
= 1;
4179 dd
->psxmitwait_check_rate
= QIB_7220_PSXMITWAIT_CHECK_RATE
;
4184 static u32 __iomem
*qib_7220_getsendbuf(struct qib_pportdata
*ppd
, u64 pbc
,
4187 u32 first
, last
, plen
= pbc
& QIB_PBC_LENGTH_MASK
;
4188 struct qib_devdata
*dd
= ppd
->dd
;
4191 if (((pbc
>> 32) & PBC_7220_VL15_SEND_CTRL
) &&
4192 !(ppd
->lflags
& (QIBL_IB_AUTONEG_INPROG
| QIBL_LINKACTIVE
)))
4193 buf
= get_7220_link_buf(ppd
, pbufnum
);
4195 if ((plen
+ 1) > dd
->piosize2kmax_dwords
)
4196 first
= dd
->piobcnt2k
;
4199 /* try 4k if all 2k busy, so same last for both sizes */
4200 last
= dd
->cspec
->lastbuf_for_pio
;
4201 buf
= qib_getsendbuf_range(dd
, pbufnum
, first
, last
);
4206 /* these 2 "counters" are really control registers, and are always RW */
4207 static void qib_set_cntr_7220_sample(struct qib_pportdata
*ppd
, u32 intv
,
4210 write_7220_creg(ppd
->dd
, cr_psinterval
, intv
);
4211 write_7220_creg(ppd
->dd
, cr_psstart
, start
);
4215 * NOTE: no real attempt is made to generalize the SDMA stuff.
4216 * At some point "soon" we will have a new more generalized
4217 * set of sdma interface, and then we'll clean this up.
4220 /* Must be called with sdma_lock held, or before init finished */
4221 static void qib_sdma_update_7220_tail(struct qib_pportdata
*ppd
, u16 tail
)
4223 /* Commit writes to memory and advance the tail on the chip */
4225 ppd
->sdma_descq_tail
= tail
;
4226 qib_write_kreg(ppd
->dd
, kr_senddmatail
, tail
);
4229 static void qib_sdma_set_7220_desc_cnt(struct qib_pportdata
*ppd
, unsigned cnt
)
4233 static struct sdma_set_state_action sdma_7220_action_table
[] = {
4234 [qib_sdma_state_s00_hw_down
] = {
4238 .go_s99_running_tofalse
= 1,
4240 [qib_sdma_state_s10_hw_start_up_wait
] = {
4245 [qib_sdma_state_s20_idle
] = {
4250 [qib_sdma_state_s30_sw_clean_up_wait
] = {
4255 [qib_sdma_state_s40_hw_clean_up_wait
] = {
4260 [qib_sdma_state_s50_hw_halt_wait
] = {
4265 [qib_sdma_state_s99_running
] = {
4269 .go_s99_running_totrue
= 1,
4273 static void qib_7220_sdma_init_early(struct qib_pportdata
*ppd
)
4275 ppd
->sdma_state
.set_state_action
= sdma_7220_action_table
;
4278 static int init_sdma_7220_regs(struct qib_pportdata
*ppd
)
4280 struct qib_devdata
*dd
= ppd
->dd
;
4282 u64 senddmabufmask
[3] = { 0 };
4284 /* Set SendDmaBase */
4285 qib_write_kreg(dd
, kr_senddmabase
, ppd
->sdma_descq_phys
);
4286 qib_sdma_7220_setlengen(ppd
);
4287 qib_sdma_update_7220_tail(ppd
, 0); /* Set SendDmaTail */
4288 /* Set SendDmaHeadAddr */
4289 qib_write_kreg(dd
, kr_senddmaheadaddr
, ppd
->sdma_head_phys
);
4292 * Reserve all the former "kernel" piobufs, using high number range
4293 * so we get as many 4K buffers as possible
4295 n
= dd
->piobcnt2k
+ dd
->piobcnt4k
;
4296 i
= n
- dd
->cspec
->sdmabufcnt
;
4298 for (; i
< n
; ++i
) {
4299 unsigned word
= i
/ 64;
4300 unsigned bit
= i
& 63;
4303 senddmabufmask
[word
] |= 1ULL << bit
;
4305 qib_write_kreg(dd
, kr_senddmabufmask0
, senddmabufmask
[0]);
4306 qib_write_kreg(dd
, kr_senddmabufmask1
, senddmabufmask
[1]);
4307 qib_write_kreg(dd
, kr_senddmabufmask2
, senddmabufmask
[2]);
4309 ppd
->sdma_state
.first_sendbuf
= i
;
4310 ppd
->sdma_state
.last_sendbuf
= n
;
4315 /* sdma_lock must be held */
4316 static u16
qib_sdma_7220_gethead(struct qib_pportdata
*ppd
)
4318 struct qib_devdata
*dd
= ppd
->dd
;
4326 use_dmahead
= __qib_sdma_running(ppd
) &&
4327 (dd
->flags
& QIB_HAS_SDMA_TIMEOUT
);
4329 hwhead
= use_dmahead
?
4330 (u16
)le64_to_cpu(*ppd
->sdma_head_dma
) :
4331 (u16
)qib_read_kreg32(dd
, kr_senddmahead
);
4333 swhead
= ppd
->sdma_descq_head
;
4334 swtail
= ppd
->sdma_descq_tail
;
4335 cnt
= ppd
->sdma_descq_cnt
;
4337 if (swhead
< swtail
) {
4339 sane
= (hwhead
>= swhead
) & (hwhead
<= swtail
);
4340 } else if (swhead
> swtail
) {
4341 /* wrapped around */
4342 sane
= ((hwhead
>= swhead
) && (hwhead
< cnt
)) ||
4346 sane
= (hwhead
== swhead
);
4349 if (unlikely(!sane
)) {
4351 /* try one more time, directly from the register */
4355 /* assume no progress */
4362 static int qib_sdma_7220_busy(struct qib_pportdata
*ppd
)
4364 u64 hwstatus
= qib_read_kreg64(ppd
->dd
, kr_senddmastatus
);
4366 return (hwstatus
& SYM_MASK(SendDmaStatus
, ScoreBoardDrainInProg
)) ||
4367 (hwstatus
& SYM_MASK(SendDmaStatus
, AbortInProg
)) ||
4368 (hwstatus
& SYM_MASK(SendDmaStatus
, InternalSDmaEnable
)) ||
4369 !(hwstatus
& SYM_MASK(SendDmaStatus
, ScbEmpty
));
4373 * Compute the amount of delay before sending the next packet if the
4374 * port's send rate differs from the static rate set for the QP.
4375 * Since the delay affects this packet but the amount of the delay is
4376 * based on the length of the previous packet, use the last delay computed
4377 * and save the delay count for this packet to be used next time
4380 static u32
qib_7220_setpbc_control(struct qib_pportdata
*ppd
, u32 plen
,
4383 u8 snd_mult
= ppd
->delay_mult
;
4384 u8 rcv_mult
= ib_rate_to_delay
[srate
];
4385 u32 ret
= ppd
->cpspec
->last_delay_mult
;
4387 ppd
->cpspec
->last_delay_mult
= (rcv_mult
> snd_mult
) ?
4388 (plen
* (rcv_mult
- snd_mult
) + 1) >> 1 : 0;
4390 /* Indicate VL15, if necessary */
4392 ret
|= PBC_7220_VL15_SEND_CTRL
;
4396 static void qib_7220_initvl15_bufs(struct qib_devdata
*dd
)
4400 static void qib_7220_init_ctxt(struct qib_ctxtdata
*rcd
)
4403 rcd
->rcvegrcnt
= IBA7220_KRCVEGRCNT
;
4404 rcd
->rcvegr_tid_base
= 0;
4406 rcd
->rcvegrcnt
= rcd
->dd
->cspec
->rcvegrcnt
;
4407 rcd
->rcvegr_tid_base
= IBA7220_KRCVEGRCNT
+
4408 (rcd
->ctxt
- 1) * rcd
->rcvegrcnt
;
4412 static void qib_7220_txchk_change(struct qib_devdata
*dd
, u32 start
,
4413 u32 len
, u32 which
, struct qib_ctxtdata
*rcd
)
4416 unsigned long flags
;
4419 case TXCHK_CHG_TYPE_KERN
:
4420 /* see if we need to raise avail update threshold */
4421 spin_lock_irqsave(&dd
->uctxt_lock
, flags
);
4422 for (i
= dd
->first_user_ctxt
;
4423 dd
->cspec
->updthresh
!= dd
->cspec
->updthresh_dflt
4424 && i
< dd
->cfgctxts
; i
++)
4425 if (dd
->rcd
[i
] && dd
->rcd
[i
]->subctxt_cnt
&&
4426 ((dd
->rcd
[i
]->piocnt
/ dd
->rcd
[i
]->subctxt_cnt
) - 1)
4427 < dd
->cspec
->updthresh_dflt
)
4429 spin_unlock_irqrestore(&dd
->uctxt_lock
, flags
);
4430 if (i
== dd
->cfgctxts
) {
4431 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
4432 dd
->cspec
->updthresh
= dd
->cspec
->updthresh_dflt
;
4433 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, AvailUpdThld
);
4434 dd
->sendctrl
|= (dd
->cspec
->updthresh
&
4435 SYM_RMASK(SendCtrl
, AvailUpdThld
)) <<
4436 SYM_LSB(SendCtrl
, AvailUpdThld
);
4437 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
4438 sendctrl_7220_mod(dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
4441 case TXCHK_CHG_TYPE_USER
:
4442 spin_lock_irqsave(&dd
->sendctrl_lock
, flags
);
4443 if (rcd
&& rcd
->subctxt_cnt
&& ((rcd
->piocnt
4444 / rcd
->subctxt_cnt
) - 1) < dd
->cspec
->updthresh
) {
4445 dd
->cspec
->updthresh
= (rcd
->piocnt
/
4446 rcd
->subctxt_cnt
) - 1;
4447 dd
->sendctrl
&= ~SYM_MASK(SendCtrl
, AvailUpdThld
);
4448 dd
->sendctrl
|= (dd
->cspec
->updthresh
&
4449 SYM_RMASK(SendCtrl
, AvailUpdThld
))
4450 << SYM_LSB(SendCtrl
, AvailUpdThld
);
4451 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
4452 sendctrl_7220_mod(dd
->pport
, QIB_SENDCTRL_AVAIL_BLIP
);
4454 spin_unlock_irqrestore(&dd
->sendctrl_lock
, flags
);
4459 static void writescratch(struct qib_devdata
*dd
, u32 val
)
4461 qib_write_kreg(dd
, kr_scratch
, val
);
4464 #define VALID_TS_RD_REG_MASK 0xBF
4466 * qib_7220_tempsense_read - read register of temp sensor via TWSI
4467 * @dd: the qlogic_ib device
4468 * @regnum: register to read from
4470 * returns reg contents (0..255) or < 0 for error
4472 static int qib_7220_tempsense_rd(struct qib_devdata
*dd
, int regnum
)
4482 /* return a bogus value for (the one) register we do not have */
4483 if (!((1 << regnum
) & VALID_TS_RD_REG_MASK
)) {
4488 ret
= mutex_lock_interruptible(&dd
->eep_lock
);
4492 ret
= qib_twsi_blk_rd(dd
, QIB_TWSI_TEMP_DEV
, regnum
, &rdata
, 1);
4496 mutex_unlock(&dd
->eep_lock
);
4499 * There are three possibilities here:
4500 * ret is actual value (0..255)
4501 * ret is -ENXIO or -EINVAL from twsi code or this file
4502 * ret is -EINTR from mutex_lock_interruptible.
4508 #ifdef CONFIG_INFINIBAND_QIB_DCA
4509 static int qib_7220_notify_dca(struct qib_devdata
*dd
, unsigned long event
)
4515 /* Dummy function, as 7220 boards never disable EEPROM Write */
4516 static int qib_7220_eeprom_wen(struct qib_devdata
*dd
, int wen
)
4522 * qib_init_iba7220_funcs - set up the chip-specific function pointers
4523 * @dev: the pci_dev for qlogic_ib device
4524 * @ent: pci_device_id struct for this dev
4526 * This is global, and is called directly at init to set up the
4527 * chip-specific function pointers for later use.
4529 struct qib_devdata
*qib_init_iba7220_funcs(struct pci_dev
*pdev
,
4530 const struct pci_device_id
*ent
)
4532 struct qib_devdata
*dd
;
4534 u32 boardid
, minwidth
;
4536 dd
= qib_alloc_devdata(pdev
, sizeof(struct qib_chip_specific
) +
4537 sizeof(struct qib_chippport_specific
));
4541 dd
->f_bringup_serdes
= qib_7220_bringup_serdes
;
4542 dd
->f_cleanup
= qib_setup_7220_cleanup
;
4543 dd
->f_clear_tids
= qib_7220_clear_tids
;
4544 dd
->f_free_irq
= qib_7220_free_irq
;
4545 dd
->f_get_base_info
= qib_7220_get_base_info
;
4546 dd
->f_get_msgheader
= qib_7220_get_msgheader
;
4547 dd
->f_getsendbuf
= qib_7220_getsendbuf
;
4548 dd
->f_gpio_mod
= gpio_7220_mod
;
4549 dd
->f_eeprom_wen
= qib_7220_eeprom_wen
;
4550 dd
->f_hdrqempty
= qib_7220_hdrqempty
;
4551 dd
->f_ib_updown
= qib_7220_ib_updown
;
4552 dd
->f_init_ctxt
= qib_7220_init_ctxt
;
4553 dd
->f_initvl15_bufs
= qib_7220_initvl15_bufs
;
4554 dd
->f_intr_fallback
= qib_7220_intr_fallback
;
4555 dd
->f_late_initreg
= qib_late_7220_initreg
;
4556 dd
->f_setpbc_control
= qib_7220_setpbc_control
;
4557 dd
->f_portcntr
= qib_portcntr_7220
;
4558 dd
->f_put_tid
= qib_7220_put_tid
;
4559 dd
->f_quiet_serdes
= qib_7220_quiet_serdes
;
4560 dd
->f_rcvctrl
= rcvctrl_7220_mod
;
4561 dd
->f_read_cntrs
= qib_read_7220cntrs
;
4562 dd
->f_read_portcntrs
= qib_read_7220portcntrs
;
4563 dd
->f_reset
= qib_setup_7220_reset
;
4564 dd
->f_init_sdma_regs
= init_sdma_7220_regs
;
4565 dd
->f_sdma_busy
= qib_sdma_7220_busy
;
4566 dd
->f_sdma_gethead
= qib_sdma_7220_gethead
;
4567 dd
->f_sdma_sendctrl
= qib_7220_sdma_sendctrl
;
4568 dd
->f_sdma_set_desc_cnt
= qib_sdma_set_7220_desc_cnt
;
4569 dd
->f_sdma_update_tail
= qib_sdma_update_7220_tail
;
4570 dd
->f_sdma_hw_clean_up
= qib_7220_sdma_hw_clean_up
;
4571 dd
->f_sdma_hw_start_up
= qib_7220_sdma_hw_start_up
;
4572 dd
->f_sdma_init_early
= qib_7220_sdma_init_early
;
4573 dd
->f_sendctrl
= sendctrl_7220_mod
;
4574 dd
->f_set_armlaunch
= qib_set_7220_armlaunch
;
4575 dd
->f_set_cntr_sample
= qib_set_cntr_7220_sample
;
4576 dd
->f_iblink_state
= qib_7220_iblink_state
;
4577 dd
->f_ibphys_portstate
= qib_7220_phys_portstate
;
4578 dd
->f_get_ib_cfg
= qib_7220_get_ib_cfg
;
4579 dd
->f_set_ib_cfg
= qib_7220_set_ib_cfg
;
4580 dd
->f_set_ib_loopback
= qib_7220_set_loopback
;
4581 dd
->f_set_intr_state
= qib_7220_set_intr_state
;
4582 dd
->f_setextled
= qib_setup_7220_setextled
;
4583 dd
->f_txchk_change
= qib_7220_txchk_change
;
4584 dd
->f_update_usrhead
= qib_update_7220_usrhead
;
4585 dd
->f_wantpiobuf_intr
= qib_wantpiobuf_7220_intr
;
4586 dd
->f_xgxs_reset
= qib_7220_xgxs_reset
;
4587 dd
->f_writescratch
= writescratch
;
4588 dd
->f_tempsense_rd
= qib_7220_tempsense_rd
;
4589 #ifdef CONFIG_INFINIBAND_QIB_DCA
4590 dd
->f_notify_dca
= qib_7220_notify_dca
;
4593 * Do remaining pcie setup and save pcie values in dd.
4594 * Any error printing is already done by the init code.
4595 * On return, we have the chip mapped, but chip registers
4596 * are not set up until start of qib_init_7220_variables.
4598 ret
= qib_pcie_ddinit(dd
, pdev
, ent
);
4602 /* initialize chip-specific variables */
4603 ret
= qib_init_7220_variables(dd
);
4610 boardid
= SYM_FIELD(dd
->revision
, Revision
,
4617 minwidth
= 16; /* x16 capable boards */
4620 minwidth
= 8; /* x8 capable boards */
4623 if (qib_pcie_params(dd
, minwidth
, NULL
, NULL
))
4625 "Failed to setup PCIe or interrupts; continuing anyway\n");
4627 /* save IRQ for possible later use */
4628 dd
->cspec
->irq
= pdev
->irq
;
4630 if (qib_read_kreg64(dd
, kr_hwerrstatus
) &
4631 QLOGIC_IB_HWE_SERDESPLLFAILED
)
4632 qib_write_kreg(dd
, kr_hwerrclear
,
4633 QLOGIC_IB_HWE_SERDESPLLFAILED
);
4635 /* setup interrupt handler (interrupt type handled above) */
4636 qib_setup_7220_interrupt(dd
);
4637 qib_7220_init_hwerrors(dd
);
4639 /* clear diagctrl register, in case diags were running and crashed */
4640 qib_write_kreg(dd
, kr_hwdiagctrl
, 0);
4645 qib_pcie_ddcleanup(dd
);
4647 qib_free_devdata(dd
);