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1 /*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
45
46 #include "qib.h"
47 #include "qib_7322_regs.h"
48 #include "qib_qsfp.h"
49
50 #include "qib_mad.h"
51
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
66 u16 linitcmd);
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
71
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata *, int);
75 static int serdes_7322_init_old(struct qib_pportdata *);
76 static int serdes_7322_init_new(struct qib_pportdata *);
77
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
79
80 /* LE2 serdes values for different cases */
81 #define LE2_DEFAULT 5
82 #define LE2_5m 4
83 #define LE2_QME 0
84
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
87
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout = 375;
90 static const unsigned rcv_int_count = 16;
91 static const unsigned sdma_idle_cnt = 64;
92
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
95
96 /*
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
99 */
100 ushort qib_num_cfg_vls = 2;
101 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
103
104 static ushort qib_chase = 1;
105 module_param_named(chase, qib_chase, ushort, S_IRUGO);
106 MODULE_PARM_DESC(chase, "Enable state chase handling");
107
108 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110 MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
112
113 static ushort qib_singleport;
114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
116
117 /*
118 * Receive header queue sizes
119 */
120 static unsigned qib_rcvhdrcnt;
121 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
122 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
123
124 static unsigned qib_rcvhdrsize;
125 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
126 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
127
128 static unsigned qib_rcvhdrentsize;
129 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
130 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
131
132 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
133 /* for read back, default index is ~5m copper cable */
134 static char txselect_list[MAX_ATTEN_LEN] = "10";
135 static struct kparam_string kp_txselect = {
136 .string = txselect_list,
137 .maxlen = MAX_ATTEN_LEN
138 };
139 static int setup_txselect(const char *, struct kernel_param *);
140 module_param_call(txselect, setup_txselect, param_get_string,
141 &kp_txselect, S_IWUSR | S_IRUGO);
142 MODULE_PARM_DESC(txselect, \
143 "Tx serdes indices (for no QSFP or invalid QSFP data)");
144
145 #define BOARD_QME7342 5
146 #define BOARD_QMH7342 6
147 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
148 BOARD_QMH7342)
149 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
150 BOARD_QME7342)
151
152 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
153
154 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
155
156 #define MASK_ACROSS(lsb, msb) \
157 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
158
159 #define SYM_RMASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK)
161
162 #define SYM_MASK(regname, fldname) ((u64) \
163 QIB_7322_##regname##_##fldname##_RMASK << \
164 QIB_7322_##regname##_##fldname##_LSB)
165
166 #define SYM_FIELD(value, regname, fldname) ((u64) \
167 (((value) >> SYM_LSB(regname, fldname)) & \
168 SYM_RMASK(regname, fldname)))
169
170 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
171 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
172 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
173
174 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
175 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
176 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
177 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
178 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
179 /* Below because most, but not all, fields of IntMask have that full suffix */
180 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
181
182
183 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
184
185 /*
186 * the size bits give us 2^N, in KB units. 0 marks as invalid,
187 * and 7 is reserved. We currently use only 2KB and 4KB
188 */
189 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
190 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
191 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
192 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
193
194 #define SendIBSLIDAssignMask \
195 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
196 #define SendIBSLMCMask \
197 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
198
199 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
200 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
201 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
202 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
203 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
204 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
205
206 #define _QIB_GPIO_SDA_NUM 1
207 #define _QIB_GPIO_SCL_NUM 0
208 #define QIB_EEPROM_WEN_NUM 14
209 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
210
211 /* HW counter clock is at 4nsec */
212 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
213
214 /* full speed IB port 1 only */
215 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
216 #define PORT_SPD_CAP_SHIFT 3
217
218 /* full speed featuremask, both ports */
219 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
220
221 /*
222 * This file contains almost all the chip-specific register information and
223 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
224 */
225
226 /* Use defines to tie machine-generated names to lower-case names */
227 #define kr_contextcnt KREG_IDX(ContextCnt)
228 #define kr_control KREG_IDX(Control)
229 #define kr_counterregbase KREG_IDX(CntrRegBase)
230 #define kr_errclear KREG_IDX(ErrClear)
231 #define kr_errmask KREG_IDX(ErrMask)
232 #define kr_errstatus KREG_IDX(ErrStatus)
233 #define kr_extctrl KREG_IDX(EXTCtrl)
234 #define kr_extstatus KREG_IDX(EXTStatus)
235 #define kr_gpio_clear KREG_IDX(GPIOClear)
236 #define kr_gpio_mask KREG_IDX(GPIOMask)
237 #define kr_gpio_out KREG_IDX(GPIOOut)
238 #define kr_gpio_status KREG_IDX(GPIOStatus)
239 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
240 #define kr_debugportval KREG_IDX(DebugPortValueReg)
241 #define kr_fmask KREG_IDX(feature_mask)
242 #define kr_act_fmask KREG_IDX(active_feature_mask)
243 #define kr_hwerrclear KREG_IDX(HwErrClear)
244 #define kr_hwerrmask KREG_IDX(HwErrMask)
245 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
246 #define kr_intclear KREG_IDX(IntClear)
247 #define kr_intmask KREG_IDX(IntMask)
248 #define kr_intredirect KREG_IDX(IntRedirect0)
249 #define kr_intstatus KREG_IDX(IntStatus)
250 #define kr_pagealign KREG_IDX(PageAlign)
251 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
252 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
253 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
254 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
255 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
256 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
257 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
258 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
259 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
260 #define kr_revision KREG_IDX(Revision)
261 #define kr_scratch KREG_IDX(Scratch)
262 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
263 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
264 #define kr_sendctrl KREG_IDX(SendCtrl)
265 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
266 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
267 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
268 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
269 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
270 #define kr_sendpiosize KREG_IDX(SendBufSize)
271 #define kr_sendregbase KREG_IDX(SendRegBase)
272 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
273 #define kr_userregbase KREG_IDX(UserRegBase)
274 #define kr_intgranted KREG_IDX(Int_Granted)
275 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
276 #define kr_intblocked KREG_IDX(IntBlocked)
277 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
278
279 /*
280 * per-port kernel registers. Access only with qib_read_kreg_port()
281 * or qib_write_kreg_port()
282 */
283 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
284 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
285 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
286 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
287 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
288 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
289 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
290 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
291 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
292 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
293 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
294 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
295 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
296 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
297 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
298 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
299 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
300 #define krp_psstart KREG_IBPORT_IDX(PSStart)
301 #define krp_psstat KREG_IBPORT_IDX(PSStat)
302 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
303 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
304 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
305 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
306 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
307 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
308 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
309 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
310 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
311 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
312 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
313 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
314 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
315 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
316 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
317 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
318 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
319 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
320 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
321 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
322 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
323 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
324 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
325 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
326 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
327 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
328 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
329 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
330 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
331 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
332 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
333
334 /*
335 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
336 * or qib_write_kreg_ctxt()
337 */
338 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
339 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
340
341 /*
342 * TID Flow table, per context. Reduces
343 * number of hdrq updates to one per flow (or on errors).
344 * context 0 and 1 share same memory, but have distinct
345 * addresses. Since for now, we never use expected sends
346 * on kernel contexts, we don't worry about that (we initialize
347 * those entries for ctxt 0/1 on driver load twice, for example).
348 */
349 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
350 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
351
352 /* these are the error bits in the tid flows, and are W1C */
353 #define TIDFLOW_ERRBITS ( \
354 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
355 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
356 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
357 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
358
359 /* Most (not all) Counters are per-IBport.
360 * Requires LBIntCnt is at offset 0 in the group
361 */
362 #define CREG_IDX(regname) \
363 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
364
365 #define crp_badformat CREG_IDX(RxVersionErrCnt)
366 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
367 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
368 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
369 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
370 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
371 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
372 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
373 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
374 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
375 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
376 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
377 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
378 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
379 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
380 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
381 #define crp_pktsend CREG_IDX(TxDataPktCnt)
382 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
383 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
384 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
385 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
386 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
387 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
388 #define crp_rcvebp CREG_IDX(RxEBPCnt)
389 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
390 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
391 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
392 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
393 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
394 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
395 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
396 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
397 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
398 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
399 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
400 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
401 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
402 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
403 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
404 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
405 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
406 #define crp_wordrcv CREG_IDX(RxDwordCnt)
407 #define crp_wordsend CREG_IDX(TxDwordCnt)
408 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
409
410 /* these are the (few) counters that are not port-specific */
411 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
412 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
413 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
414 #define cr_lbint CREG_DEVIDX(LBIntCnt)
415 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
416 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
417 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
418 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
419 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
420
421 /* no chip register for # of IB ports supported, so define */
422 #define NUM_IB_PORTS 2
423
424 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
425 #define NUM_VL15_BUFS NUM_IB_PORTS
426
427 /*
428 * context 0 and 1 are special, and there is no chip register that
429 * defines this value, so we have to define it here.
430 * These are all allocated to either 0 or 1 for single port
431 * hardware configuration, otherwise each gets half
432 */
433 #define KCTXT0_EGRCNT 2048
434
435 /* values for vl and port fields in PBC, 7322-specific */
436 #define PBC_PORT_SEL_LSB 26
437 #define PBC_PORT_SEL_RMASK 1
438 #define PBC_VL_NUM_LSB 27
439 #define PBC_VL_NUM_RMASK 7
440 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
441 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
442
443 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
444 [IB_RATE_2_5_GBPS] = 16,
445 [IB_RATE_5_GBPS] = 8,
446 [IB_RATE_10_GBPS] = 4,
447 [IB_RATE_20_GBPS] = 2,
448 [IB_RATE_30_GBPS] = 2,
449 [IB_RATE_40_GBPS] = 1
450 };
451
452 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
453 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
454
455 /* link training states, from IBC */
456 #define IB_7322_LT_STATE_DISABLED 0x00
457 #define IB_7322_LT_STATE_LINKUP 0x01
458 #define IB_7322_LT_STATE_POLLACTIVE 0x02
459 #define IB_7322_LT_STATE_POLLQUIET 0x03
460 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
461 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
462 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
463 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
464 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
465 #define IB_7322_LT_STATE_CFGIDLE 0x0b
466 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
467 #define IB_7322_LT_STATE_TXREVLANES 0x0d
468 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
469 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
470 #define IB_7322_LT_STATE_CFGENH 0x10
471 #define IB_7322_LT_STATE_CFGTEST 0x11
472
473 /* link state machine states from IBC */
474 #define IB_7322_L_STATE_DOWN 0x0
475 #define IB_7322_L_STATE_INIT 0x1
476 #define IB_7322_L_STATE_ARM 0x2
477 #define IB_7322_L_STATE_ACTIVE 0x3
478 #define IB_7322_L_STATE_ACT_DEFER 0x4
479
480 static const u8 qib_7322_physportstate[0x20] = {
481 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
482 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
483 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
484 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
485 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
486 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
487 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
488 [IB_7322_LT_STATE_CFGRCVFCFG] =
489 IB_PHYSPORTSTATE_CFG_TRAIN,
490 [IB_7322_LT_STATE_CFGWAITRMT] =
491 IB_PHYSPORTSTATE_CFG_TRAIN,
492 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
493 [IB_7322_LT_STATE_RECOVERRETRAIN] =
494 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
495 [IB_7322_LT_STATE_RECOVERWAITRMT] =
496 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
497 [IB_7322_LT_STATE_RECOVERIDLE] =
498 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
499 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
500 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
501 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
502 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH,
503 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
505 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
506 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
507 };
508
509 struct qib_chip_specific {
510 u64 __iomem *cregbase;
511 u64 *cntrs;
512 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
513 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
514 u64 main_int_mask; /* clear bits which have dedicated handlers */
515 u64 int_enable_mask; /* for per port interrupts in single port mode */
516 u64 errormask;
517 u64 hwerrmask;
518 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
519 u64 gpio_mask; /* shadow the gpio mask register */
520 u64 extctrl; /* shadow the gpio output enable, etc... */
521 u32 ncntrs;
522 u32 nportcntrs;
523 u32 cntrnamelen;
524 u32 portcntrnamelen;
525 u32 numctxts;
526 u32 rcvegrcnt;
527 u32 updthresh; /* current AvailUpdThld */
528 u32 updthresh_dflt; /* default AvailUpdThld */
529 u32 r1;
530 int irq;
531 u32 num_msix_entries;
532 u32 sdmabufcnt;
533 u32 lastbuf_for_pio;
534 u32 stay_in_freeze;
535 u32 recovery_ports_initted;
536 struct msix_entry *msix_entries;
537 void **msix_arg;
538 unsigned long *sendchkenable;
539 unsigned long *sendgrhchk;
540 unsigned long *sendibchk;
541 u32 rcvavail_timeout[18];
542 char emsgbuf[128]; /* for device error interrupt msg buffer */
543 };
544
545 /* Table of entries in "human readable" form Tx Emphasis. */
546 struct txdds_ent {
547 u8 amp;
548 u8 pre;
549 u8 main;
550 u8 post;
551 };
552
553 struct vendor_txdds_ent {
554 u8 oui[QSFP_VOUI_LEN];
555 u8 *partnum;
556 struct txdds_ent sdr;
557 struct txdds_ent ddr;
558 struct txdds_ent qdr;
559 };
560
561 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
562
563 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
564 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
565 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
566 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
567
568 #define H1_FORCE_VAL 8
569 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
570 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
571
572 /* The static and dynamic registers are paired, and the pairs indexed by spd */
573 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
574 + ((spd) * 2))
575
576 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
577 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
578 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
579 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
580 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
581
582 struct qib_chippport_specific {
583 u64 __iomem *kpregbase;
584 u64 __iomem *cpregbase;
585 u64 *portcntrs;
586 struct qib_pportdata *ppd;
587 wait_queue_head_t autoneg_wait;
588 struct delayed_work autoneg_work;
589 struct delayed_work ipg_work;
590 struct timer_list chase_timer;
591 /*
592 * these 5 fields are used to establish deltas for IB symbol
593 * errors and linkrecovery errors. They can be reported on
594 * some chips during link negotiation prior to INIT, and with
595 * DDR when faking DDR negotiations with non-IBTA switches.
596 * The chip counters are adjusted at driver unload if there is
597 * a non-zero delta.
598 */
599 u64 ibdeltainprog;
600 u64 ibsymdelta;
601 u64 ibsymsnap;
602 u64 iblnkerrdelta;
603 u64 iblnkerrsnap;
604 u64 iblnkdownsnap;
605 u64 iblnkdowndelta;
606 u64 ibmalfdelta;
607 u64 ibmalfsnap;
608 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
609 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
610 u64 qdr_dfe_time;
611 u64 chase_end;
612 u32 autoneg_tries;
613 u32 recovery_init;
614 u32 qdr_dfe_on;
615 u32 qdr_reforce;
616 /*
617 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
618 * entry zero is unused, to simplify indexing
619 */
620 u8 h1_val;
621 u8 no_eep; /* txselect table index to use if no qsfp info */
622 u8 ipg_tries;
623 u8 ibmalfusesnap;
624 struct qib_qsfp_data qsfp_data;
625 char epmsgbuf[192]; /* for port error interrupt msg buffer */
626 u8 bounced;
627 };
628
629 static struct {
630 const char *name;
631 irq_handler_t handler;
632 int lsb;
633 int port; /* 0 if not port-specific, else port # */
634 } irq_table[] = {
635 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
636 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
637 SYM_LSB(IntStatus, SendBufAvail), 0 },
638 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
639 SYM_LSB(IntStatus, SDmaInt_0), 1 },
640 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
641 SYM_LSB(IntStatus, SDmaInt_1), 2 },
642 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
643 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
644 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
645 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
646 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
647 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
648 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
649 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
650 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
651 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
652 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
653 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
654 };
655
656 /* ibcctrl bits */
657 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
658 /* cycle through TS1/TS2 till OK */
659 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
660 /* wait for TS1, then go on */
661 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
662 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
663
664 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
665 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
666 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
667
668 #define BLOB_7322_IBCHG 0x101
669
670 static inline void qib_write_kreg(const struct qib_devdata *dd,
671 const u32 regno, u64 value);
672 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
673 static void write_7322_initregs(struct qib_devdata *);
674 static void write_7322_init_portregs(struct qib_pportdata *);
675 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
676 static void check_7322_rxe_status(struct qib_pportdata *);
677 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
678
679 /**
680 * qib_read_ureg32 - read 32-bit virtualized per-context register
681 * @dd: device
682 * @regno: register number
683 * @ctxt: context number
684 *
685 * Return the contents of a register that is virtualized to be per context.
686 * Returns -1 on errors (not distinguishable from valid contents at
687 * runtime; we may add a separate error variable at some point).
688 */
689 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
690 enum qib_ureg regno, int ctxt)
691 {
692 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
693 return 0;
694 return readl(regno + (u64 __iomem *)(
695 (dd->ureg_align * ctxt) + (dd->userbase ?
696 (char __iomem *)dd->userbase :
697 (char __iomem *)dd->kregbase + dd->uregbase)));
698 }
699
700 /**
701 * qib_read_ureg - read virtualized per-context register
702 * @dd: device
703 * @regno: register number
704 * @ctxt: context number
705 *
706 * Return the contents of a register that is virtualized to be per context.
707 * Returns -1 on errors (not distinguishable from valid contents at
708 * runtime; we may add a separate error variable at some point).
709 */
710 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
711 enum qib_ureg regno, int ctxt)
712 {
713
714 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
715 return 0;
716 return readq(regno + (u64 __iomem *)(
717 (dd->ureg_align * ctxt) + (dd->userbase ?
718 (char __iomem *)dd->userbase :
719 (char __iomem *)dd->kregbase + dd->uregbase)));
720 }
721
722 /**
723 * qib_write_ureg - write virtualized per-context register
724 * @dd: device
725 * @regno: register number
726 * @value: value
727 * @ctxt: context
728 *
729 * Write the contents of a register that is virtualized to be per context.
730 */
731 static inline void qib_write_ureg(const struct qib_devdata *dd,
732 enum qib_ureg regno, u64 value, int ctxt)
733 {
734 u64 __iomem *ubase;
735 if (dd->userbase)
736 ubase = (u64 __iomem *)
737 ((char __iomem *) dd->userbase +
738 dd->ureg_align * ctxt);
739 else
740 ubase = (u64 __iomem *)
741 (dd->uregbase +
742 (char __iomem *) dd->kregbase +
743 dd->ureg_align * ctxt);
744
745 if (dd->kregbase && (dd->flags & QIB_PRESENT))
746 writeq(value, &ubase[regno]);
747 }
748
749 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
750 const u32 regno)
751 {
752 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
753 return -1;
754 return readl((u32 __iomem *) &dd->kregbase[regno]);
755 }
756
757 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
758 const u32 regno)
759 {
760 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
761 return -1;
762 return readq(&dd->kregbase[regno]);
763 }
764
765 static inline void qib_write_kreg(const struct qib_devdata *dd,
766 const u32 regno, u64 value)
767 {
768 if (dd->kregbase && (dd->flags & QIB_PRESENT))
769 writeq(value, &dd->kregbase[regno]);
770 }
771
772 /*
773 * not many sanity checks for the port-specific kernel register routines,
774 * since they are only used when it's known to be safe.
775 */
776 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
777 const u16 regno)
778 {
779 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
780 return 0ULL;
781 return readq(&ppd->cpspec->kpregbase[regno]);
782 }
783
784 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
785 const u16 regno, u64 value)
786 {
787 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
788 (ppd->dd->flags & QIB_PRESENT))
789 writeq(value, &ppd->cpspec->kpregbase[regno]);
790 }
791
792 /**
793 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
794 * @dd: the qlogic_ib device
795 * @regno: the register number to write
796 * @ctxt: the context containing the register
797 * @value: the value to write
798 */
799 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
800 const u16 regno, unsigned ctxt,
801 u64 value)
802 {
803 qib_write_kreg(dd, regno + ctxt, value);
804 }
805
806 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
807 {
808 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
809 return 0;
810 return readq(&dd->cspec->cregbase[regno]);
811
812
813 }
814
815 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
816 {
817 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
818 return 0;
819 return readl(&dd->cspec->cregbase[regno]);
820
821
822 }
823
824 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
825 u16 regno, u64 value)
826 {
827 if (ppd->cpspec && ppd->cpspec->cpregbase &&
828 (ppd->dd->flags & QIB_PRESENT))
829 writeq(value, &ppd->cpspec->cpregbase[regno]);
830 }
831
832 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
833 u16 regno)
834 {
835 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
836 !(ppd->dd->flags & QIB_PRESENT))
837 return 0;
838 return readq(&ppd->cpspec->cpregbase[regno]);
839 }
840
841 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
842 u16 regno)
843 {
844 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
845 !(ppd->dd->flags & QIB_PRESENT))
846 return 0;
847 return readl(&ppd->cpspec->cpregbase[regno]);
848 }
849
850 /* bits in Control register */
851 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
852 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
853
854 /* bits in general interrupt regs */
855 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
856 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
857 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
858 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
859 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
860 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
861 #define QIB_I_C_ERROR INT_MASK(Err)
862
863 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
864 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
865 #define QIB_I_GPIO INT_MASK(AssertGPIO)
866 #define QIB_I_P_SDMAINT(pidx) \
867 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
868 INT_MASK_P(SDmaProgress, pidx) | \
869 INT_MASK_PM(SDmaCleanupDone, pidx))
870
871 /* Interrupt bits that are "per port" */
872 #define QIB_I_P_BITSEXTANT(pidx) \
873 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
874 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
875 INT_MASK_P(SDmaProgress, pidx) | \
876 INT_MASK_PM(SDmaCleanupDone, pidx))
877
878 /* Interrupt bits that are common to a device */
879 /* currently unused: QIB_I_SPIOSENT */
880 #define QIB_I_C_BITSEXTANT \
881 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
882 QIB_I_SPIOSENT | \
883 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
884
885 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
886 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
887
888 /*
889 * Error bits that are "per port".
890 */
891 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
892 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
893 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
894 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
895 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
896 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
897 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
898 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
899 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
900 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
901 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
902 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
903 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
904 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
905 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
906 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
907 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
908 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
909 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
910 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
911 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
912 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
913 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
914 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
915 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
916 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
917 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
918 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
919
920 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
921 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
922 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
923 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
924 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
925 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
926 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
927 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
928 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
929 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
930 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
931
932 /* Error bits that are common to a device */
933 #define QIB_E_RESET ERR_MASK(ResetNegated)
934 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
935 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
936
937
938 /*
939 * Per chip (rather than per-port) errors. Most either do
940 * nothing but trigger a print (because they self-recover, or
941 * always occur in tandem with other errors that handle the
942 * issue), or because they indicate errors with no recovery,
943 * but we want to know that they happened.
944 */
945 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
946 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
947 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
948 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
949 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
950 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
951 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
952 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
953
954 /* SDMA chip errors (not per port)
955 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
956 * the SDMAHALT error immediately, so we just print the dup error via the
957 * E_AUTO mechanism. This is true of most of the per-port fatal errors
958 * as well, but since this is port-independent, by definition, it's
959 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
960 * packet send errors, and so are handled in the same manner as other
961 * per-packet errors.
962 */
963 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
964 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
965 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
966
967 /*
968 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
969 * it is used to print "common" packet errors.
970 */
971 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
972 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
973 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
974 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
975 QIB_E_P_REBP)
976
977 /* Error Bits that Packet-related (Receive, per-port) */
978 #define QIB_E_P_RPKTERRS (\
979 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
980 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
981 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
982 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
983 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
984 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
985
986 /*
987 * Error bits that are Send-related (per port)
988 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
989 * All of these potentially need to have a buffer disarmed
990 */
991 #define QIB_E_P_SPKTERRS (\
992 QIB_E_P_SUNEXP_PKTNUM |\
993 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
994 QIB_E_P_SMAXPKTLEN |\
995 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
996 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
997 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
998
999 #define QIB_E_SPKTERRS ( \
1000 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1001 ERR_MASK_N(SendUnsupportedVLErr) | \
1002 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1003
1004 #define QIB_E_P_SDMAERRS ( \
1005 QIB_E_P_SDMAHALT | \
1006 QIB_E_P_SDMADESCADDRMISALIGN | \
1007 QIB_E_P_SDMAUNEXPDATA | \
1008 QIB_E_P_SDMAMISSINGDW | \
1009 QIB_E_P_SDMADWEN | \
1010 QIB_E_P_SDMARPYTAG | \
1011 QIB_E_P_SDMA1STDESC | \
1012 QIB_E_P_SDMABASE | \
1013 QIB_E_P_SDMATAILOUTOFBOUND | \
1014 QIB_E_P_SDMAOUTOFBOUND | \
1015 QIB_E_P_SDMAGENMISMATCH)
1016
1017 /*
1018 * This sets some bits more than once, but makes it more obvious which
1019 * bits are not handled under other categories, and the repeat definition
1020 * is not a problem.
1021 */
1022 #define QIB_E_P_BITSEXTANT ( \
1023 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1024 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1025 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1026 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1027 )
1028
1029 /*
1030 * These are errors that can occur when the link
1031 * changes state while a packet is being sent or received. This doesn't
1032 * cover things like EBP or VCRC that can be the result of a sending
1033 * having the link change state, so we receive a "known bad" packet.
1034 * All of these are "per port", so renamed:
1035 */
1036 #define QIB_E_P_LINK_PKTERRS (\
1037 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1038 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1039 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1040 QIB_E_P_RUNEXPCHAR)
1041
1042 /*
1043 * This sets some bits more than once, but makes it more obvious which
1044 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1045 * and the repeat definition is not a problem.
1046 */
1047 #define QIB_E_C_BITSEXTANT (\
1048 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1049 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1050 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1051
1052 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1053 #define E_SPKT_ERRS_IGNORE 0
1054
1055 #define QIB_EXTS_MEMBIST_DISABLED \
1056 SYM_MASK(EXTStatus, MemBISTDisabled)
1057 #define QIB_EXTS_MEMBIST_ENDTEST \
1058 SYM_MASK(EXTStatus, MemBISTEndTest)
1059
1060 #define QIB_E_SPIOARMLAUNCH \
1061 ERR_MASK(SendArmLaunchErr)
1062
1063 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1064 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1065
1066 /*
1067 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1068 * and also if forced QDR (only QDR enabled). It's enabled for the
1069 * forced QDR case so that scrambling will be enabled by the TS3
1070 * exchange, when supported by both sides of the link.
1071 */
1072 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1073 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1074 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1075 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1076 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1077 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1078 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1079 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1080
1081 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1082 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1083
1084 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1085 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1086 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1087
1088 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1089 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1090 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1091 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1092 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1093 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1094 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1095
1096 #define IBA7322_REDIRECT_VEC_PER_REG 12
1097
1098 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1099 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1100 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1101 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1102 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1103
1104 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1105
1106 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1107 .msg = #fldname }
1108 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1109 fldname##Mask##_##port), .msg = #fldname }
1110 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1111 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1112 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1113 HWE_AUTO(PCIESerdesPClkNotDetect),
1114 HWE_AUTO(PowerOnBISTFailed),
1115 HWE_AUTO(TempsenseTholdReached),
1116 HWE_AUTO(MemoryErr),
1117 HWE_AUTO(PCIeBusParityErr),
1118 HWE_AUTO(PcieCplTimeout),
1119 HWE_AUTO(PciePoisonedTLP),
1120 HWE_AUTO_P(SDmaMemReadErr, 1),
1121 HWE_AUTO_P(SDmaMemReadErr, 0),
1122 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1123 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1124 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1125 HWE_AUTO(statusValidNoEop),
1126 HWE_AUTO(LATriggered),
1127 { .mask = 0 }
1128 };
1129
1130 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1131 .msg = #fldname }
1132 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1133 .msg = #fldname }
1134 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1135 E_AUTO(ResetNegated),
1136 E_AUTO(HardwareErr),
1137 E_AUTO(InvalidAddrErr),
1138 E_AUTO(SDmaVL15Err),
1139 E_AUTO(SBufVL15MisUseErr),
1140 E_AUTO(InvalidEEPCmd),
1141 E_AUTO(RcvContextShareErr),
1142 E_AUTO(SendVLMismatchErr),
1143 E_AUTO(SendArmLaunchErr),
1144 E_AUTO(SendSpecialTriggerErr),
1145 E_AUTO(SDmaWrongPortErr),
1146 E_AUTO(SDmaBufMaskDuplicateErr),
1147 E_AUTO(RcvHdrFullErr),
1148 E_AUTO(RcvEgrFullErr),
1149 { .mask = 0 }
1150 };
1151
1152 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1153 E_P_AUTO(IBStatusChanged),
1154 E_P_AUTO(SHeadersErr),
1155 E_P_AUTO(VL15BufMisuseErr),
1156 /*
1157 * SDmaHaltErr is not really an error, make it clearer;
1158 */
1159 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1160 E_P_AUTO(SDmaDescAddrMisalignErr),
1161 E_P_AUTO(SDmaUnexpDataErr),
1162 E_P_AUTO(SDmaMissingDwErr),
1163 E_P_AUTO(SDmaDwEnErr),
1164 E_P_AUTO(SDmaRpyTagErr),
1165 E_P_AUTO(SDma1stDescErr),
1166 E_P_AUTO(SDmaBaseErr),
1167 E_P_AUTO(SDmaTailOutOfBoundErr),
1168 E_P_AUTO(SDmaOutOfBoundErr),
1169 E_P_AUTO(SDmaGenMismatchErr),
1170 E_P_AUTO(SendBufMisuseErr),
1171 E_P_AUTO(SendUnsupportedVLErr),
1172 E_P_AUTO(SendUnexpectedPktNumErr),
1173 E_P_AUTO(SendDroppedDataPktErr),
1174 E_P_AUTO(SendDroppedSmpPktErr),
1175 E_P_AUTO(SendPktLenErr),
1176 E_P_AUTO(SendUnderRunErr),
1177 E_P_AUTO(SendMaxPktLenErr),
1178 E_P_AUTO(SendMinPktLenErr),
1179 E_P_AUTO(RcvIBLostLinkErr),
1180 E_P_AUTO(RcvHdrErr),
1181 E_P_AUTO(RcvHdrLenErr),
1182 E_P_AUTO(RcvBadTidErr),
1183 E_P_AUTO(RcvBadVersionErr),
1184 E_P_AUTO(RcvIBFlowErr),
1185 E_P_AUTO(RcvEBPErr),
1186 E_P_AUTO(RcvUnsupportedVLErr),
1187 E_P_AUTO(RcvUnexpectedCharErr),
1188 E_P_AUTO(RcvShortPktLenErr),
1189 E_P_AUTO(RcvLongPktLenErr),
1190 E_P_AUTO(RcvMaxPktLenErr),
1191 E_P_AUTO(RcvMinPktLenErr),
1192 E_P_AUTO(RcvICRCErr),
1193 E_P_AUTO(RcvVCRCErr),
1194 E_P_AUTO(RcvFormatErr),
1195 { .mask = 0 }
1196 };
1197
1198 /*
1199 * Below generates "auto-message" for interrupts not specific to any port or
1200 * context
1201 */
1202 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1203 .msg = #fldname }
1204 /* Below generates "auto-message" for interrupts specific to a port */
1205 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1206 SYM_LSB(IntMask, fldname##Mask##_0), \
1207 SYM_LSB(IntMask, fldname##Mask##_1)), \
1208 .msg = #fldname "_P" }
1209 /* For some reason, the SerDesTrimDone bits are reversed */
1210 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1211 SYM_LSB(IntMask, fldname##Mask##_1), \
1212 SYM_LSB(IntMask, fldname##Mask##_0)), \
1213 .msg = #fldname "_P" }
1214 /*
1215 * Below generates "auto-message" for interrupts specific to a context,
1216 * with ctxt-number appended
1217 */
1218 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1219 SYM_LSB(IntMask, fldname##0IntMask), \
1220 SYM_LSB(IntMask, fldname##17IntMask)), \
1221 .msg = #fldname "_C"}
1222
1223 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1224 INTR_AUTO_P(SDmaInt),
1225 INTR_AUTO_P(SDmaProgressInt),
1226 INTR_AUTO_P(SDmaIdleInt),
1227 INTR_AUTO_P(SDmaCleanupDone),
1228 INTR_AUTO_C(RcvUrg),
1229 INTR_AUTO_P(ErrInt),
1230 INTR_AUTO(ErrInt), /* non-port-specific errs */
1231 INTR_AUTO(AssertGPIOInt),
1232 INTR_AUTO_P(SendDoneInt),
1233 INTR_AUTO(SendBufAvailInt),
1234 INTR_AUTO_C(RcvAvail),
1235 { .mask = 0 }
1236 };
1237
1238 #define TXSYMPTOM_AUTO_P(fldname) \
1239 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1240 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1241 TXSYMPTOM_AUTO_P(NonKeyPacket),
1242 TXSYMPTOM_AUTO_P(GRHFail),
1243 TXSYMPTOM_AUTO_P(PkeyFail),
1244 TXSYMPTOM_AUTO_P(QPFail),
1245 TXSYMPTOM_AUTO_P(SLIDFail),
1246 TXSYMPTOM_AUTO_P(RawIPV6),
1247 TXSYMPTOM_AUTO_P(PacketTooSmall),
1248 { .mask = 0 }
1249 };
1250
1251 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1252
1253 /*
1254 * Called when we might have an error that is specific to a particular
1255 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1256 * because we don't need to force the update of pioavail
1257 */
1258 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1259 {
1260 struct qib_devdata *dd = ppd->dd;
1261 u32 i;
1262 int any;
1263 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1264 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1265 unsigned long sbuf[4];
1266
1267 /*
1268 * It's possible that sendbuffererror could have bits set; might
1269 * have already done this as a result of hardware error handling.
1270 */
1271 any = 0;
1272 for (i = 0; i < regcnt; ++i) {
1273 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1274 if (sbuf[i]) {
1275 any = 1;
1276 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1277 }
1278 }
1279
1280 if (any)
1281 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1282 }
1283
1284 /* No txe_recover yet, if ever */
1285
1286 /* No decode__errors yet */
1287 static void err_decode(char *msg, size_t len, u64 errs,
1288 const struct qib_hwerror_msgs *msp)
1289 {
1290 u64 these, lmask;
1291 int took, multi, n = 0;
1292
1293 while (msp && msp->mask) {
1294 multi = (msp->mask & (msp->mask - 1));
1295 while (errs & msp->mask) {
1296 these = (errs & msp->mask);
1297 lmask = (these & (these - 1)) ^ these;
1298 if (len) {
1299 if (n++) {
1300 /* separate the strings */
1301 *msg++ = ',';
1302 len--;
1303 }
1304 took = scnprintf(msg, len, "%s", msp->msg);
1305 len -= took;
1306 msg += took;
1307 }
1308 errs &= ~lmask;
1309 if (len && multi) {
1310 /* More than one bit this mask */
1311 int idx = -1;
1312
1313 while (lmask & msp->mask) {
1314 ++idx;
1315 lmask >>= 1;
1316 }
1317 took = scnprintf(msg, len, "_%d", idx);
1318 len -= took;
1319 msg += took;
1320 }
1321 }
1322 ++msp;
1323 }
1324 /* If some bits are left, show in hex. */
1325 if (len && errs)
1326 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1327 (unsigned long long) errs);
1328 }
1329
1330 /* only called if r1 set */
1331 static void flush_fifo(struct qib_pportdata *ppd)
1332 {
1333 struct qib_devdata *dd = ppd->dd;
1334 u32 __iomem *piobuf;
1335 u32 bufn;
1336 u32 *hdr;
1337 u64 pbc;
1338 const unsigned hdrwords = 7;
1339 static struct qib_ib_header ibhdr = {
1340 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1341 .lrh[1] = IB_LID_PERMISSIVE,
1342 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1343 .lrh[3] = IB_LID_PERMISSIVE,
1344 .u.oth.bth[0] = cpu_to_be32(
1345 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1346 .u.oth.bth[1] = cpu_to_be32(0),
1347 .u.oth.bth[2] = cpu_to_be32(0),
1348 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1349 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1350 };
1351
1352 /*
1353 * Send a dummy VL15 packet to flush the launch FIFO.
1354 * This will not actually be sent since the TxeBypassIbc bit is set.
1355 */
1356 pbc = PBC_7322_VL15_SEND |
1357 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1358 (hdrwords + SIZE_OF_CRC);
1359 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1360 if (!piobuf)
1361 return;
1362 writeq(pbc, piobuf);
1363 hdr = (u32 *) &ibhdr;
1364 if (dd->flags & QIB_PIO_FLUSH_WC) {
1365 qib_flush_wc();
1366 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1367 qib_flush_wc();
1368 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1369 qib_flush_wc();
1370 } else
1371 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1372 qib_sendbuf_done(dd, bufn);
1373 }
1374
1375 /*
1376 * This is called with interrupts disabled and sdma_lock held.
1377 */
1378 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1379 {
1380 struct qib_devdata *dd = ppd->dd;
1381 u64 set_sendctrl = 0;
1382 u64 clr_sendctrl = 0;
1383
1384 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1385 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1386 else
1387 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1388
1389 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1390 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1391 else
1392 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1393
1394 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1395 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1396 else
1397 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1398
1399 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1400 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1401 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1402 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1403 else
1404 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1405 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1406 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1407
1408 spin_lock(&dd->sendctrl_lock);
1409
1410 /* If we are draining everything, block sends first */
1411 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1412 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1413 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1414 qib_write_kreg(dd, kr_scratch, 0);
1415 }
1416
1417 ppd->p_sendctrl |= set_sendctrl;
1418 ppd->p_sendctrl &= ~clr_sendctrl;
1419
1420 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1421 qib_write_kreg_port(ppd, krp_sendctrl,
1422 ppd->p_sendctrl |
1423 SYM_MASK(SendCtrl_0, SDmaCleanup));
1424 else
1425 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1426 qib_write_kreg(dd, kr_scratch, 0);
1427
1428 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1429 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1430 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1431 qib_write_kreg(dd, kr_scratch, 0);
1432 }
1433
1434 spin_unlock(&dd->sendctrl_lock);
1435
1436 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1437 flush_fifo(ppd);
1438 }
1439
1440 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1441 {
1442 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1443 }
1444
1445 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1446 {
1447 /*
1448 * Set SendDmaLenGen and clear and set
1449 * the MSB of the generation count to enable generation checking
1450 * and load the internal generation counter.
1451 */
1452 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1453 qib_write_kreg_port(ppd, krp_senddmalengen,
1454 ppd->sdma_descq_cnt |
1455 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1456 }
1457
1458 /*
1459 * Must be called with sdma_lock held, or before init finished.
1460 */
1461 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1462 {
1463 /* Commit writes to memory and advance the tail on the chip */
1464 wmb();
1465 ppd->sdma_descq_tail = tail;
1466 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1467 }
1468
1469 /*
1470 * This is called with interrupts disabled and sdma_lock held.
1471 */
1472 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1473 {
1474 /*
1475 * Drain all FIFOs.
1476 * The hardware doesn't require this but we do it so that verbs
1477 * and user applications don't wait for link active to send stale
1478 * data.
1479 */
1480 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1481
1482 qib_sdma_7322_setlengen(ppd);
1483 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1484 ppd->sdma_head_dma[0] = 0;
1485 qib_7322_sdma_sendctrl(ppd,
1486 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1487 }
1488
1489 #define DISABLES_SDMA ( \
1490 QIB_E_P_SDMAHALT | \
1491 QIB_E_P_SDMADESCADDRMISALIGN | \
1492 QIB_E_P_SDMAMISSINGDW | \
1493 QIB_E_P_SDMADWEN | \
1494 QIB_E_P_SDMARPYTAG | \
1495 QIB_E_P_SDMA1STDESC | \
1496 QIB_E_P_SDMABASE | \
1497 QIB_E_P_SDMATAILOUTOFBOUND | \
1498 QIB_E_P_SDMAOUTOFBOUND | \
1499 QIB_E_P_SDMAGENMISMATCH)
1500
1501 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1502 {
1503 unsigned long flags;
1504 struct qib_devdata *dd = ppd->dd;
1505
1506 errs &= QIB_E_P_SDMAERRS;
1507
1508 if (errs & QIB_E_P_SDMAUNEXPDATA)
1509 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1510 ppd->port);
1511
1512 spin_lock_irqsave(&ppd->sdma_lock, flags);
1513
1514 switch (ppd->sdma_state.current_state) {
1515 case qib_sdma_state_s00_hw_down:
1516 break;
1517
1518 case qib_sdma_state_s10_hw_start_up_wait:
1519 if (errs & QIB_E_P_SDMAHALT)
1520 __qib_sdma_process_event(ppd,
1521 qib_sdma_event_e20_hw_started);
1522 break;
1523
1524 case qib_sdma_state_s20_idle:
1525 break;
1526
1527 case qib_sdma_state_s30_sw_clean_up_wait:
1528 break;
1529
1530 case qib_sdma_state_s40_hw_clean_up_wait:
1531 if (errs & QIB_E_P_SDMAHALT)
1532 __qib_sdma_process_event(ppd,
1533 qib_sdma_event_e50_hw_cleaned);
1534 break;
1535
1536 case qib_sdma_state_s50_hw_halt_wait:
1537 if (errs & QIB_E_P_SDMAHALT)
1538 __qib_sdma_process_event(ppd,
1539 qib_sdma_event_e60_hw_halted);
1540 break;
1541
1542 case qib_sdma_state_s99_running:
1543 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1544 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1545 break;
1546 }
1547
1548 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1549 }
1550
1551 /*
1552 * handle per-device errors (not per-port errors)
1553 */
1554 static noinline void handle_7322_errors(struct qib_devdata *dd)
1555 {
1556 char *msg;
1557 u64 iserr = 0;
1558 u64 errs;
1559 u64 mask;
1560 int log_idx;
1561
1562 qib_stats.sps_errints++;
1563 errs = qib_read_kreg64(dd, kr_errstatus);
1564 if (!errs) {
1565 qib_devinfo(dd->pcidev, "device error interrupt, "
1566 "but no error bits set!\n");
1567 goto done;
1568 }
1569
1570 /* don't report errors that are masked */
1571 errs &= dd->cspec->errormask;
1572 msg = dd->cspec->emsgbuf;
1573
1574 /* do these first, they are most important */
1575 if (errs & QIB_E_HARDWARE) {
1576 *msg = '\0';
1577 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1578 } else
1579 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1580 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1581 qib_inc_eeprom_err(dd, log_idx, 1);
1582
1583 if (errs & QIB_E_SPKTERRS) {
1584 qib_disarm_7322_senderrbufs(dd->pport);
1585 qib_stats.sps_txerrs++;
1586 } else if (errs & QIB_E_INVALIDADDR)
1587 qib_stats.sps_txerrs++;
1588 else if (errs & QIB_E_ARMLAUNCH) {
1589 qib_stats.sps_txerrs++;
1590 qib_disarm_7322_senderrbufs(dd->pport);
1591 }
1592 qib_write_kreg(dd, kr_errclear, errs);
1593
1594 /*
1595 * The ones we mask off are handled specially below
1596 * or above. Also mask SDMADISABLED by default as it
1597 * is too chatty.
1598 */
1599 mask = QIB_E_HARDWARE;
1600 *msg = '\0';
1601
1602 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1603 qib_7322error_msgs);
1604
1605 /*
1606 * Getting reset is a tragedy for all ports. Mark the device
1607 * _and_ the ports as "offline" in way meaningful to each.
1608 */
1609 if (errs & QIB_E_RESET) {
1610 int pidx;
1611
1612 qib_dev_err(dd, "Got reset, requires re-init "
1613 "(unload and reload driver)\n");
1614 dd->flags &= ~QIB_INITTED; /* needs re-init */
1615 /* mark as having had error */
1616 *dd->devstatusp |= QIB_STATUS_HWERROR;
1617 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1618 if (dd->pport[pidx].link_speed_supported)
1619 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1620 }
1621
1622 if (*msg && iserr)
1623 qib_dev_err(dd, "%s error\n", msg);
1624
1625 /*
1626 * If there were hdrq or egrfull errors, wake up any processes
1627 * waiting in poll. We used to try to check which contexts had
1628 * the overflow, but given the cost of that and the chip reads
1629 * to support it, it's better to just wake everybody up if we
1630 * get an overflow; waiters can poll again if it's not them.
1631 */
1632 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1633 qib_handle_urcv(dd, ~0U);
1634 if (errs & ERR_MASK(RcvEgrFullErr))
1635 qib_stats.sps_buffull++;
1636 else
1637 qib_stats.sps_hdrfull++;
1638 }
1639
1640 done:
1641 return;
1642 }
1643
1644 static void reenable_chase(unsigned long opaque)
1645 {
1646 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1647
1648 ppd->cpspec->chase_timer.expires = 0;
1649 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1650 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1651 }
1652
1653 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1654 {
1655 ppd->cpspec->chase_end = 0;
1656
1657 if (!qib_chase)
1658 return;
1659
1660 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1661 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1662 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1663 add_timer(&ppd->cpspec->chase_timer);
1664 }
1665
1666 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1667 {
1668 u8 ibclt;
1669 u64 tnow;
1670
1671 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1672
1673 /*
1674 * Detect and handle the state chase issue, where we can
1675 * get stuck if we are unlucky on timing on both sides of
1676 * the link. If we are, we disable, set a timer, and
1677 * then re-enable.
1678 */
1679 switch (ibclt) {
1680 case IB_7322_LT_STATE_CFGRCVFCFG:
1681 case IB_7322_LT_STATE_CFGWAITRMT:
1682 case IB_7322_LT_STATE_TXREVLANES:
1683 case IB_7322_LT_STATE_CFGENH:
1684 tnow = get_jiffies_64();
1685 if (ppd->cpspec->chase_end &&
1686 time_after64(tnow, ppd->cpspec->chase_end))
1687 disable_chase(ppd, tnow, ibclt);
1688 else if (!ppd->cpspec->chase_end)
1689 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1690 break;
1691 default:
1692 ppd->cpspec->chase_end = 0;
1693 break;
1694 }
1695
1696 if (ibclt == IB_7322_LT_STATE_CFGTEST &&
1697 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1698 force_h1(ppd);
1699 ppd->cpspec->qdr_reforce = 1;
1700 if (!ppd->dd->cspec->r1)
1701 serdes_7322_los_enable(ppd, 0);
1702 } else if (ppd->cpspec->qdr_reforce &&
1703 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1704 (ibclt == IB_7322_LT_STATE_CFGENH ||
1705 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1706 ibclt == IB_7322_LT_STATE_LINKUP))
1707 force_h1(ppd);
1708
1709 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1710 ppd->link_speed_enabled == QIB_IB_QDR &&
1711 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1712 ibclt == IB_7322_LT_STATE_CFGENH ||
1713 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1714 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1715 adj_tx_serdes(ppd);
1716
1717 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1718 u8 ltstate = qib_7322_phys_portstate(ibcst);
1719 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1720 LinkTrainingState);
1721 if (!ppd->dd->cspec->r1 &&
1722 pibclt == IB_7322_LT_STATE_LINKUP &&
1723 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1724 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1725 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1726 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1727 /* If the link went down (but no into recovery,
1728 * turn LOS back on */
1729 serdes_7322_los_enable(ppd, 1);
1730 if (!ppd->cpspec->qdr_dfe_on &&
1731 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1732 ppd->cpspec->qdr_dfe_on = 1;
1733 ppd->cpspec->qdr_dfe_time = 0;
1734 /* On link down, reenable QDR adaptation */
1735 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1736 ppd->dd->cspec->r1 ?
1737 QDR_STATIC_ADAPT_DOWN_R1 :
1738 QDR_STATIC_ADAPT_DOWN);
1739 printk(KERN_INFO QIB_DRV_NAME
1740 " IB%u:%u re-enabled QDR adaptation "
1741 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1742 }
1743 }
1744 }
1745
1746 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1747
1748 /*
1749 * This is per-pport error handling.
1750 * will likely get it's own MSIx interrupt (one for each port,
1751 * although just a single handler).
1752 */
1753 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1754 {
1755 char *msg;
1756 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1757 struct qib_devdata *dd = ppd->dd;
1758
1759 /* do this as soon as possible */
1760 fmask = qib_read_kreg64(dd, kr_act_fmask);
1761 if (!fmask)
1762 check_7322_rxe_status(ppd);
1763
1764 errs = qib_read_kreg_port(ppd, krp_errstatus);
1765 if (!errs)
1766 qib_devinfo(dd->pcidev,
1767 "Port%d error interrupt, but no error bits set!\n",
1768 ppd->port);
1769 if (!fmask)
1770 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1771 if (!errs)
1772 goto done;
1773
1774 msg = ppd->cpspec->epmsgbuf;
1775 *msg = '\0';
1776
1777 if (errs & ~QIB_E_P_BITSEXTANT) {
1778 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1779 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1780 if (!*msg)
1781 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1782 "no others");
1783 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1784 " errors 0x%016Lx set (and %s)\n",
1785 (errs & ~QIB_E_P_BITSEXTANT), msg);
1786 *msg = '\0';
1787 }
1788
1789 if (errs & QIB_E_P_SHDR) {
1790 u64 symptom;
1791
1792 /* determine cause, then write to clear */
1793 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1794 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1795 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1796 hdrchk_msgs);
1797 *msg = '\0';
1798 /* senderrbuf cleared in SPKTERRS below */
1799 }
1800
1801 if (errs & QIB_E_P_SPKTERRS) {
1802 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1803 !(ppd->lflags & QIBL_LINKACTIVE)) {
1804 /*
1805 * This can happen when trying to bring the link
1806 * up, but the IB link changes state at the "wrong"
1807 * time. The IB logic then complains that the packet
1808 * isn't valid. We don't want to confuse people, so
1809 * we just don't print them, except at debug
1810 */
1811 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1812 (errs & QIB_E_P_LINK_PKTERRS),
1813 qib_7322p_error_msgs);
1814 *msg = '\0';
1815 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1816 }
1817 qib_disarm_7322_senderrbufs(ppd);
1818 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1819 !(ppd->lflags & QIBL_LINKACTIVE)) {
1820 /*
1821 * This can happen when SMA is trying to bring the link
1822 * up, but the IB link changes state at the "wrong" time.
1823 * The IB logic then complains that the packet isn't
1824 * valid. We don't want to confuse people, so we just
1825 * don't print them, except at debug
1826 */
1827 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1828 qib_7322p_error_msgs);
1829 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1830 *msg = '\0';
1831 }
1832
1833 qib_write_kreg_port(ppd, krp_errclear, errs);
1834
1835 errs &= ~ignore_this_time;
1836 if (!errs)
1837 goto done;
1838
1839 if (errs & QIB_E_P_RPKTERRS)
1840 qib_stats.sps_rcverrs++;
1841 if (errs & QIB_E_P_SPKTERRS)
1842 qib_stats.sps_txerrs++;
1843
1844 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1845
1846 if (errs & QIB_E_P_SDMAERRS)
1847 sdma_7322_p_errors(ppd, errs);
1848
1849 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1850 u64 ibcs;
1851 u8 ltstate;
1852
1853 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1854 ltstate = qib_7322_phys_portstate(ibcs);
1855
1856 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1857 handle_serdes_issues(ppd, ibcs);
1858 if (!(ppd->cpspec->ibcctrl_a &
1859 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1860 /*
1861 * We got our interrupt, so init code should be
1862 * happy and not try alternatives. Now squelch
1863 * other "chatter" from link-negotiation (pre Init)
1864 */
1865 ppd->cpspec->ibcctrl_a |=
1866 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1867 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1868 ppd->cpspec->ibcctrl_a);
1869 }
1870
1871 /* Update our picture of width and speed from chip */
1872 ppd->link_width_active =
1873 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1874 IB_WIDTH_4X : IB_WIDTH_1X;
1875 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1876 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1877 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1878 QIB_IB_DDR : QIB_IB_SDR;
1879
1880 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1881 IB_PHYSPORTSTATE_DISABLED)
1882 qib_set_ib_7322_lstate(ppd, 0,
1883 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1884 else {
1885 u32 lstate;
1886 /*
1887 * We need the current logical link state before
1888 * lflags are set in handle_e_ibstatuschanged.
1889 */
1890 lstate = qib_7322_iblink_state(ibcs);
1891
1892 if (IS_QMH(dd) && !ppd->cpspec->bounced &&
1893 ltstate == IB_PHYSPORTSTATE_LINKUP &&
1894 (lstate >= IB_PORT_INIT &&
1895 lstate <= IB_PORT_ACTIVE)) {
1896 ppd->cpspec->bounced = 1;
1897 qib_7322_set_ib_cfg(ppd, QIB_IB_CFG_LSTATE,
1898 IB_LINKCMD_DOWN | IB_LINKINITCMD_POLL);
1899 }
1900
1901 /*
1902 * Since going into a recovery state causes the link
1903 * state to go down and since recovery is transitory,
1904 * it is better if we "miss" ever seeing the link
1905 * training state go into recovery (i.e., ignore this
1906 * transition for link state special handling purposes)
1907 * without updating lastibcstat.
1908 */
1909 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1910 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1911 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1912 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1913 qib_handle_e_ibstatuschanged(ppd, ibcs);
1914 }
1915 }
1916 if (*msg && iserr)
1917 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1918
1919 if (ppd->state_wanted & ppd->lflags)
1920 wake_up_interruptible(&ppd->state_wait);
1921 done:
1922 return;
1923 }
1924
1925 /* enable/disable chip from delivering interrupts */
1926 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1927 {
1928 if (enable) {
1929 if (dd->flags & QIB_BADINTR)
1930 return;
1931 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1932 /* cause any pending enabled interrupts to be re-delivered */
1933 qib_write_kreg(dd, kr_intclear, 0ULL);
1934 if (dd->cspec->num_msix_entries) {
1935 /* and same for MSIx */
1936 u64 val = qib_read_kreg64(dd, kr_intgranted);
1937 if (val)
1938 qib_write_kreg(dd, kr_intgranted, val);
1939 }
1940 } else
1941 qib_write_kreg(dd, kr_intmask, 0ULL);
1942 }
1943
1944 /*
1945 * Try to cleanup as much as possible for anything that might have gone
1946 * wrong while in freeze mode, such as pio buffers being written by user
1947 * processes (causing armlaunch), send errors due to going into freeze mode,
1948 * etc., and try to avoid causing extra interrupts while doing so.
1949 * Forcibly update the in-memory pioavail register copies after cleanup
1950 * because the chip won't do it while in freeze mode (the register values
1951 * themselves are kept correct).
1952 * Make sure that we don't lose any important interrupts by using the chip
1953 * feature that says that writing 0 to a bit in *clear that is set in
1954 * *status will cause an interrupt to be generated again (if allowed by
1955 * the *mask value).
1956 * This is in chip-specific code because of all of the register accesses,
1957 * even though the details are similar on most chips.
1958 */
1959 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1960 {
1961 int pidx;
1962
1963 /* disable error interrupts, to avoid confusion */
1964 qib_write_kreg(dd, kr_errmask, 0ULL);
1965
1966 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1967 if (dd->pport[pidx].link_speed_supported)
1968 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1969 0ULL);
1970
1971 /* also disable interrupts; errormask is sometimes overwriten */
1972 qib_7322_set_intr_state(dd, 0);
1973
1974 /* clear the freeze, and be sure chip saw it */
1975 qib_write_kreg(dd, kr_control, dd->control);
1976 qib_read_kreg32(dd, kr_scratch);
1977
1978 /*
1979 * Force new interrupt if any hwerr, error or interrupt bits are
1980 * still set, and clear "safe" send packet errors related to freeze
1981 * and cancelling sends. Re-enable error interrupts before possible
1982 * force of re-interrupt on pending interrupts.
1983 */
1984 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1985 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1986 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1987 /* We need to purge per-port errs and reset mask, too */
1988 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1989 if (!dd->pport[pidx].link_speed_supported)
1990 continue;
1991 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1992 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1993 }
1994 qib_7322_set_intr_state(dd, 1);
1995 }
1996
1997 /* no error handling to speak of */
1998 /**
1999 * qib_7322_handle_hwerrors - display hardware errors.
2000 * @dd: the qlogic_ib device
2001 * @msg: the output buffer
2002 * @msgl: the size of the output buffer
2003 *
2004 * Use same msg buffer as regular errors to avoid excessive stack
2005 * use. Most hardware errors are catastrophic, but for right now,
2006 * we'll print them and continue. We reuse the same message buffer as
2007 * qib_handle_errors() to avoid excessive stack usage.
2008 */
2009 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
2010 size_t msgl)
2011 {
2012 u64 hwerrs;
2013 u32 ctrl;
2014 int isfatal = 0;
2015
2016 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
2017 if (!hwerrs)
2018 goto bail;
2019 if (hwerrs == ~0ULL) {
2020 qib_dev_err(dd, "Read of hardware error status failed "
2021 "(all bits set); ignoring\n");
2022 goto bail;
2023 }
2024 qib_stats.sps_hwerrs++;
2025
2026 /* Always clear the error status register, except BIST fail */
2027 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2028 ~HWE_MASK(PowerOnBISTFailed));
2029
2030 hwerrs &= dd->cspec->hwerrmask;
2031
2032 /* no EEPROM logging, yet */
2033
2034 if (hwerrs)
2035 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2036 "(cleared)\n", (unsigned long long) hwerrs);
2037
2038 ctrl = qib_read_kreg32(dd, kr_control);
2039 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2040 /*
2041 * No recovery yet...
2042 */
2043 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2044 dd->cspec->stay_in_freeze) {
2045 /*
2046 * If any set that we aren't ignoring only make the
2047 * complaint once, in case it's stuck or recurring,
2048 * and we get here multiple times
2049 * Force link down, so switch knows, and
2050 * LEDs are turned off.
2051 */
2052 if (dd->flags & QIB_INITTED)
2053 isfatal = 1;
2054 } else
2055 qib_7322_clear_freeze(dd);
2056 }
2057
2058 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2059 isfatal = 1;
2060 strlcpy(msg, "[Memory BIST test failed, "
2061 "InfiniPath hardware unusable]", msgl);
2062 /* ignore from now on, so disable until driver reloaded */
2063 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2064 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2065 }
2066
2067 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2068
2069 /* Ignore esoteric PLL failures et al. */
2070
2071 qib_dev_err(dd, "%s hardware error\n", msg);
2072
2073 if (isfatal && !dd->diag_client) {
2074 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2075 " usable, SN %.16s\n", dd->serial);
2076 /*
2077 * for /sys status file and user programs to print; if no
2078 * trailing brace is copied, we'll know it was truncated.
2079 */
2080 if (dd->freezemsg)
2081 snprintf(dd->freezemsg, dd->freezelen,
2082 "{%s}", msg);
2083 qib_disable_after_error(dd);
2084 }
2085 bail:;
2086 }
2087
2088 /**
2089 * qib_7322_init_hwerrors - enable hardware errors
2090 * @dd: the qlogic_ib device
2091 *
2092 * now that we have finished initializing everything that might reasonably
2093 * cause a hardware error, and cleared those errors bits as they occur,
2094 * we can enable hardware errors in the mask (potentially enabling
2095 * freeze mode), and enable hardware errors as errors (along with
2096 * everything else) in errormask
2097 */
2098 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2099 {
2100 int pidx;
2101 u64 extsval;
2102
2103 extsval = qib_read_kreg64(dd, kr_extstatus);
2104 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2105 QIB_EXTS_MEMBIST_ENDTEST)))
2106 qib_dev_err(dd, "MemBIST did not complete!\n");
2107
2108 /* never clear BIST failure, so reported on each driver load */
2109 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2110 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2111
2112 /* clear all */
2113 qib_write_kreg(dd, kr_errclear, ~0ULL);
2114 /* enable errors that are masked, at least this first time. */
2115 qib_write_kreg(dd, kr_errmask, ~0ULL);
2116 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2117 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2118 if (dd->pport[pidx].link_speed_supported)
2119 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2120 ~0ULL);
2121 }
2122
2123 /*
2124 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2125 * on chips that are count-based, rather than trigger-based. There is no
2126 * reference counting, but that's also fine, given the intended use.
2127 * Only chip-specific because it's all register accesses
2128 */
2129 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2130 {
2131 if (enable) {
2132 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2133 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2134 } else
2135 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2136 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2137 }
2138
2139 /*
2140 * Formerly took parameter <which> in pre-shifted,
2141 * pre-merged form with LinkCmd and LinkInitCmd
2142 * together, and assuming the zero was NOP.
2143 */
2144 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2145 u16 linitcmd)
2146 {
2147 u64 mod_wd;
2148 struct qib_devdata *dd = ppd->dd;
2149 unsigned long flags;
2150
2151 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2152 /*
2153 * If we are told to disable, note that so link-recovery
2154 * code does not attempt to bring us back up.
2155 * Also reset everything that we can, so we start
2156 * completely clean when re-enabled (before we
2157 * actually issue the disable to the IBC)
2158 */
2159 qib_7322_mini_pcs_reset(ppd);
2160 spin_lock_irqsave(&ppd->lflags_lock, flags);
2161 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2162 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2163 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2164 /*
2165 * Any other linkinitcmd will lead to LINKDOWN and then
2166 * to INIT (if all is well), so clear flag to let
2167 * link-recovery code attempt to bring us back up.
2168 */
2169 spin_lock_irqsave(&ppd->lflags_lock, flags);
2170 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2171 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2172 /*
2173 * Clear status change interrupt reduction so the
2174 * new state is seen.
2175 */
2176 ppd->cpspec->ibcctrl_a &=
2177 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2178 }
2179
2180 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2181 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2182
2183 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2184 mod_wd);
2185 /* write to chip to prevent back-to-back writes of ibc reg */
2186 qib_write_kreg(dd, kr_scratch, 0);
2187
2188 }
2189
2190 /*
2191 * The total RCV buffer memory is 64KB, used for both ports, and is
2192 * in units of 64 bytes (same as IB flow control credit unit).
2193 * The consumedVL unit in the same registers are in 32 byte units!
2194 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2195 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2196 * in krp_rxcreditvl15, rather than 10.
2197 */
2198 #define RCV_BUF_UNITSZ 64
2199 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2200
2201 static void set_vls(struct qib_pportdata *ppd)
2202 {
2203 int i, numvls, totcred, cred_vl, vl0extra;
2204 struct qib_devdata *dd = ppd->dd;
2205 u64 val;
2206
2207 numvls = qib_num_vls(ppd->vls_operational);
2208
2209 /*
2210 * Set up per-VL credits. Below is kluge based on these assumptions:
2211 * 1) port is disabled at the time early_init is called.
2212 * 2) give VL15 17 credits, for two max-plausible packets.
2213 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2214 */
2215 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2216 totcred = NUM_RCV_BUF_UNITS(dd);
2217 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2218 totcred -= cred_vl;
2219 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2220 cred_vl = totcred / numvls;
2221 vl0extra = totcred - cred_vl * numvls;
2222 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2223 for (i = 1; i < numvls; i++)
2224 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2225 for (; i < 8; i++) /* no buffer space for other VLs */
2226 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2227
2228 /* Notify IBC that credits need to be recalculated */
2229 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2230 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2231 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2232 qib_write_kreg(dd, kr_scratch, 0ULL);
2233 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2234 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2235
2236 for (i = 0; i < numvls; i++)
2237 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2238 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2239
2240 /* Change the number of operational VLs */
2241 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2242 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2243 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2244 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2245 qib_write_kreg(dd, kr_scratch, 0ULL);
2246 }
2247
2248 /*
2249 * The code that deals with actual SerDes is in serdes_7322_init().
2250 * Compared to the code for iba7220, it is minimal.
2251 */
2252 static int serdes_7322_init(struct qib_pportdata *ppd);
2253
2254 /**
2255 * qib_7322_bringup_serdes - bring up the serdes
2256 * @ppd: physical port on the qlogic_ib device
2257 */
2258 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2259 {
2260 struct qib_devdata *dd = ppd->dd;
2261 u64 val, guid, ibc;
2262 unsigned long flags;
2263 int ret = 0;
2264
2265 /*
2266 * SerDes model not in Pd, but still need to
2267 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2268 * eventually.
2269 */
2270 /* Put IBC in reset, sends disabled (should be in reset already) */
2271 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2272 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2273 qib_write_kreg(dd, kr_scratch, 0ULL);
2274
2275 if (qib_compat_ddr_negotiate) {
2276 ppd->cpspec->ibdeltainprog = 1;
2277 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2278 crp_ibsymbolerr);
2279 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2280 crp_iblinkerrrecov);
2281 }
2282
2283 /* flowcontrolwatermark is in units of KBytes */
2284 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2285 /*
2286 * Flow control is sent this often, even if no changes in
2287 * buffer space occur. Units are 128ns for this chip.
2288 * Set to 3usec.
2289 */
2290 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2291 /* max error tolerance */
2292 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2293 /* IB credit flow control. */
2294 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2295 /*
2296 * set initial max size pkt IBC will send, including ICRC; it's the
2297 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2298 */
2299 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2300 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2301 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2302
2303 /* initially come up waiting for TS1, without sending anything. */
2304 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2305 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2306
2307 /*
2308 * Reset the PCS interface to the serdes (and also ibc, which is still
2309 * in reset from above). Writes new value of ibcctrl_a as last step.
2310 */
2311 qib_7322_mini_pcs_reset(ppd);
2312 qib_write_kreg(dd, kr_scratch, 0ULL);
2313
2314 if (!ppd->cpspec->ibcctrl_b) {
2315 unsigned lse = ppd->link_speed_enabled;
2316
2317 /*
2318 * Not on re-init after reset, establish shadow
2319 * and force initial config.
2320 */
2321 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2322 krp_ibcctrl_b);
2323 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2324 IBA7322_IBC_SPEED_DDR |
2325 IBA7322_IBC_SPEED_SDR |
2326 IBA7322_IBC_WIDTH_AUTONEG |
2327 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2328 if (lse & (lse - 1)) /* Muliple speeds enabled */
2329 ppd->cpspec->ibcctrl_b |=
2330 (lse << IBA7322_IBC_SPEED_LSB) |
2331 IBA7322_IBC_IBTA_1_2_MASK |
2332 IBA7322_IBC_MAX_SPEED_MASK;
2333 else
2334 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2335 IBA7322_IBC_SPEED_QDR |
2336 IBA7322_IBC_IBTA_1_2_MASK :
2337 (lse == QIB_IB_DDR) ?
2338 IBA7322_IBC_SPEED_DDR :
2339 IBA7322_IBC_SPEED_SDR;
2340 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2341 (IB_WIDTH_1X | IB_WIDTH_4X))
2342 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2343 else
2344 ppd->cpspec->ibcctrl_b |=
2345 ppd->link_width_enabled == IB_WIDTH_4X ?
2346 IBA7322_IBC_WIDTH_4X_ONLY :
2347 IBA7322_IBC_WIDTH_1X_ONLY;
2348
2349 /* always enable these on driver reload, not sticky */
2350 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2351 IBA7322_IBC_HRTBT_MASK);
2352 }
2353 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2354
2355 /* setup so we have more time at CFGTEST to change H1 */
2356 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2357 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2358 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2359 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2360
2361 serdes_7322_init(ppd);
2362
2363 guid = be64_to_cpu(ppd->guid);
2364 if (!guid) {
2365 if (dd->base_guid)
2366 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2367 ppd->guid = cpu_to_be64(guid);
2368 }
2369
2370 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2371 /* write to chip to prevent back-to-back writes of ibc reg */
2372 qib_write_kreg(dd, kr_scratch, 0);
2373
2374 /* Enable port */
2375 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2376 set_vls(ppd);
2377
2378 /* be paranoid against later code motion, etc. */
2379 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2380 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2381 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2382 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2383
2384 /* Also enable IBSTATUSCHG interrupt. */
2385 val = qib_read_kreg_port(ppd, krp_errmask);
2386 qib_write_kreg_port(ppd, krp_errmask,
2387 val | ERR_MASK_N(IBStatusChanged));
2388
2389 /* Always zero until we start messing with SerDes for real */
2390 return ret;
2391 }
2392
2393 /**
2394 * qib_7322_quiet_serdes - set serdes to txidle
2395 * @dd: the qlogic_ib device
2396 * Called when driver is being unloaded
2397 */
2398 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2399 {
2400 u64 val;
2401 unsigned long flags;
2402
2403 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2404
2405 spin_lock_irqsave(&ppd->lflags_lock, flags);
2406 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2407 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2408 wake_up(&ppd->cpspec->autoneg_wait);
2409 cancel_delayed_work(&ppd->cpspec->autoneg_work);
2410 if (ppd->dd->cspec->r1)
2411 cancel_delayed_work(&ppd->cpspec->ipg_work);
2412 flush_scheduled_work();
2413
2414 ppd->cpspec->chase_end = 0;
2415 if (ppd->cpspec->chase_timer.data) /* if initted */
2416 del_timer_sync(&ppd->cpspec->chase_timer);
2417
2418 /*
2419 * Despite the name, actually disables IBC as well. Do it when
2420 * we are as sure as possible that no more packets can be
2421 * received, following the down and the PCS reset.
2422 * The actual disabling happens in qib_7322_mini_pci_reset(),
2423 * along with the PCS being reset.
2424 */
2425 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2426 qib_7322_mini_pcs_reset(ppd);
2427
2428 /*
2429 * Update the adjusted counters so the adjustment persists
2430 * across driver reload.
2431 */
2432 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2433 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2434 struct qib_devdata *dd = ppd->dd;
2435 u64 diagc;
2436
2437 /* enable counter writes */
2438 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2439 qib_write_kreg(dd, kr_hwdiagctrl,
2440 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2441
2442 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2443 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2444 if (ppd->cpspec->ibdeltainprog)
2445 val -= val - ppd->cpspec->ibsymsnap;
2446 val -= ppd->cpspec->ibsymdelta;
2447 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2448 }
2449 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2450 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2451 if (ppd->cpspec->ibdeltainprog)
2452 val -= val - ppd->cpspec->iblnkerrsnap;
2453 val -= ppd->cpspec->iblnkerrdelta;
2454 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2455 }
2456 if (ppd->cpspec->iblnkdowndelta) {
2457 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2458 val += ppd->cpspec->iblnkdowndelta;
2459 write_7322_creg_port(ppd, crp_iblinkdown, val);
2460 }
2461 /*
2462 * No need to save ibmalfdelta since IB perfcounters
2463 * are cleared on driver reload.
2464 */
2465
2466 /* and disable counter writes */
2467 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2468 }
2469 }
2470
2471 /**
2472 * qib_setup_7322_setextled - set the state of the two external LEDs
2473 * @ppd: physical port on the qlogic_ib device
2474 * @on: whether the link is up or not
2475 *
2476 * The exact combo of LEDs if on is true is determined by looking
2477 * at the ibcstatus.
2478 *
2479 * These LEDs indicate the physical and logical state of IB link.
2480 * For this chip (at least with recommended board pinouts), LED1
2481 * is Yellow (logical state) and LED2 is Green (physical state),
2482 *
2483 * Note: We try to match the Mellanox HCA LED behavior as best
2484 * we can. Green indicates physical link state is OK (something is
2485 * plugged in, and we can train).
2486 * Amber indicates the link is logically up (ACTIVE).
2487 * Mellanox further blinks the amber LED to indicate data packet
2488 * activity, but we have no hardware support for that, so it would
2489 * require waking up every 10-20 msecs and checking the counters
2490 * on the chip, and then turning the LED off if appropriate. That's
2491 * visible overhead, so not something we will do.
2492 */
2493 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2494 {
2495 struct qib_devdata *dd = ppd->dd;
2496 u64 extctl, ledblink = 0, val;
2497 unsigned long flags;
2498 int yel, grn;
2499
2500 /*
2501 * The diags use the LED to indicate diag info, so we leave
2502 * the external LED alone when the diags are running.
2503 */
2504 if (dd->diag_client)
2505 return;
2506
2507 /* Allow override of LED display for, e.g. Locating system in rack */
2508 if (ppd->led_override) {
2509 grn = (ppd->led_override & QIB_LED_PHYS);
2510 yel = (ppd->led_override & QIB_LED_LOG);
2511 } else if (on) {
2512 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2513 grn = qib_7322_phys_portstate(val) ==
2514 IB_PHYSPORTSTATE_LINKUP;
2515 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2516 } else {
2517 grn = 0;
2518 yel = 0;
2519 }
2520
2521 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2522 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2523 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2524 if (grn) {
2525 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2526 /*
2527 * Counts are in chip clock (4ns) periods.
2528 * This is 1/16 sec (66.6ms) on,
2529 * 3/16 sec (187.5 ms) off, with packets rcvd.
2530 */
2531 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2532 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2533 }
2534 if (yel)
2535 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2536 dd->cspec->extctrl = extctl;
2537 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2538 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2539
2540 if (ledblink) /* blink the LED on packet receive */
2541 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2542 }
2543
2544 /*
2545 * Disable MSIx interrupt if enabled, call generic MSIx code
2546 * to cleanup, and clear pending MSIx interrupts.
2547 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2548 */
2549 static void qib_7322_nomsix(struct qib_devdata *dd)
2550 {
2551 u64 intgranted;
2552 int n;
2553
2554 dd->cspec->main_int_mask = ~0ULL;
2555 n = dd->cspec->num_msix_entries;
2556 if (n) {
2557 int i;
2558
2559 dd->cspec->num_msix_entries = 0;
2560 for (i = 0; i < n; i++)
2561 free_irq(dd->cspec->msix_entries[i].vector,
2562 dd->cspec->msix_arg[i]);
2563 qib_nomsix(dd);
2564 }
2565 /* make sure no MSIx interrupts are left pending */
2566 intgranted = qib_read_kreg64(dd, kr_intgranted);
2567 if (intgranted)
2568 qib_write_kreg(dd, kr_intgranted, intgranted);
2569 }
2570
2571 static void qib_7322_free_irq(struct qib_devdata *dd)
2572 {
2573 if (dd->cspec->irq) {
2574 free_irq(dd->cspec->irq, dd);
2575 dd->cspec->irq = 0;
2576 }
2577 qib_7322_nomsix(dd);
2578 }
2579
2580 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2581 {
2582 int i;
2583
2584 qib_7322_free_irq(dd);
2585 kfree(dd->cspec->cntrs);
2586 kfree(dd->cspec->sendchkenable);
2587 kfree(dd->cspec->sendgrhchk);
2588 kfree(dd->cspec->sendibchk);
2589 kfree(dd->cspec->msix_entries);
2590 kfree(dd->cspec->msix_arg);
2591 for (i = 0; i < dd->num_pports; i++) {
2592 unsigned long flags;
2593 u32 mask = QSFP_GPIO_MOD_PRS_N |
2594 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2595
2596 kfree(dd->pport[i].cpspec->portcntrs);
2597 if (dd->flags & QIB_HAS_QSFP) {
2598 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2599 dd->cspec->gpio_mask &= ~mask;
2600 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2601 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2602 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2603 }
2604 if (dd->pport[i].ibport_data.smi_ah)
2605 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2606 }
2607 }
2608
2609 /* handle SDMA interrupts */
2610 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2611 {
2612 struct qib_pportdata *ppd0 = &dd->pport[0];
2613 struct qib_pportdata *ppd1 = &dd->pport[1];
2614 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2615 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2616 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2617 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2618
2619 if (intr0)
2620 qib_sdma_intr(ppd0);
2621 if (intr1)
2622 qib_sdma_intr(ppd1);
2623
2624 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2625 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2626 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2627 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2628 }
2629
2630 /*
2631 * Set or clear the Send buffer available interrupt enable bit.
2632 */
2633 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2634 {
2635 unsigned long flags;
2636
2637 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2638 if (needint)
2639 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2640 else
2641 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2642 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2643 qib_write_kreg(dd, kr_scratch, 0ULL);
2644 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2645 }
2646
2647 /*
2648 * Somehow got an interrupt with reserved bits set in interrupt status.
2649 * Print a message so we know it happened, then clear them.
2650 * keep mainline interrupt handler cache-friendly
2651 */
2652 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2653 {
2654 u64 kills;
2655 char msg[128];
2656
2657 kills = istat & ~QIB_I_BITSEXTANT;
2658 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2659 " %s\n", (unsigned long long) kills, msg);
2660 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2661 }
2662
2663 /* keep mainline interrupt handler cache-friendly */
2664 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2665 {
2666 u32 gpiostatus;
2667 int handled = 0;
2668 int pidx;
2669
2670 /*
2671 * Boards for this chip currently don't use GPIO interrupts,
2672 * so clear by writing GPIOstatus to GPIOclear, and complain
2673 * to developer. To avoid endless repeats, clear
2674 * the bits in the mask, since there is some kind of
2675 * programming error or chip problem.
2676 */
2677 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2678 /*
2679 * In theory, writing GPIOstatus to GPIOclear could
2680 * have a bad side-effect on some diagnostic that wanted
2681 * to poll for a status-change, but the various shadows
2682 * make that problematic at best. Diags will just suppress
2683 * all GPIO interrupts during such tests.
2684 */
2685 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2686 /*
2687 * Check for QSFP MOD_PRS changes
2688 * only works for single port if IB1 != pidx1
2689 */
2690 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2691 ++pidx) {
2692 struct qib_pportdata *ppd;
2693 struct qib_qsfp_data *qd;
2694 u32 mask;
2695 if (!dd->pport[pidx].link_speed_supported)
2696 continue;
2697 mask = QSFP_GPIO_MOD_PRS_N;
2698 ppd = dd->pport + pidx;
2699 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2700 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2701 u64 pins;
2702 qd = &ppd->cpspec->qsfp_data;
2703 gpiostatus &= ~mask;
2704 pins = qib_read_kreg64(dd, kr_extstatus);
2705 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2706 if (!(pins & mask)) {
2707 ++handled;
2708 qd->t_insert = get_jiffies_64();
2709 schedule_work(&qd->work);
2710 }
2711 }
2712 }
2713
2714 if (gpiostatus && !handled) {
2715 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2716 u32 gpio_irq = mask & gpiostatus;
2717
2718 /*
2719 * Clear any troublemakers, and update chip from shadow
2720 */
2721 dd->cspec->gpio_mask &= ~gpio_irq;
2722 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2723 }
2724 }
2725
2726 /*
2727 * Handle errors and unusual events first, separate function
2728 * to improve cache hits for fast path interrupt handling.
2729 */
2730 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2731 {
2732 if (istat & ~QIB_I_BITSEXTANT)
2733 unknown_7322_ibits(dd, istat);
2734 if (istat & QIB_I_GPIO)
2735 unknown_7322_gpio_intr(dd);
2736 if (istat & QIB_I_C_ERROR)
2737 handle_7322_errors(dd);
2738 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2739 handle_7322_p_errors(dd->rcd[0]->ppd);
2740 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2741 handle_7322_p_errors(dd->rcd[1]->ppd);
2742 }
2743
2744 /*
2745 * Dynamically adjust the rcv int timeout for a context based on incoming
2746 * packet rate.
2747 */
2748 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2749 {
2750 struct qib_devdata *dd = rcd->dd;
2751 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2752
2753 /*
2754 * Dynamically adjust idle timeout on chip
2755 * based on number of packets processed.
2756 */
2757 if (npkts < rcv_int_count && timeout > 2)
2758 timeout >>= 1;
2759 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2760 timeout = min(timeout << 1, rcv_int_timeout);
2761 else
2762 return;
2763
2764 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2765 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2766 }
2767
2768 /*
2769 * This is the main interrupt handler.
2770 * It will normally only be used for low frequency interrupts but may
2771 * have to handle all interrupts if INTx is enabled or fewer than normal
2772 * MSIx interrupts were allocated.
2773 * This routine should ignore the interrupt bits for any of the
2774 * dedicated MSIx handlers.
2775 */
2776 static irqreturn_t qib_7322intr(int irq, void *data)
2777 {
2778 struct qib_devdata *dd = data;
2779 irqreturn_t ret;
2780 u64 istat;
2781 u64 ctxtrbits;
2782 u64 rmask;
2783 unsigned i;
2784 u32 npkts;
2785
2786 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2787 /*
2788 * This return value is not great, but we do not want the
2789 * interrupt core code to remove our interrupt handler
2790 * because we don't appear to be handling an interrupt
2791 * during a chip reset.
2792 */
2793 ret = IRQ_HANDLED;
2794 goto bail;
2795 }
2796
2797 istat = qib_read_kreg64(dd, kr_intstatus);
2798
2799 if (unlikely(istat == ~0ULL)) {
2800 qib_bad_intrstatus(dd);
2801 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2802 /* don't know if it was our interrupt or not */
2803 ret = IRQ_NONE;
2804 goto bail;
2805 }
2806
2807 istat &= dd->cspec->main_int_mask;
2808 if (unlikely(!istat)) {
2809 /* already handled, or shared and not us */
2810 ret = IRQ_NONE;
2811 goto bail;
2812 }
2813
2814 qib_stats.sps_ints++;
2815 if (dd->int_counter != (u32) -1)
2816 dd->int_counter++;
2817
2818 /* handle "errors" of various kinds first, device ahead of port */
2819 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2820 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2821 INT_MASK_P(Err, 1))))
2822 unlikely_7322_intr(dd, istat);
2823
2824 /*
2825 * Clear the interrupt bits we found set, relatively early, so we
2826 * "know" know the chip will have seen this by the time we process
2827 * the queue, and will re-interrupt if necessary. The processor
2828 * itself won't take the interrupt again until we return.
2829 */
2830 qib_write_kreg(dd, kr_intclear, istat);
2831
2832 /*
2833 * Handle kernel receive queues before checking for pio buffers
2834 * available since receives can overflow; piobuf waiters can afford
2835 * a few extra cycles, since they were waiting anyway.
2836 */
2837 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2838 if (ctxtrbits) {
2839 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2840 (1ULL << QIB_I_RCVURG_LSB);
2841 for (i = 0; i < dd->first_user_ctxt; i++) {
2842 if (ctxtrbits & rmask) {
2843 ctxtrbits &= ~rmask;
2844 if (dd->rcd[i]) {
2845 qib_kreceive(dd->rcd[i], NULL, &npkts);
2846 }
2847 }
2848 rmask <<= 1;
2849 }
2850 if (ctxtrbits) {
2851 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2852 (ctxtrbits >> QIB_I_RCVURG_LSB);
2853 qib_handle_urcv(dd, ctxtrbits);
2854 }
2855 }
2856
2857 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2858 sdma_7322_intr(dd, istat);
2859
2860 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2861 qib_ib_piobufavail(dd);
2862
2863 ret = IRQ_HANDLED;
2864 bail:
2865 return ret;
2866 }
2867
2868 /*
2869 * Dedicated receive packet available interrupt handler.
2870 */
2871 static irqreturn_t qib_7322pintr(int irq, void *data)
2872 {
2873 struct qib_ctxtdata *rcd = data;
2874 struct qib_devdata *dd = rcd->dd;
2875 u32 npkts;
2876
2877 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2878 /*
2879 * This return value is not great, but we do not want the
2880 * interrupt core code to remove our interrupt handler
2881 * because we don't appear to be handling an interrupt
2882 * during a chip reset.
2883 */
2884 return IRQ_HANDLED;
2885
2886 qib_stats.sps_ints++;
2887 if (dd->int_counter != (u32) -1)
2888 dd->int_counter++;
2889
2890 /* Clear the interrupt bit we expect to be set. */
2891 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2892 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2893
2894 qib_kreceive(rcd, NULL, &npkts);
2895
2896 return IRQ_HANDLED;
2897 }
2898
2899 /*
2900 * Dedicated Send buffer available interrupt handler.
2901 */
2902 static irqreturn_t qib_7322bufavail(int irq, void *data)
2903 {
2904 struct qib_devdata *dd = data;
2905
2906 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2907 /*
2908 * This return value is not great, but we do not want the
2909 * interrupt core code to remove our interrupt handler
2910 * because we don't appear to be handling an interrupt
2911 * during a chip reset.
2912 */
2913 return IRQ_HANDLED;
2914
2915 qib_stats.sps_ints++;
2916 if (dd->int_counter != (u32) -1)
2917 dd->int_counter++;
2918
2919 /* Clear the interrupt bit we expect to be set. */
2920 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2921
2922 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2923 if (dd->flags & QIB_INITTED)
2924 qib_ib_piobufavail(dd);
2925 else
2926 qib_wantpiobuf_7322_intr(dd, 0);
2927
2928 return IRQ_HANDLED;
2929 }
2930
2931 /*
2932 * Dedicated Send DMA interrupt handler.
2933 */
2934 static irqreturn_t sdma_intr(int irq, void *data)
2935 {
2936 struct qib_pportdata *ppd = data;
2937 struct qib_devdata *dd = ppd->dd;
2938
2939 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2940 /*
2941 * This return value is not great, but we do not want the
2942 * interrupt core code to remove our interrupt handler
2943 * because we don't appear to be handling an interrupt
2944 * during a chip reset.
2945 */
2946 return IRQ_HANDLED;
2947
2948 qib_stats.sps_ints++;
2949 if (dd->int_counter != (u32) -1)
2950 dd->int_counter++;
2951
2952 /* Clear the interrupt bit we expect to be set. */
2953 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2954 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2955 qib_sdma_intr(ppd);
2956
2957 return IRQ_HANDLED;
2958 }
2959
2960 /*
2961 * Dedicated Send DMA idle interrupt handler.
2962 */
2963 static irqreturn_t sdma_idle_intr(int irq, void *data)
2964 {
2965 struct qib_pportdata *ppd = data;
2966 struct qib_devdata *dd = ppd->dd;
2967
2968 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2969 /*
2970 * This return value is not great, but we do not want the
2971 * interrupt core code to remove our interrupt handler
2972 * because we don't appear to be handling an interrupt
2973 * during a chip reset.
2974 */
2975 return IRQ_HANDLED;
2976
2977 qib_stats.sps_ints++;
2978 if (dd->int_counter != (u32) -1)
2979 dd->int_counter++;
2980
2981 /* Clear the interrupt bit we expect to be set. */
2982 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2983 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2984 qib_sdma_intr(ppd);
2985
2986 return IRQ_HANDLED;
2987 }
2988
2989 /*
2990 * Dedicated Send DMA progress interrupt handler.
2991 */
2992 static irqreturn_t sdma_progress_intr(int irq, void *data)
2993 {
2994 struct qib_pportdata *ppd = data;
2995 struct qib_devdata *dd = ppd->dd;
2996
2997 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2998 /*
2999 * This return value is not great, but we do not want the
3000 * interrupt core code to remove our interrupt handler
3001 * because we don't appear to be handling an interrupt
3002 * during a chip reset.
3003 */
3004 return IRQ_HANDLED;
3005
3006 qib_stats.sps_ints++;
3007 if (dd->int_counter != (u32) -1)
3008 dd->int_counter++;
3009
3010 /* Clear the interrupt bit we expect to be set. */
3011 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3012 INT_MASK_P(SDmaProgress, 1) :
3013 INT_MASK_P(SDmaProgress, 0));
3014 qib_sdma_intr(ppd);
3015
3016 return IRQ_HANDLED;
3017 }
3018
3019 /*
3020 * Dedicated Send DMA cleanup interrupt handler.
3021 */
3022 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3023 {
3024 struct qib_pportdata *ppd = data;
3025 struct qib_devdata *dd = ppd->dd;
3026
3027 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3028 /*
3029 * This return value is not great, but we do not want the
3030 * interrupt core code to remove our interrupt handler
3031 * because we don't appear to be handling an interrupt
3032 * during a chip reset.
3033 */
3034 return IRQ_HANDLED;
3035
3036 qib_stats.sps_ints++;
3037 if (dd->int_counter != (u32) -1)
3038 dd->int_counter++;
3039
3040 /* Clear the interrupt bit we expect to be set. */
3041 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3042 INT_MASK_PM(SDmaCleanupDone, 1) :
3043 INT_MASK_PM(SDmaCleanupDone, 0));
3044 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3045
3046 return IRQ_HANDLED;
3047 }
3048
3049 /*
3050 * Set up our chip-specific interrupt handler.
3051 * The interrupt type has already been setup, so
3052 * we just need to do the registration and error checking.
3053 * If we are using MSIx interrupts, we may fall back to
3054 * INTx later, if the interrupt handler doesn't get called
3055 * within 1/2 second (see verify_interrupt()).
3056 */
3057 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3058 {
3059 int ret, i, msixnum;
3060 u64 redirect[6];
3061 u64 mask;
3062
3063 if (!dd->num_pports)
3064 return;
3065
3066 if (clearpend) {
3067 /*
3068 * if not switching interrupt types, be sure interrupts are
3069 * disabled, and then clear anything pending at this point,
3070 * because we are starting clean.
3071 */
3072 qib_7322_set_intr_state(dd, 0);
3073
3074 /* clear the reset error, init error/hwerror mask */
3075 qib_7322_init_hwerrors(dd);
3076
3077 /* clear any interrupt bits that might be set */
3078 qib_write_kreg(dd, kr_intclear, ~0ULL);
3079
3080 /* make sure no pending MSIx intr, and clear diag reg */
3081 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3082 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3083 }
3084
3085 if (!dd->cspec->num_msix_entries) {
3086 /* Try to get INTx interrupt */
3087 try_intx:
3088 if (!dd->pcidev->irq) {
3089 qib_dev_err(dd, "irq is 0, BIOS error? "
3090 "Interrupts won't work\n");
3091 goto bail;
3092 }
3093 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3094 IRQF_SHARED, QIB_DRV_NAME, dd);
3095 if (ret) {
3096 qib_dev_err(dd, "Couldn't setup INTx "
3097 "interrupt (irq=%d): %d\n",
3098 dd->pcidev->irq, ret);
3099 goto bail;
3100 }
3101 dd->cspec->irq = dd->pcidev->irq;
3102 dd->cspec->main_int_mask = ~0ULL;
3103 goto bail;
3104 }
3105
3106 /* Try to get MSIx interrupts */
3107 memset(redirect, 0, sizeof redirect);
3108 mask = ~0ULL;
3109 msixnum = 0;
3110 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3111 irq_handler_t handler;
3112 const char *name;
3113 void *arg;
3114 u64 val;
3115 int lsb, reg, sh;
3116
3117 if (i < ARRAY_SIZE(irq_table)) {
3118 if (irq_table[i].port) {
3119 /* skip if for a non-configured port */
3120 if (irq_table[i].port > dd->num_pports)
3121 continue;
3122 arg = dd->pport + irq_table[i].port - 1;
3123 } else
3124 arg = dd;
3125 lsb = irq_table[i].lsb;
3126 handler = irq_table[i].handler;
3127 name = irq_table[i].name;
3128 } else {
3129 unsigned ctxt;
3130
3131 ctxt = i - ARRAY_SIZE(irq_table);
3132 /* per krcvq context receive interrupt */
3133 arg = dd->rcd[ctxt];
3134 if (!arg)
3135 continue;
3136 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3137 handler = qib_7322pintr;
3138 name = QIB_DRV_NAME " (kctx)";
3139 }
3140 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3141 handler, 0, name, arg);
3142 if (ret) {
3143 /*
3144 * Shouldn't happen since the enable said we could
3145 * have as many as we are trying to setup here.
3146 */
3147 qib_dev_err(dd, "Couldn't setup MSIx "
3148 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3149 dd->cspec->msix_entries[msixnum].vector,
3150 ret);
3151 qib_7322_nomsix(dd);
3152 goto try_intx;
3153 }
3154 dd->cspec->msix_arg[msixnum] = arg;
3155 if (lsb >= 0) {
3156 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3157 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3158 SYM_LSB(IntRedirect0, vec1);
3159 mask &= ~(1ULL << lsb);
3160 redirect[reg] |= ((u64) msixnum) << sh;
3161 }
3162 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3163 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3164 msixnum++;
3165 }
3166 /* Initialize the vector mapping */
3167 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3168 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3169 dd->cspec->main_int_mask = mask;
3170 bail:;
3171 }
3172
3173 /**
3174 * qib_7322_boardname - fill in the board name and note features
3175 * @dd: the qlogic_ib device
3176 *
3177 * info will be based on the board revision register
3178 */
3179 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3180 {
3181 /* Will need enumeration of board-types here */
3182 char *n;
3183 u32 boardid, namelen;
3184 unsigned features = DUAL_PORT_CAP;
3185
3186 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3187
3188 switch (boardid) {
3189 case 0:
3190 n = "InfiniPath_QLE7342_Emulation";
3191 break;
3192 case 1:
3193 n = "InfiniPath_QLE7340";
3194 dd->flags |= QIB_HAS_QSFP;
3195 features = PORT_SPD_CAP;
3196 break;
3197 case 2:
3198 n = "InfiniPath_QLE7342";
3199 dd->flags |= QIB_HAS_QSFP;
3200 break;
3201 case 3:
3202 n = "InfiniPath_QMI7342";
3203 break;
3204 case 4:
3205 n = "InfiniPath_Unsupported7342";
3206 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3207 features = 0;
3208 break;
3209 case BOARD_QMH7342:
3210 n = "InfiniPath_QMH7342";
3211 features = 0x24;
3212 break;
3213 case BOARD_QME7342:
3214 n = "InfiniPath_QME7342";
3215 break;
3216 case 8:
3217 n = "InfiniPath_QME7362";
3218 dd->flags |= QIB_HAS_QSFP;
3219 break;
3220 case 15:
3221 n = "InfiniPath_QLE7342_TEST";
3222 dd->flags |= QIB_HAS_QSFP;
3223 break;
3224 default:
3225 n = "InfiniPath_QLE73xy_UNKNOWN";
3226 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3227 break;
3228 }
3229 dd->board_atten = 1; /* index into txdds_Xdr */
3230
3231 namelen = strlen(n) + 1;
3232 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3233 if (!dd->boardname)
3234 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3235 else
3236 snprintf(dd->boardname, namelen, "%s", n);
3237
3238 snprintf(dd->boardversion, sizeof(dd->boardversion),
3239 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3240 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3241 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3242 dd->majrev, dd->minrev,
3243 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3244
3245 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3246 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3247 " by module parameter\n", dd->unit);
3248 features &= PORT_SPD_CAP;
3249 }
3250
3251 return features;
3252 }
3253
3254 /*
3255 * This routine sleeps, so it can only be called from user context, not
3256 * from interrupt context.
3257 */
3258 static int qib_do_7322_reset(struct qib_devdata *dd)
3259 {
3260 u64 val;
3261 u64 *msix_vecsave;
3262 int i, msix_entries, ret = 1;
3263 u16 cmdval;
3264 u8 int_line, clinesz;
3265 unsigned long flags;
3266
3267 /* Use dev_err so it shows up in logs, etc. */
3268 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3269
3270 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3271
3272 msix_entries = dd->cspec->num_msix_entries;
3273
3274 /* no interrupts till re-initted */
3275 qib_7322_set_intr_state(dd, 0);
3276
3277 if (msix_entries) {
3278 qib_7322_nomsix(dd);
3279 /* can be up to 512 bytes, too big for stack */
3280 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3281 sizeof(u64), GFP_KERNEL);
3282 if (!msix_vecsave)
3283 qib_dev_err(dd, "No mem to save MSIx data\n");
3284 } else
3285 msix_vecsave = NULL;
3286
3287 /*
3288 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3289 * info that is set up by the BIOS, so we have to save and restore
3290 * it ourselves. There is some risk something could change it,
3291 * after we save it, but since we have disabled the MSIx, it
3292 * shouldn't be touched...
3293 */
3294 for (i = 0; i < msix_entries; i++) {
3295 u64 vecaddr, vecdata;
3296 vecaddr = qib_read_kreg64(dd, 2 * i +
3297 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3298 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3299 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3300 if (msix_vecsave) {
3301 msix_vecsave[2 * i] = vecaddr;
3302 /* save it without the masked bit set */
3303 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3304 }
3305 }
3306
3307 dd->pport->cpspec->ibdeltainprog = 0;
3308 dd->pport->cpspec->ibsymdelta = 0;
3309 dd->pport->cpspec->iblnkerrdelta = 0;
3310 dd->pport->cpspec->ibmalfdelta = 0;
3311 dd->int_counter = 0; /* so we check interrupts work again */
3312
3313 /*
3314 * Keep chip from being accessed until we are ready. Use
3315 * writeq() directly, to allow the write even though QIB_PRESENT
3316 * isnt' set.
3317 */
3318 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3319 dd->flags |= QIB_DOING_RESET;
3320 val = dd->control | QLOGIC_IB_C_RESET;
3321 writeq(val, &dd->kregbase[kr_control]);
3322
3323 for (i = 1; i <= 5; i++) {
3324 /*
3325 * Allow MBIST, etc. to complete; longer on each retry.
3326 * We sometimes get machine checks from bus timeout if no
3327 * response, so for now, make it *really* long.
3328 */
3329 msleep(1000 + (1 + i) * 3000);
3330
3331 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3332
3333 /*
3334 * Use readq directly, so we don't need to mark it as PRESENT
3335 * until we get a successful indication that all is well.
3336 */
3337 val = readq(&dd->kregbase[kr_revision]);
3338 if (val == dd->revision)
3339 break;
3340 if (i == 5) {
3341 qib_dev_err(dd, "Failed to initialize after reset, "
3342 "unusable\n");
3343 ret = 0;
3344 goto bail;
3345 }
3346 }
3347
3348 dd->flags |= QIB_PRESENT; /* it's back */
3349
3350 if (msix_entries) {
3351 /* restore the MSIx vector address and data if saved above */
3352 for (i = 0; i < msix_entries; i++) {
3353 dd->cspec->msix_entries[i].entry = i;
3354 if (!msix_vecsave || !msix_vecsave[2 * i])
3355 continue;
3356 qib_write_kreg(dd, 2 * i +
3357 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3358 msix_vecsave[2 * i]);
3359 qib_write_kreg(dd, 1 + 2 * i +
3360 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3361 msix_vecsave[1 + 2 * i]);
3362 }
3363 }
3364
3365 /* initialize the remaining registers. */
3366 for (i = 0; i < dd->num_pports; ++i)
3367 write_7322_init_portregs(&dd->pport[i]);
3368 write_7322_initregs(dd);
3369
3370 if (qib_pcie_params(dd, dd->lbus_width,
3371 &dd->cspec->num_msix_entries,
3372 dd->cspec->msix_entries))
3373 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3374 "continuing anyway\n");
3375
3376 qib_setup_7322_interrupt(dd, 1);
3377
3378 for (i = 0; i < dd->num_pports; ++i) {
3379 struct qib_pportdata *ppd = &dd->pport[i];
3380
3381 spin_lock_irqsave(&ppd->lflags_lock, flags);
3382 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3383 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3384 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3385 }
3386
3387 bail:
3388 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3389 kfree(msix_vecsave);
3390 return ret;
3391 }
3392
3393 /**
3394 * qib_7322_put_tid - write a TID to the chip
3395 * @dd: the qlogic_ib device
3396 * @tidptr: pointer to the expected TID (in chip) to update
3397 * @tidtype: 0 for eager, 1 for expected
3398 * @pa: physical address of in memory buffer; tidinvalid if freeing
3399 */
3400 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3401 u32 type, unsigned long pa)
3402 {
3403 if (!(dd->flags & QIB_PRESENT))
3404 return;
3405 if (pa != dd->tidinvalid) {
3406 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3407
3408 /* paranoia checks */
3409 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3410 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3411 pa);
3412 return;
3413 }
3414 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3415 qib_dev_err(dd, "Physical page address 0x%lx "
3416 "larger than supported\n", pa);
3417 return;
3418 }
3419
3420 if (type == RCVHQ_RCV_TYPE_EAGER)
3421 chippa |= dd->tidtemplate;
3422 else /* for now, always full 4KB page */
3423 chippa |= IBA7322_TID_SZ_4K;
3424 pa = chippa;
3425 }
3426 writeq(pa, tidptr);
3427 mmiowb();
3428 }
3429
3430 /**
3431 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3432 * @dd: the qlogic_ib device
3433 * @ctxt: the ctxt
3434 *
3435 * clear all TID entries for a ctxt, expected and eager.
3436 * Used from qib_close().
3437 */
3438 static void qib_7322_clear_tids(struct qib_devdata *dd,
3439 struct qib_ctxtdata *rcd)
3440 {
3441 u64 __iomem *tidbase;
3442 unsigned long tidinv;
3443 u32 ctxt;
3444 int i;
3445
3446 if (!dd->kregbase || !rcd)
3447 return;
3448
3449 ctxt = rcd->ctxt;
3450
3451 tidinv = dd->tidinvalid;
3452 tidbase = (u64 __iomem *)
3453 ((char __iomem *) dd->kregbase +
3454 dd->rcvtidbase +
3455 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3456
3457 for (i = 0; i < dd->rcvtidcnt; i++)
3458 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3459 tidinv);
3460
3461 tidbase = (u64 __iomem *)
3462 ((char __iomem *) dd->kregbase +
3463 dd->rcvegrbase +
3464 rcd->rcvegr_tid_base * sizeof(*tidbase));
3465
3466 for (i = 0; i < rcd->rcvegrcnt; i++)
3467 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3468 tidinv);
3469 }
3470
3471 /**
3472 * qib_7322_tidtemplate - setup constants for TID updates
3473 * @dd: the qlogic_ib device
3474 *
3475 * We setup stuff that we use a lot, to avoid calculating each time
3476 */
3477 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3478 {
3479 /*
3480 * For now, we always allocate 4KB buffers (at init) so we can
3481 * receive max size packets. We may want a module parameter to
3482 * specify 2KB or 4KB and/or make it per port instead of per device
3483 * for those who want to reduce memory footprint. Note that the
3484 * rcvhdrentsize size must be large enough to hold the largest
3485 * IB header (currently 96 bytes) that we expect to handle (plus of
3486 * course the 2 dwords of RHF).
3487 */
3488 if (dd->rcvegrbufsize == 2048)
3489 dd->tidtemplate = IBA7322_TID_SZ_2K;
3490 else if (dd->rcvegrbufsize == 4096)
3491 dd->tidtemplate = IBA7322_TID_SZ_4K;
3492 dd->tidinvalid = 0;
3493 }
3494
3495 /**
3496 * qib_init_7322_get_base_info - set chip-specific flags for user code
3497 * @rcd: the qlogic_ib ctxt
3498 * @kbase: qib_base_info pointer
3499 *
3500 * We set the PCIE flag because the lower bandwidth on PCIe vs
3501 * HyperTransport can affect some user packet algorithims.
3502 */
3503
3504 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3505 struct qib_base_info *kinfo)
3506 {
3507 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3508 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3509 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3510 if (rcd->dd->cspec->r1)
3511 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3512 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3513 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3514
3515 return 0;
3516 }
3517
3518 static struct qib_message_header *
3519 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3520 {
3521 u32 offset = qib_hdrget_offset(rhf_addr);
3522
3523 return (struct qib_message_header *)
3524 (rhf_addr - dd->rhf_offset + offset);
3525 }
3526
3527 /*
3528 * Configure number of contexts.
3529 */
3530 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3531 {
3532 unsigned long flags;
3533 u32 nchipctxts;
3534
3535 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3536 dd->cspec->numctxts = nchipctxts;
3537 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3538 dd->first_user_ctxt = NUM_IB_PORTS +
3539 (qib_n_krcv_queues - 1) * dd->num_pports;
3540 if (dd->first_user_ctxt > nchipctxts)
3541 dd->first_user_ctxt = nchipctxts;
3542 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3543 } else {
3544 dd->first_user_ctxt = NUM_IB_PORTS;
3545 dd->n_krcv_queues = 1;
3546 }
3547
3548 if (!qib_cfgctxts) {
3549 int nctxts = dd->first_user_ctxt + num_online_cpus();
3550
3551 if (nctxts <= 6)
3552 dd->ctxtcnt = 6;
3553 else if (nctxts <= 10)
3554 dd->ctxtcnt = 10;
3555 else if (nctxts <= nchipctxts)
3556 dd->ctxtcnt = nchipctxts;
3557 } else if (qib_cfgctxts < dd->num_pports)
3558 dd->ctxtcnt = dd->num_pports;
3559 else if (qib_cfgctxts <= nchipctxts)
3560 dd->ctxtcnt = qib_cfgctxts;
3561 if (!dd->ctxtcnt) /* none of the above, set to max */
3562 dd->ctxtcnt = nchipctxts;
3563
3564 /*
3565 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3566 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3567 * Lock to be paranoid about later motion, etc.
3568 */
3569 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3570 if (dd->ctxtcnt > 10)
3571 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3572 else if (dd->ctxtcnt > 6)
3573 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3574 /* else configure for default 6 receive ctxts */
3575
3576 /* The XRC opcode is 5. */
3577 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3578
3579 /*
3580 * RcvCtrl *must* be written here so that the
3581 * chip understands how to change rcvegrcnt below.
3582 */
3583 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3584 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3585
3586 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3587 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3588 if (qib_rcvhdrcnt)
3589 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3590 else
3591 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3592 dd->num_pports > 1 ? 1024U : 2048U);
3593 }
3594
3595 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3596 {
3597
3598 int lsb, ret = 0;
3599 u64 maskr; /* right-justified mask */
3600
3601 switch (which) {
3602
3603 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3604 ret = ppd->link_width_enabled;
3605 goto done;
3606
3607 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3608 ret = ppd->link_width_active;
3609 goto done;
3610
3611 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3612 ret = ppd->link_speed_enabled;
3613 goto done;
3614
3615 case QIB_IB_CFG_SPD: /* Get current Link spd */
3616 ret = ppd->link_speed_active;
3617 goto done;
3618
3619 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3620 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3621 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3622 break;
3623
3624 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3625 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3626 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3627 break;
3628
3629 case QIB_IB_CFG_LINKLATENCY:
3630 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3631 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3632 goto done;
3633
3634 case QIB_IB_CFG_OP_VLS:
3635 ret = ppd->vls_operational;
3636 goto done;
3637
3638 case QIB_IB_CFG_VL_HIGH_CAP:
3639 ret = 16;
3640 goto done;
3641
3642 case QIB_IB_CFG_VL_LOW_CAP:
3643 ret = 16;
3644 goto done;
3645
3646 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3647 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3648 OverrunThreshold);
3649 goto done;
3650
3651 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3652 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3653 PhyerrThreshold);
3654 goto done;
3655
3656 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3657 /* will only take effect when the link state changes */
3658 ret = (ppd->cpspec->ibcctrl_a &
3659 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3660 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3661 goto done;
3662
3663 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3664 lsb = IBA7322_IBC_HRTBT_LSB;
3665 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3666 break;
3667
3668 case QIB_IB_CFG_PMA_TICKS:
3669 /*
3670 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3671 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3672 */
3673 if (ppd->link_speed_active == QIB_IB_QDR)
3674 ret = 3;
3675 else if (ppd->link_speed_active == QIB_IB_DDR)
3676 ret = 1;
3677 else
3678 ret = 0;
3679 goto done;
3680
3681 default:
3682 ret = -EINVAL;
3683 goto done;
3684 }
3685 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3686 done:
3687 return ret;
3688 }
3689
3690 /*
3691 * Below again cribbed liberally from older version. Do not lean
3692 * heavily on it.
3693 */
3694 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3695 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3696 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3697
3698 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3699 {
3700 struct qib_devdata *dd = ppd->dd;
3701 u64 maskr; /* right-justified mask */
3702 int lsb, ret = 0;
3703 u16 lcmd, licmd;
3704 unsigned long flags;
3705
3706 switch (which) {
3707 case QIB_IB_CFG_LIDLMC:
3708 /*
3709 * Set LID and LMC. Combined to avoid possible hazard
3710 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3711 */
3712 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3713 maskr = IBA7322_IBC_DLIDLMC_MASK;
3714 /*
3715 * For header-checking, the SLID in the packet will
3716 * be masked with SendIBSLMCMask, and compared
3717 * with SendIBSLIDAssignMask. Make sure we do not
3718 * set any bits not covered by the mask, or we get
3719 * false-positives.
3720 */
3721 qib_write_kreg_port(ppd, krp_sendslid,
3722 val & (val >> 16) & SendIBSLIDAssignMask);
3723 qib_write_kreg_port(ppd, krp_sendslidmask,
3724 (val >> 16) & SendIBSLMCMask);
3725 break;
3726
3727 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3728 ppd->link_width_enabled = val;
3729 /* convert IB value to chip register value */
3730 if (val == IB_WIDTH_1X)
3731 val = 0;
3732 else if (val == IB_WIDTH_4X)
3733 val = 1;
3734 else
3735 val = 3;
3736 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3737 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3738 break;
3739
3740 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3741 /*
3742 * As with width, only write the actual register if the
3743 * link is currently down, otherwise takes effect on next
3744 * link change. Since setting is being explictly requested
3745 * (via MAD or sysfs), clear autoneg failure status if speed
3746 * autoneg is enabled.
3747 */
3748 ppd->link_speed_enabled = val;
3749 val <<= IBA7322_IBC_SPEED_LSB;
3750 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3751 IBA7322_IBC_MAX_SPEED_MASK;
3752 if (val & (val - 1)) {
3753 /* Muliple speeds enabled */
3754 val |= IBA7322_IBC_IBTA_1_2_MASK |
3755 IBA7322_IBC_MAX_SPEED_MASK;
3756 spin_lock_irqsave(&ppd->lflags_lock, flags);
3757 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3758 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3759 } else if (val & IBA7322_IBC_SPEED_QDR)
3760 val |= IBA7322_IBC_IBTA_1_2_MASK;
3761 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3762 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3763 break;
3764
3765 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3766 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3767 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3768 break;
3769
3770 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3771 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3772 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3773 break;
3774
3775 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3776 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3777 OverrunThreshold);
3778 if (maskr != val) {
3779 ppd->cpspec->ibcctrl_a &=
3780 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3781 ppd->cpspec->ibcctrl_a |= (u64) val <<
3782 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3783 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3784 ppd->cpspec->ibcctrl_a);
3785 qib_write_kreg(dd, kr_scratch, 0ULL);
3786 }
3787 goto bail;
3788
3789 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3790 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3791 PhyerrThreshold);
3792 if (maskr != val) {
3793 ppd->cpspec->ibcctrl_a &=
3794 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3795 ppd->cpspec->ibcctrl_a |= (u64) val <<
3796 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3797 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3798 ppd->cpspec->ibcctrl_a);
3799 qib_write_kreg(dd, kr_scratch, 0ULL);
3800 }
3801 goto bail;
3802
3803 case QIB_IB_CFG_PKEYS: /* update pkeys */
3804 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3805 ((u64) ppd->pkeys[2] << 32) |
3806 ((u64) ppd->pkeys[3] << 48);
3807 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3808 goto bail;
3809
3810 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3811 /* will only take effect when the link state changes */
3812 if (val == IB_LINKINITCMD_POLL)
3813 ppd->cpspec->ibcctrl_a &=
3814 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3815 else /* SLEEP */
3816 ppd->cpspec->ibcctrl_a |=
3817 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3818 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3819 qib_write_kreg(dd, kr_scratch, 0ULL);
3820 goto bail;
3821
3822 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3823 /*
3824 * Update our housekeeping variables, and set IBC max
3825 * size, same as init code; max IBC is max we allow in
3826 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3827 * Set even if it's unchanged, print debug message only
3828 * on changes.
3829 */
3830 val = (ppd->ibmaxlen >> 2) + 1;
3831 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3832 ppd->cpspec->ibcctrl_a |= (u64)val <<
3833 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3834 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3835 ppd->cpspec->ibcctrl_a);
3836 qib_write_kreg(dd, kr_scratch, 0ULL);
3837 goto bail;
3838
3839 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3840 switch (val & 0xffff0000) {
3841 case IB_LINKCMD_DOWN:
3842 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3843 ppd->cpspec->ibmalfusesnap = 1;
3844 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3845 crp_errlink);
3846 if (!ppd->cpspec->ibdeltainprog &&
3847 qib_compat_ddr_negotiate) {
3848 ppd->cpspec->ibdeltainprog = 1;
3849 ppd->cpspec->ibsymsnap =
3850 read_7322_creg32_port(ppd,
3851 crp_ibsymbolerr);
3852 ppd->cpspec->iblnkerrsnap =
3853 read_7322_creg32_port(ppd,
3854 crp_iblinkerrrecov);
3855 }
3856 break;
3857
3858 case IB_LINKCMD_ARMED:
3859 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3860 if (ppd->cpspec->ibmalfusesnap) {
3861 ppd->cpspec->ibmalfusesnap = 0;
3862 ppd->cpspec->ibmalfdelta +=
3863 read_7322_creg32_port(ppd,
3864 crp_errlink) -
3865 ppd->cpspec->ibmalfsnap;
3866 }
3867 break;
3868
3869 case IB_LINKCMD_ACTIVE:
3870 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3871 break;
3872
3873 default:
3874 ret = -EINVAL;
3875 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3876 goto bail;
3877 }
3878 switch (val & 0xffff) {
3879 case IB_LINKINITCMD_NOP:
3880 licmd = 0;
3881 break;
3882
3883 case IB_LINKINITCMD_POLL:
3884 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3885 break;
3886
3887 case IB_LINKINITCMD_SLEEP:
3888 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3889 break;
3890
3891 case IB_LINKINITCMD_DISABLE:
3892 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3893 ppd->cpspec->chase_end = 0;
3894 /*
3895 * stop state chase counter and timer, if running.
3896 * wait forpending timer, but don't clear .data (ppd)!
3897 */
3898 if (ppd->cpspec->chase_timer.expires) {
3899 del_timer_sync(&ppd->cpspec->chase_timer);
3900 ppd->cpspec->chase_timer.expires = 0;
3901 }
3902 break;
3903
3904 default:
3905 ret = -EINVAL;
3906 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3907 val & 0xffff);
3908 goto bail;
3909 }
3910 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3911 goto bail;
3912
3913 case QIB_IB_CFG_OP_VLS:
3914 if (ppd->vls_operational != val) {
3915 ppd->vls_operational = val;
3916 set_vls(ppd);
3917 }
3918 goto bail;
3919
3920 case QIB_IB_CFG_VL_HIGH_LIMIT:
3921 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3922 goto bail;
3923
3924 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3925 if (val > 3) {
3926 ret = -EINVAL;
3927 goto bail;
3928 }
3929 lsb = IBA7322_IBC_HRTBT_LSB;
3930 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3931 break;
3932
3933 case QIB_IB_CFG_PORT:
3934 /* val is the port number of the switch we are connected to. */
3935 if (ppd->dd->cspec->r1) {
3936 cancel_delayed_work(&ppd->cpspec->ipg_work);
3937 ppd->cpspec->ipg_tries = 0;
3938 }
3939 goto bail;
3940
3941 default:
3942 ret = -EINVAL;
3943 goto bail;
3944 }
3945 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3946 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3947 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3948 qib_write_kreg(dd, kr_scratch, 0);
3949 bail:
3950 return ret;
3951 }
3952
3953 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3954 {
3955 int ret = 0;
3956 u64 val, ctrlb;
3957
3958 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3959 if (!strncmp(what, "ibc", 3)) {
3960 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3961 Loopback);
3962 val = 0; /* disable heart beat, so link will come up */
3963 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3964 ppd->dd->unit, ppd->port);
3965 } else if (!strncmp(what, "off", 3)) {
3966 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3967 Loopback);
3968 /* enable heart beat again */
3969 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3970 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3971 "(normal)\n", ppd->dd->unit, ppd->port);
3972 } else
3973 ret = -EINVAL;
3974 if (!ret) {
3975 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3976 ppd->cpspec->ibcctrl_a);
3977 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3978 << IBA7322_IBC_HRTBT_LSB);
3979 ppd->cpspec->ibcctrl_b = ctrlb | val;
3980 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3981 ppd->cpspec->ibcctrl_b);
3982 qib_write_kreg(ppd->dd, kr_scratch, 0);
3983 }
3984 return ret;
3985 }
3986
3987 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3988 struct ib_vl_weight_elem *vl)
3989 {
3990 unsigned i;
3991
3992 for (i = 0; i < 16; i++, regno++, vl++) {
3993 u32 val = qib_read_kreg_port(ppd, regno);
3994
3995 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
3996 SYM_RMASK(LowPriority0_0, VirtualLane);
3997 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
3998 SYM_RMASK(LowPriority0_0, Weight);
3999 }
4000 }
4001
4002 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
4003 struct ib_vl_weight_elem *vl)
4004 {
4005 unsigned i;
4006
4007 for (i = 0; i < 16; i++, regno++, vl++) {
4008 u64 val;
4009
4010 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
4011 SYM_LSB(LowPriority0_0, VirtualLane)) |
4012 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
4013 SYM_LSB(LowPriority0_0, Weight));
4014 qib_write_kreg_port(ppd, regno, val);
4015 }
4016 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4017 struct qib_devdata *dd = ppd->dd;
4018 unsigned long flags;
4019
4020 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4021 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4022 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4023 qib_write_kreg(dd, kr_scratch, 0);
4024 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4025 }
4026 }
4027
4028 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4029 {
4030 switch (which) {
4031 case QIB_IB_TBL_VL_HIGH_ARB:
4032 get_vl_weights(ppd, krp_highprio_0, t);
4033 break;
4034
4035 case QIB_IB_TBL_VL_LOW_ARB:
4036 get_vl_weights(ppd, krp_lowprio_0, t);
4037 break;
4038
4039 default:
4040 return -EINVAL;
4041 }
4042 return 0;
4043 }
4044
4045 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4046 {
4047 switch (which) {
4048 case QIB_IB_TBL_VL_HIGH_ARB:
4049 set_vl_weights(ppd, krp_highprio_0, t);
4050 break;
4051
4052 case QIB_IB_TBL_VL_LOW_ARB:
4053 set_vl_weights(ppd, krp_lowprio_0, t);
4054 break;
4055
4056 default:
4057 return -EINVAL;
4058 }
4059 return 0;
4060 }
4061
4062 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4063 u32 updegr, u32 egrhd, u32 npkts)
4064 {
4065 /*
4066 * Need to write timeout register before updating rcvhdrhead to ensure
4067 * that the timer is enabled on reception of a packet.
4068 */
4069 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4070 adjust_rcv_timeout(rcd, npkts);
4071 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4072 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4073 if (updegr)
4074 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4075 }
4076
4077 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4078 {
4079 u32 head, tail;
4080
4081 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4082 if (rcd->rcvhdrtail_kvaddr)
4083 tail = qib_get_rcvhdrtail(rcd);
4084 else
4085 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4086 return head == tail;
4087 }
4088
4089 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4090 QIB_RCVCTRL_CTXT_DIS | \
4091 QIB_RCVCTRL_TIDFLOW_ENB | \
4092 QIB_RCVCTRL_TIDFLOW_DIS | \
4093 QIB_RCVCTRL_TAILUPD_ENB | \
4094 QIB_RCVCTRL_TAILUPD_DIS | \
4095 QIB_RCVCTRL_INTRAVAIL_ENB | \
4096 QIB_RCVCTRL_INTRAVAIL_DIS | \
4097 QIB_RCVCTRL_BP_ENB | \
4098 QIB_RCVCTRL_BP_DIS)
4099
4100 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4101 QIB_RCVCTRL_CTXT_DIS | \
4102 QIB_RCVCTRL_PKEY_DIS | \
4103 QIB_RCVCTRL_PKEY_ENB)
4104
4105 /*
4106 * Modify the RCVCTRL register in chip-specific way. This
4107 * is a function because bit positions and (future) register
4108 * location is chip-specifc, but the needed operations are
4109 * generic. <op> is a bit-mask because we often want to
4110 * do multiple modifications.
4111 */
4112 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4113 int ctxt)
4114 {
4115 struct qib_devdata *dd = ppd->dd;
4116 struct qib_ctxtdata *rcd;
4117 u64 mask, val;
4118 unsigned long flags;
4119
4120 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4121
4122 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4123 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4124 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4125 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4126 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4127 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4128 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4129 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4130 if (op & QIB_RCVCTRL_PKEY_ENB)
4131 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4132 if (op & QIB_RCVCTRL_PKEY_DIS)
4133 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4134 if (ctxt < 0) {
4135 mask = (1ULL << dd->ctxtcnt) - 1;
4136 rcd = NULL;
4137 } else {
4138 mask = (1ULL << ctxt);
4139 rcd = dd->rcd[ctxt];
4140 }
4141 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4142 ppd->p_rcvctrl |=
4143 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4144 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4145 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4146 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4147 }
4148 /* Write these registers before the context is enabled. */
4149 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4150 rcd->rcvhdrqtailaddr_phys);
4151 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4152 rcd->rcvhdrq_phys);
4153 rcd->seq_cnt = 1;
4154 }
4155 if (op & QIB_RCVCTRL_CTXT_DIS)
4156 ppd->p_rcvctrl &=
4157 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4158 if (op & QIB_RCVCTRL_BP_ENB)
4159 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4160 if (op & QIB_RCVCTRL_BP_DIS)
4161 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4162 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4163 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4164 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4165 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4166 /*
4167 * Decide which registers to write depending on the ops enabled.
4168 * Special case is "flush" (no bits set at all)
4169 * which needs to write both.
4170 */
4171 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4172 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4173 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4174 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4175 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4176 /*
4177 * Init the context registers also; if we were
4178 * disabled, tail and head should both be zero
4179 * already from the enable, but since we don't
4180 * know, we have to do it explictly.
4181 */
4182 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4183 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4184
4185 /* be sure enabling write seen; hd/tl should be 0 */
4186 (void) qib_read_kreg32(dd, kr_scratch);
4187 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4188 dd->rcd[ctxt]->head = val;
4189 /* If kctxt, interrupt on next receive. */
4190 if (ctxt < dd->first_user_ctxt)
4191 val |= dd->rhdrhead_intr_off;
4192 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4193 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4194 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4195 /* arm rcv interrupt */
4196 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4197 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4198 }
4199 if (op & QIB_RCVCTRL_CTXT_DIS) {
4200 unsigned f;
4201
4202 /* Now that the context is disabled, clear these registers. */
4203 if (ctxt >= 0) {
4204 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4205 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4206 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4207 qib_write_ureg(dd, ur_rcvflowtable + f,
4208 TIDFLOW_ERRBITS, ctxt);
4209 } else {
4210 unsigned i;
4211
4212 for (i = 0; i < dd->cfgctxts; i++) {
4213 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4214 i, 0);
4215 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4216 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4217 qib_write_ureg(dd, ur_rcvflowtable + f,
4218 TIDFLOW_ERRBITS, i);
4219 }
4220 }
4221 }
4222 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4223 }
4224
4225 /*
4226 * Modify the SENDCTRL register in chip-specific way. This
4227 * is a function where there are multiple such registers with
4228 * slightly different layouts.
4229 * The chip doesn't allow back-to-back sendctrl writes, so write
4230 * the scratch register after writing sendctrl.
4231 *
4232 * Which register is written depends on the operation.
4233 * Most operate on the common register, while
4234 * SEND_ENB and SEND_DIS operate on the per-port ones.
4235 * SEND_ENB is included in common because it can change SPCL_TRIG
4236 */
4237 #define SENDCTRL_COMMON_MODS (\
4238 QIB_SENDCTRL_CLEAR | \
4239 QIB_SENDCTRL_AVAIL_DIS | \
4240 QIB_SENDCTRL_AVAIL_ENB | \
4241 QIB_SENDCTRL_AVAIL_BLIP | \
4242 QIB_SENDCTRL_DISARM | \
4243 QIB_SENDCTRL_DISARM_ALL | \
4244 QIB_SENDCTRL_SEND_ENB)
4245
4246 #define SENDCTRL_PORT_MODS (\
4247 QIB_SENDCTRL_CLEAR | \
4248 QIB_SENDCTRL_SEND_ENB | \
4249 QIB_SENDCTRL_SEND_DIS | \
4250 QIB_SENDCTRL_FLUSH)
4251
4252 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4253 {
4254 struct qib_devdata *dd = ppd->dd;
4255 u64 tmp_dd_sendctrl;
4256 unsigned long flags;
4257
4258 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4259
4260 /* First the dd ones that are "sticky", saved in shadow */
4261 if (op & QIB_SENDCTRL_CLEAR)
4262 dd->sendctrl = 0;
4263 if (op & QIB_SENDCTRL_AVAIL_DIS)
4264 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4265 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4266 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4267 if (dd->flags & QIB_USE_SPCL_TRIG)
4268 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4269 }
4270
4271 /* Then the ppd ones that are "sticky", saved in shadow */
4272 if (op & QIB_SENDCTRL_SEND_DIS)
4273 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4274 else if (op & QIB_SENDCTRL_SEND_ENB)
4275 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4276
4277 if (op & QIB_SENDCTRL_DISARM_ALL) {
4278 u32 i, last;
4279
4280 tmp_dd_sendctrl = dd->sendctrl;
4281 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4282 /*
4283 * Disarm any buffers that are not yet launched,
4284 * disabling updates until done.
4285 */
4286 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4287 for (i = 0; i < last; i++) {
4288 qib_write_kreg(dd, kr_sendctrl,
4289 tmp_dd_sendctrl |
4290 SYM_MASK(SendCtrl, Disarm) | i);
4291 qib_write_kreg(dd, kr_scratch, 0);
4292 }
4293 }
4294
4295 if (op & QIB_SENDCTRL_FLUSH) {
4296 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4297
4298 /*
4299 * Now drain all the fifos. The Abort bit should never be
4300 * needed, so for now, at least, we don't use it.
4301 */
4302 tmp_ppd_sendctrl |=
4303 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4304 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4305 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4306 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4307 qib_write_kreg(dd, kr_scratch, 0);
4308 }
4309
4310 tmp_dd_sendctrl = dd->sendctrl;
4311
4312 if (op & QIB_SENDCTRL_DISARM)
4313 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4314 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4315 SYM_LSB(SendCtrl, DisarmSendBuf));
4316 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4317 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4318 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4319
4320 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4321 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4322 qib_write_kreg(dd, kr_scratch, 0);
4323 }
4324
4325 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4326 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4327 qib_write_kreg(dd, kr_scratch, 0);
4328 }
4329
4330 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4331 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4332 qib_write_kreg(dd, kr_scratch, 0);
4333 }
4334
4335 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4336
4337 if (op & QIB_SENDCTRL_FLUSH) {
4338 u32 v;
4339 /*
4340 * ensure writes have hit chip, then do a few
4341 * more reads, to allow DMA of pioavail registers
4342 * to occur, so in-memory copy is in sync with
4343 * the chip. Not always safe to sleep.
4344 */
4345 v = qib_read_kreg32(dd, kr_scratch);
4346 qib_write_kreg(dd, kr_scratch, v);
4347 v = qib_read_kreg32(dd, kr_scratch);
4348 qib_write_kreg(dd, kr_scratch, v);
4349 qib_read_kreg32(dd, kr_scratch);
4350 }
4351 }
4352
4353 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4354 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4355 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4356
4357 /**
4358 * qib_portcntr_7322 - read a per-port chip counter
4359 * @ppd: the qlogic_ib pport
4360 * @creg: the counter to read (not a chip offset)
4361 */
4362 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4363 {
4364 struct qib_devdata *dd = ppd->dd;
4365 u64 ret = 0ULL;
4366 u16 creg;
4367 /* 0xffff for unimplemented or synthesized counters */
4368 static const u32 xlator[] = {
4369 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4370 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4371 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4372 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4373 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4374 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4375 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4376 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4377 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4378 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4379 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4380 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4381 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4382 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4383 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4384 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4385 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4386 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4387 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4388 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4389 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4390 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4391 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4392 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4393 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4394 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4395 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4396 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4397 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4398 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4399 /*
4400 * the next 3 aren't really counters, but were implemented
4401 * as counters in older chips, so still get accessed as
4402 * though they were counters from this code.
4403 */
4404 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4405 [QIBPORTCNTR_PSSTART] = krp_psstart,
4406 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4407 /* pseudo-counter, summed for all ports */
4408 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4409 };
4410
4411 if (reg >= ARRAY_SIZE(xlator)) {
4412 qib_devinfo(ppd->dd->pcidev,
4413 "Unimplemented portcounter %u\n", reg);
4414 goto done;
4415 }
4416 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4417
4418 /* handle non-counters and special cases first */
4419 if (reg == QIBPORTCNTR_KHDROVFL) {
4420 int i;
4421
4422 /* sum over all kernel contexts (skip if mini_init) */
4423 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4424 struct qib_ctxtdata *rcd = dd->rcd[i];
4425
4426 if (!rcd || rcd->ppd != ppd)
4427 continue;
4428 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4429 }
4430 goto done;
4431 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4432 /*
4433 * Used as part of the synthesis of port_rcv_errors
4434 * in the verbs code for IBTA counters. Not needed for 7322,
4435 * because all the errors are already counted by other cntrs.
4436 */
4437 goto done;
4438 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4439 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4440 /* were counters in older chips, now per-port kernel regs */
4441 ret = qib_read_kreg_port(ppd, creg);
4442 goto done;
4443 }
4444
4445 /*
4446 * Only fast increment counters are 64 bits; use 32 bit reads to
4447 * avoid two independent reads when on Opteron.
4448 */
4449 if (xlator[reg] & _PORT_64BIT_FLAG)
4450 ret = read_7322_creg_port(ppd, creg);
4451 else
4452 ret = read_7322_creg32_port(ppd, creg);
4453 if (creg == crp_ibsymbolerr) {
4454 if (ppd->cpspec->ibdeltainprog)
4455 ret -= ret - ppd->cpspec->ibsymsnap;
4456 ret -= ppd->cpspec->ibsymdelta;
4457 } else if (creg == crp_iblinkerrrecov) {
4458 if (ppd->cpspec->ibdeltainprog)
4459 ret -= ret - ppd->cpspec->iblnkerrsnap;
4460 ret -= ppd->cpspec->iblnkerrdelta;
4461 } else if (creg == crp_errlink)
4462 ret -= ppd->cpspec->ibmalfdelta;
4463 else if (creg == crp_iblinkdown)
4464 ret += ppd->cpspec->iblnkdowndelta;
4465 done:
4466 return ret;
4467 }
4468
4469 /*
4470 * Device counter names (not port-specific), one line per stat,
4471 * single string. Used by utilities like ipathstats to print the stats
4472 * in a way which works for different versions of drivers, without changing
4473 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4474 * display by utility.
4475 * Non-error counters are first.
4476 * Start of "error" conters is indicated by a leading "E " on the first
4477 * "error" counter, and doesn't count in label length.
4478 * The EgrOvfl list needs to be last so we truncate them at the configured
4479 * context count for the device.
4480 * cntr7322indices contains the corresponding register indices.
4481 */
4482 static const char cntr7322names[] =
4483 "Interrupts\n"
4484 "HostBusStall\n"
4485 "E RxTIDFull\n"
4486 "RxTIDInvalid\n"
4487 "RxTIDFloDrop\n" /* 7322 only */
4488 "Ctxt0EgrOvfl\n"
4489 "Ctxt1EgrOvfl\n"
4490 "Ctxt2EgrOvfl\n"
4491 "Ctxt3EgrOvfl\n"
4492 "Ctxt4EgrOvfl\n"
4493 "Ctxt5EgrOvfl\n"
4494 "Ctxt6EgrOvfl\n"
4495 "Ctxt7EgrOvfl\n"
4496 "Ctxt8EgrOvfl\n"
4497 "Ctxt9EgrOvfl\n"
4498 "Ctx10EgrOvfl\n"
4499 "Ctx11EgrOvfl\n"
4500 "Ctx12EgrOvfl\n"
4501 "Ctx13EgrOvfl\n"
4502 "Ctx14EgrOvfl\n"
4503 "Ctx15EgrOvfl\n"
4504 "Ctx16EgrOvfl\n"
4505 "Ctx17EgrOvfl\n"
4506 ;
4507
4508 static const u32 cntr7322indices[] = {
4509 cr_lbint | _PORT_64BIT_FLAG,
4510 cr_lbstall | _PORT_64BIT_FLAG,
4511 cr_tidfull,
4512 cr_tidinvalid,
4513 cr_rxtidflowdrop,
4514 cr_base_egrovfl + 0,
4515 cr_base_egrovfl + 1,
4516 cr_base_egrovfl + 2,
4517 cr_base_egrovfl + 3,
4518 cr_base_egrovfl + 4,
4519 cr_base_egrovfl + 5,
4520 cr_base_egrovfl + 6,
4521 cr_base_egrovfl + 7,
4522 cr_base_egrovfl + 8,
4523 cr_base_egrovfl + 9,
4524 cr_base_egrovfl + 10,
4525 cr_base_egrovfl + 11,
4526 cr_base_egrovfl + 12,
4527 cr_base_egrovfl + 13,
4528 cr_base_egrovfl + 14,
4529 cr_base_egrovfl + 15,
4530 cr_base_egrovfl + 16,
4531 cr_base_egrovfl + 17,
4532 };
4533
4534 /*
4535 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4536 * portcntr7322indices is somewhat complicated by some registers needing
4537 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4538 */
4539 static const char portcntr7322names[] =
4540 "TxPkt\n"
4541 "TxFlowPkt\n"
4542 "TxWords\n"
4543 "RxPkt\n"
4544 "RxFlowPkt\n"
4545 "RxWords\n"
4546 "TxFlowStall\n"
4547 "TxDmaDesc\n" /* 7220 and 7322-only */
4548 "E RxDlidFltr\n" /* 7220 and 7322-only */
4549 "IBStatusChng\n"
4550 "IBLinkDown\n"
4551 "IBLnkRecov\n"
4552 "IBRxLinkErr\n"
4553 "IBSymbolErr\n"
4554 "RxLLIErr\n"
4555 "RxBadFormat\n"
4556 "RxBadLen\n"
4557 "RxBufOvrfl\n"
4558 "RxEBP\n"
4559 "RxFlowCtlErr\n"
4560 "RxICRCerr\n"
4561 "RxLPCRCerr\n"
4562 "RxVCRCerr\n"
4563 "RxInvalLen\n"
4564 "RxInvalPKey\n"
4565 "RxPktDropped\n"
4566 "TxBadLength\n"
4567 "TxDropped\n"
4568 "TxInvalLen\n"
4569 "TxUnderrun\n"
4570 "TxUnsupVL\n"
4571 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4572 "RxVL15Drop\n"
4573 "RxVlErr\n"
4574 "XcessBufOvfl\n"
4575 "RxQPBadCtxt\n" /* 7322-only from here down */
4576 "TXBadHeader\n"
4577 ;
4578
4579 static const u32 portcntr7322indices[] = {
4580 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4581 crp_pktsendflow,
4582 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4583 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4584 crp_pktrcvflowctrl,
4585 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4586 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4587 crp_txsdmadesc | _PORT_64BIT_FLAG,
4588 crp_rxdlidfltr,
4589 crp_ibstatuschange,
4590 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4591 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4592 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4593 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4594 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4595 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4596 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4597 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4598 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4599 crp_rcvflowctrlviol,
4600 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4601 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4602 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4603 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4604 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4605 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4606 crp_txminmaxlenerr,
4607 crp_txdroppedpkt,
4608 crp_txlenerr,
4609 crp_txunderrun,
4610 crp_txunsupvl,
4611 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4612 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4613 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4614 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4615 crp_rxqpinvalidctxt,
4616 crp_txhdrerr,
4617 };
4618
4619 /* do all the setup to make the counter reads efficient later */
4620 static void init_7322_cntrnames(struct qib_devdata *dd)
4621 {
4622 int i, j = 0;
4623 char *s;
4624
4625 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4626 i++) {
4627 /* we always have at least one counter before the egrovfl */
4628 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4629 j = 1;
4630 s = strchr(s + 1, '\n');
4631 if (s && j)
4632 j++;
4633 }
4634 dd->cspec->ncntrs = i;
4635 if (!s)
4636 /* full list; size is without terminating null */
4637 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4638 else
4639 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4640 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4641 * sizeof(u64), GFP_KERNEL);
4642 if (!dd->cspec->cntrs)
4643 qib_dev_err(dd, "Failed allocation for counters\n");
4644
4645 for (i = 0, s = (char *)portcntr7322names; s; i++)
4646 s = strchr(s + 1, '\n');
4647 dd->cspec->nportcntrs = i - 1;
4648 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4649 for (i = 0; i < dd->num_pports; ++i) {
4650 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4651 * sizeof(u64), GFP_KERNEL);
4652 if (!dd->pport[i].cpspec->portcntrs)
4653 qib_dev_err(dd, "Failed allocation for"
4654 " portcounters\n");
4655 }
4656 }
4657
4658 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4659 u64 **cntrp)
4660 {
4661 u32 ret;
4662
4663 if (namep) {
4664 ret = dd->cspec->cntrnamelen;
4665 if (pos >= ret)
4666 ret = 0; /* final read after getting everything */
4667 else
4668 *namep = (char *) cntr7322names;
4669 } else {
4670 u64 *cntr = dd->cspec->cntrs;
4671 int i;
4672
4673 ret = dd->cspec->ncntrs * sizeof(u64);
4674 if (!cntr || pos >= ret) {
4675 /* everything read, or couldn't get memory */
4676 ret = 0;
4677 goto done;
4678 }
4679 *cntrp = cntr;
4680 for (i = 0; i < dd->cspec->ncntrs; i++)
4681 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4682 *cntr++ = read_7322_creg(dd,
4683 cntr7322indices[i] &
4684 _PORT_CNTR_IDXMASK);
4685 else
4686 *cntr++ = read_7322_creg32(dd,
4687 cntr7322indices[i]);
4688 }
4689 done:
4690 return ret;
4691 }
4692
4693 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4694 char **namep, u64 **cntrp)
4695 {
4696 u32 ret;
4697
4698 if (namep) {
4699 ret = dd->cspec->portcntrnamelen;
4700 if (pos >= ret)
4701 ret = 0; /* final read after getting everything */
4702 else
4703 *namep = (char *)portcntr7322names;
4704 } else {
4705 struct qib_pportdata *ppd = &dd->pport[port];
4706 u64 *cntr = ppd->cpspec->portcntrs;
4707 int i;
4708
4709 ret = dd->cspec->nportcntrs * sizeof(u64);
4710 if (!cntr || pos >= ret) {
4711 /* everything read, or couldn't get memory */
4712 ret = 0;
4713 goto done;
4714 }
4715 *cntrp = cntr;
4716 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4717 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4718 *cntr++ = qib_portcntr_7322(ppd,
4719 portcntr7322indices[i] &
4720 _PORT_CNTR_IDXMASK);
4721 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4722 *cntr++ = read_7322_creg_port(ppd,
4723 portcntr7322indices[i] &
4724 _PORT_CNTR_IDXMASK);
4725 else
4726 *cntr++ = read_7322_creg32_port(ppd,
4727 portcntr7322indices[i]);
4728 }
4729 }
4730 done:
4731 return ret;
4732 }
4733
4734 /**
4735 * qib_get_7322_faststats - get word counters from chip before they overflow
4736 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4737 *
4738 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4739 * real purpose of this function is to maintain the notion of
4740 * "active time", which in turn is only logged into the eeprom,
4741 * which we don;t have, yet, for 7322-based boards.
4742 *
4743 * called from add_timer
4744 */
4745 static void qib_get_7322_faststats(unsigned long opaque)
4746 {
4747 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4748 struct qib_pportdata *ppd;
4749 unsigned long flags;
4750 u64 traffic_wds;
4751 int pidx;
4752
4753 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4754 ppd = dd->pport + pidx;
4755
4756 /*
4757 * If port isn't enabled or not operational ports, or
4758 * diags is running (can cause memory diags to fail)
4759 * skip this port this time.
4760 */
4761 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4762 || dd->diag_client)
4763 continue;
4764
4765 /*
4766 * Maintain an activity timer, based on traffic
4767 * exceeding a threshold, so we need to check the word-counts
4768 * even if they are 64-bit.
4769 */
4770 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4771 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4772 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4773 traffic_wds -= ppd->dd->traffic_wds;
4774 ppd->dd->traffic_wds += traffic_wds;
4775 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4776 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4777 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4778 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4779 QIB_IB_QDR) &&
4780 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4781 QIBL_LINKACTIVE)) &&
4782 ppd->cpspec->qdr_dfe_time &&
4783 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4784 ppd->cpspec->qdr_dfe_on = 0;
4785
4786 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4787 ppd->dd->cspec->r1 ?
4788 QDR_STATIC_ADAPT_INIT_R1 :
4789 QDR_STATIC_ADAPT_INIT);
4790 force_h1(ppd);
4791 }
4792 }
4793 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4794 }
4795
4796 /*
4797 * If we were using MSIx, try to fallback to INTx.
4798 */
4799 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4800 {
4801 if (!dd->cspec->num_msix_entries)
4802 return 0; /* already using INTx */
4803
4804 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4805 " trying INTx interrupts\n");
4806 qib_7322_nomsix(dd);
4807 qib_enable_intx(dd->pcidev);
4808 qib_setup_7322_interrupt(dd, 0);
4809 return 1;
4810 }
4811
4812 /*
4813 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4814 * than resetting the IBC or external link state, and useful in some
4815 * cases to cause some retraining. To do this right, we reset IBC
4816 * as well, then return to previous state (which may be still in reset)
4817 * NOTE: some callers of this "know" this writes the current value
4818 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4819 * check all callers.
4820 */
4821 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4822 {
4823 u64 val;
4824 struct qib_devdata *dd = ppd->dd;
4825 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4826 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4827 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4828
4829 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4830 qib_write_kreg(dd, kr_hwerrmask,
4831 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4832 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4833 ppd->cpspec->ibcctrl_a &
4834 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4835
4836 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4837 qib_read_kreg32(dd, kr_scratch);
4838 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4839 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4840 qib_write_kreg(dd, kr_scratch, 0ULL);
4841 qib_write_kreg(dd, kr_hwerrclear,
4842 SYM_MASK(HwErrClear, statusValidNoEopClear));
4843 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4844 }
4845
4846 /*
4847 * This code for non-IBTA-compliant IB speed negotiation is only known to
4848 * work for the SDR to DDR transition, and only between an HCA and a switch
4849 * with recent firmware. It is based on observed heuristics, rather than
4850 * actual knowledge of the non-compliant speed negotiation.
4851 * It has a number of hard-coded fields, since the hope is to rewrite this
4852 * when a spec is available on how the negoation is intended to work.
4853 */
4854 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4855 u32 dcnt, u32 *data)
4856 {
4857 int i;
4858 u64 pbc;
4859 u32 __iomem *piobuf;
4860 u32 pnum, control, len;
4861 struct qib_devdata *dd = ppd->dd;
4862
4863 i = 0;
4864 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4865 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4866 pbc = ((u64) control << 32) | len;
4867 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4868 if (i++ > 15)
4869 return;
4870 udelay(2);
4871 }
4872 /* disable header check on this packet, since it can't be valid */
4873 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4874 writeq(pbc, piobuf);
4875 qib_flush_wc();
4876 qib_pio_copy(piobuf + 2, hdr, 7);
4877 qib_pio_copy(piobuf + 9, data, dcnt);
4878 if (dd->flags & QIB_USE_SPCL_TRIG) {
4879 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4880
4881 qib_flush_wc();
4882 __raw_writel(0xaebecede, piobuf + spcl_off);
4883 }
4884 qib_flush_wc();
4885 qib_sendbuf_done(dd, pnum);
4886 /* and re-enable hdr check */
4887 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4888 }
4889
4890 /*
4891 * _start packet gets sent twice at start, _done gets sent twice at end
4892 */
4893 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4894 {
4895 struct qib_devdata *dd = ppd->dd;
4896 static u32 swapped;
4897 u32 dw, i, hcnt, dcnt, *data;
4898 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4899 static u32 madpayload_start[0x40] = {
4900 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4901 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4902 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4903 };
4904 static u32 madpayload_done[0x40] = {
4905 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4906 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4907 0x40000001, 0x1388, 0x15e, /* rest 0's */
4908 };
4909
4910 dcnt = ARRAY_SIZE(madpayload_start);
4911 hcnt = ARRAY_SIZE(hdr);
4912 if (!swapped) {
4913 /* for maintainability, do it at runtime */
4914 for (i = 0; i < hcnt; i++) {
4915 dw = (__force u32) cpu_to_be32(hdr[i]);
4916 hdr[i] = dw;
4917 }
4918 for (i = 0; i < dcnt; i++) {
4919 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4920 madpayload_start[i] = dw;
4921 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4922 madpayload_done[i] = dw;
4923 }
4924 swapped = 1;
4925 }
4926
4927 data = which ? madpayload_done : madpayload_start;
4928
4929 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4930 qib_read_kreg64(dd, kr_scratch);
4931 udelay(2);
4932 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4933 qib_read_kreg64(dd, kr_scratch);
4934 udelay(2);
4935 }
4936
4937 /*
4938 * Do the absolute minimum to cause an IB speed change, and make it
4939 * ready, but don't actually trigger the change. The caller will
4940 * do that when ready (if link is in Polling training state, it will
4941 * happen immediately, otherwise when link next goes down)
4942 *
4943 * This routine should only be used as part of the DDR autonegotation
4944 * code for devices that are not compliant with IB 1.2 (or code that
4945 * fixes things up for same).
4946 *
4947 * When link has gone down, and autoneg enabled, or autoneg has
4948 * failed and we give up until next time we set both speeds, and
4949 * then we want IBTA enabled as well as "use max enabled speed.
4950 */
4951 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4952 {
4953 u64 newctrlb;
4954 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4955 IBA7322_IBC_IBTA_1_2_MASK |
4956 IBA7322_IBC_MAX_SPEED_MASK);
4957
4958 if (speed & (speed - 1)) /* multiple speeds */
4959 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4960 IBA7322_IBC_IBTA_1_2_MASK |
4961 IBA7322_IBC_MAX_SPEED_MASK;
4962 else
4963 newctrlb |= speed == QIB_IB_QDR ?
4964 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4965 ((speed == QIB_IB_DDR ?
4966 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4967
4968 if (newctrlb == ppd->cpspec->ibcctrl_b)
4969 return;
4970
4971 ppd->cpspec->ibcctrl_b = newctrlb;
4972 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4973 qib_write_kreg(ppd->dd, kr_scratch, 0);
4974 }
4975
4976 /*
4977 * This routine is only used when we are not talking to another
4978 * IB 1.2-compliant device that we think can do DDR.
4979 * (This includes all existing switch chips as of Oct 2007.)
4980 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4981 */
4982 static void try_7322_autoneg(struct qib_pportdata *ppd)
4983 {
4984 unsigned long flags;
4985
4986 spin_lock_irqsave(&ppd->lflags_lock, flags);
4987 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
4988 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4989 qib_autoneg_7322_send(ppd, 0);
4990 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
4991 qib_7322_mini_pcs_reset(ppd);
4992 /* 2 msec is minimum length of a poll cycle */
4993 schedule_delayed_work(&ppd->cpspec->autoneg_work,
4994 msecs_to_jiffies(2));
4995 }
4996
4997 /*
4998 * Handle the empirically determined mechanism for auto-negotiation
4999 * of DDR speed with switches.
5000 */
5001 static void autoneg_7322_work(struct work_struct *work)
5002 {
5003 struct qib_pportdata *ppd;
5004 struct qib_devdata *dd;
5005 u64 startms;
5006 u32 i;
5007 unsigned long flags;
5008
5009 ppd = container_of(work, struct qib_chippport_specific,
5010 autoneg_work.work)->ppd;
5011 dd = ppd->dd;
5012
5013 startms = jiffies_to_msecs(jiffies);
5014
5015 /*
5016 * Busy wait for this first part, it should be at most a
5017 * few hundred usec, since we scheduled ourselves for 2msec.
5018 */
5019 for (i = 0; i < 25; i++) {
5020 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5021 == IB_7322_LT_STATE_POLLQUIET) {
5022 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5023 break;
5024 }
5025 udelay(100);
5026 }
5027
5028 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5029 goto done; /* we got there early or told to stop */
5030
5031 /* we expect this to timeout */
5032 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5033 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5034 msecs_to_jiffies(90)))
5035 goto done;
5036 qib_7322_mini_pcs_reset(ppd);
5037
5038 /* we expect this to timeout */
5039 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5040 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5041 msecs_to_jiffies(1700)))
5042 goto done;
5043 qib_7322_mini_pcs_reset(ppd);
5044
5045 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5046
5047 /*
5048 * Wait up to 250 msec for link to train and get to INIT at DDR;
5049 * this should terminate early.
5050 */
5051 wait_event_timeout(ppd->cpspec->autoneg_wait,
5052 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5053 msecs_to_jiffies(250));
5054 done:
5055 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5056 spin_lock_irqsave(&ppd->lflags_lock, flags);
5057 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5058 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5059 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5060 ppd->cpspec->autoneg_tries = 0;
5061 }
5062 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5063 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5064 }
5065 }
5066
5067 /*
5068 * This routine is used to request IPG set in the QLogic switch.
5069 * Only called if r1.
5070 */
5071 static void try_7322_ipg(struct qib_pportdata *ppd)
5072 {
5073 struct qib_ibport *ibp = &ppd->ibport_data;
5074 struct ib_mad_send_buf *send_buf;
5075 struct ib_mad_agent *agent;
5076 struct ib_smp *smp;
5077 unsigned delay;
5078 int ret;
5079
5080 agent = ibp->send_agent;
5081 if (!agent)
5082 goto retry;
5083
5084 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5085 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5086 if (IS_ERR(send_buf))
5087 goto retry;
5088
5089 if (!ibp->smi_ah) {
5090 struct ib_ah_attr attr;
5091 struct ib_ah *ah;
5092
5093 memset(&attr, 0, sizeof attr);
5094 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5095 attr.port_num = ppd->port;
5096 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5097 if (IS_ERR(ah))
5098 ret = -EINVAL;
5099 else {
5100 send_buf->ah = ah;
5101 ibp->smi_ah = to_iah(ah);
5102 ret = 0;
5103 }
5104 } else {
5105 send_buf->ah = &ibp->smi_ah->ibah;
5106 ret = 0;
5107 }
5108
5109 smp = send_buf->mad;
5110 smp->base_version = IB_MGMT_BASE_VERSION;
5111 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5112 smp->class_version = 1;
5113 smp->method = IB_MGMT_METHOD_SEND;
5114 smp->hop_cnt = 1;
5115 smp->attr_id = QIB_VENDOR_IPG;
5116 smp->attr_mod = 0;
5117
5118 if (!ret)
5119 ret = ib_post_send_mad(send_buf, NULL);
5120 if (ret)
5121 ib_free_send_mad(send_buf);
5122 retry:
5123 delay = 2 << ppd->cpspec->ipg_tries;
5124 schedule_delayed_work(&ppd->cpspec->ipg_work, msecs_to_jiffies(delay));
5125 }
5126
5127 /*
5128 * Timeout handler for setting IPG.
5129 * Only called if r1.
5130 */
5131 static void ipg_7322_work(struct work_struct *work)
5132 {
5133 struct qib_pportdata *ppd;
5134
5135 ppd = container_of(work, struct qib_chippport_specific,
5136 ipg_work.work)->ppd;
5137 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5138 && ++ppd->cpspec->ipg_tries <= 10)
5139 try_7322_ipg(ppd);
5140 }
5141
5142 static u32 qib_7322_iblink_state(u64 ibcs)
5143 {
5144 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5145
5146 switch (state) {
5147 case IB_7322_L_STATE_INIT:
5148 state = IB_PORT_INIT;
5149 break;
5150 case IB_7322_L_STATE_ARM:
5151 state = IB_PORT_ARMED;
5152 break;
5153 case IB_7322_L_STATE_ACTIVE:
5154 /* fall through */
5155 case IB_7322_L_STATE_ACT_DEFER:
5156 state = IB_PORT_ACTIVE;
5157 break;
5158 default: /* fall through */
5159 case IB_7322_L_STATE_DOWN:
5160 state = IB_PORT_DOWN;
5161 break;
5162 }
5163 return state;
5164 }
5165
5166 /* returns the IBTA port state, rather than the IBC link training state */
5167 static u8 qib_7322_phys_portstate(u64 ibcs)
5168 {
5169 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5170 return qib_7322_physportstate[state];
5171 }
5172
5173 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5174 {
5175 int ret = 0, symadj = 0;
5176 unsigned long flags;
5177 int mult;
5178
5179 spin_lock_irqsave(&ppd->lflags_lock, flags);
5180 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5181 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5182
5183 /* Update our picture of width and speed from chip */
5184 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5185 ppd->link_speed_active = QIB_IB_QDR;
5186 mult = 4;
5187 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5188 ppd->link_speed_active = QIB_IB_DDR;
5189 mult = 2;
5190 } else {
5191 ppd->link_speed_active = QIB_IB_SDR;
5192 mult = 1;
5193 }
5194 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5195 ppd->link_width_active = IB_WIDTH_4X;
5196 mult *= 4;
5197 } else
5198 ppd->link_width_active = IB_WIDTH_1X;
5199 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5200
5201 if (!ibup) {
5202 u64 clr;
5203
5204 /* Link went down. */
5205 /* do IPG MAD again after linkdown, even if last time failed */
5206 ppd->cpspec->ipg_tries = 0;
5207 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5208 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5209 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5210 if (clr)
5211 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5212 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5213 QIBL_IB_AUTONEG_INPROG)))
5214 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5215 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5216 /* unlock the Tx settings, speed may change */
5217 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5218 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5219 reset_tx_deemphasis_override));
5220 qib_cancel_sends(ppd);
5221 /* on link down, ensure sane pcs state */
5222 qib_7322_mini_pcs_reset(ppd);
5223 spin_lock_irqsave(&ppd->sdma_lock, flags);
5224 if (__qib_sdma_running(ppd))
5225 __qib_sdma_process_event(ppd,
5226 qib_sdma_event_e70_go_idle);
5227 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5228 }
5229 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5230 if (clr == ppd->cpspec->iblnkdownsnap)
5231 ppd->cpspec->iblnkdowndelta++;
5232 } else {
5233 if (qib_compat_ddr_negotiate &&
5234 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5235 QIBL_IB_AUTONEG_INPROG)) &&
5236 ppd->link_speed_active == QIB_IB_SDR &&
5237 (ppd->link_speed_enabled & QIB_IB_DDR)
5238 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5239 /* we are SDR, and auto-negotiation enabled */
5240 ++ppd->cpspec->autoneg_tries;
5241 if (!ppd->cpspec->ibdeltainprog) {
5242 ppd->cpspec->ibdeltainprog = 1;
5243 ppd->cpspec->ibsymdelta +=
5244 read_7322_creg32_port(ppd,
5245 crp_ibsymbolerr) -
5246 ppd->cpspec->ibsymsnap;
5247 ppd->cpspec->iblnkerrdelta +=
5248 read_7322_creg32_port(ppd,
5249 crp_iblinkerrrecov) -
5250 ppd->cpspec->iblnkerrsnap;
5251 }
5252 try_7322_autoneg(ppd);
5253 ret = 1; /* no other IB status change processing */
5254 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5255 ppd->link_speed_active == QIB_IB_SDR) {
5256 qib_autoneg_7322_send(ppd, 1);
5257 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5258 qib_7322_mini_pcs_reset(ppd);
5259 udelay(2);
5260 ret = 1; /* no other IB status change processing */
5261 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5262 (ppd->link_speed_active & QIB_IB_DDR)) {
5263 spin_lock_irqsave(&ppd->lflags_lock, flags);
5264 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5265 QIBL_IB_AUTONEG_FAILED);
5266 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5267 ppd->cpspec->autoneg_tries = 0;
5268 /* re-enable SDR, for next link down */
5269 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5270 wake_up(&ppd->cpspec->autoneg_wait);
5271 symadj = 1;
5272 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5273 /*
5274 * Clear autoneg failure flag, and do setup
5275 * so we'll try next time link goes down and
5276 * back to INIT (possibly connected to a
5277 * different device).
5278 */
5279 spin_lock_irqsave(&ppd->lflags_lock, flags);
5280 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5281 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5282 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5283 symadj = 1;
5284 }
5285 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5286 symadj = 1;
5287 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5288 try_7322_ipg(ppd);
5289 if (!ppd->cpspec->recovery_init)
5290 setup_7322_link_recovery(ppd, 0);
5291 ppd->cpspec->qdr_dfe_time = jiffies +
5292 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5293 }
5294 ppd->cpspec->ibmalfusesnap = 0;
5295 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5296 crp_errlink);
5297 }
5298 if (symadj) {
5299 ppd->cpspec->iblnkdownsnap =
5300 read_7322_creg32_port(ppd, crp_iblinkdown);
5301 if (ppd->cpspec->ibdeltainprog) {
5302 ppd->cpspec->ibdeltainprog = 0;
5303 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5304 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5305 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5306 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5307 }
5308 } else if (!ibup && qib_compat_ddr_negotiate &&
5309 !ppd->cpspec->ibdeltainprog &&
5310 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5311 ppd->cpspec->ibdeltainprog = 1;
5312 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5313 crp_ibsymbolerr);
5314 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5315 crp_iblinkerrrecov);
5316 }
5317
5318 if (!ret)
5319 qib_setup_7322_setextled(ppd, ibup);
5320 return ret;
5321 }
5322
5323 /*
5324 * Does read/modify/write to appropriate registers to
5325 * set output and direction bits selected by mask.
5326 * these are in their canonical postions (e.g. lsb of
5327 * dir will end up in D48 of extctrl on existing chips).
5328 * returns contents of GP Inputs.
5329 */
5330 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5331 {
5332 u64 read_val, new_out;
5333 unsigned long flags;
5334
5335 if (mask) {
5336 /* some bits being written, lock access to GPIO */
5337 dir &= mask;
5338 out &= mask;
5339 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5340 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5341 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5342 new_out = (dd->cspec->gpio_out & ~mask) | out;
5343
5344 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5345 qib_write_kreg(dd, kr_gpio_out, new_out);
5346 dd->cspec->gpio_out = new_out;
5347 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5348 }
5349 /*
5350 * It is unlikely that a read at this time would get valid
5351 * data on a pin whose direction line was set in the same
5352 * call to this function. We include the read here because
5353 * that allows us to potentially combine a change on one pin with
5354 * a read on another, and because the old code did something like
5355 * this.
5356 */
5357 read_val = qib_read_kreg64(dd, kr_extstatus);
5358 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5359 }
5360
5361 /* Enable writes to config EEPROM, if possible. Returns previous state */
5362 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5363 {
5364 int prev_wen;
5365 u32 mask;
5366
5367 mask = 1 << QIB_EEPROM_WEN_NUM;
5368 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5369 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5370
5371 return prev_wen & 1;
5372 }
5373
5374 /*
5375 * Read fundamental info we need to use the chip. These are
5376 * the registers that describe chip capabilities, and are
5377 * saved in shadow registers.
5378 */
5379 static void get_7322_chip_params(struct qib_devdata *dd)
5380 {
5381 u64 val;
5382 u32 piobufs;
5383 int mtu;
5384
5385 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5386
5387 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5388
5389 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5390 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5391 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5392 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5393 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5394
5395 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5396 dd->piobcnt2k = val & ~0U;
5397 dd->piobcnt4k = val >> 32;
5398 val = qib_read_kreg64(dd, kr_sendpiosize);
5399 dd->piosize2k = val & ~0U;
5400 dd->piosize4k = val >> 32;
5401
5402 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5403 if (mtu == -1)
5404 mtu = QIB_DEFAULT_MTU;
5405 dd->pport[0].ibmtu = (u32)mtu;
5406 dd->pport[1].ibmtu = (u32)mtu;
5407
5408 /* these may be adjusted in init_chip_wc_pat() */
5409 dd->pio2kbase = (u32 __iomem *)
5410 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5411 dd->pio4kbase = (u32 __iomem *)
5412 ((char __iomem *) dd->kregbase +
5413 (dd->piobufbase >> 32));
5414 /*
5415 * 4K buffers take 2 pages; we use roundup just to be
5416 * paranoid; we calculate it once here, rather than on
5417 * ever buf allocate
5418 */
5419 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5420
5421 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5422
5423 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5424 (sizeof(u64) * BITS_PER_BYTE / 2);
5425 }
5426
5427 /*
5428 * The chip base addresses in cspec and cpspec have to be set
5429 * after possible init_chip_wc_pat(), rather than in
5430 * get_7322_chip_params(), so split out as separate function
5431 */
5432 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5433 {
5434 u32 cregbase;
5435 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5436
5437 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5438 (char __iomem *)dd->kregbase);
5439
5440 dd->egrtidbase = (u64 __iomem *)
5441 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5442
5443 /* port registers are defined as relative to base of chip */
5444 dd->pport[0].cpspec->kpregbase =
5445 (u64 __iomem *)((char __iomem *)dd->kregbase);
5446 dd->pport[1].cpspec->kpregbase =
5447 (u64 __iomem *)(dd->palign +
5448 (char __iomem *)dd->kregbase);
5449 dd->pport[0].cpspec->cpregbase =
5450 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5451 kr_counterregbase) + (char __iomem *)dd->kregbase);
5452 dd->pport[1].cpspec->cpregbase =
5453 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5454 kr_counterregbase) + (char __iomem *)dd->kregbase);
5455 }
5456
5457 /*
5458 * This is a fairly special-purpose observer, so we only support
5459 * the port-specific parts of SendCtrl
5460 */
5461
5462 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5463 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5464 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5465 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5466 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5467 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5468 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5469
5470 static int sendctrl_hook(struct qib_devdata *dd,
5471 const struct diag_observer *op, u32 offs,
5472 u64 *data, u64 mask, int only_32)
5473 {
5474 unsigned long flags;
5475 unsigned idx;
5476 unsigned pidx;
5477 struct qib_pportdata *ppd = NULL;
5478 u64 local_data, all_bits;
5479
5480 /*
5481 * The fixed correspondence between Physical ports and pports is
5482 * severed. We need to hunt for the ppd that corresponds
5483 * to the offset we got. And we have to do that without admitting
5484 * we know the stride, apparently.
5485 */
5486 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5487 u64 __iomem *psptr;
5488 u32 psoffs;
5489
5490 ppd = dd->pport + pidx;
5491 if (!ppd->cpspec->kpregbase)
5492 continue;
5493
5494 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5495 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5496 if (psoffs == offs)
5497 break;
5498 }
5499
5500 /* If pport is not being managed by driver, just avoid shadows. */
5501 if (pidx >= dd->num_pports)
5502 ppd = NULL;
5503
5504 /* In any case, "idx" is flat index in kreg space */
5505 idx = offs / sizeof(u64);
5506
5507 all_bits = ~0ULL;
5508 if (only_32)
5509 all_bits >>= 32;
5510
5511 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5512 if (!ppd || (mask & all_bits) != all_bits) {
5513 /*
5514 * At least some mask bits are zero, so we need
5515 * to read. The judgement call is whether from
5516 * reg or shadow. First-cut: read reg, and complain
5517 * if any bits which should be shadowed are different
5518 * from their shadowed value.
5519 */
5520 if (only_32)
5521 local_data = (u64)qib_read_kreg32(dd, idx);
5522 else
5523 local_data = qib_read_kreg64(dd, idx);
5524 *data = (local_data & ~mask) | (*data & mask);
5525 }
5526 if (mask) {
5527 /*
5528 * At least some mask bits are one, so we need
5529 * to write, but only shadow some bits.
5530 */
5531 u64 sval, tval; /* Shadowed, transient */
5532
5533 /*
5534 * New shadow val is bits we don't want to touch,
5535 * ORed with bits we do, that are intended for shadow.
5536 */
5537 if (ppd) {
5538 sval = ppd->p_sendctrl & ~mask;
5539 sval |= *data & SENDCTRL_SHADOWED & mask;
5540 ppd->p_sendctrl = sval;
5541 } else
5542 sval = *data & SENDCTRL_SHADOWED & mask;
5543 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5544 qib_write_kreg(dd, idx, tval);
5545 qib_write_kreg(dd, kr_scratch, 0Ull);
5546 }
5547 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5548 return only_32 ? 4 : 8;
5549 }
5550
5551 static const struct diag_observer sendctrl_0_observer = {
5552 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5553 KREG_IDX(SendCtrl_0) * sizeof(u64)
5554 };
5555
5556 static const struct diag_observer sendctrl_1_observer = {
5557 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5558 KREG_IDX(SendCtrl_1) * sizeof(u64)
5559 };
5560
5561 static ushort sdma_fetch_prio = 8;
5562 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5563 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5564
5565 /* Besides logging QSFP events, we set appropriate TxDDS values */
5566 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5567
5568 static void qsfp_7322_event(struct work_struct *work)
5569 {
5570 struct qib_qsfp_data *qd;
5571 struct qib_pportdata *ppd;
5572 u64 pwrup;
5573 int ret;
5574 u32 le2;
5575
5576 qd = container_of(work, struct qib_qsfp_data, work);
5577 ppd = qd->ppd;
5578 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5579
5580 /*
5581 * Some QSFP's not only do not respond until the full power-up
5582 * time, but may behave badly if we try. So hold off responding
5583 * to insertion.
5584 */
5585 while (1) {
5586 u64 now = get_jiffies_64();
5587 if (time_after64(now, pwrup))
5588 break;
5589 msleep(20);
5590 }
5591 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5592 /*
5593 * Need to change LE2 back to defaults if we couldn't
5594 * read the cable type (to handle cable swaps), so do this
5595 * even on failure to read cable information. We don't
5596 * get here for QME, so IS_QME check not needed here.
5597 */
5598 le2 = (!ret && qd->cache.atten[1] >= qib_long_atten &&
5599 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5600 LE2_5m : LE2_DEFAULT;
5601 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5602 init_txdds_table(ppd, 0);
5603 }
5604
5605 /*
5606 * There is little we can do but complain to the user if QSFP
5607 * initialization fails.
5608 */
5609 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5610 {
5611 unsigned long flags;
5612 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5613 struct qib_devdata *dd = ppd->dd;
5614 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5615
5616 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5617 qd->ppd = ppd;
5618 qib_qsfp_init(qd, qsfp_7322_event);
5619 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5620 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5621 dd->cspec->gpio_mask |= mod_prs_bit;
5622 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5623 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5624 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5625 }
5626
5627 /*
5628 * called at device initialization time, and also if the txselect
5629 * module parameter is changed. This is used for cables that don't
5630 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5631 * We initialize to the default, then if there is a specific
5632 * unit,port match, we use that (and set it immediately, for the
5633 * current speed, if the link is at INIT or better).
5634 * String format is "default# unit#,port#=# ... u,p=#", separators must
5635 * be a SPACE character. A newline terminates. The u,p=# tuples may
5636 * optionally have "u,p=#,#", where the final # is the H1 value
5637 * The last specific match is used (actually, all are used, but last
5638 * one is the one that winds up set); if none at all, fall back on default.
5639 */
5640 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5641 {
5642 char *nxt, *str;
5643 u32 pidx, unit, port, deflt, h1;
5644 unsigned long val;
5645 int any = 0, seth1;
5646 int txdds_size;
5647
5648 str = txselect_list;
5649
5650 /* default number is validated in setup_txselect() */
5651 deflt = simple_strtoul(str, &nxt, 0);
5652 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5653 dd->pport[pidx].cpspec->no_eep = deflt;
5654
5655 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5656 if (IS_QME(dd) || IS_QMH(dd))
5657 txdds_size += TXDDS_MFG_SZ;
5658
5659 while (*nxt && nxt[1]) {
5660 str = ++nxt;
5661 unit = simple_strtoul(str, &nxt, 0);
5662 if (nxt == str || !*nxt || *nxt != ',') {
5663 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5664 ;
5665 continue;
5666 }
5667 str = ++nxt;
5668 port = simple_strtoul(str, &nxt, 0);
5669 if (nxt == str || *nxt != '=') {
5670 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5671 ;
5672 continue;
5673 }
5674 str = ++nxt;
5675 val = simple_strtoul(str, &nxt, 0);
5676 if (nxt == str) {
5677 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5678 ;
5679 continue;
5680 }
5681 if (val >= txdds_size)
5682 continue;
5683 seth1 = 0;
5684 h1 = 0; /* gcc thinks it might be used uninitted */
5685 if (*nxt == ',' && nxt[1]) {
5686 str = ++nxt;
5687 h1 = (u32)simple_strtoul(str, &nxt, 0);
5688 if (nxt == str)
5689 while (*nxt && *nxt++ != ' ') /* skip */
5690 ;
5691 else
5692 seth1 = 1;
5693 }
5694 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5695 ++pidx) {
5696 struct qib_pportdata *ppd = &dd->pport[pidx];
5697
5698 if (ppd->port != port || !ppd->link_speed_supported)
5699 continue;
5700 ppd->cpspec->no_eep = val;
5701 if (seth1)
5702 ppd->cpspec->h1_val = h1;
5703 /* now change the IBC and serdes, overriding generic */
5704 init_txdds_table(ppd, 1);
5705 any++;
5706 }
5707 if (*nxt == '\n')
5708 break; /* done */
5709 }
5710 if (change && !any) {
5711 /* no specific setting, use the default.
5712 * Change the IBC and serdes, but since it's
5713 * general, don't override specific settings.
5714 */
5715 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5716 if (dd->pport[pidx].link_speed_supported)
5717 init_txdds_table(&dd->pport[pidx], 0);
5718 }
5719 }
5720
5721 /* handle the txselect parameter changing */
5722 static int setup_txselect(const char *str, struct kernel_param *kp)
5723 {
5724 struct qib_devdata *dd;
5725 unsigned long val;
5726 char *n;
5727 if (strlen(str) >= MAX_ATTEN_LEN) {
5728 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5729 "too long\n");
5730 return -ENOSPC;
5731 }
5732 val = simple_strtoul(str, &n, 0);
5733 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5734 TXDDS_MFG_SZ)) {
5735 printk(KERN_INFO QIB_DRV_NAME
5736 "txselect_values must start with a number < %d\n",
5737 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5738 return -EINVAL;
5739 }
5740 strcpy(txselect_list, str);
5741
5742 list_for_each_entry(dd, &qib_dev_list, list)
5743 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5744 set_no_qsfp_atten(dd, 1);
5745 return 0;
5746 }
5747
5748 /*
5749 * Write the final few registers that depend on some of the
5750 * init setup. Done late in init, just before bringing up
5751 * the serdes.
5752 */
5753 static int qib_late_7322_initreg(struct qib_devdata *dd)
5754 {
5755 int ret = 0, n;
5756 u64 val;
5757
5758 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5759 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5760 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5761 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5762 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5763 if (val != dd->pioavailregs_phys) {
5764 qib_dev_err(dd, "Catastrophic software error, "
5765 "SendPIOAvailAddr written as %lx, "
5766 "read back as %llx\n",
5767 (unsigned long) dd->pioavailregs_phys,
5768 (unsigned long long) val);
5769 ret = -EINVAL;
5770 }
5771
5772 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5773 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5774 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5775 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5776
5777 qib_register_observer(dd, &sendctrl_0_observer);
5778 qib_register_observer(dd, &sendctrl_1_observer);
5779
5780 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5781 qib_write_kreg(dd, kr_control, dd->control);
5782 /*
5783 * Set SendDmaFetchPriority and init Tx params, including
5784 * QSFP handler on boards that have QSFP.
5785 * First set our default attenuation entry for cables that
5786 * don't have valid attenuation.
5787 */
5788 set_no_qsfp_atten(dd, 0);
5789 for (n = 0; n < dd->num_pports; ++n) {
5790 struct qib_pportdata *ppd = dd->pport + n;
5791
5792 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5793 sdma_fetch_prio & 0xf);
5794 /* Initialize qsfp if present on board. */
5795 if (dd->flags & QIB_HAS_QSFP)
5796 qib_init_7322_qsfp(ppd);
5797 }
5798 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5799 qib_write_kreg(dd, kr_control, dd->control);
5800
5801 return ret;
5802 }
5803
5804 /* per IB port errors. */
5805 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5806 MASK_ACROSS(8, 15))
5807 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5808 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5809 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5810 MASK_ACROSS(0, 11))
5811
5812 /*
5813 * Write the initialization per-port registers that need to be done at
5814 * driver load and after reset completes (i.e., that aren't done as part
5815 * of other init procedures called from qib_init.c).
5816 * Some of these should be redundant on reset, but play safe.
5817 */
5818 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5819 {
5820 u64 val;
5821 int i;
5822
5823 if (!ppd->link_speed_supported) {
5824 /* no buffer credits for this port */
5825 for (i = 1; i < 8; i++)
5826 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5827 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5828 qib_write_kreg(ppd->dd, kr_scratch, 0);
5829 return;
5830 }
5831
5832 /*
5833 * Set the number of supported virtual lanes in IBC,
5834 * for flow control packet handling on unsupported VLs
5835 */
5836 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5837 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5838 val |= (u64)(ppd->vls_supported - 1) <<
5839 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5840 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5841
5842 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5843
5844 /* enable tx header checking */
5845 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5846 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5847 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5848
5849 qib_write_kreg_port(ppd, krp_ncmodectrl,
5850 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5851
5852 /*
5853 * Unconditionally clear the bufmask bits. If SDMA is
5854 * enabled, we'll set them appropriately later.
5855 */
5856 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5857 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5858 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5859 if (ppd->dd->cspec->r1)
5860 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5861 }
5862
5863 /*
5864 * Write the initialization per-device registers that need to be done at
5865 * driver load and after reset completes (i.e., that aren't done as part
5866 * of other init procedures called from qib_init.c). Also write per-port
5867 * registers that are affected by overall device config, such as QP mapping
5868 * Some of these should be redundant on reset, but play safe.
5869 */
5870 static void write_7322_initregs(struct qib_devdata *dd)
5871 {
5872 struct qib_pportdata *ppd;
5873 int i, pidx;
5874 u64 val;
5875
5876 /* Set Multicast QPs received by port 2 to map to context one. */
5877 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5878
5879 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5880 unsigned n, regno;
5881 unsigned long flags;
5882
5883 if (dd->n_krcv_queues < 2 ||
5884 !dd->pport[pidx].link_speed_supported)
5885 continue;
5886
5887 ppd = &dd->pport[pidx];
5888
5889 /* be paranoid against later code motion, etc. */
5890 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5891 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5892 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5893
5894 /* Initialize QP to context mapping */
5895 regno = krp_rcvqpmaptable;
5896 val = 0;
5897 if (dd->num_pports > 1)
5898 n = dd->first_user_ctxt / dd->num_pports;
5899 else
5900 n = dd->first_user_ctxt - 1;
5901 for (i = 0; i < 32; ) {
5902 unsigned ctxt;
5903
5904 if (dd->num_pports > 1)
5905 ctxt = (i % n) * dd->num_pports + pidx;
5906 else if (i % n)
5907 ctxt = (i % n) + 1;
5908 else
5909 ctxt = ppd->hw_pidx;
5910 val |= ctxt << (5 * (i % 6));
5911 i++;
5912 if (i % 6 == 0) {
5913 qib_write_kreg_port(ppd, regno, val);
5914 val = 0;
5915 regno++;
5916 }
5917 }
5918 qib_write_kreg_port(ppd, regno, val);
5919 }
5920
5921 /*
5922 * Setup up interrupt mitigation for kernel contexts, but
5923 * not user contexts (user contexts use interrupts when
5924 * stalled waiting for any packet, so want those interrupts
5925 * right away).
5926 */
5927 for (i = 0; i < dd->first_user_ctxt; i++) {
5928 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5929 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5930 }
5931
5932 /*
5933 * Initialize as (disabled) rcvflow tables. Application code
5934 * will setup each flow as it uses the flow.
5935 * Doesn't clear any of the error bits that might be set.
5936 */
5937 val = TIDFLOW_ERRBITS; /* these are W1C */
5938 for (i = 0; i < dd->cfgctxts; i++) {
5939 int flow;
5940 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5941 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5942 }
5943
5944 /*
5945 * dual cards init to dual port recovery, single port cards to
5946 * the one port. Dual port cards may later adjust to 1 port,
5947 * and then back to dual port if both ports are connected
5948 * */
5949 if (dd->num_pports)
5950 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5951 }
5952
5953 static int qib_init_7322_variables(struct qib_devdata *dd)
5954 {
5955 struct qib_pportdata *ppd;
5956 unsigned features, pidx, sbufcnt;
5957 int ret, mtu;
5958 u32 sbufs, updthresh;
5959
5960 /* pport structs are contiguous, allocated after devdata */
5961 ppd = (struct qib_pportdata *)(dd + 1);
5962 dd->pport = ppd;
5963 ppd[0].dd = dd;
5964 ppd[1].dd = dd;
5965
5966 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5967
5968 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5969 ppd[1].cpspec = &ppd[0].cpspec[1];
5970 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
5971 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
5972
5973 spin_lock_init(&dd->cspec->rcvmod_lock);
5974 spin_lock_init(&dd->cspec->gpio_lock);
5975
5976 /* we haven't yet set QIB_PRESENT, so use read directly */
5977 dd->revision = readq(&dd->kregbase[kr_revision]);
5978
5979 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
5980 qib_dev_err(dd, "Revision register read failure, "
5981 "giving up initialization\n");
5982 ret = -ENODEV;
5983 goto bail;
5984 }
5985 dd->flags |= QIB_PRESENT; /* now register routines work */
5986
5987 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
5988 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
5989 dd->cspec->r1 = dd->minrev == 1;
5990
5991 get_7322_chip_params(dd);
5992 features = qib_7322_boardname(dd);
5993
5994 /* now that piobcnt2k and 4k set, we can allocate these */
5995 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
5996 NUM_VL15_BUFS + BITS_PER_LONG - 1;
5997 sbufcnt /= BITS_PER_LONG;
5998 dd->cspec->sendchkenable = kmalloc(sbufcnt *
5999 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
6000 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
6001 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
6002 dd->cspec->sendibchk = kmalloc(sbufcnt *
6003 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
6004 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
6005 !dd->cspec->sendibchk) {
6006 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
6007 ret = -ENOMEM;
6008 goto bail;
6009 }
6010
6011 ppd = dd->pport;
6012
6013 /*
6014 * GPIO bits for TWSI data and clock,
6015 * used for serial EEPROM.
6016 */
6017 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6018 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6019 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6020
6021 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6022 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6023 QIB_HAS_THRESH_UPDATE |
6024 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6025 dd->flags |= qib_special_trigger ?
6026 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6027
6028 /*
6029 * Setup initial values. These may change when PAT is enabled, but
6030 * we need these to do initial chip register accesses.
6031 */
6032 qib_7322_set_baseaddrs(dd);
6033
6034 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6035 if (mtu == -1)
6036 mtu = QIB_DEFAULT_MTU;
6037
6038 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6039 /* all hwerrors become interrupts, unless special purposed */
6040 dd->cspec->hwerrmask = ~0ULL;
6041 /* link_recovery setup causes these errors, so ignore them,
6042 * other than clearing them when they occur */
6043 dd->cspec->hwerrmask &=
6044 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6045 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6046 HWE_MASK(LATriggered));
6047
6048 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6049 struct qib_chippport_specific *cp = ppd->cpspec;
6050 ppd->link_speed_supported = features & PORT_SPD_CAP;
6051 features >>= PORT_SPD_CAP_SHIFT;
6052 if (!ppd->link_speed_supported) {
6053 /* single port mode (7340, or configured) */
6054 dd->skip_kctxt_mask |= 1 << pidx;
6055 if (pidx == 0) {
6056 /* Make sure port is disabled. */
6057 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6058 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6059 ppd[0] = ppd[1];
6060 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6061 IBSerdesPClkNotDetectMask_0)
6062 | SYM_MASK(HwErrMask,
6063 SDmaMemReadErrMask_0));
6064 dd->cspec->int_enable_mask &= ~(
6065 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6066 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6067 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6068 SYM_MASK(IntMask, SDmaIntMask_0) |
6069 SYM_MASK(IntMask, ErrIntMask_0) |
6070 SYM_MASK(IntMask, SendDoneIntMask_0));
6071 } else {
6072 /* Make sure port is disabled. */
6073 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6074 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6075 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6076 IBSerdesPClkNotDetectMask_1)
6077 | SYM_MASK(HwErrMask,
6078 SDmaMemReadErrMask_1));
6079 dd->cspec->int_enable_mask &= ~(
6080 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6081 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6082 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6083 SYM_MASK(IntMask, SDmaIntMask_1) |
6084 SYM_MASK(IntMask, ErrIntMask_1) |
6085 SYM_MASK(IntMask, SendDoneIntMask_1));
6086 }
6087 continue;
6088 }
6089
6090 dd->num_pports++;
6091 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6092
6093 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6094 ppd->link_width_enabled = IB_WIDTH_4X;
6095 ppd->link_speed_enabled = ppd->link_speed_supported;
6096 /*
6097 * Set the initial values to reasonable default, will be set
6098 * for real when link is up.
6099 */
6100 ppd->link_width_active = IB_WIDTH_4X;
6101 ppd->link_speed_active = QIB_IB_SDR;
6102 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6103 switch (qib_num_cfg_vls) {
6104 case 1:
6105 ppd->vls_supported = IB_VL_VL0;
6106 break;
6107 case 2:
6108 ppd->vls_supported = IB_VL_VL0_1;
6109 break;
6110 default:
6111 qib_devinfo(dd->pcidev,
6112 "Invalid num_vls %u, using 4 VLs\n",
6113 qib_num_cfg_vls);
6114 qib_num_cfg_vls = 4;
6115 /* fall through */
6116 case 4:
6117 ppd->vls_supported = IB_VL_VL0_3;
6118 break;
6119 case 8:
6120 if (mtu <= 2048)
6121 ppd->vls_supported = IB_VL_VL0_7;
6122 else {
6123 qib_devinfo(dd->pcidev,
6124 "Invalid num_vls %u for MTU %d "
6125 ", using 4 VLs\n",
6126 qib_num_cfg_vls, mtu);
6127 ppd->vls_supported = IB_VL_VL0_3;
6128 qib_num_cfg_vls = 4;
6129 }
6130 break;
6131 }
6132 ppd->vls_operational = ppd->vls_supported;
6133
6134 init_waitqueue_head(&cp->autoneg_wait);
6135 INIT_DELAYED_WORK(&cp->autoneg_work,
6136 autoneg_7322_work);
6137 if (ppd->dd->cspec->r1)
6138 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6139
6140 /*
6141 * For Mez and similar cards, no qsfp info, so do
6142 * the "cable info" setup here. Can be overridden
6143 * in adapter-specific routines.
6144 */
6145 if (!(dd->flags & QIB_HAS_QSFP)) {
6146 if (!IS_QMH(dd) && !IS_QME(dd))
6147 qib_devinfo(dd->pcidev, "IB%u:%u: "
6148 "Unknown mezzanine card type\n",
6149 dd->unit, ppd->port);
6150 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6151 /*
6152 * Choose center value as default tx serdes setting
6153 * until changed through module parameter.
6154 */
6155 ppd->cpspec->no_eep = IS_QMH(dd) ?
6156 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6157 } else
6158 cp->h1_val = H1_FORCE_VAL;
6159
6160 /* Avoid writes to chip for mini_init */
6161 if (!qib_mini_init)
6162 write_7322_init_portregs(ppd);
6163
6164 init_timer(&cp->chase_timer);
6165 cp->chase_timer.function = reenable_chase;
6166 cp->chase_timer.data = (unsigned long)ppd;
6167
6168 ppd++;
6169 }
6170
6171 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6172 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6173 dd->rcvhdrsize = qib_rcvhdrsize ?
6174 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6175 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6176
6177 /* we always allocate at least 2048 bytes for eager buffers */
6178 dd->rcvegrbufsize = max(mtu, 2048);
6179
6180 qib_7322_tidtemplate(dd);
6181
6182 /*
6183 * We can request a receive interrupt for 1 or
6184 * more packets from current offset.
6185 */
6186 dd->rhdrhead_intr_off =
6187 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6188
6189 /* setup the stats timer; the add_timer is done at end of init */
6190 init_timer(&dd->stats_timer);
6191 dd->stats_timer.function = qib_get_7322_faststats;
6192 dd->stats_timer.data = (unsigned long) dd;
6193
6194 dd->ureg_align = 0x10000; /* 64KB alignment */
6195
6196 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6197
6198 qib_7322_config_ctxts(dd);
6199 qib_set_ctxtcnt(dd);
6200
6201 if (qib_wc_pat) {
6202 resource_size_t vl15off;
6203 /*
6204 * We do not set WC on the VL15 buffers to avoid
6205 * a rare problem with unaligned writes from
6206 * interrupt-flushed store buffers, so we need
6207 * to map those separately here. We can't solve
6208 * this for the rarely used mtrr case.
6209 */
6210 ret = init_chip_wc_pat(dd, 0);
6211 if (ret)
6212 goto bail;
6213
6214 /* vl15 buffers start just after the 4k buffers */
6215 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6216 dd->piobcnt4k * dd->align4k;
6217 dd->piovl15base = ioremap_nocache(vl15off,
6218 NUM_VL15_BUFS * dd->align4k);
6219 if (!dd->piovl15base)
6220 goto bail;
6221 }
6222 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6223
6224 ret = 0;
6225 if (qib_mini_init)
6226 goto bail;
6227 if (!dd->num_pports) {
6228 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6229 goto bail; /* no error, so can still figure out why err */
6230 }
6231
6232 write_7322_initregs(dd);
6233 ret = qib_create_ctxts(dd);
6234 init_7322_cntrnames(dd);
6235
6236 updthresh = 8U; /* update threshold */
6237
6238 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6239 * reserve the update threshold amount for other kernel use, such
6240 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6241 * unless we aren't enabling SDMA, in which case we want to use
6242 * all the 4k bufs for the kernel.
6243 * if this was less than the update threshold, we could wait
6244 * a long time for an update. Coded this way because we
6245 * sometimes change the update threshold for various reasons,
6246 * and we want this to remain robust.
6247 */
6248 if (dd->flags & QIB_HAS_SEND_DMA) {
6249 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6250 sbufs = updthresh > 3 ? updthresh : 3;
6251 } else {
6252 dd->cspec->sdmabufcnt = 0;
6253 sbufs = dd->piobcnt4k;
6254 }
6255 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6256 dd->cspec->sdmabufcnt;
6257 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6258 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6259 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6260 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6261
6262 /*
6263 * If we have 16 user contexts, we will have 7 sbufs
6264 * per context, so reduce the update threshold to match. We
6265 * want to update before we actually run out, at low pbufs/ctxt
6266 * so give ourselves some margin.
6267 */
6268 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6269 updthresh = dd->pbufsctxt - 2;
6270 dd->cspec->updthresh_dflt = updthresh;
6271 dd->cspec->updthresh = updthresh;
6272
6273 /* before full enable, no interrupts, no locking needed */
6274 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6275 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6276 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6277
6278 dd->psxmitwait_supported = 1;
6279 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6280 bail:
6281 if (!dd->ctxtcnt)
6282 dd->ctxtcnt = 1; /* for other initialization code */
6283
6284 return ret;
6285 }
6286
6287 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6288 u32 *pbufnum)
6289 {
6290 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6291 struct qib_devdata *dd = ppd->dd;
6292
6293 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6294 if (pbc & PBC_7322_VL15_SEND) {
6295 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6296 last = first;
6297 } else {
6298 if ((plen + 1) > dd->piosize2kmax_dwords)
6299 first = dd->piobcnt2k;
6300 else
6301 first = 0;
6302 last = dd->cspec->lastbuf_for_pio;
6303 }
6304 return qib_getsendbuf_range(dd, pbufnum, first, last);
6305 }
6306
6307 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6308 u32 start)
6309 {
6310 qib_write_kreg_port(ppd, krp_psinterval, intv);
6311 qib_write_kreg_port(ppd, krp_psstart, start);
6312 }
6313
6314 /*
6315 * Must be called with sdma_lock held, or before init finished.
6316 */
6317 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6318 {
6319 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6320 }
6321
6322 static struct sdma_set_state_action sdma_7322_action_table[] = {
6323 [qib_sdma_state_s00_hw_down] = {
6324 .go_s99_running_tofalse = 1,
6325 .op_enable = 0,
6326 .op_intenable = 0,
6327 .op_halt = 0,
6328 .op_drain = 0,
6329 },
6330 [qib_sdma_state_s10_hw_start_up_wait] = {
6331 .op_enable = 0,
6332 .op_intenable = 1,
6333 .op_halt = 1,
6334 .op_drain = 0,
6335 },
6336 [qib_sdma_state_s20_idle] = {
6337 .op_enable = 1,
6338 .op_intenable = 1,
6339 .op_halt = 1,
6340 .op_drain = 0,
6341 },
6342 [qib_sdma_state_s30_sw_clean_up_wait] = {
6343 .op_enable = 0,
6344 .op_intenable = 1,
6345 .op_halt = 1,
6346 .op_drain = 0,
6347 },
6348 [qib_sdma_state_s40_hw_clean_up_wait] = {
6349 .op_enable = 1,
6350 .op_intenable = 1,
6351 .op_halt = 1,
6352 .op_drain = 0,
6353 },
6354 [qib_sdma_state_s50_hw_halt_wait] = {
6355 .op_enable = 1,
6356 .op_intenable = 1,
6357 .op_halt = 1,
6358 .op_drain = 1,
6359 },
6360 [qib_sdma_state_s99_running] = {
6361 .op_enable = 1,
6362 .op_intenable = 1,
6363 .op_halt = 0,
6364 .op_drain = 0,
6365 .go_s99_running_totrue = 1,
6366 },
6367 };
6368
6369 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6370 {
6371 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6372 }
6373
6374 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6375 {
6376 struct qib_devdata *dd = ppd->dd;
6377 unsigned lastbuf, erstbuf;
6378 u64 senddmabufmask[3] = { 0 };
6379 int n, ret = 0;
6380
6381 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6382 qib_sdma_7322_setlengen(ppd);
6383 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6384 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6385 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6386 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6387
6388 if (dd->num_pports)
6389 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6390 else
6391 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6392 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6393 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6394 dd->cspec->sdmabufcnt);
6395 lastbuf = erstbuf + n;
6396
6397 ppd->sdma_state.first_sendbuf = erstbuf;
6398 ppd->sdma_state.last_sendbuf = lastbuf;
6399 for (; erstbuf < lastbuf; ++erstbuf) {
6400 unsigned word = erstbuf / BITS_PER_LONG;
6401 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6402
6403 BUG_ON(word >= 3);
6404 senddmabufmask[word] |= 1ULL << bit;
6405 }
6406 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6407 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6408 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6409 return ret;
6410 }
6411
6412 /* sdma_lock must be held */
6413 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6414 {
6415 struct qib_devdata *dd = ppd->dd;
6416 int sane;
6417 int use_dmahead;
6418 u16 swhead;
6419 u16 swtail;
6420 u16 cnt;
6421 u16 hwhead;
6422
6423 use_dmahead = __qib_sdma_running(ppd) &&
6424 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6425 retry:
6426 hwhead = use_dmahead ?
6427 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6428 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6429
6430 swhead = ppd->sdma_descq_head;
6431 swtail = ppd->sdma_descq_tail;
6432 cnt = ppd->sdma_descq_cnt;
6433
6434 if (swhead < swtail)
6435 /* not wrapped */
6436 sane = (hwhead >= swhead) & (hwhead <= swtail);
6437 else if (swhead > swtail)
6438 /* wrapped around */
6439 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6440 (hwhead <= swtail);
6441 else
6442 /* empty */
6443 sane = (hwhead == swhead);
6444
6445 if (unlikely(!sane)) {
6446 if (use_dmahead) {
6447 /* try one more time, directly from the register */
6448 use_dmahead = 0;
6449 goto retry;
6450 }
6451 /* proceed as if no progress */
6452 hwhead = swhead;
6453 }
6454
6455 return hwhead;
6456 }
6457
6458 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6459 {
6460 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6461
6462 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6463 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6464 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6465 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6466 }
6467
6468 /*
6469 * Compute the amount of delay before sending the next packet if the
6470 * port's send rate differs from the static rate set for the QP.
6471 * The delay affects the next packet and the amount of the delay is
6472 * based on the length of the this packet.
6473 */
6474 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6475 u8 srate, u8 vl)
6476 {
6477 u8 snd_mult = ppd->delay_mult;
6478 u8 rcv_mult = ib_rate_to_delay[srate];
6479 u32 ret;
6480
6481 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6482
6483 /* Indicate VL15, else set the VL in the control word */
6484 if (vl == 15)
6485 ret |= PBC_7322_VL15_SEND_CTRL;
6486 else
6487 ret |= vl << PBC_VL_NUM_LSB;
6488 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6489
6490 return ret;
6491 }
6492
6493 /*
6494 * Enable the per-port VL15 send buffers for use.
6495 * They follow the rest of the buffers, without a config parameter.
6496 * This was in initregs, but that is done before the shadow
6497 * is set up, and this has to be done after the shadow is
6498 * set up.
6499 */
6500 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6501 {
6502 unsigned vl15bufs;
6503
6504 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6505 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6506 TXCHK_CHG_TYPE_KERN, NULL);
6507 }
6508
6509 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6510 {
6511 if (rcd->ctxt < NUM_IB_PORTS) {
6512 if (rcd->dd->num_pports > 1) {
6513 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6514 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6515 } else {
6516 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6517 rcd->rcvegr_tid_base = 0;
6518 }
6519 } else {
6520 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6521 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6522 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6523 }
6524 }
6525
6526 #define QTXSLEEPS 5000
6527 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6528 u32 len, u32 which, struct qib_ctxtdata *rcd)
6529 {
6530 int i;
6531 const int last = start + len - 1;
6532 const int lastr = last / BITS_PER_LONG;
6533 u32 sleeps = 0;
6534 int wait = rcd != NULL;
6535 unsigned long flags;
6536
6537 while (wait) {
6538 unsigned long shadow;
6539 int cstart, previ = -1;
6540
6541 /*
6542 * when flipping from kernel to user, we can't change
6543 * the checking type if the buffer is allocated to the
6544 * driver. It's OK the other direction, because it's
6545 * from close, and we have just disarm'ed all the
6546 * buffers. All the kernel to kernel changes are also
6547 * OK.
6548 */
6549 for (cstart = start; cstart <= last; cstart++) {
6550 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6551 / BITS_PER_LONG;
6552 if (i != previ) {
6553 shadow = (unsigned long)
6554 le64_to_cpu(dd->pioavailregs_dma[i]);
6555 previ = i;
6556 }
6557 if (test_bit(((2 * cstart) +
6558 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6559 % BITS_PER_LONG, &shadow))
6560 break;
6561 }
6562
6563 if (cstart > last)
6564 break;
6565
6566 if (sleeps == QTXSLEEPS)
6567 break;
6568 /* make sure we see an updated copy next time around */
6569 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6570 sleeps++;
6571 msleep(20);
6572 }
6573
6574 switch (which) {
6575 case TXCHK_CHG_TYPE_DIS1:
6576 /*
6577 * disable checking on a range; used by diags; just
6578 * one buffer, but still written generically
6579 */
6580 for (i = start; i <= last; i++)
6581 clear_bit(i, dd->cspec->sendchkenable);
6582 break;
6583
6584 case TXCHK_CHG_TYPE_ENAB1:
6585 /*
6586 * (re)enable checking on a range; used by diags; just
6587 * one buffer, but still written generically; read
6588 * scratch to be sure buffer actually triggered, not
6589 * just flushed from processor.
6590 */
6591 qib_read_kreg32(dd, kr_scratch);
6592 for (i = start; i <= last; i++)
6593 set_bit(i, dd->cspec->sendchkenable);
6594 break;
6595
6596 case TXCHK_CHG_TYPE_KERN:
6597 /* usable by kernel */
6598 for (i = start; i <= last; i++) {
6599 set_bit(i, dd->cspec->sendibchk);
6600 clear_bit(i, dd->cspec->sendgrhchk);
6601 }
6602 spin_lock_irqsave(&dd->uctxt_lock, flags);
6603 /* see if we need to raise avail update threshold */
6604 for (i = dd->first_user_ctxt;
6605 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6606 && i < dd->cfgctxts; i++)
6607 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6608 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6609 < dd->cspec->updthresh_dflt)
6610 break;
6611 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6612 if (i == dd->cfgctxts) {
6613 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6614 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6615 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6616 dd->sendctrl |= (dd->cspec->updthresh &
6617 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6618 SYM_LSB(SendCtrl, AvailUpdThld);
6619 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6620 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6621 }
6622 break;
6623
6624 case TXCHK_CHG_TYPE_USER:
6625 /* for user process */
6626 for (i = start; i <= last; i++) {
6627 clear_bit(i, dd->cspec->sendibchk);
6628 set_bit(i, dd->cspec->sendgrhchk);
6629 }
6630 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6631 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6632 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6633 dd->cspec->updthresh = (rcd->piocnt /
6634 rcd->subctxt_cnt) - 1;
6635 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6636 dd->sendctrl |= (dd->cspec->updthresh &
6637 SYM_RMASK(SendCtrl, AvailUpdThld))
6638 << SYM_LSB(SendCtrl, AvailUpdThld);
6639 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6640 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6641 } else
6642 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6643 break;
6644
6645 default:
6646 break;
6647 }
6648
6649 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6650 qib_write_kreg(dd, kr_sendcheckmask + i,
6651 dd->cspec->sendchkenable[i]);
6652
6653 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6654 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6655 dd->cspec->sendgrhchk[i]);
6656 qib_write_kreg(dd, kr_sendibpktmask + i,
6657 dd->cspec->sendibchk[i]);
6658 }
6659
6660 /*
6661 * Be sure whatever we did was seen by the chip and acted upon,
6662 * before we return. Mostly important for which >= 2.
6663 */
6664 qib_read_kreg32(dd, kr_scratch);
6665 }
6666
6667
6668 /* useful for trigger analyzers, etc. */
6669 static void writescratch(struct qib_devdata *dd, u32 val)
6670 {
6671 qib_write_kreg(dd, kr_scratch, val);
6672 }
6673
6674 /* Dummy for now, use chip regs soon */
6675 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6676 {
6677 return -ENXIO;
6678 }
6679
6680 /**
6681 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6682 * @dev: the pci_dev for qlogic_ib device
6683 * @ent: pci_device_id struct for this dev
6684 *
6685 * Also allocates, inits, and returns the devdata struct for this
6686 * device instance
6687 *
6688 * This is global, and is called directly at init to set up the
6689 * chip-specific function pointers for later use.
6690 */
6691 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6692 const struct pci_device_id *ent)
6693 {
6694 struct qib_devdata *dd;
6695 int ret, i;
6696 u32 tabsize, actual_cnt = 0;
6697
6698 dd = qib_alloc_devdata(pdev,
6699 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6700 sizeof(struct qib_chip_specific) +
6701 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6702 if (IS_ERR(dd))
6703 goto bail;
6704
6705 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6706 dd->f_cleanup = qib_setup_7322_cleanup;
6707 dd->f_clear_tids = qib_7322_clear_tids;
6708 dd->f_free_irq = qib_7322_free_irq;
6709 dd->f_get_base_info = qib_7322_get_base_info;
6710 dd->f_get_msgheader = qib_7322_get_msgheader;
6711 dd->f_getsendbuf = qib_7322_getsendbuf;
6712 dd->f_gpio_mod = gpio_7322_mod;
6713 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6714 dd->f_hdrqempty = qib_7322_hdrqempty;
6715 dd->f_ib_updown = qib_7322_ib_updown;
6716 dd->f_init_ctxt = qib_7322_init_ctxt;
6717 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6718 dd->f_intr_fallback = qib_7322_intr_fallback;
6719 dd->f_late_initreg = qib_late_7322_initreg;
6720 dd->f_setpbc_control = qib_7322_setpbc_control;
6721 dd->f_portcntr = qib_portcntr_7322;
6722 dd->f_put_tid = qib_7322_put_tid;
6723 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6724 dd->f_rcvctrl = rcvctrl_7322_mod;
6725 dd->f_read_cntrs = qib_read_7322cntrs;
6726 dd->f_read_portcntrs = qib_read_7322portcntrs;
6727 dd->f_reset = qib_do_7322_reset;
6728 dd->f_init_sdma_regs = init_sdma_7322_regs;
6729 dd->f_sdma_busy = qib_sdma_7322_busy;
6730 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6731 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6732 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6733 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6734 dd->f_sendctrl = sendctrl_7322_mod;
6735 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6736 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6737 dd->f_iblink_state = qib_7322_iblink_state;
6738 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6739 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6740 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6741 dd->f_set_ib_loopback = qib_7322_set_loopback;
6742 dd->f_get_ib_table = qib_7322_get_ib_table;
6743 dd->f_set_ib_table = qib_7322_set_ib_table;
6744 dd->f_set_intr_state = qib_7322_set_intr_state;
6745 dd->f_setextled = qib_setup_7322_setextled;
6746 dd->f_txchk_change = qib_7322_txchk_change;
6747 dd->f_update_usrhead = qib_update_7322_usrhead;
6748 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6749 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6750 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6751 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6752 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6753 dd->f_writescratch = writescratch;
6754 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6755 /*
6756 * Do remaining PCIe setup and save PCIe values in dd.
6757 * Any error printing is already done by the init code.
6758 * On return, we have the chip mapped, but chip registers
6759 * are not set up until start of qib_init_7322_variables.
6760 */
6761 ret = qib_pcie_ddinit(dd, pdev, ent);
6762 if (ret < 0)
6763 goto bail_free;
6764
6765 /* initialize chip-specific variables */
6766 ret = qib_init_7322_variables(dd);
6767 if (ret)
6768 goto bail_cleanup;
6769
6770 if (qib_mini_init || !dd->num_pports)
6771 goto bail;
6772
6773 /*
6774 * Determine number of vectors we want; depends on port count
6775 * and number of configured kernel receive queues actually used.
6776 * Should also depend on whether sdma is enabled or not, but
6777 * that's such a rare testing case it's not worth worrying about.
6778 */
6779 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6780 for (i = 0; i < tabsize; i++)
6781 if ((i < ARRAY_SIZE(irq_table) &&
6782 irq_table[i].port <= dd->num_pports) ||
6783 (i >= ARRAY_SIZE(irq_table) &&
6784 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6785 actual_cnt++;
6786 tabsize = actual_cnt;
6787 dd->cspec->msix_entries = kmalloc(tabsize *
6788 sizeof(struct msix_entry), GFP_KERNEL);
6789 dd->cspec->msix_arg = kmalloc(tabsize *
6790 sizeof(void *), GFP_KERNEL);
6791 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6792 qib_dev_err(dd, "No memory for MSIx table\n");
6793 tabsize = 0;
6794 }
6795 for (i = 0; i < tabsize; i++)
6796 dd->cspec->msix_entries[i].entry = i;
6797
6798 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6799 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6800 "continuing anyway\n");
6801 /* may be less than we wanted, if not enough available */
6802 dd->cspec->num_msix_entries = tabsize;
6803
6804 /* setup interrupt handler */
6805 qib_setup_7322_interrupt(dd, 1);
6806
6807 /* clear diagctrl register, in case diags were running and crashed */
6808 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6809
6810 goto bail;
6811
6812 bail_cleanup:
6813 qib_pcie_ddcleanup(dd);
6814 bail_free:
6815 qib_free_devdata(dd);
6816 dd = ERR_PTR(ret);
6817 bail:
6818 return dd;
6819 }
6820
6821 /*
6822 * Set the table entry at the specified index from the table specifed.
6823 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6824 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6825 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6826 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6827 */
6828 #define DDS_ENT_AMP_LSB 14
6829 #define DDS_ENT_MAIN_LSB 9
6830 #define DDS_ENT_POST_LSB 5
6831 #define DDS_ENT_PRE_XTRA_LSB 3
6832 #define DDS_ENT_PRE_LSB 0
6833
6834 /*
6835 * Set one entry in the TxDDS table for spec'd port
6836 * ridx picks one of the entries, while tp points
6837 * to the appropriate table entry.
6838 */
6839 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6840 const struct txdds_ent *tp)
6841 {
6842 struct qib_devdata *dd = ppd->dd;
6843 u32 pack_ent;
6844 int regidx;
6845
6846 /* Get correct offset in chip-space, and in source table */
6847 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6848 /*
6849 * We do not use qib_write_kreg_port() because it was intended
6850 * only for registers in the lower "port specific" pages.
6851 * So do index calculation by hand.
6852 */
6853 if (ppd->hw_pidx)
6854 regidx += (dd->palign / sizeof(u64));
6855
6856 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6857 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6858 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6859 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6860 qib_write_kreg(dd, regidx, pack_ent);
6861 /* Prevent back-to-back writes by hitting scratch */
6862 qib_write_kreg(ppd->dd, kr_scratch, 0);
6863 }
6864
6865 static const struct vendor_txdds_ent vendor_txdds[] = {
6866 { /* Amphenol 1m 30awg NoEq */
6867 { 0x41, 0x50, 0x48 }, "584470002 ",
6868 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6869 },
6870 { /* Amphenol 3m 28awg NoEq */
6871 { 0x41, 0x50, 0x48 }, "584470004 ",
6872 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6873 },
6874 { /* Finisar 3m OM2 Optical */
6875 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6876 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6877 },
6878 { /* Finisar 30m OM2 Optical */
6879 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6880 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6881 },
6882 { /* Finisar Default OM2 Optical */
6883 { 0x00, 0x90, 0x65 }, NULL,
6884 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6885 },
6886 { /* Gore 1m 30awg NoEq */
6887 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6888 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6889 },
6890 { /* Gore 2m 30awg NoEq */
6891 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6892 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6893 },
6894 { /* Gore 1m 28awg NoEq */
6895 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6896 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6897 },
6898 { /* Gore 3m 28awg NoEq */
6899 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6900 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6901 },
6902 { /* Gore 5m 24awg Eq */
6903 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6904 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6905 },
6906 { /* Gore 7m 24awg Eq */
6907 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6908 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6909 },
6910 { /* Gore 5m 26awg Eq */
6911 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6912 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6913 },
6914 { /* Gore 7m 26awg Eq */
6915 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6916 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6917 },
6918 { /* Intersil 12m 24awg Active */
6919 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6920 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6921 },
6922 { /* Intersil 10m 28awg Active */
6923 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6924 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6925 },
6926 { /* Intersil 7m 30awg Active */
6927 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6928 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6929 },
6930 { /* Intersil 5m 32awg Active */
6931 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6932 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6933 },
6934 { /* Intersil Default Active */
6935 { 0x00, 0x30, 0xB4 }, NULL,
6936 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6937 },
6938 { /* Luxtera 20m Active Optical */
6939 { 0x00, 0x25, 0x63 }, NULL,
6940 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6941 },
6942 { /* Molex 1M Cu loopback */
6943 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6944 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6945 },
6946 { /* Molex 2m 28awg NoEq */
6947 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6948 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6949 },
6950 };
6951
6952 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6953 /* amp, pre, main, post */
6954 { 2, 2, 15, 6 }, /* Loopback */
6955 { 0, 0, 0, 1 }, /* 2 dB */
6956 { 0, 0, 0, 2 }, /* 3 dB */
6957 { 0, 0, 0, 3 }, /* 4 dB */
6958 { 0, 0, 0, 4 }, /* 5 dB */
6959 { 0, 0, 0, 5 }, /* 6 dB */
6960 { 0, 0, 0, 6 }, /* 7 dB */
6961 { 0, 0, 0, 7 }, /* 8 dB */
6962 { 0, 0, 0, 8 }, /* 9 dB */
6963 { 0, 0, 0, 9 }, /* 10 dB */
6964 { 0, 0, 0, 10 }, /* 11 dB */
6965 { 0, 0, 0, 11 }, /* 12 dB */
6966 { 0, 0, 0, 12 }, /* 13 dB */
6967 { 0, 0, 0, 13 }, /* 14 dB */
6968 { 0, 0, 0, 14 }, /* 15 dB */
6969 { 0, 0, 0, 15 }, /* 16 dB */
6970 };
6971
6972 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
6973 /* amp, pre, main, post */
6974 { 2, 2, 15, 6 }, /* Loopback */
6975 { 0, 0, 0, 8 }, /* 2 dB */
6976 { 0, 0, 0, 8 }, /* 3 dB */
6977 { 0, 0, 0, 9 }, /* 4 dB */
6978 { 0, 0, 0, 9 }, /* 5 dB */
6979 { 0, 0, 0, 10 }, /* 6 dB */
6980 { 0, 0, 0, 10 }, /* 7 dB */
6981 { 0, 0, 0, 11 }, /* 8 dB */
6982 { 0, 0, 0, 11 }, /* 9 dB */
6983 { 0, 0, 0, 12 }, /* 10 dB */
6984 { 0, 0, 0, 12 }, /* 11 dB */
6985 { 0, 0, 0, 13 }, /* 12 dB */
6986 { 0, 0, 0, 13 }, /* 13 dB */
6987 { 0, 0, 0, 14 }, /* 14 dB */
6988 { 0, 0, 0, 14 }, /* 15 dB */
6989 { 0, 0, 0, 15 }, /* 16 dB */
6990 };
6991
6992 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
6993 /* amp, pre, main, post */
6994 { 2, 2, 15, 6 }, /* Loopback */
6995 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
6996 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
6997 { 0, 1, 0, 11 }, /* 4 dB */
6998 { 0, 1, 0, 13 }, /* 5 dB */
6999 { 0, 1, 0, 15 }, /* 6 dB */
7000 { 0, 1, 3, 15 }, /* 7 dB */
7001 { 0, 1, 7, 15 }, /* 8 dB */
7002 { 0, 1, 7, 15 }, /* 9 dB */
7003 { 0, 1, 8, 15 }, /* 10 dB */
7004 { 0, 1, 9, 15 }, /* 11 dB */
7005 { 0, 1, 10, 15 }, /* 12 dB */
7006 { 0, 2, 6, 15 }, /* 13 dB */
7007 { 0, 2, 7, 15 }, /* 14 dB */
7008 { 0, 2, 8, 15 }, /* 15 dB */
7009 { 0, 2, 9, 15 }, /* 16 dB */
7010 };
7011
7012 /*
7013 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7014 * These are mostly used for mez cards going through connectors
7015 * and backplane traces, but can be used to add other "unusual"
7016 * table values as well.
7017 */
7018 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7019 /* amp, pre, main, post */
7020 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7021 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7022 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7023 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7024 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7025 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7026 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7027 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7028 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7029 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7030 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7031 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7032 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7033 };
7034
7035 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7036 /* amp, pre, main, post */
7037 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7038 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7039 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7040 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7041 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7042 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7043 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7044 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7045 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7046 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7047 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7048 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7049 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7050 };
7051
7052 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7053 /* amp, pre, main, post */
7054 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7055 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7056 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7057 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7058 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7059 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7060 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7061 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7062 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7063 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7064 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7065 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7066 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7067 };
7068
7069 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7070 /* amp, pre, main, post */
7071 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7072 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7073 };
7074
7075 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7076 unsigned atten)
7077 {
7078 /*
7079 * The attenuation table starts at 2dB for entry 1,
7080 * with entry 0 being the loopback entry.
7081 */
7082 if (atten <= 2)
7083 atten = 1;
7084 else if (atten > TXDDS_TABLE_SZ)
7085 atten = TXDDS_TABLE_SZ - 1;
7086 else
7087 atten--;
7088 return txdds + atten;
7089 }
7090
7091 /*
7092 * if override is set, the module parameter txselect has a value
7093 * for this specific port, so use it, rather than our normal mechanism.
7094 */
7095 static void find_best_ent(struct qib_pportdata *ppd,
7096 const struct txdds_ent **sdr_dds,
7097 const struct txdds_ent **ddr_dds,
7098 const struct txdds_ent **qdr_dds, int override)
7099 {
7100 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7101 int idx;
7102
7103 /* Search table of known cables */
7104 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7105 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7106
7107 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7108 (!v->partnum ||
7109 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7110 *sdr_dds = &v->sdr;
7111 *ddr_dds = &v->ddr;
7112 *qdr_dds = &v->qdr;
7113 return;
7114 }
7115 }
7116
7117 /* Lookup serdes setting by cable type and attenuation */
7118 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7119 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7120 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7121 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7122 return;
7123 }
7124
7125 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7126 qd->atten[1])) {
7127 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7128 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7129 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7130 return;
7131 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7132 /*
7133 * If we have no (or incomplete) data from the cable
7134 * EEPROM, or no QSFP, or override is set, use the
7135 * module parameter value to index into the attentuation
7136 * table.
7137 */
7138 idx = ppd->cpspec->no_eep;
7139 *sdr_dds = &txdds_sdr[idx];
7140 *ddr_dds = &txdds_ddr[idx];
7141 *qdr_dds = &txdds_qdr[idx];
7142 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7143 /* similar to above, but index into the "extra" table. */
7144 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7145 *sdr_dds = &txdds_extra_sdr[idx];
7146 *ddr_dds = &txdds_extra_ddr[idx];
7147 *qdr_dds = &txdds_extra_qdr[idx];
7148 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7149 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7150 TXDDS_MFG_SZ)) {
7151 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7152 printk(KERN_INFO QIB_DRV_NAME
7153 " IB%u:%u use idx %u into txdds_mfg\n",
7154 ppd->dd->unit, ppd->port, idx);
7155 *sdr_dds = &txdds_extra_mfg[idx];
7156 *ddr_dds = &txdds_extra_mfg[idx];
7157 *qdr_dds = &txdds_extra_mfg[idx];
7158 } else {
7159 /* this shouldn't happen, it's range checked */
7160 *sdr_dds = txdds_sdr + qib_long_atten;
7161 *ddr_dds = txdds_ddr + qib_long_atten;
7162 *qdr_dds = txdds_qdr + qib_long_atten;
7163 }
7164 }
7165
7166 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7167 {
7168 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7169 struct txdds_ent *dds;
7170 int idx;
7171 int single_ent = 0;
7172
7173 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7174
7175 /* for mez cards or override, use the selected value for all entries */
7176 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7177 single_ent = 1;
7178
7179 /* Fill in the first entry with the best entry found. */
7180 set_txdds(ppd, 0, sdr_dds);
7181 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7182 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7183 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7184 QIBL_LINKACTIVE)) {
7185 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7186 QIB_IB_QDR ? qdr_dds :
7187 (ppd->link_speed_active ==
7188 QIB_IB_DDR ? ddr_dds : sdr_dds));
7189 write_tx_serdes_param(ppd, dds);
7190 }
7191
7192 /* Fill in the remaining entries with the default table values. */
7193 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7194 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7195 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7196 single_ent ? ddr_dds : txdds_ddr + idx);
7197 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7198 single_ent ? qdr_dds : txdds_qdr + idx);
7199 }
7200 }
7201
7202 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7203 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7204 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7205 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7206 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7207 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7208 #define AHB_TRANS_TRIES 10
7209
7210 /*
7211 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7212 * 5=subsystem which is why most calls have "chan + chan >> 1"
7213 * for the channel argument.
7214 */
7215 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7216 u32 data, u32 mask)
7217 {
7218 u32 rd_data, wr_data, sz_mask;
7219 u64 trans, acc, prev_acc;
7220 u32 ret = 0xBAD0BAD;
7221 int tries;
7222
7223 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7224 /* From this point on, make sure we return access */
7225 acc = (quad << 1) | 1;
7226 qib_write_kreg(dd, KR_AHB_ACC, acc);
7227
7228 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7229 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7230 if (trans & AHB_TRANS_RDY)
7231 break;
7232 }
7233 if (tries >= AHB_TRANS_TRIES) {
7234 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7235 goto bail;
7236 }
7237
7238 /* If mask is not all 1s, we need to read, but different SerDes
7239 * entities have different sizes
7240 */
7241 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7242 wr_data = data & mask & sz_mask;
7243 if ((~mask & sz_mask) != 0) {
7244 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7245 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7246
7247 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7248 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7249 if (trans & AHB_TRANS_RDY)
7250 break;
7251 }
7252 if (tries >= AHB_TRANS_TRIES) {
7253 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7254 AHB_TRANS_TRIES);
7255 goto bail;
7256 }
7257 /* Re-read in case host split reads and read data first */
7258 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7259 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7260 wr_data |= (rd_data & ~mask & sz_mask);
7261 }
7262
7263 /* If mask is not zero, we need to write. */
7264 if (mask & sz_mask) {
7265 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7266 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7267 trans |= AHB_WR;
7268 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7269
7270 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7271 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7272 if (trans & AHB_TRANS_RDY)
7273 break;
7274 }
7275 if (tries >= AHB_TRANS_TRIES) {
7276 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7277 AHB_TRANS_TRIES);
7278 goto bail;
7279 }
7280 }
7281 ret = wr_data;
7282 bail:
7283 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7284 return ret;
7285 }
7286
7287 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7288 unsigned mask)
7289 {
7290 struct qib_devdata *dd = ppd->dd;
7291 int chan;
7292 u32 rbc;
7293
7294 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7295 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7296 data, mask);
7297 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7298 addr, 0, 0);
7299 }
7300 }
7301
7302 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7303 {
7304 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7305 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS %s\n",
7306 ppd->dd->unit, ppd->port, (enable ? "on" : "off"));
7307 if (enable)
7308 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7309 else
7310 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7311 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7312 }
7313
7314 static int serdes_7322_init(struct qib_pportdata *ppd)
7315 {
7316 int ret = 0;
7317 if (ppd->dd->cspec->r1)
7318 ret = serdes_7322_init_old(ppd);
7319 else
7320 ret = serdes_7322_init_new(ppd);
7321 return ret;
7322 }
7323
7324 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7325 {
7326 u32 le_val;
7327
7328 /*
7329 * Initialize the Tx DDS tables. Also done every QSFP event,
7330 * for adapters with QSFP
7331 */
7332 init_txdds_table(ppd, 0);
7333
7334 /* ensure no tx overrides from earlier driver loads */
7335 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7336 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7337 reset_tx_deemphasis_override));
7338
7339 /* Patch some SerDes defaults to "Better for IB" */
7340 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7341 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7342
7343 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7344 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7345 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7346 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7347
7348 /* May be overridden in qsfp_7322_event */
7349 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7350 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7351
7352 /* enable LE1 adaptation for all but QME, which is disabled */
7353 le_val = IS_QME(ppd->dd) ? 0 : 1;
7354 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7355
7356 /* Clear cmode-override, may be set from older driver */
7357 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7358
7359 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7360 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7361
7362 /* setup LoS params; these are subsystem, so chan == 5 */
7363 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7364 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7365 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7366 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7367 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7368
7369 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7370 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7371 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7372 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7373 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7374
7375 /* LoS filter select enabled */
7376 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7377
7378 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7379 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7380 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7381 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7382
7383 serdes_7322_los_enable(ppd, 1);
7384
7385 /* rxbistena; set 0 to avoid effects of it switch later */
7386 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7387
7388 /* Configure 4 DFE taps, and only they adapt */
7389 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7390
7391 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7392 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7393 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7394
7395 /*
7396 * Set receive adaptation mode. SDR and DDR adaptation are
7397 * always on, and QDR is initially enabled; later disabled.
7398 */
7399 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7400 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7401 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7402 ppd->dd->cspec->r1 ?
7403 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7404 ppd->cpspec->qdr_dfe_on = 1;
7405
7406 /* FLoop LOS gate: PPM filter enabled */
7407 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7408
7409 /* rx offset center enabled */
7410 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7411
7412 if (!ppd->dd->cspec->r1) {
7413 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7414 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7415 }
7416
7417 /* Set the frequency loop bandwidth to 15 */
7418 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7419
7420 return 0;
7421 }
7422
7423 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7424 {
7425 u64 tstart;
7426 u32 le_val, rxcaldone;
7427 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7428
7429 /*
7430 * Initialize the Tx DDS tables. Also done every QSFP event,
7431 * for adapters with QSFP
7432 */
7433 init_txdds_table(ppd, 0);
7434
7435 /* Clear cmode-override, may be set from older driver */
7436 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7437
7438 /* ensure no tx overrides from earlier driver loads */
7439 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7440 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7441 reset_tx_deemphasis_override));
7442
7443 /* START OF LSI SUGGESTED SERDES BRINGUP */
7444 /* Reset - Calibration Setup */
7445 /* Stop DFE adaptaion */
7446 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7447 /* Disable LE1 */
7448 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7449 /* Disable autoadapt for LE1 */
7450 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7451 /* Disable LE2 */
7452 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7453 /* Disable VGA */
7454 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7455 /* Disable AFE Offset Cancel */
7456 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7457 /* Disable Timing Loop */
7458 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7459 /* Disable Frequency Loop */
7460 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7461 /* Disable Baseline Wander Correction */
7462 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7463 /* Disable RX Calibration */
7464 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7465 /* Disable RX Offset Calibration */
7466 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7467 /* Select BB CDR */
7468 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7469 /* CDR Step Size */
7470 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7471 /* Enable phase Calibration */
7472 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7473 /* DFE Bandwidth [2:14-12] */
7474 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7475 /* DFE Config (4 taps only) */
7476 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7477 /* Gain Loop Bandwidth */
7478 if (!ppd->dd->cspec->r1) {
7479 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7480 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7481 } else {
7482 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7483 }
7484 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7485 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7486 /* Data Rate Select [5:7-6] (leave as default) */
7487 /* RX Parralel Word Width [3:10-8] (leave as default) */
7488
7489 /* RX REST */
7490 /* Single- or Multi-channel reset */
7491 /* RX Analog reset */
7492 /* RX Digital reset */
7493 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7494 msleep(20);
7495 /* RX Analog reset */
7496 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7497 msleep(20);
7498 /* RX Digital reset */
7499 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7500 msleep(20);
7501
7502 /* setup LoS params; these are subsystem, so chan == 5 */
7503 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7504 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7505 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7506 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7507 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7508
7509 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7510 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7511 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7512 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7513 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7514
7515 /* LoS filter select enabled */
7516 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7517
7518 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7519 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7520 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7521 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7522
7523 /* Turn on LOS on initial SERDES init */
7524 serdes_7322_los_enable(ppd, 1);
7525 /* FLoop LOS gate: PPM filter enabled */
7526 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7527
7528 /* RX LATCH CALIBRATION */
7529 /* Enable Eyefinder Phase Calibration latch */
7530 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7531 /* Enable RX Offset Calibration latch */
7532 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7533 msleep(20);
7534 /* Start Calibration */
7535 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7536 tstart = get_jiffies_64();
7537 while (chan_done &&
7538 !time_after64(tstart, tstart + msecs_to_jiffies(500))) {
7539 msleep(20);
7540 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7541 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7542 (chan + (chan >> 1)),
7543 25, 0, 0);
7544 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7545 (~chan_done & (1 << chan)) == 0)
7546 chan_done &= ~(1 << chan);
7547 }
7548 }
7549 if (chan_done) {
7550 printk(KERN_INFO QIB_DRV_NAME
7551 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7552 IBSD(ppd->hw_pidx), chan_done);
7553 } else {
7554 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7555 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7556 (chan + (chan >> 1)),
7557 25, 0, 0);
7558 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7559 printk(KERN_INFO QIB_DRV_NAME
7560 " Serdes %d chan %d calibration "
7561 "failed\n", IBSD(ppd->hw_pidx), chan);
7562 }
7563 }
7564
7565 /* Turn off Calibration */
7566 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7567 msleep(20);
7568
7569 /* BRING RX UP */
7570 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7571 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7572 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7573 /* Set LE2 Loop bandwidth */
7574 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7575 /* Enable LE2 */
7576 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7577 msleep(20);
7578 /* Enable H0 only */
7579 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7580 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7581 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7582 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7583 /* Enable VGA */
7584 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7585 msleep(20);
7586 /* Set Frequency Loop Bandwidth */
7587 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7588 /* Enable Frequency Loop */
7589 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7590 /* Set Timing Loop Bandwidth */
7591 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7592 /* Enable Timing Loop */
7593 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7594 msleep(50);
7595 /* Enable DFE
7596 * Set receive adaptation mode. SDR and DDR adaptation are
7597 * always on, and QDR is initially enabled; later disabled.
7598 */
7599 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7600 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7601 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7602 ppd->dd->cspec->r1 ?
7603 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7604 ppd->cpspec->qdr_dfe_on = 1;
7605 /* Disable LE1 */
7606 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7607 /* Disable auto adapt for LE1 */
7608 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7609 msleep(20);
7610 /* Enable AFE Offset Cancel */
7611 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7612 /* Enable Baseline Wander Correction */
7613 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7614 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7615 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7616 /* VGA output common mode */
7617 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7618
7619 return 0;
7620 }
7621
7622 /* start adjust QMH serdes parameters */
7623
7624 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7625 {
7626 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7627 9, code << 9, 0x3f << 9);
7628 }
7629
7630 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7631 int enable, u32 tapenable)
7632 {
7633 if (enable)
7634 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7635 1, 3 << 10, 0x1f << 10);
7636 else
7637 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7638 1, 0, 0x1f << 10);
7639 }
7640
7641 /* Set clock to 1, 0, 1, 0 */
7642 static void clock_man(struct qib_pportdata *ppd, int chan)
7643 {
7644 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7645 4, 0x4000, 0x4000);
7646 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7647 4, 0, 0x4000);
7648 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7649 4, 0x4000, 0x4000);
7650 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7651 4, 0, 0x4000);
7652 }
7653
7654 /*
7655 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7656 * The caller must pass the settings appropriate for the current speed,
7657 * or not care if they are correct for the current speed.
7658 */
7659 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7660 struct txdds_ent *txdds)
7661 {
7662 u64 deemph;
7663
7664 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7665 /* field names for amp, main, post, pre, respectively */
7666 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7667 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7668 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7669 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7670
7671 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7672 tx_override_deemphasis_select);
7673 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7674 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7675 txampcntl_d2a);
7676 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7677 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7678 txc0_ena);
7679 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7680 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7681 txcp1_ena);
7682 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7683 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7684 txcn1_ena);
7685 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7686 }
7687
7688 /*
7689 * Set the parameters for mez cards on link bounce, so they are
7690 * always exactly what was requested. Similar logic to init_txdds
7691 * but does just the serdes.
7692 */
7693 static void adj_tx_serdes(struct qib_pportdata *ppd)
7694 {
7695 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7696 struct txdds_ent *dds;
7697
7698 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7699 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7700 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7701 ddr_dds : sdr_dds));
7702 write_tx_serdes_param(ppd, dds);
7703 }
7704
7705 /* set QDR forced value for H1, if needed */
7706 static void force_h1(struct qib_pportdata *ppd)
7707 {
7708 int chan;
7709
7710 ppd->cpspec->qdr_reforce = 0;
7711 if (!ppd->dd->cspec->r1)
7712 return;
7713
7714 for (chan = 0; chan < SERDES_CHANS; chan++) {
7715 set_man_mode_h1(ppd, chan, 1, 0);
7716 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7717 clock_man(ppd, chan);
7718 set_man_mode_h1(ppd, chan, 0, 0);
7719 }
7720 }
7721
7722 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7723 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7724
7725 #define R_OPCODE_LSB 3
7726 #define R_OP_NOP 0
7727 #define R_OP_SHIFT 2
7728 #define R_OP_UPDATE 3
7729 #define R_TDI_LSB 2
7730 #define R_TDO_LSB 1
7731 #define R_RDY 1
7732
7733 static int qib_r_grab(struct qib_devdata *dd)
7734 {
7735 u64 val;
7736 val = SJA_EN;
7737 qib_write_kreg(dd, kr_r_access, val);
7738 qib_read_kreg32(dd, kr_scratch);
7739 return 0;
7740 }
7741
7742 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7743 * returns the current state of R_TDO
7744 */
7745 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7746 {
7747 u64 val;
7748 int timeout;
7749 for (timeout = 0; timeout < 100 ; ++timeout) {
7750 val = qib_read_kreg32(dd, kr_r_access);
7751 if (val & R_RDY)
7752 return (val >> R_TDO_LSB) & 1;
7753 }
7754 return -1;
7755 }
7756
7757 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7758 int len, u8 *inp, u8 *outp)
7759 {
7760 u64 valbase, val;
7761 int ret, pos;
7762
7763 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7764 (R_OP_SHIFT << R_OPCODE_LSB);
7765 ret = qib_r_wait_for_rdy(dd);
7766 if (ret < 0)
7767 goto bail;
7768 for (pos = 0; pos < len; ++pos) {
7769 val = valbase;
7770 if (outp) {
7771 outp[pos >> 3] &= ~(1 << (pos & 7));
7772 outp[pos >> 3] |= (ret << (pos & 7));
7773 }
7774 if (inp) {
7775 int tdi = inp[pos >> 3] >> (pos & 7);
7776 val |= ((tdi & 1) << R_TDI_LSB);
7777 }
7778 qib_write_kreg(dd, kr_r_access, val);
7779 qib_read_kreg32(dd, kr_scratch);
7780 ret = qib_r_wait_for_rdy(dd);
7781 if (ret < 0)
7782 break;
7783 }
7784 /* Restore to NOP between operations. */
7785 val = SJA_EN | (bisten << BISTEN_LSB);
7786 qib_write_kreg(dd, kr_r_access, val);
7787 qib_read_kreg32(dd, kr_scratch);
7788 ret = qib_r_wait_for_rdy(dd);
7789
7790 if (ret >= 0)
7791 ret = pos;
7792 bail:
7793 return ret;
7794 }
7795
7796 static int qib_r_update(struct qib_devdata *dd, int bisten)
7797 {
7798 u64 val;
7799 int ret;
7800
7801 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7802 ret = qib_r_wait_for_rdy(dd);
7803 if (ret >= 0) {
7804 qib_write_kreg(dd, kr_r_access, val);
7805 qib_read_kreg32(dd, kr_scratch);
7806 }
7807 return ret;
7808 }
7809
7810 #define BISTEN_PORT_SEL 15
7811 #define LEN_PORT_SEL 625
7812 #define BISTEN_AT 17
7813 #define LEN_AT 156
7814 #define BISTEN_ETM 16
7815 #define LEN_ETM 632
7816
7817 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7818
7819 /* these are common for all IB port use cases. */
7820 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7821 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7822 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7823 };
7824 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7825 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7826 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7827 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7828 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7829 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7830 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7831 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7832 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7833 };
7834 static u8 at[BIT2BYTE(LEN_AT)] = {
7835 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7836 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7837 };
7838
7839 /* used for IB1 or IB2, only one in use */
7840 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7841 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7842 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7843 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7844 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7846 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7847 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7848 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7849 };
7850
7851 /* used when both IB1 and IB2 are in use */
7852 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7853 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7854 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7855 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7856 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7857 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7858 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7859 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7860 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7861 };
7862
7863 /* used when only IB1 is in use */
7864 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7865 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7866 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7867 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7868 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7869 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7870 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7871 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7872 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7873 };
7874
7875 /* used when only IB2 is in use */
7876 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7877 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7878 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7879 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7880 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7881 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7882 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7883 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7884 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7885 };
7886
7887 /* used when both IB1 and IB2 are in use */
7888 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7889 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7890 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7891 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7892 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7893 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7894 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7895 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7896 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7897 };
7898
7899 /*
7900 * Do setup to properly handle IB link recovery; if port is zero, we
7901 * are initializing to cover both ports; otherwise we are initializing
7902 * to cover a single port card, or the port has reached INIT and we may
7903 * need to switch coverage types.
7904 */
7905 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7906 {
7907 u8 *portsel, *etm;
7908 struct qib_devdata *dd = ppd->dd;
7909
7910 if (!ppd->dd->cspec->r1)
7911 return;
7912 if (!both) {
7913 dd->cspec->recovery_ports_initted++;
7914 ppd->cpspec->recovery_init = 1;
7915 }
7916 if (!both && dd->cspec->recovery_ports_initted == 1) {
7917 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7918 etm = atetm_1port;
7919 } else {
7920 portsel = portsel_2port;
7921 etm = atetm_2port;
7922 }
7923
7924 if (qib_r_grab(dd) < 0 ||
7925 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7926 qib_r_update(dd, BISTEN_ETM) < 0 ||
7927 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7928 qib_r_update(dd, BISTEN_AT) < 0 ||
7929 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7930 portsel, NULL) < 0 ||
7931 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7932 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7933 qib_r_update(dd, BISTEN_AT) < 0 ||
7934 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7935 qib_r_update(dd, BISTEN_ETM) < 0)
7936 qib_dev_err(dd, "Failed IB link recovery setup\n");
7937 }
7938
7939 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7940 {
7941 struct qib_devdata *dd = ppd->dd;
7942 u64 fmask;
7943
7944 if (dd->cspec->recovery_ports_initted != 1)
7945 return; /* rest doesn't apply to dualport */
7946 qib_write_kreg(dd, kr_control, dd->control |
7947 SYM_MASK(Control, FreezeMode));
7948 (void)qib_read_kreg64(dd, kr_scratch);
7949 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7950 fmask = qib_read_kreg64(dd, kr_act_fmask);
7951 if (!fmask) {
7952 /*
7953 * require a powercycle before we'll work again, and make
7954 * sure we get no more interrupts, and don't turn off
7955 * freeze.
7956 */
7957 ppd->dd->cspec->stay_in_freeze = 1;
7958 qib_7322_set_intr_state(ppd->dd, 0);
7959 qib_write_kreg(dd, kr_fmask, 0ULL);
7960 qib_dev_err(dd, "HCA unusable until powercycled\n");
7961 return; /* eventually reset */
7962 }
7963
7964 qib_write_kreg(ppd->dd, kr_hwerrclear,
7965 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7966
7967 /* don't do the full clear_freeze(), not needed for this */
7968 qib_write_kreg(dd, kr_control, dd->control);
7969 qib_read_kreg32(dd, kr_scratch);
7970 /* take IBC out of reset */
7971 if (ppd->link_speed_supported) {
7972 ppd->cpspec->ibcctrl_a &=
7973 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7974 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7975 ppd->cpspec->ibcctrl_a);
7976 qib_read_kreg32(dd, kr_scratch);
7977 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7978 qib_set_ib_7322_lstate(ppd, 0,
7979 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
7980 }
7981 }