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1 /*
2 * Copyright (c) 2008, 2009, 2010 QLogic Corporation. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 /*
34 * This file contains all of the code that is specific to the
35 * InfiniPath 7322 chip
36 */
37
38 #include <linux/interrupt.h>
39 #include <linux/pci.h>
40 #include <linux/delay.h>
41 #include <linux/io.h>
42 #include <linux/jiffies.h>
43 #include <rdma/ib_verbs.h>
44 #include <rdma/ib_smi.h>
45
46 #include "qib.h"
47 #include "qib_7322_regs.h"
48 #include "qib_qsfp.h"
49
50 #include "qib_mad.h"
51
52 static void qib_setup_7322_setextled(struct qib_pportdata *, u32);
53 static void qib_7322_handle_hwerrors(struct qib_devdata *, char *, size_t);
54 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op);
55 static irqreturn_t qib_7322intr(int irq, void *data);
56 static irqreturn_t qib_7322bufavail(int irq, void *data);
57 static irqreturn_t sdma_intr(int irq, void *data);
58 static irqreturn_t sdma_idle_intr(int irq, void *data);
59 static irqreturn_t sdma_progress_intr(int irq, void *data);
60 static irqreturn_t sdma_cleanup_intr(int irq, void *data);
61 static void qib_7322_txchk_change(struct qib_devdata *, u32, u32, u32,
62 struct qib_ctxtdata *rcd);
63 static u8 qib_7322_phys_portstate(u64);
64 static u32 qib_7322_iblink_state(u64);
65 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
66 u16 linitcmd);
67 static void force_h1(struct qib_pportdata *);
68 static void adj_tx_serdes(struct qib_pportdata *);
69 static u32 qib_7322_setpbc_control(struct qib_pportdata *, u32, u8, u8);
70 static void qib_7322_mini_pcs_reset(struct qib_pportdata *);
71
72 static u32 ahb_mod(struct qib_devdata *, int, int, int, u32, u32);
73 static void ibsd_wr_allchans(struct qib_pportdata *, int, unsigned, unsigned);
74 static void serdes_7322_los_enable(struct qib_pportdata *, int);
75 static int serdes_7322_init_old(struct qib_pportdata *);
76 static int serdes_7322_init_new(struct qib_pportdata *);
77
78 #define BMASK(msb, lsb) (((1 << ((msb) + 1 - (lsb))) - 1) << (lsb))
79
80 /* LE2 serdes values for different cases */
81 #define LE2_DEFAULT 5
82 #define LE2_5m 4
83 #define LE2_QME 0
84
85 /* Below is special-purpose, so only really works for the IB SerDes blocks. */
86 #define IBSD(hw_pidx) (hw_pidx + 2)
87
88 /* these are variables for documentation and experimentation purposes */
89 static const unsigned rcv_int_timeout = 375;
90 static const unsigned rcv_int_count = 16;
91 static const unsigned sdma_idle_cnt = 64;
92
93 /* Time to stop altering Rx Equalization parameters, after link up. */
94 #define RXEQ_DISABLE_MSECS 2500
95
96 /*
97 * Number of VLs we are configured to use (to allow for more
98 * credits per vl, etc.)
99 */
100 ushort qib_num_cfg_vls = 2;
101 module_param_named(num_vls, qib_num_cfg_vls, ushort, S_IRUGO);
102 MODULE_PARM_DESC(num_vls, "Set number of Virtual Lanes to use (1-8)");
103
104 static ushort qib_chase = 1;
105 module_param_named(chase, qib_chase, ushort, S_IRUGO);
106 MODULE_PARM_DESC(chase, "Enable state chase handling");
107
108 static ushort qib_long_atten = 10; /* 10 dB ~= 5m length */
109 module_param_named(long_attenuation, qib_long_atten, ushort, S_IRUGO);
110 MODULE_PARM_DESC(long_attenuation, \
111 "attenuation cutoff (dB) for long copper cable setup");
112
113 static ushort qib_singleport;
114 module_param_named(singleport, qib_singleport, ushort, S_IRUGO);
115 MODULE_PARM_DESC(singleport, "Use only IB port 1; more per-port buffer space");
116
117 /*
118 * Receive header queue sizes
119 */
120 static unsigned qib_rcvhdrcnt;
121 module_param_named(rcvhdrcnt, qib_rcvhdrcnt, uint, S_IRUGO);
122 MODULE_PARM_DESC(rcvhdrcnt, "receive header count");
123
124 static unsigned qib_rcvhdrsize;
125 module_param_named(rcvhdrsize, qib_rcvhdrsize, uint, S_IRUGO);
126 MODULE_PARM_DESC(rcvhdrsize, "receive header size in 32-bit words");
127
128 static unsigned qib_rcvhdrentsize;
129 module_param_named(rcvhdrentsize, qib_rcvhdrentsize, uint, S_IRUGO);
130 MODULE_PARM_DESC(rcvhdrentsize, "receive header entry size in 32-bit words");
131
132 #define MAX_ATTEN_LEN 64 /* plenty for any real system */
133 /* for read back, default index is ~5m copper cable */
134 static char txselect_list[MAX_ATTEN_LEN] = "10";
135 static struct kparam_string kp_txselect = {
136 .string = txselect_list,
137 .maxlen = MAX_ATTEN_LEN
138 };
139 static int setup_txselect(const char *, struct kernel_param *);
140 module_param_call(txselect, setup_txselect, param_get_string,
141 &kp_txselect, S_IWUSR | S_IRUGO);
142 MODULE_PARM_DESC(txselect, \
143 "Tx serdes indices (for no QSFP or invalid QSFP data)");
144
145 #define BOARD_QME7342 5
146 #define BOARD_QMH7342 6
147 #define IS_QMH(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
148 BOARD_QMH7342)
149 #define IS_QME(dd) (SYM_FIELD((dd)->revision, Revision, BoardID) == \
150 BOARD_QME7342)
151
152 #define KREG_IDX(regname) (QIB_7322_##regname##_OFFS / sizeof(u64))
153
154 #define KREG_IBPORT_IDX(regname) ((QIB_7322_##regname##_0_OFFS / sizeof(u64)))
155
156 #define MASK_ACROSS(lsb, msb) \
157 (((1ULL << ((msb) + 1 - (lsb))) - 1) << (lsb))
158
159 #define SYM_RMASK(regname, fldname) ((u64) \
160 QIB_7322_##regname##_##fldname##_RMASK)
161
162 #define SYM_MASK(regname, fldname) ((u64) \
163 QIB_7322_##regname##_##fldname##_RMASK << \
164 QIB_7322_##regname##_##fldname##_LSB)
165
166 #define SYM_FIELD(value, regname, fldname) ((u64) \
167 (((value) >> SYM_LSB(regname, fldname)) & \
168 SYM_RMASK(regname, fldname)))
169
170 /* useful for things like LaFifoEmpty_0...7, TxCreditOK_0...7, etc. */
171 #define SYM_FIELD_ACROSS(value, regname, fldname, nbits) \
172 (((value) >> SYM_LSB(regname, fldname)) & MASK_ACROSS(0, nbits))
173
174 #define HWE_MASK(fldname) SYM_MASK(HwErrMask, fldname##Mask)
175 #define ERR_MASK(fldname) SYM_MASK(ErrMask, fldname##Mask)
176 #define ERR_MASK_N(fldname) SYM_MASK(ErrMask_0, fldname##Mask)
177 #define INT_MASK(fldname) SYM_MASK(IntMask, fldname##IntMask)
178 #define INT_MASK_P(fldname, port) SYM_MASK(IntMask, fldname##IntMask##_##port)
179 /* Below because most, but not all, fields of IntMask have that full suffix */
180 #define INT_MASK_PM(fldname, port) SYM_MASK(IntMask, fldname##Mask##_##port)
181
182
183 #define SYM_LSB(regname, fldname) (QIB_7322_##regname##_##fldname##_LSB)
184
185 /*
186 * the size bits give us 2^N, in KB units. 0 marks as invalid,
187 * and 7 is reserved. We currently use only 2KB and 4KB
188 */
189 #define IBA7322_TID_SZ_SHIFT QIB_7322_RcvTIDArray0_RT_BufSize_LSB
190 #define IBA7322_TID_SZ_2K (1UL<<IBA7322_TID_SZ_SHIFT) /* 2KB */
191 #define IBA7322_TID_SZ_4K (2UL<<IBA7322_TID_SZ_SHIFT) /* 4KB */
192 #define IBA7322_TID_PA_SHIFT 11U /* TID addr in chip stored w/o low bits */
193
194 #define SendIBSLIDAssignMask \
195 QIB_7322_SendIBSLIDAssign_0_SendIBSLIDAssign_15_0_RMASK
196 #define SendIBSLMCMask \
197 QIB_7322_SendIBSLIDMask_0_SendIBSLIDMask_15_0_RMASK
198
199 #define ExtLED_IB1_YEL SYM_MASK(EXTCtrl, LEDPort0YellowOn)
200 #define ExtLED_IB1_GRN SYM_MASK(EXTCtrl, LEDPort0GreenOn)
201 #define ExtLED_IB2_YEL SYM_MASK(EXTCtrl, LEDPort1YellowOn)
202 #define ExtLED_IB2_GRN SYM_MASK(EXTCtrl, LEDPort1GreenOn)
203 #define ExtLED_IB1_MASK (ExtLED_IB1_YEL | ExtLED_IB1_GRN)
204 #define ExtLED_IB2_MASK (ExtLED_IB2_YEL | ExtLED_IB2_GRN)
205
206 #define _QIB_GPIO_SDA_NUM 1
207 #define _QIB_GPIO_SCL_NUM 0
208 #define QIB_EEPROM_WEN_NUM 14
209 #define QIB_TWSI_EEPROM_DEV 0xA2 /* All Production 7322 cards. */
210
211 /* HW counter clock is at 4nsec */
212 #define QIB_7322_PSXMITWAIT_CHECK_RATE 4000
213
214 /* full speed IB port 1 only */
215 #define PORT_SPD_CAP (QIB_IB_SDR | QIB_IB_DDR | QIB_IB_QDR)
216 #define PORT_SPD_CAP_SHIFT 3
217
218 /* full speed featuremask, both ports */
219 #define DUAL_PORT_CAP (PORT_SPD_CAP | (PORT_SPD_CAP << PORT_SPD_CAP_SHIFT))
220
221 /*
222 * This file contains almost all the chip-specific register information and
223 * access functions for the FAKED QLogic InfiniPath 7322 PCI-Express chip.
224 */
225
226 /* Use defines to tie machine-generated names to lower-case names */
227 #define kr_contextcnt KREG_IDX(ContextCnt)
228 #define kr_control KREG_IDX(Control)
229 #define kr_counterregbase KREG_IDX(CntrRegBase)
230 #define kr_errclear KREG_IDX(ErrClear)
231 #define kr_errmask KREG_IDX(ErrMask)
232 #define kr_errstatus KREG_IDX(ErrStatus)
233 #define kr_extctrl KREG_IDX(EXTCtrl)
234 #define kr_extstatus KREG_IDX(EXTStatus)
235 #define kr_gpio_clear KREG_IDX(GPIOClear)
236 #define kr_gpio_mask KREG_IDX(GPIOMask)
237 #define kr_gpio_out KREG_IDX(GPIOOut)
238 #define kr_gpio_status KREG_IDX(GPIOStatus)
239 #define kr_hwdiagctrl KREG_IDX(HwDiagCtrl)
240 #define kr_debugportval KREG_IDX(DebugPortValueReg)
241 #define kr_fmask KREG_IDX(feature_mask)
242 #define kr_act_fmask KREG_IDX(active_feature_mask)
243 #define kr_hwerrclear KREG_IDX(HwErrClear)
244 #define kr_hwerrmask KREG_IDX(HwErrMask)
245 #define kr_hwerrstatus KREG_IDX(HwErrStatus)
246 #define kr_intclear KREG_IDX(IntClear)
247 #define kr_intmask KREG_IDX(IntMask)
248 #define kr_intredirect KREG_IDX(IntRedirect0)
249 #define kr_intstatus KREG_IDX(IntStatus)
250 #define kr_pagealign KREG_IDX(PageAlign)
251 #define kr_rcvavailtimeout KREG_IDX(RcvAvailTimeOut0)
252 #define kr_rcvctrl KREG_IDX(RcvCtrl) /* Common, but chip also has per-port */
253 #define kr_rcvegrbase KREG_IDX(RcvEgrBase)
254 #define kr_rcvegrcnt KREG_IDX(RcvEgrCnt)
255 #define kr_rcvhdrcnt KREG_IDX(RcvHdrCnt)
256 #define kr_rcvhdrentsize KREG_IDX(RcvHdrEntSize)
257 #define kr_rcvhdrsize KREG_IDX(RcvHdrSize)
258 #define kr_rcvtidbase KREG_IDX(RcvTIDBase)
259 #define kr_rcvtidcnt KREG_IDX(RcvTIDCnt)
260 #define kr_revision KREG_IDX(Revision)
261 #define kr_scratch KREG_IDX(Scratch)
262 #define kr_sendbuffererror KREG_IDX(SendBufErr0) /* and base for 1 and 2 */
263 #define kr_sendcheckmask KREG_IDX(SendCheckMask0) /* and 1, 2 */
264 #define kr_sendctrl KREG_IDX(SendCtrl)
265 #define kr_sendgrhcheckmask KREG_IDX(SendGRHCheckMask0) /* and 1, 2 */
266 #define kr_sendibpktmask KREG_IDX(SendIBPacketMask0) /* and 1, 2 */
267 #define kr_sendpioavailaddr KREG_IDX(SendBufAvailAddr)
268 #define kr_sendpiobufbase KREG_IDX(SendBufBase)
269 #define kr_sendpiobufcnt KREG_IDX(SendBufCnt)
270 #define kr_sendpiosize KREG_IDX(SendBufSize)
271 #define kr_sendregbase KREG_IDX(SendRegBase)
272 #define kr_sendbufavail0 KREG_IDX(SendBufAvail0)
273 #define kr_userregbase KREG_IDX(UserRegBase)
274 #define kr_intgranted KREG_IDX(Int_Granted)
275 #define kr_vecclr_wo_int KREG_IDX(vec_clr_without_int)
276 #define kr_intblocked KREG_IDX(IntBlocked)
277 #define kr_r_access KREG_IDX(SPC_JTAG_ACCESS_REG)
278
279 /*
280 * per-port kernel registers. Access only with qib_read_kreg_port()
281 * or qib_write_kreg_port()
282 */
283 #define krp_errclear KREG_IBPORT_IDX(ErrClear)
284 #define krp_errmask KREG_IBPORT_IDX(ErrMask)
285 #define krp_errstatus KREG_IBPORT_IDX(ErrStatus)
286 #define krp_highprio_0 KREG_IBPORT_IDX(HighPriority0)
287 #define krp_highprio_limit KREG_IBPORT_IDX(HighPriorityLimit)
288 #define krp_hrtbt_guid KREG_IBPORT_IDX(HRTBT_GUID)
289 #define krp_ib_pcsconfig KREG_IBPORT_IDX(IBPCSConfig)
290 #define krp_ibcctrl_a KREG_IBPORT_IDX(IBCCtrlA)
291 #define krp_ibcctrl_b KREG_IBPORT_IDX(IBCCtrlB)
292 #define krp_ibcctrl_c KREG_IBPORT_IDX(IBCCtrlC)
293 #define krp_ibcstatus_a KREG_IBPORT_IDX(IBCStatusA)
294 #define krp_ibcstatus_b KREG_IBPORT_IDX(IBCStatusB)
295 #define krp_txestatus KREG_IBPORT_IDX(TXEStatus)
296 #define krp_lowprio_0 KREG_IBPORT_IDX(LowPriority0)
297 #define krp_ncmodectrl KREG_IBPORT_IDX(IBNCModeCtrl)
298 #define krp_partitionkey KREG_IBPORT_IDX(RcvPartitionKey)
299 #define krp_psinterval KREG_IBPORT_IDX(PSInterval)
300 #define krp_psstart KREG_IBPORT_IDX(PSStart)
301 #define krp_psstat KREG_IBPORT_IDX(PSStat)
302 #define krp_rcvbthqp KREG_IBPORT_IDX(RcvBTHQP)
303 #define krp_rcvctrl KREG_IBPORT_IDX(RcvCtrl)
304 #define krp_rcvpktledcnt KREG_IBPORT_IDX(RcvPktLEDCnt)
305 #define krp_rcvqpmaptable KREG_IBPORT_IDX(RcvQPMapTableA)
306 #define krp_rxcreditvl0 KREG_IBPORT_IDX(RxCreditVL0)
307 #define krp_rxcreditvl15 (KREG_IBPORT_IDX(RxCreditVL0)+15)
308 #define krp_sendcheckcontrol KREG_IBPORT_IDX(SendCheckControl)
309 #define krp_sendctrl KREG_IBPORT_IDX(SendCtrl)
310 #define krp_senddmabase KREG_IBPORT_IDX(SendDmaBase)
311 #define krp_senddmabufmask0 KREG_IBPORT_IDX(SendDmaBufMask0)
312 #define krp_senddmabufmask1 (KREG_IBPORT_IDX(SendDmaBufMask0) + 1)
313 #define krp_senddmabufmask2 (KREG_IBPORT_IDX(SendDmaBufMask0) + 2)
314 #define krp_senddmabuf_use0 KREG_IBPORT_IDX(SendDmaBufUsed0)
315 #define krp_senddmabuf_use1 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 1)
316 #define krp_senddmabuf_use2 (KREG_IBPORT_IDX(SendDmaBufUsed0) + 2)
317 #define krp_senddmadesccnt KREG_IBPORT_IDX(SendDmaDescCnt)
318 #define krp_senddmahead KREG_IBPORT_IDX(SendDmaHead)
319 #define krp_senddmaheadaddr KREG_IBPORT_IDX(SendDmaHeadAddr)
320 #define krp_senddmaidlecnt KREG_IBPORT_IDX(SendDmaIdleCnt)
321 #define krp_senddmalengen KREG_IBPORT_IDX(SendDmaLenGen)
322 #define krp_senddmaprioritythld KREG_IBPORT_IDX(SendDmaPriorityThld)
323 #define krp_senddmareloadcnt KREG_IBPORT_IDX(SendDmaReloadCnt)
324 #define krp_senddmastatus KREG_IBPORT_IDX(SendDmaStatus)
325 #define krp_senddmatail KREG_IBPORT_IDX(SendDmaTail)
326 #define krp_sendhdrsymptom KREG_IBPORT_IDX(SendHdrErrSymptom)
327 #define krp_sendslid KREG_IBPORT_IDX(SendIBSLIDAssign)
328 #define krp_sendslidmask KREG_IBPORT_IDX(SendIBSLIDMask)
329 #define krp_ibsdtestiftx KREG_IBPORT_IDX(IB_SDTEST_IF_TX)
330 #define krp_adapt_dis_timer KREG_IBPORT_IDX(ADAPT_DISABLE_TIMER_THRESHOLD)
331 #define krp_tx_deemph_override KREG_IBPORT_IDX(IBSD_TX_DEEMPHASIS_OVERRIDE)
332 #define krp_serdesctrl KREG_IBPORT_IDX(IBSerdesCtrl)
333
334 /*
335 * Per-context kernel registers. Access only with qib_read_kreg_ctxt()
336 * or qib_write_kreg_ctxt()
337 */
338 #define krc_rcvhdraddr KREG_IDX(RcvHdrAddr0)
339 #define krc_rcvhdrtailaddr KREG_IDX(RcvHdrTailAddr0)
340
341 /*
342 * TID Flow table, per context. Reduces
343 * number of hdrq updates to one per flow (or on errors).
344 * context 0 and 1 share same memory, but have distinct
345 * addresses. Since for now, we never use expected sends
346 * on kernel contexts, we don't worry about that (we initialize
347 * those entries for ctxt 0/1 on driver load twice, for example).
348 */
349 #define NUM_TIDFLOWS_CTXT 0x20 /* 0x20 per context; have to hardcode */
350 #define ur_rcvflowtable (KREG_IDX(RcvTIDFlowTable0) - KREG_IDX(RcvHdrTail0))
351
352 /* these are the error bits in the tid flows, and are W1C */
353 #define TIDFLOW_ERRBITS ( \
354 (SYM_MASK(RcvTIDFlowTable0, GenMismatch) << \
355 SYM_LSB(RcvTIDFlowTable0, GenMismatch)) | \
356 (SYM_MASK(RcvTIDFlowTable0, SeqMismatch) << \
357 SYM_LSB(RcvTIDFlowTable0, SeqMismatch)))
358
359 /* Most (not all) Counters are per-IBport.
360 * Requires LBIntCnt is at offset 0 in the group
361 */
362 #define CREG_IDX(regname) \
363 ((QIB_7322_##regname##_0_OFFS - QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
364
365 #define crp_badformat CREG_IDX(RxVersionErrCnt)
366 #define crp_err_rlen CREG_IDX(RxLenErrCnt)
367 #define crp_erricrc CREG_IDX(RxICRCErrCnt)
368 #define crp_errlink CREG_IDX(RxLinkMalformCnt)
369 #define crp_errlpcrc CREG_IDX(RxLPCRCErrCnt)
370 #define crp_errpkey CREG_IDX(RxPKeyMismatchCnt)
371 #define crp_errvcrc CREG_IDX(RxVCRCErrCnt)
372 #define crp_excessbufferovfl CREG_IDX(ExcessBufferOvflCnt)
373 #define crp_iblinkdown CREG_IDX(IBLinkDownedCnt)
374 #define crp_iblinkerrrecov CREG_IDX(IBLinkErrRecoveryCnt)
375 #define crp_ibstatuschange CREG_IDX(IBStatusChangeCnt)
376 #define crp_ibsymbolerr CREG_IDX(IBSymbolErrCnt)
377 #define crp_invalidrlen CREG_IDX(RxMaxMinLenErrCnt)
378 #define crp_locallinkintegrityerr CREG_IDX(LocalLinkIntegrityErrCnt)
379 #define crp_pktrcv CREG_IDX(RxDataPktCnt)
380 #define crp_pktrcvflowctrl CREG_IDX(RxFlowPktCnt)
381 #define crp_pktsend CREG_IDX(TxDataPktCnt)
382 #define crp_pktsendflow CREG_IDX(TxFlowPktCnt)
383 #define crp_psrcvdatacount CREG_IDX(PSRcvDataCount)
384 #define crp_psrcvpktscount CREG_IDX(PSRcvPktsCount)
385 #define crp_psxmitdatacount CREG_IDX(PSXmitDataCount)
386 #define crp_psxmitpktscount CREG_IDX(PSXmitPktsCount)
387 #define crp_psxmitwaitcount CREG_IDX(PSXmitWaitCount)
388 #define crp_rcvebp CREG_IDX(RxEBPCnt)
389 #define crp_rcvflowctrlviol CREG_IDX(RxFlowCtrlViolCnt)
390 #define crp_rcvovfl CREG_IDX(RxBufOvflCnt)
391 #define crp_rxdlidfltr CREG_IDX(RxDlidFltrCnt)
392 #define crp_rxdroppkt CREG_IDX(RxDroppedPktCnt)
393 #define crp_rxotherlocalphyerr CREG_IDX(RxOtherLocalPhyErrCnt)
394 #define crp_rxqpinvalidctxt CREG_IDX(RxQPInvalidContextCnt)
395 #define crp_rxvlerr CREG_IDX(RxVlErrCnt)
396 #define crp_sendstall CREG_IDX(TxFlowStallCnt)
397 #define crp_txdroppedpkt CREG_IDX(TxDroppedPktCnt)
398 #define crp_txhdrerr CREG_IDX(TxHeadersErrCnt)
399 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
400 #define crp_txlenerr CREG_IDX(TxLenErrCnt)
401 #define crp_txminmaxlenerr CREG_IDX(TxMaxMinLenErrCnt)
402 #define crp_txsdmadesc CREG_IDX(TxSDmaDescCnt)
403 #define crp_txunderrun CREG_IDX(TxUnderrunCnt)
404 #define crp_txunsupvl CREG_IDX(TxUnsupVLErrCnt)
405 #define crp_vl15droppedpkt CREG_IDX(RxVL15DroppedPktCnt)
406 #define crp_wordrcv CREG_IDX(RxDwordCnt)
407 #define crp_wordsend CREG_IDX(TxDwordCnt)
408 #define crp_tx_creditstalls CREG_IDX(TxCreditUpToDateTimeOut)
409
410 /* these are the (few) counters that are not port-specific */
411 #define CREG_DEVIDX(regname) ((QIB_7322_##regname##_OFFS - \
412 QIB_7322_LBIntCnt_OFFS) / sizeof(u64))
413 #define cr_base_egrovfl CREG_DEVIDX(RxP0HdrEgrOvflCnt)
414 #define cr_lbint CREG_DEVIDX(LBIntCnt)
415 #define cr_lbstall CREG_DEVIDX(LBFlowStallCnt)
416 #define cr_pcieretrydiag CREG_DEVIDX(PcieRetryBufDiagQwordCnt)
417 #define cr_rxtidflowdrop CREG_DEVIDX(RxTidFlowDropCnt)
418 #define cr_tidfull CREG_DEVIDX(RxTIDFullErrCnt)
419 #define cr_tidinvalid CREG_DEVIDX(RxTIDValidErrCnt)
420
421 /* no chip register for # of IB ports supported, so define */
422 #define NUM_IB_PORTS 2
423
424 /* 1 VL15 buffer per hardware IB port, no register for this, so define */
425 #define NUM_VL15_BUFS NUM_IB_PORTS
426
427 /*
428 * context 0 and 1 are special, and there is no chip register that
429 * defines this value, so we have to define it here.
430 * These are all allocated to either 0 or 1 for single port
431 * hardware configuration, otherwise each gets half
432 */
433 #define KCTXT0_EGRCNT 2048
434
435 /* values for vl and port fields in PBC, 7322-specific */
436 #define PBC_PORT_SEL_LSB 26
437 #define PBC_PORT_SEL_RMASK 1
438 #define PBC_VL_NUM_LSB 27
439 #define PBC_VL_NUM_RMASK 7
440 #define PBC_7322_VL15_SEND (1ULL << 63) /* pbc; VL15, no credit check */
441 #define PBC_7322_VL15_SEND_CTRL (1ULL << 31) /* control version of same */
442
443 static u8 ib_rate_to_delay[IB_RATE_120_GBPS + 1] = {
444 [IB_RATE_2_5_GBPS] = 16,
445 [IB_RATE_5_GBPS] = 8,
446 [IB_RATE_10_GBPS] = 4,
447 [IB_RATE_20_GBPS] = 2,
448 [IB_RATE_30_GBPS] = 2,
449 [IB_RATE_40_GBPS] = 1
450 };
451
452 #define IBA7322_LINKSPEED_SHIFT SYM_LSB(IBCStatusA_0, LinkSpeedActive)
453 #define IBA7322_LINKWIDTH_SHIFT SYM_LSB(IBCStatusA_0, LinkWidthActive)
454
455 /* link training states, from IBC */
456 #define IB_7322_LT_STATE_DISABLED 0x00
457 #define IB_7322_LT_STATE_LINKUP 0x01
458 #define IB_7322_LT_STATE_POLLACTIVE 0x02
459 #define IB_7322_LT_STATE_POLLQUIET 0x03
460 #define IB_7322_LT_STATE_SLEEPDELAY 0x04
461 #define IB_7322_LT_STATE_SLEEPQUIET 0x05
462 #define IB_7322_LT_STATE_CFGDEBOUNCE 0x08
463 #define IB_7322_LT_STATE_CFGRCVFCFG 0x09
464 #define IB_7322_LT_STATE_CFGWAITRMT 0x0a
465 #define IB_7322_LT_STATE_CFGIDLE 0x0b
466 #define IB_7322_LT_STATE_RECOVERRETRAIN 0x0c
467 #define IB_7322_LT_STATE_TXREVLANES 0x0d
468 #define IB_7322_LT_STATE_RECOVERWAITRMT 0x0e
469 #define IB_7322_LT_STATE_RECOVERIDLE 0x0f
470 #define IB_7322_LT_STATE_CFGENH 0x10
471 #define IB_7322_LT_STATE_CFGTEST 0x11
472
473 /* link state machine states from IBC */
474 #define IB_7322_L_STATE_DOWN 0x0
475 #define IB_7322_L_STATE_INIT 0x1
476 #define IB_7322_L_STATE_ARM 0x2
477 #define IB_7322_L_STATE_ACTIVE 0x3
478 #define IB_7322_L_STATE_ACT_DEFER 0x4
479
480 static const u8 qib_7322_physportstate[0x20] = {
481 [IB_7322_LT_STATE_DISABLED] = IB_PHYSPORTSTATE_DISABLED,
482 [IB_7322_LT_STATE_LINKUP] = IB_PHYSPORTSTATE_LINKUP,
483 [IB_7322_LT_STATE_POLLACTIVE] = IB_PHYSPORTSTATE_POLL,
484 [IB_7322_LT_STATE_POLLQUIET] = IB_PHYSPORTSTATE_POLL,
485 [IB_7322_LT_STATE_SLEEPDELAY] = IB_PHYSPORTSTATE_SLEEP,
486 [IB_7322_LT_STATE_SLEEPQUIET] = IB_PHYSPORTSTATE_SLEEP,
487 [IB_7322_LT_STATE_CFGDEBOUNCE] = IB_PHYSPORTSTATE_CFG_TRAIN,
488 [IB_7322_LT_STATE_CFGRCVFCFG] =
489 IB_PHYSPORTSTATE_CFG_TRAIN,
490 [IB_7322_LT_STATE_CFGWAITRMT] =
491 IB_PHYSPORTSTATE_CFG_TRAIN,
492 [IB_7322_LT_STATE_CFGIDLE] = IB_PHYSPORTSTATE_CFG_IDLE,
493 [IB_7322_LT_STATE_RECOVERRETRAIN] =
494 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
495 [IB_7322_LT_STATE_RECOVERWAITRMT] =
496 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
497 [IB_7322_LT_STATE_RECOVERIDLE] =
498 IB_PHYSPORTSTATE_LINK_ERR_RECOVER,
499 [IB_7322_LT_STATE_CFGENH] = IB_PHYSPORTSTATE_CFG_ENH,
500 [IB_7322_LT_STATE_CFGTEST] = IB_PHYSPORTSTATE_CFG_TRAIN,
501 [0x12] = IB_PHYSPORTSTATE_CFG_TRAIN,
502 [0x13] = IB_PHYSPORTSTATE_CFG_WAIT_ENH,
503 [0x14] = IB_PHYSPORTSTATE_CFG_TRAIN,
504 [0x15] = IB_PHYSPORTSTATE_CFG_TRAIN,
505 [0x16] = IB_PHYSPORTSTATE_CFG_TRAIN,
506 [0x17] = IB_PHYSPORTSTATE_CFG_TRAIN
507 };
508
509 struct qib_chip_specific {
510 u64 __iomem *cregbase;
511 u64 *cntrs;
512 spinlock_t rcvmod_lock; /* protect rcvctrl shadow changes */
513 spinlock_t gpio_lock; /* RMW of shadows/regs for ExtCtrl and GPIO */
514 u64 main_int_mask; /* clear bits which have dedicated handlers */
515 u64 int_enable_mask; /* for per port interrupts in single port mode */
516 u64 errormask;
517 u64 hwerrmask;
518 u64 gpio_out; /* shadow of kr_gpio_out, for rmw ops */
519 u64 gpio_mask; /* shadow the gpio mask register */
520 u64 extctrl; /* shadow the gpio output enable, etc... */
521 u32 ncntrs;
522 u32 nportcntrs;
523 u32 cntrnamelen;
524 u32 portcntrnamelen;
525 u32 numctxts;
526 u32 rcvegrcnt;
527 u32 updthresh; /* current AvailUpdThld */
528 u32 updthresh_dflt; /* default AvailUpdThld */
529 u32 r1;
530 int irq;
531 u32 num_msix_entries;
532 u32 sdmabufcnt;
533 u32 lastbuf_for_pio;
534 u32 stay_in_freeze;
535 u32 recovery_ports_initted;
536 struct msix_entry *msix_entries;
537 void **msix_arg;
538 unsigned long *sendchkenable;
539 unsigned long *sendgrhchk;
540 unsigned long *sendibchk;
541 u32 rcvavail_timeout[18];
542 char emsgbuf[128]; /* for device error interrupt msg buffer */
543 };
544
545 /* Table of entries in "human readable" form Tx Emphasis. */
546 struct txdds_ent {
547 u8 amp;
548 u8 pre;
549 u8 main;
550 u8 post;
551 };
552
553 struct vendor_txdds_ent {
554 u8 oui[QSFP_VOUI_LEN];
555 u8 *partnum;
556 struct txdds_ent sdr;
557 struct txdds_ent ddr;
558 struct txdds_ent qdr;
559 };
560
561 static void write_tx_serdes_param(struct qib_pportdata *, struct txdds_ent *);
562
563 #define TXDDS_TABLE_SZ 16 /* number of entries per speed in onchip table */
564 #define TXDDS_EXTRA_SZ 13 /* number of extra tx settings entries */
565 #define TXDDS_MFG_SZ 2 /* number of mfg tx settings entries */
566 #define SERDES_CHANS 4 /* yes, it's obvious, but one less magic number */
567
568 #define H1_FORCE_VAL 8
569 #define H1_FORCE_QME 1 /* may be overridden via setup_txselect() */
570 #define H1_FORCE_QMH 7 /* may be overridden via setup_txselect() */
571
572 /* The static and dynamic registers are paired, and the pairs indexed by spd */
573 #define krp_static_adapt_dis(spd) (KREG_IBPORT_IDX(ADAPT_DISABLE_STATIC_SDR) \
574 + ((spd) * 2))
575
576 #define QDR_DFE_DISABLE_DELAY 4000 /* msec after LINKUP */
577 #define QDR_STATIC_ADAPT_DOWN 0xf0f0f0f0ULL /* link down, H1-H4 QDR adapts */
578 #define QDR_STATIC_ADAPT_DOWN_R1 0ULL /* r1 link down, H1-H4 QDR adapts */
579 #define QDR_STATIC_ADAPT_INIT 0xffffffffffULL /* up, disable H0,H1-8, LE */
580 #define QDR_STATIC_ADAPT_INIT_R1 0xf0ffffffffULL /* r1 up, disable H0,H1-8 */
581
582 struct qib_chippport_specific {
583 u64 __iomem *kpregbase;
584 u64 __iomem *cpregbase;
585 u64 *portcntrs;
586 struct qib_pportdata *ppd;
587 wait_queue_head_t autoneg_wait;
588 struct delayed_work autoneg_work;
589 struct delayed_work ipg_work;
590 struct timer_list chase_timer;
591 /*
592 * these 5 fields are used to establish deltas for IB symbol
593 * errors and linkrecovery errors. They can be reported on
594 * some chips during link negotiation prior to INIT, and with
595 * DDR when faking DDR negotiations with non-IBTA switches.
596 * The chip counters are adjusted at driver unload if there is
597 * a non-zero delta.
598 */
599 u64 ibdeltainprog;
600 u64 ibsymdelta;
601 u64 ibsymsnap;
602 u64 iblnkerrdelta;
603 u64 iblnkerrsnap;
604 u64 iblnkdownsnap;
605 u64 iblnkdowndelta;
606 u64 ibmalfdelta;
607 u64 ibmalfsnap;
608 u64 ibcctrl_a; /* krp_ibcctrl_a shadow */
609 u64 ibcctrl_b; /* krp_ibcctrl_b shadow */
610 u64 qdr_dfe_time;
611 u64 chase_end;
612 u32 autoneg_tries;
613 u32 recovery_init;
614 u32 qdr_dfe_on;
615 u32 qdr_reforce;
616 /*
617 * Per-bay per-channel rcv QMH H1 values and Tx values for QDR.
618 * entry zero is unused, to simplify indexing
619 */
620 u8 h1_val;
621 u8 no_eep; /* txselect table index to use if no qsfp info */
622 u8 ipg_tries;
623 u8 ibmalfusesnap;
624 struct qib_qsfp_data qsfp_data;
625 char epmsgbuf[192]; /* for port error interrupt msg buffer */
626 };
627
628 static struct {
629 const char *name;
630 irq_handler_t handler;
631 int lsb;
632 int port; /* 0 if not port-specific, else port # */
633 } irq_table[] = {
634 { QIB_DRV_NAME, qib_7322intr, -1, 0 },
635 { QIB_DRV_NAME " (buf avail)", qib_7322bufavail,
636 SYM_LSB(IntStatus, SendBufAvail), 0 },
637 { QIB_DRV_NAME " (sdma 0)", sdma_intr,
638 SYM_LSB(IntStatus, SDmaInt_0), 1 },
639 { QIB_DRV_NAME " (sdma 1)", sdma_intr,
640 SYM_LSB(IntStatus, SDmaInt_1), 2 },
641 { QIB_DRV_NAME " (sdmaI 0)", sdma_idle_intr,
642 SYM_LSB(IntStatus, SDmaIdleInt_0), 1 },
643 { QIB_DRV_NAME " (sdmaI 1)", sdma_idle_intr,
644 SYM_LSB(IntStatus, SDmaIdleInt_1), 2 },
645 { QIB_DRV_NAME " (sdmaP 0)", sdma_progress_intr,
646 SYM_LSB(IntStatus, SDmaProgressInt_0), 1 },
647 { QIB_DRV_NAME " (sdmaP 1)", sdma_progress_intr,
648 SYM_LSB(IntStatus, SDmaProgressInt_1), 2 },
649 { QIB_DRV_NAME " (sdmaC 0)", sdma_cleanup_intr,
650 SYM_LSB(IntStatus, SDmaCleanupDone_0), 1 },
651 { QIB_DRV_NAME " (sdmaC 1)", sdma_cleanup_intr,
652 SYM_LSB(IntStatus, SDmaCleanupDone_1), 2 },
653 };
654
655 /* ibcctrl bits */
656 #define QLOGIC_IB_IBCC_LINKINITCMD_DISABLE 1
657 /* cycle through TS1/TS2 till OK */
658 #define QLOGIC_IB_IBCC_LINKINITCMD_POLL 2
659 /* wait for TS1, then go on */
660 #define QLOGIC_IB_IBCC_LINKINITCMD_SLEEP 3
661 #define QLOGIC_IB_IBCC_LINKINITCMD_SHIFT 16
662
663 #define QLOGIC_IB_IBCC_LINKCMD_DOWN 1 /* move to 0x11 */
664 #define QLOGIC_IB_IBCC_LINKCMD_ARMED 2 /* move to 0x21 */
665 #define QLOGIC_IB_IBCC_LINKCMD_ACTIVE 3 /* move to 0x31 */
666
667 #define BLOB_7322_IBCHG 0x101
668
669 static inline void qib_write_kreg(const struct qib_devdata *dd,
670 const u32 regno, u64 value);
671 static inline u32 qib_read_kreg32(const struct qib_devdata *, const u32);
672 static void write_7322_initregs(struct qib_devdata *);
673 static void write_7322_init_portregs(struct qib_pportdata *);
674 static void setup_7322_link_recovery(struct qib_pportdata *, u32);
675 static void check_7322_rxe_status(struct qib_pportdata *);
676 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *, u64, u32 *);
677
678 /**
679 * qib_read_ureg32 - read 32-bit virtualized per-context register
680 * @dd: device
681 * @regno: register number
682 * @ctxt: context number
683 *
684 * Return the contents of a register that is virtualized to be per context.
685 * Returns -1 on errors (not distinguishable from valid contents at
686 * runtime; we may add a separate error variable at some point).
687 */
688 static inline u32 qib_read_ureg32(const struct qib_devdata *dd,
689 enum qib_ureg regno, int ctxt)
690 {
691 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
692 return 0;
693 return readl(regno + (u64 __iomem *)(
694 (dd->ureg_align * ctxt) + (dd->userbase ?
695 (char __iomem *)dd->userbase :
696 (char __iomem *)dd->kregbase + dd->uregbase)));
697 }
698
699 /**
700 * qib_read_ureg - read virtualized per-context register
701 * @dd: device
702 * @regno: register number
703 * @ctxt: context number
704 *
705 * Return the contents of a register that is virtualized to be per context.
706 * Returns -1 on errors (not distinguishable from valid contents at
707 * runtime; we may add a separate error variable at some point).
708 */
709 static inline u64 qib_read_ureg(const struct qib_devdata *dd,
710 enum qib_ureg regno, int ctxt)
711 {
712
713 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
714 return 0;
715 return readq(regno + (u64 __iomem *)(
716 (dd->ureg_align * ctxt) + (dd->userbase ?
717 (char __iomem *)dd->userbase :
718 (char __iomem *)dd->kregbase + dd->uregbase)));
719 }
720
721 /**
722 * qib_write_ureg - write virtualized per-context register
723 * @dd: device
724 * @regno: register number
725 * @value: value
726 * @ctxt: context
727 *
728 * Write the contents of a register that is virtualized to be per context.
729 */
730 static inline void qib_write_ureg(const struct qib_devdata *dd,
731 enum qib_ureg regno, u64 value, int ctxt)
732 {
733 u64 __iomem *ubase;
734 if (dd->userbase)
735 ubase = (u64 __iomem *)
736 ((char __iomem *) dd->userbase +
737 dd->ureg_align * ctxt);
738 else
739 ubase = (u64 __iomem *)
740 (dd->uregbase +
741 (char __iomem *) dd->kregbase +
742 dd->ureg_align * ctxt);
743
744 if (dd->kregbase && (dd->flags & QIB_PRESENT))
745 writeq(value, &ubase[regno]);
746 }
747
748 static inline u32 qib_read_kreg32(const struct qib_devdata *dd,
749 const u32 regno)
750 {
751 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
752 return -1;
753 return readl((u32 __iomem *) &dd->kregbase[regno]);
754 }
755
756 static inline u64 qib_read_kreg64(const struct qib_devdata *dd,
757 const u32 regno)
758 {
759 if (!dd->kregbase || !(dd->flags & QIB_PRESENT))
760 return -1;
761 return readq(&dd->kregbase[regno]);
762 }
763
764 static inline void qib_write_kreg(const struct qib_devdata *dd,
765 const u32 regno, u64 value)
766 {
767 if (dd->kregbase && (dd->flags & QIB_PRESENT))
768 writeq(value, &dd->kregbase[regno]);
769 }
770
771 /*
772 * not many sanity checks for the port-specific kernel register routines,
773 * since they are only used when it's known to be safe.
774 */
775 static inline u64 qib_read_kreg_port(const struct qib_pportdata *ppd,
776 const u16 regno)
777 {
778 if (!ppd->cpspec->kpregbase || !(ppd->dd->flags & QIB_PRESENT))
779 return 0ULL;
780 return readq(&ppd->cpspec->kpregbase[regno]);
781 }
782
783 static inline void qib_write_kreg_port(const struct qib_pportdata *ppd,
784 const u16 regno, u64 value)
785 {
786 if (ppd->cpspec && ppd->dd && ppd->cpspec->kpregbase &&
787 (ppd->dd->flags & QIB_PRESENT))
788 writeq(value, &ppd->cpspec->kpregbase[regno]);
789 }
790
791 /**
792 * qib_write_kreg_ctxt - write a device's per-ctxt 64-bit kernel register
793 * @dd: the qlogic_ib device
794 * @regno: the register number to write
795 * @ctxt: the context containing the register
796 * @value: the value to write
797 */
798 static inline void qib_write_kreg_ctxt(const struct qib_devdata *dd,
799 const u16 regno, unsigned ctxt,
800 u64 value)
801 {
802 qib_write_kreg(dd, regno + ctxt, value);
803 }
804
805 static inline u64 read_7322_creg(const struct qib_devdata *dd, u16 regno)
806 {
807 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
808 return 0;
809 return readq(&dd->cspec->cregbase[regno]);
810
811
812 }
813
814 static inline u32 read_7322_creg32(const struct qib_devdata *dd, u16 regno)
815 {
816 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT))
817 return 0;
818 return readl(&dd->cspec->cregbase[regno]);
819
820
821 }
822
823 static inline void write_7322_creg_port(const struct qib_pportdata *ppd,
824 u16 regno, u64 value)
825 {
826 if (ppd->cpspec && ppd->cpspec->cpregbase &&
827 (ppd->dd->flags & QIB_PRESENT))
828 writeq(value, &ppd->cpspec->cpregbase[regno]);
829 }
830
831 static inline u64 read_7322_creg_port(const struct qib_pportdata *ppd,
832 u16 regno)
833 {
834 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
835 !(ppd->dd->flags & QIB_PRESENT))
836 return 0;
837 return readq(&ppd->cpspec->cpregbase[regno]);
838 }
839
840 static inline u32 read_7322_creg32_port(const struct qib_pportdata *ppd,
841 u16 regno)
842 {
843 if (!ppd->cpspec || !ppd->cpspec->cpregbase ||
844 !(ppd->dd->flags & QIB_PRESENT))
845 return 0;
846 return readl(&ppd->cpspec->cpregbase[regno]);
847 }
848
849 /* bits in Control register */
850 #define QLOGIC_IB_C_RESET SYM_MASK(Control, SyncReset)
851 #define QLOGIC_IB_C_SDMAFETCHPRIOEN SYM_MASK(Control, SDmaDescFetchPriorityEn)
852
853 /* bits in general interrupt regs */
854 #define QIB_I_RCVURG_LSB SYM_LSB(IntMask, RcvUrg0IntMask)
855 #define QIB_I_RCVURG_RMASK MASK_ACROSS(0, 17)
856 #define QIB_I_RCVURG_MASK (QIB_I_RCVURG_RMASK << QIB_I_RCVURG_LSB)
857 #define QIB_I_RCVAVAIL_LSB SYM_LSB(IntMask, RcvAvail0IntMask)
858 #define QIB_I_RCVAVAIL_RMASK MASK_ACROSS(0, 17)
859 #define QIB_I_RCVAVAIL_MASK (QIB_I_RCVAVAIL_RMASK << QIB_I_RCVAVAIL_LSB)
860 #define QIB_I_C_ERROR INT_MASK(Err)
861
862 #define QIB_I_SPIOSENT (INT_MASK_P(SendDone, 0) | INT_MASK_P(SendDone, 1))
863 #define QIB_I_SPIOBUFAVAIL INT_MASK(SendBufAvail)
864 #define QIB_I_GPIO INT_MASK(AssertGPIO)
865 #define QIB_I_P_SDMAINT(pidx) \
866 (INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
867 INT_MASK_P(SDmaProgress, pidx) | \
868 INT_MASK_PM(SDmaCleanupDone, pidx))
869
870 /* Interrupt bits that are "per port" */
871 #define QIB_I_P_BITSEXTANT(pidx) \
872 (INT_MASK_P(Err, pidx) | INT_MASK_P(SendDone, pidx) | \
873 INT_MASK_P(SDma, pidx) | INT_MASK_P(SDmaIdle, pidx) | \
874 INT_MASK_P(SDmaProgress, pidx) | \
875 INT_MASK_PM(SDmaCleanupDone, pidx))
876
877 /* Interrupt bits that are common to a device */
878 /* currently unused: QIB_I_SPIOSENT */
879 #define QIB_I_C_BITSEXTANT \
880 (QIB_I_RCVURG_MASK | QIB_I_RCVAVAIL_MASK | \
881 QIB_I_SPIOSENT | \
882 QIB_I_C_ERROR | QIB_I_SPIOBUFAVAIL | QIB_I_GPIO)
883
884 #define QIB_I_BITSEXTANT (QIB_I_C_BITSEXTANT | \
885 QIB_I_P_BITSEXTANT(0) | QIB_I_P_BITSEXTANT(1))
886
887 /*
888 * Error bits that are "per port".
889 */
890 #define QIB_E_P_IBSTATUSCHANGED ERR_MASK_N(IBStatusChanged)
891 #define QIB_E_P_SHDR ERR_MASK_N(SHeadersErr)
892 #define QIB_E_P_VL15_BUF_MISUSE ERR_MASK_N(VL15BufMisuseErr)
893 #define QIB_E_P_SND_BUF_MISUSE ERR_MASK_N(SendBufMisuseErr)
894 #define QIB_E_P_SUNSUPVL ERR_MASK_N(SendUnsupportedVLErr)
895 #define QIB_E_P_SUNEXP_PKTNUM ERR_MASK_N(SendUnexpectedPktNumErr)
896 #define QIB_E_P_SDROP_DATA ERR_MASK_N(SendDroppedDataPktErr)
897 #define QIB_E_P_SDROP_SMP ERR_MASK_N(SendDroppedSmpPktErr)
898 #define QIB_E_P_SPKTLEN ERR_MASK_N(SendPktLenErr)
899 #define QIB_E_P_SUNDERRUN ERR_MASK_N(SendUnderRunErr)
900 #define QIB_E_P_SMAXPKTLEN ERR_MASK_N(SendMaxPktLenErr)
901 #define QIB_E_P_SMINPKTLEN ERR_MASK_N(SendMinPktLenErr)
902 #define QIB_E_P_RIBLOSTLINK ERR_MASK_N(RcvIBLostLinkErr)
903 #define QIB_E_P_RHDR ERR_MASK_N(RcvHdrErr)
904 #define QIB_E_P_RHDRLEN ERR_MASK_N(RcvHdrLenErr)
905 #define QIB_E_P_RBADTID ERR_MASK_N(RcvBadTidErr)
906 #define QIB_E_P_RBADVERSION ERR_MASK_N(RcvBadVersionErr)
907 #define QIB_E_P_RIBFLOW ERR_MASK_N(RcvIBFlowErr)
908 #define QIB_E_P_REBP ERR_MASK_N(RcvEBPErr)
909 #define QIB_E_P_RUNSUPVL ERR_MASK_N(RcvUnsupportedVLErr)
910 #define QIB_E_P_RUNEXPCHAR ERR_MASK_N(RcvUnexpectedCharErr)
911 #define QIB_E_P_RSHORTPKTLEN ERR_MASK_N(RcvShortPktLenErr)
912 #define QIB_E_P_RLONGPKTLEN ERR_MASK_N(RcvLongPktLenErr)
913 #define QIB_E_P_RMAXPKTLEN ERR_MASK_N(RcvMaxPktLenErr)
914 #define QIB_E_P_RMINPKTLEN ERR_MASK_N(RcvMinPktLenErr)
915 #define QIB_E_P_RICRC ERR_MASK_N(RcvICRCErr)
916 #define QIB_E_P_RVCRC ERR_MASK_N(RcvVCRCErr)
917 #define QIB_E_P_RFORMATERR ERR_MASK_N(RcvFormatErr)
918
919 #define QIB_E_P_SDMA1STDESC ERR_MASK_N(SDma1stDescErr)
920 #define QIB_E_P_SDMABASE ERR_MASK_N(SDmaBaseErr)
921 #define QIB_E_P_SDMADESCADDRMISALIGN ERR_MASK_N(SDmaDescAddrMisalignErr)
922 #define QIB_E_P_SDMADWEN ERR_MASK_N(SDmaDwEnErr)
923 #define QIB_E_P_SDMAGENMISMATCH ERR_MASK_N(SDmaGenMismatchErr)
924 #define QIB_E_P_SDMAHALT ERR_MASK_N(SDmaHaltErr)
925 #define QIB_E_P_SDMAMISSINGDW ERR_MASK_N(SDmaMissingDwErr)
926 #define QIB_E_P_SDMAOUTOFBOUND ERR_MASK_N(SDmaOutOfBoundErr)
927 #define QIB_E_P_SDMARPYTAG ERR_MASK_N(SDmaRpyTagErr)
928 #define QIB_E_P_SDMATAILOUTOFBOUND ERR_MASK_N(SDmaTailOutOfBoundErr)
929 #define QIB_E_P_SDMAUNEXPDATA ERR_MASK_N(SDmaUnexpDataErr)
930
931 /* Error bits that are common to a device */
932 #define QIB_E_RESET ERR_MASK(ResetNegated)
933 #define QIB_E_HARDWARE ERR_MASK(HardwareErr)
934 #define QIB_E_INVALIDADDR ERR_MASK(InvalidAddrErr)
935
936
937 /*
938 * Per chip (rather than per-port) errors. Most either do
939 * nothing but trigger a print (because they self-recover, or
940 * always occur in tandem with other errors that handle the
941 * issue), or because they indicate errors with no recovery,
942 * but we want to know that they happened.
943 */
944 #define QIB_E_SBUF_VL15_MISUSE ERR_MASK(SBufVL15MisUseErr)
945 #define QIB_E_BADEEP ERR_MASK(InvalidEEPCmd)
946 #define QIB_E_VLMISMATCH ERR_MASK(SendVLMismatchErr)
947 #define QIB_E_ARMLAUNCH ERR_MASK(SendArmLaunchErr)
948 #define QIB_E_SPCLTRIG ERR_MASK(SendSpecialTriggerErr)
949 #define QIB_E_RRCVHDRFULL ERR_MASK(RcvHdrFullErr)
950 #define QIB_E_RRCVEGRFULL ERR_MASK(RcvEgrFullErr)
951 #define QIB_E_RCVCTXTSHARE ERR_MASK(RcvContextShareErr)
952
953 /* SDMA chip errors (not per port)
954 * QIB_E_SDMA_BUF_DUP needs no special handling, because we will also get
955 * the SDMAHALT error immediately, so we just print the dup error via the
956 * E_AUTO mechanism. This is true of most of the per-port fatal errors
957 * as well, but since this is port-independent, by definition, it's
958 * handled a bit differently. SDMA_VL15 and SDMA_WRONG_PORT are per
959 * packet send errors, and so are handled in the same manner as other
960 * per-packet errors.
961 */
962 #define QIB_E_SDMA_VL15 ERR_MASK(SDmaVL15Err)
963 #define QIB_E_SDMA_WRONG_PORT ERR_MASK(SDmaWrongPortErr)
964 #define QIB_E_SDMA_BUF_DUP ERR_MASK(SDmaBufMaskDuplicateErr)
965
966 /*
967 * Below functionally equivalent to legacy QLOGIC_IB_E_PKTERRS
968 * it is used to print "common" packet errors.
969 */
970 #define QIB_E_P_PKTERRS (QIB_E_P_SPKTLEN |\
971 QIB_E_P_SDROP_DATA | QIB_E_P_RVCRC |\
972 QIB_E_P_RICRC | QIB_E_P_RSHORTPKTLEN |\
973 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
974 QIB_E_P_REBP)
975
976 /* Error Bits that Packet-related (Receive, per-port) */
977 #define QIB_E_P_RPKTERRS (\
978 QIB_E_P_RHDRLEN | QIB_E_P_RBADTID | \
979 QIB_E_P_RBADVERSION | QIB_E_P_RHDR | \
980 QIB_E_P_RLONGPKTLEN | QIB_E_P_RSHORTPKTLEN |\
981 QIB_E_P_RMAXPKTLEN | QIB_E_P_RMINPKTLEN | \
982 QIB_E_P_RFORMATERR | QIB_E_P_RUNSUPVL | \
983 QIB_E_P_RUNEXPCHAR | QIB_E_P_RIBFLOW | QIB_E_P_REBP)
984
985 /*
986 * Error bits that are Send-related (per port)
987 * (ARMLAUNCH excluded from E_SPKTERRS because it gets special handling).
988 * All of these potentially need to have a buffer disarmed
989 */
990 #define QIB_E_P_SPKTERRS (\
991 QIB_E_P_SUNEXP_PKTNUM |\
992 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
993 QIB_E_P_SMAXPKTLEN |\
994 QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SHDR | \
995 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN | \
996 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNSUPVL)
997
998 #define QIB_E_SPKTERRS ( \
999 QIB_E_SBUF_VL15_MISUSE | QIB_E_VLMISMATCH | \
1000 ERR_MASK_N(SendUnsupportedVLErr) | \
1001 QIB_E_SPCLTRIG | QIB_E_SDMA_VL15 | QIB_E_SDMA_WRONG_PORT)
1002
1003 #define QIB_E_P_SDMAERRS ( \
1004 QIB_E_P_SDMAHALT | \
1005 QIB_E_P_SDMADESCADDRMISALIGN | \
1006 QIB_E_P_SDMAUNEXPDATA | \
1007 QIB_E_P_SDMAMISSINGDW | \
1008 QIB_E_P_SDMADWEN | \
1009 QIB_E_P_SDMARPYTAG | \
1010 QIB_E_P_SDMA1STDESC | \
1011 QIB_E_P_SDMABASE | \
1012 QIB_E_P_SDMATAILOUTOFBOUND | \
1013 QIB_E_P_SDMAOUTOFBOUND | \
1014 QIB_E_P_SDMAGENMISMATCH)
1015
1016 /*
1017 * This sets some bits more than once, but makes it more obvious which
1018 * bits are not handled under other categories, and the repeat definition
1019 * is not a problem.
1020 */
1021 #define QIB_E_P_BITSEXTANT ( \
1022 QIB_E_P_SPKTERRS | QIB_E_P_PKTERRS | QIB_E_P_RPKTERRS | \
1023 QIB_E_P_RIBLOSTLINK | QIB_E_P_IBSTATUSCHANGED | \
1024 QIB_E_P_SND_BUF_MISUSE | QIB_E_P_SUNDERRUN | \
1025 QIB_E_P_SHDR | QIB_E_P_VL15_BUF_MISUSE | QIB_E_P_SDMAERRS \
1026 )
1027
1028 /*
1029 * These are errors that can occur when the link
1030 * changes state while a packet is being sent or received. This doesn't
1031 * cover things like EBP or VCRC that can be the result of a sending
1032 * having the link change state, so we receive a "known bad" packet.
1033 * All of these are "per port", so renamed:
1034 */
1035 #define QIB_E_P_LINK_PKTERRS (\
1036 QIB_E_P_SDROP_DATA | QIB_E_P_SDROP_SMP |\
1037 QIB_E_P_SMINPKTLEN | QIB_E_P_SPKTLEN |\
1038 QIB_E_P_RSHORTPKTLEN | QIB_E_P_RMINPKTLEN |\
1039 QIB_E_P_RUNEXPCHAR)
1040
1041 /*
1042 * This sets some bits more than once, but makes it more obvious which
1043 * bits are not handled under other categories (such as QIB_E_SPKTERRS),
1044 * and the repeat definition is not a problem.
1045 */
1046 #define QIB_E_C_BITSEXTANT (\
1047 QIB_E_HARDWARE | QIB_E_INVALIDADDR | QIB_E_BADEEP |\
1048 QIB_E_ARMLAUNCH | QIB_E_VLMISMATCH | QIB_E_RRCVHDRFULL |\
1049 QIB_E_RRCVEGRFULL | QIB_E_RESET | QIB_E_SBUF_VL15_MISUSE)
1050
1051 /* Likewise Neuter E_SPKT_ERRS_IGNORE */
1052 #define E_SPKT_ERRS_IGNORE 0
1053
1054 #define QIB_EXTS_MEMBIST_DISABLED \
1055 SYM_MASK(EXTStatus, MemBISTDisabled)
1056 #define QIB_EXTS_MEMBIST_ENDTEST \
1057 SYM_MASK(EXTStatus, MemBISTEndTest)
1058
1059 #define QIB_E_SPIOARMLAUNCH \
1060 ERR_MASK(SendArmLaunchErr)
1061
1062 #define IBA7322_IBCC_LINKINITCMD_MASK SYM_RMASK(IBCCtrlA_0, LinkInitCmd)
1063 #define IBA7322_IBCC_LINKCMD_SHIFT SYM_LSB(IBCCtrlA_0, LinkCmd)
1064
1065 /*
1066 * IBTA_1_2 is set when multiple speeds are enabled (normal),
1067 * and also if forced QDR (only QDR enabled). It's enabled for the
1068 * forced QDR case so that scrambling will be enabled by the TS3
1069 * exchange, when supported by both sides of the link.
1070 */
1071 #define IBA7322_IBC_IBTA_1_2_MASK SYM_MASK(IBCCtrlB_0, IB_ENHANCED_MODE)
1072 #define IBA7322_IBC_MAX_SPEED_MASK SYM_MASK(IBCCtrlB_0, SD_SPEED)
1073 #define IBA7322_IBC_SPEED_QDR SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR)
1074 #define IBA7322_IBC_SPEED_DDR SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR)
1075 #define IBA7322_IBC_SPEED_SDR SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR)
1076 #define IBA7322_IBC_SPEED_MASK (SYM_MASK(IBCCtrlB_0, SD_SPEED_SDR) | \
1077 SYM_MASK(IBCCtrlB_0, SD_SPEED_DDR) | SYM_MASK(IBCCtrlB_0, SD_SPEED_QDR))
1078 #define IBA7322_IBC_SPEED_LSB SYM_LSB(IBCCtrlB_0, SD_SPEED_SDR)
1079
1080 #define IBA7322_LEDBLINK_OFF_SHIFT SYM_LSB(RcvPktLEDCnt_0, OFFperiod)
1081 #define IBA7322_LEDBLINK_ON_SHIFT SYM_LSB(RcvPktLEDCnt_0, ONperiod)
1082
1083 #define IBA7322_IBC_WIDTH_AUTONEG SYM_MASK(IBCCtrlB_0, IB_NUM_CHANNELS)
1084 #define IBA7322_IBC_WIDTH_4X_ONLY (1<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1085 #define IBA7322_IBC_WIDTH_1X_ONLY (0<<SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS))
1086
1087 #define IBA7322_IBC_RXPOL_MASK SYM_MASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1088 #define IBA7322_IBC_RXPOL_LSB SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP)
1089 #define IBA7322_IBC_HRTBT_MASK (SYM_MASK(IBCCtrlB_0, HRTBT_AUTO) | \
1090 SYM_MASK(IBCCtrlB_0, HRTBT_ENB))
1091 #define IBA7322_IBC_HRTBT_RMASK (IBA7322_IBC_HRTBT_MASK >> \
1092 SYM_LSB(IBCCtrlB_0, HRTBT_ENB))
1093 #define IBA7322_IBC_HRTBT_LSB SYM_LSB(IBCCtrlB_0, HRTBT_ENB)
1094
1095 #define IBA7322_REDIRECT_VEC_PER_REG 12
1096
1097 #define IBA7322_SENDCHK_PKEY SYM_MASK(SendCheckControl_0, PKey_En)
1098 #define IBA7322_SENDCHK_BTHQP SYM_MASK(SendCheckControl_0, BTHQP_En)
1099 #define IBA7322_SENDCHK_SLID SYM_MASK(SendCheckControl_0, SLID_En)
1100 #define IBA7322_SENDCHK_RAW_IPV6 SYM_MASK(SendCheckControl_0, RawIPV6_En)
1101 #define IBA7322_SENDCHK_MINSZ SYM_MASK(SendCheckControl_0, PacketTooSmall_En)
1102
1103 #define AUTONEG_TRIES 3 /* sequential retries to negotiate DDR */
1104
1105 #define HWE_AUTO(fldname) { .mask = SYM_MASK(HwErrMask, fldname##Mask), \
1106 .msg = #fldname }
1107 #define HWE_AUTO_P(fldname, port) { .mask = SYM_MASK(HwErrMask, \
1108 fldname##Mask##_##port), .msg = #fldname }
1109 static const struct qib_hwerror_msgs qib_7322_hwerror_msgs[] = {
1110 HWE_AUTO_P(IBSerdesPClkNotDetect, 1),
1111 HWE_AUTO_P(IBSerdesPClkNotDetect, 0),
1112 HWE_AUTO(PCIESerdesPClkNotDetect),
1113 HWE_AUTO(PowerOnBISTFailed),
1114 HWE_AUTO(TempsenseTholdReached),
1115 HWE_AUTO(MemoryErr),
1116 HWE_AUTO(PCIeBusParityErr),
1117 HWE_AUTO(PcieCplTimeout),
1118 HWE_AUTO(PciePoisonedTLP),
1119 HWE_AUTO_P(SDmaMemReadErr, 1),
1120 HWE_AUTO_P(SDmaMemReadErr, 0),
1121 HWE_AUTO_P(IBCBusFromSPCParityErr, 1),
1122 HWE_AUTO_P(IBCBusToSPCParityErr, 1),
1123 HWE_AUTO_P(IBCBusFromSPCParityErr, 0),
1124 HWE_AUTO(statusValidNoEop),
1125 HWE_AUTO(LATriggered),
1126 { .mask = 0 }
1127 };
1128
1129 #define E_AUTO(fldname) { .mask = SYM_MASK(ErrMask, fldname##Mask), \
1130 .msg = #fldname }
1131 #define E_P_AUTO(fldname) { .mask = SYM_MASK(ErrMask_0, fldname##Mask), \
1132 .msg = #fldname }
1133 static const struct qib_hwerror_msgs qib_7322error_msgs[] = {
1134 E_AUTO(ResetNegated),
1135 E_AUTO(HardwareErr),
1136 E_AUTO(InvalidAddrErr),
1137 E_AUTO(SDmaVL15Err),
1138 E_AUTO(SBufVL15MisUseErr),
1139 E_AUTO(InvalidEEPCmd),
1140 E_AUTO(RcvContextShareErr),
1141 E_AUTO(SendVLMismatchErr),
1142 E_AUTO(SendArmLaunchErr),
1143 E_AUTO(SendSpecialTriggerErr),
1144 E_AUTO(SDmaWrongPortErr),
1145 E_AUTO(SDmaBufMaskDuplicateErr),
1146 E_AUTO(RcvHdrFullErr),
1147 E_AUTO(RcvEgrFullErr),
1148 { .mask = 0 }
1149 };
1150
1151 static const struct qib_hwerror_msgs qib_7322p_error_msgs[] = {
1152 E_P_AUTO(IBStatusChanged),
1153 E_P_AUTO(SHeadersErr),
1154 E_P_AUTO(VL15BufMisuseErr),
1155 /*
1156 * SDmaHaltErr is not really an error, make it clearer;
1157 */
1158 {.mask = SYM_MASK(ErrMask_0, SDmaHaltErrMask), .msg = "SDmaHalted"},
1159 E_P_AUTO(SDmaDescAddrMisalignErr),
1160 E_P_AUTO(SDmaUnexpDataErr),
1161 E_P_AUTO(SDmaMissingDwErr),
1162 E_P_AUTO(SDmaDwEnErr),
1163 E_P_AUTO(SDmaRpyTagErr),
1164 E_P_AUTO(SDma1stDescErr),
1165 E_P_AUTO(SDmaBaseErr),
1166 E_P_AUTO(SDmaTailOutOfBoundErr),
1167 E_P_AUTO(SDmaOutOfBoundErr),
1168 E_P_AUTO(SDmaGenMismatchErr),
1169 E_P_AUTO(SendBufMisuseErr),
1170 E_P_AUTO(SendUnsupportedVLErr),
1171 E_P_AUTO(SendUnexpectedPktNumErr),
1172 E_P_AUTO(SendDroppedDataPktErr),
1173 E_P_AUTO(SendDroppedSmpPktErr),
1174 E_P_AUTO(SendPktLenErr),
1175 E_P_AUTO(SendUnderRunErr),
1176 E_P_AUTO(SendMaxPktLenErr),
1177 E_P_AUTO(SendMinPktLenErr),
1178 E_P_AUTO(RcvIBLostLinkErr),
1179 E_P_AUTO(RcvHdrErr),
1180 E_P_AUTO(RcvHdrLenErr),
1181 E_P_AUTO(RcvBadTidErr),
1182 E_P_AUTO(RcvBadVersionErr),
1183 E_P_AUTO(RcvIBFlowErr),
1184 E_P_AUTO(RcvEBPErr),
1185 E_P_AUTO(RcvUnsupportedVLErr),
1186 E_P_AUTO(RcvUnexpectedCharErr),
1187 E_P_AUTO(RcvShortPktLenErr),
1188 E_P_AUTO(RcvLongPktLenErr),
1189 E_P_AUTO(RcvMaxPktLenErr),
1190 E_P_AUTO(RcvMinPktLenErr),
1191 E_P_AUTO(RcvICRCErr),
1192 E_P_AUTO(RcvVCRCErr),
1193 E_P_AUTO(RcvFormatErr),
1194 { .mask = 0 }
1195 };
1196
1197 /*
1198 * Below generates "auto-message" for interrupts not specific to any port or
1199 * context
1200 */
1201 #define INTR_AUTO(fldname) { .mask = SYM_MASK(IntMask, fldname##Mask), \
1202 .msg = #fldname }
1203 /* Below generates "auto-message" for interrupts specific to a port */
1204 #define INTR_AUTO_P(fldname) { .mask = MASK_ACROSS(\
1205 SYM_LSB(IntMask, fldname##Mask##_0), \
1206 SYM_LSB(IntMask, fldname##Mask##_1)), \
1207 .msg = #fldname "_P" }
1208 /* For some reason, the SerDesTrimDone bits are reversed */
1209 #define INTR_AUTO_PI(fldname) { .mask = MASK_ACROSS(\
1210 SYM_LSB(IntMask, fldname##Mask##_1), \
1211 SYM_LSB(IntMask, fldname##Mask##_0)), \
1212 .msg = #fldname "_P" }
1213 /*
1214 * Below generates "auto-message" for interrupts specific to a context,
1215 * with ctxt-number appended
1216 */
1217 #define INTR_AUTO_C(fldname) { .mask = MASK_ACROSS(\
1218 SYM_LSB(IntMask, fldname##0IntMask), \
1219 SYM_LSB(IntMask, fldname##17IntMask)), \
1220 .msg = #fldname "_C"}
1221
1222 static const struct qib_hwerror_msgs qib_7322_intr_msgs[] = {
1223 INTR_AUTO_P(SDmaInt),
1224 INTR_AUTO_P(SDmaProgressInt),
1225 INTR_AUTO_P(SDmaIdleInt),
1226 INTR_AUTO_P(SDmaCleanupDone),
1227 INTR_AUTO_C(RcvUrg),
1228 INTR_AUTO_P(ErrInt),
1229 INTR_AUTO(ErrInt), /* non-port-specific errs */
1230 INTR_AUTO(AssertGPIOInt),
1231 INTR_AUTO_P(SendDoneInt),
1232 INTR_AUTO(SendBufAvailInt),
1233 INTR_AUTO_C(RcvAvail),
1234 { .mask = 0 }
1235 };
1236
1237 #define TXSYMPTOM_AUTO_P(fldname) \
1238 { .mask = SYM_MASK(SendHdrErrSymptom_0, fldname), .msg = #fldname }
1239 static const struct qib_hwerror_msgs hdrchk_msgs[] = {
1240 TXSYMPTOM_AUTO_P(NonKeyPacket),
1241 TXSYMPTOM_AUTO_P(GRHFail),
1242 TXSYMPTOM_AUTO_P(PkeyFail),
1243 TXSYMPTOM_AUTO_P(QPFail),
1244 TXSYMPTOM_AUTO_P(SLIDFail),
1245 TXSYMPTOM_AUTO_P(RawIPV6),
1246 TXSYMPTOM_AUTO_P(PacketTooSmall),
1247 { .mask = 0 }
1248 };
1249
1250 #define IBA7322_HDRHEAD_PKTINT_SHIFT 32 /* interrupt cnt in upper 32 bits */
1251
1252 /*
1253 * Called when we might have an error that is specific to a particular
1254 * PIO buffer, and may need to cancel that buffer, so it can be re-used,
1255 * because we don't need to force the update of pioavail
1256 */
1257 static void qib_disarm_7322_senderrbufs(struct qib_pportdata *ppd)
1258 {
1259 struct qib_devdata *dd = ppd->dd;
1260 u32 i;
1261 int any;
1262 u32 piobcnt = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
1263 u32 regcnt = (piobcnt + BITS_PER_LONG - 1) / BITS_PER_LONG;
1264 unsigned long sbuf[4];
1265
1266 /*
1267 * It's possible that sendbuffererror could have bits set; might
1268 * have already done this as a result of hardware error handling.
1269 */
1270 any = 0;
1271 for (i = 0; i < regcnt; ++i) {
1272 sbuf[i] = qib_read_kreg64(dd, kr_sendbuffererror + i);
1273 if (sbuf[i]) {
1274 any = 1;
1275 qib_write_kreg(dd, kr_sendbuffererror + i, sbuf[i]);
1276 }
1277 }
1278
1279 if (any)
1280 qib_disarm_piobufs_set(dd, sbuf, piobcnt);
1281 }
1282
1283 /* No txe_recover yet, if ever */
1284
1285 /* No decode__errors yet */
1286 static void err_decode(char *msg, size_t len, u64 errs,
1287 const struct qib_hwerror_msgs *msp)
1288 {
1289 u64 these, lmask;
1290 int took, multi, n = 0;
1291
1292 while (msp && msp->mask) {
1293 multi = (msp->mask & (msp->mask - 1));
1294 while (errs & msp->mask) {
1295 these = (errs & msp->mask);
1296 lmask = (these & (these - 1)) ^ these;
1297 if (len) {
1298 if (n++) {
1299 /* separate the strings */
1300 *msg++ = ',';
1301 len--;
1302 }
1303 took = scnprintf(msg, len, "%s", msp->msg);
1304 len -= took;
1305 msg += took;
1306 }
1307 errs &= ~lmask;
1308 if (len && multi) {
1309 /* More than one bit this mask */
1310 int idx = -1;
1311
1312 while (lmask & msp->mask) {
1313 ++idx;
1314 lmask >>= 1;
1315 }
1316 took = scnprintf(msg, len, "_%d", idx);
1317 len -= took;
1318 msg += took;
1319 }
1320 }
1321 ++msp;
1322 }
1323 /* If some bits are left, show in hex. */
1324 if (len && errs)
1325 snprintf(msg, len, "%sMORE:%llX", n ? "," : "",
1326 (unsigned long long) errs);
1327 }
1328
1329 /* only called if r1 set */
1330 static void flush_fifo(struct qib_pportdata *ppd)
1331 {
1332 struct qib_devdata *dd = ppd->dd;
1333 u32 __iomem *piobuf;
1334 u32 bufn;
1335 u32 *hdr;
1336 u64 pbc;
1337 const unsigned hdrwords = 7;
1338 static struct qib_ib_header ibhdr = {
1339 .lrh[0] = cpu_to_be16(0xF000 | QIB_LRH_BTH),
1340 .lrh[1] = IB_LID_PERMISSIVE,
1341 .lrh[2] = cpu_to_be16(hdrwords + SIZE_OF_CRC),
1342 .lrh[3] = IB_LID_PERMISSIVE,
1343 .u.oth.bth[0] = cpu_to_be32(
1344 (IB_OPCODE_UD_SEND_ONLY << 24) | QIB_DEFAULT_P_KEY),
1345 .u.oth.bth[1] = cpu_to_be32(0),
1346 .u.oth.bth[2] = cpu_to_be32(0),
1347 .u.oth.u.ud.deth[0] = cpu_to_be32(0),
1348 .u.oth.u.ud.deth[1] = cpu_to_be32(0),
1349 };
1350
1351 /*
1352 * Send a dummy VL15 packet to flush the launch FIFO.
1353 * This will not actually be sent since the TxeBypassIbc bit is set.
1354 */
1355 pbc = PBC_7322_VL15_SEND |
1356 (((u64)ppd->hw_pidx) << (PBC_PORT_SEL_LSB + 32)) |
1357 (hdrwords + SIZE_OF_CRC);
1358 piobuf = qib_7322_getsendbuf(ppd, pbc, &bufn);
1359 if (!piobuf)
1360 return;
1361 writeq(pbc, piobuf);
1362 hdr = (u32 *) &ibhdr;
1363 if (dd->flags & QIB_PIO_FLUSH_WC) {
1364 qib_flush_wc();
1365 qib_pio_copy(piobuf + 2, hdr, hdrwords - 1);
1366 qib_flush_wc();
1367 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords + 1);
1368 qib_flush_wc();
1369 } else
1370 qib_pio_copy(piobuf + 2, hdr, hdrwords);
1371 qib_sendbuf_done(dd, bufn);
1372 }
1373
1374 /*
1375 * This is called with interrupts disabled and sdma_lock held.
1376 */
1377 static void qib_7322_sdma_sendctrl(struct qib_pportdata *ppd, unsigned op)
1378 {
1379 struct qib_devdata *dd = ppd->dd;
1380 u64 set_sendctrl = 0;
1381 u64 clr_sendctrl = 0;
1382
1383 if (op & QIB_SDMA_SENDCTRL_OP_ENABLE)
1384 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1385 else
1386 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaEnable);
1387
1388 if (op & QIB_SDMA_SENDCTRL_OP_INTENABLE)
1389 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1390 else
1391 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaIntEnable);
1392
1393 if (op & QIB_SDMA_SENDCTRL_OP_HALT)
1394 set_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1395 else
1396 clr_sendctrl |= SYM_MASK(SendCtrl_0, SDmaHalt);
1397
1398 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN)
1399 set_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1400 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1401 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1402 else
1403 clr_sendctrl |= SYM_MASK(SendCtrl_0, TxeBypassIbc) |
1404 SYM_MASK(SendCtrl_0, TxeAbortIbc) |
1405 SYM_MASK(SendCtrl_0, TxeDrainRmFifo);
1406
1407 spin_lock(&dd->sendctrl_lock);
1408
1409 /* If we are draining everything, block sends first */
1410 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1411 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
1412 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1413 qib_write_kreg(dd, kr_scratch, 0);
1414 }
1415
1416 ppd->p_sendctrl |= set_sendctrl;
1417 ppd->p_sendctrl &= ~clr_sendctrl;
1418
1419 if (op & QIB_SDMA_SENDCTRL_OP_CLEANUP)
1420 qib_write_kreg_port(ppd, krp_sendctrl,
1421 ppd->p_sendctrl |
1422 SYM_MASK(SendCtrl_0, SDmaCleanup));
1423 else
1424 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1425 qib_write_kreg(dd, kr_scratch, 0);
1426
1427 if (op & QIB_SDMA_SENDCTRL_OP_DRAIN) {
1428 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
1429 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
1430 qib_write_kreg(dd, kr_scratch, 0);
1431 }
1432
1433 spin_unlock(&dd->sendctrl_lock);
1434
1435 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1)
1436 flush_fifo(ppd);
1437 }
1438
1439 static void qib_7322_sdma_hw_clean_up(struct qib_pportdata *ppd)
1440 {
1441 __qib_sdma_process_event(ppd, qib_sdma_event_e50_hw_cleaned);
1442 }
1443
1444 static void qib_sdma_7322_setlengen(struct qib_pportdata *ppd)
1445 {
1446 /*
1447 * Set SendDmaLenGen and clear and set
1448 * the MSB of the generation count to enable generation checking
1449 * and load the internal generation counter.
1450 */
1451 qib_write_kreg_port(ppd, krp_senddmalengen, ppd->sdma_descq_cnt);
1452 qib_write_kreg_port(ppd, krp_senddmalengen,
1453 ppd->sdma_descq_cnt |
1454 (1ULL << QIB_7322_SendDmaLenGen_0_Generation_MSB));
1455 }
1456
1457 /*
1458 * Must be called with sdma_lock held, or before init finished.
1459 */
1460 static void qib_sdma_update_7322_tail(struct qib_pportdata *ppd, u16 tail)
1461 {
1462 /* Commit writes to memory and advance the tail on the chip */
1463 wmb();
1464 ppd->sdma_descq_tail = tail;
1465 qib_write_kreg_port(ppd, krp_senddmatail, tail);
1466 }
1467
1468 /*
1469 * This is called with interrupts disabled and sdma_lock held.
1470 */
1471 static void qib_7322_sdma_hw_start_up(struct qib_pportdata *ppd)
1472 {
1473 /*
1474 * Drain all FIFOs.
1475 * The hardware doesn't require this but we do it so that verbs
1476 * and user applications don't wait for link active to send stale
1477 * data.
1478 */
1479 sendctrl_7322_mod(ppd, QIB_SENDCTRL_FLUSH);
1480
1481 qib_sdma_7322_setlengen(ppd);
1482 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
1483 ppd->sdma_head_dma[0] = 0;
1484 qib_7322_sdma_sendctrl(ppd,
1485 ppd->sdma_state.current_op | QIB_SDMA_SENDCTRL_OP_CLEANUP);
1486 }
1487
1488 #define DISABLES_SDMA ( \
1489 QIB_E_P_SDMAHALT | \
1490 QIB_E_P_SDMADESCADDRMISALIGN | \
1491 QIB_E_P_SDMAMISSINGDW | \
1492 QIB_E_P_SDMADWEN | \
1493 QIB_E_P_SDMARPYTAG | \
1494 QIB_E_P_SDMA1STDESC | \
1495 QIB_E_P_SDMABASE | \
1496 QIB_E_P_SDMATAILOUTOFBOUND | \
1497 QIB_E_P_SDMAOUTOFBOUND | \
1498 QIB_E_P_SDMAGENMISMATCH)
1499
1500 static void sdma_7322_p_errors(struct qib_pportdata *ppd, u64 errs)
1501 {
1502 unsigned long flags;
1503 struct qib_devdata *dd = ppd->dd;
1504
1505 errs &= QIB_E_P_SDMAERRS;
1506
1507 if (errs & QIB_E_P_SDMAUNEXPDATA)
1508 qib_dev_err(dd, "IB%u:%u SDmaUnexpData\n", dd->unit,
1509 ppd->port);
1510
1511 spin_lock_irqsave(&ppd->sdma_lock, flags);
1512
1513 switch (ppd->sdma_state.current_state) {
1514 case qib_sdma_state_s00_hw_down:
1515 break;
1516
1517 case qib_sdma_state_s10_hw_start_up_wait:
1518 if (errs & QIB_E_P_SDMAHALT)
1519 __qib_sdma_process_event(ppd,
1520 qib_sdma_event_e20_hw_started);
1521 break;
1522
1523 case qib_sdma_state_s20_idle:
1524 break;
1525
1526 case qib_sdma_state_s30_sw_clean_up_wait:
1527 break;
1528
1529 case qib_sdma_state_s40_hw_clean_up_wait:
1530 if (errs & QIB_E_P_SDMAHALT)
1531 __qib_sdma_process_event(ppd,
1532 qib_sdma_event_e50_hw_cleaned);
1533 break;
1534
1535 case qib_sdma_state_s50_hw_halt_wait:
1536 if (errs & QIB_E_P_SDMAHALT)
1537 __qib_sdma_process_event(ppd,
1538 qib_sdma_event_e60_hw_halted);
1539 break;
1540
1541 case qib_sdma_state_s99_running:
1542 __qib_sdma_process_event(ppd, qib_sdma_event_e7322_err_halted);
1543 __qib_sdma_process_event(ppd, qib_sdma_event_e60_hw_halted);
1544 break;
1545 }
1546
1547 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
1548 }
1549
1550 /*
1551 * handle per-device errors (not per-port errors)
1552 */
1553 static noinline void handle_7322_errors(struct qib_devdata *dd)
1554 {
1555 char *msg;
1556 u64 iserr = 0;
1557 u64 errs;
1558 u64 mask;
1559 int log_idx;
1560
1561 qib_stats.sps_errints++;
1562 errs = qib_read_kreg64(dd, kr_errstatus);
1563 if (!errs) {
1564 qib_devinfo(dd->pcidev, "device error interrupt, "
1565 "but no error bits set!\n");
1566 goto done;
1567 }
1568
1569 /* don't report errors that are masked */
1570 errs &= dd->cspec->errormask;
1571 msg = dd->cspec->emsgbuf;
1572
1573 /* do these first, they are most important */
1574 if (errs & QIB_E_HARDWARE) {
1575 *msg = '\0';
1576 qib_7322_handle_hwerrors(dd, msg, sizeof dd->cspec->emsgbuf);
1577 } else
1578 for (log_idx = 0; log_idx < QIB_EEP_LOG_CNT; ++log_idx)
1579 if (errs & dd->eep_st_masks[log_idx].errs_to_log)
1580 qib_inc_eeprom_err(dd, log_idx, 1);
1581
1582 if (errs & QIB_E_SPKTERRS) {
1583 qib_disarm_7322_senderrbufs(dd->pport);
1584 qib_stats.sps_txerrs++;
1585 } else if (errs & QIB_E_INVALIDADDR)
1586 qib_stats.sps_txerrs++;
1587 else if (errs & QIB_E_ARMLAUNCH) {
1588 qib_stats.sps_txerrs++;
1589 qib_disarm_7322_senderrbufs(dd->pport);
1590 }
1591 qib_write_kreg(dd, kr_errclear, errs);
1592
1593 /*
1594 * The ones we mask off are handled specially below
1595 * or above. Also mask SDMADISABLED by default as it
1596 * is too chatty.
1597 */
1598 mask = QIB_E_HARDWARE;
1599 *msg = '\0';
1600
1601 err_decode(msg, sizeof dd->cspec->emsgbuf, errs & ~mask,
1602 qib_7322error_msgs);
1603
1604 /*
1605 * Getting reset is a tragedy for all ports. Mark the device
1606 * _and_ the ports as "offline" in way meaningful to each.
1607 */
1608 if (errs & QIB_E_RESET) {
1609 int pidx;
1610
1611 qib_dev_err(dd, "Got reset, requires re-init "
1612 "(unload and reload driver)\n");
1613 dd->flags &= ~QIB_INITTED; /* needs re-init */
1614 /* mark as having had error */
1615 *dd->devstatusp |= QIB_STATUS_HWERROR;
1616 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1617 if (dd->pport[pidx].link_speed_supported)
1618 *dd->pport[pidx].statusp &= ~QIB_STATUS_IB_CONF;
1619 }
1620
1621 if (*msg && iserr)
1622 qib_dev_err(dd, "%s error\n", msg);
1623
1624 /*
1625 * If there were hdrq or egrfull errors, wake up any processes
1626 * waiting in poll. We used to try to check which contexts had
1627 * the overflow, but given the cost of that and the chip reads
1628 * to support it, it's better to just wake everybody up if we
1629 * get an overflow; waiters can poll again if it's not them.
1630 */
1631 if (errs & (ERR_MASK(RcvEgrFullErr) | ERR_MASK(RcvHdrFullErr))) {
1632 qib_handle_urcv(dd, ~0U);
1633 if (errs & ERR_MASK(RcvEgrFullErr))
1634 qib_stats.sps_buffull++;
1635 else
1636 qib_stats.sps_hdrfull++;
1637 }
1638
1639 done:
1640 return;
1641 }
1642
1643 static void reenable_chase(unsigned long opaque)
1644 {
1645 struct qib_pportdata *ppd = (struct qib_pportdata *)opaque;
1646
1647 ppd->cpspec->chase_timer.expires = 0;
1648 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1649 QLOGIC_IB_IBCC_LINKINITCMD_POLL);
1650 }
1651
1652 static void disable_chase(struct qib_pportdata *ppd, u64 tnow, u8 ibclt)
1653 {
1654 ppd->cpspec->chase_end = 0;
1655
1656 if (!qib_chase)
1657 return;
1658
1659 qib_set_ib_7322_lstate(ppd, QLOGIC_IB_IBCC_LINKCMD_DOWN,
1660 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1661 ppd->cpspec->chase_timer.expires = jiffies + QIB_CHASE_DIS_TIME;
1662 add_timer(&ppd->cpspec->chase_timer);
1663 }
1664
1665 static void handle_serdes_issues(struct qib_pportdata *ppd, u64 ibcst)
1666 {
1667 u8 ibclt;
1668 u64 tnow;
1669
1670 ibclt = (u8)SYM_FIELD(ibcst, IBCStatusA_0, LinkTrainingState);
1671
1672 /*
1673 * Detect and handle the state chase issue, where we can
1674 * get stuck if we are unlucky on timing on both sides of
1675 * the link. If we are, we disable, set a timer, and
1676 * then re-enable.
1677 */
1678 switch (ibclt) {
1679 case IB_7322_LT_STATE_CFGRCVFCFG:
1680 case IB_7322_LT_STATE_CFGWAITRMT:
1681 case IB_7322_LT_STATE_TXREVLANES:
1682 case IB_7322_LT_STATE_CFGENH:
1683 tnow = get_jiffies_64();
1684 if (ppd->cpspec->chase_end &&
1685 time_after64(tnow, ppd->cpspec->chase_end))
1686 disable_chase(ppd, tnow, ibclt);
1687 else if (!ppd->cpspec->chase_end)
1688 ppd->cpspec->chase_end = tnow + QIB_CHASE_TIME;
1689 break;
1690 default:
1691 ppd->cpspec->chase_end = 0;
1692 break;
1693 }
1694
1695 if (ibclt == IB_7322_LT_STATE_CFGTEST &&
1696 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR))) {
1697 force_h1(ppd);
1698 ppd->cpspec->qdr_reforce = 1;
1699 if (!ppd->dd->cspec->r1)
1700 serdes_7322_los_enable(ppd, 0);
1701 } else if (ppd->cpspec->qdr_reforce &&
1702 (ibcst & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) &&
1703 (ibclt == IB_7322_LT_STATE_CFGENH ||
1704 ibclt == IB_7322_LT_STATE_CFGIDLE ||
1705 ibclt == IB_7322_LT_STATE_LINKUP))
1706 force_h1(ppd);
1707
1708 if ((IS_QMH(ppd->dd) || IS_QME(ppd->dd)) &&
1709 ppd->link_speed_enabled == QIB_IB_QDR &&
1710 (ibclt == IB_7322_LT_STATE_CFGTEST ||
1711 ibclt == IB_7322_LT_STATE_CFGENH ||
1712 (ibclt >= IB_7322_LT_STATE_POLLACTIVE &&
1713 ibclt <= IB_7322_LT_STATE_SLEEPQUIET)))
1714 adj_tx_serdes(ppd);
1715
1716 if (ibclt != IB_7322_LT_STATE_LINKUP) {
1717 u8 ltstate = qib_7322_phys_portstate(ibcst);
1718 u8 pibclt = (u8)SYM_FIELD(ppd->lastibcstat, IBCStatusA_0,
1719 LinkTrainingState);
1720 if (!ppd->dd->cspec->r1 &&
1721 pibclt == IB_7322_LT_STATE_LINKUP &&
1722 ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1723 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1724 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1725 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1726 /* If the link went down (but no into recovery,
1727 * turn LOS back on */
1728 serdes_7322_los_enable(ppd, 1);
1729 if (!ppd->cpspec->qdr_dfe_on &&
1730 ibclt <= IB_7322_LT_STATE_SLEEPQUIET) {
1731 ppd->cpspec->qdr_dfe_on = 1;
1732 ppd->cpspec->qdr_dfe_time = 0;
1733 /* On link down, reenable QDR adaptation */
1734 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
1735 ppd->dd->cspec->r1 ?
1736 QDR_STATIC_ADAPT_DOWN_R1 :
1737 QDR_STATIC_ADAPT_DOWN);
1738 printk(KERN_INFO QIB_DRV_NAME
1739 " IB%u:%u re-enabled QDR adaptation "
1740 "ibclt %x\n", ppd->dd->unit, ppd->port, ibclt);
1741 }
1742 }
1743 }
1744
1745 static int qib_7322_set_ib_cfg(struct qib_pportdata *, int, u32);
1746
1747 /*
1748 * This is per-pport error handling.
1749 * will likely get it's own MSIx interrupt (one for each port,
1750 * although just a single handler).
1751 */
1752 static noinline void handle_7322_p_errors(struct qib_pportdata *ppd)
1753 {
1754 char *msg;
1755 u64 ignore_this_time = 0, iserr = 0, errs, fmask;
1756 struct qib_devdata *dd = ppd->dd;
1757
1758 /* do this as soon as possible */
1759 fmask = qib_read_kreg64(dd, kr_act_fmask);
1760 if (!fmask)
1761 check_7322_rxe_status(ppd);
1762
1763 errs = qib_read_kreg_port(ppd, krp_errstatus);
1764 if (!errs)
1765 qib_devinfo(dd->pcidev,
1766 "Port%d error interrupt, but no error bits set!\n",
1767 ppd->port);
1768 if (!fmask)
1769 errs &= ~QIB_E_P_IBSTATUSCHANGED;
1770 if (!errs)
1771 goto done;
1772
1773 msg = ppd->cpspec->epmsgbuf;
1774 *msg = '\0';
1775
1776 if (errs & ~QIB_E_P_BITSEXTANT) {
1777 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1778 errs & ~QIB_E_P_BITSEXTANT, qib_7322p_error_msgs);
1779 if (!*msg)
1780 snprintf(msg, sizeof ppd->cpspec->epmsgbuf,
1781 "no others");
1782 qib_dev_porterr(dd, ppd->port, "error interrupt with unknown"
1783 " errors 0x%016Lx set (and %s)\n",
1784 (errs & ~QIB_E_P_BITSEXTANT), msg);
1785 *msg = '\0';
1786 }
1787
1788 if (errs & QIB_E_P_SHDR) {
1789 u64 symptom;
1790
1791 /* determine cause, then write to clear */
1792 symptom = qib_read_kreg_port(ppd, krp_sendhdrsymptom);
1793 qib_write_kreg_port(ppd, krp_sendhdrsymptom, 0);
1794 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, symptom,
1795 hdrchk_msgs);
1796 *msg = '\0';
1797 /* senderrbuf cleared in SPKTERRS below */
1798 }
1799
1800 if (errs & QIB_E_P_SPKTERRS) {
1801 if ((errs & QIB_E_P_LINK_PKTERRS) &&
1802 !(ppd->lflags & QIBL_LINKACTIVE)) {
1803 /*
1804 * This can happen when trying to bring the link
1805 * up, but the IB link changes state at the "wrong"
1806 * time. The IB logic then complains that the packet
1807 * isn't valid. We don't want to confuse people, so
1808 * we just don't print them, except at debug
1809 */
1810 err_decode(msg, sizeof ppd->cpspec->epmsgbuf,
1811 (errs & QIB_E_P_LINK_PKTERRS),
1812 qib_7322p_error_msgs);
1813 *msg = '\0';
1814 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1815 }
1816 qib_disarm_7322_senderrbufs(ppd);
1817 } else if ((errs & QIB_E_P_LINK_PKTERRS) &&
1818 !(ppd->lflags & QIBL_LINKACTIVE)) {
1819 /*
1820 * This can happen when SMA is trying to bring the link
1821 * up, but the IB link changes state at the "wrong" time.
1822 * The IB logic then complains that the packet isn't
1823 * valid. We don't want to confuse people, so we just
1824 * don't print them, except at debug
1825 */
1826 err_decode(msg, sizeof ppd->cpspec->epmsgbuf, errs,
1827 qib_7322p_error_msgs);
1828 ignore_this_time = errs & QIB_E_P_LINK_PKTERRS;
1829 *msg = '\0';
1830 }
1831
1832 qib_write_kreg_port(ppd, krp_errclear, errs);
1833
1834 errs &= ~ignore_this_time;
1835 if (!errs)
1836 goto done;
1837
1838 if (errs & QIB_E_P_RPKTERRS)
1839 qib_stats.sps_rcverrs++;
1840 if (errs & QIB_E_P_SPKTERRS)
1841 qib_stats.sps_txerrs++;
1842
1843 iserr = errs & ~(QIB_E_P_RPKTERRS | QIB_E_P_PKTERRS);
1844
1845 if (errs & QIB_E_P_SDMAERRS)
1846 sdma_7322_p_errors(ppd, errs);
1847
1848 if (errs & QIB_E_P_IBSTATUSCHANGED) {
1849 u64 ibcs;
1850 u8 ltstate;
1851
1852 ibcs = qib_read_kreg_port(ppd, krp_ibcstatus_a);
1853 ltstate = qib_7322_phys_portstate(ibcs);
1854
1855 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
1856 handle_serdes_issues(ppd, ibcs);
1857 if (!(ppd->cpspec->ibcctrl_a &
1858 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn))) {
1859 /*
1860 * We got our interrupt, so init code should be
1861 * happy and not try alternatives. Now squelch
1862 * other "chatter" from link-negotiation (pre Init)
1863 */
1864 ppd->cpspec->ibcctrl_a |=
1865 SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
1866 qib_write_kreg_port(ppd, krp_ibcctrl_a,
1867 ppd->cpspec->ibcctrl_a);
1868 }
1869
1870 /* Update our picture of width and speed from chip */
1871 ppd->link_width_active =
1872 (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) ?
1873 IB_WIDTH_4X : IB_WIDTH_1X;
1874 ppd->link_speed_active = (ibcs & SYM_MASK(IBCStatusA_0,
1875 LinkSpeedQDR)) ? QIB_IB_QDR : (ibcs &
1876 SYM_MASK(IBCStatusA_0, LinkSpeedActive)) ?
1877 QIB_IB_DDR : QIB_IB_SDR;
1878
1879 if ((ppd->lflags & QIBL_IB_LINK_DISABLED) && ltstate !=
1880 IB_PHYSPORTSTATE_DISABLED)
1881 qib_set_ib_7322_lstate(ppd, 0,
1882 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
1883 else
1884 /*
1885 * Since going into a recovery state causes the link
1886 * state to go down and since recovery is transitory,
1887 * it is better if we "miss" ever seeing the link
1888 * training state go into recovery (i.e., ignore this
1889 * transition for link state special handling purposes)
1890 * without updating lastibcstat.
1891 */
1892 if (ltstate != IB_PHYSPORTSTATE_LINK_ERR_RECOVER &&
1893 ltstate != IB_PHYSPORTSTATE_RECOVERY_RETRAIN &&
1894 ltstate != IB_PHYSPORTSTATE_RECOVERY_WAITRMT &&
1895 ltstate != IB_PHYSPORTSTATE_RECOVERY_IDLE)
1896 qib_handle_e_ibstatuschanged(ppd, ibcs);
1897 }
1898 if (*msg && iserr)
1899 qib_dev_porterr(dd, ppd->port, "%s error\n", msg);
1900
1901 if (ppd->state_wanted & ppd->lflags)
1902 wake_up_interruptible(&ppd->state_wait);
1903 done:
1904 return;
1905 }
1906
1907 /* enable/disable chip from delivering interrupts */
1908 static void qib_7322_set_intr_state(struct qib_devdata *dd, u32 enable)
1909 {
1910 if (enable) {
1911 if (dd->flags & QIB_BADINTR)
1912 return;
1913 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask);
1914 /* cause any pending enabled interrupts to be re-delivered */
1915 qib_write_kreg(dd, kr_intclear, 0ULL);
1916 if (dd->cspec->num_msix_entries) {
1917 /* and same for MSIx */
1918 u64 val = qib_read_kreg64(dd, kr_intgranted);
1919 if (val)
1920 qib_write_kreg(dd, kr_intgranted, val);
1921 }
1922 } else
1923 qib_write_kreg(dd, kr_intmask, 0ULL);
1924 }
1925
1926 /*
1927 * Try to cleanup as much as possible for anything that might have gone
1928 * wrong while in freeze mode, such as pio buffers being written by user
1929 * processes (causing armlaunch), send errors due to going into freeze mode,
1930 * etc., and try to avoid causing extra interrupts while doing so.
1931 * Forcibly update the in-memory pioavail register copies after cleanup
1932 * because the chip won't do it while in freeze mode (the register values
1933 * themselves are kept correct).
1934 * Make sure that we don't lose any important interrupts by using the chip
1935 * feature that says that writing 0 to a bit in *clear that is set in
1936 * *status will cause an interrupt to be generated again (if allowed by
1937 * the *mask value).
1938 * This is in chip-specific code because of all of the register accesses,
1939 * even though the details are similar on most chips.
1940 */
1941 static void qib_7322_clear_freeze(struct qib_devdata *dd)
1942 {
1943 int pidx;
1944
1945 /* disable error interrupts, to avoid confusion */
1946 qib_write_kreg(dd, kr_errmask, 0ULL);
1947
1948 for (pidx = 0; pidx < dd->num_pports; ++pidx)
1949 if (dd->pport[pidx].link_speed_supported)
1950 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
1951 0ULL);
1952
1953 /* also disable interrupts; errormask is sometimes overwriten */
1954 qib_7322_set_intr_state(dd, 0);
1955
1956 /* clear the freeze, and be sure chip saw it */
1957 qib_write_kreg(dd, kr_control, dd->control);
1958 qib_read_kreg32(dd, kr_scratch);
1959
1960 /*
1961 * Force new interrupt if any hwerr, error or interrupt bits are
1962 * still set, and clear "safe" send packet errors related to freeze
1963 * and cancelling sends. Re-enable error interrupts before possible
1964 * force of re-interrupt on pending interrupts.
1965 */
1966 qib_write_kreg(dd, kr_hwerrclear, 0ULL);
1967 qib_write_kreg(dd, kr_errclear, E_SPKT_ERRS_IGNORE);
1968 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
1969 /* We need to purge per-port errs and reset mask, too */
1970 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
1971 if (!dd->pport[pidx].link_speed_supported)
1972 continue;
1973 qib_write_kreg_port(dd->pport + pidx, krp_errclear, ~0Ull);
1974 qib_write_kreg_port(dd->pport + pidx, krp_errmask, ~0Ull);
1975 }
1976 qib_7322_set_intr_state(dd, 1);
1977 }
1978
1979 /* no error handling to speak of */
1980 /**
1981 * qib_7322_handle_hwerrors - display hardware errors.
1982 * @dd: the qlogic_ib device
1983 * @msg: the output buffer
1984 * @msgl: the size of the output buffer
1985 *
1986 * Use same msg buffer as regular errors to avoid excessive stack
1987 * use. Most hardware errors are catastrophic, but for right now,
1988 * we'll print them and continue. We reuse the same message buffer as
1989 * qib_handle_errors() to avoid excessive stack usage.
1990 */
1991 static void qib_7322_handle_hwerrors(struct qib_devdata *dd, char *msg,
1992 size_t msgl)
1993 {
1994 u64 hwerrs;
1995 u32 ctrl;
1996 int isfatal = 0;
1997
1998 hwerrs = qib_read_kreg64(dd, kr_hwerrstatus);
1999 if (!hwerrs)
2000 goto bail;
2001 if (hwerrs == ~0ULL) {
2002 qib_dev_err(dd, "Read of hardware error status failed "
2003 "(all bits set); ignoring\n");
2004 goto bail;
2005 }
2006 qib_stats.sps_hwerrs++;
2007
2008 /* Always clear the error status register, except BIST fail */
2009 qib_write_kreg(dd, kr_hwerrclear, hwerrs &
2010 ~HWE_MASK(PowerOnBISTFailed));
2011
2012 hwerrs &= dd->cspec->hwerrmask;
2013
2014 /* no EEPROM logging, yet */
2015
2016 if (hwerrs)
2017 qib_devinfo(dd->pcidev, "Hardware error: hwerr=0x%llx "
2018 "(cleared)\n", (unsigned long long) hwerrs);
2019
2020 ctrl = qib_read_kreg32(dd, kr_control);
2021 if ((ctrl & SYM_MASK(Control, FreezeMode)) && !dd->diag_client) {
2022 /*
2023 * No recovery yet...
2024 */
2025 if ((hwerrs & ~HWE_MASK(LATriggered)) ||
2026 dd->cspec->stay_in_freeze) {
2027 /*
2028 * If any set that we aren't ignoring only make the
2029 * complaint once, in case it's stuck or recurring,
2030 * and we get here multiple times
2031 * Force link down, so switch knows, and
2032 * LEDs are turned off.
2033 */
2034 if (dd->flags & QIB_INITTED)
2035 isfatal = 1;
2036 } else
2037 qib_7322_clear_freeze(dd);
2038 }
2039
2040 if (hwerrs & HWE_MASK(PowerOnBISTFailed)) {
2041 isfatal = 1;
2042 strlcpy(msg, "[Memory BIST test failed, "
2043 "InfiniPath hardware unusable]", msgl);
2044 /* ignore from now on, so disable until driver reloaded */
2045 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed);
2046 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2047 }
2048
2049 err_decode(msg, msgl, hwerrs, qib_7322_hwerror_msgs);
2050
2051 /* Ignore esoteric PLL failures et al. */
2052
2053 qib_dev_err(dd, "%s hardware error\n", msg);
2054
2055 if (isfatal && !dd->diag_client) {
2056 qib_dev_err(dd, "Fatal Hardware Error, no longer"
2057 " usable, SN %.16s\n", dd->serial);
2058 /*
2059 * for /sys status file and user programs to print; if no
2060 * trailing brace is copied, we'll know it was truncated.
2061 */
2062 if (dd->freezemsg)
2063 snprintf(dd->freezemsg, dd->freezelen,
2064 "{%s}", msg);
2065 qib_disable_after_error(dd);
2066 }
2067 bail:;
2068 }
2069
2070 /**
2071 * qib_7322_init_hwerrors - enable hardware errors
2072 * @dd: the qlogic_ib device
2073 *
2074 * now that we have finished initializing everything that might reasonably
2075 * cause a hardware error, and cleared those errors bits as they occur,
2076 * we can enable hardware errors in the mask (potentially enabling
2077 * freeze mode), and enable hardware errors as errors (along with
2078 * everything else) in errormask
2079 */
2080 static void qib_7322_init_hwerrors(struct qib_devdata *dd)
2081 {
2082 int pidx;
2083 u64 extsval;
2084
2085 extsval = qib_read_kreg64(dd, kr_extstatus);
2086 if (!(extsval & (QIB_EXTS_MEMBIST_DISABLED |
2087 QIB_EXTS_MEMBIST_ENDTEST)))
2088 qib_dev_err(dd, "MemBIST did not complete!\n");
2089
2090 /* never clear BIST failure, so reported on each driver load */
2091 qib_write_kreg(dd, kr_hwerrclear, ~HWE_MASK(PowerOnBISTFailed));
2092 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
2093
2094 /* clear all */
2095 qib_write_kreg(dd, kr_errclear, ~0ULL);
2096 /* enable errors that are masked, at least this first time. */
2097 qib_write_kreg(dd, kr_errmask, ~0ULL);
2098 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask);
2099 for (pidx = 0; pidx < dd->num_pports; ++pidx)
2100 if (dd->pport[pidx].link_speed_supported)
2101 qib_write_kreg_port(dd->pport + pidx, krp_errmask,
2102 ~0ULL);
2103 }
2104
2105 /*
2106 * Disable and enable the armlaunch error. Used for PIO bandwidth testing
2107 * on chips that are count-based, rather than trigger-based. There is no
2108 * reference counting, but that's also fine, given the intended use.
2109 * Only chip-specific because it's all register accesses
2110 */
2111 static void qib_set_7322_armlaunch(struct qib_devdata *dd, u32 enable)
2112 {
2113 if (enable) {
2114 qib_write_kreg(dd, kr_errclear, QIB_E_SPIOARMLAUNCH);
2115 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH;
2116 } else
2117 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH;
2118 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask);
2119 }
2120
2121 /*
2122 * Formerly took parameter <which> in pre-shifted,
2123 * pre-merged form with LinkCmd and LinkInitCmd
2124 * together, and assuming the zero was NOP.
2125 */
2126 static void qib_set_ib_7322_lstate(struct qib_pportdata *ppd, u16 linkcmd,
2127 u16 linitcmd)
2128 {
2129 u64 mod_wd;
2130 struct qib_devdata *dd = ppd->dd;
2131 unsigned long flags;
2132
2133 if (linitcmd == QLOGIC_IB_IBCC_LINKINITCMD_DISABLE) {
2134 /*
2135 * If we are told to disable, note that so link-recovery
2136 * code does not attempt to bring us back up.
2137 * Also reset everything that we can, so we start
2138 * completely clean when re-enabled (before we
2139 * actually issue the disable to the IBC)
2140 */
2141 qib_7322_mini_pcs_reset(ppd);
2142 spin_lock_irqsave(&ppd->lflags_lock, flags);
2143 ppd->lflags |= QIBL_IB_LINK_DISABLED;
2144 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2145 } else if (linitcmd || linkcmd == QLOGIC_IB_IBCC_LINKCMD_DOWN) {
2146 /*
2147 * Any other linkinitcmd will lead to LINKDOWN and then
2148 * to INIT (if all is well), so clear flag to let
2149 * link-recovery code attempt to bring us back up.
2150 */
2151 spin_lock_irqsave(&ppd->lflags_lock, flags);
2152 ppd->lflags &= ~QIBL_IB_LINK_DISABLED;
2153 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2154 /*
2155 * Clear status change interrupt reduction so the
2156 * new state is seen.
2157 */
2158 ppd->cpspec->ibcctrl_a &=
2159 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
2160 }
2161
2162 mod_wd = (linkcmd << IBA7322_IBCC_LINKCMD_SHIFT) |
2163 (linitcmd << QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2164
2165 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a |
2166 mod_wd);
2167 /* write to chip to prevent back-to-back writes of ibc reg */
2168 qib_write_kreg(dd, kr_scratch, 0);
2169
2170 }
2171
2172 /*
2173 * The total RCV buffer memory is 64KB, used for both ports, and is
2174 * in units of 64 bytes (same as IB flow control credit unit).
2175 * The consumedVL unit in the same registers are in 32 byte units!
2176 * So, a VL15 packet needs 4.50 IB credits, and 9 rx buffer chunks,
2177 * and we can therefore allocate just 9 IB credits for 2 VL15 packets
2178 * in krp_rxcreditvl15, rather than 10.
2179 */
2180 #define RCV_BUF_UNITSZ 64
2181 #define NUM_RCV_BUF_UNITS(dd) ((64 * 1024) / (RCV_BUF_UNITSZ * dd->num_pports))
2182
2183 static void set_vls(struct qib_pportdata *ppd)
2184 {
2185 int i, numvls, totcred, cred_vl, vl0extra;
2186 struct qib_devdata *dd = ppd->dd;
2187 u64 val;
2188
2189 numvls = qib_num_vls(ppd->vls_operational);
2190
2191 /*
2192 * Set up per-VL credits. Below is kluge based on these assumptions:
2193 * 1) port is disabled at the time early_init is called.
2194 * 2) give VL15 17 credits, for two max-plausible packets.
2195 * 3) Give VL0-N the rest, with any rounding excess used for VL0
2196 */
2197 /* 2 VL15 packets @ 288 bytes each (including IB headers) */
2198 totcred = NUM_RCV_BUF_UNITS(dd);
2199 cred_vl = (2 * 288 + RCV_BUF_UNITSZ - 1) / RCV_BUF_UNITSZ;
2200 totcred -= cred_vl;
2201 qib_write_kreg_port(ppd, krp_rxcreditvl15, (u64) cred_vl);
2202 cred_vl = totcred / numvls;
2203 vl0extra = totcred - cred_vl * numvls;
2204 qib_write_kreg_port(ppd, krp_rxcreditvl0, cred_vl + vl0extra);
2205 for (i = 1; i < numvls; i++)
2206 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, cred_vl);
2207 for (; i < 8; i++) /* no buffer space for other VLs */
2208 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
2209
2210 /* Notify IBC that credits need to be recalculated */
2211 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
2212 val |= SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2213 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2214 qib_write_kreg(dd, kr_scratch, 0ULL);
2215 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, CREDIT_CHANGE);
2216 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
2217
2218 for (i = 0; i < numvls; i++)
2219 val = qib_read_kreg_port(ppd, krp_rxcreditvl0 + i);
2220 val = qib_read_kreg_port(ppd, krp_rxcreditvl15);
2221
2222 /* Change the number of operational VLs */
2223 ppd->cpspec->ibcctrl_a = (ppd->cpspec->ibcctrl_a &
2224 ~SYM_MASK(IBCCtrlA_0, NumVLane)) |
2225 ((u64)(numvls - 1) << SYM_LSB(IBCCtrlA_0, NumVLane));
2226 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2227 qib_write_kreg(dd, kr_scratch, 0ULL);
2228 }
2229
2230 /*
2231 * The code that deals with actual SerDes is in serdes_7322_init().
2232 * Compared to the code for iba7220, it is minimal.
2233 */
2234 static int serdes_7322_init(struct qib_pportdata *ppd);
2235
2236 /**
2237 * qib_7322_bringup_serdes - bring up the serdes
2238 * @ppd: physical port on the qlogic_ib device
2239 */
2240 static int qib_7322_bringup_serdes(struct qib_pportdata *ppd)
2241 {
2242 struct qib_devdata *dd = ppd->dd;
2243 u64 val, guid, ibc;
2244 unsigned long flags;
2245 int ret = 0;
2246
2247 /*
2248 * SerDes model not in Pd, but still need to
2249 * set up much of IBCCtrl and IBCDDRCtrl; move elsewhere
2250 * eventually.
2251 */
2252 /* Put IBC in reset, sends disabled (should be in reset already) */
2253 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2254 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
2255 qib_write_kreg(dd, kr_scratch, 0ULL);
2256
2257 if (qib_compat_ddr_negotiate) {
2258 ppd->cpspec->ibdeltainprog = 1;
2259 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
2260 crp_ibsymbolerr);
2261 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
2262 crp_iblinkerrrecov);
2263 }
2264
2265 /* flowcontrolwatermark is in units of KBytes */
2266 ibc = 0x5ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlWaterMark);
2267 /*
2268 * Flow control is sent this often, even if no changes in
2269 * buffer space occur. Units are 128ns for this chip.
2270 * Set to 3usec.
2271 */
2272 ibc |= 24ULL << SYM_LSB(IBCCtrlA_0, FlowCtrlPeriod);
2273 /* max error tolerance */
2274 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
2275 /* IB credit flow control. */
2276 ibc |= 0xfULL << SYM_LSB(IBCCtrlA_0, OverrunThreshold);
2277 /*
2278 * set initial max size pkt IBC will send, including ICRC; it's the
2279 * PIO buffer size in dwords, less 1; also see qib_set_mtu()
2280 */
2281 ibc |= ((u64)(ppd->ibmaxlen >> 2) + 1) <<
2282 SYM_LSB(IBCCtrlA_0, MaxPktLen);
2283 ppd->cpspec->ibcctrl_a = ibc; /* without linkcmd or linkinitcmd! */
2284
2285 /* initially come up waiting for TS1, without sending anything. */
2286 val = ppd->cpspec->ibcctrl_a | (QLOGIC_IB_IBCC_LINKINITCMD_DISABLE <<
2287 QLOGIC_IB_IBCC_LINKINITCMD_SHIFT);
2288
2289 /*
2290 * Reset the PCS interface to the serdes (and also ibc, which is still
2291 * in reset from above). Writes new value of ibcctrl_a as last step.
2292 */
2293 qib_7322_mini_pcs_reset(ppd);
2294 qib_write_kreg(dd, kr_scratch, 0ULL);
2295
2296 if (!ppd->cpspec->ibcctrl_b) {
2297 unsigned lse = ppd->link_speed_enabled;
2298
2299 /*
2300 * Not on re-init after reset, establish shadow
2301 * and force initial config.
2302 */
2303 ppd->cpspec->ibcctrl_b = qib_read_kreg_port(ppd,
2304 krp_ibcctrl_b);
2305 ppd->cpspec->ibcctrl_b &= ~(IBA7322_IBC_SPEED_QDR |
2306 IBA7322_IBC_SPEED_DDR |
2307 IBA7322_IBC_SPEED_SDR |
2308 IBA7322_IBC_WIDTH_AUTONEG |
2309 SYM_MASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED));
2310 if (lse & (lse - 1)) /* Muliple speeds enabled */
2311 ppd->cpspec->ibcctrl_b |=
2312 (lse << IBA7322_IBC_SPEED_LSB) |
2313 IBA7322_IBC_IBTA_1_2_MASK |
2314 IBA7322_IBC_MAX_SPEED_MASK;
2315 else
2316 ppd->cpspec->ibcctrl_b |= (lse == QIB_IB_QDR) ?
2317 IBA7322_IBC_SPEED_QDR |
2318 IBA7322_IBC_IBTA_1_2_MASK :
2319 (lse == QIB_IB_DDR) ?
2320 IBA7322_IBC_SPEED_DDR :
2321 IBA7322_IBC_SPEED_SDR;
2322 if ((ppd->link_width_enabled & (IB_WIDTH_1X | IB_WIDTH_4X)) ==
2323 (IB_WIDTH_1X | IB_WIDTH_4X))
2324 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_WIDTH_AUTONEG;
2325 else
2326 ppd->cpspec->ibcctrl_b |=
2327 ppd->link_width_enabled == IB_WIDTH_4X ?
2328 IBA7322_IBC_WIDTH_4X_ONLY :
2329 IBA7322_IBC_WIDTH_1X_ONLY;
2330
2331 /* always enable these on driver reload, not sticky */
2332 ppd->cpspec->ibcctrl_b |= (IBA7322_IBC_RXPOL_MASK |
2333 IBA7322_IBC_HRTBT_MASK);
2334 }
2335 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
2336
2337 /* setup so we have more time at CFGTEST to change H1 */
2338 val = qib_read_kreg_port(ppd, krp_ibcctrl_c);
2339 val &= ~SYM_MASK(IBCCtrlC_0, IB_FRONT_PORCH);
2340 val |= 0xfULL << SYM_LSB(IBCCtrlC_0, IB_FRONT_PORCH);
2341 qib_write_kreg_port(ppd, krp_ibcctrl_c, val);
2342
2343 serdes_7322_init(ppd);
2344
2345 guid = be64_to_cpu(ppd->guid);
2346 if (!guid) {
2347 if (dd->base_guid)
2348 guid = be64_to_cpu(dd->base_guid) + ppd->port - 1;
2349 ppd->guid = cpu_to_be64(guid);
2350 }
2351
2352 qib_write_kreg_port(ppd, krp_hrtbt_guid, guid);
2353 /* write to chip to prevent back-to-back writes of ibc reg */
2354 qib_write_kreg(dd, kr_scratch, 0);
2355
2356 /* Enable port */
2357 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0, IBLinkEn);
2358 set_vls(ppd);
2359
2360 /* be paranoid against later code motion, etc. */
2361 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
2362 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvIBPortEnable);
2363 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
2364 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
2365
2366 /* Hold the link state machine for mezz boards */
2367 if (IS_QMH(dd) || IS_QME(dd))
2368 qib_set_ib_7322_lstate(ppd, 0,
2369 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2370
2371 /* Also enable IBSTATUSCHG interrupt. */
2372 val = qib_read_kreg_port(ppd, krp_errmask);
2373 qib_write_kreg_port(ppd, krp_errmask,
2374 val | ERR_MASK_N(IBStatusChanged));
2375
2376 /* Always zero until we start messing with SerDes for real */
2377 return ret;
2378 }
2379
2380 /**
2381 * qib_7322_quiet_serdes - set serdes to txidle
2382 * @dd: the qlogic_ib device
2383 * Called when driver is being unloaded
2384 */
2385 static void qib_7322_mini_quiet_serdes(struct qib_pportdata *ppd)
2386 {
2387 u64 val;
2388 unsigned long flags;
2389
2390 qib_set_ib_7322_lstate(ppd, 0, QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
2391
2392 spin_lock_irqsave(&ppd->lflags_lock, flags);
2393 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
2394 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
2395 wake_up(&ppd->cpspec->autoneg_wait);
2396 cancel_delayed_work_sync(&ppd->cpspec->autoneg_work);
2397 if (ppd->dd->cspec->r1)
2398 cancel_delayed_work_sync(&ppd->cpspec->ipg_work);
2399
2400 ppd->cpspec->chase_end = 0;
2401 if (ppd->cpspec->chase_timer.data) /* if initted */
2402 del_timer_sync(&ppd->cpspec->chase_timer);
2403
2404 /*
2405 * Despite the name, actually disables IBC as well. Do it when
2406 * we are as sure as possible that no more packets can be
2407 * received, following the down and the PCS reset.
2408 * The actual disabling happens in qib_7322_mini_pci_reset(),
2409 * along with the PCS being reset.
2410 */
2411 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, IBLinkEn);
2412 qib_7322_mini_pcs_reset(ppd);
2413
2414 /*
2415 * Update the adjusted counters so the adjustment persists
2416 * across driver reload.
2417 */
2418 if (ppd->cpspec->ibsymdelta || ppd->cpspec->iblnkerrdelta ||
2419 ppd->cpspec->ibdeltainprog || ppd->cpspec->iblnkdowndelta) {
2420 struct qib_devdata *dd = ppd->dd;
2421 u64 diagc;
2422
2423 /* enable counter writes */
2424 diagc = qib_read_kreg64(dd, kr_hwdiagctrl);
2425 qib_write_kreg(dd, kr_hwdiagctrl,
2426 diagc | SYM_MASK(HwDiagCtrl, CounterWrEnable));
2427
2428 if (ppd->cpspec->ibsymdelta || ppd->cpspec->ibdeltainprog) {
2429 val = read_7322_creg32_port(ppd, crp_ibsymbolerr);
2430 if (ppd->cpspec->ibdeltainprog)
2431 val -= val - ppd->cpspec->ibsymsnap;
2432 val -= ppd->cpspec->ibsymdelta;
2433 write_7322_creg_port(ppd, crp_ibsymbolerr, val);
2434 }
2435 if (ppd->cpspec->iblnkerrdelta || ppd->cpspec->ibdeltainprog) {
2436 val = read_7322_creg32_port(ppd, crp_iblinkerrrecov);
2437 if (ppd->cpspec->ibdeltainprog)
2438 val -= val - ppd->cpspec->iblnkerrsnap;
2439 val -= ppd->cpspec->iblnkerrdelta;
2440 write_7322_creg_port(ppd, crp_iblinkerrrecov, val);
2441 }
2442 if (ppd->cpspec->iblnkdowndelta) {
2443 val = read_7322_creg32_port(ppd, crp_iblinkdown);
2444 val += ppd->cpspec->iblnkdowndelta;
2445 write_7322_creg_port(ppd, crp_iblinkdown, val);
2446 }
2447 /*
2448 * No need to save ibmalfdelta since IB perfcounters
2449 * are cleared on driver reload.
2450 */
2451
2452 /* and disable counter writes */
2453 qib_write_kreg(dd, kr_hwdiagctrl, diagc);
2454 }
2455 }
2456
2457 /**
2458 * qib_setup_7322_setextled - set the state of the two external LEDs
2459 * @ppd: physical port on the qlogic_ib device
2460 * @on: whether the link is up or not
2461 *
2462 * The exact combo of LEDs if on is true is determined by looking
2463 * at the ibcstatus.
2464 *
2465 * These LEDs indicate the physical and logical state of IB link.
2466 * For this chip (at least with recommended board pinouts), LED1
2467 * is Yellow (logical state) and LED2 is Green (physical state),
2468 *
2469 * Note: We try to match the Mellanox HCA LED behavior as best
2470 * we can. Green indicates physical link state is OK (something is
2471 * plugged in, and we can train).
2472 * Amber indicates the link is logically up (ACTIVE).
2473 * Mellanox further blinks the amber LED to indicate data packet
2474 * activity, but we have no hardware support for that, so it would
2475 * require waking up every 10-20 msecs and checking the counters
2476 * on the chip, and then turning the LED off if appropriate. That's
2477 * visible overhead, so not something we will do.
2478 */
2479 static void qib_setup_7322_setextled(struct qib_pportdata *ppd, u32 on)
2480 {
2481 struct qib_devdata *dd = ppd->dd;
2482 u64 extctl, ledblink = 0, val;
2483 unsigned long flags;
2484 int yel, grn;
2485
2486 /*
2487 * The diags use the LED to indicate diag info, so we leave
2488 * the external LED alone when the diags are running.
2489 */
2490 if (dd->diag_client)
2491 return;
2492
2493 /* Allow override of LED display for, e.g. Locating system in rack */
2494 if (ppd->led_override) {
2495 grn = (ppd->led_override & QIB_LED_PHYS);
2496 yel = (ppd->led_override & QIB_LED_LOG);
2497 } else if (on) {
2498 val = qib_read_kreg_port(ppd, krp_ibcstatus_a);
2499 grn = qib_7322_phys_portstate(val) ==
2500 IB_PHYSPORTSTATE_LINKUP;
2501 yel = qib_7322_iblink_state(val) == IB_PORT_ACTIVE;
2502 } else {
2503 grn = 0;
2504 yel = 0;
2505 }
2506
2507 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2508 extctl = dd->cspec->extctrl & (ppd->port == 1 ?
2509 ~ExtLED_IB1_MASK : ~ExtLED_IB2_MASK);
2510 if (grn) {
2511 extctl |= ppd->port == 1 ? ExtLED_IB1_GRN : ExtLED_IB2_GRN;
2512 /*
2513 * Counts are in chip clock (4ns) periods.
2514 * This is 1/16 sec (66.6ms) on,
2515 * 3/16 sec (187.5 ms) off, with packets rcvd.
2516 */
2517 ledblink = ((66600 * 1000UL / 4) << IBA7322_LEDBLINK_ON_SHIFT) |
2518 ((187500 * 1000UL / 4) << IBA7322_LEDBLINK_OFF_SHIFT);
2519 }
2520 if (yel)
2521 extctl |= ppd->port == 1 ? ExtLED_IB1_YEL : ExtLED_IB2_YEL;
2522 dd->cspec->extctrl = extctl;
2523 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
2524 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2525
2526 if (ledblink) /* blink the LED on packet receive */
2527 qib_write_kreg_port(ppd, krp_rcvpktledcnt, ledblink);
2528 }
2529
2530 /*
2531 * Disable MSIx interrupt if enabled, call generic MSIx code
2532 * to cleanup, and clear pending MSIx interrupts.
2533 * Used for fallback to INTx, after reset, and when MSIx setup fails.
2534 */
2535 static void qib_7322_nomsix(struct qib_devdata *dd)
2536 {
2537 u64 intgranted;
2538 int n;
2539
2540 dd->cspec->main_int_mask = ~0ULL;
2541 n = dd->cspec->num_msix_entries;
2542 if (n) {
2543 int i;
2544
2545 dd->cspec->num_msix_entries = 0;
2546 for (i = 0; i < n; i++)
2547 free_irq(dd->cspec->msix_entries[i].vector,
2548 dd->cspec->msix_arg[i]);
2549 qib_nomsix(dd);
2550 }
2551 /* make sure no MSIx interrupts are left pending */
2552 intgranted = qib_read_kreg64(dd, kr_intgranted);
2553 if (intgranted)
2554 qib_write_kreg(dd, kr_intgranted, intgranted);
2555 }
2556
2557 static void qib_7322_free_irq(struct qib_devdata *dd)
2558 {
2559 if (dd->cspec->irq) {
2560 free_irq(dd->cspec->irq, dd);
2561 dd->cspec->irq = 0;
2562 }
2563 qib_7322_nomsix(dd);
2564 }
2565
2566 static void qib_setup_7322_cleanup(struct qib_devdata *dd)
2567 {
2568 int i;
2569
2570 qib_7322_free_irq(dd);
2571 kfree(dd->cspec->cntrs);
2572 kfree(dd->cspec->sendchkenable);
2573 kfree(dd->cspec->sendgrhchk);
2574 kfree(dd->cspec->sendibchk);
2575 kfree(dd->cspec->msix_entries);
2576 kfree(dd->cspec->msix_arg);
2577 for (i = 0; i < dd->num_pports; i++) {
2578 unsigned long flags;
2579 u32 mask = QSFP_GPIO_MOD_PRS_N |
2580 (QSFP_GPIO_MOD_PRS_N << QSFP_GPIO_PORT2_SHIFT);
2581
2582 kfree(dd->pport[i].cpspec->portcntrs);
2583 if (dd->flags & QIB_HAS_QSFP) {
2584 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
2585 dd->cspec->gpio_mask &= ~mask;
2586 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2587 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
2588 qib_qsfp_deinit(&dd->pport[i].cpspec->qsfp_data);
2589 }
2590 if (dd->pport[i].ibport_data.smi_ah)
2591 ib_destroy_ah(&dd->pport[i].ibport_data.smi_ah->ibah);
2592 }
2593 }
2594
2595 /* handle SDMA interrupts */
2596 static void sdma_7322_intr(struct qib_devdata *dd, u64 istat)
2597 {
2598 struct qib_pportdata *ppd0 = &dd->pport[0];
2599 struct qib_pportdata *ppd1 = &dd->pport[1];
2600 u64 intr0 = istat & (INT_MASK_P(SDma, 0) |
2601 INT_MASK_P(SDmaIdle, 0) | INT_MASK_P(SDmaProgress, 0));
2602 u64 intr1 = istat & (INT_MASK_P(SDma, 1) |
2603 INT_MASK_P(SDmaIdle, 1) | INT_MASK_P(SDmaProgress, 1));
2604
2605 if (intr0)
2606 qib_sdma_intr(ppd0);
2607 if (intr1)
2608 qib_sdma_intr(ppd1);
2609
2610 if (istat & INT_MASK_PM(SDmaCleanupDone, 0))
2611 qib_sdma_process_event(ppd0, qib_sdma_event_e20_hw_started);
2612 if (istat & INT_MASK_PM(SDmaCleanupDone, 1))
2613 qib_sdma_process_event(ppd1, qib_sdma_event_e20_hw_started);
2614 }
2615
2616 /*
2617 * Set or clear the Send buffer available interrupt enable bit.
2618 */
2619 static void qib_wantpiobuf_7322_intr(struct qib_devdata *dd, u32 needint)
2620 {
2621 unsigned long flags;
2622
2623 spin_lock_irqsave(&dd->sendctrl_lock, flags);
2624 if (needint)
2625 dd->sendctrl |= SYM_MASK(SendCtrl, SendIntBufAvail);
2626 else
2627 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendIntBufAvail);
2628 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
2629 qib_write_kreg(dd, kr_scratch, 0ULL);
2630 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
2631 }
2632
2633 /*
2634 * Somehow got an interrupt with reserved bits set in interrupt status.
2635 * Print a message so we know it happened, then clear them.
2636 * keep mainline interrupt handler cache-friendly
2637 */
2638 static noinline void unknown_7322_ibits(struct qib_devdata *dd, u64 istat)
2639 {
2640 u64 kills;
2641 char msg[128];
2642
2643 kills = istat & ~QIB_I_BITSEXTANT;
2644 qib_dev_err(dd, "Clearing reserved interrupt(s) 0x%016llx:"
2645 " %s\n", (unsigned long long) kills, msg);
2646 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills));
2647 }
2648
2649 /* keep mainline interrupt handler cache-friendly */
2650 static noinline void unknown_7322_gpio_intr(struct qib_devdata *dd)
2651 {
2652 u32 gpiostatus;
2653 int handled = 0;
2654 int pidx;
2655
2656 /*
2657 * Boards for this chip currently don't use GPIO interrupts,
2658 * so clear by writing GPIOstatus to GPIOclear, and complain
2659 * to developer. To avoid endless repeats, clear
2660 * the bits in the mask, since there is some kind of
2661 * programming error or chip problem.
2662 */
2663 gpiostatus = qib_read_kreg32(dd, kr_gpio_status);
2664 /*
2665 * In theory, writing GPIOstatus to GPIOclear could
2666 * have a bad side-effect on some diagnostic that wanted
2667 * to poll for a status-change, but the various shadows
2668 * make that problematic at best. Diags will just suppress
2669 * all GPIO interrupts during such tests.
2670 */
2671 qib_write_kreg(dd, kr_gpio_clear, gpiostatus);
2672 /*
2673 * Check for QSFP MOD_PRS changes
2674 * only works for single port if IB1 != pidx1
2675 */
2676 for (pidx = 0; pidx < dd->num_pports && (dd->flags & QIB_HAS_QSFP);
2677 ++pidx) {
2678 struct qib_pportdata *ppd;
2679 struct qib_qsfp_data *qd;
2680 u32 mask;
2681 if (!dd->pport[pidx].link_speed_supported)
2682 continue;
2683 mask = QSFP_GPIO_MOD_PRS_N;
2684 ppd = dd->pport + pidx;
2685 mask <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
2686 if (gpiostatus & dd->cspec->gpio_mask & mask) {
2687 u64 pins;
2688 qd = &ppd->cpspec->qsfp_data;
2689 gpiostatus &= ~mask;
2690 pins = qib_read_kreg64(dd, kr_extstatus);
2691 pins >>= SYM_LSB(EXTStatus, GPIOIn);
2692 if (!(pins & mask)) {
2693 ++handled;
2694 qd->t_insert = get_jiffies_64();
2695 queue_work(ib_wq, &qd->work);
2696 }
2697 }
2698 }
2699
2700 if (gpiostatus && !handled) {
2701 const u32 mask = qib_read_kreg32(dd, kr_gpio_mask);
2702 u32 gpio_irq = mask & gpiostatus;
2703
2704 /*
2705 * Clear any troublemakers, and update chip from shadow
2706 */
2707 dd->cspec->gpio_mask &= ~gpio_irq;
2708 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
2709 }
2710 }
2711
2712 /*
2713 * Handle errors and unusual events first, separate function
2714 * to improve cache hits for fast path interrupt handling.
2715 */
2716 static noinline void unlikely_7322_intr(struct qib_devdata *dd, u64 istat)
2717 {
2718 if (istat & ~QIB_I_BITSEXTANT)
2719 unknown_7322_ibits(dd, istat);
2720 if (istat & QIB_I_GPIO)
2721 unknown_7322_gpio_intr(dd);
2722 if (istat & QIB_I_C_ERROR)
2723 handle_7322_errors(dd);
2724 if (istat & INT_MASK_P(Err, 0) && dd->rcd[0])
2725 handle_7322_p_errors(dd->rcd[0]->ppd);
2726 if (istat & INT_MASK_P(Err, 1) && dd->rcd[1])
2727 handle_7322_p_errors(dd->rcd[1]->ppd);
2728 }
2729
2730 /*
2731 * Dynamically adjust the rcv int timeout for a context based on incoming
2732 * packet rate.
2733 */
2734 static void adjust_rcv_timeout(struct qib_ctxtdata *rcd, int npkts)
2735 {
2736 struct qib_devdata *dd = rcd->dd;
2737 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt];
2738
2739 /*
2740 * Dynamically adjust idle timeout on chip
2741 * based on number of packets processed.
2742 */
2743 if (npkts < rcv_int_count && timeout > 2)
2744 timeout >>= 1;
2745 else if (npkts >= rcv_int_count && timeout < rcv_int_timeout)
2746 timeout = min(timeout << 1, rcv_int_timeout);
2747 else
2748 return;
2749
2750 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout;
2751 qib_write_kreg(dd, kr_rcvavailtimeout + rcd->ctxt, timeout);
2752 }
2753
2754 /*
2755 * This is the main interrupt handler.
2756 * It will normally only be used for low frequency interrupts but may
2757 * have to handle all interrupts if INTx is enabled or fewer than normal
2758 * MSIx interrupts were allocated.
2759 * This routine should ignore the interrupt bits for any of the
2760 * dedicated MSIx handlers.
2761 */
2762 static irqreturn_t qib_7322intr(int irq, void *data)
2763 {
2764 struct qib_devdata *dd = data;
2765 irqreturn_t ret;
2766 u64 istat;
2767 u64 ctxtrbits;
2768 u64 rmask;
2769 unsigned i;
2770 u32 npkts;
2771
2772 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT) {
2773 /*
2774 * This return value is not great, but we do not want the
2775 * interrupt core code to remove our interrupt handler
2776 * because we don't appear to be handling an interrupt
2777 * during a chip reset.
2778 */
2779 ret = IRQ_HANDLED;
2780 goto bail;
2781 }
2782
2783 istat = qib_read_kreg64(dd, kr_intstatus);
2784
2785 if (unlikely(istat == ~0ULL)) {
2786 qib_bad_intrstatus(dd);
2787 qib_dev_err(dd, "Interrupt status all f's, skipping\n");
2788 /* don't know if it was our interrupt or not */
2789 ret = IRQ_NONE;
2790 goto bail;
2791 }
2792
2793 istat &= dd->cspec->main_int_mask;
2794 if (unlikely(!istat)) {
2795 /* already handled, or shared and not us */
2796 ret = IRQ_NONE;
2797 goto bail;
2798 }
2799
2800 qib_stats.sps_ints++;
2801 if (dd->int_counter != (u32) -1)
2802 dd->int_counter++;
2803
2804 /* handle "errors" of various kinds first, device ahead of port */
2805 if (unlikely(istat & (~QIB_I_BITSEXTANT | QIB_I_GPIO |
2806 QIB_I_C_ERROR | INT_MASK_P(Err, 0) |
2807 INT_MASK_P(Err, 1))))
2808 unlikely_7322_intr(dd, istat);
2809
2810 /*
2811 * Clear the interrupt bits we found set, relatively early, so we
2812 * "know" know the chip will have seen this by the time we process
2813 * the queue, and will re-interrupt if necessary. The processor
2814 * itself won't take the interrupt again until we return.
2815 */
2816 qib_write_kreg(dd, kr_intclear, istat);
2817
2818 /*
2819 * Handle kernel receive queues before checking for pio buffers
2820 * available since receives can overflow; piobuf waiters can afford
2821 * a few extra cycles, since they were waiting anyway.
2822 */
2823 ctxtrbits = istat & (QIB_I_RCVAVAIL_MASK | QIB_I_RCVURG_MASK);
2824 if (ctxtrbits) {
2825 rmask = (1ULL << QIB_I_RCVAVAIL_LSB) |
2826 (1ULL << QIB_I_RCVURG_LSB);
2827 for (i = 0; i < dd->first_user_ctxt; i++) {
2828 if (ctxtrbits & rmask) {
2829 ctxtrbits &= ~rmask;
2830 if (dd->rcd[i]) {
2831 qib_kreceive(dd->rcd[i], NULL, &npkts);
2832 }
2833 }
2834 rmask <<= 1;
2835 }
2836 if (ctxtrbits) {
2837 ctxtrbits = (ctxtrbits >> QIB_I_RCVAVAIL_LSB) |
2838 (ctxtrbits >> QIB_I_RCVURG_LSB);
2839 qib_handle_urcv(dd, ctxtrbits);
2840 }
2841 }
2842
2843 if (istat & (QIB_I_P_SDMAINT(0) | QIB_I_P_SDMAINT(1)))
2844 sdma_7322_intr(dd, istat);
2845
2846 if ((istat & QIB_I_SPIOBUFAVAIL) && (dd->flags & QIB_INITTED))
2847 qib_ib_piobufavail(dd);
2848
2849 ret = IRQ_HANDLED;
2850 bail:
2851 return ret;
2852 }
2853
2854 /*
2855 * Dedicated receive packet available interrupt handler.
2856 */
2857 static irqreturn_t qib_7322pintr(int irq, void *data)
2858 {
2859 struct qib_ctxtdata *rcd = data;
2860 struct qib_devdata *dd = rcd->dd;
2861 u32 npkts;
2862
2863 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2864 /*
2865 * This return value is not great, but we do not want the
2866 * interrupt core code to remove our interrupt handler
2867 * because we don't appear to be handling an interrupt
2868 * during a chip reset.
2869 */
2870 return IRQ_HANDLED;
2871
2872 qib_stats.sps_ints++;
2873 if (dd->int_counter != (u32) -1)
2874 dd->int_counter++;
2875
2876 /* Clear the interrupt bit we expect to be set. */
2877 qib_write_kreg(dd, kr_intclear, ((1ULL << QIB_I_RCVAVAIL_LSB) |
2878 (1ULL << QIB_I_RCVURG_LSB)) << rcd->ctxt);
2879
2880 qib_kreceive(rcd, NULL, &npkts);
2881
2882 return IRQ_HANDLED;
2883 }
2884
2885 /*
2886 * Dedicated Send buffer available interrupt handler.
2887 */
2888 static irqreturn_t qib_7322bufavail(int irq, void *data)
2889 {
2890 struct qib_devdata *dd = data;
2891
2892 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2893 /*
2894 * This return value is not great, but we do not want the
2895 * interrupt core code to remove our interrupt handler
2896 * because we don't appear to be handling an interrupt
2897 * during a chip reset.
2898 */
2899 return IRQ_HANDLED;
2900
2901 qib_stats.sps_ints++;
2902 if (dd->int_counter != (u32) -1)
2903 dd->int_counter++;
2904
2905 /* Clear the interrupt bit we expect to be set. */
2906 qib_write_kreg(dd, kr_intclear, QIB_I_SPIOBUFAVAIL);
2907
2908 /* qib_ib_piobufavail() will clear the want PIO interrupt if needed */
2909 if (dd->flags & QIB_INITTED)
2910 qib_ib_piobufavail(dd);
2911 else
2912 qib_wantpiobuf_7322_intr(dd, 0);
2913
2914 return IRQ_HANDLED;
2915 }
2916
2917 /*
2918 * Dedicated Send DMA interrupt handler.
2919 */
2920 static irqreturn_t sdma_intr(int irq, void *data)
2921 {
2922 struct qib_pportdata *ppd = data;
2923 struct qib_devdata *dd = ppd->dd;
2924
2925 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2926 /*
2927 * This return value is not great, but we do not want the
2928 * interrupt core code to remove our interrupt handler
2929 * because we don't appear to be handling an interrupt
2930 * during a chip reset.
2931 */
2932 return IRQ_HANDLED;
2933
2934 qib_stats.sps_ints++;
2935 if (dd->int_counter != (u32) -1)
2936 dd->int_counter++;
2937
2938 /* Clear the interrupt bit we expect to be set. */
2939 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2940 INT_MASK_P(SDma, 1) : INT_MASK_P(SDma, 0));
2941 qib_sdma_intr(ppd);
2942
2943 return IRQ_HANDLED;
2944 }
2945
2946 /*
2947 * Dedicated Send DMA idle interrupt handler.
2948 */
2949 static irqreturn_t sdma_idle_intr(int irq, void *data)
2950 {
2951 struct qib_pportdata *ppd = data;
2952 struct qib_devdata *dd = ppd->dd;
2953
2954 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2955 /*
2956 * This return value is not great, but we do not want the
2957 * interrupt core code to remove our interrupt handler
2958 * because we don't appear to be handling an interrupt
2959 * during a chip reset.
2960 */
2961 return IRQ_HANDLED;
2962
2963 qib_stats.sps_ints++;
2964 if (dd->int_counter != (u32) -1)
2965 dd->int_counter++;
2966
2967 /* Clear the interrupt bit we expect to be set. */
2968 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2969 INT_MASK_P(SDmaIdle, 1) : INT_MASK_P(SDmaIdle, 0));
2970 qib_sdma_intr(ppd);
2971
2972 return IRQ_HANDLED;
2973 }
2974
2975 /*
2976 * Dedicated Send DMA progress interrupt handler.
2977 */
2978 static irqreturn_t sdma_progress_intr(int irq, void *data)
2979 {
2980 struct qib_pportdata *ppd = data;
2981 struct qib_devdata *dd = ppd->dd;
2982
2983 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
2984 /*
2985 * This return value is not great, but we do not want the
2986 * interrupt core code to remove our interrupt handler
2987 * because we don't appear to be handling an interrupt
2988 * during a chip reset.
2989 */
2990 return IRQ_HANDLED;
2991
2992 qib_stats.sps_ints++;
2993 if (dd->int_counter != (u32) -1)
2994 dd->int_counter++;
2995
2996 /* Clear the interrupt bit we expect to be set. */
2997 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
2998 INT_MASK_P(SDmaProgress, 1) :
2999 INT_MASK_P(SDmaProgress, 0));
3000 qib_sdma_intr(ppd);
3001
3002 return IRQ_HANDLED;
3003 }
3004
3005 /*
3006 * Dedicated Send DMA cleanup interrupt handler.
3007 */
3008 static irqreturn_t sdma_cleanup_intr(int irq, void *data)
3009 {
3010 struct qib_pportdata *ppd = data;
3011 struct qib_devdata *dd = ppd->dd;
3012
3013 if ((dd->flags & (QIB_PRESENT | QIB_BADINTR)) != QIB_PRESENT)
3014 /*
3015 * This return value is not great, but we do not want the
3016 * interrupt core code to remove our interrupt handler
3017 * because we don't appear to be handling an interrupt
3018 * during a chip reset.
3019 */
3020 return IRQ_HANDLED;
3021
3022 qib_stats.sps_ints++;
3023 if (dd->int_counter != (u32) -1)
3024 dd->int_counter++;
3025
3026 /* Clear the interrupt bit we expect to be set. */
3027 qib_write_kreg(dd, kr_intclear, ppd->hw_pidx ?
3028 INT_MASK_PM(SDmaCleanupDone, 1) :
3029 INT_MASK_PM(SDmaCleanupDone, 0));
3030 qib_sdma_process_event(ppd, qib_sdma_event_e20_hw_started);
3031
3032 return IRQ_HANDLED;
3033 }
3034
3035 /*
3036 * Set up our chip-specific interrupt handler.
3037 * The interrupt type has already been setup, so
3038 * we just need to do the registration and error checking.
3039 * If we are using MSIx interrupts, we may fall back to
3040 * INTx later, if the interrupt handler doesn't get called
3041 * within 1/2 second (see verify_interrupt()).
3042 */
3043 static void qib_setup_7322_interrupt(struct qib_devdata *dd, int clearpend)
3044 {
3045 int ret, i, msixnum;
3046 u64 redirect[6];
3047 u64 mask;
3048
3049 if (!dd->num_pports)
3050 return;
3051
3052 if (clearpend) {
3053 /*
3054 * if not switching interrupt types, be sure interrupts are
3055 * disabled, and then clear anything pending at this point,
3056 * because we are starting clean.
3057 */
3058 qib_7322_set_intr_state(dd, 0);
3059
3060 /* clear the reset error, init error/hwerror mask */
3061 qib_7322_init_hwerrors(dd);
3062
3063 /* clear any interrupt bits that might be set */
3064 qib_write_kreg(dd, kr_intclear, ~0ULL);
3065
3066 /* make sure no pending MSIx intr, and clear diag reg */
3067 qib_write_kreg(dd, kr_intgranted, ~0ULL);
3068 qib_write_kreg(dd, kr_vecclr_wo_int, ~0ULL);
3069 }
3070
3071 if (!dd->cspec->num_msix_entries) {
3072 /* Try to get INTx interrupt */
3073 try_intx:
3074 if (!dd->pcidev->irq) {
3075 qib_dev_err(dd, "irq is 0, BIOS error? "
3076 "Interrupts won't work\n");
3077 goto bail;
3078 }
3079 ret = request_irq(dd->pcidev->irq, qib_7322intr,
3080 IRQF_SHARED, QIB_DRV_NAME, dd);
3081 if (ret) {
3082 qib_dev_err(dd, "Couldn't setup INTx "
3083 "interrupt (irq=%d): %d\n",
3084 dd->pcidev->irq, ret);
3085 goto bail;
3086 }
3087 dd->cspec->irq = dd->pcidev->irq;
3088 dd->cspec->main_int_mask = ~0ULL;
3089 goto bail;
3090 }
3091
3092 /* Try to get MSIx interrupts */
3093 memset(redirect, 0, sizeof redirect);
3094 mask = ~0ULL;
3095 msixnum = 0;
3096 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) {
3097 irq_handler_t handler;
3098 const char *name;
3099 void *arg;
3100 u64 val;
3101 int lsb, reg, sh;
3102
3103 if (i < ARRAY_SIZE(irq_table)) {
3104 if (irq_table[i].port) {
3105 /* skip if for a non-configured port */
3106 if (irq_table[i].port > dd->num_pports)
3107 continue;
3108 arg = dd->pport + irq_table[i].port - 1;
3109 } else
3110 arg = dd;
3111 lsb = irq_table[i].lsb;
3112 handler = irq_table[i].handler;
3113 name = irq_table[i].name;
3114 } else {
3115 unsigned ctxt;
3116
3117 ctxt = i - ARRAY_SIZE(irq_table);
3118 /* per krcvq context receive interrupt */
3119 arg = dd->rcd[ctxt];
3120 if (!arg)
3121 continue;
3122 lsb = QIB_I_RCVAVAIL_LSB + ctxt;
3123 handler = qib_7322pintr;
3124 name = QIB_DRV_NAME " (kctx)";
3125 }
3126 ret = request_irq(dd->cspec->msix_entries[msixnum].vector,
3127 handler, 0, name, arg);
3128 if (ret) {
3129 /*
3130 * Shouldn't happen since the enable said we could
3131 * have as many as we are trying to setup here.
3132 */
3133 qib_dev_err(dd, "Couldn't setup MSIx "
3134 "interrupt (vec=%d, irq=%d): %d\n", msixnum,
3135 dd->cspec->msix_entries[msixnum].vector,
3136 ret);
3137 qib_7322_nomsix(dd);
3138 goto try_intx;
3139 }
3140 dd->cspec->msix_arg[msixnum] = arg;
3141 if (lsb >= 0) {
3142 reg = lsb / IBA7322_REDIRECT_VEC_PER_REG;
3143 sh = (lsb % IBA7322_REDIRECT_VEC_PER_REG) *
3144 SYM_LSB(IntRedirect0, vec1);
3145 mask &= ~(1ULL << lsb);
3146 redirect[reg] |= ((u64) msixnum) << sh;
3147 }
3148 val = qib_read_kreg64(dd, 2 * msixnum + 1 +
3149 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3150 msixnum++;
3151 }
3152 /* Initialize the vector mapping */
3153 for (i = 0; i < ARRAY_SIZE(redirect); i++)
3154 qib_write_kreg(dd, kr_intredirect + i, redirect[i]);
3155 dd->cspec->main_int_mask = mask;
3156 bail:;
3157 }
3158
3159 /**
3160 * qib_7322_boardname - fill in the board name and note features
3161 * @dd: the qlogic_ib device
3162 *
3163 * info will be based on the board revision register
3164 */
3165 static unsigned qib_7322_boardname(struct qib_devdata *dd)
3166 {
3167 /* Will need enumeration of board-types here */
3168 char *n;
3169 u32 boardid, namelen;
3170 unsigned features = DUAL_PORT_CAP;
3171
3172 boardid = SYM_FIELD(dd->revision, Revision, BoardID);
3173
3174 switch (boardid) {
3175 case 0:
3176 n = "InfiniPath_QLE7342_Emulation";
3177 break;
3178 case 1:
3179 n = "InfiniPath_QLE7340";
3180 dd->flags |= QIB_HAS_QSFP;
3181 features = PORT_SPD_CAP;
3182 break;
3183 case 2:
3184 n = "InfiniPath_QLE7342";
3185 dd->flags |= QIB_HAS_QSFP;
3186 break;
3187 case 3:
3188 n = "InfiniPath_QMI7342";
3189 break;
3190 case 4:
3191 n = "InfiniPath_Unsupported7342";
3192 qib_dev_err(dd, "Unsupported version of QMH7342\n");
3193 features = 0;
3194 break;
3195 case BOARD_QMH7342:
3196 n = "InfiniPath_QMH7342";
3197 features = 0x24;
3198 break;
3199 case BOARD_QME7342:
3200 n = "InfiniPath_QME7342";
3201 break;
3202 case 8:
3203 n = "InfiniPath_QME7362";
3204 dd->flags |= QIB_HAS_QSFP;
3205 break;
3206 case 15:
3207 n = "InfiniPath_QLE7342_TEST";
3208 dd->flags |= QIB_HAS_QSFP;
3209 break;
3210 default:
3211 n = "InfiniPath_QLE73xy_UNKNOWN";
3212 qib_dev_err(dd, "Unknown 7322 board type %u\n", boardid);
3213 break;
3214 }
3215 dd->board_atten = 1; /* index into txdds_Xdr */
3216
3217 namelen = strlen(n) + 1;
3218 dd->boardname = kmalloc(namelen, GFP_KERNEL);
3219 if (!dd->boardname)
3220 qib_dev_err(dd, "Failed allocation for board name: %s\n", n);
3221 else
3222 snprintf(dd->boardname, namelen, "%s", n);
3223
3224 snprintf(dd->boardversion, sizeof(dd->boardversion),
3225 "ChipABI %u.%u, %s, InfiniPath%u %u.%u, SW Compat %u\n",
3226 QIB_CHIP_VERS_MAJ, QIB_CHIP_VERS_MIN, dd->boardname,
3227 (unsigned)SYM_FIELD(dd->revision, Revision_R, Arch),
3228 dd->majrev, dd->minrev,
3229 (unsigned)SYM_FIELD(dd->revision, Revision_R, SW));
3230
3231 if (qib_singleport && (features >> PORT_SPD_CAP_SHIFT) & PORT_SPD_CAP) {
3232 qib_devinfo(dd->pcidev, "IB%u: Forced to single port mode"
3233 " by module parameter\n", dd->unit);
3234 features &= PORT_SPD_CAP;
3235 }
3236
3237 return features;
3238 }
3239
3240 /*
3241 * This routine sleeps, so it can only be called from user context, not
3242 * from interrupt context.
3243 */
3244 static int qib_do_7322_reset(struct qib_devdata *dd)
3245 {
3246 u64 val;
3247 u64 *msix_vecsave;
3248 int i, msix_entries, ret = 1;
3249 u16 cmdval;
3250 u8 int_line, clinesz;
3251 unsigned long flags;
3252
3253 /* Use dev_err so it shows up in logs, etc. */
3254 qib_dev_err(dd, "Resetting InfiniPath unit %u\n", dd->unit);
3255
3256 qib_pcie_getcmd(dd, &cmdval, &int_line, &clinesz);
3257
3258 msix_entries = dd->cspec->num_msix_entries;
3259
3260 /* no interrupts till re-initted */
3261 qib_7322_set_intr_state(dd, 0);
3262
3263 if (msix_entries) {
3264 qib_7322_nomsix(dd);
3265 /* can be up to 512 bytes, too big for stack */
3266 msix_vecsave = kmalloc(2 * dd->cspec->num_msix_entries *
3267 sizeof(u64), GFP_KERNEL);
3268 if (!msix_vecsave)
3269 qib_dev_err(dd, "No mem to save MSIx data\n");
3270 } else
3271 msix_vecsave = NULL;
3272
3273 /*
3274 * Core PCI (as of 2.6.18) doesn't save or rewrite the full vector
3275 * info that is set up by the BIOS, so we have to save and restore
3276 * it ourselves. There is some risk something could change it,
3277 * after we save it, but since we have disabled the MSIx, it
3278 * shouldn't be touched...
3279 */
3280 for (i = 0; i < msix_entries; i++) {
3281 u64 vecaddr, vecdata;
3282 vecaddr = qib_read_kreg64(dd, 2 * i +
3283 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3284 vecdata = qib_read_kreg64(dd, 1 + 2 * i +
3285 (QIB_7322_MsixTable_OFFS / sizeof(u64)));
3286 if (msix_vecsave) {
3287 msix_vecsave[2 * i] = vecaddr;
3288 /* save it without the masked bit set */
3289 msix_vecsave[1 + 2 * i] = vecdata & ~0x100000000ULL;
3290 }
3291 }
3292
3293 dd->pport->cpspec->ibdeltainprog = 0;
3294 dd->pport->cpspec->ibsymdelta = 0;
3295 dd->pport->cpspec->iblnkerrdelta = 0;
3296 dd->pport->cpspec->ibmalfdelta = 0;
3297 dd->int_counter = 0; /* so we check interrupts work again */
3298
3299 /*
3300 * Keep chip from being accessed until we are ready. Use
3301 * writeq() directly, to allow the write even though QIB_PRESENT
3302 * isnt' set.
3303 */
3304 dd->flags &= ~(QIB_INITTED | QIB_PRESENT | QIB_BADINTR);
3305 dd->flags |= QIB_DOING_RESET;
3306 val = dd->control | QLOGIC_IB_C_RESET;
3307 writeq(val, &dd->kregbase[kr_control]);
3308
3309 for (i = 1; i <= 5; i++) {
3310 /*
3311 * Allow MBIST, etc. to complete; longer on each retry.
3312 * We sometimes get machine checks from bus timeout if no
3313 * response, so for now, make it *really* long.
3314 */
3315 msleep(1000 + (1 + i) * 3000);
3316
3317 qib_pcie_reenable(dd, cmdval, int_line, clinesz);
3318
3319 /*
3320 * Use readq directly, so we don't need to mark it as PRESENT
3321 * until we get a successful indication that all is well.
3322 */
3323 val = readq(&dd->kregbase[kr_revision]);
3324 if (val == dd->revision)
3325 break;
3326 if (i == 5) {
3327 qib_dev_err(dd, "Failed to initialize after reset, "
3328 "unusable\n");
3329 ret = 0;
3330 goto bail;
3331 }
3332 }
3333
3334 dd->flags |= QIB_PRESENT; /* it's back */
3335
3336 if (msix_entries) {
3337 /* restore the MSIx vector address and data if saved above */
3338 for (i = 0; i < msix_entries; i++) {
3339 dd->cspec->msix_entries[i].entry = i;
3340 if (!msix_vecsave || !msix_vecsave[2 * i])
3341 continue;
3342 qib_write_kreg(dd, 2 * i +
3343 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3344 msix_vecsave[2 * i]);
3345 qib_write_kreg(dd, 1 + 2 * i +
3346 (QIB_7322_MsixTable_OFFS / sizeof(u64)),
3347 msix_vecsave[1 + 2 * i]);
3348 }
3349 }
3350
3351 /* initialize the remaining registers. */
3352 for (i = 0; i < dd->num_pports; ++i)
3353 write_7322_init_portregs(&dd->pport[i]);
3354 write_7322_initregs(dd);
3355
3356 if (qib_pcie_params(dd, dd->lbus_width,
3357 &dd->cspec->num_msix_entries,
3358 dd->cspec->msix_entries))
3359 qib_dev_err(dd, "Reset failed to setup PCIe or interrupts; "
3360 "continuing anyway\n");
3361
3362 qib_setup_7322_interrupt(dd, 1);
3363
3364 for (i = 0; i < dd->num_pports; ++i) {
3365 struct qib_pportdata *ppd = &dd->pport[i];
3366
3367 spin_lock_irqsave(&ppd->lflags_lock, flags);
3368 ppd->lflags |= QIBL_IB_FORCE_NOTIFY;
3369 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3370 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3371 }
3372
3373 bail:
3374 dd->flags &= ~QIB_DOING_RESET; /* OK or not, no longer resetting */
3375 kfree(msix_vecsave);
3376 return ret;
3377 }
3378
3379 /**
3380 * qib_7322_put_tid - write a TID to the chip
3381 * @dd: the qlogic_ib device
3382 * @tidptr: pointer to the expected TID (in chip) to update
3383 * @tidtype: 0 for eager, 1 for expected
3384 * @pa: physical address of in memory buffer; tidinvalid if freeing
3385 */
3386 static void qib_7322_put_tid(struct qib_devdata *dd, u64 __iomem *tidptr,
3387 u32 type, unsigned long pa)
3388 {
3389 if (!(dd->flags & QIB_PRESENT))
3390 return;
3391 if (pa != dd->tidinvalid) {
3392 u64 chippa = pa >> IBA7322_TID_PA_SHIFT;
3393
3394 /* paranoia checks */
3395 if (pa != (chippa << IBA7322_TID_PA_SHIFT)) {
3396 qib_dev_err(dd, "Physaddr %lx not 2KB aligned!\n",
3397 pa);
3398 return;
3399 }
3400 if (chippa >= (1UL << IBA7322_TID_SZ_SHIFT)) {
3401 qib_dev_err(dd, "Physical page address 0x%lx "
3402 "larger than supported\n", pa);
3403 return;
3404 }
3405
3406 if (type == RCVHQ_RCV_TYPE_EAGER)
3407 chippa |= dd->tidtemplate;
3408 else /* for now, always full 4KB page */
3409 chippa |= IBA7322_TID_SZ_4K;
3410 pa = chippa;
3411 }
3412 writeq(pa, tidptr);
3413 mmiowb();
3414 }
3415
3416 /**
3417 * qib_7322_clear_tids - clear all TID entries for a ctxt, expected and eager
3418 * @dd: the qlogic_ib device
3419 * @ctxt: the ctxt
3420 *
3421 * clear all TID entries for a ctxt, expected and eager.
3422 * Used from qib_close().
3423 */
3424 static void qib_7322_clear_tids(struct qib_devdata *dd,
3425 struct qib_ctxtdata *rcd)
3426 {
3427 u64 __iomem *tidbase;
3428 unsigned long tidinv;
3429 u32 ctxt;
3430 int i;
3431
3432 if (!dd->kregbase || !rcd)
3433 return;
3434
3435 ctxt = rcd->ctxt;
3436
3437 tidinv = dd->tidinvalid;
3438 tidbase = (u64 __iomem *)
3439 ((char __iomem *) dd->kregbase +
3440 dd->rcvtidbase +
3441 ctxt * dd->rcvtidcnt * sizeof(*tidbase));
3442
3443 for (i = 0; i < dd->rcvtidcnt; i++)
3444 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EXPECTED,
3445 tidinv);
3446
3447 tidbase = (u64 __iomem *)
3448 ((char __iomem *) dd->kregbase +
3449 dd->rcvegrbase +
3450 rcd->rcvegr_tid_base * sizeof(*tidbase));
3451
3452 for (i = 0; i < rcd->rcvegrcnt; i++)
3453 qib_7322_put_tid(dd, &tidbase[i], RCVHQ_RCV_TYPE_EAGER,
3454 tidinv);
3455 }
3456
3457 /**
3458 * qib_7322_tidtemplate - setup constants for TID updates
3459 * @dd: the qlogic_ib device
3460 *
3461 * We setup stuff that we use a lot, to avoid calculating each time
3462 */
3463 static void qib_7322_tidtemplate(struct qib_devdata *dd)
3464 {
3465 /*
3466 * For now, we always allocate 4KB buffers (at init) so we can
3467 * receive max size packets. We may want a module parameter to
3468 * specify 2KB or 4KB and/or make it per port instead of per device
3469 * for those who want to reduce memory footprint. Note that the
3470 * rcvhdrentsize size must be large enough to hold the largest
3471 * IB header (currently 96 bytes) that we expect to handle (plus of
3472 * course the 2 dwords of RHF).
3473 */
3474 if (dd->rcvegrbufsize == 2048)
3475 dd->tidtemplate = IBA7322_TID_SZ_2K;
3476 else if (dd->rcvegrbufsize == 4096)
3477 dd->tidtemplate = IBA7322_TID_SZ_4K;
3478 dd->tidinvalid = 0;
3479 }
3480
3481 /**
3482 * qib_init_7322_get_base_info - set chip-specific flags for user code
3483 * @rcd: the qlogic_ib ctxt
3484 * @kbase: qib_base_info pointer
3485 *
3486 * We set the PCIE flag because the lower bandwidth on PCIe vs
3487 * HyperTransport can affect some user packet algorithims.
3488 */
3489
3490 static int qib_7322_get_base_info(struct qib_ctxtdata *rcd,
3491 struct qib_base_info *kinfo)
3492 {
3493 kinfo->spi_runtime_flags |= QIB_RUNTIME_CTXT_MSB_IN_QP |
3494 QIB_RUNTIME_PCIE | QIB_RUNTIME_NODMA_RTAIL |
3495 QIB_RUNTIME_HDRSUPP | QIB_RUNTIME_SDMA;
3496 if (rcd->dd->cspec->r1)
3497 kinfo->spi_runtime_flags |= QIB_RUNTIME_RCHK;
3498 if (rcd->dd->flags & QIB_USE_SPCL_TRIG)
3499 kinfo->spi_runtime_flags |= QIB_RUNTIME_SPECIAL_TRIGGER;
3500
3501 return 0;
3502 }
3503
3504 static struct qib_message_header *
3505 qib_7322_get_msgheader(struct qib_devdata *dd, __le32 *rhf_addr)
3506 {
3507 u32 offset = qib_hdrget_offset(rhf_addr);
3508
3509 return (struct qib_message_header *)
3510 (rhf_addr - dd->rhf_offset + offset);
3511 }
3512
3513 /*
3514 * Configure number of contexts.
3515 */
3516 static void qib_7322_config_ctxts(struct qib_devdata *dd)
3517 {
3518 unsigned long flags;
3519 u32 nchipctxts;
3520
3521 nchipctxts = qib_read_kreg32(dd, kr_contextcnt);
3522 dd->cspec->numctxts = nchipctxts;
3523 if (qib_n_krcv_queues > 1 && dd->num_pports) {
3524 dd->first_user_ctxt = NUM_IB_PORTS +
3525 (qib_n_krcv_queues - 1) * dd->num_pports;
3526 if (dd->first_user_ctxt > nchipctxts)
3527 dd->first_user_ctxt = nchipctxts;
3528 dd->n_krcv_queues = dd->first_user_ctxt / dd->num_pports;
3529 } else {
3530 dd->first_user_ctxt = NUM_IB_PORTS;
3531 dd->n_krcv_queues = 1;
3532 }
3533
3534 if (!qib_cfgctxts) {
3535 int nctxts = dd->first_user_ctxt + num_online_cpus();
3536
3537 if (nctxts <= 6)
3538 dd->ctxtcnt = 6;
3539 else if (nctxts <= 10)
3540 dd->ctxtcnt = 10;
3541 else if (nctxts <= nchipctxts)
3542 dd->ctxtcnt = nchipctxts;
3543 } else if (qib_cfgctxts < dd->num_pports)
3544 dd->ctxtcnt = dd->num_pports;
3545 else if (qib_cfgctxts <= nchipctxts)
3546 dd->ctxtcnt = qib_cfgctxts;
3547 if (!dd->ctxtcnt) /* none of the above, set to max */
3548 dd->ctxtcnt = nchipctxts;
3549
3550 /*
3551 * Chip can be configured for 6, 10, or 18 ctxts, and choice
3552 * affects number of eager TIDs per ctxt (1K, 2K, 4K).
3553 * Lock to be paranoid about later motion, etc.
3554 */
3555 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
3556 if (dd->ctxtcnt > 10)
3557 dd->rcvctrl |= 2ULL << SYM_LSB(RcvCtrl, ContextCfg);
3558 else if (dd->ctxtcnt > 6)
3559 dd->rcvctrl |= 1ULL << SYM_LSB(RcvCtrl, ContextCfg);
3560 /* else configure for default 6 receive ctxts */
3561
3562 /* The XRC opcode is 5. */
3563 dd->rcvctrl |= 5ULL << SYM_LSB(RcvCtrl, XrcTypeCode);
3564
3565 /*
3566 * RcvCtrl *must* be written here so that the
3567 * chip understands how to change rcvegrcnt below.
3568 */
3569 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
3570 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
3571
3572 /* kr_rcvegrcnt changes based on the number of contexts enabled */
3573 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt);
3574 if (qib_rcvhdrcnt)
3575 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt);
3576 else
3577 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt,
3578 dd->num_pports > 1 ? 1024U : 2048U);
3579 }
3580
3581 static int qib_7322_get_ib_cfg(struct qib_pportdata *ppd, int which)
3582 {
3583
3584 int lsb, ret = 0;
3585 u64 maskr; /* right-justified mask */
3586
3587 switch (which) {
3588
3589 case QIB_IB_CFG_LWID_ENB: /* Get allowed Link-width */
3590 ret = ppd->link_width_enabled;
3591 goto done;
3592
3593 case QIB_IB_CFG_LWID: /* Get currently active Link-width */
3594 ret = ppd->link_width_active;
3595 goto done;
3596
3597 case QIB_IB_CFG_SPD_ENB: /* Get allowed Link speeds */
3598 ret = ppd->link_speed_enabled;
3599 goto done;
3600
3601 case QIB_IB_CFG_SPD: /* Get current Link spd */
3602 ret = ppd->link_speed_active;
3603 goto done;
3604
3605 case QIB_IB_CFG_RXPOL_ENB: /* Get Auto-RX-polarity enable */
3606 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3607 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3608 break;
3609
3610 case QIB_IB_CFG_LREV_ENB: /* Get Auto-Lane-reversal enable */
3611 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3612 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3613 break;
3614
3615 case QIB_IB_CFG_LINKLATENCY:
3616 ret = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
3617 SYM_MASK(IBCStatusB_0, LinkRoundTripLatency);
3618 goto done;
3619
3620 case QIB_IB_CFG_OP_VLS:
3621 ret = ppd->vls_operational;
3622 goto done;
3623
3624 case QIB_IB_CFG_VL_HIGH_CAP:
3625 ret = 16;
3626 goto done;
3627
3628 case QIB_IB_CFG_VL_LOW_CAP:
3629 ret = 16;
3630 goto done;
3631
3632 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3633 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3634 OverrunThreshold);
3635 goto done;
3636
3637 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3638 ret = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3639 PhyerrThreshold);
3640 goto done;
3641
3642 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3643 /* will only take effect when the link state changes */
3644 ret = (ppd->cpspec->ibcctrl_a &
3645 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState)) ?
3646 IB_LINKINITCMD_SLEEP : IB_LINKINITCMD_POLL;
3647 goto done;
3648
3649 case QIB_IB_CFG_HRTBT: /* Get Heartbeat off/enable/auto */
3650 lsb = IBA7322_IBC_HRTBT_LSB;
3651 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3652 break;
3653
3654 case QIB_IB_CFG_PMA_TICKS:
3655 /*
3656 * 0x00 = 10x link transfer rate or 4 nsec. for 2.5Gbs
3657 * Since the clock is always 250MHz, the value is 3, 1 or 0.
3658 */
3659 if (ppd->link_speed_active == QIB_IB_QDR)
3660 ret = 3;
3661 else if (ppd->link_speed_active == QIB_IB_DDR)
3662 ret = 1;
3663 else
3664 ret = 0;
3665 goto done;
3666
3667 default:
3668 ret = -EINVAL;
3669 goto done;
3670 }
3671 ret = (int)((ppd->cpspec->ibcctrl_b >> lsb) & maskr);
3672 done:
3673 return ret;
3674 }
3675
3676 /*
3677 * Below again cribbed liberally from older version. Do not lean
3678 * heavily on it.
3679 */
3680 #define IBA7322_IBC_DLIDLMC_SHIFT QIB_7322_IBCCtrlB_0_IB_DLID_LSB
3681 #define IBA7322_IBC_DLIDLMC_MASK (QIB_7322_IBCCtrlB_0_IB_DLID_RMASK \
3682 | (QIB_7322_IBCCtrlB_0_IB_DLID_MASK_RMASK << 16))
3683
3684 static int qib_7322_set_ib_cfg(struct qib_pportdata *ppd, int which, u32 val)
3685 {
3686 struct qib_devdata *dd = ppd->dd;
3687 u64 maskr; /* right-justified mask */
3688 int lsb, ret = 0;
3689 u16 lcmd, licmd;
3690 unsigned long flags;
3691
3692 switch (which) {
3693 case QIB_IB_CFG_LIDLMC:
3694 /*
3695 * Set LID and LMC. Combined to avoid possible hazard
3696 * caller puts LMC in 16MSbits, DLID in 16LSbits of val
3697 */
3698 lsb = IBA7322_IBC_DLIDLMC_SHIFT;
3699 maskr = IBA7322_IBC_DLIDLMC_MASK;
3700 /*
3701 * For header-checking, the SLID in the packet will
3702 * be masked with SendIBSLMCMask, and compared
3703 * with SendIBSLIDAssignMask. Make sure we do not
3704 * set any bits not covered by the mask, or we get
3705 * false-positives.
3706 */
3707 qib_write_kreg_port(ppd, krp_sendslid,
3708 val & (val >> 16) & SendIBSLIDAssignMask);
3709 qib_write_kreg_port(ppd, krp_sendslidmask,
3710 (val >> 16) & SendIBSLMCMask);
3711 break;
3712
3713 case QIB_IB_CFG_LWID_ENB: /* set allowed Link-width */
3714 ppd->link_width_enabled = val;
3715 /* convert IB value to chip register value */
3716 if (val == IB_WIDTH_1X)
3717 val = 0;
3718 else if (val == IB_WIDTH_4X)
3719 val = 1;
3720 else
3721 val = 3;
3722 maskr = SYM_RMASK(IBCCtrlB_0, IB_NUM_CHANNELS);
3723 lsb = SYM_LSB(IBCCtrlB_0, IB_NUM_CHANNELS);
3724 break;
3725
3726 case QIB_IB_CFG_SPD_ENB: /* set allowed Link speeds */
3727 /*
3728 * As with width, only write the actual register if the
3729 * link is currently down, otherwise takes effect on next
3730 * link change. Since setting is being explictly requested
3731 * (via MAD or sysfs), clear autoneg failure status if speed
3732 * autoneg is enabled.
3733 */
3734 ppd->link_speed_enabled = val;
3735 val <<= IBA7322_IBC_SPEED_LSB;
3736 maskr = IBA7322_IBC_SPEED_MASK | IBA7322_IBC_IBTA_1_2_MASK |
3737 IBA7322_IBC_MAX_SPEED_MASK;
3738 if (val & (val - 1)) {
3739 /* Muliple speeds enabled */
3740 val |= IBA7322_IBC_IBTA_1_2_MASK |
3741 IBA7322_IBC_MAX_SPEED_MASK;
3742 spin_lock_irqsave(&ppd->lflags_lock, flags);
3743 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
3744 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
3745 } else if (val & IBA7322_IBC_SPEED_QDR)
3746 val |= IBA7322_IBC_IBTA_1_2_MASK;
3747 /* IBTA 1.2 mode + min/max + speed bits are contiguous */
3748 lsb = SYM_LSB(IBCCtrlB_0, IB_ENHANCED_MODE);
3749 break;
3750
3751 case QIB_IB_CFG_RXPOL_ENB: /* set Auto-RX-polarity enable */
3752 lsb = SYM_LSB(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3753 maskr = SYM_RMASK(IBCCtrlB_0, IB_POLARITY_REV_SUPP);
3754 break;
3755
3756 case QIB_IB_CFG_LREV_ENB: /* set Auto-Lane-reversal enable */
3757 lsb = SYM_LSB(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3758 maskr = SYM_RMASK(IBCCtrlB_0, IB_LANE_REV_SUPPORTED);
3759 break;
3760
3761 case QIB_IB_CFG_OVERRUN_THRESH: /* IB overrun threshold */
3762 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3763 OverrunThreshold);
3764 if (maskr != val) {
3765 ppd->cpspec->ibcctrl_a &=
3766 ~SYM_MASK(IBCCtrlA_0, OverrunThreshold);
3767 ppd->cpspec->ibcctrl_a |= (u64) val <<
3768 SYM_LSB(IBCCtrlA_0, OverrunThreshold);
3769 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3770 ppd->cpspec->ibcctrl_a);
3771 qib_write_kreg(dd, kr_scratch, 0ULL);
3772 }
3773 goto bail;
3774
3775 case QIB_IB_CFG_PHYERR_THRESH: /* IB PHY error threshold */
3776 maskr = SYM_FIELD(ppd->cpspec->ibcctrl_a, IBCCtrlA_0,
3777 PhyerrThreshold);
3778 if (maskr != val) {
3779 ppd->cpspec->ibcctrl_a &=
3780 ~SYM_MASK(IBCCtrlA_0, PhyerrThreshold);
3781 ppd->cpspec->ibcctrl_a |= (u64) val <<
3782 SYM_LSB(IBCCtrlA_0, PhyerrThreshold);
3783 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3784 ppd->cpspec->ibcctrl_a);
3785 qib_write_kreg(dd, kr_scratch, 0ULL);
3786 }
3787 goto bail;
3788
3789 case QIB_IB_CFG_PKEYS: /* update pkeys */
3790 maskr = (u64) ppd->pkeys[0] | ((u64) ppd->pkeys[1] << 16) |
3791 ((u64) ppd->pkeys[2] << 32) |
3792 ((u64) ppd->pkeys[3] << 48);
3793 qib_write_kreg_port(ppd, krp_partitionkey, maskr);
3794 goto bail;
3795
3796 case QIB_IB_CFG_LINKDEFAULT: /* IB link default (sleep/poll) */
3797 /* will only take effect when the link state changes */
3798 if (val == IB_LINKINITCMD_POLL)
3799 ppd->cpspec->ibcctrl_a &=
3800 ~SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3801 else /* SLEEP */
3802 ppd->cpspec->ibcctrl_a |=
3803 SYM_MASK(IBCCtrlA_0, LinkDownDefaultState);
3804 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
3805 qib_write_kreg(dd, kr_scratch, 0ULL);
3806 goto bail;
3807
3808 case QIB_IB_CFG_MTU: /* update the MTU in IBC */
3809 /*
3810 * Update our housekeeping variables, and set IBC max
3811 * size, same as init code; max IBC is max we allow in
3812 * buffer, less the qword pbc, plus 1 for ICRC, in dwords
3813 * Set even if it's unchanged, print debug message only
3814 * on changes.
3815 */
3816 val = (ppd->ibmaxlen >> 2) + 1;
3817 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0, MaxPktLen);
3818 ppd->cpspec->ibcctrl_a |= (u64)val <<
3819 SYM_LSB(IBCCtrlA_0, MaxPktLen);
3820 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3821 ppd->cpspec->ibcctrl_a);
3822 qib_write_kreg(dd, kr_scratch, 0ULL);
3823 goto bail;
3824
3825 case QIB_IB_CFG_LSTATE: /* set the IB link state */
3826 switch (val & 0xffff0000) {
3827 case IB_LINKCMD_DOWN:
3828 lcmd = QLOGIC_IB_IBCC_LINKCMD_DOWN;
3829 ppd->cpspec->ibmalfusesnap = 1;
3830 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
3831 crp_errlink);
3832 if (!ppd->cpspec->ibdeltainprog &&
3833 qib_compat_ddr_negotiate) {
3834 ppd->cpspec->ibdeltainprog = 1;
3835 ppd->cpspec->ibsymsnap =
3836 read_7322_creg32_port(ppd,
3837 crp_ibsymbolerr);
3838 ppd->cpspec->iblnkerrsnap =
3839 read_7322_creg32_port(ppd,
3840 crp_iblinkerrrecov);
3841 }
3842 break;
3843
3844 case IB_LINKCMD_ARMED:
3845 lcmd = QLOGIC_IB_IBCC_LINKCMD_ARMED;
3846 if (ppd->cpspec->ibmalfusesnap) {
3847 ppd->cpspec->ibmalfusesnap = 0;
3848 ppd->cpspec->ibmalfdelta +=
3849 read_7322_creg32_port(ppd,
3850 crp_errlink) -
3851 ppd->cpspec->ibmalfsnap;
3852 }
3853 break;
3854
3855 case IB_LINKCMD_ACTIVE:
3856 lcmd = QLOGIC_IB_IBCC_LINKCMD_ACTIVE;
3857 break;
3858
3859 default:
3860 ret = -EINVAL;
3861 qib_dev_err(dd, "bad linkcmd req 0x%x\n", val >> 16);
3862 goto bail;
3863 }
3864 switch (val & 0xffff) {
3865 case IB_LINKINITCMD_NOP:
3866 licmd = 0;
3867 break;
3868
3869 case IB_LINKINITCMD_POLL:
3870 licmd = QLOGIC_IB_IBCC_LINKINITCMD_POLL;
3871 break;
3872
3873 case IB_LINKINITCMD_SLEEP:
3874 licmd = QLOGIC_IB_IBCC_LINKINITCMD_SLEEP;
3875 break;
3876
3877 case IB_LINKINITCMD_DISABLE:
3878 licmd = QLOGIC_IB_IBCC_LINKINITCMD_DISABLE;
3879 ppd->cpspec->chase_end = 0;
3880 /*
3881 * stop state chase counter and timer, if running.
3882 * wait forpending timer, but don't clear .data (ppd)!
3883 */
3884 if (ppd->cpspec->chase_timer.expires) {
3885 del_timer_sync(&ppd->cpspec->chase_timer);
3886 ppd->cpspec->chase_timer.expires = 0;
3887 }
3888 break;
3889
3890 default:
3891 ret = -EINVAL;
3892 qib_dev_err(dd, "bad linkinitcmd req 0x%x\n",
3893 val & 0xffff);
3894 goto bail;
3895 }
3896 qib_set_ib_7322_lstate(ppd, lcmd, licmd);
3897 goto bail;
3898
3899 case QIB_IB_CFG_OP_VLS:
3900 if (ppd->vls_operational != val) {
3901 ppd->vls_operational = val;
3902 set_vls(ppd);
3903 }
3904 goto bail;
3905
3906 case QIB_IB_CFG_VL_HIGH_LIMIT:
3907 qib_write_kreg_port(ppd, krp_highprio_limit, val);
3908 goto bail;
3909
3910 case QIB_IB_CFG_HRTBT: /* set Heartbeat off/enable/auto */
3911 if (val > 3) {
3912 ret = -EINVAL;
3913 goto bail;
3914 }
3915 lsb = IBA7322_IBC_HRTBT_LSB;
3916 maskr = IBA7322_IBC_HRTBT_RMASK; /* OR of AUTO and ENB */
3917 break;
3918
3919 case QIB_IB_CFG_PORT:
3920 /* val is the port number of the switch we are connected to. */
3921 if (ppd->dd->cspec->r1) {
3922 cancel_delayed_work(&ppd->cpspec->ipg_work);
3923 ppd->cpspec->ipg_tries = 0;
3924 }
3925 goto bail;
3926
3927 default:
3928 ret = -EINVAL;
3929 goto bail;
3930 }
3931 ppd->cpspec->ibcctrl_b &= ~(maskr << lsb);
3932 ppd->cpspec->ibcctrl_b |= (((u64) val & maskr) << lsb);
3933 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
3934 qib_write_kreg(dd, kr_scratch, 0);
3935 bail:
3936 return ret;
3937 }
3938
3939 static int qib_7322_set_loopback(struct qib_pportdata *ppd, const char *what)
3940 {
3941 int ret = 0;
3942 u64 val, ctrlb;
3943
3944 /* only IBC loopback, may add serdes and xgxs loopbacks later */
3945 if (!strncmp(what, "ibc", 3)) {
3946 ppd->cpspec->ibcctrl_a |= SYM_MASK(IBCCtrlA_0,
3947 Loopback);
3948 val = 0; /* disable heart beat, so link will come up */
3949 qib_devinfo(ppd->dd->pcidev, "Enabling IB%u:%u IBC loopback\n",
3950 ppd->dd->unit, ppd->port);
3951 } else if (!strncmp(what, "off", 3)) {
3952 ppd->cpspec->ibcctrl_a &= ~SYM_MASK(IBCCtrlA_0,
3953 Loopback);
3954 /* enable heart beat again */
3955 val = IBA7322_IBC_HRTBT_RMASK << IBA7322_IBC_HRTBT_LSB;
3956 qib_devinfo(ppd->dd->pcidev, "Disabling IB%u:%u IBC loopback "
3957 "(normal)\n", ppd->dd->unit, ppd->port);
3958 } else
3959 ret = -EINVAL;
3960 if (!ret) {
3961 qib_write_kreg_port(ppd, krp_ibcctrl_a,
3962 ppd->cpspec->ibcctrl_a);
3963 ctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_HRTBT_MASK
3964 << IBA7322_IBC_HRTBT_LSB);
3965 ppd->cpspec->ibcctrl_b = ctrlb | val;
3966 qib_write_kreg_port(ppd, krp_ibcctrl_b,
3967 ppd->cpspec->ibcctrl_b);
3968 qib_write_kreg(ppd->dd, kr_scratch, 0);
3969 }
3970 return ret;
3971 }
3972
3973 static void get_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3974 struct ib_vl_weight_elem *vl)
3975 {
3976 unsigned i;
3977
3978 for (i = 0; i < 16; i++, regno++, vl++) {
3979 u32 val = qib_read_kreg_port(ppd, regno);
3980
3981 vl->vl = (val >> SYM_LSB(LowPriority0_0, VirtualLane)) &
3982 SYM_RMASK(LowPriority0_0, VirtualLane);
3983 vl->weight = (val >> SYM_LSB(LowPriority0_0, Weight)) &
3984 SYM_RMASK(LowPriority0_0, Weight);
3985 }
3986 }
3987
3988 static void set_vl_weights(struct qib_pportdata *ppd, unsigned regno,
3989 struct ib_vl_weight_elem *vl)
3990 {
3991 unsigned i;
3992
3993 for (i = 0; i < 16; i++, regno++, vl++) {
3994 u64 val;
3995
3996 val = ((vl->vl & SYM_RMASK(LowPriority0_0, VirtualLane)) <<
3997 SYM_LSB(LowPriority0_0, VirtualLane)) |
3998 ((vl->weight & SYM_RMASK(LowPriority0_0, Weight)) <<
3999 SYM_LSB(LowPriority0_0, Weight));
4000 qib_write_kreg_port(ppd, regno, val);
4001 }
4002 if (!(ppd->p_sendctrl & SYM_MASK(SendCtrl_0, IBVLArbiterEn))) {
4003 struct qib_devdata *dd = ppd->dd;
4004 unsigned long flags;
4005
4006 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4007 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, IBVLArbiterEn);
4008 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4009 qib_write_kreg(dd, kr_scratch, 0);
4010 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4011 }
4012 }
4013
4014 static int qib_7322_get_ib_table(struct qib_pportdata *ppd, int which, void *t)
4015 {
4016 switch (which) {
4017 case QIB_IB_TBL_VL_HIGH_ARB:
4018 get_vl_weights(ppd, krp_highprio_0, t);
4019 break;
4020
4021 case QIB_IB_TBL_VL_LOW_ARB:
4022 get_vl_weights(ppd, krp_lowprio_0, t);
4023 break;
4024
4025 default:
4026 return -EINVAL;
4027 }
4028 return 0;
4029 }
4030
4031 static int qib_7322_set_ib_table(struct qib_pportdata *ppd, int which, void *t)
4032 {
4033 switch (which) {
4034 case QIB_IB_TBL_VL_HIGH_ARB:
4035 set_vl_weights(ppd, krp_highprio_0, t);
4036 break;
4037
4038 case QIB_IB_TBL_VL_LOW_ARB:
4039 set_vl_weights(ppd, krp_lowprio_0, t);
4040 break;
4041
4042 default:
4043 return -EINVAL;
4044 }
4045 return 0;
4046 }
4047
4048 static void qib_update_7322_usrhead(struct qib_ctxtdata *rcd, u64 hd,
4049 u32 updegr, u32 egrhd, u32 npkts)
4050 {
4051 /*
4052 * Need to write timeout register before updating rcvhdrhead to ensure
4053 * that the timer is enabled on reception of a packet.
4054 */
4055 if (hd >> IBA7322_HDRHEAD_PKTINT_SHIFT)
4056 adjust_rcv_timeout(rcd, npkts);
4057 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4058 qib_write_ureg(rcd->dd, ur_rcvhdrhead, hd, rcd->ctxt);
4059 if (updegr)
4060 qib_write_ureg(rcd->dd, ur_rcvegrindexhead, egrhd, rcd->ctxt);
4061 }
4062
4063 static u32 qib_7322_hdrqempty(struct qib_ctxtdata *rcd)
4064 {
4065 u32 head, tail;
4066
4067 head = qib_read_ureg32(rcd->dd, ur_rcvhdrhead, rcd->ctxt);
4068 if (rcd->rcvhdrtail_kvaddr)
4069 tail = qib_get_rcvhdrtail(rcd);
4070 else
4071 tail = qib_read_ureg32(rcd->dd, ur_rcvhdrtail, rcd->ctxt);
4072 return head == tail;
4073 }
4074
4075 #define RCVCTRL_COMMON_MODS (QIB_RCVCTRL_CTXT_ENB | \
4076 QIB_RCVCTRL_CTXT_DIS | \
4077 QIB_RCVCTRL_TIDFLOW_ENB | \
4078 QIB_RCVCTRL_TIDFLOW_DIS | \
4079 QIB_RCVCTRL_TAILUPD_ENB | \
4080 QIB_RCVCTRL_TAILUPD_DIS | \
4081 QIB_RCVCTRL_INTRAVAIL_ENB | \
4082 QIB_RCVCTRL_INTRAVAIL_DIS | \
4083 QIB_RCVCTRL_BP_ENB | \
4084 QIB_RCVCTRL_BP_DIS)
4085
4086 #define RCVCTRL_PORT_MODS (QIB_RCVCTRL_CTXT_ENB | \
4087 QIB_RCVCTRL_CTXT_DIS | \
4088 QIB_RCVCTRL_PKEY_DIS | \
4089 QIB_RCVCTRL_PKEY_ENB)
4090
4091 /*
4092 * Modify the RCVCTRL register in chip-specific way. This
4093 * is a function because bit positions and (future) register
4094 * location is chip-specifc, but the needed operations are
4095 * generic. <op> is a bit-mask because we often want to
4096 * do multiple modifications.
4097 */
4098 static void rcvctrl_7322_mod(struct qib_pportdata *ppd, unsigned int op,
4099 int ctxt)
4100 {
4101 struct qib_devdata *dd = ppd->dd;
4102 struct qib_ctxtdata *rcd;
4103 u64 mask, val;
4104 unsigned long flags;
4105
4106 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
4107
4108 if (op & QIB_RCVCTRL_TIDFLOW_ENB)
4109 dd->rcvctrl |= SYM_MASK(RcvCtrl, TidFlowEnable);
4110 if (op & QIB_RCVCTRL_TIDFLOW_DIS)
4111 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TidFlowEnable);
4112 if (op & QIB_RCVCTRL_TAILUPD_ENB)
4113 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4114 if (op & QIB_RCVCTRL_TAILUPD_DIS)
4115 dd->rcvctrl &= ~SYM_MASK(RcvCtrl, TailUpd);
4116 if (op & QIB_RCVCTRL_PKEY_ENB)
4117 ppd->p_rcvctrl &= ~SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4118 if (op & QIB_RCVCTRL_PKEY_DIS)
4119 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvPartitionKeyDisable);
4120 if (ctxt < 0) {
4121 mask = (1ULL << dd->ctxtcnt) - 1;
4122 rcd = NULL;
4123 } else {
4124 mask = (1ULL << ctxt);
4125 rcd = dd->rcd[ctxt];
4126 }
4127 if ((op & QIB_RCVCTRL_CTXT_ENB) && rcd) {
4128 ppd->p_rcvctrl |=
4129 (mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4130 if (!(dd->flags & QIB_NODMA_RTAIL)) {
4131 op |= QIB_RCVCTRL_TAILUPD_ENB; /* need reg write */
4132 dd->rcvctrl |= SYM_MASK(RcvCtrl, TailUpd);
4133 }
4134 /* Write these registers before the context is enabled. */
4135 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt,
4136 rcd->rcvhdrqtailaddr_phys);
4137 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt,
4138 rcd->rcvhdrq_phys);
4139 rcd->seq_cnt = 1;
4140 }
4141 if (op & QIB_RCVCTRL_CTXT_DIS)
4142 ppd->p_rcvctrl &=
4143 ~(mask << SYM_LSB(RcvCtrl_0, ContextEnableKernel));
4144 if (op & QIB_RCVCTRL_BP_ENB)
4145 dd->rcvctrl |= mask << SYM_LSB(RcvCtrl, dontDropRHQFull);
4146 if (op & QIB_RCVCTRL_BP_DIS)
4147 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, dontDropRHQFull));
4148 if (op & QIB_RCVCTRL_INTRAVAIL_ENB)
4149 dd->rcvctrl |= (mask << SYM_LSB(RcvCtrl, IntrAvail));
4150 if (op & QIB_RCVCTRL_INTRAVAIL_DIS)
4151 dd->rcvctrl &= ~(mask << SYM_LSB(RcvCtrl, IntrAvail));
4152 /*
4153 * Decide which registers to write depending on the ops enabled.
4154 * Special case is "flush" (no bits set at all)
4155 * which needs to write both.
4156 */
4157 if (op == 0 || (op & RCVCTRL_COMMON_MODS))
4158 qib_write_kreg(dd, kr_rcvctrl, dd->rcvctrl);
4159 if (op == 0 || (op & RCVCTRL_PORT_MODS))
4160 qib_write_kreg_port(ppd, krp_rcvctrl, ppd->p_rcvctrl);
4161 if ((op & QIB_RCVCTRL_CTXT_ENB) && dd->rcd[ctxt]) {
4162 /*
4163 * Init the context registers also; if we were
4164 * disabled, tail and head should both be zero
4165 * already from the enable, but since we don't
4166 * know, we have to do it explictly.
4167 */
4168 val = qib_read_ureg32(dd, ur_rcvegrindextail, ctxt);
4169 qib_write_ureg(dd, ur_rcvegrindexhead, val, ctxt);
4170
4171 /* be sure enabling write seen; hd/tl should be 0 */
4172 (void) qib_read_kreg32(dd, kr_scratch);
4173 val = qib_read_ureg32(dd, ur_rcvhdrtail, ctxt);
4174 dd->rcd[ctxt]->head = val;
4175 /* If kctxt, interrupt on next receive. */
4176 if (ctxt < dd->first_user_ctxt)
4177 val |= dd->rhdrhead_intr_off;
4178 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4179 } else if ((op & QIB_RCVCTRL_INTRAVAIL_ENB) &&
4180 dd->rcd[ctxt] && dd->rhdrhead_intr_off) {
4181 /* arm rcv interrupt */
4182 val = dd->rcd[ctxt]->head | dd->rhdrhead_intr_off;
4183 qib_write_ureg(dd, ur_rcvhdrhead, val, ctxt);
4184 }
4185 if (op & QIB_RCVCTRL_CTXT_DIS) {
4186 unsigned f;
4187
4188 /* Now that the context is disabled, clear these registers. */
4189 if (ctxt >= 0) {
4190 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr, ctxt, 0);
4191 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, ctxt, 0);
4192 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4193 qib_write_ureg(dd, ur_rcvflowtable + f,
4194 TIDFLOW_ERRBITS, ctxt);
4195 } else {
4196 unsigned i;
4197
4198 for (i = 0; i < dd->cfgctxts; i++) {
4199 qib_write_kreg_ctxt(dd, krc_rcvhdrtailaddr,
4200 i, 0);
4201 qib_write_kreg_ctxt(dd, krc_rcvhdraddr, i, 0);
4202 for (f = 0; f < NUM_TIDFLOWS_CTXT; f++)
4203 qib_write_ureg(dd, ur_rcvflowtable + f,
4204 TIDFLOW_ERRBITS, i);
4205 }
4206 }
4207 }
4208 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
4209 }
4210
4211 /*
4212 * Modify the SENDCTRL register in chip-specific way. This
4213 * is a function where there are multiple such registers with
4214 * slightly different layouts.
4215 * The chip doesn't allow back-to-back sendctrl writes, so write
4216 * the scratch register after writing sendctrl.
4217 *
4218 * Which register is written depends on the operation.
4219 * Most operate on the common register, while
4220 * SEND_ENB and SEND_DIS operate on the per-port ones.
4221 * SEND_ENB is included in common because it can change SPCL_TRIG
4222 */
4223 #define SENDCTRL_COMMON_MODS (\
4224 QIB_SENDCTRL_CLEAR | \
4225 QIB_SENDCTRL_AVAIL_DIS | \
4226 QIB_SENDCTRL_AVAIL_ENB | \
4227 QIB_SENDCTRL_AVAIL_BLIP | \
4228 QIB_SENDCTRL_DISARM | \
4229 QIB_SENDCTRL_DISARM_ALL | \
4230 QIB_SENDCTRL_SEND_ENB)
4231
4232 #define SENDCTRL_PORT_MODS (\
4233 QIB_SENDCTRL_CLEAR | \
4234 QIB_SENDCTRL_SEND_ENB | \
4235 QIB_SENDCTRL_SEND_DIS | \
4236 QIB_SENDCTRL_FLUSH)
4237
4238 static void sendctrl_7322_mod(struct qib_pportdata *ppd, u32 op)
4239 {
4240 struct qib_devdata *dd = ppd->dd;
4241 u64 tmp_dd_sendctrl;
4242 unsigned long flags;
4243
4244 spin_lock_irqsave(&dd->sendctrl_lock, flags);
4245
4246 /* First the dd ones that are "sticky", saved in shadow */
4247 if (op & QIB_SENDCTRL_CLEAR)
4248 dd->sendctrl = 0;
4249 if (op & QIB_SENDCTRL_AVAIL_DIS)
4250 dd->sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4251 else if (op & QIB_SENDCTRL_AVAIL_ENB) {
4252 dd->sendctrl |= SYM_MASK(SendCtrl, SendBufAvailUpd);
4253 if (dd->flags & QIB_USE_SPCL_TRIG)
4254 dd->sendctrl |= SYM_MASK(SendCtrl, SpecialTriggerEn);
4255 }
4256
4257 /* Then the ppd ones that are "sticky", saved in shadow */
4258 if (op & QIB_SENDCTRL_SEND_DIS)
4259 ppd->p_sendctrl &= ~SYM_MASK(SendCtrl_0, SendEnable);
4260 else if (op & QIB_SENDCTRL_SEND_ENB)
4261 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, SendEnable);
4262
4263 if (op & QIB_SENDCTRL_DISARM_ALL) {
4264 u32 i, last;
4265
4266 tmp_dd_sendctrl = dd->sendctrl;
4267 last = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
4268 /*
4269 * Disarm any buffers that are not yet launched,
4270 * disabling updates until done.
4271 */
4272 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4273 for (i = 0; i < last; i++) {
4274 qib_write_kreg(dd, kr_sendctrl,
4275 tmp_dd_sendctrl |
4276 SYM_MASK(SendCtrl, Disarm) | i);
4277 qib_write_kreg(dd, kr_scratch, 0);
4278 }
4279 }
4280
4281 if (op & QIB_SENDCTRL_FLUSH) {
4282 u64 tmp_ppd_sendctrl = ppd->p_sendctrl;
4283
4284 /*
4285 * Now drain all the fifos. The Abort bit should never be
4286 * needed, so for now, at least, we don't use it.
4287 */
4288 tmp_ppd_sendctrl |=
4289 SYM_MASK(SendCtrl_0, TxeDrainRmFifo) |
4290 SYM_MASK(SendCtrl_0, TxeDrainLaFifo) |
4291 SYM_MASK(SendCtrl_0, TxeBypassIbc);
4292 qib_write_kreg_port(ppd, krp_sendctrl, tmp_ppd_sendctrl);
4293 qib_write_kreg(dd, kr_scratch, 0);
4294 }
4295
4296 tmp_dd_sendctrl = dd->sendctrl;
4297
4298 if (op & QIB_SENDCTRL_DISARM)
4299 tmp_dd_sendctrl |= SYM_MASK(SendCtrl, Disarm) |
4300 ((op & QIB_7322_SendCtrl_DisarmSendBuf_RMASK) <<
4301 SYM_LSB(SendCtrl, DisarmSendBuf));
4302 if ((op & QIB_SENDCTRL_AVAIL_BLIP) &&
4303 (dd->sendctrl & SYM_MASK(SendCtrl, SendBufAvailUpd)))
4304 tmp_dd_sendctrl &= ~SYM_MASK(SendCtrl, SendBufAvailUpd);
4305
4306 if (op == 0 || (op & SENDCTRL_COMMON_MODS)) {
4307 qib_write_kreg(dd, kr_sendctrl, tmp_dd_sendctrl);
4308 qib_write_kreg(dd, kr_scratch, 0);
4309 }
4310
4311 if (op == 0 || (op & SENDCTRL_PORT_MODS)) {
4312 qib_write_kreg_port(ppd, krp_sendctrl, ppd->p_sendctrl);
4313 qib_write_kreg(dd, kr_scratch, 0);
4314 }
4315
4316 if (op & QIB_SENDCTRL_AVAIL_BLIP) {
4317 qib_write_kreg(dd, kr_sendctrl, dd->sendctrl);
4318 qib_write_kreg(dd, kr_scratch, 0);
4319 }
4320
4321 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
4322
4323 if (op & QIB_SENDCTRL_FLUSH) {
4324 u32 v;
4325 /*
4326 * ensure writes have hit chip, then do a few
4327 * more reads, to allow DMA of pioavail registers
4328 * to occur, so in-memory copy is in sync with
4329 * the chip. Not always safe to sleep.
4330 */
4331 v = qib_read_kreg32(dd, kr_scratch);
4332 qib_write_kreg(dd, kr_scratch, v);
4333 v = qib_read_kreg32(dd, kr_scratch);
4334 qib_write_kreg(dd, kr_scratch, v);
4335 qib_read_kreg32(dd, kr_scratch);
4336 }
4337 }
4338
4339 #define _PORT_VIRT_FLAG 0x8000U /* "virtual", need adjustments */
4340 #define _PORT_64BIT_FLAG 0x10000U /* not "virtual", but 64bit */
4341 #define _PORT_CNTR_IDXMASK 0x7fffU /* mask off flags above */
4342
4343 /**
4344 * qib_portcntr_7322 - read a per-port chip counter
4345 * @ppd: the qlogic_ib pport
4346 * @creg: the counter to read (not a chip offset)
4347 */
4348 static u64 qib_portcntr_7322(struct qib_pportdata *ppd, u32 reg)
4349 {
4350 struct qib_devdata *dd = ppd->dd;
4351 u64 ret = 0ULL;
4352 u16 creg;
4353 /* 0xffff for unimplemented or synthesized counters */
4354 static const u32 xlator[] = {
4355 [QIBPORTCNTR_PKTSEND] = crp_pktsend | _PORT_64BIT_FLAG,
4356 [QIBPORTCNTR_WORDSEND] = crp_wordsend | _PORT_64BIT_FLAG,
4357 [QIBPORTCNTR_PSXMITDATA] = crp_psxmitdatacount,
4358 [QIBPORTCNTR_PSXMITPKTS] = crp_psxmitpktscount,
4359 [QIBPORTCNTR_PSXMITWAIT] = crp_psxmitwaitcount,
4360 [QIBPORTCNTR_SENDSTALL] = crp_sendstall,
4361 [QIBPORTCNTR_PKTRCV] = crp_pktrcv | _PORT_64BIT_FLAG,
4362 [QIBPORTCNTR_PSRCVDATA] = crp_psrcvdatacount,
4363 [QIBPORTCNTR_PSRCVPKTS] = crp_psrcvpktscount,
4364 [QIBPORTCNTR_RCVEBP] = crp_rcvebp,
4365 [QIBPORTCNTR_RCVOVFL] = crp_rcvovfl,
4366 [QIBPORTCNTR_WORDRCV] = crp_wordrcv | _PORT_64BIT_FLAG,
4367 [QIBPORTCNTR_RXDROPPKT] = 0xffff, /* not needed for 7322 */
4368 [QIBPORTCNTR_RXLOCALPHYERR] = crp_rxotherlocalphyerr,
4369 [QIBPORTCNTR_RXVLERR] = crp_rxvlerr,
4370 [QIBPORTCNTR_ERRICRC] = crp_erricrc,
4371 [QIBPORTCNTR_ERRVCRC] = crp_errvcrc,
4372 [QIBPORTCNTR_ERRLPCRC] = crp_errlpcrc,
4373 [QIBPORTCNTR_BADFORMAT] = crp_badformat,
4374 [QIBPORTCNTR_ERR_RLEN] = crp_err_rlen,
4375 [QIBPORTCNTR_IBSYMBOLERR] = crp_ibsymbolerr,
4376 [QIBPORTCNTR_INVALIDRLEN] = crp_invalidrlen,
4377 [QIBPORTCNTR_UNSUPVL] = crp_txunsupvl,
4378 [QIBPORTCNTR_EXCESSBUFOVFL] = crp_excessbufferovfl,
4379 [QIBPORTCNTR_ERRLINK] = crp_errlink,
4380 [QIBPORTCNTR_IBLINKDOWN] = crp_iblinkdown,
4381 [QIBPORTCNTR_IBLINKERRRECOV] = crp_iblinkerrrecov,
4382 [QIBPORTCNTR_LLI] = crp_locallinkintegrityerr,
4383 [QIBPORTCNTR_VL15PKTDROP] = crp_vl15droppedpkt,
4384 [QIBPORTCNTR_ERRPKEY] = crp_errpkey,
4385 /*
4386 * the next 3 aren't really counters, but were implemented
4387 * as counters in older chips, so still get accessed as
4388 * though they were counters from this code.
4389 */
4390 [QIBPORTCNTR_PSINTERVAL] = krp_psinterval,
4391 [QIBPORTCNTR_PSSTART] = krp_psstart,
4392 [QIBPORTCNTR_PSSTAT] = krp_psstat,
4393 /* pseudo-counter, summed for all ports */
4394 [QIBPORTCNTR_KHDROVFL] = 0xffff,
4395 };
4396
4397 if (reg >= ARRAY_SIZE(xlator)) {
4398 qib_devinfo(ppd->dd->pcidev,
4399 "Unimplemented portcounter %u\n", reg);
4400 goto done;
4401 }
4402 creg = xlator[reg] & _PORT_CNTR_IDXMASK;
4403
4404 /* handle non-counters and special cases first */
4405 if (reg == QIBPORTCNTR_KHDROVFL) {
4406 int i;
4407
4408 /* sum over all kernel contexts (skip if mini_init) */
4409 for (i = 0; dd->rcd && i < dd->first_user_ctxt; i++) {
4410 struct qib_ctxtdata *rcd = dd->rcd[i];
4411
4412 if (!rcd || rcd->ppd != ppd)
4413 continue;
4414 ret += read_7322_creg32(dd, cr_base_egrovfl + i);
4415 }
4416 goto done;
4417 } else if (reg == QIBPORTCNTR_RXDROPPKT) {
4418 /*
4419 * Used as part of the synthesis of port_rcv_errors
4420 * in the verbs code for IBTA counters. Not needed for 7322,
4421 * because all the errors are already counted by other cntrs.
4422 */
4423 goto done;
4424 } else if (reg == QIBPORTCNTR_PSINTERVAL ||
4425 reg == QIBPORTCNTR_PSSTART || reg == QIBPORTCNTR_PSSTAT) {
4426 /* were counters in older chips, now per-port kernel regs */
4427 ret = qib_read_kreg_port(ppd, creg);
4428 goto done;
4429 }
4430
4431 /*
4432 * Only fast increment counters are 64 bits; use 32 bit reads to
4433 * avoid two independent reads when on Opteron.
4434 */
4435 if (xlator[reg] & _PORT_64BIT_FLAG)
4436 ret = read_7322_creg_port(ppd, creg);
4437 else
4438 ret = read_7322_creg32_port(ppd, creg);
4439 if (creg == crp_ibsymbolerr) {
4440 if (ppd->cpspec->ibdeltainprog)
4441 ret -= ret - ppd->cpspec->ibsymsnap;
4442 ret -= ppd->cpspec->ibsymdelta;
4443 } else if (creg == crp_iblinkerrrecov) {
4444 if (ppd->cpspec->ibdeltainprog)
4445 ret -= ret - ppd->cpspec->iblnkerrsnap;
4446 ret -= ppd->cpspec->iblnkerrdelta;
4447 } else if (creg == crp_errlink)
4448 ret -= ppd->cpspec->ibmalfdelta;
4449 else if (creg == crp_iblinkdown)
4450 ret += ppd->cpspec->iblnkdowndelta;
4451 done:
4452 return ret;
4453 }
4454
4455 /*
4456 * Device counter names (not port-specific), one line per stat,
4457 * single string. Used by utilities like ipathstats to print the stats
4458 * in a way which works for different versions of drivers, without changing
4459 * the utility. Names need to be 12 chars or less (w/o newline), for proper
4460 * display by utility.
4461 * Non-error counters are first.
4462 * Start of "error" conters is indicated by a leading "E " on the first
4463 * "error" counter, and doesn't count in label length.
4464 * The EgrOvfl list needs to be last so we truncate them at the configured
4465 * context count for the device.
4466 * cntr7322indices contains the corresponding register indices.
4467 */
4468 static const char cntr7322names[] =
4469 "Interrupts\n"
4470 "HostBusStall\n"
4471 "E RxTIDFull\n"
4472 "RxTIDInvalid\n"
4473 "RxTIDFloDrop\n" /* 7322 only */
4474 "Ctxt0EgrOvfl\n"
4475 "Ctxt1EgrOvfl\n"
4476 "Ctxt2EgrOvfl\n"
4477 "Ctxt3EgrOvfl\n"
4478 "Ctxt4EgrOvfl\n"
4479 "Ctxt5EgrOvfl\n"
4480 "Ctxt6EgrOvfl\n"
4481 "Ctxt7EgrOvfl\n"
4482 "Ctxt8EgrOvfl\n"
4483 "Ctxt9EgrOvfl\n"
4484 "Ctx10EgrOvfl\n"
4485 "Ctx11EgrOvfl\n"
4486 "Ctx12EgrOvfl\n"
4487 "Ctx13EgrOvfl\n"
4488 "Ctx14EgrOvfl\n"
4489 "Ctx15EgrOvfl\n"
4490 "Ctx16EgrOvfl\n"
4491 "Ctx17EgrOvfl\n"
4492 ;
4493
4494 static const u32 cntr7322indices[] = {
4495 cr_lbint | _PORT_64BIT_FLAG,
4496 cr_lbstall | _PORT_64BIT_FLAG,
4497 cr_tidfull,
4498 cr_tidinvalid,
4499 cr_rxtidflowdrop,
4500 cr_base_egrovfl + 0,
4501 cr_base_egrovfl + 1,
4502 cr_base_egrovfl + 2,
4503 cr_base_egrovfl + 3,
4504 cr_base_egrovfl + 4,
4505 cr_base_egrovfl + 5,
4506 cr_base_egrovfl + 6,
4507 cr_base_egrovfl + 7,
4508 cr_base_egrovfl + 8,
4509 cr_base_egrovfl + 9,
4510 cr_base_egrovfl + 10,
4511 cr_base_egrovfl + 11,
4512 cr_base_egrovfl + 12,
4513 cr_base_egrovfl + 13,
4514 cr_base_egrovfl + 14,
4515 cr_base_egrovfl + 15,
4516 cr_base_egrovfl + 16,
4517 cr_base_egrovfl + 17,
4518 };
4519
4520 /*
4521 * same as cntr7322names and cntr7322indices, but for port-specific counters.
4522 * portcntr7322indices is somewhat complicated by some registers needing
4523 * adjustments of various kinds, and those are ORed with _PORT_VIRT_FLAG
4524 */
4525 static const char portcntr7322names[] =
4526 "TxPkt\n"
4527 "TxFlowPkt\n"
4528 "TxWords\n"
4529 "RxPkt\n"
4530 "RxFlowPkt\n"
4531 "RxWords\n"
4532 "TxFlowStall\n"
4533 "TxDmaDesc\n" /* 7220 and 7322-only */
4534 "E RxDlidFltr\n" /* 7220 and 7322-only */
4535 "IBStatusChng\n"
4536 "IBLinkDown\n"
4537 "IBLnkRecov\n"
4538 "IBRxLinkErr\n"
4539 "IBSymbolErr\n"
4540 "RxLLIErr\n"
4541 "RxBadFormat\n"
4542 "RxBadLen\n"
4543 "RxBufOvrfl\n"
4544 "RxEBP\n"
4545 "RxFlowCtlErr\n"
4546 "RxICRCerr\n"
4547 "RxLPCRCerr\n"
4548 "RxVCRCerr\n"
4549 "RxInvalLen\n"
4550 "RxInvalPKey\n"
4551 "RxPktDropped\n"
4552 "TxBadLength\n"
4553 "TxDropped\n"
4554 "TxInvalLen\n"
4555 "TxUnderrun\n"
4556 "TxUnsupVL\n"
4557 "RxLclPhyErr\n" /* 7220 and 7322-only from here down */
4558 "RxVL15Drop\n"
4559 "RxVlErr\n"
4560 "XcessBufOvfl\n"
4561 "RxQPBadCtxt\n" /* 7322-only from here down */
4562 "TXBadHeader\n"
4563 ;
4564
4565 static const u32 portcntr7322indices[] = {
4566 QIBPORTCNTR_PKTSEND | _PORT_VIRT_FLAG,
4567 crp_pktsendflow,
4568 QIBPORTCNTR_WORDSEND | _PORT_VIRT_FLAG,
4569 QIBPORTCNTR_PKTRCV | _PORT_VIRT_FLAG,
4570 crp_pktrcvflowctrl,
4571 QIBPORTCNTR_WORDRCV | _PORT_VIRT_FLAG,
4572 QIBPORTCNTR_SENDSTALL | _PORT_VIRT_FLAG,
4573 crp_txsdmadesc | _PORT_64BIT_FLAG,
4574 crp_rxdlidfltr,
4575 crp_ibstatuschange,
4576 QIBPORTCNTR_IBLINKDOWN | _PORT_VIRT_FLAG,
4577 QIBPORTCNTR_IBLINKERRRECOV | _PORT_VIRT_FLAG,
4578 QIBPORTCNTR_ERRLINK | _PORT_VIRT_FLAG,
4579 QIBPORTCNTR_IBSYMBOLERR | _PORT_VIRT_FLAG,
4580 QIBPORTCNTR_LLI | _PORT_VIRT_FLAG,
4581 QIBPORTCNTR_BADFORMAT | _PORT_VIRT_FLAG,
4582 QIBPORTCNTR_ERR_RLEN | _PORT_VIRT_FLAG,
4583 QIBPORTCNTR_RCVOVFL | _PORT_VIRT_FLAG,
4584 QIBPORTCNTR_RCVEBP | _PORT_VIRT_FLAG,
4585 crp_rcvflowctrlviol,
4586 QIBPORTCNTR_ERRICRC | _PORT_VIRT_FLAG,
4587 QIBPORTCNTR_ERRLPCRC | _PORT_VIRT_FLAG,
4588 QIBPORTCNTR_ERRVCRC | _PORT_VIRT_FLAG,
4589 QIBPORTCNTR_INVALIDRLEN | _PORT_VIRT_FLAG,
4590 QIBPORTCNTR_ERRPKEY | _PORT_VIRT_FLAG,
4591 QIBPORTCNTR_RXDROPPKT | _PORT_VIRT_FLAG,
4592 crp_txminmaxlenerr,
4593 crp_txdroppedpkt,
4594 crp_txlenerr,
4595 crp_txunderrun,
4596 crp_txunsupvl,
4597 QIBPORTCNTR_RXLOCALPHYERR | _PORT_VIRT_FLAG,
4598 QIBPORTCNTR_VL15PKTDROP | _PORT_VIRT_FLAG,
4599 QIBPORTCNTR_RXVLERR | _PORT_VIRT_FLAG,
4600 QIBPORTCNTR_EXCESSBUFOVFL | _PORT_VIRT_FLAG,
4601 crp_rxqpinvalidctxt,
4602 crp_txhdrerr,
4603 };
4604
4605 /* do all the setup to make the counter reads efficient later */
4606 static void init_7322_cntrnames(struct qib_devdata *dd)
4607 {
4608 int i, j = 0;
4609 char *s;
4610
4611 for (i = 0, s = (char *)cntr7322names; s && j <= dd->cfgctxts;
4612 i++) {
4613 /* we always have at least one counter before the egrovfl */
4614 if (!j && !strncmp("Ctxt0EgrOvfl", s + 1, 12))
4615 j = 1;
4616 s = strchr(s + 1, '\n');
4617 if (s && j)
4618 j++;
4619 }
4620 dd->cspec->ncntrs = i;
4621 if (!s)
4622 /* full list; size is without terminating null */
4623 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1;
4624 else
4625 dd->cspec->cntrnamelen = 1 + s - cntr7322names;
4626 dd->cspec->cntrs = kmalloc(dd->cspec->ncntrs
4627 * sizeof(u64), GFP_KERNEL);
4628 if (!dd->cspec->cntrs)
4629 qib_dev_err(dd, "Failed allocation for counters\n");
4630
4631 for (i = 0, s = (char *)portcntr7322names; s; i++)
4632 s = strchr(s + 1, '\n');
4633 dd->cspec->nportcntrs = i - 1;
4634 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1;
4635 for (i = 0; i < dd->num_pports; ++i) {
4636 dd->pport[i].cpspec->portcntrs = kmalloc(dd->cspec->nportcntrs
4637 * sizeof(u64), GFP_KERNEL);
4638 if (!dd->pport[i].cpspec->portcntrs)
4639 qib_dev_err(dd, "Failed allocation for"
4640 " portcounters\n");
4641 }
4642 }
4643
4644 static u32 qib_read_7322cntrs(struct qib_devdata *dd, loff_t pos, char **namep,
4645 u64 **cntrp)
4646 {
4647 u32 ret;
4648
4649 if (namep) {
4650 ret = dd->cspec->cntrnamelen;
4651 if (pos >= ret)
4652 ret = 0; /* final read after getting everything */
4653 else
4654 *namep = (char *) cntr7322names;
4655 } else {
4656 u64 *cntr = dd->cspec->cntrs;
4657 int i;
4658
4659 ret = dd->cspec->ncntrs * sizeof(u64);
4660 if (!cntr || pos >= ret) {
4661 /* everything read, or couldn't get memory */
4662 ret = 0;
4663 goto done;
4664 }
4665 *cntrp = cntr;
4666 for (i = 0; i < dd->cspec->ncntrs; i++)
4667 if (cntr7322indices[i] & _PORT_64BIT_FLAG)
4668 *cntr++ = read_7322_creg(dd,
4669 cntr7322indices[i] &
4670 _PORT_CNTR_IDXMASK);
4671 else
4672 *cntr++ = read_7322_creg32(dd,
4673 cntr7322indices[i]);
4674 }
4675 done:
4676 return ret;
4677 }
4678
4679 static u32 qib_read_7322portcntrs(struct qib_devdata *dd, loff_t pos, u32 port,
4680 char **namep, u64 **cntrp)
4681 {
4682 u32 ret;
4683
4684 if (namep) {
4685 ret = dd->cspec->portcntrnamelen;
4686 if (pos >= ret)
4687 ret = 0; /* final read after getting everything */
4688 else
4689 *namep = (char *)portcntr7322names;
4690 } else {
4691 struct qib_pportdata *ppd = &dd->pport[port];
4692 u64 *cntr = ppd->cpspec->portcntrs;
4693 int i;
4694
4695 ret = dd->cspec->nportcntrs * sizeof(u64);
4696 if (!cntr || pos >= ret) {
4697 /* everything read, or couldn't get memory */
4698 ret = 0;
4699 goto done;
4700 }
4701 *cntrp = cntr;
4702 for (i = 0; i < dd->cspec->nportcntrs; i++) {
4703 if (portcntr7322indices[i] & _PORT_VIRT_FLAG)
4704 *cntr++ = qib_portcntr_7322(ppd,
4705 portcntr7322indices[i] &
4706 _PORT_CNTR_IDXMASK);
4707 else if (portcntr7322indices[i] & _PORT_64BIT_FLAG)
4708 *cntr++ = read_7322_creg_port(ppd,
4709 portcntr7322indices[i] &
4710 _PORT_CNTR_IDXMASK);
4711 else
4712 *cntr++ = read_7322_creg32_port(ppd,
4713 portcntr7322indices[i]);
4714 }
4715 }
4716 done:
4717 return ret;
4718 }
4719
4720 /**
4721 * qib_get_7322_faststats - get word counters from chip before they overflow
4722 * @opaque - contains a pointer to the qlogic_ib device qib_devdata
4723 *
4724 * VESTIGIAL IBA7322 has no "small fast counters", so the only
4725 * real purpose of this function is to maintain the notion of
4726 * "active time", which in turn is only logged into the eeprom,
4727 * which we don;t have, yet, for 7322-based boards.
4728 *
4729 * called from add_timer
4730 */
4731 static void qib_get_7322_faststats(unsigned long opaque)
4732 {
4733 struct qib_devdata *dd = (struct qib_devdata *) opaque;
4734 struct qib_pportdata *ppd;
4735 unsigned long flags;
4736 u64 traffic_wds;
4737 int pidx;
4738
4739 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
4740 ppd = dd->pport + pidx;
4741
4742 /*
4743 * If port isn't enabled or not operational ports, or
4744 * diags is running (can cause memory diags to fail)
4745 * skip this port this time.
4746 */
4747 if (!ppd->link_speed_supported || !(dd->flags & QIB_INITTED)
4748 || dd->diag_client)
4749 continue;
4750
4751 /*
4752 * Maintain an activity timer, based on traffic
4753 * exceeding a threshold, so we need to check the word-counts
4754 * even if they are 64-bit.
4755 */
4756 traffic_wds = qib_portcntr_7322(ppd, QIBPORTCNTR_WORDRCV) +
4757 qib_portcntr_7322(ppd, QIBPORTCNTR_WORDSEND);
4758 spin_lock_irqsave(&ppd->dd->eep_st_lock, flags);
4759 traffic_wds -= ppd->dd->traffic_wds;
4760 ppd->dd->traffic_wds += traffic_wds;
4761 if (traffic_wds >= QIB_TRAFFIC_ACTIVE_THRESHOLD)
4762 atomic_add(ACTIVITY_TIMER, &ppd->dd->active_time);
4763 spin_unlock_irqrestore(&ppd->dd->eep_st_lock, flags);
4764 if (ppd->cpspec->qdr_dfe_on && (ppd->link_speed_active &
4765 QIB_IB_QDR) &&
4766 (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
4767 QIBL_LINKACTIVE)) &&
4768 ppd->cpspec->qdr_dfe_time &&
4769 time_after64(get_jiffies_64(), ppd->cpspec->qdr_dfe_time)) {
4770 ppd->cpspec->qdr_dfe_on = 0;
4771
4772 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
4773 ppd->dd->cspec->r1 ?
4774 QDR_STATIC_ADAPT_INIT_R1 :
4775 QDR_STATIC_ADAPT_INIT);
4776 force_h1(ppd);
4777 }
4778 }
4779 mod_timer(&dd->stats_timer, jiffies + HZ * ACTIVITY_TIMER);
4780 }
4781
4782 /*
4783 * If we were using MSIx, try to fallback to INTx.
4784 */
4785 static int qib_7322_intr_fallback(struct qib_devdata *dd)
4786 {
4787 if (!dd->cspec->num_msix_entries)
4788 return 0; /* already using INTx */
4789
4790 qib_devinfo(dd->pcidev, "MSIx interrupt not detected,"
4791 " trying INTx interrupts\n");
4792 qib_7322_nomsix(dd);
4793 qib_enable_intx(dd->pcidev);
4794 qib_setup_7322_interrupt(dd, 0);
4795 return 1;
4796 }
4797
4798 /*
4799 * Reset the XGXS (between serdes and IBC). Slightly less intrusive
4800 * than resetting the IBC or external link state, and useful in some
4801 * cases to cause some retraining. To do this right, we reset IBC
4802 * as well, then return to previous state (which may be still in reset)
4803 * NOTE: some callers of this "know" this writes the current value
4804 * of cpspec->ibcctrl_a as part of it's operation, so if that changes,
4805 * check all callers.
4806 */
4807 static void qib_7322_mini_pcs_reset(struct qib_pportdata *ppd)
4808 {
4809 u64 val;
4810 struct qib_devdata *dd = ppd->dd;
4811 const u64 reset_bits = SYM_MASK(IBPCSConfig_0, xcv_rreset) |
4812 SYM_MASK(IBPCSConfig_0, xcv_treset) |
4813 SYM_MASK(IBPCSConfig_0, tx_rx_reset);
4814
4815 val = qib_read_kreg_port(ppd, krp_ib_pcsconfig);
4816 qib_write_kreg(dd, kr_hwerrmask,
4817 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop));
4818 qib_write_kreg_port(ppd, krp_ibcctrl_a,
4819 ppd->cpspec->ibcctrl_a &
4820 ~SYM_MASK(IBCCtrlA_0, IBLinkEn));
4821
4822 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val | reset_bits);
4823 qib_read_kreg32(dd, kr_scratch);
4824 qib_write_kreg_port(ppd, krp_ib_pcsconfig, val & ~reset_bits);
4825 qib_write_kreg_port(ppd, krp_ibcctrl_a, ppd->cpspec->ibcctrl_a);
4826 qib_write_kreg(dd, kr_scratch, 0ULL);
4827 qib_write_kreg(dd, kr_hwerrclear,
4828 SYM_MASK(HwErrClear, statusValidNoEopClear));
4829 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask);
4830 }
4831
4832 /*
4833 * This code for non-IBTA-compliant IB speed negotiation is only known to
4834 * work for the SDR to DDR transition, and only between an HCA and a switch
4835 * with recent firmware. It is based on observed heuristics, rather than
4836 * actual knowledge of the non-compliant speed negotiation.
4837 * It has a number of hard-coded fields, since the hope is to rewrite this
4838 * when a spec is available on how the negoation is intended to work.
4839 */
4840 static void autoneg_7322_sendpkt(struct qib_pportdata *ppd, u32 *hdr,
4841 u32 dcnt, u32 *data)
4842 {
4843 int i;
4844 u64 pbc;
4845 u32 __iomem *piobuf;
4846 u32 pnum, control, len;
4847 struct qib_devdata *dd = ppd->dd;
4848
4849 i = 0;
4850 len = 7 + dcnt + 1; /* 7 dword header, dword data, icrc */
4851 control = qib_7322_setpbc_control(ppd, len, 0, 15);
4852 pbc = ((u64) control << 32) | len;
4853 while (!(piobuf = qib_7322_getsendbuf(ppd, pbc, &pnum))) {
4854 if (i++ > 15)
4855 return;
4856 udelay(2);
4857 }
4858 /* disable header check on this packet, since it can't be valid */
4859 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_DIS1, NULL);
4860 writeq(pbc, piobuf);
4861 qib_flush_wc();
4862 qib_pio_copy(piobuf + 2, hdr, 7);
4863 qib_pio_copy(piobuf + 9, data, dcnt);
4864 if (dd->flags & QIB_USE_SPCL_TRIG) {
4865 u32 spcl_off = (pnum >= dd->piobcnt2k) ? 2047 : 1023;
4866
4867 qib_flush_wc();
4868 __raw_writel(0xaebecede, piobuf + spcl_off);
4869 }
4870 qib_flush_wc();
4871 qib_sendbuf_done(dd, pnum);
4872 /* and re-enable hdr check */
4873 dd->f_txchk_change(dd, pnum, 1, TXCHK_CHG_TYPE_ENAB1, NULL);
4874 }
4875
4876 /*
4877 * _start packet gets sent twice at start, _done gets sent twice at end
4878 */
4879 static void qib_autoneg_7322_send(struct qib_pportdata *ppd, int which)
4880 {
4881 struct qib_devdata *dd = ppd->dd;
4882 static u32 swapped;
4883 u32 dw, i, hcnt, dcnt, *data;
4884 static u32 hdr[7] = { 0xf002ffff, 0x48ffff, 0x6400abba };
4885 static u32 madpayload_start[0x40] = {
4886 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4887 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4888 0x1, 0x1388, 0x15e, 0x1, /* rest 0's */
4889 };
4890 static u32 madpayload_done[0x40] = {
4891 0x1810103, 0x1, 0x0, 0x0, 0x2c90000, 0x2c9, 0x0, 0x0,
4892 0xffffffff, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0,
4893 0x40000001, 0x1388, 0x15e, /* rest 0's */
4894 };
4895
4896 dcnt = ARRAY_SIZE(madpayload_start);
4897 hcnt = ARRAY_SIZE(hdr);
4898 if (!swapped) {
4899 /* for maintainability, do it at runtime */
4900 for (i = 0; i < hcnt; i++) {
4901 dw = (__force u32) cpu_to_be32(hdr[i]);
4902 hdr[i] = dw;
4903 }
4904 for (i = 0; i < dcnt; i++) {
4905 dw = (__force u32) cpu_to_be32(madpayload_start[i]);
4906 madpayload_start[i] = dw;
4907 dw = (__force u32) cpu_to_be32(madpayload_done[i]);
4908 madpayload_done[i] = dw;
4909 }
4910 swapped = 1;
4911 }
4912
4913 data = which ? madpayload_done : madpayload_start;
4914
4915 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4916 qib_read_kreg64(dd, kr_scratch);
4917 udelay(2);
4918 autoneg_7322_sendpkt(ppd, hdr, dcnt, data);
4919 qib_read_kreg64(dd, kr_scratch);
4920 udelay(2);
4921 }
4922
4923 /*
4924 * Do the absolute minimum to cause an IB speed change, and make it
4925 * ready, but don't actually trigger the change. The caller will
4926 * do that when ready (if link is in Polling training state, it will
4927 * happen immediately, otherwise when link next goes down)
4928 *
4929 * This routine should only be used as part of the DDR autonegotation
4930 * code for devices that are not compliant with IB 1.2 (or code that
4931 * fixes things up for same).
4932 *
4933 * When link has gone down, and autoneg enabled, or autoneg has
4934 * failed and we give up until next time we set both speeds, and
4935 * then we want IBTA enabled as well as "use max enabled speed.
4936 */
4937 static void set_7322_ibspeed_fast(struct qib_pportdata *ppd, u32 speed)
4938 {
4939 u64 newctrlb;
4940 newctrlb = ppd->cpspec->ibcctrl_b & ~(IBA7322_IBC_SPEED_MASK |
4941 IBA7322_IBC_IBTA_1_2_MASK |
4942 IBA7322_IBC_MAX_SPEED_MASK);
4943
4944 if (speed & (speed - 1)) /* multiple speeds */
4945 newctrlb |= (speed << IBA7322_IBC_SPEED_LSB) |
4946 IBA7322_IBC_IBTA_1_2_MASK |
4947 IBA7322_IBC_MAX_SPEED_MASK;
4948 else
4949 newctrlb |= speed == QIB_IB_QDR ?
4950 IBA7322_IBC_SPEED_QDR | IBA7322_IBC_IBTA_1_2_MASK :
4951 ((speed == QIB_IB_DDR ?
4952 IBA7322_IBC_SPEED_DDR : IBA7322_IBC_SPEED_SDR));
4953
4954 if (newctrlb == ppd->cpspec->ibcctrl_b)
4955 return;
4956
4957 ppd->cpspec->ibcctrl_b = newctrlb;
4958 qib_write_kreg_port(ppd, krp_ibcctrl_b, ppd->cpspec->ibcctrl_b);
4959 qib_write_kreg(ppd->dd, kr_scratch, 0);
4960 }
4961
4962 /*
4963 * This routine is only used when we are not talking to another
4964 * IB 1.2-compliant device that we think can do DDR.
4965 * (This includes all existing switch chips as of Oct 2007.)
4966 * 1.2-compliant devices go directly to DDR prior to reaching INIT
4967 */
4968 static void try_7322_autoneg(struct qib_pportdata *ppd)
4969 {
4970 unsigned long flags;
4971
4972 spin_lock_irqsave(&ppd->lflags_lock, flags);
4973 ppd->lflags |= QIBL_IB_AUTONEG_INPROG;
4974 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
4975 qib_autoneg_7322_send(ppd, 0);
4976 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
4977 qib_7322_mini_pcs_reset(ppd);
4978 /* 2 msec is minimum length of a poll cycle */
4979 queue_delayed_work(ib_wq, &ppd->cpspec->autoneg_work,
4980 msecs_to_jiffies(2));
4981 }
4982
4983 /*
4984 * Handle the empirically determined mechanism for auto-negotiation
4985 * of DDR speed with switches.
4986 */
4987 static void autoneg_7322_work(struct work_struct *work)
4988 {
4989 struct qib_pportdata *ppd;
4990 struct qib_devdata *dd;
4991 u64 startms;
4992 u32 i;
4993 unsigned long flags;
4994
4995 ppd = container_of(work, struct qib_chippport_specific,
4996 autoneg_work.work)->ppd;
4997 dd = ppd->dd;
4998
4999 startms = jiffies_to_msecs(jiffies);
5000
5001 /*
5002 * Busy wait for this first part, it should be at most a
5003 * few hundred usec, since we scheduled ourselves for 2msec.
5004 */
5005 for (i = 0; i < 25; i++) {
5006 if (SYM_FIELD(ppd->lastibcstat, IBCStatusA_0, LinkState)
5007 == IB_7322_LT_STATE_POLLQUIET) {
5008 qib_set_linkstate(ppd, QIB_IB_LINKDOWN_DISABLE);
5009 break;
5010 }
5011 udelay(100);
5012 }
5013
5014 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG))
5015 goto done; /* we got there early or told to stop */
5016
5017 /* we expect this to timeout */
5018 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5019 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5020 msecs_to_jiffies(90)))
5021 goto done;
5022 qib_7322_mini_pcs_reset(ppd);
5023
5024 /* we expect this to timeout */
5025 if (wait_event_timeout(ppd->cpspec->autoneg_wait,
5026 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5027 msecs_to_jiffies(1700)))
5028 goto done;
5029 qib_7322_mini_pcs_reset(ppd);
5030
5031 set_7322_ibspeed_fast(ppd, QIB_IB_SDR);
5032
5033 /*
5034 * Wait up to 250 msec for link to train and get to INIT at DDR;
5035 * this should terminate early.
5036 */
5037 wait_event_timeout(ppd->cpspec->autoneg_wait,
5038 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG),
5039 msecs_to_jiffies(250));
5040 done:
5041 if (ppd->lflags & QIBL_IB_AUTONEG_INPROG) {
5042 spin_lock_irqsave(&ppd->lflags_lock, flags);
5043 ppd->lflags &= ~QIBL_IB_AUTONEG_INPROG;
5044 if (ppd->cpspec->autoneg_tries == AUTONEG_TRIES) {
5045 ppd->lflags |= QIBL_IB_AUTONEG_FAILED;
5046 ppd->cpspec->autoneg_tries = 0;
5047 }
5048 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5049 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5050 }
5051 }
5052
5053 /*
5054 * This routine is used to request IPG set in the QLogic switch.
5055 * Only called if r1.
5056 */
5057 static void try_7322_ipg(struct qib_pportdata *ppd)
5058 {
5059 struct qib_ibport *ibp = &ppd->ibport_data;
5060 struct ib_mad_send_buf *send_buf;
5061 struct ib_mad_agent *agent;
5062 struct ib_smp *smp;
5063 unsigned delay;
5064 int ret;
5065
5066 agent = ibp->send_agent;
5067 if (!agent)
5068 goto retry;
5069
5070 send_buf = ib_create_send_mad(agent, 0, 0, 0, IB_MGMT_MAD_HDR,
5071 IB_MGMT_MAD_DATA, GFP_ATOMIC);
5072 if (IS_ERR(send_buf))
5073 goto retry;
5074
5075 if (!ibp->smi_ah) {
5076 struct ib_ah_attr attr;
5077 struct ib_ah *ah;
5078
5079 memset(&attr, 0, sizeof attr);
5080 attr.dlid = be16_to_cpu(IB_LID_PERMISSIVE);
5081 attr.port_num = ppd->port;
5082 ah = ib_create_ah(ibp->qp0->ibqp.pd, &attr);
5083 if (IS_ERR(ah))
5084 ret = -EINVAL;
5085 else {
5086 send_buf->ah = ah;
5087 ibp->smi_ah = to_iah(ah);
5088 ret = 0;
5089 }
5090 } else {
5091 send_buf->ah = &ibp->smi_ah->ibah;
5092 ret = 0;
5093 }
5094
5095 smp = send_buf->mad;
5096 smp->base_version = IB_MGMT_BASE_VERSION;
5097 smp->mgmt_class = IB_MGMT_CLASS_SUBN_DIRECTED_ROUTE;
5098 smp->class_version = 1;
5099 smp->method = IB_MGMT_METHOD_SEND;
5100 smp->hop_cnt = 1;
5101 smp->attr_id = QIB_VENDOR_IPG;
5102 smp->attr_mod = 0;
5103
5104 if (!ret)
5105 ret = ib_post_send_mad(send_buf, NULL);
5106 if (ret)
5107 ib_free_send_mad(send_buf);
5108 retry:
5109 delay = 2 << ppd->cpspec->ipg_tries;
5110 queue_delayed_work(ib_wq, &ppd->cpspec->ipg_work,
5111 msecs_to_jiffies(delay));
5112 }
5113
5114 /*
5115 * Timeout handler for setting IPG.
5116 * Only called if r1.
5117 */
5118 static void ipg_7322_work(struct work_struct *work)
5119 {
5120 struct qib_pportdata *ppd;
5121
5122 ppd = container_of(work, struct qib_chippport_specific,
5123 ipg_work.work)->ppd;
5124 if ((ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED | QIBL_LINKACTIVE))
5125 && ++ppd->cpspec->ipg_tries <= 10)
5126 try_7322_ipg(ppd);
5127 }
5128
5129 static u32 qib_7322_iblink_state(u64 ibcs)
5130 {
5131 u32 state = (u32)SYM_FIELD(ibcs, IBCStatusA_0, LinkState);
5132
5133 switch (state) {
5134 case IB_7322_L_STATE_INIT:
5135 state = IB_PORT_INIT;
5136 break;
5137 case IB_7322_L_STATE_ARM:
5138 state = IB_PORT_ARMED;
5139 break;
5140 case IB_7322_L_STATE_ACTIVE:
5141 /* fall through */
5142 case IB_7322_L_STATE_ACT_DEFER:
5143 state = IB_PORT_ACTIVE;
5144 break;
5145 default: /* fall through */
5146 case IB_7322_L_STATE_DOWN:
5147 state = IB_PORT_DOWN;
5148 break;
5149 }
5150 return state;
5151 }
5152
5153 /* returns the IBTA port state, rather than the IBC link training state */
5154 static u8 qib_7322_phys_portstate(u64 ibcs)
5155 {
5156 u8 state = (u8)SYM_FIELD(ibcs, IBCStatusA_0, LinkTrainingState);
5157 return qib_7322_physportstate[state];
5158 }
5159
5160 static int qib_7322_ib_updown(struct qib_pportdata *ppd, int ibup, u64 ibcs)
5161 {
5162 int ret = 0, symadj = 0;
5163 unsigned long flags;
5164 int mult;
5165
5166 spin_lock_irqsave(&ppd->lflags_lock, flags);
5167 ppd->lflags &= ~QIBL_IB_FORCE_NOTIFY;
5168 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5169
5170 /* Update our picture of width and speed from chip */
5171 if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedQDR)) {
5172 ppd->link_speed_active = QIB_IB_QDR;
5173 mult = 4;
5174 } else if (ibcs & SYM_MASK(IBCStatusA_0, LinkSpeedActive)) {
5175 ppd->link_speed_active = QIB_IB_DDR;
5176 mult = 2;
5177 } else {
5178 ppd->link_speed_active = QIB_IB_SDR;
5179 mult = 1;
5180 }
5181 if (ibcs & SYM_MASK(IBCStatusA_0, LinkWidthActive)) {
5182 ppd->link_width_active = IB_WIDTH_4X;
5183 mult *= 4;
5184 } else
5185 ppd->link_width_active = IB_WIDTH_1X;
5186 ppd->delay_mult = ib_rate_to_delay[mult_to_ib_rate(mult)];
5187
5188 if (!ibup) {
5189 u64 clr;
5190
5191 /* Link went down. */
5192 /* do IPG MAD again after linkdown, even if last time failed */
5193 ppd->cpspec->ipg_tries = 0;
5194 clr = qib_read_kreg_port(ppd, krp_ibcstatus_b) &
5195 (SYM_MASK(IBCStatusB_0, heartbeat_timed_out) |
5196 SYM_MASK(IBCStatusB_0, heartbeat_crosstalk));
5197 if (clr)
5198 qib_write_kreg_port(ppd, krp_ibcstatus_b, clr);
5199 if (!(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5200 QIBL_IB_AUTONEG_INPROG)))
5201 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5202 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5203 /* unlock the Tx settings, speed may change */
5204 qib_write_kreg_port(ppd, krp_tx_deemph_override,
5205 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
5206 reset_tx_deemphasis_override));
5207 qib_cancel_sends(ppd);
5208 /* on link down, ensure sane pcs state */
5209 qib_7322_mini_pcs_reset(ppd);
5210 spin_lock_irqsave(&ppd->sdma_lock, flags);
5211 if (__qib_sdma_running(ppd))
5212 __qib_sdma_process_event(ppd,
5213 qib_sdma_event_e70_go_idle);
5214 spin_unlock_irqrestore(&ppd->sdma_lock, flags);
5215 }
5216 clr = read_7322_creg32_port(ppd, crp_iblinkdown);
5217 if (clr == ppd->cpspec->iblnkdownsnap)
5218 ppd->cpspec->iblnkdowndelta++;
5219 } else {
5220 if (qib_compat_ddr_negotiate &&
5221 !(ppd->lflags & (QIBL_IB_AUTONEG_FAILED |
5222 QIBL_IB_AUTONEG_INPROG)) &&
5223 ppd->link_speed_active == QIB_IB_SDR &&
5224 (ppd->link_speed_enabled & QIB_IB_DDR)
5225 && ppd->cpspec->autoneg_tries < AUTONEG_TRIES) {
5226 /* we are SDR, and auto-negotiation enabled */
5227 ++ppd->cpspec->autoneg_tries;
5228 if (!ppd->cpspec->ibdeltainprog) {
5229 ppd->cpspec->ibdeltainprog = 1;
5230 ppd->cpspec->ibsymdelta +=
5231 read_7322_creg32_port(ppd,
5232 crp_ibsymbolerr) -
5233 ppd->cpspec->ibsymsnap;
5234 ppd->cpspec->iblnkerrdelta +=
5235 read_7322_creg32_port(ppd,
5236 crp_iblinkerrrecov) -
5237 ppd->cpspec->iblnkerrsnap;
5238 }
5239 try_7322_autoneg(ppd);
5240 ret = 1; /* no other IB status change processing */
5241 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5242 ppd->link_speed_active == QIB_IB_SDR) {
5243 qib_autoneg_7322_send(ppd, 1);
5244 set_7322_ibspeed_fast(ppd, QIB_IB_DDR);
5245 qib_7322_mini_pcs_reset(ppd);
5246 udelay(2);
5247 ret = 1; /* no other IB status change processing */
5248 } else if ((ppd->lflags & QIBL_IB_AUTONEG_INPROG) &&
5249 (ppd->link_speed_active & QIB_IB_DDR)) {
5250 spin_lock_irqsave(&ppd->lflags_lock, flags);
5251 ppd->lflags &= ~(QIBL_IB_AUTONEG_INPROG |
5252 QIBL_IB_AUTONEG_FAILED);
5253 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5254 ppd->cpspec->autoneg_tries = 0;
5255 /* re-enable SDR, for next link down */
5256 set_7322_ibspeed_fast(ppd, ppd->link_speed_enabled);
5257 wake_up(&ppd->cpspec->autoneg_wait);
5258 symadj = 1;
5259 } else if (ppd->lflags & QIBL_IB_AUTONEG_FAILED) {
5260 /*
5261 * Clear autoneg failure flag, and do setup
5262 * so we'll try next time link goes down and
5263 * back to INIT (possibly connected to a
5264 * different device).
5265 */
5266 spin_lock_irqsave(&ppd->lflags_lock, flags);
5267 ppd->lflags &= ~QIBL_IB_AUTONEG_FAILED;
5268 spin_unlock_irqrestore(&ppd->lflags_lock, flags);
5269 ppd->cpspec->ibcctrl_b |= IBA7322_IBC_IBTA_1_2_MASK;
5270 symadj = 1;
5271 }
5272 if (!(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5273 symadj = 1;
5274 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10)
5275 try_7322_ipg(ppd);
5276 if (!ppd->cpspec->recovery_init)
5277 setup_7322_link_recovery(ppd, 0);
5278 ppd->cpspec->qdr_dfe_time = jiffies +
5279 msecs_to_jiffies(QDR_DFE_DISABLE_DELAY);
5280 }
5281 ppd->cpspec->ibmalfusesnap = 0;
5282 ppd->cpspec->ibmalfsnap = read_7322_creg32_port(ppd,
5283 crp_errlink);
5284 }
5285 if (symadj) {
5286 ppd->cpspec->iblnkdownsnap =
5287 read_7322_creg32_port(ppd, crp_iblinkdown);
5288 if (ppd->cpspec->ibdeltainprog) {
5289 ppd->cpspec->ibdeltainprog = 0;
5290 ppd->cpspec->ibsymdelta += read_7322_creg32_port(ppd,
5291 crp_ibsymbolerr) - ppd->cpspec->ibsymsnap;
5292 ppd->cpspec->iblnkerrdelta += read_7322_creg32_port(ppd,
5293 crp_iblinkerrrecov) - ppd->cpspec->iblnkerrsnap;
5294 }
5295 } else if (!ibup && qib_compat_ddr_negotiate &&
5296 !ppd->cpspec->ibdeltainprog &&
5297 !(ppd->lflags & QIBL_IB_AUTONEG_INPROG)) {
5298 ppd->cpspec->ibdeltainprog = 1;
5299 ppd->cpspec->ibsymsnap = read_7322_creg32_port(ppd,
5300 crp_ibsymbolerr);
5301 ppd->cpspec->iblnkerrsnap = read_7322_creg32_port(ppd,
5302 crp_iblinkerrrecov);
5303 }
5304
5305 if (!ret)
5306 qib_setup_7322_setextled(ppd, ibup);
5307 return ret;
5308 }
5309
5310 /*
5311 * Does read/modify/write to appropriate registers to
5312 * set output and direction bits selected by mask.
5313 * these are in their canonical postions (e.g. lsb of
5314 * dir will end up in D48 of extctrl on existing chips).
5315 * returns contents of GP Inputs.
5316 */
5317 static int gpio_7322_mod(struct qib_devdata *dd, u32 out, u32 dir, u32 mask)
5318 {
5319 u64 read_val, new_out;
5320 unsigned long flags;
5321
5322 if (mask) {
5323 /* some bits being written, lock access to GPIO */
5324 dir &= mask;
5325 out &= mask;
5326 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5327 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe));
5328 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe));
5329 new_out = (dd->cspec->gpio_out & ~mask) | out;
5330
5331 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5332 qib_write_kreg(dd, kr_gpio_out, new_out);
5333 dd->cspec->gpio_out = new_out;
5334 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5335 }
5336 /*
5337 * It is unlikely that a read at this time would get valid
5338 * data on a pin whose direction line was set in the same
5339 * call to this function. We include the read here because
5340 * that allows us to potentially combine a change on one pin with
5341 * a read on another, and because the old code did something like
5342 * this.
5343 */
5344 read_val = qib_read_kreg64(dd, kr_extstatus);
5345 return SYM_FIELD(read_val, EXTStatus, GPIOIn);
5346 }
5347
5348 /* Enable writes to config EEPROM, if possible. Returns previous state */
5349 static int qib_7322_eeprom_wen(struct qib_devdata *dd, int wen)
5350 {
5351 int prev_wen;
5352 u32 mask;
5353
5354 mask = 1 << QIB_EEPROM_WEN_NUM;
5355 prev_wen = ~gpio_7322_mod(dd, 0, 0, 0) >> QIB_EEPROM_WEN_NUM;
5356 gpio_7322_mod(dd, wen ? 0 : mask, mask, mask);
5357
5358 return prev_wen & 1;
5359 }
5360
5361 /*
5362 * Read fundamental info we need to use the chip. These are
5363 * the registers that describe chip capabilities, and are
5364 * saved in shadow registers.
5365 */
5366 static void get_7322_chip_params(struct qib_devdata *dd)
5367 {
5368 u64 val;
5369 u32 piobufs;
5370 int mtu;
5371
5372 dd->palign = qib_read_kreg32(dd, kr_pagealign);
5373
5374 dd->uregbase = qib_read_kreg32(dd, kr_userregbase);
5375
5376 dd->rcvtidcnt = qib_read_kreg32(dd, kr_rcvtidcnt);
5377 dd->rcvtidbase = qib_read_kreg32(dd, kr_rcvtidbase);
5378 dd->rcvegrbase = qib_read_kreg32(dd, kr_rcvegrbase);
5379 dd->piobufbase = qib_read_kreg64(dd, kr_sendpiobufbase);
5380 dd->pio2k_bufbase = dd->piobufbase & 0xffffffff;
5381
5382 val = qib_read_kreg64(dd, kr_sendpiobufcnt);
5383 dd->piobcnt2k = val & ~0U;
5384 dd->piobcnt4k = val >> 32;
5385 val = qib_read_kreg64(dd, kr_sendpiosize);
5386 dd->piosize2k = val & ~0U;
5387 dd->piosize4k = val >> 32;
5388
5389 mtu = ib_mtu_enum_to_int(qib_ibmtu);
5390 if (mtu == -1)
5391 mtu = QIB_DEFAULT_MTU;
5392 dd->pport[0].ibmtu = (u32)mtu;
5393 dd->pport[1].ibmtu = (u32)mtu;
5394
5395 /* these may be adjusted in init_chip_wc_pat() */
5396 dd->pio2kbase = (u32 __iomem *)
5397 ((char __iomem *) dd->kregbase + dd->pio2k_bufbase);
5398 dd->pio4kbase = (u32 __iomem *)
5399 ((char __iomem *) dd->kregbase +
5400 (dd->piobufbase >> 32));
5401 /*
5402 * 4K buffers take 2 pages; we use roundup just to be
5403 * paranoid; we calculate it once here, rather than on
5404 * ever buf allocate
5405 */
5406 dd->align4k = ALIGN(dd->piosize4k, dd->palign);
5407
5408 piobufs = dd->piobcnt4k + dd->piobcnt2k + NUM_VL15_BUFS;
5409
5410 dd->pioavregs = ALIGN(piobufs, sizeof(u64) * BITS_PER_BYTE / 2) /
5411 (sizeof(u64) * BITS_PER_BYTE / 2);
5412 }
5413
5414 /*
5415 * The chip base addresses in cspec and cpspec have to be set
5416 * after possible init_chip_wc_pat(), rather than in
5417 * get_7322_chip_params(), so split out as separate function
5418 */
5419 static void qib_7322_set_baseaddrs(struct qib_devdata *dd)
5420 {
5421 u32 cregbase;
5422 cregbase = qib_read_kreg32(dd, kr_counterregbase);
5423
5424 dd->cspec->cregbase = (u64 __iomem *)(cregbase +
5425 (char __iomem *)dd->kregbase);
5426
5427 dd->egrtidbase = (u64 __iomem *)
5428 ((char __iomem *) dd->kregbase + dd->rcvegrbase);
5429
5430 /* port registers are defined as relative to base of chip */
5431 dd->pport[0].cpspec->kpregbase =
5432 (u64 __iomem *)((char __iomem *)dd->kregbase);
5433 dd->pport[1].cpspec->kpregbase =
5434 (u64 __iomem *)(dd->palign +
5435 (char __iomem *)dd->kregbase);
5436 dd->pport[0].cpspec->cpregbase =
5437 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[0],
5438 kr_counterregbase) + (char __iomem *)dd->kregbase);
5439 dd->pport[1].cpspec->cpregbase =
5440 (u64 __iomem *)(qib_read_kreg_port(&dd->pport[1],
5441 kr_counterregbase) + (char __iomem *)dd->kregbase);
5442 }
5443
5444 /*
5445 * This is a fairly special-purpose observer, so we only support
5446 * the port-specific parts of SendCtrl
5447 */
5448
5449 #define SENDCTRL_SHADOWED (SYM_MASK(SendCtrl_0, SendEnable) | \
5450 SYM_MASK(SendCtrl_0, SDmaEnable) | \
5451 SYM_MASK(SendCtrl_0, SDmaIntEnable) | \
5452 SYM_MASK(SendCtrl_0, SDmaSingleDescriptor) | \
5453 SYM_MASK(SendCtrl_0, SDmaHalt) | \
5454 SYM_MASK(SendCtrl_0, IBVLArbiterEn) | \
5455 SYM_MASK(SendCtrl_0, ForceCreditUpToDate))
5456
5457 static int sendctrl_hook(struct qib_devdata *dd,
5458 const struct diag_observer *op, u32 offs,
5459 u64 *data, u64 mask, int only_32)
5460 {
5461 unsigned long flags;
5462 unsigned idx;
5463 unsigned pidx;
5464 struct qib_pportdata *ppd = NULL;
5465 u64 local_data, all_bits;
5466
5467 /*
5468 * The fixed correspondence between Physical ports and pports is
5469 * severed. We need to hunt for the ppd that corresponds
5470 * to the offset we got. And we have to do that without admitting
5471 * we know the stride, apparently.
5472 */
5473 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5474 u64 __iomem *psptr;
5475 u32 psoffs;
5476
5477 ppd = dd->pport + pidx;
5478 if (!ppd->cpspec->kpregbase)
5479 continue;
5480
5481 psptr = ppd->cpspec->kpregbase + krp_sendctrl;
5482 psoffs = (u32) (psptr - dd->kregbase) * sizeof(*psptr);
5483 if (psoffs == offs)
5484 break;
5485 }
5486
5487 /* If pport is not being managed by driver, just avoid shadows. */
5488 if (pidx >= dd->num_pports)
5489 ppd = NULL;
5490
5491 /* In any case, "idx" is flat index in kreg space */
5492 idx = offs / sizeof(u64);
5493
5494 all_bits = ~0ULL;
5495 if (only_32)
5496 all_bits >>= 32;
5497
5498 spin_lock_irqsave(&dd->sendctrl_lock, flags);
5499 if (!ppd || (mask & all_bits) != all_bits) {
5500 /*
5501 * At least some mask bits are zero, so we need
5502 * to read. The judgement call is whether from
5503 * reg or shadow. First-cut: read reg, and complain
5504 * if any bits which should be shadowed are different
5505 * from their shadowed value.
5506 */
5507 if (only_32)
5508 local_data = (u64)qib_read_kreg32(dd, idx);
5509 else
5510 local_data = qib_read_kreg64(dd, idx);
5511 *data = (local_data & ~mask) | (*data & mask);
5512 }
5513 if (mask) {
5514 /*
5515 * At least some mask bits are one, so we need
5516 * to write, but only shadow some bits.
5517 */
5518 u64 sval, tval; /* Shadowed, transient */
5519
5520 /*
5521 * New shadow val is bits we don't want to touch,
5522 * ORed with bits we do, that are intended for shadow.
5523 */
5524 if (ppd) {
5525 sval = ppd->p_sendctrl & ~mask;
5526 sval |= *data & SENDCTRL_SHADOWED & mask;
5527 ppd->p_sendctrl = sval;
5528 } else
5529 sval = *data & SENDCTRL_SHADOWED & mask;
5530 tval = sval | (*data & ~SENDCTRL_SHADOWED & mask);
5531 qib_write_kreg(dd, idx, tval);
5532 qib_write_kreg(dd, kr_scratch, 0Ull);
5533 }
5534 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
5535 return only_32 ? 4 : 8;
5536 }
5537
5538 static const struct diag_observer sendctrl_0_observer = {
5539 sendctrl_hook, KREG_IDX(SendCtrl_0) * sizeof(u64),
5540 KREG_IDX(SendCtrl_0) * sizeof(u64)
5541 };
5542
5543 static const struct diag_observer sendctrl_1_observer = {
5544 sendctrl_hook, KREG_IDX(SendCtrl_1) * sizeof(u64),
5545 KREG_IDX(SendCtrl_1) * sizeof(u64)
5546 };
5547
5548 static ushort sdma_fetch_prio = 8;
5549 module_param_named(sdma_fetch_prio, sdma_fetch_prio, ushort, S_IRUGO);
5550 MODULE_PARM_DESC(sdma_fetch_prio, "SDMA descriptor fetch priority");
5551
5552 /* Besides logging QSFP events, we set appropriate TxDDS values */
5553 static void init_txdds_table(struct qib_pportdata *ppd, int override);
5554
5555 static void qsfp_7322_event(struct work_struct *work)
5556 {
5557 struct qib_qsfp_data *qd;
5558 struct qib_pportdata *ppd;
5559 u64 pwrup;
5560 int ret;
5561 u32 le2;
5562
5563 qd = container_of(work, struct qib_qsfp_data, work);
5564 ppd = qd->ppd;
5565 pwrup = qd->t_insert + msecs_to_jiffies(QSFP_PWR_LAG_MSEC);
5566
5567 /*
5568 * Some QSFP's not only do not respond until the full power-up
5569 * time, but may behave badly if we try. So hold off responding
5570 * to insertion.
5571 */
5572 while (1) {
5573 u64 now = get_jiffies_64();
5574 if (time_after64(now, pwrup))
5575 break;
5576 msleep(20);
5577 }
5578 ret = qib_refresh_qsfp_cache(ppd, &qd->cache);
5579 /*
5580 * Need to change LE2 back to defaults if we couldn't
5581 * read the cable type (to handle cable swaps), so do this
5582 * even on failure to read cable information. We don't
5583 * get here for QME, so IS_QME check not needed here.
5584 */
5585 le2 = (!ret && qd->cache.atten[1] >= qib_long_atten &&
5586 !ppd->dd->cspec->r1 && QSFP_IS_CU(qd->cache.tech)) ?
5587 LE2_5m : LE2_DEFAULT;
5588 ibsd_wr_allchans(ppd, 13, (le2 << 7), BMASK(9, 7));
5589 init_txdds_table(ppd, 0);
5590 }
5591
5592 /*
5593 * There is little we can do but complain to the user if QSFP
5594 * initialization fails.
5595 */
5596 static void qib_init_7322_qsfp(struct qib_pportdata *ppd)
5597 {
5598 unsigned long flags;
5599 struct qib_qsfp_data *qd = &ppd->cpspec->qsfp_data;
5600 struct qib_devdata *dd = ppd->dd;
5601 u64 mod_prs_bit = QSFP_GPIO_MOD_PRS_N;
5602
5603 mod_prs_bit <<= (QSFP_GPIO_PORT2_SHIFT * ppd->hw_pidx);
5604 qd->ppd = ppd;
5605 qib_qsfp_init(qd, qsfp_7322_event);
5606 spin_lock_irqsave(&dd->cspec->gpio_lock, flags);
5607 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert));
5608 dd->cspec->gpio_mask |= mod_prs_bit;
5609 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl);
5610 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask);
5611 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags);
5612 }
5613
5614 /*
5615 * called at device initialization time, and also if the txselect
5616 * module parameter is changed. This is used for cables that don't
5617 * have valid QSFP EEPROMs (not present, or attenuation is zero).
5618 * We initialize to the default, then if there is a specific
5619 * unit,port match, we use that (and set it immediately, for the
5620 * current speed, if the link is at INIT or better).
5621 * String format is "default# unit#,port#=# ... u,p=#", separators must
5622 * be a SPACE character. A newline terminates. The u,p=# tuples may
5623 * optionally have "u,p=#,#", where the final # is the H1 value
5624 * The last specific match is used (actually, all are used, but last
5625 * one is the one that winds up set); if none at all, fall back on default.
5626 */
5627 static void set_no_qsfp_atten(struct qib_devdata *dd, int change)
5628 {
5629 char *nxt, *str;
5630 u32 pidx, unit, port, deflt, h1;
5631 unsigned long val;
5632 int any = 0, seth1;
5633 int txdds_size;
5634
5635 str = txselect_list;
5636
5637 /* default number is validated in setup_txselect() */
5638 deflt = simple_strtoul(str, &nxt, 0);
5639 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5640 dd->pport[pidx].cpspec->no_eep = deflt;
5641
5642 txdds_size = TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ;
5643 if (IS_QME(dd) || IS_QMH(dd))
5644 txdds_size += TXDDS_MFG_SZ;
5645
5646 while (*nxt && nxt[1]) {
5647 str = ++nxt;
5648 unit = simple_strtoul(str, &nxt, 0);
5649 if (nxt == str || !*nxt || *nxt != ',') {
5650 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5651 ;
5652 continue;
5653 }
5654 str = ++nxt;
5655 port = simple_strtoul(str, &nxt, 0);
5656 if (nxt == str || *nxt != '=') {
5657 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5658 ;
5659 continue;
5660 }
5661 str = ++nxt;
5662 val = simple_strtoul(str, &nxt, 0);
5663 if (nxt == str) {
5664 while (*nxt && *nxt++ != ' ') /* skip to next, if any */
5665 ;
5666 continue;
5667 }
5668 if (val >= txdds_size)
5669 continue;
5670 seth1 = 0;
5671 h1 = 0; /* gcc thinks it might be used uninitted */
5672 if (*nxt == ',' && nxt[1]) {
5673 str = ++nxt;
5674 h1 = (u32)simple_strtoul(str, &nxt, 0);
5675 if (nxt == str)
5676 while (*nxt && *nxt++ != ' ') /* skip */
5677 ;
5678 else
5679 seth1 = 1;
5680 }
5681 for (pidx = 0; dd->unit == unit && pidx < dd->num_pports;
5682 ++pidx) {
5683 struct qib_pportdata *ppd = &dd->pport[pidx];
5684
5685 if (ppd->port != port || !ppd->link_speed_supported)
5686 continue;
5687 ppd->cpspec->no_eep = val;
5688 if (seth1)
5689 ppd->cpspec->h1_val = h1;
5690 /* now change the IBC and serdes, overriding generic */
5691 init_txdds_table(ppd, 1);
5692 /* Re-enable the physical state machine on mezz boards
5693 * now that the correct settings have been set. */
5694 if (IS_QMH(dd) || IS_QME(dd))
5695 qib_set_ib_7322_lstate(ppd, 0,
5696 QLOGIC_IB_IBCC_LINKINITCMD_SLEEP);
5697 any++;
5698 }
5699 if (*nxt == '\n')
5700 break; /* done */
5701 }
5702 if (change && !any) {
5703 /* no specific setting, use the default.
5704 * Change the IBC and serdes, but since it's
5705 * general, don't override specific settings.
5706 */
5707 for (pidx = 0; pidx < dd->num_pports; ++pidx)
5708 if (dd->pport[pidx].link_speed_supported)
5709 init_txdds_table(&dd->pport[pidx], 0);
5710 }
5711 }
5712
5713 /* handle the txselect parameter changing */
5714 static int setup_txselect(const char *str, struct kernel_param *kp)
5715 {
5716 struct qib_devdata *dd;
5717 unsigned long val;
5718 char *n;
5719 if (strlen(str) >= MAX_ATTEN_LEN) {
5720 printk(KERN_INFO QIB_DRV_NAME " txselect_values string "
5721 "too long\n");
5722 return -ENOSPC;
5723 }
5724 val = simple_strtoul(str, &n, 0);
5725 if (n == str || val >= (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
5726 TXDDS_MFG_SZ)) {
5727 printk(KERN_INFO QIB_DRV_NAME
5728 "txselect_values must start with a number < %d\n",
5729 TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ + TXDDS_MFG_SZ);
5730 return -EINVAL;
5731 }
5732 strcpy(txselect_list, str);
5733
5734 list_for_each_entry(dd, &qib_dev_list, list)
5735 if (dd->deviceid == PCI_DEVICE_ID_QLOGIC_IB_7322)
5736 set_no_qsfp_atten(dd, 1);
5737 return 0;
5738 }
5739
5740 /*
5741 * Write the final few registers that depend on some of the
5742 * init setup. Done late in init, just before bringing up
5743 * the serdes.
5744 */
5745 static int qib_late_7322_initreg(struct qib_devdata *dd)
5746 {
5747 int ret = 0, n;
5748 u64 val;
5749
5750 qib_write_kreg(dd, kr_rcvhdrentsize, dd->rcvhdrentsize);
5751 qib_write_kreg(dd, kr_rcvhdrsize, dd->rcvhdrsize);
5752 qib_write_kreg(dd, kr_rcvhdrcnt, dd->rcvhdrcnt);
5753 qib_write_kreg(dd, kr_sendpioavailaddr, dd->pioavailregs_phys);
5754 val = qib_read_kreg64(dd, kr_sendpioavailaddr);
5755 if (val != dd->pioavailregs_phys) {
5756 qib_dev_err(dd, "Catastrophic software error, "
5757 "SendPIOAvailAddr written as %lx, "
5758 "read back as %llx\n",
5759 (unsigned long) dd->pioavailregs_phys,
5760 (unsigned long long) val);
5761 ret = -EINVAL;
5762 }
5763
5764 n = dd->piobcnt2k + dd->piobcnt4k + NUM_VL15_BUFS;
5765 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_KERN, NULL);
5766 /* driver sends get pkey, lid, etc. checking also, to catch bugs */
5767 qib_7322_txchk_change(dd, 0, n, TXCHK_CHG_TYPE_ENAB1, NULL);
5768
5769 qib_register_observer(dd, &sendctrl_0_observer);
5770 qib_register_observer(dd, &sendctrl_1_observer);
5771
5772 dd->control &= ~QLOGIC_IB_C_SDMAFETCHPRIOEN;
5773 qib_write_kreg(dd, kr_control, dd->control);
5774 /*
5775 * Set SendDmaFetchPriority and init Tx params, including
5776 * QSFP handler on boards that have QSFP.
5777 * First set our default attenuation entry for cables that
5778 * don't have valid attenuation.
5779 */
5780 set_no_qsfp_atten(dd, 0);
5781 for (n = 0; n < dd->num_pports; ++n) {
5782 struct qib_pportdata *ppd = dd->pport + n;
5783
5784 qib_write_kreg_port(ppd, krp_senddmaprioritythld,
5785 sdma_fetch_prio & 0xf);
5786 /* Initialize qsfp if present on board. */
5787 if (dd->flags & QIB_HAS_QSFP)
5788 qib_init_7322_qsfp(ppd);
5789 }
5790 dd->control |= QLOGIC_IB_C_SDMAFETCHPRIOEN;
5791 qib_write_kreg(dd, kr_control, dd->control);
5792
5793 return ret;
5794 }
5795
5796 /* per IB port errors. */
5797 #define SENDCTRL_PIBP (MASK_ACROSS(0, 1) | MASK_ACROSS(3, 3) | \
5798 MASK_ACROSS(8, 15))
5799 #define RCVCTRL_PIBP (MASK_ACROSS(0, 17) | MASK_ACROSS(39, 41))
5800 #define ERRS_PIBP (MASK_ACROSS(57, 58) | MASK_ACROSS(54, 54) | \
5801 MASK_ACROSS(36, 49) | MASK_ACROSS(29, 34) | MASK_ACROSS(14, 17) | \
5802 MASK_ACROSS(0, 11))
5803
5804 /*
5805 * Write the initialization per-port registers that need to be done at
5806 * driver load and after reset completes (i.e., that aren't done as part
5807 * of other init procedures called from qib_init.c).
5808 * Some of these should be redundant on reset, but play safe.
5809 */
5810 static void write_7322_init_portregs(struct qib_pportdata *ppd)
5811 {
5812 u64 val;
5813 int i;
5814
5815 if (!ppd->link_speed_supported) {
5816 /* no buffer credits for this port */
5817 for (i = 1; i < 8; i++)
5818 qib_write_kreg_port(ppd, krp_rxcreditvl0 + i, 0);
5819 qib_write_kreg_port(ppd, krp_ibcctrl_b, 0);
5820 qib_write_kreg(ppd->dd, kr_scratch, 0);
5821 return;
5822 }
5823
5824 /*
5825 * Set the number of supported virtual lanes in IBC,
5826 * for flow control packet handling on unsupported VLs
5827 */
5828 val = qib_read_kreg_port(ppd, krp_ibsdtestiftx);
5829 val &= ~SYM_MASK(IB_SDTEST_IF_TX_0, VL_CAP);
5830 val |= (u64)(ppd->vls_supported - 1) <<
5831 SYM_LSB(IB_SDTEST_IF_TX_0, VL_CAP);
5832 qib_write_kreg_port(ppd, krp_ibsdtestiftx, val);
5833
5834 qib_write_kreg_port(ppd, krp_rcvbthqp, QIB_KD_QP);
5835
5836 /* enable tx header checking */
5837 qib_write_kreg_port(ppd, krp_sendcheckcontrol, IBA7322_SENDCHK_PKEY |
5838 IBA7322_SENDCHK_BTHQP | IBA7322_SENDCHK_SLID |
5839 IBA7322_SENDCHK_RAW_IPV6 | IBA7322_SENDCHK_MINSZ);
5840
5841 qib_write_kreg_port(ppd, krp_ncmodectrl,
5842 SYM_MASK(IBNCModeCtrl_0, ScrambleCapLocal));
5843
5844 /*
5845 * Unconditionally clear the bufmask bits. If SDMA is
5846 * enabled, we'll set them appropriately later.
5847 */
5848 qib_write_kreg_port(ppd, krp_senddmabufmask0, 0);
5849 qib_write_kreg_port(ppd, krp_senddmabufmask1, 0);
5850 qib_write_kreg_port(ppd, krp_senddmabufmask2, 0);
5851 if (ppd->dd->cspec->r1)
5852 ppd->p_sendctrl |= SYM_MASK(SendCtrl_0, ForceCreditUpToDate);
5853 }
5854
5855 /*
5856 * Write the initialization per-device registers that need to be done at
5857 * driver load and after reset completes (i.e., that aren't done as part
5858 * of other init procedures called from qib_init.c). Also write per-port
5859 * registers that are affected by overall device config, such as QP mapping
5860 * Some of these should be redundant on reset, but play safe.
5861 */
5862 static void write_7322_initregs(struct qib_devdata *dd)
5863 {
5864 struct qib_pportdata *ppd;
5865 int i, pidx;
5866 u64 val;
5867
5868 /* Set Multicast QPs received by port 2 to map to context one. */
5869 qib_write_kreg(dd, KREG_IDX(RcvQPMulticastContext_1), 1);
5870
5871 for (pidx = 0; pidx < dd->num_pports; ++pidx) {
5872 unsigned n, regno;
5873 unsigned long flags;
5874
5875 if (dd->n_krcv_queues < 2 ||
5876 !dd->pport[pidx].link_speed_supported)
5877 continue;
5878
5879 ppd = &dd->pport[pidx];
5880
5881 /* be paranoid against later code motion, etc. */
5882 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags);
5883 ppd->p_rcvctrl |= SYM_MASK(RcvCtrl_0, RcvQPMapEnable);
5884 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags);
5885
5886 /* Initialize QP to context mapping */
5887 regno = krp_rcvqpmaptable;
5888 val = 0;
5889 if (dd->num_pports > 1)
5890 n = dd->first_user_ctxt / dd->num_pports;
5891 else
5892 n = dd->first_user_ctxt - 1;
5893 for (i = 0; i < 32; ) {
5894 unsigned ctxt;
5895
5896 if (dd->num_pports > 1)
5897 ctxt = (i % n) * dd->num_pports + pidx;
5898 else if (i % n)
5899 ctxt = (i % n) + 1;
5900 else
5901 ctxt = ppd->hw_pidx;
5902 val |= ctxt << (5 * (i % 6));
5903 i++;
5904 if (i % 6 == 0) {
5905 qib_write_kreg_port(ppd, regno, val);
5906 val = 0;
5907 regno++;
5908 }
5909 }
5910 qib_write_kreg_port(ppd, regno, val);
5911 }
5912
5913 /*
5914 * Setup up interrupt mitigation for kernel contexts, but
5915 * not user contexts (user contexts use interrupts when
5916 * stalled waiting for any packet, so want those interrupts
5917 * right away).
5918 */
5919 for (i = 0; i < dd->first_user_ctxt; i++) {
5920 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout;
5921 qib_write_kreg(dd, kr_rcvavailtimeout + i, rcv_int_timeout);
5922 }
5923
5924 /*
5925 * Initialize as (disabled) rcvflow tables. Application code
5926 * will setup each flow as it uses the flow.
5927 * Doesn't clear any of the error bits that might be set.
5928 */
5929 val = TIDFLOW_ERRBITS; /* these are W1C */
5930 for (i = 0; i < dd->cfgctxts; i++) {
5931 int flow;
5932 for (flow = 0; flow < NUM_TIDFLOWS_CTXT; flow++)
5933 qib_write_ureg(dd, ur_rcvflowtable+flow, val, i);
5934 }
5935
5936 /*
5937 * dual cards init to dual port recovery, single port cards to
5938 * the one port. Dual port cards may later adjust to 1 port,
5939 * and then back to dual port if both ports are connected
5940 * */
5941 if (dd->num_pports)
5942 setup_7322_link_recovery(dd->pport, dd->num_pports > 1);
5943 }
5944
5945 static int qib_init_7322_variables(struct qib_devdata *dd)
5946 {
5947 struct qib_pportdata *ppd;
5948 unsigned features, pidx, sbufcnt;
5949 int ret, mtu;
5950 u32 sbufs, updthresh;
5951
5952 /* pport structs are contiguous, allocated after devdata */
5953 ppd = (struct qib_pportdata *)(dd + 1);
5954 dd->pport = ppd;
5955 ppd[0].dd = dd;
5956 ppd[1].dd = dd;
5957
5958 dd->cspec = (struct qib_chip_specific *)(ppd + 2);
5959
5960 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1);
5961 ppd[1].cpspec = &ppd[0].cpspec[1];
5962 ppd[0].cpspec->ppd = &ppd[0]; /* for autoneg_7322_work() */
5963 ppd[1].cpspec->ppd = &ppd[1]; /* for autoneg_7322_work() */
5964
5965 spin_lock_init(&dd->cspec->rcvmod_lock);
5966 spin_lock_init(&dd->cspec->gpio_lock);
5967
5968 /* we haven't yet set QIB_PRESENT, so use read directly */
5969 dd->revision = readq(&dd->kregbase[kr_revision]);
5970
5971 if ((dd->revision & 0xffffffffU) == 0xffffffffU) {
5972 qib_dev_err(dd, "Revision register read failure, "
5973 "giving up initialization\n");
5974 ret = -ENODEV;
5975 goto bail;
5976 }
5977 dd->flags |= QIB_PRESENT; /* now register routines work */
5978
5979 dd->majrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMajor);
5980 dd->minrev = (u8) SYM_FIELD(dd->revision, Revision_R, ChipRevMinor);
5981 dd->cspec->r1 = dd->minrev == 1;
5982
5983 get_7322_chip_params(dd);
5984 features = qib_7322_boardname(dd);
5985
5986 /* now that piobcnt2k and 4k set, we can allocate these */
5987 sbufcnt = dd->piobcnt2k + dd->piobcnt4k +
5988 NUM_VL15_BUFS + BITS_PER_LONG - 1;
5989 sbufcnt /= BITS_PER_LONG;
5990 dd->cspec->sendchkenable = kmalloc(sbufcnt *
5991 sizeof(*dd->cspec->sendchkenable), GFP_KERNEL);
5992 dd->cspec->sendgrhchk = kmalloc(sbufcnt *
5993 sizeof(*dd->cspec->sendgrhchk), GFP_KERNEL);
5994 dd->cspec->sendibchk = kmalloc(sbufcnt *
5995 sizeof(*dd->cspec->sendibchk), GFP_KERNEL);
5996 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk ||
5997 !dd->cspec->sendibchk) {
5998 qib_dev_err(dd, "Failed allocation for hdrchk bitmaps\n");
5999 ret = -ENOMEM;
6000 goto bail;
6001 }
6002
6003 ppd = dd->pport;
6004
6005 /*
6006 * GPIO bits for TWSI data and clock,
6007 * used for serial EEPROM.
6008 */
6009 dd->gpio_sda_num = _QIB_GPIO_SDA_NUM;
6010 dd->gpio_scl_num = _QIB_GPIO_SCL_NUM;
6011 dd->twsi_eeprom_dev = QIB_TWSI_EEPROM_DEV;
6012
6013 dd->flags |= QIB_HAS_INTX | QIB_HAS_LINK_LATENCY |
6014 QIB_NODMA_RTAIL | QIB_HAS_VLSUPP | QIB_HAS_HDRSUPP |
6015 QIB_HAS_THRESH_UPDATE |
6016 (sdma_idle_cnt ? QIB_HAS_SDMA_TIMEOUT : 0);
6017 dd->flags |= qib_special_trigger ?
6018 QIB_USE_SPCL_TRIG : QIB_HAS_SEND_DMA;
6019
6020 /*
6021 * Setup initial values. These may change when PAT is enabled, but
6022 * we need these to do initial chip register accesses.
6023 */
6024 qib_7322_set_baseaddrs(dd);
6025
6026 mtu = ib_mtu_enum_to_int(qib_ibmtu);
6027 if (mtu == -1)
6028 mtu = QIB_DEFAULT_MTU;
6029
6030 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT;
6031 /* all hwerrors become interrupts, unless special purposed */
6032 dd->cspec->hwerrmask = ~0ULL;
6033 /* link_recovery setup causes these errors, so ignore them,
6034 * other than clearing them when they occur */
6035 dd->cspec->hwerrmask &=
6036 ~(SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_0) |
6037 SYM_MASK(HwErrMask, IBSerdesPClkNotDetectMask_1) |
6038 HWE_MASK(LATriggered));
6039
6040 for (pidx = 0; pidx < NUM_IB_PORTS; ++pidx) {
6041 struct qib_chippport_specific *cp = ppd->cpspec;
6042 ppd->link_speed_supported = features & PORT_SPD_CAP;
6043 features >>= PORT_SPD_CAP_SHIFT;
6044 if (!ppd->link_speed_supported) {
6045 /* single port mode (7340, or configured) */
6046 dd->skip_kctxt_mask |= 1 << pidx;
6047 if (pidx == 0) {
6048 /* Make sure port is disabled. */
6049 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6050 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6051 ppd[0] = ppd[1];
6052 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6053 IBSerdesPClkNotDetectMask_0)
6054 | SYM_MASK(HwErrMask,
6055 SDmaMemReadErrMask_0));
6056 dd->cspec->int_enable_mask &= ~(
6057 SYM_MASK(IntMask, SDmaCleanupDoneMask_0) |
6058 SYM_MASK(IntMask, SDmaIdleIntMask_0) |
6059 SYM_MASK(IntMask, SDmaProgressIntMask_0) |
6060 SYM_MASK(IntMask, SDmaIntMask_0) |
6061 SYM_MASK(IntMask, ErrIntMask_0) |
6062 SYM_MASK(IntMask, SendDoneIntMask_0));
6063 } else {
6064 /* Make sure port is disabled. */
6065 qib_write_kreg_port(ppd, krp_rcvctrl, 0);
6066 qib_write_kreg_port(ppd, krp_ibcctrl_a, 0);
6067 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask,
6068 IBSerdesPClkNotDetectMask_1)
6069 | SYM_MASK(HwErrMask,
6070 SDmaMemReadErrMask_1));
6071 dd->cspec->int_enable_mask &= ~(
6072 SYM_MASK(IntMask, SDmaCleanupDoneMask_1) |
6073 SYM_MASK(IntMask, SDmaIdleIntMask_1) |
6074 SYM_MASK(IntMask, SDmaProgressIntMask_1) |
6075 SYM_MASK(IntMask, SDmaIntMask_1) |
6076 SYM_MASK(IntMask, ErrIntMask_1) |
6077 SYM_MASK(IntMask, SendDoneIntMask_1));
6078 }
6079 continue;
6080 }
6081
6082 dd->num_pports++;
6083 qib_init_pportdata(ppd, dd, pidx, dd->num_pports);
6084
6085 ppd->link_width_supported = IB_WIDTH_1X | IB_WIDTH_4X;
6086 ppd->link_width_enabled = IB_WIDTH_4X;
6087 ppd->link_speed_enabled = ppd->link_speed_supported;
6088 /*
6089 * Set the initial values to reasonable default, will be set
6090 * for real when link is up.
6091 */
6092 ppd->link_width_active = IB_WIDTH_4X;
6093 ppd->link_speed_active = QIB_IB_SDR;
6094 ppd->delay_mult = ib_rate_to_delay[IB_RATE_10_GBPS];
6095 switch (qib_num_cfg_vls) {
6096 case 1:
6097 ppd->vls_supported = IB_VL_VL0;
6098 break;
6099 case 2:
6100 ppd->vls_supported = IB_VL_VL0_1;
6101 break;
6102 default:
6103 qib_devinfo(dd->pcidev,
6104 "Invalid num_vls %u, using 4 VLs\n",
6105 qib_num_cfg_vls);
6106 qib_num_cfg_vls = 4;
6107 /* fall through */
6108 case 4:
6109 ppd->vls_supported = IB_VL_VL0_3;
6110 break;
6111 case 8:
6112 if (mtu <= 2048)
6113 ppd->vls_supported = IB_VL_VL0_7;
6114 else {
6115 qib_devinfo(dd->pcidev,
6116 "Invalid num_vls %u for MTU %d "
6117 ", using 4 VLs\n",
6118 qib_num_cfg_vls, mtu);
6119 ppd->vls_supported = IB_VL_VL0_3;
6120 qib_num_cfg_vls = 4;
6121 }
6122 break;
6123 }
6124 ppd->vls_operational = ppd->vls_supported;
6125
6126 init_waitqueue_head(&cp->autoneg_wait);
6127 INIT_DELAYED_WORK(&cp->autoneg_work,
6128 autoneg_7322_work);
6129 if (ppd->dd->cspec->r1)
6130 INIT_DELAYED_WORK(&cp->ipg_work, ipg_7322_work);
6131
6132 /*
6133 * For Mez and similar cards, no qsfp info, so do
6134 * the "cable info" setup here. Can be overridden
6135 * in adapter-specific routines.
6136 */
6137 if (!(dd->flags & QIB_HAS_QSFP)) {
6138 if (!IS_QMH(dd) && !IS_QME(dd))
6139 qib_devinfo(dd->pcidev, "IB%u:%u: "
6140 "Unknown mezzanine card type\n",
6141 dd->unit, ppd->port);
6142 cp->h1_val = IS_QMH(dd) ? H1_FORCE_QMH : H1_FORCE_QME;
6143 /*
6144 * Choose center value as default tx serdes setting
6145 * until changed through module parameter.
6146 */
6147 ppd->cpspec->no_eep = IS_QMH(dd) ?
6148 TXDDS_TABLE_SZ + 2 : TXDDS_TABLE_SZ + 4;
6149 } else
6150 cp->h1_val = H1_FORCE_VAL;
6151
6152 /* Avoid writes to chip for mini_init */
6153 if (!qib_mini_init)
6154 write_7322_init_portregs(ppd);
6155
6156 init_timer(&cp->chase_timer);
6157 cp->chase_timer.function = reenable_chase;
6158 cp->chase_timer.data = (unsigned long)ppd;
6159
6160 ppd++;
6161 }
6162
6163 dd->rcvhdrentsize = qib_rcvhdrentsize ?
6164 qib_rcvhdrentsize : QIB_RCVHDR_ENTSIZE;
6165 dd->rcvhdrsize = qib_rcvhdrsize ?
6166 qib_rcvhdrsize : QIB_DFLT_RCVHDRSIZE;
6167 dd->rhf_offset = dd->rcvhdrentsize - sizeof(u64) / sizeof(u32);
6168
6169 /* we always allocate at least 2048 bytes for eager buffers */
6170 dd->rcvegrbufsize = max(mtu, 2048);
6171
6172 qib_7322_tidtemplate(dd);
6173
6174 /*
6175 * We can request a receive interrupt for 1 or
6176 * more packets from current offset.
6177 */
6178 dd->rhdrhead_intr_off =
6179 (u64) rcv_int_count << IBA7322_HDRHEAD_PKTINT_SHIFT;
6180
6181 /* setup the stats timer; the add_timer is done at end of init */
6182 init_timer(&dd->stats_timer);
6183 dd->stats_timer.function = qib_get_7322_faststats;
6184 dd->stats_timer.data = (unsigned long) dd;
6185
6186 dd->ureg_align = 0x10000; /* 64KB alignment */
6187
6188 dd->piosize2kmax_dwords = dd->piosize2k >> 2;
6189
6190 qib_7322_config_ctxts(dd);
6191 qib_set_ctxtcnt(dd);
6192
6193 if (qib_wc_pat) {
6194 resource_size_t vl15off;
6195 /*
6196 * We do not set WC on the VL15 buffers to avoid
6197 * a rare problem with unaligned writes from
6198 * interrupt-flushed store buffers, so we need
6199 * to map those separately here. We can't solve
6200 * this for the rarely used mtrr case.
6201 */
6202 ret = init_chip_wc_pat(dd, 0);
6203 if (ret)
6204 goto bail;
6205
6206 /* vl15 buffers start just after the 4k buffers */
6207 vl15off = dd->physaddr + (dd->piobufbase >> 32) +
6208 dd->piobcnt4k * dd->align4k;
6209 dd->piovl15base = ioremap_nocache(vl15off,
6210 NUM_VL15_BUFS * dd->align4k);
6211 if (!dd->piovl15base)
6212 goto bail;
6213 }
6214 qib_7322_set_baseaddrs(dd); /* set chip access pointers now */
6215
6216 ret = 0;
6217 if (qib_mini_init)
6218 goto bail;
6219 if (!dd->num_pports) {
6220 qib_dev_err(dd, "No ports enabled, giving up initialization\n");
6221 goto bail; /* no error, so can still figure out why err */
6222 }
6223
6224 write_7322_initregs(dd);
6225 ret = qib_create_ctxts(dd);
6226 init_7322_cntrnames(dd);
6227
6228 updthresh = 8U; /* update threshold */
6229
6230 /* use all of 4KB buffers for the kernel SDMA, zero if !SDMA.
6231 * reserve the update threshold amount for other kernel use, such
6232 * as sending SMI, MAD, and ACKs, or 3, whichever is greater,
6233 * unless we aren't enabling SDMA, in which case we want to use
6234 * all the 4k bufs for the kernel.
6235 * if this was less than the update threshold, we could wait
6236 * a long time for an update. Coded this way because we
6237 * sometimes change the update threshold for various reasons,
6238 * and we want this to remain robust.
6239 */
6240 if (dd->flags & QIB_HAS_SEND_DMA) {
6241 dd->cspec->sdmabufcnt = dd->piobcnt4k;
6242 sbufs = updthresh > 3 ? updthresh : 3;
6243 } else {
6244 dd->cspec->sdmabufcnt = 0;
6245 sbufs = dd->piobcnt4k;
6246 }
6247 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k -
6248 dd->cspec->sdmabufcnt;
6249 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs;
6250 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */
6251 dd->pbufsctxt = (dd->cfgctxts > dd->first_user_ctxt) ?
6252 dd->lastctxt_piobuf / (dd->cfgctxts - dd->first_user_ctxt) : 0;
6253
6254 /*
6255 * If we have 16 user contexts, we will have 7 sbufs
6256 * per context, so reduce the update threshold to match. We
6257 * want to update before we actually run out, at low pbufs/ctxt
6258 * so give ourselves some margin.
6259 */
6260 if (dd->pbufsctxt >= 2 && dd->pbufsctxt - 2 < updthresh)
6261 updthresh = dd->pbufsctxt - 2;
6262 dd->cspec->updthresh_dflt = updthresh;
6263 dd->cspec->updthresh = updthresh;
6264
6265 /* before full enable, no interrupts, no locking needed */
6266 dd->sendctrl |= ((updthresh & SYM_RMASK(SendCtrl, AvailUpdThld))
6267 << SYM_LSB(SendCtrl, AvailUpdThld)) |
6268 SYM_MASK(SendCtrl, SendBufAvailPad64Byte);
6269
6270 dd->psxmitwait_supported = 1;
6271 dd->psxmitwait_check_rate = QIB_7322_PSXMITWAIT_CHECK_RATE;
6272 bail:
6273 if (!dd->ctxtcnt)
6274 dd->ctxtcnt = 1; /* for other initialization code */
6275
6276 return ret;
6277 }
6278
6279 static u32 __iomem *qib_7322_getsendbuf(struct qib_pportdata *ppd, u64 pbc,
6280 u32 *pbufnum)
6281 {
6282 u32 first, last, plen = pbc & QIB_PBC_LENGTH_MASK;
6283 struct qib_devdata *dd = ppd->dd;
6284
6285 /* last is same for 2k and 4k, because we use 4k if all 2k busy */
6286 if (pbc & PBC_7322_VL15_SEND) {
6287 first = dd->piobcnt2k + dd->piobcnt4k + ppd->hw_pidx;
6288 last = first;
6289 } else {
6290 if ((plen + 1) > dd->piosize2kmax_dwords)
6291 first = dd->piobcnt2k;
6292 else
6293 first = 0;
6294 last = dd->cspec->lastbuf_for_pio;
6295 }
6296 return qib_getsendbuf_range(dd, pbufnum, first, last);
6297 }
6298
6299 static void qib_set_cntr_7322_sample(struct qib_pportdata *ppd, u32 intv,
6300 u32 start)
6301 {
6302 qib_write_kreg_port(ppd, krp_psinterval, intv);
6303 qib_write_kreg_port(ppd, krp_psstart, start);
6304 }
6305
6306 /*
6307 * Must be called with sdma_lock held, or before init finished.
6308 */
6309 static void qib_sdma_set_7322_desc_cnt(struct qib_pportdata *ppd, unsigned cnt)
6310 {
6311 qib_write_kreg_port(ppd, krp_senddmadesccnt, cnt);
6312 }
6313
6314 static struct sdma_set_state_action sdma_7322_action_table[] = {
6315 [qib_sdma_state_s00_hw_down] = {
6316 .go_s99_running_tofalse = 1,
6317 .op_enable = 0,
6318 .op_intenable = 0,
6319 .op_halt = 0,
6320 .op_drain = 0,
6321 },
6322 [qib_sdma_state_s10_hw_start_up_wait] = {
6323 .op_enable = 0,
6324 .op_intenable = 1,
6325 .op_halt = 1,
6326 .op_drain = 0,
6327 },
6328 [qib_sdma_state_s20_idle] = {
6329 .op_enable = 1,
6330 .op_intenable = 1,
6331 .op_halt = 1,
6332 .op_drain = 0,
6333 },
6334 [qib_sdma_state_s30_sw_clean_up_wait] = {
6335 .op_enable = 0,
6336 .op_intenable = 1,
6337 .op_halt = 1,
6338 .op_drain = 0,
6339 },
6340 [qib_sdma_state_s40_hw_clean_up_wait] = {
6341 .op_enable = 1,
6342 .op_intenable = 1,
6343 .op_halt = 1,
6344 .op_drain = 0,
6345 },
6346 [qib_sdma_state_s50_hw_halt_wait] = {
6347 .op_enable = 1,
6348 .op_intenable = 1,
6349 .op_halt = 1,
6350 .op_drain = 1,
6351 },
6352 [qib_sdma_state_s99_running] = {
6353 .op_enable = 1,
6354 .op_intenable = 1,
6355 .op_halt = 0,
6356 .op_drain = 0,
6357 .go_s99_running_totrue = 1,
6358 },
6359 };
6360
6361 static void qib_7322_sdma_init_early(struct qib_pportdata *ppd)
6362 {
6363 ppd->sdma_state.set_state_action = sdma_7322_action_table;
6364 }
6365
6366 static int init_sdma_7322_regs(struct qib_pportdata *ppd)
6367 {
6368 struct qib_devdata *dd = ppd->dd;
6369 unsigned lastbuf, erstbuf;
6370 u64 senddmabufmask[3] = { 0 };
6371 int n, ret = 0;
6372
6373 qib_write_kreg_port(ppd, krp_senddmabase, ppd->sdma_descq_phys);
6374 qib_sdma_7322_setlengen(ppd);
6375 qib_sdma_update_7322_tail(ppd, 0); /* Set SendDmaTail */
6376 qib_write_kreg_port(ppd, krp_senddmareloadcnt, sdma_idle_cnt);
6377 qib_write_kreg_port(ppd, krp_senddmadesccnt, 0);
6378 qib_write_kreg_port(ppd, krp_senddmaheadaddr, ppd->sdma_head_phys);
6379
6380 if (dd->num_pports)
6381 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */
6382 else
6383 n = dd->cspec->sdmabufcnt; /* failsafe for init */
6384 erstbuf = (dd->piobcnt2k + dd->piobcnt4k) -
6385 ((dd->num_pports == 1 || ppd->port == 2) ? n :
6386 dd->cspec->sdmabufcnt);
6387 lastbuf = erstbuf + n;
6388
6389 ppd->sdma_state.first_sendbuf = erstbuf;
6390 ppd->sdma_state.last_sendbuf = lastbuf;
6391 for (; erstbuf < lastbuf; ++erstbuf) {
6392 unsigned word = erstbuf / BITS_PER_LONG;
6393 unsigned bit = erstbuf & (BITS_PER_LONG - 1);
6394
6395 BUG_ON(word >= 3);
6396 senddmabufmask[word] |= 1ULL << bit;
6397 }
6398 qib_write_kreg_port(ppd, krp_senddmabufmask0, senddmabufmask[0]);
6399 qib_write_kreg_port(ppd, krp_senddmabufmask1, senddmabufmask[1]);
6400 qib_write_kreg_port(ppd, krp_senddmabufmask2, senddmabufmask[2]);
6401 return ret;
6402 }
6403
6404 /* sdma_lock must be held */
6405 static u16 qib_sdma_7322_gethead(struct qib_pportdata *ppd)
6406 {
6407 struct qib_devdata *dd = ppd->dd;
6408 int sane;
6409 int use_dmahead;
6410 u16 swhead;
6411 u16 swtail;
6412 u16 cnt;
6413 u16 hwhead;
6414
6415 use_dmahead = __qib_sdma_running(ppd) &&
6416 (dd->flags & QIB_HAS_SDMA_TIMEOUT);
6417 retry:
6418 hwhead = use_dmahead ?
6419 (u16) le64_to_cpu(*ppd->sdma_head_dma) :
6420 (u16) qib_read_kreg_port(ppd, krp_senddmahead);
6421
6422 swhead = ppd->sdma_descq_head;
6423 swtail = ppd->sdma_descq_tail;
6424 cnt = ppd->sdma_descq_cnt;
6425
6426 if (swhead < swtail)
6427 /* not wrapped */
6428 sane = (hwhead >= swhead) & (hwhead <= swtail);
6429 else if (swhead > swtail)
6430 /* wrapped around */
6431 sane = ((hwhead >= swhead) && (hwhead < cnt)) ||
6432 (hwhead <= swtail);
6433 else
6434 /* empty */
6435 sane = (hwhead == swhead);
6436
6437 if (unlikely(!sane)) {
6438 if (use_dmahead) {
6439 /* try one more time, directly from the register */
6440 use_dmahead = 0;
6441 goto retry;
6442 }
6443 /* proceed as if no progress */
6444 hwhead = swhead;
6445 }
6446
6447 return hwhead;
6448 }
6449
6450 static int qib_sdma_7322_busy(struct qib_pportdata *ppd)
6451 {
6452 u64 hwstatus = qib_read_kreg_port(ppd, krp_senddmastatus);
6453
6454 return (hwstatus & SYM_MASK(SendDmaStatus_0, ScoreBoardDrainInProg)) ||
6455 (hwstatus & SYM_MASK(SendDmaStatus_0, HaltInProg)) ||
6456 !(hwstatus & SYM_MASK(SendDmaStatus_0, InternalSDmaHalt)) ||
6457 !(hwstatus & SYM_MASK(SendDmaStatus_0, ScbEmpty));
6458 }
6459
6460 /*
6461 * Compute the amount of delay before sending the next packet if the
6462 * port's send rate differs from the static rate set for the QP.
6463 * The delay affects the next packet and the amount of the delay is
6464 * based on the length of the this packet.
6465 */
6466 static u32 qib_7322_setpbc_control(struct qib_pportdata *ppd, u32 plen,
6467 u8 srate, u8 vl)
6468 {
6469 u8 snd_mult = ppd->delay_mult;
6470 u8 rcv_mult = ib_rate_to_delay[srate];
6471 u32 ret;
6472
6473 ret = rcv_mult > snd_mult ? ((plen + 1) >> 1) * snd_mult : 0;
6474
6475 /* Indicate VL15, else set the VL in the control word */
6476 if (vl == 15)
6477 ret |= PBC_7322_VL15_SEND_CTRL;
6478 else
6479 ret |= vl << PBC_VL_NUM_LSB;
6480 ret |= ((u32)(ppd->hw_pidx)) << PBC_PORT_SEL_LSB;
6481
6482 return ret;
6483 }
6484
6485 /*
6486 * Enable the per-port VL15 send buffers for use.
6487 * They follow the rest of the buffers, without a config parameter.
6488 * This was in initregs, but that is done before the shadow
6489 * is set up, and this has to be done after the shadow is
6490 * set up.
6491 */
6492 static void qib_7322_initvl15_bufs(struct qib_devdata *dd)
6493 {
6494 unsigned vl15bufs;
6495
6496 vl15bufs = dd->piobcnt2k + dd->piobcnt4k;
6497 qib_chg_pioavailkernel(dd, vl15bufs, NUM_VL15_BUFS,
6498 TXCHK_CHG_TYPE_KERN, NULL);
6499 }
6500
6501 static void qib_7322_init_ctxt(struct qib_ctxtdata *rcd)
6502 {
6503 if (rcd->ctxt < NUM_IB_PORTS) {
6504 if (rcd->dd->num_pports > 1) {
6505 rcd->rcvegrcnt = KCTXT0_EGRCNT / 2;
6506 rcd->rcvegr_tid_base = rcd->ctxt ? rcd->rcvegrcnt : 0;
6507 } else {
6508 rcd->rcvegrcnt = KCTXT0_EGRCNT;
6509 rcd->rcvegr_tid_base = 0;
6510 }
6511 } else {
6512 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt;
6513 rcd->rcvegr_tid_base = KCTXT0_EGRCNT +
6514 (rcd->ctxt - NUM_IB_PORTS) * rcd->rcvegrcnt;
6515 }
6516 }
6517
6518 #define QTXSLEEPS 5000
6519 static void qib_7322_txchk_change(struct qib_devdata *dd, u32 start,
6520 u32 len, u32 which, struct qib_ctxtdata *rcd)
6521 {
6522 int i;
6523 const int last = start + len - 1;
6524 const int lastr = last / BITS_PER_LONG;
6525 u32 sleeps = 0;
6526 int wait = rcd != NULL;
6527 unsigned long flags;
6528
6529 while (wait) {
6530 unsigned long shadow;
6531 int cstart, previ = -1;
6532
6533 /*
6534 * when flipping from kernel to user, we can't change
6535 * the checking type if the buffer is allocated to the
6536 * driver. It's OK the other direction, because it's
6537 * from close, and we have just disarm'ed all the
6538 * buffers. All the kernel to kernel changes are also
6539 * OK.
6540 */
6541 for (cstart = start; cstart <= last; cstart++) {
6542 i = ((2 * cstart) + QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6543 / BITS_PER_LONG;
6544 if (i != previ) {
6545 shadow = (unsigned long)
6546 le64_to_cpu(dd->pioavailregs_dma[i]);
6547 previ = i;
6548 }
6549 if (test_bit(((2 * cstart) +
6550 QLOGIC_IB_SENDPIOAVAIL_BUSY_SHIFT)
6551 % BITS_PER_LONG, &shadow))
6552 break;
6553 }
6554
6555 if (cstart > last)
6556 break;
6557
6558 if (sleeps == QTXSLEEPS)
6559 break;
6560 /* make sure we see an updated copy next time around */
6561 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6562 sleeps++;
6563 msleep(20);
6564 }
6565
6566 switch (which) {
6567 case TXCHK_CHG_TYPE_DIS1:
6568 /*
6569 * disable checking on a range; used by diags; just
6570 * one buffer, but still written generically
6571 */
6572 for (i = start; i <= last; i++)
6573 clear_bit(i, dd->cspec->sendchkenable);
6574 break;
6575
6576 case TXCHK_CHG_TYPE_ENAB1:
6577 /*
6578 * (re)enable checking on a range; used by diags; just
6579 * one buffer, but still written generically; read
6580 * scratch to be sure buffer actually triggered, not
6581 * just flushed from processor.
6582 */
6583 qib_read_kreg32(dd, kr_scratch);
6584 for (i = start; i <= last; i++)
6585 set_bit(i, dd->cspec->sendchkenable);
6586 break;
6587
6588 case TXCHK_CHG_TYPE_KERN:
6589 /* usable by kernel */
6590 for (i = start; i <= last; i++) {
6591 set_bit(i, dd->cspec->sendibchk);
6592 clear_bit(i, dd->cspec->sendgrhchk);
6593 }
6594 spin_lock_irqsave(&dd->uctxt_lock, flags);
6595 /* see if we need to raise avail update threshold */
6596 for (i = dd->first_user_ctxt;
6597 dd->cspec->updthresh != dd->cspec->updthresh_dflt
6598 && i < dd->cfgctxts; i++)
6599 if (dd->rcd[i] && dd->rcd[i]->subctxt_cnt &&
6600 ((dd->rcd[i]->piocnt / dd->rcd[i]->subctxt_cnt) - 1)
6601 < dd->cspec->updthresh_dflt)
6602 break;
6603 spin_unlock_irqrestore(&dd->uctxt_lock, flags);
6604 if (i == dd->cfgctxts) {
6605 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6606 dd->cspec->updthresh = dd->cspec->updthresh_dflt;
6607 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6608 dd->sendctrl |= (dd->cspec->updthresh &
6609 SYM_RMASK(SendCtrl, AvailUpdThld)) <<
6610 SYM_LSB(SendCtrl, AvailUpdThld);
6611 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6612 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6613 }
6614 break;
6615
6616 case TXCHK_CHG_TYPE_USER:
6617 /* for user process */
6618 for (i = start; i <= last; i++) {
6619 clear_bit(i, dd->cspec->sendibchk);
6620 set_bit(i, dd->cspec->sendgrhchk);
6621 }
6622 spin_lock_irqsave(&dd->sendctrl_lock, flags);
6623 if (rcd && rcd->subctxt_cnt && ((rcd->piocnt
6624 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) {
6625 dd->cspec->updthresh = (rcd->piocnt /
6626 rcd->subctxt_cnt) - 1;
6627 dd->sendctrl &= ~SYM_MASK(SendCtrl, AvailUpdThld);
6628 dd->sendctrl |= (dd->cspec->updthresh &
6629 SYM_RMASK(SendCtrl, AvailUpdThld))
6630 << SYM_LSB(SendCtrl, AvailUpdThld);
6631 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6632 sendctrl_7322_mod(dd->pport, QIB_SENDCTRL_AVAIL_BLIP);
6633 } else
6634 spin_unlock_irqrestore(&dd->sendctrl_lock, flags);
6635 break;
6636
6637 default:
6638 break;
6639 }
6640
6641 for (i = start / BITS_PER_LONG; which >= 2 && i <= lastr; ++i)
6642 qib_write_kreg(dd, kr_sendcheckmask + i,
6643 dd->cspec->sendchkenable[i]);
6644
6645 for (i = start / BITS_PER_LONG; which < 2 && i <= lastr; ++i) {
6646 qib_write_kreg(dd, kr_sendgrhcheckmask + i,
6647 dd->cspec->sendgrhchk[i]);
6648 qib_write_kreg(dd, kr_sendibpktmask + i,
6649 dd->cspec->sendibchk[i]);
6650 }
6651
6652 /*
6653 * Be sure whatever we did was seen by the chip and acted upon,
6654 * before we return. Mostly important for which >= 2.
6655 */
6656 qib_read_kreg32(dd, kr_scratch);
6657 }
6658
6659
6660 /* useful for trigger analyzers, etc. */
6661 static void writescratch(struct qib_devdata *dd, u32 val)
6662 {
6663 qib_write_kreg(dd, kr_scratch, val);
6664 }
6665
6666 /* Dummy for now, use chip regs soon */
6667 static int qib_7322_tempsense_rd(struct qib_devdata *dd, int regnum)
6668 {
6669 return -ENXIO;
6670 }
6671
6672 /**
6673 * qib_init_iba7322_funcs - set up the chip-specific function pointers
6674 * @dev: the pci_dev for qlogic_ib device
6675 * @ent: pci_device_id struct for this dev
6676 *
6677 * Also allocates, inits, and returns the devdata struct for this
6678 * device instance
6679 *
6680 * This is global, and is called directly at init to set up the
6681 * chip-specific function pointers for later use.
6682 */
6683 struct qib_devdata *qib_init_iba7322_funcs(struct pci_dev *pdev,
6684 const struct pci_device_id *ent)
6685 {
6686 struct qib_devdata *dd;
6687 int ret, i;
6688 u32 tabsize, actual_cnt = 0;
6689
6690 dd = qib_alloc_devdata(pdev,
6691 NUM_IB_PORTS * sizeof(struct qib_pportdata) +
6692 sizeof(struct qib_chip_specific) +
6693 NUM_IB_PORTS * sizeof(struct qib_chippport_specific));
6694 if (IS_ERR(dd))
6695 goto bail;
6696
6697 dd->f_bringup_serdes = qib_7322_bringup_serdes;
6698 dd->f_cleanup = qib_setup_7322_cleanup;
6699 dd->f_clear_tids = qib_7322_clear_tids;
6700 dd->f_free_irq = qib_7322_free_irq;
6701 dd->f_get_base_info = qib_7322_get_base_info;
6702 dd->f_get_msgheader = qib_7322_get_msgheader;
6703 dd->f_getsendbuf = qib_7322_getsendbuf;
6704 dd->f_gpio_mod = gpio_7322_mod;
6705 dd->f_eeprom_wen = qib_7322_eeprom_wen;
6706 dd->f_hdrqempty = qib_7322_hdrqempty;
6707 dd->f_ib_updown = qib_7322_ib_updown;
6708 dd->f_init_ctxt = qib_7322_init_ctxt;
6709 dd->f_initvl15_bufs = qib_7322_initvl15_bufs;
6710 dd->f_intr_fallback = qib_7322_intr_fallback;
6711 dd->f_late_initreg = qib_late_7322_initreg;
6712 dd->f_setpbc_control = qib_7322_setpbc_control;
6713 dd->f_portcntr = qib_portcntr_7322;
6714 dd->f_put_tid = qib_7322_put_tid;
6715 dd->f_quiet_serdes = qib_7322_mini_quiet_serdes;
6716 dd->f_rcvctrl = rcvctrl_7322_mod;
6717 dd->f_read_cntrs = qib_read_7322cntrs;
6718 dd->f_read_portcntrs = qib_read_7322portcntrs;
6719 dd->f_reset = qib_do_7322_reset;
6720 dd->f_init_sdma_regs = init_sdma_7322_regs;
6721 dd->f_sdma_busy = qib_sdma_7322_busy;
6722 dd->f_sdma_gethead = qib_sdma_7322_gethead;
6723 dd->f_sdma_sendctrl = qib_7322_sdma_sendctrl;
6724 dd->f_sdma_set_desc_cnt = qib_sdma_set_7322_desc_cnt;
6725 dd->f_sdma_update_tail = qib_sdma_update_7322_tail;
6726 dd->f_sendctrl = sendctrl_7322_mod;
6727 dd->f_set_armlaunch = qib_set_7322_armlaunch;
6728 dd->f_set_cntr_sample = qib_set_cntr_7322_sample;
6729 dd->f_iblink_state = qib_7322_iblink_state;
6730 dd->f_ibphys_portstate = qib_7322_phys_portstate;
6731 dd->f_get_ib_cfg = qib_7322_get_ib_cfg;
6732 dd->f_set_ib_cfg = qib_7322_set_ib_cfg;
6733 dd->f_set_ib_loopback = qib_7322_set_loopback;
6734 dd->f_get_ib_table = qib_7322_get_ib_table;
6735 dd->f_set_ib_table = qib_7322_set_ib_table;
6736 dd->f_set_intr_state = qib_7322_set_intr_state;
6737 dd->f_setextled = qib_setup_7322_setextled;
6738 dd->f_txchk_change = qib_7322_txchk_change;
6739 dd->f_update_usrhead = qib_update_7322_usrhead;
6740 dd->f_wantpiobuf_intr = qib_wantpiobuf_7322_intr;
6741 dd->f_xgxs_reset = qib_7322_mini_pcs_reset;
6742 dd->f_sdma_hw_clean_up = qib_7322_sdma_hw_clean_up;
6743 dd->f_sdma_hw_start_up = qib_7322_sdma_hw_start_up;
6744 dd->f_sdma_init_early = qib_7322_sdma_init_early;
6745 dd->f_writescratch = writescratch;
6746 dd->f_tempsense_rd = qib_7322_tempsense_rd;
6747 /*
6748 * Do remaining PCIe setup and save PCIe values in dd.
6749 * Any error printing is already done by the init code.
6750 * On return, we have the chip mapped, but chip registers
6751 * are not set up until start of qib_init_7322_variables.
6752 */
6753 ret = qib_pcie_ddinit(dd, pdev, ent);
6754 if (ret < 0)
6755 goto bail_free;
6756
6757 /* initialize chip-specific variables */
6758 ret = qib_init_7322_variables(dd);
6759 if (ret)
6760 goto bail_cleanup;
6761
6762 if (qib_mini_init || !dd->num_pports)
6763 goto bail;
6764
6765 /*
6766 * Determine number of vectors we want; depends on port count
6767 * and number of configured kernel receive queues actually used.
6768 * Should also depend on whether sdma is enabled or not, but
6769 * that's such a rare testing case it's not worth worrying about.
6770 */
6771 tabsize = dd->first_user_ctxt + ARRAY_SIZE(irq_table);
6772 for (i = 0; i < tabsize; i++)
6773 if ((i < ARRAY_SIZE(irq_table) &&
6774 irq_table[i].port <= dd->num_pports) ||
6775 (i >= ARRAY_SIZE(irq_table) &&
6776 dd->rcd[i - ARRAY_SIZE(irq_table)]))
6777 actual_cnt++;
6778 tabsize = actual_cnt;
6779 dd->cspec->msix_entries = kmalloc(tabsize *
6780 sizeof(struct msix_entry), GFP_KERNEL);
6781 dd->cspec->msix_arg = kmalloc(tabsize *
6782 sizeof(void *), GFP_KERNEL);
6783 if (!dd->cspec->msix_entries || !dd->cspec->msix_arg) {
6784 qib_dev_err(dd, "No memory for MSIx table\n");
6785 tabsize = 0;
6786 }
6787 for (i = 0; i < tabsize; i++)
6788 dd->cspec->msix_entries[i].entry = i;
6789
6790 if (qib_pcie_params(dd, 8, &tabsize, dd->cspec->msix_entries))
6791 qib_dev_err(dd, "Failed to setup PCIe or interrupts; "
6792 "continuing anyway\n");
6793 /* may be less than we wanted, if not enough available */
6794 dd->cspec->num_msix_entries = tabsize;
6795
6796 /* setup interrupt handler */
6797 qib_setup_7322_interrupt(dd, 1);
6798
6799 /* clear diagctrl register, in case diags were running and crashed */
6800 qib_write_kreg(dd, kr_hwdiagctrl, 0);
6801
6802 goto bail;
6803
6804 bail_cleanup:
6805 qib_pcie_ddcleanup(dd);
6806 bail_free:
6807 qib_free_devdata(dd);
6808 dd = ERR_PTR(ret);
6809 bail:
6810 return dd;
6811 }
6812
6813 /*
6814 * Set the table entry at the specified index from the table specifed.
6815 * There are 3 * TXDDS_TABLE_SZ entries in all per port, with the first
6816 * TXDDS_TABLE_SZ for SDR, the next for DDR, and the last for QDR.
6817 * 'idx' below addresses the correct entry, while its 4 LSBs select the
6818 * corresponding entry (one of TXDDS_TABLE_SZ) from the selected table.
6819 */
6820 #define DDS_ENT_AMP_LSB 14
6821 #define DDS_ENT_MAIN_LSB 9
6822 #define DDS_ENT_POST_LSB 5
6823 #define DDS_ENT_PRE_XTRA_LSB 3
6824 #define DDS_ENT_PRE_LSB 0
6825
6826 /*
6827 * Set one entry in the TxDDS table for spec'd port
6828 * ridx picks one of the entries, while tp points
6829 * to the appropriate table entry.
6830 */
6831 static void set_txdds(struct qib_pportdata *ppd, int ridx,
6832 const struct txdds_ent *tp)
6833 {
6834 struct qib_devdata *dd = ppd->dd;
6835 u32 pack_ent;
6836 int regidx;
6837
6838 /* Get correct offset in chip-space, and in source table */
6839 regidx = KREG_IBPORT_IDX(IBSD_DDS_MAP_TABLE) + ridx;
6840 /*
6841 * We do not use qib_write_kreg_port() because it was intended
6842 * only for registers in the lower "port specific" pages.
6843 * So do index calculation by hand.
6844 */
6845 if (ppd->hw_pidx)
6846 regidx += (dd->palign / sizeof(u64));
6847
6848 pack_ent = tp->amp << DDS_ENT_AMP_LSB;
6849 pack_ent |= tp->main << DDS_ENT_MAIN_LSB;
6850 pack_ent |= tp->pre << DDS_ENT_PRE_LSB;
6851 pack_ent |= tp->post << DDS_ENT_POST_LSB;
6852 qib_write_kreg(dd, regidx, pack_ent);
6853 /* Prevent back-to-back writes by hitting scratch */
6854 qib_write_kreg(ppd->dd, kr_scratch, 0);
6855 }
6856
6857 static const struct vendor_txdds_ent vendor_txdds[] = {
6858 { /* Amphenol 1m 30awg NoEq */
6859 { 0x41, 0x50, 0x48 }, "584470002 ",
6860 { 10, 0, 0, 5 }, { 10, 0, 0, 9 }, { 7, 1, 0, 13 },
6861 },
6862 { /* Amphenol 3m 28awg NoEq */
6863 { 0x41, 0x50, 0x48 }, "584470004 ",
6864 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 7, 15 },
6865 },
6866 { /* Finisar 3m OM2 Optical */
6867 { 0x00, 0x90, 0x65 }, "FCBG410QB1C03-QL",
6868 { 0, 0, 0, 3 }, { 0, 0, 0, 4 }, { 0, 0, 0, 13 },
6869 },
6870 { /* Finisar 30m OM2 Optical */
6871 { 0x00, 0x90, 0x65 }, "FCBG410QB1C30-QL",
6872 { 0, 0, 0, 1 }, { 0, 0, 0, 5 }, { 0, 0, 0, 11 },
6873 },
6874 { /* Finisar Default OM2 Optical */
6875 { 0x00, 0x90, 0x65 }, NULL,
6876 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 0, 0, 12 },
6877 },
6878 { /* Gore 1m 30awg NoEq */
6879 { 0x00, 0x21, 0x77 }, "QSN3300-1 ",
6880 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 0, 15 },
6881 },
6882 { /* Gore 2m 30awg NoEq */
6883 { 0x00, 0x21, 0x77 }, "QSN3300-2 ",
6884 { 0, 0, 0, 8 }, { 0, 0, 0, 10 }, { 0, 1, 7, 15 },
6885 },
6886 { /* Gore 1m 28awg NoEq */
6887 { 0x00, 0x21, 0x77 }, "QSN3800-1 ",
6888 { 0, 0, 0, 6 }, { 0, 0, 0, 8 }, { 0, 1, 0, 15 },
6889 },
6890 { /* Gore 3m 28awg NoEq */
6891 { 0x00, 0x21, 0x77 }, "QSN3800-3 ",
6892 { 0, 0, 0, 9 }, { 0, 0, 0, 13 }, { 0, 1, 7, 15 },
6893 },
6894 { /* Gore 5m 24awg Eq */
6895 { 0x00, 0x21, 0x77 }, "QSN7000-5 ",
6896 { 0, 0, 0, 7 }, { 0, 0, 0, 9 }, { 0, 1, 3, 15 },
6897 },
6898 { /* Gore 7m 24awg Eq */
6899 { 0x00, 0x21, 0x77 }, "QSN7000-7 ",
6900 { 0, 0, 0, 9 }, { 0, 0, 0, 11 }, { 0, 2, 6, 15 },
6901 },
6902 { /* Gore 5m 26awg Eq */
6903 { 0x00, 0x21, 0x77 }, "QSN7600-5 ",
6904 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 0, 1, 9, 13 },
6905 },
6906 { /* Gore 7m 26awg Eq */
6907 { 0x00, 0x21, 0x77 }, "QSN7600-7 ",
6908 { 0, 0, 0, 8 }, { 0, 0, 0, 11 }, { 10, 1, 8, 15 },
6909 },
6910 { /* Intersil 12m 24awg Active */
6911 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1224",
6912 { 0, 0, 0, 2 }, { 0, 0, 0, 5 }, { 0, 3, 0, 9 },
6913 },
6914 { /* Intersil 10m 28awg Active */
6915 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP1028",
6916 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 2, 0, 2 },
6917 },
6918 { /* Intersil 7m 30awg Active */
6919 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0730",
6920 { 0, 0, 0, 6 }, { 0, 0, 0, 4 }, { 0, 1, 0, 3 },
6921 },
6922 { /* Intersil 5m 32awg Active */
6923 { 0x00, 0x30, 0xB4 }, "QLX4000CQSFP0532",
6924 { 0, 0, 0, 6 }, { 0, 0, 0, 6 }, { 0, 2, 0, 8 },
6925 },
6926 { /* Intersil Default Active */
6927 { 0x00, 0x30, 0xB4 }, NULL,
6928 { 0, 0, 0, 6 }, { 0, 0, 0, 5 }, { 0, 2, 0, 5 },
6929 },
6930 { /* Luxtera 20m Active Optical */
6931 { 0x00, 0x25, 0x63 }, NULL,
6932 { 0, 0, 0, 5 }, { 0, 0, 0, 8 }, { 0, 2, 0, 12 },
6933 },
6934 { /* Molex 1M Cu loopback */
6935 { 0x00, 0x09, 0x3A }, "74763-0025 ",
6936 { 2, 2, 6, 15 }, { 2, 2, 6, 15 }, { 2, 2, 6, 15 },
6937 },
6938 { /* Molex 2m 28awg NoEq */
6939 { 0x00, 0x09, 0x3A }, "74757-2201 ",
6940 { 0, 0, 0, 6 }, { 0, 0, 0, 9 }, { 0, 1, 1, 15 },
6941 },
6942 };
6943
6944 static const struct txdds_ent txdds_sdr[TXDDS_TABLE_SZ] = {
6945 /* amp, pre, main, post */
6946 { 2, 2, 15, 6 }, /* Loopback */
6947 { 0, 0, 0, 1 }, /* 2 dB */
6948 { 0, 0, 0, 2 }, /* 3 dB */
6949 { 0, 0, 0, 3 }, /* 4 dB */
6950 { 0, 0, 0, 4 }, /* 5 dB */
6951 { 0, 0, 0, 5 }, /* 6 dB */
6952 { 0, 0, 0, 6 }, /* 7 dB */
6953 { 0, 0, 0, 7 }, /* 8 dB */
6954 { 0, 0, 0, 8 }, /* 9 dB */
6955 { 0, 0, 0, 9 }, /* 10 dB */
6956 { 0, 0, 0, 10 }, /* 11 dB */
6957 { 0, 0, 0, 11 }, /* 12 dB */
6958 { 0, 0, 0, 12 }, /* 13 dB */
6959 { 0, 0, 0, 13 }, /* 14 dB */
6960 { 0, 0, 0, 14 }, /* 15 dB */
6961 { 0, 0, 0, 15 }, /* 16 dB */
6962 };
6963
6964 static const struct txdds_ent txdds_ddr[TXDDS_TABLE_SZ] = {
6965 /* amp, pre, main, post */
6966 { 2, 2, 15, 6 }, /* Loopback */
6967 { 0, 0, 0, 8 }, /* 2 dB */
6968 { 0, 0, 0, 8 }, /* 3 dB */
6969 { 0, 0, 0, 9 }, /* 4 dB */
6970 { 0, 0, 0, 9 }, /* 5 dB */
6971 { 0, 0, 0, 10 }, /* 6 dB */
6972 { 0, 0, 0, 10 }, /* 7 dB */
6973 { 0, 0, 0, 11 }, /* 8 dB */
6974 { 0, 0, 0, 11 }, /* 9 dB */
6975 { 0, 0, 0, 12 }, /* 10 dB */
6976 { 0, 0, 0, 12 }, /* 11 dB */
6977 { 0, 0, 0, 13 }, /* 12 dB */
6978 { 0, 0, 0, 13 }, /* 13 dB */
6979 { 0, 0, 0, 14 }, /* 14 dB */
6980 { 0, 0, 0, 14 }, /* 15 dB */
6981 { 0, 0, 0, 15 }, /* 16 dB */
6982 };
6983
6984 static const struct txdds_ent txdds_qdr[TXDDS_TABLE_SZ] = {
6985 /* amp, pre, main, post */
6986 { 2, 2, 15, 6 }, /* Loopback */
6987 { 0, 1, 0, 7 }, /* 2 dB (also QMH7342) */
6988 { 0, 1, 0, 9 }, /* 3 dB (also QMH7342) */
6989 { 0, 1, 0, 11 }, /* 4 dB */
6990 { 0, 1, 0, 13 }, /* 5 dB */
6991 { 0, 1, 0, 15 }, /* 6 dB */
6992 { 0, 1, 3, 15 }, /* 7 dB */
6993 { 0, 1, 7, 15 }, /* 8 dB */
6994 { 0, 1, 7, 15 }, /* 9 dB */
6995 { 0, 1, 8, 15 }, /* 10 dB */
6996 { 0, 1, 9, 15 }, /* 11 dB */
6997 { 0, 1, 10, 15 }, /* 12 dB */
6998 { 0, 2, 6, 15 }, /* 13 dB */
6999 { 0, 2, 7, 15 }, /* 14 dB */
7000 { 0, 2, 8, 15 }, /* 15 dB */
7001 { 0, 2, 9, 15 }, /* 16 dB */
7002 };
7003
7004 /*
7005 * extra entries for use with txselect, for indices >= TXDDS_TABLE_SZ.
7006 * These are mostly used for mez cards going through connectors
7007 * and backplane traces, but can be used to add other "unusual"
7008 * table values as well.
7009 */
7010 static const struct txdds_ent txdds_extra_sdr[TXDDS_EXTRA_SZ] = {
7011 /* amp, pre, main, post */
7012 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7013 { 0, 0, 0, 1 }, /* QMH7342 backplane settings */
7014 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7015 { 0, 0, 0, 2 }, /* QMH7342 backplane settings */
7016 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7017 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7018 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7019 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7020 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7021 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7022 { 0, 0, 0, 11 }, /* QME7342 backplane settings */
7023 { 0, 0, 0, 3 }, /* QMH7342 backplane settings */
7024 { 0, 0, 0, 4 }, /* QMH7342 backplane settings */
7025 };
7026
7027 static const struct txdds_ent txdds_extra_ddr[TXDDS_EXTRA_SZ] = {
7028 /* amp, pre, main, post */
7029 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7030 { 0, 0, 0, 7 }, /* QMH7342 backplane settings */
7031 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7032 { 0, 0, 0, 8 }, /* QMH7342 backplane settings */
7033 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7034 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7035 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7036 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7037 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7038 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7039 { 0, 0, 0, 13 }, /* QME7342 backplane settings */
7040 { 0, 0, 0, 9 }, /* QMH7342 backplane settings */
7041 { 0, 0, 0, 10 }, /* QMH7342 backplane settings */
7042 };
7043
7044 static const struct txdds_ent txdds_extra_qdr[TXDDS_EXTRA_SZ] = {
7045 /* amp, pre, main, post */
7046 { 0, 1, 0, 4 }, /* QMH7342 backplane settings */
7047 { 0, 1, 0, 5 }, /* QMH7342 backplane settings */
7048 { 0, 1, 0, 6 }, /* QMH7342 backplane settings */
7049 { 0, 1, 0, 8 }, /* QMH7342 backplane settings */
7050 { 0, 1, 12, 10 }, /* QME7342 backplane setting */
7051 { 0, 1, 12, 11 }, /* QME7342 backplane setting */
7052 { 0, 1, 12, 12 }, /* QME7342 backplane setting */
7053 { 0, 1, 12, 14 }, /* QME7342 backplane setting */
7054 { 0, 1, 12, 6 }, /* QME7342 backplane setting */
7055 { 0, 1, 12, 7 }, /* QME7342 backplane setting */
7056 { 0, 1, 12, 8 }, /* QME7342 backplane setting */
7057 { 0, 1, 0, 10 }, /* QMH7342 backplane settings */
7058 { 0, 1, 0, 12 }, /* QMH7342 backplane settings */
7059 };
7060
7061 static const struct txdds_ent txdds_extra_mfg[TXDDS_MFG_SZ] = {
7062 /* amp, pre, main, post */
7063 { 0, 0, 0, 0 }, /* QME7342 mfg settings */
7064 { 0, 0, 0, 6 }, /* QME7342 P2 mfg settings */
7065 };
7066
7067 static const struct txdds_ent *get_atten_table(const struct txdds_ent *txdds,
7068 unsigned atten)
7069 {
7070 /*
7071 * The attenuation table starts at 2dB for entry 1,
7072 * with entry 0 being the loopback entry.
7073 */
7074 if (atten <= 2)
7075 atten = 1;
7076 else if (atten > TXDDS_TABLE_SZ)
7077 atten = TXDDS_TABLE_SZ - 1;
7078 else
7079 atten--;
7080 return txdds + atten;
7081 }
7082
7083 /*
7084 * if override is set, the module parameter txselect has a value
7085 * for this specific port, so use it, rather than our normal mechanism.
7086 */
7087 static void find_best_ent(struct qib_pportdata *ppd,
7088 const struct txdds_ent **sdr_dds,
7089 const struct txdds_ent **ddr_dds,
7090 const struct txdds_ent **qdr_dds, int override)
7091 {
7092 struct qib_qsfp_cache *qd = &ppd->cpspec->qsfp_data.cache;
7093 int idx;
7094
7095 /* Search table of known cables */
7096 for (idx = 0; !override && idx < ARRAY_SIZE(vendor_txdds); ++idx) {
7097 const struct vendor_txdds_ent *v = vendor_txdds + idx;
7098
7099 if (!memcmp(v->oui, qd->oui, QSFP_VOUI_LEN) &&
7100 (!v->partnum ||
7101 !memcmp(v->partnum, qd->partnum, QSFP_PN_LEN))) {
7102 *sdr_dds = &v->sdr;
7103 *ddr_dds = &v->ddr;
7104 *qdr_dds = &v->qdr;
7105 return;
7106 }
7107 }
7108
7109 /* Lookup serdes setting by cable type and attenuation */
7110 if (!override && QSFP_IS_ACTIVE(qd->tech)) {
7111 *sdr_dds = txdds_sdr + ppd->dd->board_atten;
7112 *ddr_dds = txdds_ddr + ppd->dd->board_atten;
7113 *qdr_dds = txdds_qdr + ppd->dd->board_atten;
7114 return;
7115 }
7116
7117 if (!override && QSFP_HAS_ATTEN(qd->tech) && (qd->atten[0] ||
7118 qd->atten[1])) {
7119 *sdr_dds = get_atten_table(txdds_sdr, qd->atten[0]);
7120 *ddr_dds = get_atten_table(txdds_ddr, qd->atten[0]);
7121 *qdr_dds = get_atten_table(txdds_qdr, qd->atten[1]);
7122 return;
7123 } else if (ppd->cpspec->no_eep < TXDDS_TABLE_SZ) {
7124 /*
7125 * If we have no (or incomplete) data from the cable
7126 * EEPROM, or no QSFP, or override is set, use the
7127 * module parameter value to index into the attentuation
7128 * table.
7129 */
7130 idx = ppd->cpspec->no_eep;
7131 *sdr_dds = &txdds_sdr[idx];
7132 *ddr_dds = &txdds_ddr[idx];
7133 *qdr_dds = &txdds_qdr[idx];
7134 } else if (ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ)) {
7135 /* similar to above, but index into the "extra" table. */
7136 idx = ppd->cpspec->no_eep - TXDDS_TABLE_SZ;
7137 *sdr_dds = &txdds_extra_sdr[idx];
7138 *ddr_dds = &txdds_extra_ddr[idx];
7139 *qdr_dds = &txdds_extra_qdr[idx];
7140 } else if ((IS_QME(ppd->dd) || IS_QMH(ppd->dd)) &&
7141 ppd->cpspec->no_eep < (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ +
7142 TXDDS_MFG_SZ)) {
7143 idx = ppd->cpspec->no_eep - (TXDDS_TABLE_SZ + TXDDS_EXTRA_SZ);
7144 printk(KERN_INFO QIB_DRV_NAME
7145 " IB%u:%u use idx %u into txdds_mfg\n",
7146 ppd->dd->unit, ppd->port, idx);
7147 *sdr_dds = &txdds_extra_mfg[idx];
7148 *ddr_dds = &txdds_extra_mfg[idx];
7149 *qdr_dds = &txdds_extra_mfg[idx];
7150 } else {
7151 /* this shouldn't happen, it's range checked */
7152 *sdr_dds = txdds_sdr + qib_long_atten;
7153 *ddr_dds = txdds_ddr + qib_long_atten;
7154 *qdr_dds = txdds_qdr + qib_long_atten;
7155 }
7156 }
7157
7158 static void init_txdds_table(struct qib_pportdata *ppd, int override)
7159 {
7160 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7161 struct txdds_ent *dds;
7162 int idx;
7163 int single_ent = 0;
7164
7165 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, override);
7166
7167 /* for mez cards or override, use the selected value for all entries */
7168 if (!(ppd->dd->flags & QIB_HAS_QSFP) || override)
7169 single_ent = 1;
7170
7171 /* Fill in the first entry with the best entry found. */
7172 set_txdds(ppd, 0, sdr_dds);
7173 set_txdds(ppd, TXDDS_TABLE_SZ, ddr_dds);
7174 set_txdds(ppd, 2 * TXDDS_TABLE_SZ, qdr_dds);
7175 if (ppd->lflags & (QIBL_LINKINIT | QIBL_LINKARMED |
7176 QIBL_LINKACTIVE)) {
7177 dds = (struct txdds_ent *)(ppd->link_speed_active ==
7178 QIB_IB_QDR ? qdr_dds :
7179 (ppd->link_speed_active ==
7180 QIB_IB_DDR ? ddr_dds : sdr_dds));
7181 write_tx_serdes_param(ppd, dds);
7182 }
7183
7184 /* Fill in the remaining entries with the default table values. */
7185 for (idx = 1; idx < ARRAY_SIZE(txdds_sdr); ++idx) {
7186 set_txdds(ppd, idx, single_ent ? sdr_dds : txdds_sdr + idx);
7187 set_txdds(ppd, idx + TXDDS_TABLE_SZ,
7188 single_ent ? ddr_dds : txdds_ddr + idx);
7189 set_txdds(ppd, idx + 2 * TXDDS_TABLE_SZ,
7190 single_ent ? qdr_dds : txdds_qdr + idx);
7191 }
7192 }
7193
7194 #define KR_AHB_ACC KREG_IDX(ahb_access_ctrl)
7195 #define KR_AHB_TRANS KREG_IDX(ahb_transaction_reg)
7196 #define AHB_TRANS_RDY SYM_MASK(ahb_transaction_reg, ahb_rdy)
7197 #define AHB_ADDR_LSB SYM_LSB(ahb_transaction_reg, ahb_address)
7198 #define AHB_DATA_LSB SYM_LSB(ahb_transaction_reg, ahb_data)
7199 #define AHB_WR SYM_MASK(ahb_transaction_reg, write_not_read)
7200 #define AHB_TRANS_TRIES 10
7201
7202 /*
7203 * The chan argument is 0=chan0, 1=chan1, 2=pll, 3=chan2, 4=chan4,
7204 * 5=subsystem which is why most calls have "chan + chan >> 1"
7205 * for the channel argument.
7206 */
7207 static u32 ahb_mod(struct qib_devdata *dd, int quad, int chan, int addr,
7208 u32 data, u32 mask)
7209 {
7210 u32 rd_data, wr_data, sz_mask;
7211 u64 trans, acc, prev_acc;
7212 u32 ret = 0xBAD0BAD;
7213 int tries;
7214
7215 prev_acc = qib_read_kreg64(dd, KR_AHB_ACC);
7216 /* From this point on, make sure we return access */
7217 acc = (quad << 1) | 1;
7218 qib_write_kreg(dd, KR_AHB_ACC, acc);
7219
7220 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7221 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7222 if (trans & AHB_TRANS_RDY)
7223 break;
7224 }
7225 if (tries >= AHB_TRANS_TRIES) {
7226 qib_dev_err(dd, "No ahb_rdy in %d tries\n", AHB_TRANS_TRIES);
7227 goto bail;
7228 }
7229
7230 /* If mask is not all 1s, we need to read, but different SerDes
7231 * entities have different sizes
7232 */
7233 sz_mask = (1UL << ((quad == 1) ? 32 : 16)) - 1;
7234 wr_data = data & mask & sz_mask;
7235 if ((~mask & sz_mask) != 0) {
7236 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7237 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7238
7239 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7240 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7241 if (trans & AHB_TRANS_RDY)
7242 break;
7243 }
7244 if (tries >= AHB_TRANS_TRIES) {
7245 qib_dev_err(dd, "No Rd ahb_rdy in %d tries\n",
7246 AHB_TRANS_TRIES);
7247 goto bail;
7248 }
7249 /* Re-read in case host split reads and read data first */
7250 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7251 rd_data = (uint32_t)(trans >> AHB_DATA_LSB);
7252 wr_data |= (rd_data & ~mask & sz_mask);
7253 }
7254
7255 /* If mask is not zero, we need to write. */
7256 if (mask & sz_mask) {
7257 trans = ((chan << 6) | addr) << (AHB_ADDR_LSB + 1);
7258 trans |= ((uint64_t)wr_data << AHB_DATA_LSB);
7259 trans |= AHB_WR;
7260 qib_write_kreg(dd, KR_AHB_TRANS, trans);
7261
7262 for (tries = 1; tries < AHB_TRANS_TRIES; ++tries) {
7263 trans = qib_read_kreg64(dd, KR_AHB_TRANS);
7264 if (trans & AHB_TRANS_RDY)
7265 break;
7266 }
7267 if (tries >= AHB_TRANS_TRIES) {
7268 qib_dev_err(dd, "No Wr ahb_rdy in %d tries\n",
7269 AHB_TRANS_TRIES);
7270 goto bail;
7271 }
7272 }
7273 ret = wr_data;
7274 bail:
7275 qib_write_kreg(dd, KR_AHB_ACC, prev_acc);
7276 return ret;
7277 }
7278
7279 static void ibsd_wr_allchans(struct qib_pportdata *ppd, int addr, unsigned data,
7280 unsigned mask)
7281 {
7282 struct qib_devdata *dd = ppd->dd;
7283 int chan;
7284 u32 rbc;
7285
7286 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7287 ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)), addr,
7288 data, mask);
7289 rbc = ahb_mod(dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7290 addr, 0, 0);
7291 }
7292 }
7293
7294 static void serdes_7322_los_enable(struct qib_pportdata *ppd, int enable)
7295 {
7296 u64 data = qib_read_kreg_port(ppd, krp_serdesctrl);
7297 printk(KERN_INFO QIB_DRV_NAME " IB%u:%u Turning LOS %s\n",
7298 ppd->dd->unit, ppd->port, (enable ? "on" : "off"));
7299 if (enable)
7300 data |= SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7301 else
7302 data &= ~SYM_MASK(IBSerdesCtrl_0, RXLOSEN);
7303 qib_write_kreg_port(ppd, krp_serdesctrl, data);
7304 }
7305
7306 static int serdes_7322_init(struct qib_pportdata *ppd)
7307 {
7308 int ret = 0;
7309 if (ppd->dd->cspec->r1)
7310 ret = serdes_7322_init_old(ppd);
7311 else
7312 ret = serdes_7322_init_new(ppd);
7313 return ret;
7314 }
7315
7316 static int serdes_7322_init_old(struct qib_pportdata *ppd)
7317 {
7318 u32 le_val;
7319
7320 /*
7321 * Initialize the Tx DDS tables. Also done every QSFP event,
7322 * for adapters with QSFP
7323 */
7324 init_txdds_table(ppd, 0);
7325
7326 /* ensure no tx overrides from earlier driver loads */
7327 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7328 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7329 reset_tx_deemphasis_override));
7330
7331 /* Patch some SerDes defaults to "Better for IB" */
7332 /* Timing Loop Bandwidth: cdr_timing[11:9] = 0 */
7333 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7334
7335 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7336 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7337 /* Enable LE2: rxle2en_r2a addr 13 bit [6] = 1 */
7338 ibsd_wr_allchans(ppd, 13, (1 << 6), (1 << 6));
7339
7340 /* May be overridden in qsfp_7322_event */
7341 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7342 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7343
7344 /* enable LE1 adaptation for all but QME, which is disabled */
7345 le_val = IS_QME(ppd->dd) ? 0 : 1;
7346 ibsd_wr_allchans(ppd, 13, (le_val << 5), (1 << 5));
7347
7348 /* Clear cmode-override, may be set from older driver */
7349 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7350
7351 /* Timing Recovery: rxtapsel addr 5 bits [9:8] = 0 */
7352 ibsd_wr_allchans(ppd, 5, (0 << 8), BMASK(9, 8));
7353
7354 /* setup LoS params; these are subsystem, so chan == 5 */
7355 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7356 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7357 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7358 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7359 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7360
7361 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7362 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7363 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7364 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7365 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7366
7367 /* LoS filter select enabled */
7368 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7369
7370 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7371 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7372 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7373 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7374
7375 serdes_7322_los_enable(ppd, 1);
7376
7377 /* rxbistena; set 0 to avoid effects of it switch later */
7378 ibsd_wr_allchans(ppd, 9, 0 << 15, 1 << 15);
7379
7380 /* Configure 4 DFE taps, and only they adapt */
7381 ibsd_wr_allchans(ppd, 16, 0 << 0, BMASK(1, 0));
7382
7383 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7384 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7385 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7386
7387 /*
7388 * Set receive adaptation mode. SDR and DDR adaptation are
7389 * always on, and QDR is initially enabled; later disabled.
7390 */
7391 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7392 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7393 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7394 ppd->dd->cspec->r1 ?
7395 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7396 ppd->cpspec->qdr_dfe_on = 1;
7397
7398 /* FLoop LOS gate: PPM filter enabled */
7399 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7400
7401 /* rx offset center enabled */
7402 ibsd_wr_allchans(ppd, 12, 1 << 4, 1 << 4);
7403
7404 if (!ppd->dd->cspec->r1) {
7405 ibsd_wr_allchans(ppd, 12, 1 << 12, 1 << 12);
7406 ibsd_wr_allchans(ppd, 12, 2 << 8, 0x0f << 8);
7407 }
7408
7409 /* Set the frequency loop bandwidth to 15 */
7410 ibsd_wr_allchans(ppd, 2, 15 << 5, BMASK(8, 5));
7411
7412 return 0;
7413 }
7414
7415 static int serdes_7322_init_new(struct qib_pportdata *ppd)
7416 {
7417 u64 tstart;
7418 u32 le_val, rxcaldone;
7419 int chan, chan_done = (1 << SERDES_CHANS) - 1;
7420
7421 /*
7422 * Initialize the Tx DDS tables. Also done every QSFP event,
7423 * for adapters with QSFP
7424 */
7425 init_txdds_table(ppd, 0);
7426
7427 /* Clear cmode-override, may be set from older driver */
7428 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 0 << 14, 1 << 14);
7429
7430 /* ensure no tx overrides from earlier driver loads */
7431 qib_write_kreg_port(ppd, krp_tx_deemph_override,
7432 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7433 reset_tx_deemphasis_override));
7434
7435 /* START OF LSI SUGGESTED SERDES BRINGUP */
7436 /* Reset - Calibration Setup */
7437 /* Stop DFE adaptaion */
7438 ibsd_wr_allchans(ppd, 1, 0, BMASK(9, 1));
7439 /* Disable LE1 */
7440 ibsd_wr_allchans(ppd, 13, 0, BMASK(5, 5));
7441 /* Disable autoadapt for LE1 */
7442 ibsd_wr_allchans(ppd, 1, 0, BMASK(15, 15));
7443 /* Disable LE2 */
7444 ibsd_wr_allchans(ppd, 13, 0, BMASK(6, 6));
7445 /* Disable VGA */
7446 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7447 /* Disable AFE Offset Cancel */
7448 ibsd_wr_allchans(ppd, 12, 0, BMASK(12, 12));
7449 /* Disable Timing Loop */
7450 ibsd_wr_allchans(ppd, 2, 0, BMASK(3, 3));
7451 /* Disable Frequency Loop */
7452 ibsd_wr_allchans(ppd, 2, 0, BMASK(4, 4));
7453 /* Disable Baseline Wander Correction */
7454 ibsd_wr_allchans(ppd, 13, 0, BMASK(13, 13));
7455 /* Disable RX Calibration */
7456 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7457 /* Disable RX Offset Calibration */
7458 ibsd_wr_allchans(ppd, 12, 0, BMASK(4, 4));
7459 /* Select BB CDR */
7460 ibsd_wr_allchans(ppd, 2, (1 << 15), BMASK(15, 15));
7461 /* CDR Step Size */
7462 ibsd_wr_allchans(ppd, 5, 0, BMASK(9, 8));
7463 /* Enable phase Calibration */
7464 ibsd_wr_allchans(ppd, 12, (1 << 5), BMASK(5, 5));
7465 /* DFE Bandwidth [2:14-12] */
7466 ibsd_wr_allchans(ppd, 2, (4 << 12), BMASK(14, 12));
7467 /* DFE Config (4 taps only) */
7468 ibsd_wr_allchans(ppd, 16, 0, BMASK(1, 0));
7469 /* Gain Loop Bandwidth */
7470 if (!ppd->dd->cspec->r1) {
7471 ibsd_wr_allchans(ppd, 12, 1 << 12, BMASK(12, 12));
7472 ibsd_wr_allchans(ppd, 12, 2 << 8, BMASK(11, 8));
7473 } else {
7474 ibsd_wr_allchans(ppd, 19, (3 << 11), BMASK(13, 11));
7475 }
7476 /* Baseline Wander Correction Gain [13:4-0] (leave as default) */
7477 /* Baseline Wander Correction Gain [3:7-5] (leave as default) */
7478 /* Data Rate Select [5:7-6] (leave as default) */
7479 /* RX Parralel Word Width [3:10-8] (leave as default) */
7480
7481 /* RX REST */
7482 /* Single- or Multi-channel reset */
7483 /* RX Analog reset */
7484 /* RX Digital reset */
7485 ibsd_wr_allchans(ppd, 0, 0, BMASK(15, 13));
7486 msleep(20);
7487 /* RX Analog reset */
7488 ibsd_wr_allchans(ppd, 0, (1 << 14), BMASK(14, 14));
7489 msleep(20);
7490 /* RX Digital reset */
7491 ibsd_wr_allchans(ppd, 0, (1 << 13), BMASK(13, 13));
7492 msleep(20);
7493
7494 /* setup LoS params; these are subsystem, so chan == 5 */
7495 /* LoS filter threshold_count on, ch 0-3, set to 8 */
7496 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 5, 8 << 11, BMASK(14, 11));
7497 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 8 << 4, BMASK(7, 4));
7498 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 8, 8 << 11, BMASK(14, 11));
7499 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 8 << 4, BMASK(7, 4));
7500
7501 /* LoS filter threshold_count off, ch 0-3, set to 4 */
7502 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 6, 4 << 0, BMASK(3, 0));
7503 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 7, 4 << 8, BMASK(11, 8));
7504 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 4 << 0, BMASK(3, 0));
7505 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 10, 4 << 8, BMASK(11, 8));
7506
7507 /* LoS filter select enabled */
7508 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), 5, 9, 1 << 15, 1 << 15);
7509
7510 /* LoS target data: SDR=4, DDR=2, QDR=1 */
7511 ibsd_wr_allchans(ppd, 14, (1 << 3), BMASK(5, 3)); /* QDR */
7512 ibsd_wr_allchans(ppd, 20, (2 << 10), BMASK(12, 10)); /* DDR */
7513 ibsd_wr_allchans(ppd, 20, (4 << 13), BMASK(15, 13)); /* SDR */
7514
7515 /* Turn on LOS on initial SERDES init */
7516 serdes_7322_los_enable(ppd, 1);
7517 /* FLoop LOS gate: PPM filter enabled */
7518 ibsd_wr_allchans(ppd, 38, 0 << 10, 1 << 10);
7519
7520 /* RX LATCH CALIBRATION */
7521 /* Enable Eyefinder Phase Calibration latch */
7522 ibsd_wr_allchans(ppd, 15, 1, BMASK(0, 0));
7523 /* Enable RX Offset Calibration latch */
7524 ibsd_wr_allchans(ppd, 12, (1 << 4), BMASK(4, 4));
7525 msleep(20);
7526 /* Start Calibration */
7527 ibsd_wr_allchans(ppd, 4, (1 << 10), BMASK(10, 10));
7528 tstart = get_jiffies_64();
7529 while (chan_done &&
7530 !time_after64(tstart, tstart + msecs_to_jiffies(500))) {
7531 msleep(20);
7532 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7533 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7534 (chan + (chan >> 1)),
7535 25, 0, 0);
7536 if ((~rxcaldone & (u32)BMASK(9, 9)) == 0 &&
7537 (~chan_done & (1 << chan)) == 0)
7538 chan_done &= ~(1 << chan);
7539 }
7540 }
7541 if (chan_done) {
7542 printk(KERN_INFO QIB_DRV_NAME
7543 " Serdes %d calibration not done after .5 sec: 0x%x\n",
7544 IBSD(ppd->hw_pidx), chan_done);
7545 } else {
7546 for (chan = 0; chan < SERDES_CHANS; ++chan) {
7547 rxcaldone = ahb_mod(ppd->dd, IBSD(ppd->hw_pidx),
7548 (chan + (chan >> 1)),
7549 25, 0, 0);
7550 if ((~rxcaldone & (u32)BMASK(10, 10)) == 0)
7551 printk(KERN_INFO QIB_DRV_NAME
7552 " Serdes %d chan %d calibration "
7553 "failed\n", IBSD(ppd->hw_pidx), chan);
7554 }
7555 }
7556
7557 /* Turn off Calibration */
7558 ibsd_wr_allchans(ppd, 4, 0, BMASK(10, 10));
7559 msleep(20);
7560
7561 /* BRING RX UP */
7562 /* Set LE2 value (May be overridden in qsfp_7322_event) */
7563 le_val = IS_QME(ppd->dd) ? LE2_QME : LE2_DEFAULT;
7564 ibsd_wr_allchans(ppd, 13, (le_val << 7), BMASK(9, 7));
7565 /* Set LE2 Loop bandwidth */
7566 ibsd_wr_allchans(ppd, 3, (7 << 5), BMASK(7, 5));
7567 /* Enable LE2 */
7568 ibsd_wr_allchans(ppd, 13, (1 << 6), BMASK(6, 6));
7569 msleep(20);
7570 /* Enable H0 only */
7571 ibsd_wr_allchans(ppd, 1, 1, BMASK(9, 1));
7572 /* gain hi stop 32 (22) (6:1) lo stop 7 (10:7) target 22 (13) (15:11) */
7573 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac;
7574 ibsd_wr_allchans(ppd, 21, le_val, 0xfffe);
7575 /* Enable VGA */
7576 ibsd_wr_allchans(ppd, 5, 0, BMASK(0, 0));
7577 msleep(20);
7578 /* Set Frequency Loop Bandwidth */
7579 ibsd_wr_allchans(ppd, 2, (7 << 5), BMASK(8, 5));
7580 /* Enable Frequency Loop */
7581 ibsd_wr_allchans(ppd, 2, (1 << 4), BMASK(4, 4));
7582 /* Set Timing Loop Bandwidth */
7583 ibsd_wr_allchans(ppd, 2, 0, BMASK(11, 9));
7584 /* Enable Timing Loop */
7585 ibsd_wr_allchans(ppd, 2, (1 << 3), BMASK(3, 3));
7586 msleep(50);
7587 /* Enable DFE
7588 * Set receive adaptation mode. SDR and DDR adaptation are
7589 * always on, and QDR is initially enabled; later disabled.
7590 */
7591 qib_write_kreg_port(ppd, krp_static_adapt_dis(0), 0ULL);
7592 qib_write_kreg_port(ppd, krp_static_adapt_dis(1), 0ULL);
7593 qib_write_kreg_port(ppd, krp_static_adapt_dis(2),
7594 ppd->dd->cspec->r1 ?
7595 QDR_STATIC_ADAPT_DOWN_R1 : QDR_STATIC_ADAPT_DOWN);
7596 ppd->cpspec->qdr_dfe_on = 1;
7597 /* Disable LE1 */
7598 ibsd_wr_allchans(ppd, 13, (0 << 5), (1 << 5));
7599 /* Disable auto adapt for LE1 */
7600 ibsd_wr_allchans(ppd, 1, (0 << 15), BMASK(15, 15));
7601 msleep(20);
7602 /* Enable AFE Offset Cancel */
7603 ibsd_wr_allchans(ppd, 12, (1 << 12), BMASK(12, 12));
7604 /* Enable Baseline Wander Correction */
7605 ibsd_wr_allchans(ppd, 12, (1 << 13), BMASK(13, 13));
7606 /* Termination: rxtermctrl_r2d addr 11 bits [12:11] = 1 */
7607 ibsd_wr_allchans(ppd, 11, (1 << 11), BMASK(12, 11));
7608 /* VGA output common mode */
7609 ibsd_wr_allchans(ppd, 12, (3 << 2), BMASK(3, 2));
7610
7611 return 0;
7612 }
7613
7614 /* start adjust QMH serdes parameters */
7615
7616 static void set_man_code(struct qib_pportdata *ppd, int chan, int code)
7617 {
7618 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7619 9, code << 9, 0x3f << 9);
7620 }
7621
7622 static void set_man_mode_h1(struct qib_pportdata *ppd, int chan,
7623 int enable, u32 tapenable)
7624 {
7625 if (enable)
7626 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7627 1, 3 << 10, 0x1f << 10);
7628 else
7629 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7630 1, 0, 0x1f << 10);
7631 }
7632
7633 /* Set clock to 1, 0, 1, 0 */
7634 static void clock_man(struct qib_pportdata *ppd, int chan)
7635 {
7636 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7637 4, 0x4000, 0x4000);
7638 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7639 4, 0, 0x4000);
7640 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7641 4, 0x4000, 0x4000);
7642 ahb_mod(ppd->dd, IBSD(ppd->hw_pidx), (chan + (chan >> 1)),
7643 4, 0, 0x4000);
7644 }
7645
7646 /*
7647 * write the current Tx serdes pre,post,main,amp settings into the serdes.
7648 * The caller must pass the settings appropriate for the current speed,
7649 * or not care if they are correct for the current speed.
7650 */
7651 static void write_tx_serdes_param(struct qib_pportdata *ppd,
7652 struct txdds_ent *txdds)
7653 {
7654 u64 deemph;
7655
7656 deemph = qib_read_kreg_port(ppd, krp_tx_deemph_override);
7657 /* field names for amp, main, post, pre, respectively */
7658 deemph &= ~(SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txampcntl_d2a) |
7659 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txc0_ena) |
7660 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcp1_ena) |
7661 SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0, txcn1_ena));
7662
7663 deemph |= SYM_MASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7664 tx_override_deemphasis_select);
7665 deemph |= (txdds->amp & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7666 txampcntl_d2a)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7667 txampcntl_d2a);
7668 deemph |= (txdds->main & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7669 txc0_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7670 txc0_ena);
7671 deemph |= (txdds->post & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7672 txcp1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7673 txcp1_ena);
7674 deemph |= (txdds->pre & SYM_RMASK(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7675 txcn1_ena)) << SYM_LSB(IBSD_TX_DEEMPHASIS_OVERRIDE_0,
7676 txcn1_ena);
7677 qib_write_kreg_port(ppd, krp_tx_deemph_override, deemph);
7678 }
7679
7680 /*
7681 * Set the parameters for mez cards on link bounce, so they are
7682 * always exactly what was requested. Similar logic to init_txdds
7683 * but does just the serdes.
7684 */
7685 static void adj_tx_serdes(struct qib_pportdata *ppd)
7686 {
7687 const struct txdds_ent *sdr_dds, *ddr_dds, *qdr_dds;
7688 struct txdds_ent *dds;
7689
7690 find_best_ent(ppd, &sdr_dds, &ddr_dds, &qdr_dds, 1);
7691 dds = (struct txdds_ent *)(ppd->link_speed_active == QIB_IB_QDR ?
7692 qdr_dds : (ppd->link_speed_active == QIB_IB_DDR ?
7693 ddr_dds : sdr_dds));
7694 write_tx_serdes_param(ppd, dds);
7695 }
7696
7697 /* set QDR forced value for H1, if needed */
7698 static void force_h1(struct qib_pportdata *ppd)
7699 {
7700 int chan;
7701
7702 ppd->cpspec->qdr_reforce = 0;
7703 if (!ppd->dd->cspec->r1)
7704 return;
7705
7706 for (chan = 0; chan < SERDES_CHANS; chan++) {
7707 set_man_mode_h1(ppd, chan, 1, 0);
7708 set_man_code(ppd, chan, ppd->cpspec->h1_val);
7709 clock_man(ppd, chan);
7710 set_man_mode_h1(ppd, chan, 0, 0);
7711 }
7712 }
7713
7714 #define SJA_EN SYM_MASK(SPC_JTAG_ACCESS_REG, SPC_JTAG_ACCESS_EN)
7715 #define BISTEN_LSB SYM_LSB(SPC_JTAG_ACCESS_REG, bist_en)
7716
7717 #define R_OPCODE_LSB 3
7718 #define R_OP_NOP 0
7719 #define R_OP_SHIFT 2
7720 #define R_OP_UPDATE 3
7721 #define R_TDI_LSB 2
7722 #define R_TDO_LSB 1
7723 #define R_RDY 1
7724
7725 static int qib_r_grab(struct qib_devdata *dd)
7726 {
7727 u64 val;
7728 val = SJA_EN;
7729 qib_write_kreg(dd, kr_r_access, val);
7730 qib_read_kreg32(dd, kr_scratch);
7731 return 0;
7732 }
7733
7734 /* qib_r_wait_for_rdy() not only waits for the ready bit, it
7735 * returns the current state of R_TDO
7736 */
7737 static int qib_r_wait_for_rdy(struct qib_devdata *dd)
7738 {
7739 u64 val;
7740 int timeout;
7741 for (timeout = 0; timeout < 100 ; ++timeout) {
7742 val = qib_read_kreg32(dd, kr_r_access);
7743 if (val & R_RDY)
7744 return (val >> R_TDO_LSB) & 1;
7745 }
7746 return -1;
7747 }
7748
7749 static int qib_r_shift(struct qib_devdata *dd, int bisten,
7750 int len, u8 *inp, u8 *outp)
7751 {
7752 u64 valbase, val;
7753 int ret, pos;
7754
7755 valbase = SJA_EN | (bisten << BISTEN_LSB) |
7756 (R_OP_SHIFT << R_OPCODE_LSB);
7757 ret = qib_r_wait_for_rdy(dd);
7758 if (ret < 0)
7759 goto bail;
7760 for (pos = 0; pos < len; ++pos) {
7761 val = valbase;
7762 if (outp) {
7763 outp[pos >> 3] &= ~(1 << (pos & 7));
7764 outp[pos >> 3] |= (ret << (pos & 7));
7765 }
7766 if (inp) {
7767 int tdi = inp[pos >> 3] >> (pos & 7);
7768 val |= ((tdi & 1) << R_TDI_LSB);
7769 }
7770 qib_write_kreg(dd, kr_r_access, val);
7771 qib_read_kreg32(dd, kr_scratch);
7772 ret = qib_r_wait_for_rdy(dd);
7773 if (ret < 0)
7774 break;
7775 }
7776 /* Restore to NOP between operations. */
7777 val = SJA_EN | (bisten << BISTEN_LSB);
7778 qib_write_kreg(dd, kr_r_access, val);
7779 qib_read_kreg32(dd, kr_scratch);
7780 ret = qib_r_wait_for_rdy(dd);
7781
7782 if (ret >= 0)
7783 ret = pos;
7784 bail:
7785 return ret;
7786 }
7787
7788 static int qib_r_update(struct qib_devdata *dd, int bisten)
7789 {
7790 u64 val;
7791 int ret;
7792
7793 val = SJA_EN | (bisten << BISTEN_LSB) | (R_OP_UPDATE << R_OPCODE_LSB);
7794 ret = qib_r_wait_for_rdy(dd);
7795 if (ret >= 0) {
7796 qib_write_kreg(dd, kr_r_access, val);
7797 qib_read_kreg32(dd, kr_scratch);
7798 }
7799 return ret;
7800 }
7801
7802 #define BISTEN_PORT_SEL 15
7803 #define LEN_PORT_SEL 625
7804 #define BISTEN_AT 17
7805 #define LEN_AT 156
7806 #define BISTEN_ETM 16
7807 #define LEN_ETM 632
7808
7809 #define BIT2BYTE(x) (((x) + BITS_PER_BYTE - 1) / BITS_PER_BYTE)
7810
7811 /* these are common for all IB port use cases. */
7812 static u8 reset_at[BIT2BYTE(LEN_AT)] = {
7813 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7814 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7815 };
7816 static u8 reset_atetm[BIT2BYTE(LEN_ETM)] = {
7817 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7818 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7819 0x00, 0x00, 0x00, 0x80, 0xe3, 0x81, 0x73, 0x3c, 0x70, 0x8e,
7820 0x07, 0xce, 0xf1, 0xc0, 0x39, 0x1e, 0x38, 0xc7, 0x03, 0xe7,
7821 0x78, 0xe0, 0x1c, 0x0f, 0x9c, 0x7f, 0x80, 0x73, 0x0f, 0x70,
7822 0xde, 0x01, 0xce, 0x39, 0xc0, 0xf9, 0x06, 0x38, 0xd7, 0x00,
7823 0xe7, 0x19, 0xe0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7824 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00,
7825 };
7826 static u8 at[BIT2BYTE(LEN_AT)] = {
7827 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00,
7828 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00,
7829 };
7830
7831 /* used for IB1 or IB2, only one in use */
7832 static u8 atetm_1port[BIT2BYTE(LEN_ETM)] = {
7833 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7834 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7835 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7836 0x00, 0x10, 0xf2, 0x80, 0x83, 0x1e, 0x38, 0x00, 0x00, 0x00,
7837 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7838 0x00, 0x00, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xc8, 0x03,
7839 0x07, 0x7b, 0xa0, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x18, 0x00,
7840 0x18, 0x00, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00,
7841 };
7842
7843 /* used when both IB1 and IB2 are in use */
7844 static u8 atetm_2port[BIT2BYTE(LEN_ETM)] = {
7845 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7846 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79,
7847 0xc0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
7848 0x00, 0x00, 0xf8, 0x80, 0x83, 0x1e, 0x38, 0xe0, 0x03, 0x05,
7849 0x7b, 0xa0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80,
7850 0xa2, 0x0f, 0x50, 0xf4, 0x41, 0x00, 0x18, 0x78, 0xd1, 0x07,
7851 0x02, 0x7c, 0x80, 0x3e, 0x00, 0x02, 0x00, 0x00, 0x3e, 0x00,
7852 0x02, 0x00, 0x00, 0x00, 0x00, 0x64, 0x00, 0x00, 0x00,
7853 };
7854
7855 /* used when only IB1 is in use */
7856 static u8 portsel_port1[BIT2BYTE(LEN_PORT_SEL)] = {
7857 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7858 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7859 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7860 0x13, 0x78, 0x78, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7861 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7862 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7863 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7864 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7865 };
7866
7867 /* used when only IB2 is in use */
7868 static u8 portsel_port2[BIT2BYTE(LEN_PORT_SEL)] = {
7869 0x32, 0x65, 0xa4, 0x7b, 0x10, 0x98, 0xdc, 0xfe, 0x39, 0x39,
7870 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x73, 0x32, 0x32, 0x32,
7871 0x32, 0x32, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7872 0x39, 0x78, 0x78, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39, 0x39,
7873 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x74, 0x32,
7874 0x32, 0x32, 0x32, 0x32, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7875 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a, 0x3a,
7876 0x3a, 0x3a, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01,
7877 };
7878
7879 /* used when both IB1 and IB2 are in use */
7880 static u8 portsel_2port[BIT2BYTE(LEN_PORT_SEL)] = {
7881 0x32, 0xba, 0x54, 0x76, 0x10, 0x98, 0xdc, 0xfe, 0x13, 0x13,
7882 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x73, 0x0c, 0x0c, 0x0c,
7883 0x0c, 0x0c, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7884 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13, 0x13,
7885 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x74, 0x32,
7886 0x32, 0x32, 0x32, 0x32, 0x14, 0x14, 0x14, 0x14, 0x14, 0x3a,
7887 0x3a, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14, 0x14,
7888 0x14, 0x14, 0x9f, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00,
7889 };
7890
7891 /*
7892 * Do setup to properly handle IB link recovery; if port is zero, we
7893 * are initializing to cover both ports; otherwise we are initializing
7894 * to cover a single port card, or the port has reached INIT and we may
7895 * need to switch coverage types.
7896 */
7897 static void setup_7322_link_recovery(struct qib_pportdata *ppd, u32 both)
7898 {
7899 u8 *portsel, *etm;
7900 struct qib_devdata *dd = ppd->dd;
7901
7902 if (!ppd->dd->cspec->r1)
7903 return;
7904 if (!both) {
7905 dd->cspec->recovery_ports_initted++;
7906 ppd->cpspec->recovery_init = 1;
7907 }
7908 if (!both && dd->cspec->recovery_ports_initted == 1) {
7909 portsel = ppd->port == 1 ? portsel_port1 : portsel_port2;
7910 etm = atetm_1port;
7911 } else {
7912 portsel = portsel_2port;
7913 etm = atetm_2port;
7914 }
7915
7916 if (qib_r_grab(dd) < 0 ||
7917 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, reset_atetm, NULL) < 0 ||
7918 qib_r_update(dd, BISTEN_ETM) < 0 ||
7919 qib_r_shift(dd, BISTEN_AT, LEN_AT, reset_at, NULL) < 0 ||
7920 qib_r_update(dd, BISTEN_AT) < 0 ||
7921 qib_r_shift(dd, BISTEN_PORT_SEL, LEN_PORT_SEL,
7922 portsel, NULL) < 0 ||
7923 qib_r_update(dd, BISTEN_PORT_SEL) < 0 ||
7924 qib_r_shift(dd, BISTEN_AT, LEN_AT, at, NULL) < 0 ||
7925 qib_r_update(dd, BISTEN_AT) < 0 ||
7926 qib_r_shift(dd, BISTEN_ETM, LEN_ETM, etm, NULL) < 0 ||
7927 qib_r_update(dd, BISTEN_ETM) < 0)
7928 qib_dev_err(dd, "Failed IB link recovery setup\n");
7929 }
7930
7931 static void check_7322_rxe_status(struct qib_pportdata *ppd)
7932 {
7933 struct qib_devdata *dd = ppd->dd;
7934 u64 fmask;
7935
7936 if (dd->cspec->recovery_ports_initted != 1)
7937 return; /* rest doesn't apply to dualport */
7938 qib_write_kreg(dd, kr_control, dd->control |
7939 SYM_MASK(Control, FreezeMode));
7940 (void)qib_read_kreg64(dd, kr_scratch);
7941 udelay(3); /* ibcreset asserted 400ns, be sure that's over */
7942 fmask = qib_read_kreg64(dd, kr_act_fmask);
7943 if (!fmask) {
7944 /*
7945 * require a powercycle before we'll work again, and make
7946 * sure we get no more interrupts, and don't turn off
7947 * freeze.
7948 */
7949 ppd->dd->cspec->stay_in_freeze = 1;
7950 qib_7322_set_intr_state(ppd->dd, 0);
7951 qib_write_kreg(dd, kr_fmask, 0ULL);
7952 qib_dev_err(dd, "HCA unusable until powercycled\n");
7953 return; /* eventually reset */
7954 }
7955
7956 qib_write_kreg(ppd->dd, kr_hwerrclear,
7957 SYM_MASK(HwErrClear, IBSerdesPClkNotDetectClear_1));
7958
7959 /* don't do the full clear_freeze(), not needed for this */
7960 qib_write_kreg(dd, kr_control, dd->control);
7961 qib_read_kreg32(dd, kr_scratch);
7962 /* take IBC out of reset */
7963 if (ppd->link_speed_supported) {
7964 ppd->cpspec->ibcctrl_a &=
7965 ~SYM_MASK(IBCCtrlA_0, IBStatIntReductionEn);
7966 qib_write_kreg_port(ppd, krp_ibcctrl_a,
7967 ppd->cpspec->ibcctrl_a);
7968 qib_read_kreg32(dd, kr_scratch);
7969 if (ppd->lflags & QIBL_IB_LINK_DISABLED)
7970 qib_set_ib_7322_lstate(ppd, 0,
7971 QLOGIC_IB_IBCC_LINKINITCMD_DISABLE);
7972 }
7973 }