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ASoC: cs42l52: Improve two size determinations in cs42l52_i2c_probe()
[mirror_ubuntu-jammy-kernel.git] / drivers / input / touchscreen / hideep.c
1 /*
2 * Copyright (C) 2012-2017 Hideep, Inc.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License version 2
6 * as published by the Free Software Foudation.
7 */
8
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/firmware.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/gpio/machine.h>
15 #include <linux/i2c.h>
16 #include <linux/acpi.h>
17 #include <linux/interrupt.h>
18 #include <linux/regmap.h>
19 #include <linux/sysfs.h>
20 #include <linux/input.h>
21 #include <linux/input/mt.h>
22 #include <linux/input/touchscreen.h>
23 #include <linux/regulator/consumer.h>
24 #include <asm/unaligned.h>
25
26 #define HIDEEP_TS_NAME "HiDeep Touchscreen"
27 #define HIDEEP_I2C_NAME "hideep_ts"
28
29 #define HIDEEP_MT_MAX 10
30 #define HIDEEP_KEY_MAX 3
31
32 /* count(2) + touch data(100) + key data(6) */
33 #define HIDEEP_MAX_EVENT 108UL
34
35 #define HIDEEP_TOUCH_EVENT_INDEX 2
36 #define HIDEEP_KEY_EVENT_INDEX 102
37
38 /* Touch & key event */
39 #define HIDEEP_EVENT_ADDR 0x240
40
41 /* command list */
42 #define HIDEEP_RESET_CMD 0x9800
43
44 /* event bit */
45 #define HIDEEP_MT_RELEASED BIT(4)
46 #define HIDEEP_KEY_PRESSED BIT(7)
47 #define HIDEEP_KEY_FIRST_PRESSED BIT(8)
48 #define HIDEEP_KEY_PRESSED_MASK (HIDEEP_KEY_PRESSED | \
49 HIDEEP_KEY_FIRST_PRESSED)
50
51 #define HIDEEP_KEY_IDX_MASK 0x0f
52
53 /* For NVM */
54 #define HIDEEP_YRAM_BASE 0x40000000
55 #define HIDEEP_PERIPHERAL_BASE 0x50000000
56 #define HIDEEP_ESI_BASE (HIDEEP_PERIPHERAL_BASE + 0x00000000)
57 #define HIDEEP_FLASH_BASE (HIDEEP_PERIPHERAL_BASE + 0x01000000)
58 #define HIDEEP_SYSCON_BASE (HIDEEP_PERIPHERAL_BASE + 0x02000000)
59
60 #define HIDEEP_SYSCON_MOD_CON (HIDEEP_SYSCON_BASE + 0x0000)
61 #define HIDEEP_SYSCON_SPC_CON (HIDEEP_SYSCON_BASE + 0x0004)
62 #define HIDEEP_SYSCON_CLK_CON (HIDEEP_SYSCON_BASE + 0x0008)
63 #define HIDEEP_SYSCON_CLK_ENA (HIDEEP_SYSCON_BASE + 0x000C)
64 #define HIDEEP_SYSCON_RST_CON (HIDEEP_SYSCON_BASE + 0x0010)
65 #define HIDEEP_SYSCON_WDT_CON (HIDEEP_SYSCON_BASE + 0x0014)
66 #define HIDEEP_SYSCON_WDT_CNT (HIDEEP_SYSCON_BASE + 0x0018)
67 #define HIDEEP_SYSCON_PWR_CON (HIDEEP_SYSCON_BASE + 0x0020)
68 #define HIDEEP_SYSCON_PGM_ID (HIDEEP_SYSCON_BASE + 0x00F4)
69
70 #define HIDEEP_FLASH_CON (HIDEEP_FLASH_BASE + 0x0000)
71 #define HIDEEP_FLASH_STA (HIDEEP_FLASH_BASE + 0x0004)
72 #define HIDEEP_FLASH_CFG (HIDEEP_FLASH_BASE + 0x0008)
73 #define HIDEEP_FLASH_TIM (HIDEEP_FLASH_BASE + 0x000C)
74 #define HIDEEP_FLASH_CACHE_CFG (HIDEEP_FLASH_BASE + 0x0010)
75 #define HIDEEP_FLASH_PIO_SIG (HIDEEP_FLASH_BASE + 0x400000)
76
77 #define HIDEEP_ESI_TX_INVALID (HIDEEP_ESI_BASE + 0x0008)
78
79 #define HIDEEP_PERASE 0x00040000
80 #define HIDEEP_WRONLY 0x00100000
81
82 #define HIDEEP_NVM_MASK_OFS 0x0000000C
83 #define HIDEEP_NVM_DEFAULT_PAGE 0
84 #define HIDEEP_NVM_SFR_WPAGE 1
85 #define HIDEEP_NVM_SFR_RPAGE 2
86
87 #define HIDEEP_PIO_SIG 0x00400000
88 #define HIDEEP_PROT_MODE 0x03400000
89
90 #define HIDEEP_NVM_PAGE_SIZE 128
91
92 #define HIDEEP_DWZ_INFO 0x000002C0
93
94 struct hideep_event {
95 __le16 x;
96 __le16 y;
97 __le16 z;
98 u8 w;
99 u8 flag;
100 u8 type;
101 u8 index;
102 };
103
104 struct dwz_info {
105 __be32 code_start;
106 u8 code_crc[12];
107
108 __be32 c_code_start;
109 __be16 gen_ver;
110 __be16 c_code_len;
111
112 __be32 vr_start;
113 __be16 rsv0;
114 __be16 vr_len;
115
116 __be32 ft_start;
117 __be16 vr_version;
118 __be16 ft_len;
119
120 __be16 core_ver;
121 __be16 boot_ver;
122
123 __be16 release_ver;
124 __be16 custom_ver;
125
126 u8 factory_id;
127 u8 panel_type;
128 u8 model_name[6];
129
130 __be16 extra_option;
131 __be16 product_code;
132
133 __be16 vendor_id;
134 __be16 product_id;
135 };
136
137 struct pgm_packet {
138 struct {
139 u8 unused[3];
140 u8 len;
141 __be32 addr;
142 } header;
143 __be32 payload[HIDEEP_NVM_PAGE_SIZE / sizeof(__be32)];
144 };
145
146 #define HIDEEP_XFER_BUF_SIZE sizeof(struct pgm_packet)
147
148 struct hideep_ts {
149 struct i2c_client *client;
150 struct input_dev *input_dev;
151 struct regmap *reg;
152
153 struct touchscreen_properties prop;
154
155 struct gpio_desc *reset_gpio;
156
157 struct regulator *vcc_vdd;
158 struct regulator *vcc_vid;
159
160 struct mutex dev_mutex;
161
162 u32 tch_count;
163 u32 lpm_count;
164
165 /*
166 * Data buffer to read packet from the device (contacts and key
167 * states). We align it on double-word boundary to keep word-sized
168 * fields in contact data and double-word-sized fields in program
169 * packet aligned.
170 */
171 u8 xfer_buf[HIDEEP_XFER_BUF_SIZE] __aligned(4);
172
173 int key_num;
174 u32 key_codes[HIDEEP_KEY_MAX];
175
176 struct dwz_info dwz_info;
177
178 unsigned int fw_size;
179 u32 nvm_mask;
180 };
181
182 static int hideep_pgm_w_mem(struct hideep_ts *ts, u32 addr,
183 const __be32 *data, size_t count)
184 {
185 struct pgm_packet *packet = (void *)ts->xfer_buf;
186 size_t len = count * sizeof(*data);
187 struct i2c_msg msg = {
188 .addr = ts->client->addr,
189 .len = len + sizeof(packet->header.len) +
190 sizeof(packet->header.addr),
191 .buf = &packet->header.len,
192 };
193 int ret;
194
195 if (len > HIDEEP_NVM_PAGE_SIZE)
196 return -EINVAL;
197
198 packet->header.len = 0x80 | (count - 1);
199 packet->header.addr = cpu_to_be32(addr);
200 memcpy(packet->payload, data, len);
201
202 ret = i2c_transfer(ts->client->adapter, &msg, 1);
203 if (ret != 1)
204 return ret < 0 ? ret : -EIO;
205
206 return 0;
207 }
208
209 static int hideep_pgm_r_mem(struct hideep_ts *ts, u32 addr,
210 __be32 *data, size_t count)
211 {
212 struct pgm_packet *packet = (void *)ts->xfer_buf;
213 size_t len = count * sizeof(*data);
214 struct i2c_msg msg[] = {
215 {
216 .addr = ts->client->addr,
217 .len = sizeof(packet->header.len) +
218 sizeof(packet->header.addr),
219 .buf = &packet->header.len,
220 },
221 {
222 .addr = ts->client->addr,
223 .flags = I2C_M_RD,
224 .len = len,
225 .buf = (u8 *)data,
226 },
227 };
228 int ret;
229
230 if (len > HIDEEP_NVM_PAGE_SIZE)
231 return -EINVAL;
232
233 packet->header.len = count - 1;
234 packet->header.addr = cpu_to_be32(addr);
235
236 ret = i2c_transfer(ts->client->adapter, msg, ARRAY_SIZE(msg));
237 if (ret != ARRAY_SIZE(msg))
238 return ret < 0 ? ret : -EIO;
239
240 return 0;
241 }
242
243 static int hideep_pgm_r_reg(struct hideep_ts *ts, u32 addr, u32 *val)
244 {
245 __be32 data;
246 int error;
247
248 error = hideep_pgm_r_mem(ts, addr, &data, 1);
249 if (error) {
250 dev_err(&ts->client->dev,
251 "read of register %#08x failed: %d\n",
252 addr, error);
253 return error;
254 }
255
256 *val = be32_to_cpu(data);
257 return 0;
258 }
259
260 static int hideep_pgm_w_reg(struct hideep_ts *ts, u32 addr, u32 val)
261 {
262 __be32 data = cpu_to_be32(val);
263 int error;
264
265 error = hideep_pgm_w_mem(ts, addr, &data, 1);
266 if (error) {
267 dev_err(&ts->client->dev,
268 "write to register %#08x (%#08x) failed: %d\n",
269 addr, val, error);
270 return error;
271 }
272
273 return 0;
274 }
275
276 #define SW_RESET_IN_PGM(clk) \
277 { \
278 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CNT, (clk)); \
279 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x03); \
280 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x01); \
281 }
282
283 #define SET_FLASH_PIO(ce) \
284 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, \
285 0x01 | ((ce) << 1))
286
287 #define SET_PIO_SIG(x, y) \
288 hideep_pgm_w_reg(ts, HIDEEP_FLASH_PIO_SIG + (x), (y))
289
290 #define SET_FLASH_HWCONTROL() \
291 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CON, 0x00)
292
293 #define NVM_W_SFR(x, y) \
294 { \
295 SET_FLASH_PIO(1); \
296 SET_PIO_SIG(x, y); \
297 SET_FLASH_PIO(0); \
298 }
299
300 static void hideep_pgm_set(struct hideep_ts *ts)
301 {
302 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_WDT_CON, 0x00);
303 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_SPC_CON, 0x00);
304 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_ENA, 0xFF);
305 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_CLK_CON, 0x01);
306 hideep_pgm_w_reg(ts, HIDEEP_SYSCON_PWR_CON, 0x01);
307 hideep_pgm_w_reg(ts, HIDEEP_FLASH_TIM, 0x03);
308 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CACHE_CFG, 0x00);
309 }
310
311 static int hideep_pgm_get_pattern(struct hideep_ts *ts, u32 *pattern)
312 {
313 u16 p1 = 0xAF39;
314 u16 p2 = 0xDF9D;
315 int error;
316
317 error = regmap_bulk_write(ts->reg, p1, &p2, 1);
318 if (error) {
319 dev_err(&ts->client->dev,
320 "%s: regmap_bulk_write() failed with %d\n",
321 __func__, error);
322 return error;
323 }
324
325 usleep_range(1000, 1100);
326
327 /* flush invalid Tx load register */
328 error = hideep_pgm_w_reg(ts, HIDEEP_ESI_TX_INVALID, 0x01);
329 if (error)
330 return error;
331
332 error = hideep_pgm_r_reg(ts, HIDEEP_SYSCON_PGM_ID, pattern);
333 if (error)
334 return error;
335
336 return 0;
337 }
338
339 static int hideep_enter_pgm(struct hideep_ts *ts)
340 {
341 int retry_count = 10;
342 u32 pattern;
343 int error;
344
345 while (retry_count--) {
346 error = hideep_pgm_get_pattern(ts, &pattern);
347 if (error) {
348 dev_err(&ts->client->dev,
349 "hideep_pgm_get_pattern failed: %d\n", error);
350 } else if (pattern != 0x39AF9DDF) {
351 dev_err(&ts->client->dev, "%s: bad pattern: %#08x\n",
352 __func__, pattern);
353 } else {
354 dev_dbg(&ts->client->dev, "found magic code");
355
356 hideep_pgm_set(ts);
357 usleep_range(1000, 1100);
358
359 return 0;
360 }
361 }
362
363 dev_err(&ts->client->dev, "failed to enter pgm mode\n");
364 SW_RESET_IN_PGM(1000);
365 return -EIO;
366 }
367
368 static void hideep_nvm_unlock(struct hideep_ts *ts)
369 {
370 u32 unmask_code;
371
372 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_RPAGE);
373 hideep_pgm_r_reg(ts, 0x0000000C, &unmask_code);
374 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
375
376 /* make it unprotected code */
377 unmask_code &= ~HIDEEP_PROT_MODE;
378
379 /* compare unmask code */
380 if (unmask_code != ts->nvm_mask)
381 dev_warn(&ts->client->dev,
382 "read mask code different %#08x vs %#08x",
383 unmask_code, ts->nvm_mask);
384
385 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_SFR_WPAGE);
386 SET_FLASH_PIO(0);
387
388 NVM_W_SFR(HIDEEP_NVM_MASK_OFS, ts->nvm_mask);
389 SET_FLASH_HWCONTROL();
390 hideep_pgm_w_reg(ts, HIDEEP_FLASH_CFG, HIDEEP_NVM_DEFAULT_PAGE);
391 }
392
393 static int hideep_check_status(struct hideep_ts *ts)
394 {
395 int time_out = 100;
396 int status;
397 int error;
398
399 while (time_out--) {
400 error = hideep_pgm_r_reg(ts, HIDEEP_FLASH_STA, &status);
401 if (!error && status)
402 return 0;
403
404 usleep_range(1000, 1100);
405 }
406
407 return -ETIMEDOUT;
408 }
409
410 static int hideep_program_page(struct hideep_ts *ts, u32 addr,
411 const __be32 *ucode, size_t xfer_count)
412 {
413 u32 val;
414 int error;
415
416 error = hideep_check_status(ts);
417 if (error)
418 return -EBUSY;
419
420 addr &= ~(HIDEEP_NVM_PAGE_SIZE - 1);
421
422 SET_FLASH_PIO(0);
423 SET_FLASH_PIO(1);
424
425 /* erase page */
426 SET_PIO_SIG(HIDEEP_PERASE | addr, 0xFFFFFFFF);
427
428 SET_FLASH_PIO(0);
429
430 error = hideep_check_status(ts);
431 if (error)
432 return -EBUSY;
433
434 /* write page */
435 SET_FLASH_PIO(1);
436
437 val = be32_to_cpu(ucode[0]);
438 SET_PIO_SIG(HIDEEP_WRONLY | addr, val);
439
440 hideep_pgm_w_mem(ts, HIDEEP_FLASH_PIO_SIG | HIDEEP_WRONLY,
441 ucode, xfer_count);
442
443 val = be32_to_cpu(ucode[xfer_count - 1]);
444 SET_PIO_SIG(124, val);
445
446 SET_FLASH_PIO(0);
447
448 usleep_range(1000, 1100);
449
450 error = hideep_check_status(ts);
451 if (error)
452 return -EBUSY;
453
454 SET_FLASH_HWCONTROL();
455
456 return 0;
457 }
458
459 static int hideep_program_nvm(struct hideep_ts *ts,
460 const __be32 *ucode, size_t ucode_len)
461 {
462 struct pgm_packet *packet_r = (void *)ts->xfer_buf;
463 __be32 *current_ucode = packet_r->payload;
464 size_t xfer_len;
465 size_t xfer_count;
466 u32 addr = 0;
467 int error;
468
469 hideep_nvm_unlock(ts);
470
471 while (ucode_len > 0) {
472 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
473 xfer_count = xfer_len / sizeof(*ucode);
474
475 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
476 current_ucode, xfer_count);
477 if (error) {
478 dev_err(&ts->client->dev,
479 "%s: failed to read page at offset %#08x: %d\n",
480 __func__, addr, error);
481 return error;
482 }
483
484 /* See if the page needs updating */
485 if (memcmp(ucode, current_ucode, xfer_len)) {
486 error = hideep_program_page(ts, addr,
487 ucode, xfer_count);
488 if (error) {
489 dev_err(&ts->client->dev,
490 "%s: iwrite failure @%#08x: %d\n",
491 __func__, addr, error);
492 return error;
493 }
494
495 usleep_range(1000, 1100);
496 }
497
498 ucode += xfer_count;
499 addr += xfer_len;
500 ucode_len -= xfer_len;
501 }
502
503 return 0;
504 }
505
506 static int hideep_verify_nvm(struct hideep_ts *ts,
507 const __be32 *ucode, size_t ucode_len)
508 {
509 struct pgm_packet *packet_r = (void *)ts->xfer_buf;
510 __be32 *current_ucode = packet_r->payload;
511 size_t xfer_len;
512 size_t xfer_count;
513 u32 addr = 0;
514 int i;
515 int error;
516
517 while (ucode_len > 0) {
518 xfer_len = min_t(size_t, ucode_len, HIDEEP_NVM_PAGE_SIZE);
519 xfer_count = xfer_len / sizeof(*ucode);
520
521 error = hideep_pgm_r_mem(ts, 0x00000000 + addr,
522 current_ucode, xfer_count);
523 if (error) {
524 dev_err(&ts->client->dev,
525 "%s: failed to read page at offset %#08x: %d\n",
526 __func__, addr, error);
527 return error;
528 }
529
530 if (memcmp(ucode, current_ucode, xfer_len)) {
531 const u8 *ucode_bytes = (const u8 *)ucode;
532 const u8 *current_bytes = (const u8 *)current_ucode;
533
534 for (i = 0; i < xfer_len; i++)
535 if (ucode_bytes[i] != current_bytes[i])
536 dev_err(&ts->client->dev,
537 "%s: mismatch @%#08x: (%#02x vs %#02x)\n",
538 __func__, addr + i,
539 ucode_bytes[i],
540 current_bytes[i]);
541
542 return -EIO;
543 }
544
545 ucode += xfer_count;
546 addr += xfer_len;
547 ucode_len -= xfer_len;
548 }
549
550 return 0;
551 }
552
553 static int hideep_load_dwz(struct hideep_ts *ts)
554 {
555 u16 product_code;
556 int error;
557
558 error = hideep_enter_pgm(ts);
559 if (error)
560 return error;
561
562 msleep(50);
563
564 error = hideep_pgm_r_mem(ts, HIDEEP_DWZ_INFO,
565 (void *)&ts->dwz_info,
566 sizeof(ts->dwz_info) / sizeof(__be32));
567
568 SW_RESET_IN_PGM(10);
569 msleep(50);
570
571 if (error) {
572 dev_err(&ts->client->dev,
573 "failed to fetch DWZ data: %d\n", error);
574 return error;
575 }
576
577 product_code = be16_to_cpu(ts->dwz_info.product_code);
578
579 switch (product_code & 0xF0) {
580 case 0x40:
581 dev_dbg(&ts->client->dev, "used crimson IC");
582 ts->fw_size = 1024 * 48;
583 ts->nvm_mask = 0x00310000;
584 break;
585 case 0x60:
586 dev_dbg(&ts->client->dev, "used lime IC");
587 ts->fw_size = 1024 * 64;
588 ts->nvm_mask = 0x0030027B;
589 break;
590 default:
591 dev_err(&ts->client->dev, "product code is wrong: %#04x",
592 product_code);
593 return -EINVAL;
594 }
595
596 dev_dbg(&ts->client->dev, "firmware release version: %#04x",
597 be16_to_cpu(ts->dwz_info.release_ver));
598
599 return 0;
600 }
601
602 static int hideep_flash_firmware(struct hideep_ts *ts,
603 const __be32 *ucode, size_t ucode_len)
604 {
605 int retry_cnt = 3;
606 int error;
607
608 while (retry_cnt--) {
609 error = hideep_program_nvm(ts, ucode, ucode_len);
610 if (!error) {
611 error = hideep_verify_nvm(ts, ucode, ucode_len);
612 if (!error)
613 return 0;
614 }
615 }
616
617 return error;
618 }
619
620 static int hideep_update_firmware(struct hideep_ts *ts,
621 const __be32 *ucode, size_t ucode_len)
622 {
623 int error, error2;
624
625 dev_dbg(&ts->client->dev, "starting firmware update");
626
627 /* enter program mode */
628 error = hideep_enter_pgm(ts);
629 if (error)
630 return error;
631
632 error = hideep_flash_firmware(ts, ucode, ucode_len);
633 if (error)
634 dev_err(&ts->client->dev,
635 "firmware update failed: %d\n", error);
636 else
637 dev_dbg(&ts->client->dev, "firmware updated successfully\n");
638
639 SW_RESET_IN_PGM(1000);
640
641 error2 = hideep_load_dwz(ts);
642 if (error2)
643 dev_err(&ts->client->dev,
644 "failed to load dwz after firmware update: %d\n",
645 error2);
646
647 return error ?: error2;
648 }
649
650 static int hideep_power_on(struct hideep_ts *ts)
651 {
652 int error = 0;
653
654 error = regulator_enable(ts->vcc_vdd);
655 if (error)
656 dev_err(&ts->client->dev,
657 "failed to enable 'vdd' regulator: %d", error);
658
659 usleep_range(999, 1000);
660
661 error = regulator_enable(ts->vcc_vid);
662 if (error)
663 dev_err(&ts->client->dev,
664 "failed to enable 'vcc_vid' regulator: %d",
665 error);
666
667 msleep(30);
668
669 if (ts->reset_gpio) {
670 gpiod_set_value_cansleep(ts->reset_gpio, 0);
671 } else {
672 error = regmap_write(ts->reg, HIDEEP_RESET_CMD, 0x01);
673 if (error)
674 dev_err(&ts->client->dev,
675 "failed to send 'reset' command: %d\n", error);
676 }
677
678 msleep(50);
679
680 return error;
681 }
682
683 static void hideep_power_off(void *data)
684 {
685 struct hideep_ts *ts = data;
686
687 if (ts->reset_gpio)
688 gpiod_set_value(ts->reset_gpio, 1);
689
690 regulator_disable(ts->vcc_vid);
691 regulator_disable(ts->vcc_vdd);
692 }
693
694 #define __GET_MT_TOOL_TYPE(type) ((type) == 0x01 ? MT_TOOL_FINGER : MT_TOOL_PEN)
695
696 static void hideep_report_slot(struct input_dev *input,
697 const struct hideep_event *event)
698 {
699 input_mt_slot(input, event->index & 0x0f);
700 input_mt_report_slot_state(input,
701 __GET_MT_TOOL_TYPE(event->type),
702 !(event->flag & HIDEEP_MT_RELEASED));
703 if (!(event->flag & HIDEEP_MT_RELEASED)) {
704 input_report_abs(input, ABS_MT_POSITION_X,
705 le16_to_cpup(&event->x));
706 input_report_abs(input, ABS_MT_POSITION_Y,
707 le16_to_cpup(&event->y));
708 input_report_abs(input, ABS_MT_PRESSURE,
709 le16_to_cpup(&event->z));
710 input_report_abs(input, ABS_MT_TOUCH_MAJOR, event->w);
711 }
712 }
713
714 static void hideep_parse_and_report(struct hideep_ts *ts)
715 {
716 const struct hideep_event *events =
717 (void *)&ts->xfer_buf[HIDEEP_TOUCH_EVENT_INDEX];
718 const u8 *keys = &ts->xfer_buf[HIDEEP_KEY_EVENT_INDEX];
719 int touch_count = ts->xfer_buf[0];
720 int key_count = ts->xfer_buf[1] & 0x0f;
721 int lpm_count = ts->xfer_buf[1] & 0xf0;
722 int i;
723
724 /* get touch event count */
725 dev_dbg(&ts->client->dev, "mt = %d, key = %d, lpm = %02x",
726 touch_count, key_count, lpm_count);
727
728 touch_count = min(touch_count, HIDEEP_MT_MAX);
729 for (i = 0; i < touch_count; i++)
730 hideep_report_slot(ts->input_dev, events + i);
731
732 key_count = min(key_count, HIDEEP_KEY_MAX);
733 for (i = 0; i < key_count; i++) {
734 u8 key_data = keys[i * 2];
735
736 input_report_key(ts->input_dev,
737 ts->key_codes[key_data & HIDEEP_KEY_IDX_MASK],
738 key_data & HIDEEP_KEY_PRESSED_MASK);
739 }
740
741 input_mt_sync_frame(ts->input_dev);
742 input_sync(ts->input_dev);
743 }
744
745 static irqreturn_t hideep_irq(int irq, void *handle)
746 {
747 struct hideep_ts *ts = handle;
748 int error;
749
750 BUILD_BUG_ON(HIDEEP_MAX_EVENT > HIDEEP_XFER_BUF_SIZE);
751
752 error = regmap_bulk_read(ts->reg, HIDEEP_EVENT_ADDR,
753 ts->xfer_buf, HIDEEP_MAX_EVENT / 2);
754 if (error) {
755 dev_err(&ts->client->dev, "failed to read events: %d\n", error);
756 goto out;
757 }
758
759 hideep_parse_and_report(ts);
760
761 out:
762 return IRQ_HANDLED;
763 }
764
765 static int hideep_get_axis_info(struct hideep_ts *ts)
766 {
767 __le16 val[2];
768 int error;
769
770 error = regmap_bulk_read(ts->reg, 0x28, val, ARRAY_SIZE(val));
771 if (error)
772 return error;
773
774 ts->prop.max_x = le16_to_cpup(val);
775 ts->prop.max_y = le16_to_cpup(val + 1);
776
777 dev_dbg(&ts->client->dev, "X: %d, Y: %d",
778 ts->prop.max_x, ts->prop.max_y);
779
780 return 0;
781 }
782
783 static int hideep_init_input(struct hideep_ts *ts)
784 {
785 struct device *dev = &ts->client->dev;
786 int i;
787 int error;
788
789 ts->input_dev = devm_input_allocate_device(dev);
790 if (!ts->input_dev) {
791 dev_err(dev, "failed to allocate input device\n");
792 return -ENOMEM;
793 }
794
795 ts->input_dev->name = HIDEEP_TS_NAME;
796 ts->input_dev->id.bustype = BUS_I2C;
797 input_set_drvdata(ts->input_dev, ts);
798
799 input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_X);
800 input_set_capability(ts->input_dev, EV_ABS, ABS_MT_POSITION_Y);
801 input_set_abs_params(ts->input_dev, ABS_MT_PRESSURE, 0, 65535, 0, 0);
802 input_set_abs_params(ts->input_dev, ABS_MT_TOUCH_MAJOR, 0, 255, 0, 0);
803 input_set_abs_params(ts->input_dev, ABS_MT_TOOL_TYPE,
804 0, MT_TOOL_MAX, 0, 0);
805 touchscreen_parse_properties(ts->input_dev, true, &ts->prop);
806
807 if (ts->prop.max_x == 0 || ts->prop.max_y == 0) {
808 error = hideep_get_axis_info(ts);
809 if (error)
810 return error;
811 }
812
813 error = input_mt_init_slots(ts->input_dev, HIDEEP_MT_MAX,
814 INPUT_MT_DIRECT);
815 if (error)
816 return error;
817
818 ts->key_num = device_property_read_u32_array(dev, "linux,keycodes",
819 NULL, 0);
820 if (ts->key_num > HIDEEP_KEY_MAX) {
821 dev_err(dev, "too many keys defined: %d\n",
822 ts->key_num);
823 return -EINVAL;
824 }
825
826 if (ts->key_num <= 0) {
827 dev_dbg(dev,
828 "missing or malformed 'linux,keycodes' property\n");
829 } else {
830 error = device_property_read_u32_array(dev, "linux,keycodes",
831 ts->key_codes,
832 ts->key_num);
833 if (error) {
834 dev_dbg(dev, "failed to read keymap: %d", error);
835 return error;
836 }
837
838 if (ts->key_num) {
839 ts->input_dev->keycode = ts->key_codes;
840 ts->input_dev->keycodesize = sizeof(ts->key_codes[0]);
841 ts->input_dev->keycodemax = ts->key_num;
842
843 for (i = 0; i < ts->key_num; i++)
844 input_set_capability(ts->input_dev, EV_KEY,
845 ts->key_codes[i]);
846 }
847 }
848
849 error = input_register_device(ts->input_dev);
850 if (error) {
851 dev_err(dev, "failed to register input device: %d", error);
852 return error;
853 }
854
855 return 0;
856 }
857
858 static ssize_t hideep_update_fw(struct device *dev,
859 struct device_attribute *attr,
860 const char *buf, size_t count)
861 {
862 struct i2c_client *client = to_i2c_client(dev);
863 struct hideep_ts *ts = i2c_get_clientdata(client);
864 const struct firmware *fw_entry;
865 char *fw_name;
866 int mode;
867 int error;
868
869 error = kstrtoint(buf, 0, &mode);
870 if (error)
871 return error;
872
873 fw_name = kasprintf(GFP_KERNEL, "hideep_ts_%04x.bin",
874 be16_to_cpu(ts->dwz_info.product_id));
875 if (!fw_name)
876 return -ENOMEM;
877
878 error = request_firmware(&fw_entry, fw_name, dev);
879 if (error) {
880 dev_err(dev, "failed to request firmware %s: %d",
881 fw_name, error);
882 goto out_free_fw_name;
883 }
884
885 if (fw_entry->size % sizeof(__be32)) {
886 dev_err(dev, "invalid firmware size %zu\n", fw_entry->size);
887 error = -EINVAL;
888 goto out_release_fw;
889 }
890
891 if (fw_entry->size > ts->fw_size) {
892 dev_err(dev, "fw size (%zu) is too big (memory size %d)\n",
893 fw_entry->size, ts->fw_size);
894 error = -EFBIG;
895 goto out_release_fw;
896 }
897
898 mutex_lock(&ts->dev_mutex);
899 disable_irq(client->irq);
900
901 error = hideep_update_firmware(ts, (const __be32 *)fw_entry->data,
902 fw_entry->size);
903
904 enable_irq(client->irq);
905 mutex_unlock(&ts->dev_mutex);
906
907 out_release_fw:
908 release_firmware(fw_entry);
909 out_free_fw_name:
910 kfree(fw_name);
911
912 return error ?: count;
913 }
914
915 static ssize_t hideep_fw_version_show(struct device *dev,
916 struct device_attribute *attr, char *buf)
917 {
918 struct i2c_client *client = to_i2c_client(dev);
919 struct hideep_ts *ts = i2c_get_clientdata(client);
920 ssize_t len;
921
922 mutex_lock(&ts->dev_mutex);
923 len = scnprintf(buf, PAGE_SIZE, "%04x\n",
924 be16_to_cpu(ts->dwz_info.release_ver));
925 mutex_unlock(&ts->dev_mutex);
926
927 return len;
928 }
929
930 static ssize_t hideep_product_id_show(struct device *dev,
931 struct device_attribute *attr, char *buf)
932 {
933 struct i2c_client *client = to_i2c_client(dev);
934 struct hideep_ts *ts = i2c_get_clientdata(client);
935 ssize_t len;
936
937 mutex_lock(&ts->dev_mutex);
938 len = scnprintf(buf, PAGE_SIZE, "%04x\n",
939 be16_to_cpu(ts->dwz_info.product_id));
940 mutex_unlock(&ts->dev_mutex);
941
942 return len;
943 }
944
945 static DEVICE_ATTR(version, 0664, hideep_fw_version_show, NULL);
946 static DEVICE_ATTR(product_id, 0664, hideep_product_id_show, NULL);
947 static DEVICE_ATTR(update_fw, 0664, NULL, hideep_update_fw);
948
949 static struct attribute *hideep_ts_sysfs_entries[] = {
950 &dev_attr_version.attr,
951 &dev_attr_product_id.attr,
952 &dev_attr_update_fw.attr,
953 NULL,
954 };
955
956 static const struct attribute_group hideep_ts_attr_group = {
957 .attrs = hideep_ts_sysfs_entries,
958 };
959
960 static int __maybe_unused hideep_suspend(struct device *dev)
961 {
962 struct i2c_client *client = to_i2c_client(dev);
963 struct hideep_ts *ts = i2c_get_clientdata(client);
964
965 disable_irq(client->irq);
966 hideep_power_off(ts);
967
968 return 0;
969 }
970
971 static int __maybe_unused hideep_resume(struct device *dev)
972 {
973 struct i2c_client *client = to_i2c_client(dev);
974 struct hideep_ts *ts = i2c_get_clientdata(client);
975 int error;
976
977 error = hideep_power_on(ts);
978 if (error) {
979 dev_err(&client->dev, "power on failed");
980 return error;
981 }
982
983 enable_irq(client->irq);
984
985 return 0;
986 }
987
988 static SIMPLE_DEV_PM_OPS(hideep_pm_ops, hideep_suspend, hideep_resume);
989
990 static const struct regmap_config hideep_regmap_config = {
991 .reg_bits = 16,
992 .reg_format_endian = REGMAP_ENDIAN_LITTLE,
993 .val_bits = 16,
994 .val_format_endian = REGMAP_ENDIAN_LITTLE,
995 .max_register = 0xffff,
996 };
997
998 static int hideep_probe(struct i2c_client *client,
999 const struct i2c_device_id *id)
1000 {
1001 struct hideep_ts *ts;
1002 int error;
1003
1004 /* check i2c bus */
1005 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1006 dev_err(&client->dev, "check i2c device error");
1007 return -ENODEV;
1008 }
1009
1010 if (client->irq <= 0) {
1011 dev_err(&client->dev, "missing irq: %d\n", client->irq);
1012 return -EINVAL;
1013 }
1014
1015 ts = devm_kzalloc(&client->dev, sizeof(*ts), GFP_KERNEL);
1016 if (!ts)
1017 return -ENOMEM;
1018
1019 ts->client = client;
1020 i2c_set_clientdata(client, ts);
1021 mutex_init(&ts->dev_mutex);
1022
1023 ts->reg = devm_regmap_init_i2c(client, &hideep_regmap_config);
1024 if (IS_ERR(ts->reg)) {
1025 error = PTR_ERR(ts->reg);
1026 dev_err(&client->dev,
1027 "failed to initialize regmap: %d\n", error);
1028 return error;
1029 }
1030
1031 ts->vcc_vdd = devm_regulator_get(&client->dev, "vdd");
1032 if (IS_ERR(ts->vcc_vdd))
1033 return PTR_ERR(ts->vcc_vdd);
1034
1035 ts->vcc_vid = devm_regulator_get(&client->dev, "vid");
1036 if (IS_ERR(ts->vcc_vid))
1037 return PTR_ERR(ts->vcc_vid);
1038
1039 ts->reset_gpio = devm_gpiod_get_optional(&client->dev,
1040 "reset", GPIOD_OUT_HIGH);
1041 if (IS_ERR(ts->reset_gpio))
1042 return PTR_ERR(ts->reset_gpio);
1043
1044 error = hideep_power_on(ts);
1045 if (error) {
1046 dev_err(&client->dev, "power on failed: %d\n", error);
1047 return error;
1048 }
1049
1050 error = devm_add_action_or_reset(&client->dev, hideep_power_off, ts);
1051 if (error)
1052 return error;
1053
1054 error = hideep_load_dwz(ts);
1055 if (error) {
1056 dev_err(&client->dev, "failed to load dwz: %d", error);
1057 return error;
1058 }
1059
1060 error = hideep_init_input(ts);
1061 if (error)
1062 return error;
1063
1064 error = devm_request_threaded_irq(&client->dev, client->irq,
1065 NULL, hideep_irq, IRQF_ONESHOT,
1066 client->name, ts);
1067 if (error) {
1068 dev_err(&client->dev, "failed to request irq %d: %d\n",
1069 client->irq, error);
1070 return error;
1071 }
1072
1073 error = devm_device_add_group(&client->dev, &hideep_ts_attr_group);
1074 if (error) {
1075 dev_err(&client->dev,
1076 "failed to add sysfs attributes: %d\n", error);
1077 return error;
1078 }
1079
1080 return 0;
1081 }
1082
1083 static const struct i2c_device_id hideep_i2c_id[] = {
1084 { HIDEEP_I2C_NAME, 0 },
1085 { }
1086 };
1087 MODULE_DEVICE_TABLE(i2c, hideep_i2c_id);
1088
1089 #ifdef CONFIG_ACPI
1090 static const struct acpi_device_id hideep_acpi_id[] = {
1091 { "HIDP0001", 0 },
1092 { }
1093 };
1094 MODULE_DEVICE_TABLE(acpi, hideep_acpi_id);
1095 #endif
1096
1097 #ifdef CONFIG_OF
1098 static const struct of_device_id hideep_match_table[] = {
1099 { .compatible = "hideep,hideep-ts" },
1100 { }
1101 };
1102 MODULE_DEVICE_TABLE(of, hideep_match_table);
1103 #endif
1104
1105 static struct i2c_driver hideep_driver = {
1106 .driver = {
1107 .name = HIDEEP_I2C_NAME,
1108 .of_match_table = of_match_ptr(hideep_match_table),
1109 .acpi_match_table = ACPI_PTR(hideep_acpi_id),
1110 .pm = &hideep_pm_ops,
1111 },
1112 .id_table = hideep_i2c_id,
1113 .probe = hideep_probe,
1114 };
1115
1116 module_i2c_driver(hideep_driver);
1117
1118 MODULE_DESCRIPTION("Driver for HiDeep Touchscreen Controller");
1119 MODULE_AUTHOR("anthony.kim@hideep.com");
1120 MODULE_LICENSE("GPL v2");
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