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1 /*
2 * Philips UCB1400 touchscreen driver
3 *
4 * Author: Nicolas Pitre
5 * Created: September 25, 2006
6 * Copyright: MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
13 * covering the UCB1100, UCB1200 and UCB1300.. Support for the UCB1400 has
14 * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
15 */
16
17 #include <linux/module.h>
18 #include <linux/moduleparam.h>
19 #include <linux/init.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/input.h>
23 #include <linux/device.h>
24 #include <linux/interrupt.h>
25 #include <linux/suspend.h>
26 #include <linux/slab.h>
27 #include <linux/kthread.h>
28 #include <linux/freezer.h>
29
30 #include <sound/driver.h>
31 #include <sound/core.h>
32 #include <sound/ac97_codec.h>
33
34
35 /*
36 * Interesting UCB1400 AC-link registers
37 */
38
39 #define UCB_IE_RIS 0x5e
40 #define UCB_IE_FAL 0x60
41 #define UCB_IE_STATUS 0x62
42 #define UCB_IE_CLEAR 0x62
43 #define UCB_IE_ADC (1 << 11)
44 #define UCB_IE_TSPX (1 << 12)
45
46 #define UCB_TS_CR 0x64
47 #define UCB_TS_CR_TSMX_POW (1 << 0)
48 #define UCB_TS_CR_TSPX_POW (1 << 1)
49 #define UCB_TS_CR_TSMY_POW (1 << 2)
50 #define UCB_TS_CR_TSPY_POW (1 << 3)
51 #define UCB_TS_CR_TSMX_GND (1 << 4)
52 #define UCB_TS_CR_TSPX_GND (1 << 5)
53 #define UCB_TS_CR_TSMY_GND (1 << 6)
54 #define UCB_TS_CR_TSPY_GND (1 << 7)
55 #define UCB_TS_CR_MODE_INT (0 << 8)
56 #define UCB_TS_CR_MODE_PRES (1 << 8)
57 #define UCB_TS_CR_MODE_POS (2 << 8)
58 #define UCB_TS_CR_BIAS_ENA (1 << 11)
59 #define UCB_TS_CR_TSPX_LOW (1 << 12)
60 #define UCB_TS_CR_TSMX_LOW (1 << 13)
61
62 #define UCB_ADC_CR 0x66
63 #define UCB_ADC_SYNC_ENA (1 << 0)
64 #define UCB_ADC_VREFBYP_CON (1 << 1)
65 #define UCB_ADC_INP_TSPX (0 << 2)
66 #define UCB_ADC_INP_TSMX (1 << 2)
67 #define UCB_ADC_INP_TSPY (2 << 2)
68 #define UCB_ADC_INP_TSMY (3 << 2)
69 #define UCB_ADC_INP_AD0 (4 << 2)
70 #define UCB_ADC_INP_AD1 (5 << 2)
71 #define UCB_ADC_INP_AD2 (6 << 2)
72 #define UCB_ADC_INP_AD3 (7 << 2)
73 #define UCB_ADC_EXT_REF (1 << 5)
74 #define UCB_ADC_START (1 << 7)
75 #define UCB_ADC_ENA (1 << 15)
76
77 #define UCB_ADC_DATA 0x68
78 #define UCB_ADC_DAT_VALID (1 << 15)
79 #define UCB_ADC_DAT_VALUE(x) ((x) & 0x3ff)
80
81 #define UCB_ID 0x7e
82 #define UCB_ID_1400 0x4304
83
84
85 struct ucb1400 {
86 struct snd_ac97 *ac97;
87 struct input_dev *ts_idev;
88
89 int irq;
90
91 wait_queue_head_t ts_wait;
92 struct task_struct *ts_task;
93
94 unsigned int irq_pending; /* not bit field shared */
95 unsigned int ts_restart:1;
96 unsigned int adcsync:1;
97 };
98
99 static int adcsync;
100 static int ts_delay = 55; /* us */
101 static int ts_delay_pressure; /* us */
102
103 static inline u16 ucb1400_reg_read(struct ucb1400 *ucb, u16 reg)
104 {
105 return ucb->ac97->bus->ops->read(ucb->ac97, reg);
106 }
107
108 static inline void ucb1400_reg_write(struct ucb1400 *ucb, u16 reg, u16 val)
109 {
110 ucb->ac97->bus->ops->write(ucb->ac97, reg, val);
111 }
112
113 static inline void ucb1400_adc_enable(struct ucb1400 *ucb)
114 {
115 ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
116 }
117
118 static unsigned int ucb1400_adc_read(struct ucb1400 *ucb, u16 adc_channel)
119 {
120 unsigned int val;
121
122 if (ucb->adcsync)
123 adc_channel |= UCB_ADC_SYNC_ENA;
124
125 ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
126 ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | adc_channel | UCB_ADC_START);
127
128 for (;;) {
129 val = ucb1400_reg_read(ucb, UCB_ADC_DATA);
130 if (val & UCB_ADC_DAT_VALID)
131 break;
132 /* yield to other processes */
133 set_current_state(TASK_INTERRUPTIBLE);
134 schedule_timeout(1);
135 }
136
137 return UCB_ADC_DAT_VALUE(val);
138 }
139
140 static inline void ucb1400_adc_disable(struct ucb1400 *ucb)
141 {
142 ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
143 }
144
145 /* Switch to interrupt mode. */
146 static inline void ucb1400_ts_mode_int(struct ucb1400 *ucb)
147 {
148 ucb1400_reg_write(ucb, UCB_TS_CR,
149 UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
150 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
151 UCB_TS_CR_MODE_INT);
152 }
153
154 /*
155 * Switch to pressure mode, and read pressure. We don't need to wait
156 * here, since both plates are being driven.
157 */
158 static inline unsigned int ucb1400_ts_read_pressure(struct ucb1400 *ucb)
159 {
160 ucb1400_reg_write(ucb, UCB_TS_CR,
161 UCB_TS_CR_TSMX_POW | UCB_TS_CR_TSPX_POW |
162 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_GND |
163 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
164 udelay(ts_delay_pressure);
165 return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
166 }
167
168 /*
169 * Switch to X position mode and measure Y plate. We switch the plate
170 * configuration in pressure mode, then switch to position mode. This
171 * gives a faster response time. Even so, we need to wait about 55us
172 * for things to stabilise.
173 */
174 static inline unsigned int ucb1400_ts_read_xpos(struct ucb1400 *ucb)
175 {
176 ucb1400_reg_write(ucb, UCB_TS_CR,
177 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
178 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
179 ucb1400_reg_write(ucb, UCB_TS_CR,
180 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
181 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
182 ucb1400_reg_write(ucb, UCB_TS_CR,
183 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
184 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
185
186 udelay(ts_delay);
187
188 return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPY);
189 }
190
191 /*
192 * Switch to Y position mode and measure X plate. We switch the plate
193 * configuration in pressure mode, then switch to position mode. This
194 * gives a faster response time. Even so, we need to wait about 55us
195 * for things to stabilise.
196 */
197 static inline unsigned int ucb1400_ts_read_ypos(struct ucb1400 *ucb)
198 {
199 ucb1400_reg_write(ucb, UCB_TS_CR,
200 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
201 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
202 ucb1400_reg_write(ucb, UCB_TS_CR,
203 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
204 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
205 ucb1400_reg_write(ucb, UCB_TS_CR,
206 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
207 UCB_TS_CR_MODE_POS | UCB_TS_CR_BIAS_ENA);
208
209 udelay(ts_delay);
210
211 return ucb1400_adc_read(ucb, UCB_ADC_INP_TSPX);
212 }
213
214 /*
215 * Switch to X plate resistance mode. Set MX to ground, PX to
216 * supply. Measure current.
217 */
218 static inline unsigned int ucb1400_ts_read_xres(struct ucb1400 *ucb)
219 {
220 ucb1400_reg_write(ucb, UCB_TS_CR,
221 UCB_TS_CR_TSMX_GND | UCB_TS_CR_TSPX_POW |
222 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
223 return ucb1400_adc_read(ucb, 0);
224 }
225
226 /*
227 * Switch to Y plate resistance mode. Set MY to ground, PY to
228 * supply. Measure current.
229 */
230 static inline unsigned int ucb1400_ts_read_yres(struct ucb1400 *ucb)
231 {
232 ucb1400_reg_write(ucb, UCB_TS_CR,
233 UCB_TS_CR_TSMY_GND | UCB_TS_CR_TSPY_POW |
234 UCB_TS_CR_MODE_PRES | UCB_TS_CR_BIAS_ENA);
235 return ucb1400_adc_read(ucb, 0);
236 }
237
238 static inline int ucb1400_ts_pen_down(struct ucb1400 *ucb)
239 {
240 unsigned short val = ucb1400_reg_read(ucb, UCB_TS_CR);
241 return (val & (UCB_TS_CR_TSPX_LOW | UCB_TS_CR_TSMX_LOW));
242 }
243
244 static inline void ucb1400_ts_irq_enable(struct ucb1400 *ucb)
245 {
246 ucb1400_reg_write(ucb, UCB_IE_CLEAR, UCB_IE_TSPX);
247 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
248 ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_TSPX);
249 }
250
251 static inline void ucb1400_ts_irq_disable(struct ucb1400 *ucb)
252 {
253 ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
254 }
255
256 static void ucb1400_ts_evt_add(struct input_dev *idev, u16 pressure, u16 x, u16 y)
257 {
258 input_report_abs(idev, ABS_X, x);
259 input_report_abs(idev, ABS_Y, y);
260 input_report_abs(idev, ABS_PRESSURE, pressure);
261 input_sync(idev);
262 }
263
264 static void ucb1400_ts_event_release(struct input_dev *idev)
265 {
266 input_report_abs(idev, ABS_PRESSURE, 0);
267 input_sync(idev);
268 }
269
270 static void ucb1400_handle_pending_irq(struct ucb1400 *ucb)
271 {
272 unsigned int isr;
273
274 isr = ucb1400_reg_read(ucb, UCB_IE_STATUS);
275 ucb1400_reg_write(ucb, UCB_IE_CLEAR, isr);
276 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
277
278 if (isr & UCB_IE_TSPX)
279 ucb1400_ts_irq_disable(ucb);
280 else
281 printk(KERN_ERR "ucb1400: unexpected IE_STATUS = %#x\n", isr);
282
283 enable_irq(ucb->irq);
284 }
285
286 static int ucb1400_ts_thread(void *_ucb)
287 {
288 struct ucb1400 *ucb = _ucb;
289 struct task_struct *tsk = current;
290 int valid = 0;
291 struct sched_param param = { .sched_priority = 1 };
292
293 sched_setscheduler(tsk, SCHED_FIFO, &param);
294
295 set_freezable();
296 while (!kthread_should_stop()) {
297 unsigned int x, y, p;
298 long timeout;
299
300 ucb->ts_restart = 0;
301
302 if (ucb->irq_pending) {
303 ucb->irq_pending = 0;
304 ucb1400_handle_pending_irq(ucb);
305 }
306
307 ucb1400_adc_enable(ucb);
308 x = ucb1400_ts_read_xpos(ucb);
309 y = ucb1400_ts_read_ypos(ucb);
310 p = ucb1400_ts_read_pressure(ucb);
311 ucb1400_adc_disable(ucb);
312
313 /* Switch back to interrupt mode. */
314 ucb1400_ts_mode_int(ucb);
315
316 msleep(10);
317
318 if (ucb1400_ts_pen_down(ucb)) {
319 ucb1400_ts_irq_enable(ucb);
320
321 /*
322 * If we spat out a valid sample set last time,
323 * spit out a "pen off" sample here.
324 */
325 if (valid) {
326 ucb1400_ts_event_release(ucb->ts_idev);
327 valid = 0;
328 }
329
330 timeout = MAX_SCHEDULE_TIMEOUT;
331 } else {
332 valid = 1;
333 ucb1400_ts_evt_add(ucb->ts_idev, p, x, y);
334 timeout = msecs_to_jiffies(10);
335 }
336
337 wait_event_interruptible_timeout(ucb->ts_wait,
338 ucb->irq_pending || ucb->ts_restart || kthread_should_stop(),
339 timeout);
340 try_to_freeze();
341 }
342
343 /* Send the "pen off" if we are stopping with the pen still active */
344 if (valid)
345 ucb1400_ts_event_release(ucb->ts_idev);
346
347 ucb->ts_task = NULL;
348 return 0;
349 }
350
351 /*
352 * A restriction with interrupts exists when using the ucb1400, as
353 * the codec read/write routines may sleep while waiting for codec
354 * access completion and uses semaphores for access control to the
355 * AC97 bus. A complete codec read cycle could take anywhere from
356 * 60 to 100uSec so we *definitely* don't want to spin inside the
357 * interrupt handler waiting for codec access. So, we handle the
358 * interrupt by scheduling a RT kernel thread to run in process
359 * context instead of interrupt context.
360 */
361 static irqreturn_t ucb1400_hard_irq(int irqnr, void *devid)
362 {
363 struct ucb1400 *ucb = devid;
364
365 if (irqnr == ucb->irq) {
366 disable_irq(ucb->irq);
367 ucb->irq_pending = 1;
368 wake_up(&ucb->ts_wait);
369 return IRQ_HANDLED;
370 }
371 return IRQ_NONE;
372 }
373
374 static int ucb1400_ts_open(struct input_dev *idev)
375 {
376 struct ucb1400 *ucb = input_get_drvdata(idev);
377 int ret = 0;
378
379 BUG_ON(ucb->ts_task);
380
381 ucb->ts_task = kthread_run(ucb1400_ts_thread, ucb, "UCB1400_ts");
382 if (IS_ERR(ucb->ts_task)) {
383 ret = PTR_ERR(ucb->ts_task);
384 ucb->ts_task = NULL;
385 }
386
387 return ret;
388 }
389
390 static void ucb1400_ts_close(struct input_dev *idev)
391 {
392 struct ucb1400 *ucb = input_get_drvdata(idev);
393
394 if (ucb->ts_task)
395 kthread_stop(ucb->ts_task);
396
397 ucb1400_ts_irq_disable(ucb);
398 ucb1400_reg_write(ucb, UCB_TS_CR, 0);
399 }
400
401 #ifdef CONFIG_PM
402 static int ucb1400_ts_resume(struct device *dev)
403 {
404 struct ucb1400 *ucb = dev_get_drvdata(dev);
405
406 if (ucb->ts_task) {
407 /*
408 * Restart the TS thread to ensure the
409 * TS interrupt mode is set up again
410 * after sleep.
411 */
412 ucb->ts_restart = 1;
413 wake_up(&ucb->ts_wait);
414 }
415 return 0;
416 }
417 #else
418 #define ucb1400_ts_resume NULL
419 #endif
420
421 #ifndef NO_IRQ
422 #define NO_IRQ 0
423 #endif
424
425 /*
426 * Try to probe our interrupt, rather than relying on lots of
427 * hard-coded machine dependencies.
428 */
429 static int ucb1400_detect_irq(struct ucb1400 *ucb)
430 {
431 unsigned long mask, timeout;
432
433 mask = probe_irq_on();
434 if (!mask) {
435 probe_irq_off(mask);
436 return -EBUSY;
437 }
438
439 /* Enable the ADC interrupt. */
440 ucb1400_reg_write(ucb, UCB_IE_RIS, UCB_IE_ADC);
441 ucb1400_reg_write(ucb, UCB_IE_FAL, UCB_IE_ADC);
442 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
443 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
444
445 /* Cause an ADC interrupt. */
446 ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA);
447 ucb1400_reg_write(ucb, UCB_ADC_CR, UCB_ADC_ENA | UCB_ADC_START);
448
449 /* Wait for the conversion to complete. */
450 timeout = jiffies + HZ/2;
451 while (!(ucb1400_reg_read(ucb, UCB_ADC_DATA) & UCB_ADC_DAT_VALID)) {
452 cpu_relax();
453 if (time_after(jiffies, timeout)) {
454 printk(KERN_ERR "ucb1400: timed out in IRQ probe\n");
455 probe_irq_off(mask);
456 return -ENODEV;
457 }
458 }
459 ucb1400_reg_write(ucb, UCB_ADC_CR, 0);
460
461 /* Disable and clear interrupt. */
462 ucb1400_reg_write(ucb, UCB_IE_RIS, 0);
463 ucb1400_reg_write(ucb, UCB_IE_FAL, 0);
464 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0xffff);
465 ucb1400_reg_write(ucb, UCB_IE_CLEAR, 0);
466
467 /* Read triggered interrupt. */
468 ucb->irq = probe_irq_off(mask);
469 if (ucb->irq < 0 || ucb->irq == NO_IRQ)
470 return -ENODEV;
471
472 return 0;
473 }
474
475 static int ucb1400_ts_probe(struct device *dev)
476 {
477 struct ucb1400 *ucb;
478 struct input_dev *idev;
479 int error, id, x_res, y_res;
480
481 ucb = kzalloc(sizeof(struct ucb1400), GFP_KERNEL);
482 idev = input_allocate_device();
483 if (!ucb || !idev) {
484 error = -ENOMEM;
485 goto err_free_devs;
486 }
487
488 ucb->ts_idev = idev;
489 ucb->adcsync = adcsync;
490 ucb->ac97 = to_ac97_t(dev);
491 init_waitqueue_head(&ucb->ts_wait);
492
493 id = ucb1400_reg_read(ucb, UCB_ID);
494 if (id != UCB_ID_1400) {
495 error = -ENODEV;
496 goto err_free_devs;
497 }
498
499 error = ucb1400_detect_irq(ucb);
500 if (error) {
501 printk(KERN_ERR "UCB1400: IRQ probe failed\n");
502 goto err_free_devs;
503 }
504
505 error = request_irq(ucb->irq, ucb1400_hard_irq, IRQF_TRIGGER_RISING,
506 "UCB1400", ucb);
507 if (error) {
508 printk(KERN_ERR "ucb1400: unable to grab irq%d: %d\n",
509 ucb->irq, error);
510 goto err_free_devs;
511 }
512 printk(KERN_DEBUG "UCB1400: found IRQ %d\n", ucb->irq);
513
514 input_set_drvdata(idev, ucb);
515
516 idev->dev.parent = dev;
517 idev->name = "UCB1400 touchscreen interface";
518 idev->id.vendor = ucb1400_reg_read(ucb, AC97_VENDOR_ID1);
519 idev->id.product = id;
520 idev->open = ucb1400_ts_open;
521 idev->close = ucb1400_ts_close;
522 idev->evbit[0] = BIT(EV_ABS);
523
524 ucb1400_adc_enable(ucb);
525 x_res = ucb1400_ts_read_xres(ucb);
526 y_res = ucb1400_ts_read_yres(ucb);
527 ucb1400_adc_disable(ucb);
528 printk(KERN_DEBUG "UCB1400: x/y = %d/%d\n", x_res, y_res);
529
530 input_set_abs_params(idev, ABS_X, 0, x_res, 0, 0);
531 input_set_abs_params(idev, ABS_Y, 0, y_res, 0, 0);
532 input_set_abs_params(idev, ABS_PRESSURE, 0, 0, 0, 0);
533
534 error = input_register_device(idev);
535 if (error)
536 goto err_free_irq;
537
538 dev_set_drvdata(dev, ucb);
539 return 0;
540
541 err_free_irq:
542 free_irq(ucb->irq, ucb);
543 err_free_devs:
544 input_free_device(idev);
545 kfree(ucb);
546 return error;
547 }
548
549 static int ucb1400_ts_remove(struct device *dev)
550 {
551 struct ucb1400 *ucb = dev_get_drvdata(dev);
552
553 free_irq(ucb->irq, ucb);
554 input_unregister_device(ucb->ts_idev);
555 dev_set_drvdata(dev, NULL);
556 kfree(ucb);
557 return 0;
558 }
559
560 static struct device_driver ucb1400_ts_driver = {
561 .name = "ucb1400_ts",
562 .owner = THIS_MODULE,
563 .bus = &ac97_bus_type,
564 .probe = ucb1400_ts_probe,
565 .remove = ucb1400_ts_remove,
566 .resume = ucb1400_ts_resume,
567 };
568
569 static int __init ucb1400_ts_init(void)
570 {
571 return driver_register(&ucb1400_ts_driver);
572 }
573
574 static void __exit ucb1400_ts_exit(void)
575 {
576 driver_unregister(&ucb1400_ts_driver);
577 }
578
579 module_param(adcsync, bool, 0444);
580 MODULE_PARM_DESC(adcsync, "Synchronize touch readings with ADCSYNC pin.");
581
582 module_param(ts_delay, int, 0444);
583 MODULE_PARM_DESC(ts_delay, "Delay between panel setup and position read. Default = 55us.");
584
585 module_param(ts_delay_pressure, int, 0444);
586 MODULE_PARM_DESC(ts_delay_pressure,
587 "delay between panel setup and pressure read. Default = 0us.");
588
589 module_init(ucb1400_ts_init);
590 module_exit(ucb1400_ts_exit);
591
592 MODULE_DESCRIPTION("Philips UCB1400 touchscreen driver");
593 MODULE_LICENSE("GPL");