]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blob - drivers/iommu/amd_iommu.c
projects / mirror_ubuntu-bionic-kernel.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branches 'arm/exynos', 'arm/renesas', 'arm/rockchip', 'arm/omap', 'arm/mediatek...
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define AMD_IOMMU_MAPPING_ERROR 0
58
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
60
61 #define LOOP_TIMEOUT 100000
62
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
85
86 /* List of all available dev_data structures */
87 static LIST_HEAD(dev_data_list);
88 static DEFINE_SPINLOCK(dev_data_list_lock);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207 unsigned long flags;
208
209 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
210 if (!dev_data)
211 return NULL;
212
213 dev_data->devid = devid;
214
215 spin_lock_irqsave(&dev_data_list_lock, flags);
216 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
217 spin_unlock_irqrestore(&dev_data_list_lock, flags);
218
219 ratelimit_default_init(&dev_data->rs);
220
221 return dev_data;
222 }
223
224 static struct iommu_dev_data *search_dev_data(u16 devid)
225 {
226 struct iommu_dev_data *dev_data;
227 unsigned long flags;
228
229 spin_lock_irqsave(&dev_data_list_lock, flags);
230 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
231 if (dev_data->devid == devid)
232 goto out_unlock;
233 }
234
235 dev_data = NULL;
236
237 out_unlock:
238 spin_unlock_irqrestore(&dev_data_list_lock, flags);
239
240 return dev_data;
241 }
242
243 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
244 {
245 *(u16 *)data = alias;
246 return 0;
247 }
248
249 static u16 get_alias(struct device *dev)
250 {
251 struct pci_dev *pdev = to_pci_dev(dev);
252 u16 devid, ivrs_alias, pci_alias;
253
254 /* The callers make sure that get_device_id() does not fail here */
255 devid = get_device_id(dev);
256 ivrs_alias = amd_iommu_alias_table[devid];
257 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
258
259 if (ivrs_alias == pci_alias)
260 return ivrs_alias;
261
262 /*
263 * DMA alias showdown
264 *
265 * The IVRS is fairly reliable in telling us about aliases, but it
266 * can't know about every screwy device. If we don't have an IVRS
267 * reported alias, use the PCI reported alias. In that case we may
268 * still need to initialize the rlookup and dev_table entries if the
269 * alias is to a non-existent device.
270 */
271 if (ivrs_alias == devid) {
272 if (!amd_iommu_rlookup_table[pci_alias]) {
273 amd_iommu_rlookup_table[pci_alias] =
274 amd_iommu_rlookup_table[devid];
275 memcpy(amd_iommu_dev_table[pci_alias].data,
276 amd_iommu_dev_table[devid].data,
277 sizeof(amd_iommu_dev_table[pci_alias].data));
278 }
279
280 return pci_alias;
281 }
282
283 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
284 "for device %s[%04x:%04x], kernel reported alias "
285 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
286 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
287 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
288 PCI_FUNC(pci_alias));
289
290 /*
291 * If we don't have a PCI DMA alias and the IVRS alias is on the same
292 * bus, then the IVRS table may know about a quirk that we don't.
293 */
294 if (pci_alias == devid &&
295 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
296 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
297 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
298 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
299 dev_name(dev));
300 }
301
302 return ivrs_alias;
303 }
304
305 static struct iommu_dev_data *find_dev_data(u16 devid)
306 {
307 struct iommu_dev_data *dev_data;
308 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
309
310 dev_data = search_dev_data(devid);
311
312 if (dev_data == NULL) {
313 dev_data = alloc_dev_data(devid);
314
315 if (translation_pre_enabled(iommu))
316 dev_data->defer_attach = true;
317 }
318
319 return dev_data;
320 }
321
322 struct iommu_dev_data *get_dev_data(struct device *dev)
323 {
324 return dev->archdata.iommu;
325 }
326 EXPORT_SYMBOL(get_dev_data);
327
328 /*
329 * Find or create an IOMMU group for a acpihid device.
330 */
331 static struct iommu_group *acpihid_device_group(struct device *dev)
332 {
333 struct acpihid_map_entry *p, *entry = NULL;
334 int devid;
335
336 devid = get_acpihid_device_id(dev, &entry);
337 if (devid < 0)
338 return ERR_PTR(devid);
339
340 list_for_each_entry(p, &acpihid_map, list) {
341 if ((devid == p->devid) && p->group)
342 entry->group = p->group;
343 }
344
345 if (!entry->group)
346 entry->group = generic_device_group(dev);
347 else
348 iommu_group_ref_get(entry->group);
349
350 return entry->group;
351 }
352
353 static bool pci_iommuv2_capable(struct pci_dev *pdev)
354 {
355 static const int caps[] = {
356 PCI_EXT_CAP_ID_ATS,
357 PCI_EXT_CAP_ID_PRI,
358 PCI_EXT_CAP_ID_PASID,
359 };
360 int i, pos;
361
362 for (i = 0; i < 3; ++i) {
363 pos = pci_find_ext_capability(pdev, caps[i]);
364 if (pos == 0)
365 return false;
366 }
367
368 return true;
369 }
370
371 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
372 {
373 struct iommu_dev_data *dev_data;
374
375 dev_data = get_dev_data(&pdev->dev);
376
377 return dev_data->errata & (1 << erratum) ? true : false;
378 }
379
380 /*
381 * This function checks if the driver got a valid device from the caller to
382 * avoid dereferencing invalid pointers.
383 */
384 static bool check_device(struct device *dev)
385 {
386 int devid;
387
388 if (!dev || !dev->dma_mask)
389 return false;
390
391 devid = get_device_id(dev);
392 if (devid < 0)
393 return false;
394
395 /* Out of our scope? */
396 if (devid > amd_iommu_last_bdf)
397 return false;
398
399 if (amd_iommu_rlookup_table[devid] == NULL)
400 return false;
401
402 return true;
403 }
404
405 static void init_iommu_group(struct device *dev)
406 {
407 struct iommu_group *group;
408
409 group = iommu_group_get_for_dev(dev);
410 if (IS_ERR(group))
411 return;
412
413 iommu_group_put(group);
414 }
415
416 static int iommu_init_device(struct device *dev)
417 {
418 struct iommu_dev_data *dev_data;
419 struct amd_iommu *iommu;
420 int devid;
421
422 if (dev->archdata.iommu)
423 return 0;
424
425 devid = get_device_id(dev);
426 if (devid < 0)
427 return devid;
428
429 iommu = amd_iommu_rlookup_table[devid];
430
431 dev_data = find_dev_data(devid);
432 if (!dev_data)
433 return -ENOMEM;
434
435 dev_data->alias = get_alias(dev);
436
437 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
438 struct amd_iommu *iommu;
439
440 iommu = amd_iommu_rlookup_table[dev_data->devid];
441 dev_data->iommu_v2 = iommu->is_iommu_v2;
442 }
443
444 dev->archdata.iommu = dev_data;
445
446 iommu_device_link(&iommu->iommu, dev);
447
448 return 0;
449 }
450
451 static void iommu_ignore_device(struct device *dev)
452 {
453 u16 alias;
454 int devid;
455
456 devid = get_device_id(dev);
457 if (devid < 0)
458 return;
459
460 alias = get_alias(dev);
461
462 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
463 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
464
465 amd_iommu_rlookup_table[devid] = NULL;
466 amd_iommu_rlookup_table[alias] = NULL;
467 }
468
469 static void iommu_uninit_device(struct device *dev)
470 {
471 struct iommu_dev_data *dev_data;
472 struct amd_iommu *iommu;
473 int devid;
474
475 devid = get_device_id(dev);
476 if (devid < 0)
477 return;
478
479 iommu = amd_iommu_rlookup_table[devid];
480
481 dev_data = search_dev_data(devid);
482 if (!dev_data)
483 return;
484
485 if (dev_data->domain)
486 detach_device(dev);
487
488 iommu_device_unlink(&iommu->iommu, dev);
489
490 iommu_group_remove_device(dev);
491
492 /* Remove dma-ops */
493 dev->dma_ops = NULL;
494
495 /*
496 * We keep dev_data around for unplugged devices and reuse it when the
497 * device is re-plugged - not doing so would introduce a ton of races.
498 */
499 }
500
501 /****************************************************************************
502 *
503 * Interrupt handling functions
504 *
505 ****************************************************************************/
506
507 static void dump_dte_entry(u16 devid)
508 {
509 int i;
510
511 for (i = 0; i < 4; ++i)
512 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
513 amd_iommu_dev_table[devid].data[i]);
514 }
515
516 static void dump_command(unsigned long phys_addr)
517 {
518 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
519 int i;
520
521 for (i = 0; i < 4; ++i)
522 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
523 }
524
525 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
526 u64 address, int flags)
527 {
528 struct iommu_dev_data *dev_data = NULL;
529 struct pci_dev *pdev;
530
531 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
532 if (pdev)
533 dev_data = get_dev_data(&pdev->dev);
534
535 if (dev_data && __ratelimit(&dev_data->rs)) {
536 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
537 domain_id, address, flags);
538 } else if (printk_ratelimit()) {
539 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
540 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
541 domain_id, address, flags);
542 }
543
544 if (pdev)
545 pci_dev_put(pdev);
546 }
547
548 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 {
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, domid, address, flags);
574 return;
575 } else {
576 printk(KERN_ERR "AMD-Vi: Event logged [");
577 }
578
579 switch (type) {
580 case EVENT_TYPE_ILL_DEV:
581 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
582 "address=0x%016llx flags=0x%04x]\n",
583 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
584 address, flags);
585 dump_dte_entry(devid);
586 break;
587 case EVENT_TYPE_DEV_TAB_ERR:
588 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
591 address, flags);
592 break;
593 case EVENT_TYPE_PAGE_TAB_ERR:
594 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
597 domid, address, flags);
598 break;
599 case EVENT_TYPE_ILL_CMD:
600 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
601 dump_command(address);
602 break;
603 case EVENT_TYPE_CMD_HARD_ERR:
604 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
605 "flags=0x%04x]\n", address, flags);
606 break;
607 case EVENT_TYPE_IOTLB_INV_TO:
608 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
609 "address=0x%016llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 address);
612 break;
613 case EVENT_TYPE_INV_DEV_REQ:
614 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 address, flags);
618 break;
619 default:
620 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
621 }
622
623 memset(__evt, 0, 4 * sizeof(u32));
624 }
625
626 static void iommu_poll_events(struct amd_iommu *iommu)
627 {
628 u32 head, tail;
629
630 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
631 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
632
633 while (head != tail) {
634 iommu_print_event(iommu, iommu->evt_buf + head);
635 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
636 }
637
638 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 }
640
641 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
642 {
643 struct amd_iommu_fault fault;
644
645 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
646 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
647 return;
648 }
649
650 fault.address = raw[1];
651 fault.pasid = PPR_PASID(raw[0]);
652 fault.device_id = PPR_DEVID(raw[0]);
653 fault.tag = PPR_TAG(raw[0]);
654 fault.flags = PPR_FLAGS(raw[0]);
655
656 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
657 }
658
659 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
660 {
661 u32 head, tail;
662
663 if (iommu->ppr_log == NULL)
664 return;
665
666 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
668
669 while (head != tail) {
670 volatile u64 *raw;
671 u64 entry[2];
672 int i;
673
674 raw = (u64 *)(iommu->ppr_log + head);
675
676 /*
677 * Hardware bug: Interrupt may arrive before the entry is
678 * written to memory. If this happens we need to wait for the
679 * entry to arrive.
680 */
681 for (i = 0; i < LOOP_TIMEOUT; ++i) {
682 if (PPR_REQ_TYPE(raw[0]) != 0)
683 break;
684 udelay(1);
685 }
686
687 /* Avoid memcpy function-call overhead */
688 entry[0] = raw[0];
689 entry[1] = raw[1];
690
691 /*
692 * To detect the hardware bug we need to clear the entry
693 * back to zero.
694 */
695 raw[0] = raw[1] = 0UL;
696
697 /* Update head pointer of hardware ring-buffer */
698 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
699 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700
701 /* Handle PPR entry */
702 iommu_handle_ppr_entry(iommu, entry);
703
704 /* Refresh ring-buffer information */
705 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
707 }
708 }
709
710 #ifdef CONFIG_IRQ_REMAP
711 static int (*iommu_ga_log_notifier)(u32);
712
713 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
714 {
715 iommu_ga_log_notifier = notifier;
716
717 return 0;
718 }
719 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
720
721 static void iommu_poll_ga_log(struct amd_iommu *iommu)
722 {
723 u32 head, tail, cnt = 0;
724
725 if (iommu->ga_log == NULL)
726 return;
727
728 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
729 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
730
731 while (head != tail) {
732 volatile u64 *raw;
733 u64 log_entry;
734
735 raw = (u64 *)(iommu->ga_log + head);
736 cnt++;
737
738 /* Avoid memcpy function-call overhead */
739 log_entry = *raw;
740
741 /* Update head pointer of hardware ring-buffer */
742 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
743 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
744
745 /* Handle GA entry */
746 switch (GA_REQ_TYPE(log_entry)) {
747 case GA_GUEST_NR:
748 if (!iommu_ga_log_notifier)
749 break;
750
751 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
752 __func__, GA_DEVID(log_entry),
753 GA_TAG(log_entry));
754
755 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
756 pr_err("AMD-Vi: GA log notifier failed.\n");
757 break;
758 default:
759 break;
760 }
761 }
762 }
763 #endif /* CONFIG_IRQ_REMAP */
764
765 #define AMD_IOMMU_INT_MASK \
766 (MMIO_STATUS_EVT_INT_MASK | \
767 MMIO_STATUS_PPR_INT_MASK | \
768 MMIO_STATUS_GALOG_INT_MASK)
769
770 irqreturn_t amd_iommu_int_thread(int irq, void *data)
771 {
772 struct amd_iommu *iommu = (struct amd_iommu *) data;
773 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
774
775 while (status & AMD_IOMMU_INT_MASK) {
776 /* Enable EVT and PPR and GA interrupts again */
777 writel(AMD_IOMMU_INT_MASK,
778 iommu->mmio_base + MMIO_STATUS_OFFSET);
779
780 if (status & MMIO_STATUS_EVT_INT_MASK) {
781 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
782 iommu_poll_events(iommu);
783 }
784
785 if (status & MMIO_STATUS_PPR_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
787 iommu_poll_ppr_log(iommu);
788 }
789
790 #ifdef CONFIG_IRQ_REMAP
791 if (status & MMIO_STATUS_GALOG_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
793 iommu_poll_ga_log(iommu);
794 }
795 #endif
796
797 /*
798 * Hardware bug: ERBT1312
799 * When re-enabling interrupt (by writing 1
800 * to clear the bit), the hardware might also try to set
801 * the interrupt bit in the event status register.
802 * In this scenario, the bit will be set, and disable
803 * subsequent interrupts.
804 *
805 * Workaround: The IOMMU driver should read back the
806 * status register and check if the interrupt bits are cleared.
807 * If not, driver will need to go through the interrupt handler
808 * again and re-clear the bits
809 */
810 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
811 }
812 return IRQ_HANDLED;
813 }
814
815 irqreturn_t amd_iommu_int_handler(int irq, void *data)
816 {
817 return IRQ_WAKE_THREAD;
818 }
819
820 /****************************************************************************
821 *
822 * IOMMU command queuing functions
823 *
824 ****************************************************************************/
825
826 static int wait_on_sem(volatile u64 *sem)
827 {
828 int i = 0;
829
830 while (*sem == 0 && i < LOOP_TIMEOUT) {
831 udelay(1);
832 i += 1;
833 }
834
835 if (i == LOOP_TIMEOUT) {
836 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
837 return -EIO;
838 }
839
840 return 0;
841 }
842
843 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
844 struct iommu_cmd *cmd)
845 {
846 u8 *target;
847
848 target = iommu->cmd_buf + iommu->cmd_buf_tail;
849
850 iommu->cmd_buf_tail += sizeof(*cmd);
851 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
852
853 /* Copy command to buffer */
854 memcpy(target, cmd, sizeof(*cmd));
855
856 /* Tell the IOMMU about it */
857 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
858 }
859
860 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
861 {
862 WARN_ON(address & 0x7ULL);
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
866 cmd->data[1] = upper_32_bits(__pa(address));
867 cmd->data[2] = 1;
868 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
869 }
870
871 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
872 {
873 memset(cmd, 0, sizeof(*cmd));
874 cmd->data[0] = devid;
875 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
876 }
877
878 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
879 size_t size, u16 domid, int pde)
880 {
881 u64 pages;
882 bool s;
883
884 pages = iommu_num_pages(address, size, PAGE_SIZE);
885 s = false;
886
887 if (pages > 1) {
888 /*
889 * If we have to flush more than one page, flush all
890 * TLB entries for this domain
891 */
892 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
893 s = true;
894 }
895
896 address &= PAGE_MASK;
897
898 memset(cmd, 0, sizeof(*cmd));
899 cmd->data[1] |= domid;
900 cmd->data[2] = lower_32_bits(address);
901 cmd->data[3] = upper_32_bits(address);
902 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
903 if (s) /* size bit - we flush more than one 4kb page */
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
905 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
907 }
908
909 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
910 u64 address, size_t size)
911 {
912 u64 pages;
913 bool s;
914
915 pages = iommu_num_pages(address, size, PAGE_SIZE);
916 s = false;
917
918 if (pages > 1) {
919 /*
920 * If we have to flush more than one page, flush all
921 * TLB entries for this domain
922 */
923 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
924 s = true;
925 }
926
927 address &= PAGE_MASK;
928
929 memset(cmd, 0, sizeof(*cmd));
930 cmd->data[0] = devid;
931 cmd->data[0] |= (qdep & 0xff) << 24;
932 cmd->data[1] = devid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
936 if (s)
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 }
939
940 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
941 u64 address, bool size)
942 {
943 memset(cmd, 0, sizeof(*cmd));
944
945 address &= ~(0xfffULL);
946
947 cmd->data[0] = pasid;
948 cmd->data[1] = domid;
949 cmd->data[2] = lower_32_bits(address);
950 cmd->data[3] = upper_32_bits(address);
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
953 if (size)
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
956 }
957
958 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
959 int qdep, u64 address, bool size)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962
963 address &= ~(0xfffULL);
964
965 cmd->data[0] = devid;
966 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
967 cmd->data[0] |= (qdep & 0xff) << 24;
968 cmd->data[1] = devid;
969 cmd->data[1] |= (pasid & 0xff) << 16;
970 cmd->data[2] = lower_32_bits(address);
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 cmd->data[3] = upper_32_bits(address);
973 if (size)
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
975 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
976 }
977
978 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
979 int status, int tag, bool gn)
980 {
981 memset(cmd, 0, sizeof(*cmd));
982
983 cmd->data[0] = devid;
984 if (gn) {
985 cmd->data[1] = pasid;
986 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
987 }
988 cmd->data[3] = tag & 0x1ff;
989 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
990
991 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
992 }
993
994 static void build_inv_all(struct iommu_cmd *cmd)
995 {
996 memset(cmd, 0, sizeof(*cmd));
997 CMD_SET_TYPE(cmd, CMD_INV_ALL);
998 }
999
1000 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1001 {
1002 memset(cmd, 0, sizeof(*cmd));
1003 cmd->data[0] = devid;
1004 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1005 }
1006
1007 /*
1008 * Writes the command to the IOMMUs command buffer and informs the
1009 * hardware about the new command.
1010 */
1011 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1012 struct iommu_cmd *cmd,
1013 bool sync)
1014 {
1015 unsigned int count = 0;
1016 u32 left, next_tail;
1017
1018 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1019 again:
1020 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1021
1022 if (left <= 0x20) {
1023 /* Skip udelay() the first time around */
1024 if (count++) {
1025 if (count == LOOP_TIMEOUT) {
1026 pr_err("AMD-Vi: Command buffer timeout\n");
1027 return -EIO;
1028 }
1029
1030 udelay(1);
1031 }
1032
1033 /* Update head and recheck remaining space */
1034 iommu->cmd_buf_head = readl(iommu->mmio_base +
1035 MMIO_CMD_HEAD_OFFSET);
1036
1037 goto again;
1038 }
1039
1040 copy_cmd_to_buffer(iommu, cmd);
1041
1042 /* Do we need to make sure all commands are processed? */
1043 iommu->need_sync = sync;
1044
1045 return 0;
1046 }
1047
1048 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1049 struct iommu_cmd *cmd,
1050 bool sync)
1051 {
1052 unsigned long flags;
1053 int ret;
1054
1055 spin_lock_irqsave(&iommu->lock, flags);
1056 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1057 spin_unlock_irqrestore(&iommu->lock, flags);
1058
1059 return ret;
1060 }
1061
1062 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1063 {
1064 return iommu_queue_command_sync(iommu, cmd, true);
1065 }
1066
1067 /*
1068 * This function queues a completion wait command into the command
1069 * buffer of an IOMMU
1070 */
1071 static int iommu_completion_wait(struct amd_iommu *iommu)
1072 {
1073 struct iommu_cmd cmd;
1074 unsigned long flags;
1075 int ret;
1076
1077 if (!iommu->need_sync)
1078 return 0;
1079
1080
1081 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1082
1083 spin_lock_irqsave(&iommu->lock, flags);
1084
1085 iommu->cmd_sem = 0;
1086
1087 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1088 if (ret)
1089 goto out_unlock;
1090
1091 ret = wait_on_sem(&iommu->cmd_sem);
1092
1093 out_unlock:
1094 spin_unlock_irqrestore(&iommu->lock, flags);
1095
1096 return ret;
1097 }
1098
1099 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1100 {
1101 struct iommu_cmd cmd;
1102
1103 build_inv_dte(&cmd, devid);
1104
1105 return iommu_queue_command(iommu, &cmd);
1106 }
1107
1108 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1109 {
1110 u32 devid;
1111
1112 for (devid = 0; devid <= 0xffff; ++devid)
1113 iommu_flush_dte(iommu, devid);
1114
1115 iommu_completion_wait(iommu);
1116 }
1117
1118 /*
1119 * This function uses heavy locking and may disable irqs for some time. But
1120 * this is no issue because it is only called during resume.
1121 */
1122 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1123 {
1124 u32 dom_id;
1125
1126 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1127 struct iommu_cmd cmd;
1128 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1129 dom_id, 1);
1130 iommu_queue_command(iommu, &cmd);
1131 }
1132
1133 iommu_completion_wait(iommu);
1134 }
1135
1136 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1137 {
1138 struct iommu_cmd cmd;
1139
1140 build_inv_all(&cmd);
1141
1142 iommu_queue_command(iommu, &cmd);
1143 iommu_completion_wait(iommu);
1144 }
1145
1146 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1147 {
1148 struct iommu_cmd cmd;
1149
1150 build_inv_irt(&cmd, devid);
1151
1152 iommu_queue_command(iommu, &cmd);
1153 }
1154
1155 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1156 {
1157 u32 devid;
1158
1159 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1160 iommu_flush_irt(iommu, devid);
1161
1162 iommu_completion_wait(iommu);
1163 }
1164
1165 void iommu_flush_all_caches(struct amd_iommu *iommu)
1166 {
1167 if (iommu_feature(iommu, FEATURE_IA)) {
1168 amd_iommu_flush_all(iommu);
1169 } else {
1170 amd_iommu_flush_dte_all(iommu);
1171 amd_iommu_flush_irt_all(iommu);
1172 amd_iommu_flush_tlb_all(iommu);
1173 }
1174 }
1175
1176 /*
1177 * Command send function for flushing on-device TLB
1178 */
1179 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1180 u64 address, size_t size)
1181 {
1182 struct amd_iommu *iommu;
1183 struct iommu_cmd cmd;
1184 int qdep;
1185
1186 qdep = dev_data->ats.qdep;
1187 iommu = amd_iommu_rlookup_table[dev_data->devid];
1188
1189 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1190
1191 return iommu_queue_command(iommu, &cmd);
1192 }
1193
1194 /*
1195 * Command send function for invalidating a device table entry
1196 */
1197 static int device_flush_dte(struct iommu_dev_data *dev_data)
1198 {
1199 struct amd_iommu *iommu;
1200 u16 alias;
1201 int ret;
1202
1203 iommu = amd_iommu_rlookup_table[dev_data->devid];
1204 alias = dev_data->alias;
1205
1206 ret = iommu_flush_dte(iommu, dev_data->devid);
1207 if (!ret && alias != dev_data->devid)
1208 ret = iommu_flush_dte(iommu, alias);
1209 if (ret)
1210 return ret;
1211
1212 if (dev_data->ats.enabled)
1213 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1214
1215 return ret;
1216 }
1217
1218 /*
1219 * TLB invalidation function which is called from the mapping functions.
1220 * It invalidates a single PTE if the range to flush is within a single
1221 * page. Otherwise it flushes the whole TLB of the IOMMU.
1222 */
1223 static void __domain_flush_pages(struct protection_domain *domain,
1224 u64 address, size_t size, int pde)
1225 {
1226 struct iommu_dev_data *dev_data;
1227 struct iommu_cmd cmd;
1228 int ret = 0, i;
1229
1230 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1231
1232 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1233 if (!domain->dev_iommu[i])
1234 continue;
1235
1236 /*
1237 * Devices of this domain are behind this IOMMU
1238 * We need a TLB flush
1239 */
1240 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1241 }
1242
1243 list_for_each_entry(dev_data, &domain->dev_list, list) {
1244
1245 if (!dev_data->ats.enabled)
1246 continue;
1247
1248 ret |= device_flush_iotlb(dev_data, address, size);
1249 }
1250
1251 WARN_ON(ret);
1252 }
1253
1254 static void domain_flush_pages(struct protection_domain *domain,
1255 u64 address, size_t size)
1256 {
1257 __domain_flush_pages(domain, address, size, 0);
1258 }
1259
1260 /* Flush the whole IO/TLB for a given protection domain */
1261 static void domain_flush_tlb(struct protection_domain *domain)
1262 {
1263 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1264 }
1265
1266 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1267 static void domain_flush_tlb_pde(struct protection_domain *domain)
1268 {
1269 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1270 }
1271
1272 static void domain_flush_complete(struct protection_domain *domain)
1273 {
1274 int i;
1275
1276 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1277 if (domain && !domain->dev_iommu[i])
1278 continue;
1279
1280 /*
1281 * Devices of this domain are behind this IOMMU
1282 * We need to wait for completion of all commands.
1283 */
1284 iommu_completion_wait(amd_iommus[i]);
1285 }
1286 }
1287
1288
1289 /*
1290 * This function flushes the DTEs for all devices in domain
1291 */
1292 static void domain_flush_devices(struct protection_domain *domain)
1293 {
1294 struct iommu_dev_data *dev_data;
1295
1296 list_for_each_entry(dev_data, &domain->dev_list, list)
1297 device_flush_dte(dev_data);
1298 }
1299
1300 /****************************************************************************
1301 *
1302 * The functions below are used the create the page table mappings for
1303 * unity mapped regions.
1304 *
1305 ****************************************************************************/
1306
1307 /*
1308 * This function is used to add another level to an IO page table. Adding
1309 * another level increases the size of the address space by 9 bits to a size up
1310 * to 64 bits.
1311 */
1312 static bool increase_address_space(struct protection_domain *domain,
1313 gfp_t gfp)
1314 {
1315 u64 *pte;
1316
1317 if (domain->mode == PAGE_MODE_6_LEVEL)
1318 /* address space already 64 bit large */
1319 return false;
1320
1321 pte = (void *)get_zeroed_page(gfp);
1322 if (!pte)
1323 return false;
1324
1325 *pte = PM_LEVEL_PDE(domain->mode,
1326 virt_to_phys(domain->pt_root));
1327 domain->pt_root = pte;
1328 domain->mode += 1;
1329 domain->updated = true;
1330
1331 return true;
1332 }
1333
1334 static u64 *alloc_pte(struct protection_domain *domain,
1335 unsigned long address,
1336 unsigned long page_size,
1337 u64 **pte_page,
1338 gfp_t gfp)
1339 {
1340 int level, end_lvl;
1341 u64 *pte, *page;
1342
1343 BUG_ON(!is_power_of_2(page_size));
1344
1345 while (address > PM_LEVEL_SIZE(domain->mode))
1346 increase_address_space(domain, gfp);
1347
1348 level = domain->mode - 1;
1349 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1350 address = PAGE_SIZE_ALIGN(address, page_size);
1351 end_lvl = PAGE_SIZE_LEVEL(page_size);
1352
1353 while (level > end_lvl) {
1354 u64 __pte, __npte;
1355
1356 __pte = *pte;
1357
1358 if (!IOMMU_PTE_PRESENT(__pte)) {
1359 page = (u64 *)get_zeroed_page(gfp);
1360 if (!page)
1361 return NULL;
1362
1363 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1364
1365 /* pte could have been changed somewhere. */
1366 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1367 free_page((unsigned long)page);
1368 continue;
1369 }
1370 }
1371
1372 /* No level skipping support yet */
1373 if (PM_PTE_LEVEL(*pte) != level)
1374 return NULL;
1375
1376 level -= 1;
1377
1378 pte = IOMMU_PTE_PAGE(*pte);
1379
1380 if (pte_page && level == end_lvl)
1381 *pte_page = pte;
1382
1383 pte = &pte[PM_LEVEL_INDEX(level, address)];
1384 }
1385
1386 return pte;
1387 }
1388
1389 /*
1390 * This function checks if there is a PTE for a given dma address. If
1391 * there is one, it returns the pointer to it.
1392 */
1393 static u64 *fetch_pte(struct protection_domain *domain,
1394 unsigned long address,
1395 unsigned long *page_size)
1396 {
1397 int level;
1398 u64 *pte;
1399
1400 if (address > PM_LEVEL_SIZE(domain->mode))
1401 return NULL;
1402
1403 level = domain->mode - 1;
1404 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1405 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1406
1407 while (level > 0) {
1408
1409 /* Not Present */
1410 if (!IOMMU_PTE_PRESENT(*pte))
1411 return NULL;
1412
1413 /* Large PTE */
1414 if (PM_PTE_LEVEL(*pte) == 7 ||
1415 PM_PTE_LEVEL(*pte) == 0)
1416 break;
1417
1418 /* No level skipping support yet */
1419 if (PM_PTE_LEVEL(*pte) != level)
1420 return NULL;
1421
1422 level -= 1;
1423
1424 /* Walk to the next level */
1425 pte = IOMMU_PTE_PAGE(*pte);
1426 pte = &pte[PM_LEVEL_INDEX(level, address)];
1427 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1428 }
1429
1430 if (PM_PTE_LEVEL(*pte) == 0x07) {
1431 unsigned long pte_mask;
1432
1433 /*
1434 * If we have a series of large PTEs, make
1435 * sure to return a pointer to the first one.
1436 */
1437 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1438 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1439 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1440 }
1441
1442 return pte;
1443 }
1444
1445 /*
1446 * Generic mapping functions. It maps a physical address into a DMA
1447 * address space. It allocates the page table pages if necessary.
1448 * In the future it can be extended to a generic mapping function
1449 * supporting all features of AMD IOMMU page tables like level skipping
1450 * and full 64 bit address spaces.
1451 */
1452 static int iommu_map_page(struct protection_domain *dom,
1453 unsigned long bus_addr,
1454 unsigned long phys_addr,
1455 unsigned long page_size,
1456 int prot,
1457 gfp_t gfp)
1458 {
1459 u64 __pte, *pte;
1460 int i, count;
1461
1462 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1463 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1464
1465 if (!(prot & IOMMU_PROT_MASK))
1466 return -EINVAL;
1467
1468 count = PAGE_SIZE_PTE_COUNT(page_size);
1469 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1470
1471 if (!pte)
1472 return -ENOMEM;
1473
1474 for (i = 0; i < count; ++i)
1475 if (IOMMU_PTE_PRESENT(pte[i]))
1476 return -EBUSY;
1477
1478 if (count > 1) {
1479 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1480 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1481 } else
1482 __pte = phys_addr | IOMMU_PTE_PR | IOMMU_PTE_FC;
1483
1484 if (prot & IOMMU_PROT_IR)
1485 __pte |= IOMMU_PTE_IR;
1486 if (prot & IOMMU_PROT_IW)
1487 __pte |= IOMMU_PTE_IW;
1488
1489 for (i = 0; i < count; ++i)
1490 pte[i] = __pte;
1491
1492 update_domain(dom);
1493
1494 return 0;
1495 }
1496
1497 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1498 unsigned long bus_addr,
1499 unsigned long page_size)
1500 {
1501 unsigned long long unmapped;
1502 unsigned long unmap_size;
1503 u64 *pte;
1504
1505 BUG_ON(!is_power_of_2(page_size));
1506
1507 unmapped = 0;
1508
1509 while (unmapped < page_size) {
1510
1511 pte = fetch_pte(dom, bus_addr, &unmap_size);
1512
1513 if (pte) {
1514 int i, count;
1515
1516 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1517 for (i = 0; i < count; i++)
1518 pte[i] = 0ULL;
1519 }
1520
1521 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1522 unmapped += unmap_size;
1523 }
1524
1525 BUG_ON(unmapped && !is_power_of_2(unmapped));
1526
1527 return unmapped;
1528 }
1529
1530 /****************************************************************************
1531 *
1532 * The next functions belong to the address allocator for the dma_ops
1533 * interface functions.
1534 *
1535 ****************************************************************************/
1536
1537
1538 static unsigned long dma_ops_alloc_iova(struct device *dev,
1539 struct dma_ops_domain *dma_dom,
1540 unsigned int pages, u64 dma_mask)
1541 {
1542 unsigned long pfn = 0;
1543
1544 pages = __roundup_pow_of_two(pages);
1545
1546 if (dma_mask > DMA_BIT_MASK(32))
1547 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1548 IOVA_PFN(DMA_BIT_MASK(32)));
1549
1550 if (!pfn)
1551 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1552
1553 return (pfn << PAGE_SHIFT);
1554 }
1555
1556 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1557 unsigned long address,
1558 unsigned int pages)
1559 {
1560 pages = __roundup_pow_of_two(pages);
1561 address >>= PAGE_SHIFT;
1562
1563 free_iova_fast(&dma_dom->iovad, address, pages);
1564 }
1565
1566 /****************************************************************************
1567 *
1568 * The next functions belong to the domain allocation. A domain is
1569 * allocated for every IOMMU as the default domain. If device isolation
1570 * is enabled, every device get its own domain. The most important thing
1571 * about domains is the page table mapping the DMA address space they
1572 * contain.
1573 *
1574 ****************************************************************************/
1575
1576 /*
1577 * This function adds a protection domain to the global protection domain list
1578 */
1579 static void add_domain_to_list(struct protection_domain *domain)
1580 {
1581 unsigned long flags;
1582
1583 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1584 list_add(&domain->list, &amd_iommu_pd_list);
1585 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1586 }
1587
1588 /*
1589 * This function removes a protection domain to the global
1590 * protection domain list
1591 */
1592 static void del_domain_from_list(struct protection_domain *domain)
1593 {
1594 unsigned long flags;
1595
1596 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1597 list_del(&domain->list);
1598 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1599 }
1600
1601 static u16 domain_id_alloc(void)
1602 {
1603 unsigned long flags;
1604 int id;
1605
1606 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1607 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1608 BUG_ON(id == 0);
1609 if (id > 0 && id < MAX_DOMAIN_ID)
1610 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1611 else
1612 id = 0;
1613 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1614
1615 return id;
1616 }
1617
1618 static void domain_id_free(int id)
1619 {
1620 unsigned long flags;
1621
1622 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1623 if (id > 0 && id < MAX_DOMAIN_ID)
1624 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1625 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1626 }
1627
1628 #define DEFINE_FREE_PT_FN(LVL, FN) \
1629 static void free_pt_##LVL (unsigned long __pt) \
1630 { \
1631 unsigned long p; \
1632 u64 *pt; \
1633 int i; \
1634 \
1635 pt = (u64 *)__pt; \
1636 \
1637 for (i = 0; i < 512; ++i) { \
1638 /* PTE present? */ \
1639 if (!IOMMU_PTE_PRESENT(pt[i])) \
1640 continue; \
1641 \
1642 /* Large PTE? */ \
1643 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1644 PM_PTE_LEVEL(pt[i]) == 7) \
1645 continue; \
1646 \
1647 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1648 FN(p); \
1649 } \
1650 free_page((unsigned long)pt); \
1651 }
1652
1653 DEFINE_FREE_PT_FN(l2, free_page)
1654 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1655 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1656 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1657 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1658
1659 static void free_pagetable(struct protection_domain *domain)
1660 {
1661 unsigned long root = (unsigned long)domain->pt_root;
1662
1663 switch (domain->mode) {
1664 case PAGE_MODE_NONE:
1665 break;
1666 case PAGE_MODE_1_LEVEL:
1667 free_page(root);
1668 break;
1669 case PAGE_MODE_2_LEVEL:
1670 free_pt_l2(root);
1671 break;
1672 case PAGE_MODE_3_LEVEL:
1673 free_pt_l3(root);
1674 break;
1675 case PAGE_MODE_4_LEVEL:
1676 free_pt_l4(root);
1677 break;
1678 case PAGE_MODE_5_LEVEL:
1679 free_pt_l5(root);
1680 break;
1681 case PAGE_MODE_6_LEVEL:
1682 free_pt_l6(root);
1683 break;
1684 default:
1685 BUG();
1686 }
1687 }
1688
1689 static void free_gcr3_tbl_level1(u64 *tbl)
1690 {
1691 u64 *ptr;
1692 int i;
1693
1694 for (i = 0; i < 512; ++i) {
1695 if (!(tbl[i] & GCR3_VALID))
1696 continue;
1697
1698 ptr = __va(tbl[i] & PAGE_MASK);
1699
1700 free_page((unsigned long)ptr);
1701 }
1702 }
1703
1704 static void free_gcr3_tbl_level2(u64 *tbl)
1705 {
1706 u64 *ptr;
1707 int i;
1708
1709 for (i = 0; i < 512; ++i) {
1710 if (!(tbl[i] & GCR3_VALID))
1711 continue;
1712
1713 ptr = __va(tbl[i] & PAGE_MASK);
1714
1715 free_gcr3_tbl_level1(ptr);
1716 }
1717 }
1718
1719 static void free_gcr3_table(struct protection_domain *domain)
1720 {
1721 if (domain->glx == 2)
1722 free_gcr3_tbl_level2(domain->gcr3_tbl);
1723 else if (domain->glx == 1)
1724 free_gcr3_tbl_level1(domain->gcr3_tbl);
1725 else
1726 BUG_ON(domain->glx != 0);
1727
1728 free_page((unsigned long)domain->gcr3_tbl);
1729 }
1730
1731 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1732 {
1733 domain_flush_tlb(&dom->domain);
1734 domain_flush_complete(&dom->domain);
1735 }
1736
1737 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1738 {
1739 struct dma_ops_domain *dom;
1740
1741 dom = container_of(iovad, struct dma_ops_domain, iovad);
1742
1743 dma_ops_domain_flush_tlb(dom);
1744 }
1745
1746 /*
1747 * Free a domain, only used if something went wrong in the
1748 * allocation path and we need to free an already allocated page table
1749 */
1750 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1751 {
1752 if (!dom)
1753 return;
1754
1755 del_domain_from_list(&dom->domain);
1756
1757 put_iova_domain(&dom->iovad);
1758
1759 free_pagetable(&dom->domain);
1760
1761 if (dom->domain.id)
1762 domain_id_free(dom->domain.id);
1763
1764 kfree(dom);
1765 }
1766
1767 /*
1768 * Allocates a new protection domain usable for the dma_ops functions.
1769 * It also initializes the page table and the address allocator data
1770 * structures required for the dma_ops interface
1771 */
1772 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1773 {
1774 struct dma_ops_domain *dma_dom;
1775
1776 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1777 if (!dma_dom)
1778 return NULL;
1779
1780 if (protection_domain_init(&dma_dom->domain))
1781 goto free_dma_dom;
1782
1783 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1784 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1785 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1786 if (!dma_dom->domain.pt_root)
1787 goto free_dma_dom;
1788
1789 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1790 IOVA_START_PFN, DMA_32BIT_PFN);
1791
1792 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1793 goto free_dma_dom;
1794
1795 /* Initialize reserved ranges */
1796 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1797
1798 add_domain_to_list(&dma_dom->domain);
1799
1800 return dma_dom;
1801
1802 free_dma_dom:
1803 dma_ops_domain_free(dma_dom);
1804
1805 return NULL;
1806 }
1807
1808 /*
1809 * little helper function to check whether a given protection domain is a
1810 * dma_ops domain
1811 */
1812 static bool dma_ops_domain(struct protection_domain *domain)
1813 {
1814 return domain->flags & PD_DMA_OPS_MASK;
1815 }
1816
1817 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1818 {
1819 u64 pte_root = 0;
1820 u64 flags = 0;
1821
1822 if (domain->mode != PAGE_MODE_NONE)
1823 pte_root = virt_to_phys(domain->pt_root);
1824
1825 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1826 << DEV_ENTRY_MODE_SHIFT;
1827 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1828
1829 flags = amd_iommu_dev_table[devid].data[1];
1830
1831 if (ats)
1832 flags |= DTE_FLAG_IOTLB;
1833
1834 if (domain->flags & PD_IOMMUV2_MASK) {
1835 u64 gcr3 = __pa(domain->gcr3_tbl);
1836 u64 glx = domain->glx;
1837 u64 tmp;
1838
1839 pte_root |= DTE_FLAG_GV;
1840 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1841
1842 /* First mask out possible old values for GCR3 table */
1843 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1844 flags &= ~tmp;
1845
1846 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1847 flags &= ~tmp;
1848
1849 /* Encode GCR3 table into DTE */
1850 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1851 pte_root |= tmp;
1852
1853 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1854 flags |= tmp;
1855
1856 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1857 flags |= tmp;
1858 }
1859
1860 flags &= ~DEV_DOMID_MASK;
1861 flags |= domain->id;
1862
1863 amd_iommu_dev_table[devid].data[1] = flags;
1864 amd_iommu_dev_table[devid].data[0] = pte_root;
1865 }
1866
1867 static void clear_dte_entry(u16 devid)
1868 {
1869 /* remove entry from the device table seen by the hardware */
1870 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1871 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1872
1873 amd_iommu_apply_erratum_63(devid);
1874 }
1875
1876 static void do_attach(struct iommu_dev_data *dev_data,
1877 struct protection_domain *domain)
1878 {
1879 struct amd_iommu *iommu;
1880 u16 alias;
1881 bool ats;
1882
1883 iommu = amd_iommu_rlookup_table[dev_data->devid];
1884 alias = dev_data->alias;
1885 ats = dev_data->ats.enabled;
1886
1887 /* Update data structures */
1888 dev_data->domain = domain;
1889 list_add(&dev_data->list, &domain->dev_list);
1890
1891 /* Do reference counting */
1892 domain->dev_iommu[iommu->index] += 1;
1893 domain->dev_cnt += 1;
1894
1895 /* Update device table */
1896 set_dte_entry(dev_data->devid, domain, ats);
1897 if (alias != dev_data->devid)
1898 set_dte_entry(alias, domain, ats);
1899
1900 device_flush_dte(dev_data);
1901 }
1902
1903 static void do_detach(struct iommu_dev_data *dev_data)
1904 {
1905 struct amd_iommu *iommu;
1906 u16 alias;
1907
1908 /*
1909 * First check if the device is still attached. It might already
1910 * be detached from its domain because the generic
1911 * iommu_detach_group code detached it and we try again here in
1912 * our alias handling.
1913 */
1914 if (!dev_data->domain)
1915 return;
1916
1917 iommu = amd_iommu_rlookup_table[dev_data->devid];
1918 alias = dev_data->alias;
1919
1920 /* decrease reference counters */
1921 dev_data->domain->dev_iommu[iommu->index] -= 1;
1922 dev_data->domain->dev_cnt -= 1;
1923
1924 /* Update data structures */
1925 dev_data->domain = NULL;
1926 list_del(&dev_data->list);
1927 clear_dte_entry(dev_data->devid);
1928 if (alias != dev_data->devid)
1929 clear_dte_entry(alias);
1930
1931 /* Flush the DTE entry */
1932 device_flush_dte(dev_data);
1933 }
1934
1935 /*
1936 * If a device is not yet associated with a domain, this function does
1937 * assigns it visible for the hardware
1938 */
1939 static int __attach_device(struct iommu_dev_data *dev_data,
1940 struct protection_domain *domain)
1941 {
1942 int ret;
1943
1944 /*
1945 * Must be called with IRQs disabled. Warn here to detect early
1946 * when its not.
1947 */
1948 WARN_ON(!irqs_disabled());
1949
1950 /* lock domain */
1951 spin_lock(&domain->lock);
1952
1953 ret = -EBUSY;
1954 if (dev_data->domain != NULL)
1955 goto out_unlock;
1956
1957 /* Attach alias group root */
1958 do_attach(dev_data, domain);
1959
1960 ret = 0;
1961
1962 out_unlock:
1963
1964 /* ready */
1965 spin_unlock(&domain->lock);
1966
1967 return ret;
1968 }
1969
1970
1971 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1972 {
1973 pci_disable_ats(pdev);
1974 pci_disable_pri(pdev);
1975 pci_disable_pasid(pdev);
1976 }
1977
1978 /* FIXME: Change generic reset-function to do the same */
1979 static int pri_reset_while_enabled(struct pci_dev *pdev)
1980 {
1981 u16 control;
1982 int pos;
1983
1984 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1985 if (!pos)
1986 return -EINVAL;
1987
1988 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1989 control |= PCI_PRI_CTRL_RESET;
1990 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1991
1992 return 0;
1993 }
1994
1995 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1996 {
1997 bool reset_enable;
1998 int reqs, ret;
1999
2000 /* FIXME: Hardcode number of outstanding requests for now */
2001 reqs = 32;
2002 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2003 reqs = 1;
2004 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2005
2006 /* Only allow access to user-accessible pages */
2007 ret = pci_enable_pasid(pdev, 0);
2008 if (ret)
2009 goto out_err;
2010
2011 /* First reset the PRI state of the device */
2012 ret = pci_reset_pri(pdev);
2013 if (ret)
2014 goto out_err;
2015
2016 /* Enable PRI */
2017 ret = pci_enable_pri(pdev, reqs);
2018 if (ret)
2019 goto out_err;
2020
2021 if (reset_enable) {
2022 ret = pri_reset_while_enabled(pdev);
2023 if (ret)
2024 goto out_err;
2025 }
2026
2027 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2028 if (ret)
2029 goto out_err;
2030
2031 return 0;
2032
2033 out_err:
2034 pci_disable_pri(pdev);
2035 pci_disable_pasid(pdev);
2036
2037 return ret;
2038 }
2039
2040 /* FIXME: Move this to PCI code */
2041 #define PCI_PRI_TLP_OFF (1 << 15)
2042
2043 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2044 {
2045 u16 status;
2046 int pos;
2047
2048 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2049 if (!pos)
2050 return false;
2051
2052 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2053
2054 return (status & PCI_PRI_TLP_OFF) ? true : false;
2055 }
2056
2057 /*
2058 * If a device is not yet associated with a domain, this function
2059 * assigns it visible for the hardware
2060 */
2061 static int attach_device(struct device *dev,
2062 struct protection_domain *domain)
2063 {
2064 struct pci_dev *pdev;
2065 struct iommu_dev_data *dev_data;
2066 unsigned long flags;
2067 int ret;
2068
2069 dev_data = get_dev_data(dev);
2070
2071 if (!dev_is_pci(dev))
2072 goto skip_ats_check;
2073
2074 pdev = to_pci_dev(dev);
2075 if (domain->flags & PD_IOMMUV2_MASK) {
2076 if (!dev_data->passthrough)
2077 return -EINVAL;
2078
2079 if (dev_data->iommu_v2) {
2080 if (pdev_iommuv2_enable(pdev) != 0)
2081 return -EINVAL;
2082
2083 dev_data->ats.enabled = true;
2084 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2085 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2086 }
2087 } else if (amd_iommu_iotlb_sup &&
2088 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2089 dev_data->ats.enabled = true;
2090 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2091 }
2092
2093 skip_ats_check:
2094 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2095 ret = __attach_device(dev_data, domain);
2096 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2097
2098 /*
2099 * We might boot into a crash-kernel here. The crashed kernel
2100 * left the caches in the IOMMU dirty. So we have to flush
2101 * here to evict all dirty stuff.
2102 */
2103 domain_flush_tlb_pde(domain);
2104
2105 return ret;
2106 }
2107
2108 /*
2109 * Removes a device from a protection domain (unlocked)
2110 */
2111 static void __detach_device(struct iommu_dev_data *dev_data)
2112 {
2113 struct protection_domain *domain;
2114
2115 /*
2116 * Must be called with IRQs disabled. Warn here to detect early
2117 * when its not.
2118 */
2119 WARN_ON(!irqs_disabled());
2120
2121 if (WARN_ON(!dev_data->domain))
2122 return;
2123
2124 domain = dev_data->domain;
2125
2126 spin_lock(&domain->lock);
2127
2128 do_detach(dev_data);
2129
2130 spin_unlock(&domain->lock);
2131 }
2132
2133 /*
2134 * Removes a device from a protection domain (with devtable_lock held)
2135 */
2136 static void detach_device(struct device *dev)
2137 {
2138 struct protection_domain *domain;
2139 struct iommu_dev_data *dev_data;
2140 unsigned long flags;
2141
2142 dev_data = get_dev_data(dev);
2143 domain = dev_data->domain;
2144
2145 /* lock device table */
2146 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2147 __detach_device(dev_data);
2148 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2149
2150 if (!dev_is_pci(dev))
2151 return;
2152
2153 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2154 pdev_iommuv2_disable(to_pci_dev(dev));
2155 else if (dev_data->ats.enabled)
2156 pci_disable_ats(to_pci_dev(dev));
2157
2158 dev_data->ats.enabled = false;
2159 }
2160
2161 static int amd_iommu_add_device(struct device *dev)
2162 {
2163 struct iommu_dev_data *dev_data;
2164 struct iommu_domain *domain;
2165 struct amd_iommu *iommu;
2166 int ret, devid;
2167
2168 if (!check_device(dev) || get_dev_data(dev))
2169 return 0;
2170
2171 devid = get_device_id(dev);
2172 if (devid < 0)
2173 return devid;
2174
2175 iommu = amd_iommu_rlookup_table[devid];
2176
2177 ret = iommu_init_device(dev);
2178 if (ret) {
2179 if (ret != -ENOTSUPP)
2180 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2181 dev_name(dev));
2182
2183 iommu_ignore_device(dev);
2184 dev->dma_ops = &nommu_dma_ops;
2185 goto out;
2186 }
2187 init_iommu_group(dev);
2188
2189 dev_data = get_dev_data(dev);
2190
2191 BUG_ON(!dev_data);
2192
2193 if (iommu_pass_through || dev_data->iommu_v2)
2194 iommu_request_dm_for_dev(dev);
2195
2196 /* Domains are initialized for this device - have a look what we ended up with */
2197 domain = iommu_get_domain_for_dev(dev);
2198 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2199 dev_data->passthrough = true;
2200 else
2201 dev->dma_ops = &amd_iommu_dma_ops;
2202
2203 out:
2204 iommu_completion_wait(iommu);
2205
2206 return 0;
2207 }
2208
2209 static void amd_iommu_remove_device(struct device *dev)
2210 {
2211 struct amd_iommu *iommu;
2212 int devid;
2213
2214 if (!check_device(dev))
2215 return;
2216
2217 devid = get_device_id(dev);
2218 if (devid < 0)
2219 return;
2220
2221 iommu = amd_iommu_rlookup_table[devid];
2222
2223 iommu_uninit_device(dev);
2224 iommu_completion_wait(iommu);
2225 }
2226
2227 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2228 {
2229 if (dev_is_pci(dev))
2230 return pci_device_group(dev);
2231
2232 return acpihid_device_group(dev);
2233 }
2234
2235 /*****************************************************************************
2236 *
2237 * The next functions belong to the dma_ops mapping/unmapping code.
2238 *
2239 *****************************************************************************/
2240
2241 /*
2242 * In the dma_ops path we only have the struct device. This function
2243 * finds the corresponding IOMMU, the protection domain and the
2244 * requestor id for a given device.
2245 * If the device is not yet associated with a domain this is also done
2246 * in this function.
2247 */
2248 static struct protection_domain *get_domain(struct device *dev)
2249 {
2250 struct protection_domain *domain;
2251 struct iommu_domain *io_domain;
2252
2253 if (!check_device(dev))
2254 return ERR_PTR(-EINVAL);
2255
2256 domain = get_dev_data(dev)->domain;
2257 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2258 get_dev_data(dev)->defer_attach = false;
2259 io_domain = iommu_get_domain_for_dev(dev);
2260 domain = to_pdomain(io_domain);
2261 attach_device(dev, domain);
2262 }
2263 if (domain == NULL)
2264 return ERR_PTR(-EBUSY);
2265
2266 if (!dma_ops_domain(domain))
2267 return ERR_PTR(-EBUSY);
2268
2269 return domain;
2270 }
2271
2272 static void update_device_table(struct protection_domain *domain)
2273 {
2274 struct iommu_dev_data *dev_data;
2275
2276 list_for_each_entry(dev_data, &domain->dev_list, list) {
2277 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2278
2279 if (dev_data->devid == dev_data->alias)
2280 continue;
2281
2282 /* There is an alias, update device table entry for it */
2283 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2284 }
2285 }
2286
2287 static void update_domain(struct protection_domain *domain)
2288 {
2289 if (!domain->updated)
2290 return;
2291
2292 update_device_table(domain);
2293
2294 domain_flush_devices(domain);
2295 domain_flush_tlb_pde(domain);
2296
2297 domain->updated = false;
2298 }
2299
2300 static int dir2prot(enum dma_data_direction direction)
2301 {
2302 if (direction == DMA_TO_DEVICE)
2303 return IOMMU_PROT_IR;
2304 else if (direction == DMA_FROM_DEVICE)
2305 return IOMMU_PROT_IW;
2306 else if (direction == DMA_BIDIRECTIONAL)
2307 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2308 else
2309 return 0;
2310 }
2311
2312 /*
2313 * This function contains common code for mapping of a physically
2314 * contiguous memory region into DMA address space. It is used by all
2315 * mapping functions provided with this IOMMU driver.
2316 * Must be called with the domain lock held.
2317 */
2318 static dma_addr_t __map_single(struct device *dev,
2319 struct dma_ops_domain *dma_dom,
2320 phys_addr_t paddr,
2321 size_t size,
2322 enum dma_data_direction direction,
2323 u64 dma_mask)
2324 {
2325 dma_addr_t offset = paddr & ~PAGE_MASK;
2326 dma_addr_t address, start, ret;
2327 unsigned int pages;
2328 int prot = 0;
2329 int i;
2330
2331 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2332 paddr &= PAGE_MASK;
2333
2334 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2335 if (address == AMD_IOMMU_MAPPING_ERROR)
2336 goto out;
2337
2338 prot = dir2prot(direction);
2339
2340 start = address;
2341 for (i = 0; i < pages; ++i) {
2342 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2343 PAGE_SIZE, prot, GFP_ATOMIC);
2344 if (ret)
2345 goto out_unmap;
2346
2347 paddr += PAGE_SIZE;
2348 start += PAGE_SIZE;
2349 }
2350 address += offset;
2351
2352 if (unlikely(amd_iommu_np_cache)) {
2353 domain_flush_pages(&dma_dom->domain, address, size);
2354 domain_flush_complete(&dma_dom->domain);
2355 }
2356
2357 out:
2358 return address;
2359
2360 out_unmap:
2361
2362 for (--i; i >= 0; --i) {
2363 start -= PAGE_SIZE;
2364 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2365 }
2366
2367 domain_flush_tlb(&dma_dom->domain);
2368 domain_flush_complete(&dma_dom->domain);
2369
2370 dma_ops_free_iova(dma_dom, address, pages);
2371
2372 return AMD_IOMMU_MAPPING_ERROR;
2373 }
2374
2375 /*
2376 * Does the reverse of the __map_single function. Must be called with
2377 * the domain lock held too
2378 */
2379 static void __unmap_single(struct dma_ops_domain *dma_dom,
2380 dma_addr_t dma_addr,
2381 size_t size,
2382 int dir)
2383 {
2384 dma_addr_t flush_addr;
2385 dma_addr_t i, start;
2386 unsigned int pages;
2387
2388 flush_addr = dma_addr;
2389 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2390 dma_addr &= PAGE_MASK;
2391 start = dma_addr;
2392
2393 for (i = 0; i < pages; ++i) {
2394 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2395 start += PAGE_SIZE;
2396 }
2397
2398 if (amd_iommu_unmap_flush) {
2399 dma_ops_free_iova(dma_dom, dma_addr, pages);
2400 domain_flush_tlb(&dma_dom->domain);
2401 domain_flush_complete(&dma_dom->domain);
2402 } else {
2403 pages = __roundup_pow_of_two(pages);
2404 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2405 }
2406 }
2407
2408 /*
2409 * The exported map_single function for dma_ops.
2410 */
2411 static dma_addr_t map_page(struct device *dev, struct page *page,
2412 unsigned long offset, size_t size,
2413 enum dma_data_direction dir,
2414 unsigned long attrs)
2415 {
2416 phys_addr_t paddr = page_to_phys(page) + offset;
2417 struct protection_domain *domain;
2418 struct dma_ops_domain *dma_dom;
2419 u64 dma_mask;
2420
2421 domain = get_domain(dev);
2422 if (PTR_ERR(domain) == -EINVAL)
2423 return (dma_addr_t)paddr;
2424 else if (IS_ERR(domain))
2425 return AMD_IOMMU_MAPPING_ERROR;
2426
2427 dma_mask = *dev->dma_mask;
2428 dma_dom = to_dma_ops_domain(domain);
2429
2430 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2431 }
2432
2433 /*
2434 * The exported unmap_single function for dma_ops.
2435 */
2436 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2437 enum dma_data_direction dir, unsigned long attrs)
2438 {
2439 struct protection_domain *domain;
2440 struct dma_ops_domain *dma_dom;
2441
2442 domain = get_domain(dev);
2443 if (IS_ERR(domain))
2444 return;
2445
2446 dma_dom = to_dma_ops_domain(domain);
2447
2448 __unmap_single(dma_dom, dma_addr, size, dir);
2449 }
2450
2451 static int sg_num_pages(struct device *dev,
2452 struct scatterlist *sglist,
2453 int nelems)
2454 {
2455 unsigned long mask, boundary_size;
2456 struct scatterlist *s;
2457 int i, npages = 0;
2458
2459 mask = dma_get_seg_boundary(dev);
2460 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2461 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2462
2463 for_each_sg(sglist, s, nelems, i) {
2464 int p, n;
2465
2466 s->dma_address = npages << PAGE_SHIFT;
2467 p = npages % boundary_size;
2468 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2469 if (p + n > boundary_size)
2470 npages += boundary_size - p;
2471 npages += n;
2472 }
2473
2474 return npages;
2475 }
2476
2477 /*
2478 * The exported map_sg function for dma_ops (handles scatter-gather
2479 * lists).
2480 */
2481 static int map_sg(struct device *dev, struct scatterlist *sglist,
2482 int nelems, enum dma_data_direction direction,
2483 unsigned long attrs)
2484 {
2485 int mapped_pages = 0, npages = 0, prot = 0, i;
2486 struct protection_domain *domain;
2487 struct dma_ops_domain *dma_dom;
2488 struct scatterlist *s;
2489 unsigned long address;
2490 u64 dma_mask;
2491
2492 domain = get_domain(dev);
2493 if (IS_ERR(domain))
2494 return 0;
2495
2496 dma_dom = to_dma_ops_domain(domain);
2497 dma_mask = *dev->dma_mask;
2498
2499 npages = sg_num_pages(dev, sglist, nelems);
2500
2501 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2502 if (address == AMD_IOMMU_MAPPING_ERROR)
2503 goto out_err;
2504
2505 prot = dir2prot(direction);
2506
2507 /* Map all sg entries */
2508 for_each_sg(sglist, s, nelems, i) {
2509 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2510
2511 for (j = 0; j < pages; ++j) {
2512 unsigned long bus_addr, phys_addr;
2513 int ret;
2514
2515 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2516 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2517 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2518 if (ret)
2519 goto out_unmap;
2520
2521 mapped_pages += 1;
2522 }
2523 }
2524
2525 /* Everything is mapped - write the right values into s->dma_address */
2526 for_each_sg(sglist, s, nelems, i) {
2527 s->dma_address += address + s->offset;
2528 s->dma_length = s->length;
2529 }
2530
2531 return nelems;
2532
2533 out_unmap:
2534 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2535 dev_name(dev), npages);
2536
2537 for_each_sg(sglist, s, nelems, i) {
2538 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2539
2540 for (j = 0; j < pages; ++j) {
2541 unsigned long bus_addr;
2542
2543 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2544 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2545
2546 if (--mapped_pages)
2547 goto out_free_iova;
2548 }
2549 }
2550
2551 out_free_iova:
2552 free_iova_fast(&dma_dom->iovad, address, npages);
2553
2554 out_err:
2555 return 0;
2556 }
2557
2558 /*
2559 * The exported map_sg function for dma_ops (handles scatter-gather
2560 * lists).
2561 */
2562 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2563 int nelems, enum dma_data_direction dir,
2564 unsigned long attrs)
2565 {
2566 struct protection_domain *domain;
2567 struct dma_ops_domain *dma_dom;
2568 unsigned long startaddr;
2569 int npages = 2;
2570
2571 domain = get_domain(dev);
2572 if (IS_ERR(domain))
2573 return;
2574
2575 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2576 dma_dom = to_dma_ops_domain(domain);
2577 npages = sg_num_pages(dev, sglist, nelems);
2578
2579 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2580 }
2581
2582 /*
2583 * The exported alloc_coherent function for dma_ops.
2584 */
2585 static void *alloc_coherent(struct device *dev, size_t size,
2586 dma_addr_t *dma_addr, gfp_t flag,
2587 unsigned long attrs)
2588 {
2589 u64 dma_mask = dev->coherent_dma_mask;
2590 struct protection_domain *domain;
2591 struct dma_ops_domain *dma_dom;
2592 struct page *page;
2593
2594 domain = get_domain(dev);
2595 if (PTR_ERR(domain) == -EINVAL) {
2596 page = alloc_pages(flag, get_order(size));
2597 *dma_addr = page_to_phys(page);
2598 return page_address(page);
2599 } else if (IS_ERR(domain))
2600 return NULL;
2601
2602 dma_dom = to_dma_ops_domain(domain);
2603 size = PAGE_ALIGN(size);
2604 dma_mask = dev->coherent_dma_mask;
2605 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2606 flag |= __GFP_ZERO;
2607
2608 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2609 if (!page) {
2610 if (!gfpflags_allow_blocking(flag))
2611 return NULL;
2612
2613 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2614 get_order(size), flag);
2615 if (!page)
2616 return NULL;
2617 }
2618
2619 if (!dma_mask)
2620 dma_mask = *dev->dma_mask;
2621
2622 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2623 size, DMA_BIDIRECTIONAL, dma_mask);
2624
2625 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2626 goto out_free;
2627
2628 return page_address(page);
2629
2630 out_free:
2631
2632 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2633 __free_pages(page, get_order(size));
2634
2635 return NULL;
2636 }
2637
2638 /*
2639 * The exported free_coherent function for dma_ops.
2640 */
2641 static void free_coherent(struct device *dev, size_t size,
2642 void *virt_addr, dma_addr_t dma_addr,
2643 unsigned long attrs)
2644 {
2645 struct protection_domain *domain;
2646 struct dma_ops_domain *dma_dom;
2647 struct page *page;
2648
2649 page = virt_to_page(virt_addr);
2650 size = PAGE_ALIGN(size);
2651
2652 domain = get_domain(dev);
2653 if (IS_ERR(domain))
2654 goto free_mem;
2655
2656 dma_dom = to_dma_ops_domain(domain);
2657
2658 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2659
2660 free_mem:
2661 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2662 __free_pages(page, get_order(size));
2663 }
2664
2665 /*
2666 * This function is called by the DMA layer to find out if we can handle a
2667 * particular device. It is part of the dma_ops.
2668 */
2669 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2670 {
2671 if (!x86_dma_supported(dev, mask))
2672 return 0;
2673 return check_device(dev);
2674 }
2675
2676 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2677 {
2678 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2679 }
2680
2681 static const struct dma_map_ops amd_iommu_dma_ops = {
2682 .alloc = alloc_coherent,
2683 .free = free_coherent,
2684 .map_page = map_page,
2685 .unmap_page = unmap_page,
2686 .map_sg = map_sg,
2687 .unmap_sg = unmap_sg,
2688 .dma_supported = amd_iommu_dma_supported,
2689 .mapping_error = amd_iommu_mapping_error,
2690 };
2691
2692 static int init_reserved_iova_ranges(void)
2693 {
2694 struct pci_dev *pdev = NULL;
2695 struct iova *val;
2696
2697 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2698 IOVA_START_PFN, DMA_32BIT_PFN);
2699
2700 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2701 &reserved_rbtree_key);
2702
2703 /* MSI memory range */
2704 val = reserve_iova(&reserved_iova_ranges,
2705 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2706 if (!val) {
2707 pr_err("Reserving MSI range failed\n");
2708 return -ENOMEM;
2709 }
2710
2711 /* HT memory range */
2712 val = reserve_iova(&reserved_iova_ranges,
2713 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2714 if (!val) {
2715 pr_err("Reserving HT range failed\n");
2716 return -ENOMEM;
2717 }
2718
2719 /*
2720 * Memory used for PCI resources
2721 * FIXME: Check whether we can reserve the PCI-hole completly
2722 */
2723 for_each_pci_dev(pdev) {
2724 int i;
2725
2726 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2727 struct resource *r = &pdev->resource[i];
2728
2729 if (!(r->flags & IORESOURCE_MEM))
2730 continue;
2731
2732 val = reserve_iova(&reserved_iova_ranges,
2733 IOVA_PFN(r->start),
2734 IOVA_PFN(r->end));
2735 if (!val) {
2736 pr_err("Reserve pci-resource range failed\n");
2737 return -ENOMEM;
2738 }
2739 }
2740 }
2741
2742 return 0;
2743 }
2744
2745 int __init amd_iommu_init_api(void)
2746 {
2747 int ret, err = 0;
2748
2749 ret = iova_cache_get();
2750 if (ret)
2751 return ret;
2752
2753 ret = init_reserved_iova_ranges();
2754 if (ret)
2755 return ret;
2756
2757 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2758 if (err)
2759 return err;
2760 #ifdef CONFIG_ARM_AMBA
2761 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2762 if (err)
2763 return err;
2764 #endif
2765 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2766 if (err)
2767 return err;
2768
2769 return 0;
2770 }
2771
2772 int __init amd_iommu_init_dma_ops(void)
2773 {
2774 swiotlb = iommu_pass_through ? 1 : 0;
2775 iommu_detected = 1;
2776
2777 /*
2778 * In case we don't initialize SWIOTLB (actually the common case
2779 * when AMD IOMMU is enabled), make sure there are global
2780 * dma_ops set as a fall-back for devices not handled by this
2781 * driver (for example non-PCI devices).
2782 */
2783 if (!swiotlb)
2784 dma_ops = &nommu_dma_ops;
2785
2786 if (amd_iommu_unmap_flush)
2787 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2788 else
2789 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2790
2791 return 0;
2792
2793 }
2794
2795 /*****************************************************************************
2796 *
2797 * The following functions belong to the exported interface of AMD IOMMU
2798 *
2799 * This interface allows access to lower level functions of the IOMMU
2800 * like protection domain handling and assignement of devices to domains
2801 * which is not possible with the dma_ops interface.
2802 *
2803 *****************************************************************************/
2804
2805 static void cleanup_domain(struct protection_domain *domain)
2806 {
2807 struct iommu_dev_data *entry;
2808 unsigned long flags;
2809
2810 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2811
2812 while (!list_empty(&domain->dev_list)) {
2813 entry = list_first_entry(&domain->dev_list,
2814 struct iommu_dev_data, list);
2815 __detach_device(entry);
2816 }
2817
2818 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2819 }
2820
2821 static void protection_domain_free(struct protection_domain *domain)
2822 {
2823 if (!domain)
2824 return;
2825
2826 del_domain_from_list(domain);
2827
2828 if (domain->id)
2829 domain_id_free(domain->id);
2830
2831 kfree(domain);
2832 }
2833
2834 static int protection_domain_init(struct protection_domain *domain)
2835 {
2836 spin_lock_init(&domain->lock);
2837 mutex_init(&domain->api_lock);
2838 domain->id = domain_id_alloc();
2839 if (!domain->id)
2840 return -ENOMEM;
2841 INIT_LIST_HEAD(&domain->dev_list);
2842
2843 return 0;
2844 }
2845
2846 static struct protection_domain *protection_domain_alloc(void)
2847 {
2848 struct protection_domain *domain;
2849
2850 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2851 if (!domain)
2852 return NULL;
2853
2854 if (protection_domain_init(domain))
2855 goto out_err;
2856
2857 add_domain_to_list(domain);
2858
2859 return domain;
2860
2861 out_err:
2862 kfree(domain);
2863
2864 return NULL;
2865 }
2866
2867 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2868 {
2869 struct protection_domain *pdomain;
2870 struct dma_ops_domain *dma_domain;
2871
2872 switch (type) {
2873 case IOMMU_DOMAIN_UNMANAGED:
2874 pdomain = protection_domain_alloc();
2875 if (!pdomain)
2876 return NULL;
2877
2878 pdomain->mode = PAGE_MODE_3_LEVEL;
2879 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2880 if (!pdomain->pt_root) {
2881 protection_domain_free(pdomain);
2882 return NULL;
2883 }
2884
2885 pdomain->domain.geometry.aperture_start = 0;
2886 pdomain->domain.geometry.aperture_end = ~0ULL;
2887 pdomain->domain.geometry.force_aperture = true;
2888
2889 break;
2890 case IOMMU_DOMAIN_DMA:
2891 dma_domain = dma_ops_domain_alloc();
2892 if (!dma_domain) {
2893 pr_err("AMD-Vi: Failed to allocate\n");
2894 return NULL;
2895 }
2896 pdomain = &dma_domain->domain;
2897 break;
2898 case IOMMU_DOMAIN_IDENTITY:
2899 pdomain = protection_domain_alloc();
2900 if (!pdomain)
2901 return NULL;
2902
2903 pdomain->mode = PAGE_MODE_NONE;
2904 break;
2905 default:
2906 return NULL;
2907 }
2908
2909 return &pdomain->domain;
2910 }
2911
2912 static void amd_iommu_domain_free(struct iommu_domain *dom)
2913 {
2914 struct protection_domain *domain;
2915 struct dma_ops_domain *dma_dom;
2916
2917 domain = to_pdomain(dom);
2918
2919 if (domain->dev_cnt > 0)
2920 cleanup_domain(domain);
2921
2922 BUG_ON(domain->dev_cnt != 0);
2923
2924 if (!dom)
2925 return;
2926
2927 switch (dom->type) {
2928 case IOMMU_DOMAIN_DMA:
2929 /* Now release the domain */
2930 dma_dom = to_dma_ops_domain(domain);
2931 dma_ops_domain_free(dma_dom);
2932 break;
2933 default:
2934 if (domain->mode != PAGE_MODE_NONE)
2935 free_pagetable(domain);
2936
2937 if (domain->flags & PD_IOMMUV2_MASK)
2938 free_gcr3_table(domain);
2939
2940 protection_domain_free(domain);
2941 break;
2942 }
2943 }
2944
2945 static void amd_iommu_detach_device(struct iommu_domain *dom,
2946 struct device *dev)
2947 {
2948 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2949 struct amd_iommu *iommu;
2950 int devid;
2951
2952 if (!check_device(dev))
2953 return;
2954
2955 devid = get_device_id(dev);
2956 if (devid < 0)
2957 return;
2958
2959 if (dev_data->domain != NULL)
2960 detach_device(dev);
2961
2962 iommu = amd_iommu_rlookup_table[devid];
2963 if (!iommu)
2964 return;
2965
2966 #ifdef CONFIG_IRQ_REMAP
2967 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2968 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2969 dev_data->use_vapic = 0;
2970 #endif
2971
2972 iommu_completion_wait(iommu);
2973 }
2974
2975 static int amd_iommu_attach_device(struct iommu_domain *dom,
2976 struct device *dev)
2977 {
2978 struct protection_domain *domain = to_pdomain(dom);
2979 struct iommu_dev_data *dev_data;
2980 struct amd_iommu *iommu;
2981 int ret;
2982
2983 if (!check_device(dev))
2984 return -EINVAL;
2985
2986 dev_data = dev->archdata.iommu;
2987
2988 iommu = amd_iommu_rlookup_table[dev_data->devid];
2989 if (!iommu)
2990 return -EINVAL;
2991
2992 if (dev_data->domain)
2993 detach_device(dev);
2994
2995 ret = attach_device(dev, domain);
2996
2997 #ifdef CONFIG_IRQ_REMAP
2998 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
2999 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3000 dev_data->use_vapic = 1;
3001 else
3002 dev_data->use_vapic = 0;
3003 }
3004 #endif
3005
3006 iommu_completion_wait(iommu);
3007
3008 return ret;
3009 }
3010
3011 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3012 phys_addr_t paddr, size_t page_size, int iommu_prot)
3013 {
3014 struct protection_domain *domain = to_pdomain(dom);
3015 int prot = 0;
3016 int ret;
3017
3018 if (domain->mode == PAGE_MODE_NONE)
3019 return -EINVAL;
3020
3021 if (iommu_prot & IOMMU_READ)
3022 prot |= IOMMU_PROT_IR;
3023 if (iommu_prot & IOMMU_WRITE)
3024 prot |= IOMMU_PROT_IW;
3025
3026 mutex_lock(&domain->api_lock);
3027 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3028 mutex_unlock(&domain->api_lock);
3029
3030 return ret;
3031 }
3032
3033 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3034 size_t page_size)
3035 {
3036 struct protection_domain *domain = to_pdomain(dom);
3037 size_t unmap_size;
3038
3039 if (domain->mode == PAGE_MODE_NONE)
3040 return -EINVAL;
3041
3042 mutex_lock(&domain->api_lock);
3043 unmap_size = iommu_unmap_page(domain, iova, page_size);
3044 mutex_unlock(&domain->api_lock);
3045
3046 domain_flush_tlb_pde(domain);
3047
3048 return unmap_size;
3049 }
3050
3051 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3052 dma_addr_t iova)
3053 {
3054 struct protection_domain *domain = to_pdomain(dom);
3055 unsigned long offset_mask, pte_pgsize;
3056 u64 *pte, __pte;
3057
3058 if (domain->mode == PAGE_MODE_NONE)
3059 return iova;
3060
3061 pte = fetch_pte(domain, iova, &pte_pgsize);
3062
3063 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3064 return 0;
3065
3066 offset_mask = pte_pgsize - 1;
3067 __pte = *pte & PM_ADDR_MASK;
3068
3069 return (__pte & ~offset_mask) | (iova & offset_mask);
3070 }
3071
3072 static bool amd_iommu_capable(enum iommu_cap cap)
3073 {
3074 switch (cap) {
3075 case IOMMU_CAP_CACHE_COHERENCY:
3076 return true;
3077 case IOMMU_CAP_INTR_REMAP:
3078 return (irq_remapping_enabled == 1);
3079 case IOMMU_CAP_NOEXEC:
3080 return false;
3081 }
3082
3083 return false;
3084 }
3085
3086 static void amd_iommu_get_resv_regions(struct device *dev,
3087 struct list_head *head)
3088 {
3089 struct iommu_resv_region *region;
3090 struct unity_map_entry *entry;
3091 int devid;
3092
3093 devid = get_device_id(dev);
3094 if (devid < 0)
3095 return;
3096
3097 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3098 size_t length;
3099 int prot = 0;
3100
3101 if (devid < entry->devid_start || devid > entry->devid_end)
3102 continue;
3103
3104 length = entry->address_end - entry->address_start;
3105 if (entry->prot & IOMMU_PROT_IR)
3106 prot |= IOMMU_READ;
3107 if (entry->prot & IOMMU_PROT_IW)
3108 prot |= IOMMU_WRITE;
3109
3110 region = iommu_alloc_resv_region(entry->address_start,
3111 length, prot,
3112 IOMMU_RESV_DIRECT);
3113 if (!region) {
3114 pr_err("Out of memory allocating dm-regions for %s\n",
3115 dev_name(dev));
3116 return;
3117 }
3118 list_add_tail(&region->list, head);
3119 }
3120
3121 region = iommu_alloc_resv_region(MSI_RANGE_START,
3122 MSI_RANGE_END - MSI_RANGE_START + 1,
3123 0, IOMMU_RESV_MSI);
3124 if (!region)
3125 return;
3126 list_add_tail(&region->list, head);
3127
3128 region = iommu_alloc_resv_region(HT_RANGE_START,
3129 HT_RANGE_END - HT_RANGE_START + 1,
3130 0, IOMMU_RESV_RESERVED);
3131 if (!region)
3132 return;
3133 list_add_tail(&region->list, head);
3134 }
3135
3136 static void amd_iommu_put_resv_regions(struct device *dev,
3137 struct list_head *head)
3138 {
3139 struct iommu_resv_region *entry, *next;
3140
3141 list_for_each_entry_safe(entry, next, head, list)
3142 kfree(entry);
3143 }
3144
3145 static void amd_iommu_apply_resv_region(struct device *dev,
3146 struct iommu_domain *domain,
3147 struct iommu_resv_region *region)
3148 {
3149 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3150 unsigned long start, end;
3151
3152 start = IOVA_PFN(region->start);
3153 end = IOVA_PFN(region->start + region->length);
3154
3155 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3156 }
3157
3158 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3159 struct device *dev)
3160 {
3161 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3162 return dev_data->defer_attach;
3163 }
3164
3165 const struct iommu_ops amd_iommu_ops = {
3166 .capable = amd_iommu_capable,
3167 .domain_alloc = amd_iommu_domain_alloc,
3168 .domain_free = amd_iommu_domain_free,
3169 .attach_dev = amd_iommu_attach_device,
3170 .detach_dev = amd_iommu_detach_device,
3171 .map = amd_iommu_map,
3172 .unmap = amd_iommu_unmap,
3173 .map_sg = default_iommu_map_sg,
3174 .iova_to_phys = amd_iommu_iova_to_phys,
3175 .add_device = amd_iommu_add_device,
3176 .remove_device = amd_iommu_remove_device,
3177 .device_group = amd_iommu_device_group,
3178 .get_resv_regions = amd_iommu_get_resv_regions,
3179 .put_resv_regions = amd_iommu_put_resv_regions,
3180 .apply_resv_region = amd_iommu_apply_resv_region,
3181 .is_attach_deferred = amd_iommu_is_attach_deferred,
3182 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3183 };
3184
3185 /*****************************************************************************
3186 *
3187 * The next functions do a basic initialization of IOMMU for pass through
3188 * mode
3189 *
3190 * In passthrough mode the IOMMU is initialized and enabled but not used for
3191 * DMA-API translation.
3192 *
3193 *****************************************************************************/
3194
3195 /* IOMMUv2 specific functions */
3196 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3197 {
3198 return atomic_notifier_chain_register(&ppr_notifier, nb);
3199 }
3200 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3201
3202 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3203 {
3204 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3205 }
3206 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3207
3208 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3209 {
3210 struct protection_domain *domain = to_pdomain(dom);
3211 unsigned long flags;
3212
3213 spin_lock_irqsave(&domain->lock, flags);
3214
3215 /* Update data structure */
3216 domain->mode = PAGE_MODE_NONE;
3217 domain->updated = true;
3218
3219 /* Make changes visible to IOMMUs */
3220 update_domain(domain);
3221
3222 /* Page-table is not visible to IOMMU anymore, so free it */
3223 free_pagetable(domain);
3224
3225 spin_unlock_irqrestore(&domain->lock, flags);
3226 }
3227 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3228
3229 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3230 {
3231 struct protection_domain *domain = to_pdomain(dom);
3232 unsigned long flags;
3233 int levels, ret;
3234
3235 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3236 return -EINVAL;
3237
3238 /* Number of GCR3 table levels required */
3239 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3240 levels += 1;
3241
3242 if (levels > amd_iommu_max_glx_val)
3243 return -EINVAL;
3244
3245 spin_lock_irqsave(&domain->lock, flags);
3246
3247 /*
3248 * Save us all sanity checks whether devices already in the
3249 * domain support IOMMUv2. Just force that the domain has no
3250 * devices attached when it is switched into IOMMUv2 mode.
3251 */
3252 ret = -EBUSY;
3253 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3254 goto out;
3255
3256 ret = -ENOMEM;
3257 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3258 if (domain->gcr3_tbl == NULL)
3259 goto out;
3260
3261 domain->glx = levels;
3262 domain->flags |= PD_IOMMUV2_MASK;
3263 domain->updated = true;
3264
3265 update_domain(domain);
3266
3267 ret = 0;
3268
3269 out:
3270 spin_unlock_irqrestore(&domain->lock, flags);
3271
3272 return ret;
3273 }
3274 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3275
3276 static int __flush_pasid(struct protection_domain *domain, int pasid,
3277 u64 address, bool size)
3278 {
3279 struct iommu_dev_data *dev_data;
3280 struct iommu_cmd cmd;
3281 int i, ret;
3282
3283 if (!(domain->flags & PD_IOMMUV2_MASK))
3284 return -EINVAL;
3285
3286 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3287
3288 /*
3289 * IOMMU TLB needs to be flushed before Device TLB to
3290 * prevent device TLB refill from IOMMU TLB
3291 */
3292 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3293 if (domain->dev_iommu[i] == 0)
3294 continue;
3295
3296 ret = iommu_queue_command(amd_iommus[i], &cmd);
3297 if (ret != 0)
3298 goto out;
3299 }
3300
3301 /* Wait until IOMMU TLB flushes are complete */
3302 domain_flush_complete(domain);
3303
3304 /* Now flush device TLBs */
3305 list_for_each_entry(dev_data, &domain->dev_list, list) {
3306 struct amd_iommu *iommu;
3307 int qdep;
3308
3309 /*
3310 There might be non-IOMMUv2 capable devices in an IOMMUv2
3311 * domain.
3312 */
3313 if (!dev_data->ats.enabled)
3314 continue;
3315
3316 qdep = dev_data->ats.qdep;
3317 iommu = amd_iommu_rlookup_table[dev_data->devid];
3318
3319 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3320 qdep, address, size);
3321
3322 ret = iommu_queue_command(iommu, &cmd);
3323 if (ret != 0)
3324 goto out;
3325 }
3326
3327 /* Wait until all device TLBs are flushed */
3328 domain_flush_complete(domain);
3329
3330 ret = 0;
3331
3332 out:
3333
3334 return ret;
3335 }
3336
3337 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3338 u64 address)
3339 {
3340 return __flush_pasid(domain, pasid, address, false);
3341 }
3342
3343 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3344 u64 address)
3345 {
3346 struct protection_domain *domain = to_pdomain(dom);
3347 unsigned long flags;
3348 int ret;
3349
3350 spin_lock_irqsave(&domain->lock, flags);
3351 ret = __amd_iommu_flush_page(domain, pasid, address);
3352 spin_unlock_irqrestore(&domain->lock, flags);
3353
3354 return ret;
3355 }
3356 EXPORT_SYMBOL(amd_iommu_flush_page);
3357
3358 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3359 {
3360 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3361 true);
3362 }
3363
3364 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3365 {
3366 struct protection_domain *domain = to_pdomain(dom);
3367 unsigned long flags;
3368 int ret;
3369
3370 spin_lock_irqsave(&domain->lock, flags);
3371 ret = __amd_iommu_flush_tlb(domain, pasid);
3372 spin_unlock_irqrestore(&domain->lock, flags);
3373
3374 return ret;
3375 }
3376 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3377
3378 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3379 {
3380 int index;
3381 u64 *pte;
3382
3383 while (true) {
3384
3385 index = (pasid >> (9 * level)) & 0x1ff;
3386 pte = &root[index];
3387
3388 if (level == 0)
3389 break;
3390
3391 if (!(*pte & GCR3_VALID)) {
3392 if (!alloc)
3393 return NULL;
3394
3395 root = (void *)get_zeroed_page(GFP_ATOMIC);
3396 if (root == NULL)
3397 return NULL;
3398
3399 *pte = __pa(root) | GCR3_VALID;
3400 }
3401
3402 root = __va(*pte & PAGE_MASK);
3403
3404 level -= 1;
3405 }
3406
3407 return pte;
3408 }
3409
3410 static int __set_gcr3(struct protection_domain *domain, int pasid,
3411 unsigned long cr3)
3412 {
3413 u64 *pte;
3414
3415 if (domain->mode != PAGE_MODE_NONE)
3416 return -EINVAL;
3417
3418 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3419 if (pte == NULL)
3420 return -ENOMEM;
3421
3422 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3423
3424 return __amd_iommu_flush_tlb(domain, pasid);
3425 }
3426
3427 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3428 {
3429 u64 *pte;
3430
3431 if (domain->mode != PAGE_MODE_NONE)
3432 return -EINVAL;
3433
3434 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3435 if (pte == NULL)
3436 return 0;
3437
3438 *pte = 0;
3439
3440 return __amd_iommu_flush_tlb(domain, pasid);
3441 }
3442
3443 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3444 unsigned long cr3)
3445 {
3446 struct protection_domain *domain = to_pdomain(dom);
3447 unsigned long flags;
3448 int ret;
3449
3450 spin_lock_irqsave(&domain->lock, flags);
3451 ret = __set_gcr3(domain, pasid, cr3);
3452 spin_unlock_irqrestore(&domain->lock, flags);
3453
3454 return ret;
3455 }
3456 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3457
3458 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3459 {
3460 struct protection_domain *domain = to_pdomain(dom);
3461 unsigned long flags;
3462 int ret;
3463
3464 spin_lock_irqsave(&domain->lock, flags);
3465 ret = __clear_gcr3(domain, pasid);
3466 spin_unlock_irqrestore(&domain->lock, flags);
3467
3468 return ret;
3469 }
3470 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3471
3472 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3473 int status, int tag)
3474 {
3475 struct iommu_dev_data *dev_data;
3476 struct amd_iommu *iommu;
3477 struct iommu_cmd cmd;
3478
3479 dev_data = get_dev_data(&pdev->dev);
3480 iommu = amd_iommu_rlookup_table[dev_data->devid];
3481
3482 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3483 tag, dev_data->pri_tlp);
3484
3485 return iommu_queue_command(iommu, &cmd);
3486 }
3487 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3488
3489 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3490 {
3491 struct protection_domain *pdomain;
3492
3493 pdomain = get_domain(&pdev->dev);
3494 if (IS_ERR(pdomain))
3495 return NULL;
3496
3497 /* Only return IOMMUv2 domains */
3498 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3499 return NULL;
3500
3501 return &pdomain->domain;
3502 }
3503 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3504
3505 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3506 {
3507 struct iommu_dev_data *dev_data;
3508
3509 if (!amd_iommu_v2_supported())
3510 return;
3511
3512 dev_data = get_dev_data(&pdev->dev);
3513 dev_data->errata |= (1 << erratum);
3514 }
3515 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3516
3517 int amd_iommu_device_info(struct pci_dev *pdev,
3518 struct amd_iommu_device_info *info)
3519 {
3520 int max_pasids;
3521 int pos;
3522
3523 if (pdev == NULL || info == NULL)
3524 return -EINVAL;
3525
3526 if (!amd_iommu_v2_supported())
3527 return -EINVAL;
3528
3529 memset(info, 0, sizeof(*info));
3530
3531 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3532 if (pos)
3533 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3534
3535 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3536 if (pos)
3537 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3538
3539 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3540 if (pos) {
3541 int features;
3542
3543 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3544 max_pasids = min(max_pasids, (1 << 20));
3545
3546 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3547 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3548
3549 features = pci_pasid_features(pdev);
3550 if (features & PCI_PASID_CAP_EXEC)
3551 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3552 if (features & PCI_PASID_CAP_PRIV)
3553 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3554 }
3555
3556 return 0;
3557 }
3558 EXPORT_SYMBOL(amd_iommu_device_info);
3559
3560 #ifdef CONFIG_IRQ_REMAP
3561
3562 /*****************************************************************************
3563 *
3564 * Interrupt Remapping Implementation
3565 *
3566 *****************************************************************************/
3567
3568 static struct irq_chip amd_ir_chip;
3569
3570 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3571 {
3572 u64 dte;
3573
3574 dte = amd_iommu_dev_table[devid].data[2];
3575 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3576 dte |= virt_to_phys(table->table);
3577 dte |= DTE_IRQ_REMAP_INTCTL;
3578 dte |= DTE_IRQ_TABLE_LEN;
3579 dte |= DTE_IRQ_REMAP_ENABLE;
3580
3581 amd_iommu_dev_table[devid].data[2] = dte;
3582 }
3583
3584 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3585 {
3586 struct irq_remap_table *table = NULL;
3587 struct amd_iommu *iommu;
3588 unsigned long flags;
3589 u16 alias;
3590
3591 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3592
3593 iommu = amd_iommu_rlookup_table[devid];
3594 if (!iommu)
3595 goto out_unlock;
3596
3597 table = irq_lookup_table[devid];
3598 if (table)
3599 goto out_unlock;
3600
3601 alias = amd_iommu_alias_table[devid];
3602 table = irq_lookup_table[alias];
3603 if (table) {
3604 irq_lookup_table[devid] = table;
3605 set_dte_irq_entry(devid, table);
3606 iommu_flush_dte(iommu, devid);
3607 goto out;
3608 }
3609
3610 /* Nothing there yet, allocate new irq remapping table */
3611 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3612 if (!table)
3613 goto out_unlock;
3614
3615 /* Initialize table spin-lock */
3616 spin_lock_init(&table->lock);
3617
3618 if (ioapic)
3619 /* Keep the first 32 indexes free for IOAPIC interrupts */
3620 table->min_index = 32;
3621
3622 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3623 if (!table->table) {
3624 kfree(table);
3625 table = NULL;
3626 goto out_unlock;
3627 }
3628
3629 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3630 memset(table->table, 0,
3631 MAX_IRQS_PER_TABLE * sizeof(u32));
3632 else
3633 memset(table->table, 0,
3634 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3635
3636 if (ioapic) {
3637 int i;
3638
3639 for (i = 0; i < 32; ++i)
3640 iommu->irte_ops->set_allocated(table, i);
3641 }
3642
3643 irq_lookup_table[devid] = table;
3644 set_dte_irq_entry(devid, table);
3645 iommu_flush_dte(iommu, devid);
3646 if (devid != alias) {
3647 irq_lookup_table[alias] = table;
3648 set_dte_irq_entry(alias, table);
3649 iommu_flush_dte(iommu, alias);
3650 }
3651
3652 out:
3653 iommu_completion_wait(iommu);
3654
3655 out_unlock:
3656 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3657
3658 return table;
3659 }
3660
3661 static int alloc_irq_index(u16 devid, int count)
3662 {
3663 struct irq_remap_table *table;
3664 unsigned long flags;
3665 int index, c;
3666 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3667
3668 if (!iommu)
3669 return -ENODEV;
3670
3671 table = get_irq_table(devid, false);
3672 if (!table)
3673 return -ENODEV;
3674
3675 spin_lock_irqsave(&table->lock, flags);
3676
3677 /* Scan table for free entries */
3678 for (c = 0, index = table->min_index;
3679 index < MAX_IRQS_PER_TABLE;
3680 ++index) {
3681 if (!iommu->irte_ops->is_allocated(table, index))
3682 c += 1;
3683 else
3684 c = 0;
3685
3686 if (c == count) {
3687 for (; c != 0; --c)
3688 iommu->irte_ops->set_allocated(table, index - c + 1);
3689
3690 index -= count - 1;
3691 goto out;
3692 }
3693 }
3694
3695 index = -ENOSPC;
3696
3697 out:
3698 spin_unlock_irqrestore(&table->lock, flags);
3699
3700 return index;
3701 }
3702
3703 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3704 struct amd_ir_data *data)
3705 {
3706 struct irq_remap_table *table;
3707 struct amd_iommu *iommu;
3708 unsigned long flags;
3709 struct irte_ga *entry;
3710
3711 iommu = amd_iommu_rlookup_table[devid];
3712 if (iommu == NULL)
3713 return -EINVAL;
3714
3715 table = get_irq_table(devid, false);
3716 if (!table)
3717 return -ENOMEM;
3718
3719 spin_lock_irqsave(&table->lock, flags);
3720
3721 entry = (struct irte_ga *)table->table;
3722 entry = &entry[index];
3723 entry->lo.fields_remap.valid = 0;
3724 entry->hi.val = irte->hi.val;
3725 entry->lo.val = irte->lo.val;
3726 entry->lo.fields_remap.valid = 1;
3727 if (data)
3728 data->ref = entry;
3729
3730 spin_unlock_irqrestore(&table->lock, flags);
3731
3732 iommu_flush_irt(iommu, devid);
3733 iommu_completion_wait(iommu);
3734
3735 return 0;
3736 }
3737
3738 static int modify_irte(u16 devid, int index, union irte *irte)
3739 {
3740 struct irq_remap_table *table;
3741 struct amd_iommu *iommu;
3742 unsigned long flags;
3743
3744 iommu = amd_iommu_rlookup_table[devid];
3745 if (iommu == NULL)
3746 return -EINVAL;
3747
3748 table = get_irq_table(devid, false);
3749 if (!table)
3750 return -ENOMEM;
3751
3752 spin_lock_irqsave(&table->lock, flags);
3753 table->table[index] = irte->val;
3754 spin_unlock_irqrestore(&table->lock, flags);
3755
3756 iommu_flush_irt(iommu, devid);
3757 iommu_completion_wait(iommu);
3758
3759 return 0;
3760 }
3761
3762 static void free_irte(u16 devid, int index)
3763 {
3764 struct irq_remap_table *table;
3765 struct amd_iommu *iommu;
3766 unsigned long flags;
3767
3768 iommu = amd_iommu_rlookup_table[devid];
3769 if (iommu == NULL)
3770 return;
3771
3772 table = get_irq_table(devid, false);
3773 if (!table)
3774 return;
3775
3776 spin_lock_irqsave(&table->lock, flags);
3777 iommu->irte_ops->clear_allocated(table, index);
3778 spin_unlock_irqrestore(&table->lock, flags);
3779
3780 iommu_flush_irt(iommu, devid);
3781 iommu_completion_wait(iommu);
3782 }
3783
3784 static void irte_prepare(void *entry,
3785 u32 delivery_mode, u32 dest_mode,
3786 u8 vector, u32 dest_apicid, int devid)
3787 {
3788 union irte *irte = (union irte *) entry;
3789
3790 irte->val = 0;
3791 irte->fields.vector = vector;
3792 irte->fields.int_type = delivery_mode;
3793 irte->fields.destination = dest_apicid;
3794 irte->fields.dm = dest_mode;
3795 irte->fields.valid = 1;
3796 }
3797
3798 static void irte_ga_prepare(void *entry,
3799 u32 delivery_mode, u32 dest_mode,
3800 u8 vector, u32 dest_apicid, int devid)
3801 {
3802 struct irte_ga *irte = (struct irte_ga *) entry;
3803
3804 irte->lo.val = 0;
3805 irte->hi.val = 0;
3806 irte->lo.fields_remap.int_type = delivery_mode;
3807 irte->lo.fields_remap.dm = dest_mode;
3808 irte->hi.fields.vector = vector;
3809 irte->lo.fields_remap.destination = dest_apicid;
3810 irte->lo.fields_remap.valid = 1;
3811 }
3812
3813 static void irte_activate(void *entry, u16 devid, u16 index)
3814 {
3815 union irte *irte = (union irte *) entry;
3816
3817 irte->fields.valid = 1;
3818 modify_irte(devid, index, irte);
3819 }
3820
3821 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3822 {
3823 struct irte_ga *irte = (struct irte_ga *) entry;
3824
3825 irte->lo.fields_remap.valid = 1;
3826 modify_irte_ga(devid, index, irte, NULL);
3827 }
3828
3829 static void irte_deactivate(void *entry, u16 devid, u16 index)
3830 {
3831 union irte *irte = (union irte *) entry;
3832
3833 irte->fields.valid = 0;
3834 modify_irte(devid, index, irte);
3835 }
3836
3837 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3838 {
3839 struct irte_ga *irte = (struct irte_ga *) entry;
3840
3841 irte->lo.fields_remap.valid = 0;
3842 modify_irte_ga(devid, index, irte, NULL);
3843 }
3844
3845 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3846 u8 vector, u32 dest_apicid)
3847 {
3848 union irte *irte = (union irte *) entry;
3849
3850 irte->fields.vector = vector;
3851 irte->fields.destination = dest_apicid;
3852 modify_irte(devid, index, irte);
3853 }
3854
3855 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3856 u8 vector, u32 dest_apicid)
3857 {
3858 struct irte_ga *irte = (struct irte_ga *) entry;
3859 struct iommu_dev_data *dev_data = search_dev_data(devid);
3860
3861 if (!dev_data || !dev_data->use_vapic ||
3862 !irte->lo.fields_remap.guest_mode) {
3863 irte->hi.fields.vector = vector;
3864 irte->lo.fields_remap.destination = dest_apicid;
3865 modify_irte_ga(devid, index, irte, NULL);
3866 }
3867 }
3868
3869 #define IRTE_ALLOCATED (~1U)
3870 static void irte_set_allocated(struct irq_remap_table *table, int index)
3871 {
3872 table->table[index] = IRTE_ALLOCATED;
3873 }
3874
3875 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3876 {
3877 struct irte_ga *ptr = (struct irte_ga *)table->table;
3878 struct irte_ga *irte = &ptr[index];
3879
3880 memset(&irte->lo.val, 0, sizeof(u64));
3881 memset(&irte->hi.val, 0, sizeof(u64));
3882 irte->hi.fields.vector = 0xff;
3883 }
3884
3885 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3886 {
3887 union irte *ptr = (union irte *)table->table;
3888 union irte *irte = &ptr[index];
3889
3890 return irte->val != 0;
3891 }
3892
3893 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3894 {
3895 struct irte_ga *ptr = (struct irte_ga *)table->table;
3896 struct irte_ga *irte = &ptr[index];
3897
3898 return irte->hi.fields.vector != 0;
3899 }
3900
3901 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3902 {
3903 table->table[index] = 0;
3904 }
3905
3906 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3907 {
3908 struct irte_ga *ptr = (struct irte_ga *)table->table;
3909 struct irte_ga *irte = &ptr[index];
3910
3911 memset(&irte->lo.val, 0, sizeof(u64));
3912 memset(&irte->hi.val, 0, sizeof(u64));
3913 }
3914
3915 static int get_devid(struct irq_alloc_info *info)
3916 {
3917 int devid = -1;
3918
3919 switch (info->type) {
3920 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3921 devid = get_ioapic_devid(info->ioapic_id);
3922 break;
3923 case X86_IRQ_ALLOC_TYPE_HPET:
3924 devid = get_hpet_devid(info->hpet_id);
3925 break;
3926 case X86_IRQ_ALLOC_TYPE_MSI:
3927 case X86_IRQ_ALLOC_TYPE_MSIX:
3928 devid = get_device_id(&info->msi_dev->dev);
3929 break;
3930 default:
3931 BUG_ON(1);
3932 break;
3933 }
3934
3935 return devid;
3936 }
3937
3938 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3939 {
3940 struct amd_iommu *iommu;
3941 int devid;
3942
3943 if (!info)
3944 return NULL;
3945
3946 devid = get_devid(info);
3947 if (devid >= 0) {
3948 iommu = amd_iommu_rlookup_table[devid];
3949 if (iommu)
3950 return iommu->ir_domain;
3951 }
3952
3953 return NULL;
3954 }
3955
3956 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3957 {
3958 struct amd_iommu *iommu;
3959 int devid;
3960
3961 if (!info)
3962 return NULL;
3963
3964 switch (info->type) {
3965 case X86_IRQ_ALLOC_TYPE_MSI:
3966 case X86_IRQ_ALLOC_TYPE_MSIX:
3967 devid = get_device_id(&info->msi_dev->dev);
3968 if (devid < 0)
3969 return NULL;
3970
3971 iommu = amd_iommu_rlookup_table[devid];
3972 if (iommu)
3973 return iommu->msi_domain;
3974 break;
3975 default:
3976 break;
3977 }
3978
3979 return NULL;
3980 }
3981
3982 struct irq_remap_ops amd_iommu_irq_ops = {
3983 .prepare = amd_iommu_prepare,
3984 .enable = amd_iommu_enable,
3985 .disable = amd_iommu_disable,
3986 .reenable = amd_iommu_reenable,
3987 .enable_faulting = amd_iommu_enable_faulting,
3988 .get_ir_irq_domain = get_ir_irq_domain,
3989 .get_irq_domain = get_irq_domain,
3990 };
3991
3992 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3993 struct irq_cfg *irq_cfg,
3994 struct irq_alloc_info *info,
3995 int devid, int index, int sub_handle)
3996 {
3997 struct irq_2_irte *irte_info = &data->irq_2_irte;
3998 struct msi_msg *msg = &data->msi_entry;
3999 struct IO_APIC_route_entry *entry;
4000 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4001
4002 if (!iommu)
4003 return;
4004
4005 data->irq_2_irte.devid = devid;
4006 data->irq_2_irte.index = index + sub_handle;
4007 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4008 apic->irq_dest_mode, irq_cfg->vector,
4009 irq_cfg->dest_apicid, devid);
4010
4011 switch (info->type) {
4012 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4013 /* Setup IOAPIC entry */
4014 entry = info->ioapic_entry;
4015 info->ioapic_entry = NULL;
4016 memset(entry, 0, sizeof(*entry));
4017 entry->vector = index;
4018 entry->mask = 0;
4019 entry->trigger = info->ioapic_trigger;
4020 entry->polarity = info->ioapic_polarity;
4021 /* Mask level triggered irqs. */
4022 if (info->ioapic_trigger)
4023 entry->mask = 1;
4024 break;
4025
4026 case X86_IRQ_ALLOC_TYPE_HPET:
4027 case X86_IRQ_ALLOC_TYPE_MSI:
4028 case X86_IRQ_ALLOC_TYPE_MSIX:
4029 msg->address_hi = MSI_ADDR_BASE_HI;
4030 msg->address_lo = MSI_ADDR_BASE_LO;
4031 msg->data = irte_info->index;
4032 break;
4033
4034 default:
4035 BUG_ON(1);
4036 break;
4037 }
4038 }
4039
4040 struct amd_irte_ops irte_32_ops = {
4041 .prepare = irte_prepare,
4042 .activate = irte_activate,
4043 .deactivate = irte_deactivate,
4044 .set_affinity = irte_set_affinity,
4045 .set_allocated = irte_set_allocated,
4046 .is_allocated = irte_is_allocated,
4047 .clear_allocated = irte_clear_allocated,
4048 };
4049
4050 struct amd_irte_ops irte_128_ops = {
4051 .prepare = irte_ga_prepare,
4052 .activate = irte_ga_activate,
4053 .deactivate = irte_ga_deactivate,
4054 .set_affinity = irte_ga_set_affinity,
4055 .set_allocated = irte_ga_set_allocated,
4056 .is_allocated = irte_ga_is_allocated,
4057 .clear_allocated = irte_ga_clear_allocated,
4058 };
4059
4060 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4061 unsigned int nr_irqs, void *arg)
4062 {
4063 struct irq_alloc_info *info = arg;
4064 struct irq_data *irq_data;
4065 struct amd_ir_data *data = NULL;
4066 struct irq_cfg *cfg;
4067 int i, ret, devid;
4068 int index = -1;
4069
4070 if (!info)
4071 return -EINVAL;
4072 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4073 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4074 return -EINVAL;
4075
4076 /*
4077 * With IRQ remapping enabled, don't need contiguous CPU vectors
4078 * to support multiple MSI interrupts.
4079 */
4080 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4081 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4082
4083 devid = get_devid(info);
4084 if (devid < 0)
4085 return -EINVAL;
4086
4087 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4088 if (ret < 0)
4089 return ret;
4090
4091 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4092 if (get_irq_table(devid, true))
4093 index = info->ioapic_pin;
4094 else
4095 ret = -ENOMEM;
4096 } else {
4097 index = alloc_irq_index(devid, nr_irqs);
4098 }
4099 if (index < 0) {
4100 pr_warn("Failed to allocate IRTE\n");
4101 ret = index;
4102 goto out_free_parent;
4103 }
4104
4105 for (i = 0; i < nr_irqs; i++) {
4106 irq_data = irq_domain_get_irq_data(domain, virq + i);
4107 cfg = irqd_cfg(irq_data);
4108 if (!irq_data || !cfg) {
4109 ret = -EINVAL;
4110 goto out_free_data;
4111 }
4112
4113 ret = -ENOMEM;
4114 data = kzalloc(sizeof(*data), GFP_KERNEL);
4115 if (!data)
4116 goto out_free_data;
4117
4118 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4119 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4120 else
4121 data->entry = kzalloc(sizeof(struct irte_ga),
4122 GFP_KERNEL);
4123 if (!data->entry) {
4124 kfree(data);
4125 goto out_free_data;
4126 }
4127
4128 irq_data->hwirq = (devid << 16) + i;
4129 irq_data->chip_data = data;
4130 irq_data->chip = &amd_ir_chip;
4131 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4132 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4133 }
4134
4135 return 0;
4136
4137 out_free_data:
4138 for (i--; i >= 0; i--) {
4139 irq_data = irq_domain_get_irq_data(domain, virq + i);
4140 if (irq_data)
4141 kfree(irq_data->chip_data);
4142 }
4143 for (i = 0; i < nr_irqs; i++)
4144 free_irte(devid, index + i);
4145 out_free_parent:
4146 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4147 return ret;
4148 }
4149
4150 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4151 unsigned int nr_irqs)
4152 {
4153 struct irq_2_irte *irte_info;
4154 struct irq_data *irq_data;
4155 struct amd_ir_data *data;
4156 int i;
4157
4158 for (i = 0; i < nr_irqs; i++) {
4159 irq_data = irq_domain_get_irq_data(domain, virq + i);
4160 if (irq_data && irq_data->chip_data) {
4161 data = irq_data->chip_data;
4162 irte_info = &data->irq_2_irte;
4163 free_irte(irte_info->devid, irte_info->index);
4164 kfree(data->entry);
4165 kfree(data);
4166 }
4167 }
4168 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4169 }
4170
4171 static void irq_remapping_activate(struct irq_domain *domain,
4172 struct irq_data *irq_data)
4173 {
4174 struct amd_ir_data *data = irq_data->chip_data;
4175 struct irq_2_irte *irte_info = &data->irq_2_irte;
4176 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4177
4178 if (iommu)
4179 iommu->irte_ops->activate(data->entry, irte_info->devid,
4180 irte_info->index);
4181 }
4182
4183 static void irq_remapping_deactivate(struct irq_domain *domain,
4184 struct irq_data *irq_data)
4185 {
4186 struct amd_ir_data *data = irq_data->chip_data;
4187 struct irq_2_irte *irte_info = &data->irq_2_irte;
4188 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4189
4190 if (iommu)
4191 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4192 irte_info->index);
4193 }
4194
4195 static const struct irq_domain_ops amd_ir_domain_ops = {
4196 .alloc = irq_remapping_alloc,
4197 .free = irq_remapping_free,
4198 .activate = irq_remapping_activate,
4199 .deactivate = irq_remapping_deactivate,
4200 };
4201
4202 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4203 {
4204 struct amd_iommu *iommu;
4205 struct amd_iommu_pi_data *pi_data = vcpu_info;
4206 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4207 struct amd_ir_data *ir_data = data->chip_data;
4208 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4209 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4210 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4211
4212 /* Note:
4213 * This device has never been set up for guest mode.
4214 * we should not modify the IRTE
4215 */
4216 if (!dev_data || !dev_data->use_vapic)
4217 return 0;
4218
4219 pi_data->ir_data = ir_data;
4220
4221 /* Note:
4222 * SVM tries to set up for VAPIC mode, but we are in
4223 * legacy mode. So, we force legacy mode instead.
4224 */
4225 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4226 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4227 __func__);
4228 pi_data->is_guest_mode = false;
4229 }
4230
4231 iommu = amd_iommu_rlookup_table[irte_info->devid];
4232 if (iommu == NULL)
4233 return -EINVAL;
4234
4235 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4236 if (pi_data->is_guest_mode) {
4237 /* Setting */
4238 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4239 irte->hi.fields.vector = vcpu_pi_info->vector;
4240 irte->lo.fields_vapic.ga_log_intr = 1;
4241 irte->lo.fields_vapic.guest_mode = 1;
4242 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4243
4244 ir_data->cached_ga_tag = pi_data->ga_tag;
4245 } else {
4246 /* Un-Setting */
4247 struct irq_cfg *cfg = irqd_cfg(data);
4248
4249 irte->hi.val = 0;
4250 irte->lo.val = 0;
4251 irte->hi.fields.vector = cfg->vector;
4252 irte->lo.fields_remap.guest_mode = 0;
4253 irte->lo.fields_remap.destination = cfg->dest_apicid;
4254 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4255 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4256
4257 /*
4258 * This communicates the ga_tag back to the caller
4259 * so that it can do all the necessary clean up.
4260 */
4261 ir_data->cached_ga_tag = 0;
4262 }
4263
4264 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4265 }
4266
4267 static int amd_ir_set_affinity(struct irq_data *data,
4268 const struct cpumask *mask, bool force)
4269 {
4270 struct amd_ir_data *ir_data = data->chip_data;
4271 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4272 struct irq_cfg *cfg = irqd_cfg(data);
4273 struct irq_data *parent = data->parent_data;
4274 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4275 int ret;
4276
4277 if (!iommu)
4278 return -ENODEV;
4279
4280 ret = parent->chip->irq_set_affinity(parent, mask, force);
4281 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4282 return ret;
4283
4284 /*
4285 * Atomically updates the IRTE with the new destination, vector
4286 * and flushes the interrupt entry cache.
4287 */
4288 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4289 irte_info->index, cfg->vector, cfg->dest_apicid);
4290
4291 /*
4292 * After this point, all the interrupts will start arriving
4293 * at the new destination. So, time to cleanup the previous
4294 * vector allocation.
4295 */
4296 send_cleanup_vector(cfg);
4297
4298 return IRQ_SET_MASK_OK_DONE;
4299 }
4300
4301 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4302 {
4303 struct amd_ir_data *ir_data = irq_data->chip_data;
4304
4305 *msg = ir_data->msi_entry;
4306 }
4307
4308 static struct irq_chip amd_ir_chip = {
4309 .name = "AMD-IR",
4310 .irq_ack = ir_ack_apic_edge,
4311 .irq_set_affinity = amd_ir_set_affinity,
4312 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4313 .irq_compose_msi_msg = ir_compose_msi_msg,
4314 };
4315
4316 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4317 {
4318 struct fwnode_handle *fn;
4319
4320 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4321 if (!fn)
4322 return -ENOMEM;
4323 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4324 irq_domain_free_fwnode(fn);
4325 if (!iommu->ir_domain)
4326 return -ENOMEM;
4327
4328 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4329 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4330 "AMD-IR-MSI",
4331 iommu->index);
4332 return 0;
4333 }
4334
4335 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4336 {
4337 unsigned long flags;
4338 struct amd_iommu *iommu;
4339 struct irq_remap_table *irt;
4340 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4341 int devid = ir_data->irq_2_irte.devid;
4342 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4343 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4344
4345 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4346 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4347 return 0;
4348
4349 iommu = amd_iommu_rlookup_table[devid];
4350 if (!iommu)
4351 return -ENODEV;
4352
4353 irt = get_irq_table(devid, false);
4354 if (!irt)
4355 return -ENODEV;
4356
4357 spin_lock_irqsave(&irt->lock, flags);
4358
4359 if (ref->lo.fields_vapic.guest_mode) {
4360 if (cpu >= 0)
4361 ref->lo.fields_vapic.destination = cpu;
4362 ref->lo.fields_vapic.is_run = is_run;
4363 barrier();
4364 }
4365
4366 spin_unlock_irqrestore(&irt->lock, flags);
4367
4368 iommu_flush_irt(iommu, devid);
4369 iommu_completion_wait(iommu);
4370 return 0;
4371 }
4372 EXPORT_SYMBOL(amd_iommu_update_ga);
4373 #endif
ubuntu-bionic-kernel mirror