2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define AMD_IOMMU_MAPPING_ERROR 0
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61 #define LOOP_TIMEOUT 100000
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
86 /* List of all available dev_data structures */
87 static LIST_HEAD(dev_data_list
);
88 static DEFINE_SPINLOCK(dev_data_list_lock
);
90 LIST_HEAD(ioapic_map
);
92 LIST_HEAD(acpihid_map
);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops
;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
101 int amd_iommu_max_glx_val
= -1;
103 static const struct dma_map_ops amd_iommu_dma_ops
;
106 * This struct contains device specific data for the IOMMU
108 struct iommu_dev_data
{
109 struct list_head list
; /* For domain->dev_list */
110 struct list_head dev_data_list
; /* For global dev_data_list */
111 struct protection_domain
*domain
; /* Domain the device is bound to */
112 u16 devid
; /* PCI Device ID */
113 u16 alias
; /* Alias Device ID */
114 bool iommu_v2
; /* Device can make use of IOMMUv2 */
115 bool passthrough
; /* Device is identity mapped */
119 } ats
; /* ATS state */
120 bool pri_tlp
; /* PASID TLB required for
122 u32 errata
; /* Bitmap for errata to apply */
123 bool use_vapic
; /* Enable device to use vapic mode */
125 struct ratelimit_state rs
; /* Ratelimit IOPF messages */
129 * general struct to manage commands send to an IOMMU
135 struct kmem_cache
*amd_iommu_irq_cache
;
137 static void update_domain(struct protection_domain
*domain
);
138 static int protection_domain_init(struct protection_domain
*domain
);
139 static void detach_device(struct device
*dev
);
141 #define FLUSH_QUEUE_SIZE 256
143 struct flush_queue_entry
{
144 unsigned long iova_pfn
;
146 u64 counter
; /* Flush counter when this entry was added to the queue */
150 struct flush_queue_entry
*entries
;
156 * Data container for a dma_ops specific protection domain
158 struct dma_ops_domain
{
159 /* generic protection domain information */
160 struct protection_domain domain
;
163 struct iova_domain iovad
;
165 struct flush_queue __percpu
*flush_queue
;
168 * We need two counter here to be race-free wrt. IOTLB flushing and
169 * adding entries to the flush queue.
171 * The flush_start_cnt is incremented _before_ the IOTLB flush starts.
172 * New entries added to the flush ring-buffer get their 'counter' value
173 * from here. This way we can make sure that entries added to the queue
174 * (or other per-cpu queues of the same domain) while the TLB is about
175 * to be flushed are not considered to be flushed already.
177 atomic64_t flush_start_cnt
;
180 * The flush_finish_cnt is incremented when an IOTLB flush is complete.
181 * This value is always smaller than flush_start_cnt. The queue_add
182 * function frees all IOVAs that have a counter value smaller than
183 * flush_finish_cnt. This makes sure that we only free IOVAs that are
184 * flushed out of the IOTLB of the domain.
186 atomic64_t flush_finish_cnt
;
189 * Timer to make sure we don't keep IOVAs around unflushed
192 struct timer_list flush_timer
;
193 atomic_t flush_timer_on
;
196 static struct iova_domain reserved_iova_ranges
;
197 static struct lock_class_key reserved_rbtree_key
;
199 /****************************************************************************
203 ****************************************************************************/
205 static inline int match_hid_uid(struct device
*dev
,
206 struct acpihid_map_entry
*entry
)
208 const char *hid
, *uid
;
210 hid
= acpi_device_hid(ACPI_COMPANION(dev
));
211 uid
= acpi_device_uid(ACPI_COMPANION(dev
));
217 return strcmp(hid
, entry
->hid
);
220 return strcmp(hid
, entry
->hid
);
222 return (strcmp(hid
, entry
->hid
) || strcmp(uid
, entry
->uid
));
225 static inline u16
get_pci_device_id(struct device
*dev
)
227 struct pci_dev
*pdev
= to_pci_dev(dev
);
229 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
232 static inline int get_acpihid_device_id(struct device
*dev
,
233 struct acpihid_map_entry
**entry
)
235 struct acpihid_map_entry
*p
;
237 list_for_each_entry(p
, &acpihid_map
, list
) {
238 if (!match_hid_uid(dev
, p
)) {
247 static inline int get_device_id(struct device
*dev
)
252 devid
= get_pci_device_id(dev
);
254 devid
= get_acpihid_device_id(dev
, NULL
);
259 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
261 return container_of(dom
, struct protection_domain
, domain
);
264 static struct dma_ops_domain
* to_dma_ops_domain(struct protection_domain
*domain
)
266 BUG_ON(domain
->flags
!= PD_DMA_OPS_MASK
);
267 return container_of(domain
, struct dma_ops_domain
, domain
);
270 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
272 struct iommu_dev_data
*dev_data
;
275 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
279 dev_data
->devid
= devid
;
281 spin_lock_irqsave(&dev_data_list_lock
, flags
);
282 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
283 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
285 ratelimit_default_init(&dev_data
->rs
);
290 static struct iommu_dev_data
*search_dev_data(u16 devid
)
292 struct iommu_dev_data
*dev_data
;
295 spin_lock_irqsave(&dev_data_list_lock
, flags
);
296 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
297 if (dev_data
->devid
== devid
)
304 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
309 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
311 *(u16
*)data
= alias
;
315 static u16
get_alias(struct device
*dev
)
317 struct pci_dev
*pdev
= to_pci_dev(dev
);
318 u16 devid
, ivrs_alias
, pci_alias
;
320 /* The callers make sure that get_device_id() does not fail here */
321 devid
= get_device_id(dev
);
322 ivrs_alias
= amd_iommu_alias_table
[devid
];
323 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
325 if (ivrs_alias
== pci_alias
)
331 * The IVRS is fairly reliable in telling us about aliases, but it
332 * can't know about every screwy device. If we don't have an IVRS
333 * reported alias, use the PCI reported alias. In that case we may
334 * still need to initialize the rlookup and dev_table entries if the
335 * alias is to a non-existent device.
337 if (ivrs_alias
== devid
) {
338 if (!amd_iommu_rlookup_table
[pci_alias
]) {
339 amd_iommu_rlookup_table
[pci_alias
] =
340 amd_iommu_rlookup_table
[devid
];
341 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
342 amd_iommu_dev_table
[devid
].data
,
343 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
349 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
350 "for device %s[%04x:%04x], kernel reported alias "
351 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
352 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
353 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
354 PCI_FUNC(pci_alias
));
357 * If we don't have a PCI DMA alias and the IVRS alias is on the same
358 * bus, then the IVRS table may know about a quirk that we don't.
360 if (pci_alias
== devid
&&
361 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
362 pci_add_dma_alias(pdev
, ivrs_alias
& 0xff);
363 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
364 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
371 static struct iommu_dev_data
*find_dev_data(u16 devid
)
373 struct iommu_dev_data
*dev_data
;
375 dev_data
= search_dev_data(devid
);
377 if (dev_data
== NULL
)
378 dev_data
= alloc_dev_data(devid
);
383 static struct iommu_dev_data
*get_dev_data(struct device
*dev
)
385 return dev
->archdata
.iommu
;
389 * Find or create an IOMMU group for a acpihid device.
391 static struct iommu_group
*acpihid_device_group(struct device
*dev
)
393 struct acpihid_map_entry
*p
, *entry
= NULL
;
396 devid
= get_acpihid_device_id(dev
, &entry
);
398 return ERR_PTR(devid
);
400 list_for_each_entry(p
, &acpihid_map
, list
) {
401 if ((devid
== p
->devid
) && p
->group
)
402 entry
->group
= p
->group
;
406 entry
->group
= generic_device_group(dev
);
408 iommu_group_ref_get(entry
->group
);
413 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
415 static const int caps
[] = {
418 PCI_EXT_CAP_ID_PASID
,
422 for (i
= 0; i
< 3; ++i
) {
423 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
431 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
433 struct iommu_dev_data
*dev_data
;
435 dev_data
= get_dev_data(&pdev
->dev
);
437 return dev_data
->errata
& (1 << erratum
) ? true : false;
441 * This function checks if the driver got a valid device from the caller to
442 * avoid dereferencing invalid pointers.
444 static bool check_device(struct device
*dev
)
448 if (!dev
|| !dev
->dma_mask
)
451 devid
= get_device_id(dev
);
455 /* Out of our scope? */
456 if (devid
> amd_iommu_last_bdf
)
459 if (amd_iommu_rlookup_table
[devid
] == NULL
)
465 static void init_iommu_group(struct device
*dev
)
467 struct iommu_group
*group
;
469 group
= iommu_group_get_for_dev(dev
);
473 iommu_group_put(group
);
476 static int iommu_init_device(struct device
*dev
)
478 struct iommu_dev_data
*dev_data
;
479 struct amd_iommu
*iommu
;
482 if (dev
->archdata
.iommu
)
485 devid
= get_device_id(dev
);
489 iommu
= amd_iommu_rlookup_table
[devid
];
491 dev_data
= find_dev_data(devid
);
495 dev_data
->alias
= get_alias(dev
);
497 if (dev_is_pci(dev
) && pci_iommuv2_capable(to_pci_dev(dev
))) {
498 struct amd_iommu
*iommu
;
500 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
501 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
504 dev
->archdata
.iommu
= dev_data
;
506 iommu_device_link(&iommu
->iommu
, dev
);
511 static void iommu_ignore_device(struct device
*dev
)
516 devid
= get_device_id(dev
);
520 alias
= get_alias(dev
);
522 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
523 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
525 amd_iommu_rlookup_table
[devid
] = NULL
;
526 amd_iommu_rlookup_table
[alias
] = NULL
;
529 static void iommu_uninit_device(struct device
*dev
)
531 struct iommu_dev_data
*dev_data
;
532 struct amd_iommu
*iommu
;
535 devid
= get_device_id(dev
);
539 iommu
= amd_iommu_rlookup_table
[devid
];
541 dev_data
= search_dev_data(devid
);
545 if (dev_data
->domain
)
548 iommu_device_unlink(&iommu
->iommu
, dev
);
550 iommu_group_remove_device(dev
);
556 * We keep dev_data around for unplugged devices and reuse it when the
557 * device is re-plugged - not doing so would introduce a ton of races.
561 /****************************************************************************
563 * Interrupt handling functions
565 ****************************************************************************/
567 static void dump_dte_entry(u16 devid
)
571 for (i
= 0; i
< 4; ++i
)
572 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
573 amd_iommu_dev_table
[devid
].data
[i
]);
576 static void dump_command(unsigned long phys_addr
)
578 struct iommu_cmd
*cmd
= phys_to_virt(phys_addr
);
581 for (i
= 0; i
< 4; ++i
)
582 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
585 static void amd_iommu_report_page_fault(u16 devid
, u16 domain_id
,
586 u64 address
, int flags
)
588 struct iommu_dev_data
*dev_data
= NULL
;
589 struct pci_dev
*pdev
;
591 pdev
= pci_get_bus_and_slot(PCI_BUS_NUM(devid
), devid
& 0xff);
593 dev_data
= get_dev_data(&pdev
->dev
);
595 if (dev_data
&& __ratelimit(&dev_data
->rs
)) {
596 dev_err(&pdev
->dev
, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
597 domain_id
, address
, flags
);
598 } else if (printk_ratelimit()) {
599 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
601 domain_id
, address
, flags
);
608 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
610 int type
, devid
, domid
, flags
;
611 volatile u32
*event
= __evt
;
616 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
617 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
618 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
619 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
620 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
623 /* Did we hit the erratum? */
624 if (++count
== LOOP_TIMEOUT
) {
625 pr_err("AMD-Vi: No event written to event log\n");
632 if (type
== EVENT_TYPE_IO_FAULT
) {
633 amd_iommu_report_page_fault(devid
, domid
, address
, flags
);
636 printk(KERN_ERR
"AMD-Vi: Event logged [");
640 case EVENT_TYPE_ILL_DEV
:
641 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
642 "address=0x%016llx flags=0x%04x]\n",
643 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
645 dump_dte_entry(devid
);
647 case EVENT_TYPE_DEV_TAB_ERR
:
648 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
649 "address=0x%016llx flags=0x%04x]\n",
650 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
653 case EVENT_TYPE_PAGE_TAB_ERR
:
654 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
655 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
656 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
657 domid
, address
, flags
);
659 case EVENT_TYPE_ILL_CMD
:
660 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
661 dump_command(address
);
663 case EVENT_TYPE_CMD_HARD_ERR
:
664 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
665 "flags=0x%04x]\n", address
, flags
);
667 case EVENT_TYPE_IOTLB_INV_TO
:
668 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
669 "address=0x%016llx]\n",
670 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
673 case EVENT_TYPE_INV_DEV_REQ
:
674 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
675 "address=0x%016llx flags=0x%04x]\n",
676 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
680 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
683 memset(__evt
, 0, 4 * sizeof(u32
));
686 static void iommu_poll_events(struct amd_iommu
*iommu
)
690 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
691 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
693 while (head
!= tail
) {
694 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
695 head
= (head
+ EVENT_ENTRY_SIZE
) % EVT_BUFFER_SIZE
;
698 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
701 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
703 struct amd_iommu_fault fault
;
705 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
706 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
710 fault
.address
= raw
[1];
711 fault
.pasid
= PPR_PASID(raw
[0]);
712 fault
.device_id
= PPR_DEVID(raw
[0]);
713 fault
.tag
= PPR_TAG(raw
[0]);
714 fault
.flags
= PPR_FLAGS(raw
[0]);
716 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
719 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
723 if (iommu
->ppr_log
== NULL
)
726 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
727 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
729 while (head
!= tail
) {
734 raw
= (u64
*)(iommu
->ppr_log
+ head
);
737 * Hardware bug: Interrupt may arrive before the entry is
738 * written to memory. If this happens we need to wait for the
741 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
742 if (PPR_REQ_TYPE(raw
[0]) != 0)
747 /* Avoid memcpy function-call overhead */
752 * To detect the hardware bug we need to clear the entry
755 raw
[0] = raw
[1] = 0UL;
757 /* Update head pointer of hardware ring-buffer */
758 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
759 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
761 /* Handle PPR entry */
762 iommu_handle_ppr_entry(iommu
, entry
);
764 /* Refresh ring-buffer information */
765 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
766 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
770 #ifdef CONFIG_IRQ_REMAP
771 static int (*iommu_ga_log_notifier
)(u32
);
773 int amd_iommu_register_ga_log_notifier(int (*notifier
)(u32
))
775 iommu_ga_log_notifier
= notifier
;
779 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier
);
781 static void iommu_poll_ga_log(struct amd_iommu
*iommu
)
783 u32 head
, tail
, cnt
= 0;
785 if (iommu
->ga_log
== NULL
)
788 head
= readl(iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
789 tail
= readl(iommu
->mmio_base
+ MMIO_GA_TAIL_OFFSET
);
791 while (head
!= tail
) {
795 raw
= (u64
*)(iommu
->ga_log
+ head
);
798 /* Avoid memcpy function-call overhead */
801 /* Update head pointer of hardware ring-buffer */
802 head
= (head
+ GA_ENTRY_SIZE
) % GA_LOG_SIZE
;
803 writel(head
, iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
805 /* Handle GA entry */
806 switch (GA_REQ_TYPE(log_entry
)) {
808 if (!iommu_ga_log_notifier
)
811 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
812 __func__
, GA_DEVID(log_entry
),
815 if (iommu_ga_log_notifier(GA_TAG(log_entry
)) != 0)
816 pr_err("AMD-Vi: GA log notifier failed.\n");
823 #endif /* CONFIG_IRQ_REMAP */
825 #define AMD_IOMMU_INT_MASK \
826 (MMIO_STATUS_EVT_INT_MASK | \
827 MMIO_STATUS_PPR_INT_MASK | \
828 MMIO_STATUS_GALOG_INT_MASK)
830 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
832 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
833 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
835 while (status
& AMD_IOMMU_INT_MASK
) {
836 /* Enable EVT and PPR and GA interrupts again */
837 writel(AMD_IOMMU_INT_MASK
,
838 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
840 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
841 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
842 iommu_poll_events(iommu
);
845 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
846 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
847 iommu_poll_ppr_log(iommu
);
850 #ifdef CONFIG_IRQ_REMAP
851 if (status
& MMIO_STATUS_GALOG_INT_MASK
) {
852 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
853 iommu_poll_ga_log(iommu
);
858 * Hardware bug: ERBT1312
859 * When re-enabling interrupt (by writing 1
860 * to clear the bit), the hardware might also try to set
861 * the interrupt bit in the event status register.
862 * In this scenario, the bit will be set, and disable
863 * subsequent interrupts.
865 * Workaround: The IOMMU driver should read back the
866 * status register and check if the interrupt bits are cleared.
867 * If not, driver will need to go through the interrupt handler
868 * again and re-clear the bits
870 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
875 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
877 return IRQ_WAKE_THREAD
;
880 /****************************************************************************
882 * IOMMU command queuing functions
884 ****************************************************************************/
886 static int wait_on_sem(volatile u64
*sem
)
890 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
895 if (i
== LOOP_TIMEOUT
) {
896 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
903 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
904 struct iommu_cmd
*cmd
)
908 target
= iommu
->cmd_buf
+ iommu
->cmd_buf_tail
;
910 iommu
->cmd_buf_tail
+= sizeof(*cmd
);
911 iommu
->cmd_buf_tail
%= CMD_BUFFER_SIZE
;
913 /* Copy command to buffer */
914 memcpy(target
, cmd
, sizeof(*cmd
));
916 /* Tell the IOMMU about it */
917 writel(iommu
->cmd_buf_tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
920 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
922 WARN_ON(address
& 0x7ULL
);
924 memset(cmd
, 0, sizeof(*cmd
));
925 cmd
->data
[0] = lower_32_bits(__pa(address
)) | CMD_COMPL_WAIT_STORE_MASK
;
926 cmd
->data
[1] = upper_32_bits(__pa(address
));
928 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
931 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
933 memset(cmd
, 0, sizeof(*cmd
));
934 cmd
->data
[0] = devid
;
935 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
938 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
939 size_t size
, u16 domid
, int pde
)
944 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
949 * If we have to flush more than one page, flush all
950 * TLB entries for this domain
952 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
956 address
&= PAGE_MASK
;
958 memset(cmd
, 0, sizeof(*cmd
));
959 cmd
->data
[1] |= domid
;
960 cmd
->data
[2] = lower_32_bits(address
);
961 cmd
->data
[3] = upper_32_bits(address
);
962 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
963 if (s
) /* size bit - we flush more than one 4kb page */
964 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
965 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
966 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
969 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
970 u64 address
, size_t size
)
975 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
980 * If we have to flush more than one page, flush all
981 * TLB entries for this domain
983 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
987 address
&= PAGE_MASK
;
989 memset(cmd
, 0, sizeof(*cmd
));
990 cmd
->data
[0] = devid
;
991 cmd
->data
[0] |= (qdep
& 0xff) << 24;
992 cmd
->data
[1] = devid
;
993 cmd
->data
[2] = lower_32_bits(address
);
994 cmd
->data
[3] = upper_32_bits(address
);
995 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
997 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
1000 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
1001 u64 address
, bool size
)
1003 memset(cmd
, 0, sizeof(*cmd
));
1005 address
&= ~(0xfffULL
);
1007 cmd
->data
[0] = pasid
;
1008 cmd
->data
[1] = domid
;
1009 cmd
->data
[2] = lower_32_bits(address
);
1010 cmd
->data
[3] = upper_32_bits(address
);
1011 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
1012 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
1014 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
1015 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
1018 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
1019 int qdep
, u64 address
, bool size
)
1021 memset(cmd
, 0, sizeof(*cmd
));
1023 address
&= ~(0xfffULL
);
1025 cmd
->data
[0] = devid
;
1026 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
1027 cmd
->data
[0] |= (qdep
& 0xff) << 24;
1028 cmd
->data
[1] = devid
;
1029 cmd
->data
[1] |= (pasid
& 0xff) << 16;
1030 cmd
->data
[2] = lower_32_bits(address
);
1031 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
1032 cmd
->data
[3] = upper_32_bits(address
);
1034 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
1035 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
1038 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
1039 int status
, int tag
, bool gn
)
1041 memset(cmd
, 0, sizeof(*cmd
));
1043 cmd
->data
[0] = devid
;
1045 cmd
->data
[1] = pasid
;
1046 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
1048 cmd
->data
[3] = tag
& 0x1ff;
1049 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
1051 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
1054 static void build_inv_all(struct iommu_cmd
*cmd
)
1056 memset(cmd
, 0, sizeof(*cmd
));
1057 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
1060 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
1062 memset(cmd
, 0, sizeof(*cmd
));
1063 cmd
->data
[0] = devid
;
1064 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
1068 * Writes the command to the IOMMUs command buffer and informs the
1069 * hardware about the new command.
1071 static int __iommu_queue_command_sync(struct amd_iommu
*iommu
,
1072 struct iommu_cmd
*cmd
,
1075 unsigned int count
= 0;
1076 u32 left
, next_tail
;
1078 next_tail
= (iommu
->cmd_buf_tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
1080 left
= (iommu
->cmd_buf_head
- next_tail
) % CMD_BUFFER_SIZE
;
1083 /* Skip udelay() the first time around */
1085 if (count
== LOOP_TIMEOUT
) {
1086 pr_err("AMD-Vi: Command buffer timeout\n");
1093 /* Update head and recheck remaining space */
1094 iommu
->cmd_buf_head
= readl(iommu
->mmio_base
+
1095 MMIO_CMD_HEAD_OFFSET
);
1100 copy_cmd_to_buffer(iommu
, cmd
);
1102 /* Do we need to make sure all commands are processed? */
1103 iommu
->need_sync
= sync
;
1108 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
1109 struct iommu_cmd
*cmd
,
1112 unsigned long flags
;
1115 spin_lock_irqsave(&iommu
->lock
, flags
);
1116 ret
= __iommu_queue_command_sync(iommu
, cmd
, sync
);
1117 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1122 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1124 return iommu_queue_command_sync(iommu
, cmd
, true);
1128 * This function queues a completion wait command into the command
1129 * buffer of an IOMMU
1131 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1133 struct iommu_cmd cmd
;
1134 unsigned long flags
;
1137 if (!iommu
->need_sync
)
1141 build_completion_wait(&cmd
, (u64
)&iommu
->cmd_sem
);
1143 spin_lock_irqsave(&iommu
->lock
, flags
);
1147 ret
= __iommu_queue_command_sync(iommu
, &cmd
, false);
1151 ret
= wait_on_sem(&iommu
->cmd_sem
);
1154 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1159 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1161 struct iommu_cmd cmd
;
1163 build_inv_dte(&cmd
, devid
);
1165 return iommu_queue_command(iommu
, &cmd
);
1168 static void iommu_flush_dte_all(struct amd_iommu
*iommu
)
1172 for (devid
= 0; devid
<= 0xffff; ++devid
)
1173 iommu_flush_dte(iommu
, devid
);
1175 iommu_completion_wait(iommu
);
1179 * This function uses heavy locking and may disable irqs for some time. But
1180 * this is no issue because it is only called during resume.
1182 static void iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1186 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1187 struct iommu_cmd cmd
;
1188 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1190 iommu_queue_command(iommu
, &cmd
);
1193 iommu_completion_wait(iommu
);
1196 static void iommu_flush_all(struct amd_iommu
*iommu
)
1198 struct iommu_cmd cmd
;
1200 build_inv_all(&cmd
);
1202 iommu_queue_command(iommu
, &cmd
);
1203 iommu_completion_wait(iommu
);
1206 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1208 struct iommu_cmd cmd
;
1210 build_inv_irt(&cmd
, devid
);
1212 iommu_queue_command(iommu
, &cmd
);
1215 static void iommu_flush_irt_all(struct amd_iommu
*iommu
)
1219 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1220 iommu_flush_irt(iommu
, devid
);
1222 iommu_completion_wait(iommu
);
1225 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1227 if (iommu_feature(iommu
, FEATURE_IA
)) {
1228 iommu_flush_all(iommu
);
1230 iommu_flush_dte_all(iommu
);
1231 iommu_flush_irt_all(iommu
);
1232 iommu_flush_tlb_all(iommu
);
1237 * Command send function for flushing on-device TLB
1239 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1240 u64 address
, size_t size
)
1242 struct amd_iommu
*iommu
;
1243 struct iommu_cmd cmd
;
1246 qdep
= dev_data
->ats
.qdep
;
1247 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1249 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1251 return iommu_queue_command(iommu
, &cmd
);
1255 * Command send function for invalidating a device table entry
1257 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1259 struct amd_iommu
*iommu
;
1263 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1264 alias
= dev_data
->alias
;
1266 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1267 if (!ret
&& alias
!= dev_data
->devid
)
1268 ret
= iommu_flush_dte(iommu
, alias
);
1272 if (dev_data
->ats
.enabled
)
1273 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1279 * TLB invalidation function which is called from the mapping functions.
1280 * It invalidates a single PTE if the range to flush is within a single
1281 * page. Otherwise it flushes the whole TLB of the IOMMU.
1283 static void __domain_flush_pages(struct protection_domain
*domain
,
1284 u64 address
, size_t size
, int pde
)
1286 struct iommu_dev_data
*dev_data
;
1287 struct iommu_cmd cmd
;
1290 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1292 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1293 if (!domain
->dev_iommu
[i
])
1297 * Devices of this domain are behind this IOMMU
1298 * We need a TLB flush
1300 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1303 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1305 if (!dev_data
->ats
.enabled
)
1308 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1314 static void domain_flush_pages(struct protection_domain
*domain
,
1315 u64 address
, size_t size
)
1317 __domain_flush_pages(domain
, address
, size
, 0);
1320 /* Flush the whole IO/TLB for a given protection domain */
1321 static void domain_flush_tlb(struct protection_domain
*domain
)
1323 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1326 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1327 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1329 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1332 static void domain_flush_complete(struct protection_domain
*domain
)
1336 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1337 if (domain
&& !domain
->dev_iommu
[i
])
1341 * Devices of this domain are behind this IOMMU
1342 * We need to wait for completion of all commands.
1344 iommu_completion_wait(amd_iommus
[i
]);
1350 * This function flushes the DTEs for all devices in domain
1352 static void domain_flush_devices(struct protection_domain
*domain
)
1354 struct iommu_dev_data
*dev_data
;
1356 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1357 device_flush_dte(dev_data
);
1360 /****************************************************************************
1362 * The functions below are used the create the page table mappings for
1363 * unity mapped regions.
1365 ****************************************************************************/
1368 * This function is used to add another level to an IO page table. Adding
1369 * another level increases the size of the address space by 9 bits to a size up
1372 static bool increase_address_space(struct protection_domain
*domain
,
1377 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1378 /* address space already 64 bit large */
1381 pte
= (void *)get_zeroed_page(gfp
);
1385 *pte
= PM_LEVEL_PDE(domain
->mode
,
1386 virt_to_phys(domain
->pt_root
));
1387 domain
->pt_root
= pte
;
1389 domain
->updated
= true;
1394 static u64
*alloc_pte(struct protection_domain
*domain
,
1395 unsigned long address
,
1396 unsigned long page_size
,
1403 BUG_ON(!is_power_of_2(page_size
));
1405 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1406 increase_address_space(domain
, gfp
);
1408 level
= domain
->mode
- 1;
1409 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1410 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1411 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1413 while (level
> end_lvl
) {
1418 if (!IOMMU_PTE_PRESENT(__pte
)) {
1419 page
= (u64
*)get_zeroed_page(gfp
);
1423 __npte
= PM_LEVEL_PDE(level
, virt_to_phys(page
));
1425 /* pte could have been changed somewhere. */
1426 if (cmpxchg64(pte
, __pte
, __npte
) != __pte
) {
1427 free_page((unsigned long)page
);
1432 /* No level skipping support yet */
1433 if (PM_PTE_LEVEL(*pte
) != level
)
1438 pte
= IOMMU_PTE_PAGE(*pte
);
1440 if (pte_page
&& level
== end_lvl
)
1443 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1450 * This function checks if there is a PTE for a given dma address. If
1451 * there is one, it returns the pointer to it.
1453 static u64
*fetch_pte(struct protection_domain
*domain
,
1454 unsigned long address
,
1455 unsigned long *page_size
)
1460 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1463 level
= domain
->mode
- 1;
1464 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1465 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1470 if (!IOMMU_PTE_PRESENT(*pte
))
1474 if (PM_PTE_LEVEL(*pte
) == 7 ||
1475 PM_PTE_LEVEL(*pte
) == 0)
1478 /* No level skipping support yet */
1479 if (PM_PTE_LEVEL(*pte
) != level
)
1484 /* Walk to the next level */
1485 pte
= IOMMU_PTE_PAGE(*pte
);
1486 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1487 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1490 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1491 unsigned long pte_mask
;
1494 * If we have a series of large PTEs, make
1495 * sure to return a pointer to the first one.
1497 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1498 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1499 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1506 * Generic mapping functions. It maps a physical address into a DMA
1507 * address space. It allocates the page table pages if necessary.
1508 * In the future it can be extended to a generic mapping function
1509 * supporting all features of AMD IOMMU page tables like level skipping
1510 * and full 64 bit address spaces.
1512 static int iommu_map_page(struct protection_domain
*dom
,
1513 unsigned long bus_addr
,
1514 unsigned long phys_addr
,
1515 unsigned long page_size
,
1522 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1523 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1525 if (!(prot
& IOMMU_PROT_MASK
))
1528 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1529 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, gfp
);
1534 for (i
= 0; i
< count
; ++i
)
1535 if (IOMMU_PTE_PRESENT(pte
[i
]))
1539 __pte
= PAGE_SIZE_PTE(phys_addr
, page_size
);
1540 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_P
| IOMMU_PTE_FC
;
1542 __pte
= phys_addr
| IOMMU_PTE_P
| IOMMU_PTE_FC
;
1544 if (prot
& IOMMU_PROT_IR
)
1545 __pte
|= IOMMU_PTE_IR
;
1546 if (prot
& IOMMU_PROT_IW
)
1547 __pte
|= IOMMU_PTE_IW
;
1549 for (i
= 0; i
< count
; ++i
)
1557 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1558 unsigned long bus_addr
,
1559 unsigned long page_size
)
1561 unsigned long long unmapped
;
1562 unsigned long unmap_size
;
1565 BUG_ON(!is_power_of_2(page_size
));
1569 while (unmapped
< page_size
) {
1571 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1576 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1577 for (i
= 0; i
< count
; i
++)
1581 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1582 unmapped
+= unmap_size
;
1585 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1590 /****************************************************************************
1592 * The next functions belong to the address allocator for the dma_ops
1593 * interface functions.
1595 ****************************************************************************/
1598 static unsigned long dma_ops_alloc_iova(struct device
*dev
,
1599 struct dma_ops_domain
*dma_dom
,
1600 unsigned int pages
, u64 dma_mask
)
1602 unsigned long pfn
= 0;
1604 pages
= __roundup_pow_of_two(pages
);
1606 if (dma_mask
> DMA_BIT_MASK(32))
1607 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1608 IOVA_PFN(DMA_BIT_MASK(32)));
1611 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
, IOVA_PFN(dma_mask
));
1613 return (pfn
<< PAGE_SHIFT
);
1616 static void dma_ops_free_iova(struct dma_ops_domain
*dma_dom
,
1617 unsigned long address
,
1620 pages
= __roundup_pow_of_two(pages
);
1621 address
>>= PAGE_SHIFT
;
1623 free_iova_fast(&dma_dom
->iovad
, address
, pages
);
1626 /****************************************************************************
1628 * The next functions belong to the domain allocation. A domain is
1629 * allocated for every IOMMU as the default domain. If device isolation
1630 * is enabled, every device get its own domain. The most important thing
1631 * about domains is the page table mapping the DMA address space they
1634 ****************************************************************************/
1637 * This function adds a protection domain to the global protection domain list
1639 static void add_domain_to_list(struct protection_domain
*domain
)
1641 unsigned long flags
;
1643 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1644 list_add(&domain
->list
, &amd_iommu_pd_list
);
1645 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1649 * This function removes a protection domain to the global
1650 * protection domain list
1652 static void del_domain_from_list(struct protection_domain
*domain
)
1654 unsigned long flags
;
1656 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1657 list_del(&domain
->list
);
1658 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1661 static u16
domain_id_alloc(void)
1663 unsigned long flags
;
1666 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1667 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1669 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1670 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1673 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1678 static void domain_id_free(int id
)
1680 unsigned long flags
;
1682 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1683 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1684 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1685 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1688 #define DEFINE_FREE_PT_FN(LVL, FN) \
1689 static void free_pt_##LVL (unsigned long __pt) \
1697 for (i = 0; i < 512; ++i) { \
1698 /* PTE present? */ \
1699 if (!IOMMU_PTE_PRESENT(pt[i])) \
1703 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1704 PM_PTE_LEVEL(pt[i]) == 7) \
1707 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1710 free_page((unsigned long)pt); \
1713 DEFINE_FREE_PT_FN(l2
, free_page
)
1714 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1715 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1716 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1717 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1719 static void free_pagetable(struct protection_domain
*domain
)
1721 unsigned long root
= (unsigned long)domain
->pt_root
;
1723 switch (domain
->mode
) {
1724 case PAGE_MODE_NONE
:
1726 case PAGE_MODE_1_LEVEL
:
1729 case PAGE_MODE_2_LEVEL
:
1732 case PAGE_MODE_3_LEVEL
:
1735 case PAGE_MODE_4_LEVEL
:
1738 case PAGE_MODE_5_LEVEL
:
1741 case PAGE_MODE_6_LEVEL
:
1749 static void free_gcr3_tbl_level1(u64
*tbl
)
1754 for (i
= 0; i
< 512; ++i
) {
1755 if (!(tbl
[i
] & GCR3_VALID
))
1758 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1760 free_page((unsigned long)ptr
);
1764 static void free_gcr3_tbl_level2(u64
*tbl
)
1769 for (i
= 0; i
< 512; ++i
) {
1770 if (!(tbl
[i
] & GCR3_VALID
))
1773 ptr
= __va(tbl
[i
] & PAGE_MASK
);
1775 free_gcr3_tbl_level1(ptr
);
1779 static void free_gcr3_table(struct protection_domain
*domain
)
1781 if (domain
->glx
== 2)
1782 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1783 else if (domain
->glx
== 1)
1784 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1786 BUG_ON(domain
->glx
!= 0);
1788 free_page((unsigned long)domain
->gcr3_tbl
);
1791 static void dma_ops_domain_free_flush_queue(struct dma_ops_domain
*dom
)
1795 for_each_possible_cpu(cpu
) {
1796 struct flush_queue
*queue
;
1798 queue
= per_cpu_ptr(dom
->flush_queue
, cpu
);
1799 kfree(queue
->entries
);
1802 free_percpu(dom
->flush_queue
);
1804 dom
->flush_queue
= NULL
;
1807 static int dma_ops_domain_alloc_flush_queue(struct dma_ops_domain
*dom
)
1811 atomic64_set(&dom
->flush_start_cnt
, 0);
1812 atomic64_set(&dom
->flush_finish_cnt
, 0);
1814 dom
->flush_queue
= alloc_percpu(struct flush_queue
);
1815 if (!dom
->flush_queue
)
1818 /* First make sure everything is cleared */
1819 for_each_possible_cpu(cpu
) {
1820 struct flush_queue
*queue
;
1822 queue
= per_cpu_ptr(dom
->flush_queue
, cpu
);
1825 queue
->entries
= NULL
;
1828 /* Now start doing the allocation */
1829 for_each_possible_cpu(cpu
) {
1830 struct flush_queue
*queue
;
1832 queue
= per_cpu_ptr(dom
->flush_queue
, cpu
);
1833 queue
->entries
= kzalloc(FLUSH_QUEUE_SIZE
* sizeof(*queue
->entries
),
1835 if (!queue
->entries
) {
1836 dma_ops_domain_free_flush_queue(dom
);
1840 spin_lock_init(&queue
->lock
);
1846 static void dma_ops_domain_flush_tlb(struct dma_ops_domain
*dom
)
1848 atomic64_inc(&dom
->flush_start_cnt
);
1849 domain_flush_tlb(&dom
->domain
);
1850 domain_flush_complete(&dom
->domain
);
1851 atomic64_inc(&dom
->flush_finish_cnt
);
1854 static inline bool queue_ring_full(struct flush_queue
*queue
)
1856 assert_spin_locked(&queue
->lock
);
1858 return (((queue
->tail
+ 1) % FLUSH_QUEUE_SIZE
) == queue
->head
);
1861 #define queue_ring_for_each(i, q) \
1862 for (i = (q)->head; i != (q)->tail; i = (i + 1) % FLUSH_QUEUE_SIZE)
1864 static inline unsigned queue_ring_add(struct flush_queue
*queue
)
1866 unsigned idx
= queue
->tail
;
1868 assert_spin_locked(&queue
->lock
);
1869 queue
->tail
= (idx
+ 1) % FLUSH_QUEUE_SIZE
;
1874 static inline void queue_ring_remove_head(struct flush_queue
*queue
)
1876 assert_spin_locked(&queue
->lock
);
1877 queue
->head
= (queue
->head
+ 1) % FLUSH_QUEUE_SIZE
;
1880 static void queue_ring_free_flushed(struct dma_ops_domain
*dom
,
1881 struct flush_queue
*queue
)
1883 u64 counter
= atomic64_read(&dom
->flush_finish_cnt
);
1886 queue_ring_for_each(idx
, queue
) {
1888 * This assumes that counter values in the ring-buffer are
1889 * monotonously rising.
1891 if (queue
->entries
[idx
].counter
>= counter
)
1894 free_iova_fast(&dom
->iovad
,
1895 queue
->entries
[idx
].iova_pfn
,
1896 queue
->entries
[idx
].pages
);
1898 queue_ring_remove_head(queue
);
1902 static void queue_add(struct dma_ops_domain
*dom
,
1903 unsigned long address
, unsigned long pages
)
1905 struct flush_queue
*queue
;
1906 unsigned long flags
;
1909 pages
= __roundup_pow_of_two(pages
);
1910 address
>>= PAGE_SHIFT
;
1912 queue
= get_cpu_ptr(dom
->flush_queue
);
1913 spin_lock_irqsave(&queue
->lock
, flags
);
1916 * First remove the enries from the ring-buffer that are already
1917 * flushed to make the below queue_ring_full() check less likely
1919 queue_ring_free_flushed(dom
, queue
);
1922 * When ring-queue is full, flush the entries from the IOTLB so
1923 * that we can free all entries with queue_ring_free_flushed()
1926 if (queue_ring_full(queue
)) {
1927 dma_ops_domain_flush_tlb(dom
);
1928 queue_ring_free_flushed(dom
, queue
);
1931 idx
= queue_ring_add(queue
);
1933 queue
->entries
[idx
].iova_pfn
= address
;
1934 queue
->entries
[idx
].pages
= pages
;
1935 queue
->entries
[idx
].counter
= atomic64_read(&dom
->flush_start_cnt
);
1937 spin_unlock_irqrestore(&queue
->lock
, flags
);
1939 if (atomic_cmpxchg(&dom
->flush_timer_on
, 0, 1) == 0)
1940 mod_timer(&dom
->flush_timer
, jiffies
+ msecs_to_jiffies(10));
1942 put_cpu_ptr(dom
->flush_queue
);
1945 static void queue_flush_timeout(unsigned long data
)
1947 struct dma_ops_domain
*dom
= (struct dma_ops_domain
*)data
;
1950 atomic_set(&dom
->flush_timer_on
, 0);
1952 dma_ops_domain_flush_tlb(dom
);
1954 for_each_possible_cpu(cpu
) {
1955 struct flush_queue
*queue
;
1956 unsigned long flags
;
1958 queue
= per_cpu_ptr(dom
->flush_queue
, cpu
);
1959 spin_lock_irqsave(&queue
->lock
, flags
);
1960 queue_ring_free_flushed(dom
, queue
);
1961 spin_unlock_irqrestore(&queue
->lock
, flags
);
1966 * Free a domain, only used if something went wrong in the
1967 * allocation path and we need to free an already allocated page table
1969 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1974 del_domain_from_list(&dom
->domain
);
1976 if (timer_pending(&dom
->flush_timer
))
1977 del_timer(&dom
->flush_timer
);
1979 dma_ops_domain_free_flush_queue(dom
);
1981 put_iova_domain(&dom
->iovad
);
1983 free_pagetable(&dom
->domain
);
1986 domain_id_free(dom
->domain
.id
);
1992 * Allocates a new protection domain usable for the dma_ops functions.
1993 * It also initializes the page table and the address allocator data
1994 * structures required for the dma_ops interface
1996 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1998 struct dma_ops_domain
*dma_dom
;
2000 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
2004 if (protection_domain_init(&dma_dom
->domain
))
2007 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
2008 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2009 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
2010 if (!dma_dom
->domain
.pt_root
)
2013 init_iova_domain(&dma_dom
->iovad
, PAGE_SIZE
,
2014 IOVA_START_PFN
, DMA_32BIT_PFN
);
2016 /* Initialize reserved ranges */
2017 copy_reserved_iova(&reserved_iova_ranges
, &dma_dom
->iovad
);
2019 if (dma_ops_domain_alloc_flush_queue(dma_dom
))
2022 setup_timer(&dma_dom
->flush_timer
, queue_flush_timeout
,
2023 (unsigned long)dma_dom
);
2025 atomic_set(&dma_dom
->flush_timer_on
, 0);
2027 add_domain_to_list(&dma_dom
->domain
);
2032 dma_ops_domain_free(dma_dom
);
2038 * little helper function to check whether a given protection domain is a
2041 static bool dma_ops_domain(struct protection_domain
*domain
)
2043 return domain
->flags
& PD_DMA_OPS_MASK
;
2046 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
2051 if (domain
->mode
!= PAGE_MODE_NONE
)
2052 pte_root
= virt_to_phys(domain
->pt_root
);
2054 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
2055 << DEV_ENTRY_MODE_SHIFT
;
2056 pte_root
|= IOMMU_PTE_IR
| IOMMU_PTE_IW
| IOMMU_PTE_P
| IOMMU_PTE_TV
;
2058 flags
= amd_iommu_dev_table
[devid
].data
[1];
2061 flags
|= DTE_FLAG_IOTLB
;
2063 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2064 u64 gcr3
= __pa(domain
->gcr3_tbl
);
2065 u64 glx
= domain
->glx
;
2068 pte_root
|= DTE_FLAG_GV
;
2069 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
2071 /* First mask out possible old values for GCR3 table */
2072 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
2075 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
2078 /* Encode GCR3 table into DTE */
2079 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
2082 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
2085 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
2090 flags
&= ~(DTE_FLAG_SA
| 0xffffULL
);
2091 flags
|= domain
->id
;
2093 amd_iommu_dev_table
[devid
].data
[1] = flags
;
2094 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
2097 static void clear_dte_entry(u16 devid
)
2099 /* remove entry from the device table seen by the hardware */
2100 amd_iommu_dev_table
[devid
].data
[0] = IOMMU_PTE_P
| IOMMU_PTE_TV
;
2101 amd_iommu_dev_table
[devid
].data
[1] &= DTE_FLAG_MASK
;
2103 amd_iommu_apply_erratum_63(devid
);
2106 static void do_attach(struct iommu_dev_data
*dev_data
,
2107 struct protection_domain
*domain
)
2109 struct amd_iommu
*iommu
;
2113 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2114 alias
= dev_data
->alias
;
2115 ats
= dev_data
->ats
.enabled
;
2117 /* Update data structures */
2118 dev_data
->domain
= domain
;
2119 list_add(&dev_data
->list
, &domain
->dev_list
);
2121 /* Do reference counting */
2122 domain
->dev_iommu
[iommu
->index
] += 1;
2123 domain
->dev_cnt
+= 1;
2125 /* Update device table */
2126 set_dte_entry(dev_data
->devid
, domain
, ats
);
2127 if (alias
!= dev_data
->devid
)
2128 set_dte_entry(alias
, domain
, ats
);
2130 device_flush_dte(dev_data
);
2133 static void do_detach(struct iommu_dev_data
*dev_data
)
2135 struct amd_iommu
*iommu
;
2139 * First check if the device is still attached. It might already
2140 * be detached from its domain because the generic
2141 * iommu_detach_group code detached it and we try again here in
2142 * our alias handling.
2144 if (!dev_data
->domain
)
2147 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2148 alias
= dev_data
->alias
;
2150 /* decrease reference counters */
2151 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2152 dev_data
->domain
->dev_cnt
-= 1;
2154 /* Update data structures */
2155 dev_data
->domain
= NULL
;
2156 list_del(&dev_data
->list
);
2157 clear_dte_entry(dev_data
->devid
);
2158 if (alias
!= dev_data
->devid
)
2159 clear_dte_entry(alias
);
2161 /* Flush the DTE entry */
2162 device_flush_dte(dev_data
);
2166 * If a device is not yet associated with a domain, this function does
2167 * assigns it visible for the hardware
2169 static int __attach_device(struct iommu_dev_data
*dev_data
,
2170 struct protection_domain
*domain
)
2175 * Must be called with IRQs disabled. Warn here to detect early
2178 WARN_ON(!irqs_disabled());
2181 spin_lock(&domain
->lock
);
2184 if (dev_data
->domain
!= NULL
)
2187 /* Attach alias group root */
2188 do_attach(dev_data
, domain
);
2195 spin_unlock(&domain
->lock
);
2201 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2203 pci_disable_ats(pdev
);
2204 pci_disable_pri(pdev
);
2205 pci_disable_pasid(pdev
);
2208 /* FIXME: Change generic reset-function to do the same */
2209 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2214 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2218 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2219 control
|= PCI_PRI_CTRL_RESET
;
2220 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2225 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2230 /* FIXME: Hardcode number of outstanding requests for now */
2232 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2234 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2236 /* Only allow access to user-accessible pages */
2237 ret
= pci_enable_pasid(pdev
, 0);
2241 /* First reset the PRI state of the device */
2242 ret
= pci_reset_pri(pdev
);
2247 ret
= pci_enable_pri(pdev
, reqs
);
2252 ret
= pri_reset_while_enabled(pdev
);
2257 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2264 pci_disable_pri(pdev
);
2265 pci_disable_pasid(pdev
);
2270 /* FIXME: Move this to PCI code */
2271 #define PCI_PRI_TLP_OFF (1 << 15)
2273 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2278 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2282 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2284 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2288 * If a device is not yet associated with a domain, this function
2289 * assigns it visible for the hardware
2291 static int attach_device(struct device
*dev
,
2292 struct protection_domain
*domain
)
2294 struct pci_dev
*pdev
;
2295 struct iommu_dev_data
*dev_data
;
2296 unsigned long flags
;
2299 dev_data
= get_dev_data(dev
);
2301 if (!dev_is_pci(dev
))
2302 goto skip_ats_check
;
2304 pdev
= to_pci_dev(dev
);
2305 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2306 if (!dev_data
->passthrough
)
2309 if (dev_data
->iommu_v2
) {
2310 if (pdev_iommuv2_enable(pdev
) != 0)
2313 dev_data
->ats
.enabled
= true;
2314 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2315 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2317 } else if (amd_iommu_iotlb_sup
&&
2318 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2319 dev_data
->ats
.enabled
= true;
2320 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2324 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2325 ret
= __attach_device(dev_data
, domain
);
2326 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2329 * We might boot into a crash-kernel here. The crashed kernel
2330 * left the caches in the IOMMU dirty. So we have to flush
2331 * here to evict all dirty stuff.
2333 domain_flush_tlb_pde(domain
);
2339 * Removes a device from a protection domain (unlocked)
2341 static void __detach_device(struct iommu_dev_data
*dev_data
)
2343 struct protection_domain
*domain
;
2346 * Must be called with IRQs disabled. Warn here to detect early
2349 WARN_ON(!irqs_disabled());
2351 if (WARN_ON(!dev_data
->domain
))
2354 domain
= dev_data
->domain
;
2356 spin_lock(&domain
->lock
);
2358 do_detach(dev_data
);
2360 spin_unlock(&domain
->lock
);
2364 * Removes a device from a protection domain (with devtable_lock held)
2366 static void detach_device(struct device
*dev
)
2368 struct protection_domain
*domain
;
2369 struct iommu_dev_data
*dev_data
;
2370 unsigned long flags
;
2372 dev_data
= get_dev_data(dev
);
2373 domain
= dev_data
->domain
;
2375 /* lock device table */
2376 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2377 __detach_device(dev_data
);
2378 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2380 if (!dev_is_pci(dev
))
2383 if (domain
->flags
& PD_IOMMUV2_MASK
&& dev_data
->iommu_v2
)
2384 pdev_iommuv2_disable(to_pci_dev(dev
));
2385 else if (dev_data
->ats
.enabled
)
2386 pci_disable_ats(to_pci_dev(dev
));
2388 dev_data
->ats
.enabled
= false;
2391 static int amd_iommu_add_device(struct device
*dev
)
2393 struct iommu_dev_data
*dev_data
;
2394 struct iommu_domain
*domain
;
2395 struct amd_iommu
*iommu
;
2398 if (!check_device(dev
) || get_dev_data(dev
))
2401 devid
= get_device_id(dev
);
2405 iommu
= amd_iommu_rlookup_table
[devid
];
2407 ret
= iommu_init_device(dev
);
2409 if (ret
!= -ENOTSUPP
)
2410 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2413 iommu_ignore_device(dev
);
2414 dev
->dma_ops
= &nommu_dma_ops
;
2417 init_iommu_group(dev
);
2419 dev_data
= get_dev_data(dev
);
2423 if (iommu_pass_through
|| dev_data
->iommu_v2
)
2424 iommu_request_dm_for_dev(dev
);
2426 /* Domains are initialized for this device - have a look what we ended up with */
2427 domain
= iommu_get_domain_for_dev(dev
);
2428 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
)
2429 dev_data
->passthrough
= true;
2431 dev
->dma_ops
= &amd_iommu_dma_ops
;
2434 iommu_completion_wait(iommu
);
2439 static void amd_iommu_remove_device(struct device
*dev
)
2441 struct amd_iommu
*iommu
;
2444 if (!check_device(dev
))
2447 devid
= get_device_id(dev
);
2451 iommu
= amd_iommu_rlookup_table
[devid
];
2453 iommu_uninit_device(dev
);
2454 iommu_completion_wait(iommu
);
2457 static struct iommu_group
*amd_iommu_device_group(struct device
*dev
)
2459 if (dev_is_pci(dev
))
2460 return pci_device_group(dev
);
2462 return acpihid_device_group(dev
);
2465 /*****************************************************************************
2467 * The next functions belong to the dma_ops mapping/unmapping code.
2469 *****************************************************************************/
2472 * In the dma_ops path we only have the struct device. This function
2473 * finds the corresponding IOMMU, the protection domain and the
2474 * requestor id for a given device.
2475 * If the device is not yet associated with a domain this is also done
2478 static struct protection_domain
*get_domain(struct device
*dev
)
2480 struct protection_domain
*domain
;
2482 if (!check_device(dev
))
2483 return ERR_PTR(-EINVAL
);
2485 domain
= get_dev_data(dev
)->domain
;
2486 if (!dma_ops_domain(domain
))
2487 return ERR_PTR(-EBUSY
);
2492 static void update_device_table(struct protection_domain
*domain
)
2494 struct iommu_dev_data
*dev_data
;
2496 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
2497 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2499 if (dev_data
->devid
== dev_data
->alias
)
2502 /* There is an alias, update device table entry for it */
2503 set_dte_entry(dev_data
->alias
, domain
, dev_data
->ats
.enabled
);
2507 static void update_domain(struct protection_domain
*domain
)
2509 if (!domain
->updated
)
2512 update_device_table(domain
);
2514 domain_flush_devices(domain
);
2515 domain_flush_tlb_pde(domain
);
2517 domain
->updated
= false;
2520 static int dir2prot(enum dma_data_direction direction
)
2522 if (direction
== DMA_TO_DEVICE
)
2523 return IOMMU_PROT_IR
;
2524 else if (direction
== DMA_FROM_DEVICE
)
2525 return IOMMU_PROT_IW
;
2526 else if (direction
== DMA_BIDIRECTIONAL
)
2527 return IOMMU_PROT_IW
| IOMMU_PROT_IR
;
2532 * This function contains common code for mapping of a physically
2533 * contiguous memory region into DMA address space. It is used by all
2534 * mapping functions provided with this IOMMU driver.
2535 * Must be called with the domain lock held.
2537 static dma_addr_t
__map_single(struct device
*dev
,
2538 struct dma_ops_domain
*dma_dom
,
2541 enum dma_data_direction direction
,
2544 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2545 dma_addr_t address
, start
, ret
;
2550 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2553 address
= dma_ops_alloc_iova(dev
, dma_dom
, pages
, dma_mask
);
2554 if (address
== AMD_IOMMU_MAPPING_ERROR
)
2557 prot
= dir2prot(direction
);
2560 for (i
= 0; i
< pages
; ++i
) {
2561 ret
= iommu_map_page(&dma_dom
->domain
, start
, paddr
,
2562 PAGE_SIZE
, prot
, GFP_ATOMIC
);
2571 if (unlikely(amd_iommu_np_cache
)) {
2572 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2573 domain_flush_complete(&dma_dom
->domain
);
2581 for (--i
; i
>= 0; --i
) {
2583 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2586 domain_flush_tlb(&dma_dom
->domain
);
2587 domain_flush_complete(&dma_dom
->domain
);
2589 dma_ops_free_iova(dma_dom
, address
, pages
);
2591 return AMD_IOMMU_MAPPING_ERROR
;
2595 * Does the reverse of the __map_single function. Must be called with
2596 * the domain lock held too
2598 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2599 dma_addr_t dma_addr
,
2603 dma_addr_t flush_addr
;
2604 dma_addr_t i
, start
;
2607 flush_addr
= dma_addr
;
2608 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2609 dma_addr
&= PAGE_MASK
;
2612 for (i
= 0; i
< pages
; ++i
) {
2613 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2617 if (amd_iommu_unmap_flush
) {
2618 dma_ops_free_iova(dma_dom
, dma_addr
, pages
);
2619 domain_flush_tlb(&dma_dom
->domain
);
2620 domain_flush_complete(&dma_dom
->domain
);
2622 queue_add(dma_dom
, dma_addr
, pages
);
2627 * The exported map_single function for dma_ops.
2629 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2630 unsigned long offset
, size_t size
,
2631 enum dma_data_direction dir
,
2632 unsigned long attrs
)
2634 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2635 struct protection_domain
*domain
;
2636 struct dma_ops_domain
*dma_dom
;
2639 domain
= get_domain(dev
);
2640 if (PTR_ERR(domain
) == -EINVAL
)
2641 return (dma_addr_t
)paddr
;
2642 else if (IS_ERR(domain
))
2643 return AMD_IOMMU_MAPPING_ERROR
;
2645 dma_mask
= *dev
->dma_mask
;
2646 dma_dom
= to_dma_ops_domain(domain
);
2648 return __map_single(dev
, dma_dom
, paddr
, size
, dir
, dma_mask
);
2652 * The exported unmap_single function for dma_ops.
2654 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2655 enum dma_data_direction dir
, unsigned long attrs
)
2657 struct protection_domain
*domain
;
2658 struct dma_ops_domain
*dma_dom
;
2660 domain
= get_domain(dev
);
2664 dma_dom
= to_dma_ops_domain(domain
);
2666 __unmap_single(dma_dom
, dma_addr
, size
, dir
);
2669 static int sg_num_pages(struct device
*dev
,
2670 struct scatterlist
*sglist
,
2673 unsigned long mask
, boundary_size
;
2674 struct scatterlist
*s
;
2677 mask
= dma_get_seg_boundary(dev
);
2678 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
2679 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
2681 for_each_sg(sglist
, s
, nelems
, i
) {
2684 s
->dma_address
= npages
<< PAGE_SHIFT
;
2685 p
= npages
% boundary_size
;
2686 n
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2687 if (p
+ n
> boundary_size
)
2688 npages
+= boundary_size
- p
;
2696 * The exported map_sg function for dma_ops (handles scatter-gather
2699 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2700 int nelems
, enum dma_data_direction direction
,
2701 unsigned long attrs
)
2703 int mapped_pages
= 0, npages
= 0, prot
= 0, i
;
2704 struct protection_domain
*domain
;
2705 struct dma_ops_domain
*dma_dom
;
2706 struct scatterlist
*s
;
2707 unsigned long address
;
2710 domain
= get_domain(dev
);
2714 dma_dom
= to_dma_ops_domain(domain
);
2715 dma_mask
= *dev
->dma_mask
;
2717 npages
= sg_num_pages(dev
, sglist
, nelems
);
2719 address
= dma_ops_alloc_iova(dev
, dma_dom
, npages
, dma_mask
);
2720 if (address
== AMD_IOMMU_MAPPING_ERROR
)
2723 prot
= dir2prot(direction
);
2725 /* Map all sg entries */
2726 for_each_sg(sglist
, s
, nelems
, i
) {
2727 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2729 for (j
= 0; j
< pages
; ++j
) {
2730 unsigned long bus_addr
, phys_addr
;
2733 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2734 phys_addr
= (sg_phys(s
) & PAGE_MASK
) + (j
<< PAGE_SHIFT
);
2735 ret
= iommu_map_page(domain
, bus_addr
, phys_addr
, PAGE_SIZE
, prot
, GFP_ATOMIC
);
2743 /* Everything is mapped - write the right values into s->dma_address */
2744 for_each_sg(sglist
, s
, nelems
, i
) {
2745 s
->dma_address
+= address
+ s
->offset
;
2746 s
->dma_length
= s
->length
;
2752 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2753 dev_name(dev
), npages
);
2755 for_each_sg(sglist
, s
, nelems
, i
) {
2756 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2758 for (j
= 0; j
< pages
; ++j
) {
2759 unsigned long bus_addr
;
2761 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2762 iommu_unmap_page(domain
, bus_addr
, PAGE_SIZE
);
2770 free_iova_fast(&dma_dom
->iovad
, address
, npages
);
2777 * The exported map_sg function for dma_ops (handles scatter-gather
2780 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2781 int nelems
, enum dma_data_direction dir
,
2782 unsigned long attrs
)
2784 struct protection_domain
*domain
;
2785 struct dma_ops_domain
*dma_dom
;
2786 unsigned long startaddr
;
2789 domain
= get_domain(dev
);
2793 startaddr
= sg_dma_address(sglist
) & PAGE_MASK
;
2794 dma_dom
= to_dma_ops_domain(domain
);
2795 npages
= sg_num_pages(dev
, sglist
, nelems
);
2797 __unmap_single(dma_dom
, startaddr
, npages
<< PAGE_SHIFT
, dir
);
2801 * The exported alloc_coherent function for dma_ops.
2803 static void *alloc_coherent(struct device
*dev
, size_t size
,
2804 dma_addr_t
*dma_addr
, gfp_t flag
,
2805 unsigned long attrs
)
2807 u64 dma_mask
= dev
->coherent_dma_mask
;
2808 struct protection_domain
*domain
;
2809 struct dma_ops_domain
*dma_dom
;
2812 domain
= get_domain(dev
);
2813 if (PTR_ERR(domain
) == -EINVAL
) {
2814 page
= alloc_pages(flag
, get_order(size
));
2815 *dma_addr
= page_to_phys(page
);
2816 return page_address(page
);
2817 } else if (IS_ERR(domain
))
2820 dma_dom
= to_dma_ops_domain(domain
);
2821 size
= PAGE_ALIGN(size
);
2822 dma_mask
= dev
->coherent_dma_mask
;
2823 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2826 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2828 if (!gfpflags_allow_blocking(flag
))
2831 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2832 get_order(size
), flag
);
2838 dma_mask
= *dev
->dma_mask
;
2840 *dma_addr
= __map_single(dev
, dma_dom
, page_to_phys(page
),
2841 size
, DMA_BIDIRECTIONAL
, dma_mask
);
2843 if (*dma_addr
== AMD_IOMMU_MAPPING_ERROR
)
2846 return page_address(page
);
2850 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2851 __free_pages(page
, get_order(size
));
2857 * The exported free_coherent function for dma_ops.
2859 static void free_coherent(struct device
*dev
, size_t size
,
2860 void *virt_addr
, dma_addr_t dma_addr
,
2861 unsigned long attrs
)
2863 struct protection_domain
*domain
;
2864 struct dma_ops_domain
*dma_dom
;
2867 page
= virt_to_page(virt_addr
);
2868 size
= PAGE_ALIGN(size
);
2870 domain
= get_domain(dev
);
2874 dma_dom
= to_dma_ops_domain(domain
);
2876 __unmap_single(dma_dom
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2879 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2880 __free_pages(page
, get_order(size
));
2884 * This function is called by the DMA layer to find out if we can handle a
2885 * particular device. It is part of the dma_ops.
2887 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2889 if (!x86_dma_supported(dev
, mask
))
2891 return check_device(dev
);
2894 static int amd_iommu_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
2896 return dma_addr
== AMD_IOMMU_MAPPING_ERROR
;
2899 static const struct dma_map_ops amd_iommu_dma_ops
= {
2900 .alloc
= alloc_coherent
,
2901 .free
= free_coherent
,
2902 .map_page
= map_page
,
2903 .unmap_page
= unmap_page
,
2905 .unmap_sg
= unmap_sg
,
2906 .dma_supported
= amd_iommu_dma_supported
,
2907 .mapping_error
= amd_iommu_mapping_error
,
2910 static int init_reserved_iova_ranges(void)
2912 struct pci_dev
*pdev
= NULL
;
2915 init_iova_domain(&reserved_iova_ranges
, PAGE_SIZE
,
2916 IOVA_START_PFN
, DMA_32BIT_PFN
);
2918 lockdep_set_class(&reserved_iova_ranges
.iova_rbtree_lock
,
2919 &reserved_rbtree_key
);
2921 /* MSI memory range */
2922 val
= reserve_iova(&reserved_iova_ranges
,
2923 IOVA_PFN(MSI_RANGE_START
), IOVA_PFN(MSI_RANGE_END
));
2925 pr_err("Reserving MSI range failed\n");
2929 /* HT memory range */
2930 val
= reserve_iova(&reserved_iova_ranges
,
2931 IOVA_PFN(HT_RANGE_START
), IOVA_PFN(HT_RANGE_END
));
2933 pr_err("Reserving HT range failed\n");
2938 * Memory used for PCI resources
2939 * FIXME: Check whether we can reserve the PCI-hole completly
2941 for_each_pci_dev(pdev
) {
2944 for (i
= 0; i
< PCI_NUM_RESOURCES
; ++i
) {
2945 struct resource
*r
= &pdev
->resource
[i
];
2947 if (!(r
->flags
& IORESOURCE_MEM
))
2950 val
= reserve_iova(&reserved_iova_ranges
,
2954 pr_err("Reserve pci-resource range failed\n");
2963 int __init
amd_iommu_init_api(void)
2967 ret
= iova_cache_get();
2971 ret
= init_reserved_iova_ranges();
2975 err
= bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2978 #ifdef CONFIG_ARM_AMBA
2979 err
= bus_set_iommu(&amba_bustype
, &amd_iommu_ops
);
2983 err
= bus_set_iommu(&platform_bus_type
, &amd_iommu_ops
);
2990 int __init
amd_iommu_init_dma_ops(void)
2992 swiotlb
= iommu_pass_through
? 1 : 0;
2996 * In case we don't initialize SWIOTLB (actually the common case
2997 * when AMD IOMMU is enabled), make sure there are global
2998 * dma_ops set as a fall-back for devices not handled by this
2999 * driver (for example non-PCI devices).
3002 dma_ops
= &nommu_dma_ops
;
3004 if (amd_iommu_unmap_flush
)
3005 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3007 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3013 /*****************************************************************************
3015 * The following functions belong to the exported interface of AMD IOMMU
3017 * This interface allows access to lower level functions of the IOMMU
3018 * like protection domain handling and assignement of devices to domains
3019 * which is not possible with the dma_ops interface.
3021 *****************************************************************************/
3023 static void cleanup_domain(struct protection_domain
*domain
)
3025 struct iommu_dev_data
*entry
;
3026 unsigned long flags
;
3028 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3030 while (!list_empty(&domain
->dev_list
)) {
3031 entry
= list_first_entry(&domain
->dev_list
,
3032 struct iommu_dev_data
, list
);
3033 __detach_device(entry
);
3036 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3039 static void protection_domain_free(struct protection_domain
*domain
)
3044 del_domain_from_list(domain
);
3047 domain_id_free(domain
->id
);
3052 static int protection_domain_init(struct protection_domain
*domain
)
3054 spin_lock_init(&domain
->lock
);
3055 mutex_init(&domain
->api_lock
);
3056 domain
->id
= domain_id_alloc();
3059 INIT_LIST_HEAD(&domain
->dev_list
);
3064 static struct protection_domain
*protection_domain_alloc(void)
3066 struct protection_domain
*domain
;
3068 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
3072 if (protection_domain_init(domain
))
3075 add_domain_to_list(domain
);
3085 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
3087 struct protection_domain
*pdomain
;
3088 struct dma_ops_domain
*dma_domain
;
3091 case IOMMU_DOMAIN_UNMANAGED
:
3092 pdomain
= protection_domain_alloc();
3096 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
3097 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
3098 if (!pdomain
->pt_root
) {
3099 protection_domain_free(pdomain
);
3103 pdomain
->domain
.geometry
.aperture_start
= 0;
3104 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
3105 pdomain
->domain
.geometry
.force_aperture
= true;
3108 case IOMMU_DOMAIN_DMA
:
3109 dma_domain
= dma_ops_domain_alloc();
3111 pr_err("AMD-Vi: Failed to allocate\n");
3114 pdomain
= &dma_domain
->domain
;
3116 case IOMMU_DOMAIN_IDENTITY
:
3117 pdomain
= protection_domain_alloc();
3121 pdomain
->mode
= PAGE_MODE_NONE
;
3127 return &pdomain
->domain
;
3130 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
3132 struct protection_domain
*domain
;
3133 struct dma_ops_domain
*dma_dom
;
3135 domain
= to_pdomain(dom
);
3137 if (domain
->dev_cnt
> 0)
3138 cleanup_domain(domain
);
3140 BUG_ON(domain
->dev_cnt
!= 0);
3145 switch (dom
->type
) {
3146 case IOMMU_DOMAIN_DMA
:
3147 /* Now release the domain */
3148 dma_dom
= to_dma_ops_domain(domain
);
3149 dma_ops_domain_free(dma_dom
);
3152 if (domain
->mode
!= PAGE_MODE_NONE
)
3153 free_pagetable(domain
);
3155 if (domain
->flags
& PD_IOMMUV2_MASK
)
3156 free_gcr3_table(domain
);
3158 protection_domain_free(domain
);
3163 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3166 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3167 struct amd_iommu
*iommu
;
3170 if (!check_device(dev
))
3173 devid
= get_device_id(dev
);
3177 if (dev_data
->domain
!= NULL
)
3180 iommu
= amd_iommu_rlookup_table
[devid
];
3184 #ifdef CONFIG_IRQ_REMAP
3185 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) &&
3186 (dom
->type
== IOMMU_DOMAIN_UNMANAGED
))
3187 dev_data
->use_vapic
= 0;
3190 iommu_completion_wait(iommu
);
3193 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3196 struct protection_domain
*domain
= to_pdomain(dom
);
3197 struct iommu_dev_data
*dev_data
;
3198 struct amd_iommu
*iommu
;
3201 if (!check_device(dev
))
3204 dev_data
= dev
->archdata
.iommu
;
3206 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3210 if (dev_data
->domain
)
3213 ret
= attach_device(dev
, domain
);
3215 #ifdef CONFIG_IRQ_REMAP
3216 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
3217 if (dom
->type
== IOMMU_DOMAIN_UNMANAGED
)
3218 dev_data
->use_vapic
= 1;
3220 dev_data
->use_vapic
= 0;
3224 iommu_completion_wait(iommu
);
3229 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3230 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3232 struct protection_domain
*domain
= to_pdomain(dom
);
3236 if (domain
->mode
== PAGE_MODE_NONE
)
3239 if (iommu_prot
& IOMMU_READ
)
3240 prot
|= IOMMU_PROT_IR
;
3241 if (iommu_prot
& IOMMU_WRITE
)
3242 prot
|= IOMMU_PROT_IW
;
3244 mutex_lock(&domain
->api_lock
);
3245 ret
= iommu_map_page(domain
, iova
, paddr
, page_size
, prot
, GFP_KERNEL
);
3246 mutex_unlock(&domain
->api_lock
);
3251 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3254 struct protection_domain
*domain
= to_pdomain(dom
);
3257 if (domain
->mode
== PAGE_MODE_NONE
)
3260 mutex_lock(&domain
->api_lock
);
3261 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3262 mutex_unlock(&domain
->api_lock
);
3264 domain_flush_tlb_pde(domain
);
3265 domain_flush_complete(domain
);
3270 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3273 struct protection_domain
*domain
= to_pdomain(dom
);
3274 unsigned long offset_mask
, pte_pgsize
;
3277 if (domain
->mode
== PAGE_MODE_NONE
)
3280 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3282 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3285 offset_mask
= pte_pgsize
- 1;
3286 __pte
= *pte
& PM_ADDR_MASK
;
3288 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3291 static bool amd_iommu_capable(enum iommu_cap cap
)
3294 case IOMMU_CAP_CACHE_COHERENCY
:
3296 case IOMMU_CAP_INTR_REMAP
:
3297 return (irq_remapping_enabled
== 1);
3298 case IOMMU_CAP_NOEXEC
:
3305 static void amd_iommu_get_resv_regions(struct device
*dev
,
3306 struct list_head
*head
)
3308 struct iommu_resv_region
*region
;
3309 struct unity_map_entry
*entry
;
3312 devid
= get_device_id(dev
);
3316 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3320 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3323 length
= entry
->address_end
- entry
->address_start
;
3324 if (entry
->prot
& IOMMU_PROT_IR
)
3326 if (entry
->prot
& IOMMU_PROT_IW
)
3327 prot
|= IOMMU_WRITE
;
3329 region
= iommu_alloc_resv_region(entry
->address_start
,
3333 pr_err("Out of memory allocating dm-regions for %s\n",
3337 list_add_tail(®ion
->list
, head
);
3340 region
= iommu_alloc_resv_region(MSI_RANGE_START
,
3341 MSI_RANGE_END
- MSI_RANGE_START
+ 1,
3345 list_add_tail(®ion
->list
, head
);
3347 region
= iommu_alloc_resv_region(HT_RANGE_START
,
3348 HT_RANGE_END
- HT_RANGE_START
+ 1,
3349 0, IOMMU_RESV_RESERVED
);
3352 list_add_tail(®ion
->list
, head
);
3355 static void amd_iommu_put_resv_regions(struct device
*dev
,
3356 struct list_head
*head
)
3358 struct iommu_resv_region
*entry
, *next
;
3360 list_for_each_entry_safe(entry
, next
, head
, list
)
3364 static void amd_iommu_apply_resv_region(struct device
*dev
,
3365 struct iommu_domain
*domain
,
3366 struct iommu_resv_region
*region
)
3368 struct dma_ops_domain
*dma_dom
= to_dma_ops_domain(to_pdomain(domain
));
3369 unsigned long start
, end
;
3371 start
= IOVA_PFN(region
->start
);
3372 end
= IOVA_PFN(region
->start
+ region
->length
);
3374 WARN_ON_ONCE(reserve_iova(&dma_dom
->iovad
, start
, end
) == NULL
);
3377 const struct iommu_ops amd_iommu_ops
= {
3378 .capable
= amd_iommu_capable
,
3379 .domain_alloc
= amd_iommu_domain_alloc
,
3380 .domain_free
= amd_iommu_domain_free
,
3381 .attach_dev
= amd_iommu_attach_device
,
3382 .detach_dev
= amd_iommu_detach_device
,
3383 .map
= amd_iommu_map
,
3384 .unmap
= amd_iommu_unmap
,
3385 .map_sg
= default_iommu_map_sg
,
3386 .iova_to_phys
= amd_iommu_iova_to_phys
,
3387 .add_device
= amd_iommu_add_device
,
3388 .remove_device
= amd_iommu_remove_device
,
3389 .device_group
= amd_iommu_device_group
,
3390 .get_resv_regions
= amd_iommu_get_resv_regions
,
3391 .put_resv_regions
= amd_iommu_put_resv_regions
,
3392 .apply_resv_region
= amd_iommu_apply_resv_region
,
3393 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3396 /*****************************************************************************
3398 * The next functions do a basic initialization of IOMMU for pass through
3401 * In passthrough mode the IOMMU is initialized and enabled but not used for
3402 * DMA-API translation.
3404 *****************************************************************************/
3406 /* IOMMUv2 specific functions */
3407 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3409 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3411 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3413 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3415 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3417 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3419 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3421 struct protection_domain
*domain
= to_pdomain(dom
);
3422 unsigned long flags
;
3424 spin_lock_irqsave(&domain
->lock
, flags
);
3426 /* Update data structure */
3427 domain
->mode
= PAGE_MODE_NONE
;
3428 domain
->updated
= true;
3430 /* Make changes visible to IOMMUs */
3431 update_domain(domain
);
3433 /* Page-table is not visible to IOMMU anymore, so free it */
3434 free_pagetable(domain
);
3436 spin_unlock_irqrestore(&domain
->lock
, flags
);
3438 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3440 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3442 struct protection_domain
*domain
= to_pdomain(dom
);
3443 unsigned long flags
;
3446 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3449 /* Number of GCR3 table levels required */
3450 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3453 if (levels
> amd_iommu_max_glx_val
)
3456 spin_lock_irqsave(&domain
->lock
, flags
);
3459 * Save us all sanity checks whether devices already in the
3460 * domain support IOMMUv2. Just force that the domain has no
3461 * devices attached when it is switched into IOMMUv2 mode.
3464 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3468 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3469 if (domain
->gcr3_tbl
== NULL
)
3472 domain
->glx
= levels
;
3473 domain
->flags
|= PD_IOMMUV2_MASK
;
3474 domain
->updated
= true;
3476 update_domain(domain
);
3481 spin_unlock_irqrestore(&domain
->lock
, flags
);
3485 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3487 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3488 u64 address
, bool size
)
3490 struct iommu_dev_data
*dev_data
;
3491 struct iommu_cmd cmd
;
3494 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3497 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3500 * IOMMU TLB needs to be flushed before Device TLB to
3501 * prevent device TLB refill from IOMMU TLB
3503 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
3504 if (domain
->dev_iommu
[i
] == 0)
3507 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3512 /* Wait until IOMMU TLB flushes are complete */
3513 domain_flush_complete(domain
);
3515 /* Now flush device TLBs */
3516 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3517 struct amd_iommu
*iommu
;
3521 There might be non-IOMMUv2 capable devices in an IOMMUv2
3524 if (!dev_data
->ats
.enabled
)
3527 qdep
= dev_data
->ats
.qdep
;
3528 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3530 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3531 qdep
, address
, size
);
3533 ret
= iommu_queue_command(iommu
, &cmd
);
3538 /* Wait until all device TLBs are flushed */
3539 domain_flush_complete(domain
);
3548 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3551 return __flush_pasid(domain
, pasid
, address
, false);
3554 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3557 struct protection_domain
*domain
= to_pdomain(dom
);
3558 unsigned long flags
;
3561 spin_lock_irqsave(&domain
->lock
, flags
);
3562 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3563 spin_unlock_irqrestore(&domain
->lock
, flags
);
3567 EXPORT_SYMBOL(amd_iommu_flush_page
);
3569 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3571 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3575 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3577 struct protection_domain
*domain
= to_pdomain(dom
);
3578 unsigned long flags
;
3581 spin_lock_irqsave(&domain
->lock
, flags
);
3582 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3583 spin_unlock_irqrestore(&domain
->lock
, flags
);
3587 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3589 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3596 index
= (pasid
>> (9 * level
)) & 0x1ff;
3602 if (!(*pte
& GCR3_VALID
)) {
3606 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3610 *pte
= __pa(root
) | GCR3_VALID
;
3613 root
= __va(*pte
& PAGE_MASK
);
3621 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3626 if (domain
->mode
!= PAGE_MODE_NONE
)
3629 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3633 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3635 return __amd_iommu_flush_tlb(domain
, pasid
);
3638 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3642 if (domain
->mode
!= PAGE_MODE_NONE
)
3645 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3651 return __amd_iommu_flush_tlb(domain
, pasid
);
3654 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3657 struct protection_domain
*domain
= to_pdomain(dom
);
3658 unsigned long flags
;
3661 spin_lock_irqsave(&domain
->lock
, flags
);
3662 ret
= __set_gcr3(domain
, pasid
, cr3
);
3663 spin_unlock_irqrestore(&domain
->lock
, flags
);
3667 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3669 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3671 struct protection_domain
*domain
= to_pdomain(dom
);
3672 unsigned long flags
;
3675 spin_lock_irqsave(&domain
->lock
, flags
);
3676 ret
= __clear_gcr3(domain
, pasid
);
3677 spin_unlock_irqrestore(&domain
->lock
, flags
);
3681 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3683 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3684 int status
, int tag
)
3686 struct iommu_dev_data
*dev_data
;
3687 struct amd_iommu
*iommu
;
3688 struct iommu_cmd cmd
;
3690 dev_data
= get_dev_data(&pdev
->dev
);
3691 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3693 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3694 tag
, dev_data
->pri_tlp
);
3696 return iommu_queue_command(iommu
, &cmd
);
3698 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3700 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3702 struct protection_domain
*pdomain
;
3704 pdomain
= get_domain(&pdev
->dev
);
3705 if (IS_ERR(pdomain
))
3708 /* Only return IOMMUv2 domains */
3709 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3712 return &pdomain
->domain
;
3714 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3716 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3718 struct iommu_dev_data
*dev_data
;
3720 if (!amd_iommu_v2_supported())
3723 dev_data
= get_dev_data(&pdev
->dev
);
3724 dev_data
->errata
|= (1 << erratum
);
3726 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3728 int amd_iommu_device_info(struct pci_dev
*pdev
,
3729 struct amd_iommu_device_info
*info
)
3734 if (pdev
== NULL
|| info
== NULL
)
3737 if (!amd_iommu_v2_supported())
3740 memset(info
, 0, sizeof(*info
));
3742 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3744 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3746 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3748 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3750 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3754 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3755 max_pasids
= min(max_pasids
, (1 << 20));
3757 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3758 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3760 features
= pci_pasid_features(pdev
);
3761 if (features
& PCI_PASID_CAP_EXEC
)
3762 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3763 if (features
& PCI_PASID_CAP_PRIV
)
3764 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3769 EXPORT_SYMBOL(amd_iommu_device_info
);
3771 #ifdef CONFIG_IRQ_REMAP
3773 /*****************************************************************************
3775 * Interrupt Remapping Implementation
3777 *****************************************************************************/
3779 static struct irq_chip amd_ir_chip
;
3781 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3782 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3783 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3784 #define DTE_IRQ_REMAP_ENABLE 1ULL
3786 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3790 dte
= amd_iommu_dev_table
[devid
].data
[2];
3791 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3792 dte
|= virt_to_phys(table
->table
);
3793 dte
|= DTE_IRQ_REMAP_INTCTL
;
3794 dte
|= DTE_IRQ_TABLE_LEN
;
3795 dte
|= DTE_IRQ_REMAP_ENABLE
;
3797 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3800 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3802 struct irq_remap_table
*table
= NULL
;
3803 struct amd_iommu
*iommu
;
3804 unsigned long flags
;
3807 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3809 iommu
= amd_iommu_rlookup_table
[devid
];
3813 table
= irq_lookup_table
[devid
];
3817 alias
= amd_iommu_alias_table
[devid
];
3818 table
= irq_lookup_table
[alias
];
3820 irq_lookup_table
[devid
] = table
;
3821 set_dte_irq_entry(devid
, table
);
3822 iommu_flush_dte(iommu
, devid
);
3826 /* Nothing there yet, allocate new irq remapping table */
3827 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3831 /* Initialize table spin-lock */
3832 spin_lock_init(&table
->lock
);
3835 /* Keep the first 32 indexes free for IOAPIC interrupts */
3836 table
->min_index
= 32;
3838 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3839 if (!table
->table
) {
3845 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
3846 memset(table
->table
, 0,
3847 MAX_IRQS_PER_TABLE
* sizeof(u32
));
3849 memset(table
->table
, 0,
3850 (MAX_IRQS_PER_TABLE
* (sizeof(u64
) * 2)));
3855 for (i
= 0; i
< 32; ++i
)
3856 iommu
->irte_ops
->set_allocated(table
, i
);
3859 irq_lookup_table
[devid
] = table
;
3860 set_dte_irq_entry(devid
, table
);
3861 iommu_flush_dte(iommu
, devid
);
3862 if (devid
!= alias
) {
3863 irq_lookup_table
[alias
] = table
;
3864 set_dte_irq_entry(alias
, table
);
3865 iommu_flush_dte(iommu
, alias
);
3869 iommu_completion_wait(iommu
);
3872 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3877 static int alloc_irq_index(u16 devid
, int count
)
3879 struct irq_remap_table
*table
;
3880 unsigned long flags
;
3882 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
3887 table
= get_irq_table(devid
, false);
3891 spin_lock_irqsave(&table
->lock
, flags
);
3893 /* Scan table for free entries */
3894 for (c
= 0, index
= table
->min_index
;
3895 index
< MAX_IRQS_PER_TABLE
;
3897 if (!iommu
->irte_ops
->is_allocated(table
, index
))
3904 iommu
->irte_ops
->set_allocated(table
, index
- c
+ 1);
3914 spin_unlock_irqrestore(&table
->lock
, flags
);
3919 static int modify_irte_ga(u16 devid
, int index
, struct irte_ga
*irte
,
3920 struct amd_ir_data
*data
)
3922 struct irq_remap_table
*table
;
3923 struct amd_iommu
*iommu
;
3924 unsigned long flags
;
3925 struct irte_ga
*entry
;
3927 iommu
= amd_iommu_rlookup_table
[devid
];
3931 table
= get_irq_table(devid
, false);
3935 spin_lock_irqsave(&table
->lock
, flags
);
3937 entry
= (struct irte_ga
*)table
->table
;
3938 entry
= &entry
[index
];
3939 entry
->lo
.fields_remap
.valid
= 0;
3940 entry
->hi
.val
= irte
->hi
.val
;
3941 entry
->lo
.val
= irte
->lo
.val
;
3942 entry
->lo
.fields_remap
.valid
= 1;
3946 spin_unlock_irqrestore(&table
->lock
, flags
);
3948 iommu_flush_irt(iommu
, devid
);
3949 iommu_completion_wait(iommu
);
3954 static int modify_irte(u16 devid
, int index
, union irte
*irte
)
3956 struct irq_remap_table
*table
;
3957 struct amd_iommu
*iommu
;
3958 unsigned long flags
;
3960 iommu
= amd_iommu_rlookup_table
[devid
];
3964 table
= get_irq_table(devid
, false);
3968 spin_lock_irqsave(&table
->lock
, flags
);
3969 table
->table
[index
] = irte
->val
;
3970 spin_unlock_irqrestore(&table
->lock
, flags
);
3972 iommu_flush_irt(iommu
, devid
);
3973 iommu_completion_wait(iommu
);
3978 static void free_irte(u16 devid
, int index
)
3980 struct irq_remap_table
*table
;
3981 struct amd_iommu
*iommu
;
3982 unsigned long flags
;
3984 iommu
= amd_iommu_rlookup_table
[devid
];
3988 table
= get_irq_table(devid
, false);
3992 spin_lock_irqsave(&table
->lock
, flags
);
3993 iommu
->irte_ops
->clear_allocated(table
, index
);
3994 spin_unlock_irqrestore(&table
->lock
, flags
);
3996 iommu_flush_irt(iommu
, devid
);
3997 iommu_completion_wait(iommu
);
4000 static void irte_prepare(void *entry
,
4001 u32 delivery_mode
, u32 dest_mode
,
4002 u8 vector
, u32 dest_apicid
, int devid
)
4004 union irte
*irte
= (union irte
*) entry
;
4007 irte
->fields
.vector
= vector
;
4008 irte
->fields
.int_type
= delivery_mode
;
4009 irte
->fields
.destination
= dest_apicid
;
4010 irte
->fields
.dm
= dest_mode
;
4011 irte
->fields
.valid
= 1;
4014 static void irte_ga_prepare(void *entry
,
4015 u32 delivery_mode
, u32 dest_mode
,
4016 u8 vector
, u32 dest_apicid
, int devid
)
4018 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
4022 irte
->lo
.fields_remap
.int_type
= delivery_mode
;
4023 irte
->lo
.fields_remap
.dm
= dest_mode
;
4024 irte
->hi
.fields
.vector
= vector
;
4025 irte
->lo
.fields_remap
.destination
= dest_apicid
;
4026 irte
->lo
.fields_remap
.valid
= 1;
4029 static void irte_activate(void *entry
, u16 devid
, u16 index
)
4031 union irte
*irte
= (union irte
*) entry
;
4033 irte
->fields
.valid
= 1;
4034 modify_irte(devid
, index
, irte
);
4037 static void irte_ga_activate(void *entry
, u16 devid
, u16 index
)
4039 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
4041 irte
->lo
.fields_remap
.valid
= 1;
4042 modify_irte_ga(devid
, index
, irte
, NULL
);
4045 static void irte_deactivate(void *entry
, u16 devid
, u16 index
)
4047 union irte
*irte
= (union irte
*) entry
;
4049 irte
->fields
.valid
= 0;
4050 modify_irte(devid
, index
, irte
);
4053 static void irte_ga_deactivate(void *entry
, u16 devid
, u16 index
)
4055 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
4057 irte
->lo
.fields_remap
.valid
= 0;
4058 modify_irte_ga(devid
, index
, irte
, NULL
);
4061 static void irte_set_affinity(void *entry
, u16 devid
, u16 index
,
4062 u8 vector
, u32 dest_apicid
)
4064 union irte
*irte
= (union irte
*) entry
;
4066 irte
->fields
.vector
= vector
;
4067 irte
->fields
.destination
= dest_apicid
;
4068 modify_irte(devid
, index
, irte
);
4071 static void irte_ga_set_affinity(void *entry
, u16 devid
, u16 index
,
4072 u8 vector
, u32 dest_apicid
)
4074 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
4075 struct iommu_dev_data
*dev_data
= search_dev_data(devid
);
4077 if (!dev_data
|| !dev_data
->use_vapic
||
4078 !irte
->lo
.fields_remap
.guest_mode
) {
4079 irte
->hi
.fields
.vector
= vector
;
4080 irte
->lo
.fields_remap
.destination
= dest_apicid
;
4081 modify_irte_ga(devid
, index
, irte
, NULL
);
4085 #define IRTE_ALLOCATED (~1U)
4086 static void irte_set_allocated(struct irq_remap_table
*table
, int index
)
4088 table
->table
[index
] = IRTE_ALLOCATED
;
4091 static void irte_ga_set_allocated(struct irq_remap_table
*table
, int index
)
4093 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
4094 struct irte_ga
*irte
= &ptr
[index
];
4096 memset(&irte
->lo
.val
, 0, sizeof(u64
));
4097 memset(&irte
->hi
.val
, 0, sizeof(u64
));
4098 irte
->hi
.fields
.vector
= 0xff;
4101 static bool irte_is_allocated(struct irq_remap_table
*table
, int index
)
4103 union irte
*ptr
= (union irte
*)table
->table
;
4104 union irte
*irte
= &ptr
[index
];
4106 return irte
->val
!= 0;
4109 static bool irte_ga_is_allocated(struct irq_remap_table
*table
, int index
)
4111 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
4112 struct irte_ga
*irte
= &ptr
[index
];
4114 return irte
->hi
.fields
.vector
!= 0;
4117 static void irte_clear_allocated(struct irq_remap_table
*table
, int index
)
4119 table
->table
[index
] = 0;
4122 static void irte_ga_clear_allocated(struct irq_remap_table
*table
, int index
)
4124 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
4125 struct irte_ga
*irte
= &ptr
[index
];
4127 memset(&irte
->lo
.val
, 0, sizeof(u64
));
4128 memset(&irte
->hi
.val
, 0, sizeof(u64
));
4131 static int get_devid(struct irq_alloc_info
*info
)
4135 switch (info
->type
) {
4136 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4137 devid
= get_ioapic_devid(info
->ioapic_id
);
4139 case X86_IRQ_ALLOC_TYPE_HPET
:
4140 devid
= get_hpet_devid(info
->hpet_id
);
4142 case X86_IRQ_ALLOC_TYPE_MSI
:
4143 case X86_IRQ_ALLOC_TYPE_MSIX
:
4144 devid
= get_device_id(&info
->msi_dev
->dev
);
4154 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
4156 struct amd_iommu
*iommu
;
4162 devid
= get_devid(info
);
4164 iommu
= amd_iommu_rlookup_table
[devid
];
4166 return iommu
->ir_domain
;
4172 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
4174 struct amd_iommu
*iommu
;
4180 switch (info
->type
) {
4181 case X86_IRQ_ALLOC_TYPE_MSI
:
4182 case X86_IRQ_ALLOC_TYPE_MSIX
:
4183 devid
= get_device_id(&info
->msi_dev
->dev
);
4187 iommu
= amd_iommu_rlookup_table
[devid
];
4189 return iommu
->msi_domain
;
4198 struct irq_remap_ops amd_iommu_irq_ops
= {
4199 .prepare
= amd_iommu_prepare
,
4200 .enable
= amd_iommu_enable
,
4201 .disable
= amd_iommu_disable
,
4202 .reenable
= amd_iommu_reenable
,
4203 .enable_faulting
= amd_iommu_enable_faulting
,
4204 .get_ir_irq_domain
= get_ir_irq_domain
,
4205 .get_irq_domain
= get_irq_domain
,
4208 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
4209 struct irq_cfg
*irq_cfg
,
4210 struct irq_alloc_info
*info
,
4211 int devid
, int index
, int sub_handle
)
4213 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4214 struct msi_msg
*msg
= &data
->msi_entry
;
4215 struct IO_APIC_route_entry
*entry
;
4216 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
4221 data
->irq_2_irte
.devid
= devid
;
4222 data
->irq_2_irte
.index
= index
+ sub_handle
;
4223 iommu
->irte_ops
->prepare(data
->entry
, apic
->irq_delivery_mode
,
4224 apic
->irq_dest_mode
, irq_cfg
->vector
,
4225 irq_cfg
->dest_apicid
, devid
);
4227 switch (info
->type
) {
4228 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4229 /* Setup IOAPIC entry */
4230 entry
= info
->ioapic_entry
;
4231 info
->ioapic_entry
= NULL
;
4232 memset(entry
, 0, sizeof(*entry
));
4233 entry
->vector
= index
;
4235 entry
->trigger
= info
->ioapic_trigger
;
4236 entry
->polarity
= info
->ioapic_polarity
;
4237 /* Mask level triggered irqs. */
4238 if (info
->ioapic_trigger
)
4242 case X86_IRQ_ALLOC_TYPE_HPET
:
4243 case X86_IRQ_ALLOC_TYPE_MSI
:
4244 case X86_IRQ_ALLOC_TYPE_MSIX
:
4245 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4246 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4247 msg
->data
= irte_info
->index
;
4256 struct amd_irte_ops irte_32_ops
= {
4257 .prepare
= irte_prepare
,
4258 .activate
= irte_activate
,
4259 .deactivate
= irte_deactivate
,
4260 .set_affinity
= irte_set_affinity
,
4261 .set_allocated
= irte_set_allocated
,
4262 .is_allocated
= irte_is_allocated
,
4263 .clear_allocated
= irte_clear_allocated
,
4266 struct amd_irte_ops irte_128_ops
= {
4267 .prepare
= irte_ga_prepare
,
4268 .activate
= irte_ga_activate
,
4269 .deactivate
= irte_ga_deactivate
,
4270 .set_affinity
= irte_ga_set_affinity
,
4271 .set_allocated
= irte_ga_set_allocated
,
4272 .is_allocated
= irte_ga_is_allocated
,
4273 .clear_allocated
= irte_ga_clear_allocated
,
4276 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4277 unsigned int nr_irqs
, void *arg
)
4279 struct irq_alloc_info
*info
= arg
;
4280 struct irq_data
*irq_data
;
4281 struct amd_ir_data
*data
= NULL
;
4282 struct irq_cfg
*cfg
;
4288 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4289 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4293 * With IRQ remapping enabled, don't need contiguous CPU vectors
4294 * to support multiple MSI interrupts.
4296 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4297 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4299 devid
= get_devid(info
);
4303 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4307 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4308 if (get_irq_table(devid
, true))
4309 index
= info
->ioapic_pin
;
4313 index
= alloc_irq_index(devid
, nr_irqs
);
4316 pr_warn("Failed to allocate IRTE\n");
4318 goto out_free_parent
;
4321 for (i
= 0; i
< nr_irqs
; i
++) {
4322 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4323 cfg
= irqd_cfg(irq_data
);
4324 if (!irq_data
|| !cfg
) {
4330 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4334 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
4335 data
->entry
= kzalloc(sizeof(union irte
), GFP_KERNEL
);
4337 data
->entry
= kzalloc(sizeof(struct irte_ga
),
4344 irq_data
->hwirq
= (devid
<< 16) + i
;
4345 irq_data
->chip_data
= data
;
4346 irq_data
->chip
= &amd_ir_chip
;
4347 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4348 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4354 for (i
--; i
>= 0; i
--) {
4355 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4357 kfree(irq_data
->chip_data
);
4359 for (i
= 0; i
< nr_irqs
; i
++)
4360 free_irte(devid
, index
+ i
);
4362 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4366 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4367 unsigned int nr_irqs
)
4369 struct irq_2_irte
*irte_info
;
4370 struct irq_data
*irq_data
;
4371 struct amd_ir_data
*data
;
4374 for (i
= 0; i
< nr_irqs
; i
++) {
4375 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4376 if (irq_data
&& irq_data
->chip_data
) {
4377 data
= irq_data
->chip_data
;
4378 irte_info
= &data
->irq_2_irte
;
4379 free_irte(irte_info
->devid
, irte_info
->index
);
4384 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4387 static void irq_remapping_activate(struct irq_domain
*domain
,
4388 struct irq_data
*irq_data
)
4390 struct amd_ir_data
*data
= irq_data
->chip_data
;
4391 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4392 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4395 iommu
->irte_ops
->activate(data
->entry
, irte_info
->devid
,
4399 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4400 struct irq_data
*irq_data
)
4402 struct amd_ir_data
*data
= irq_data
->chip_data
;
4403 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4404 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4407 iommu
->irte_ops
->deactivate(data
->entry
, irte_info
->devid
,
4411 static const struct irq_domain_ops amd_ir_domain_ops
= {
4412 .alloc
= irq_remapping_alloc
,
4413 .free
= irq_remapping_free
,
4414 .activate
= irq_remapping_activate
,
4415 .deactivate
= irq_remapping_deactivate
,
4418 static int amd_ir_set_vcpu_affinity(struct irq_data
*data
, void *vcpu_info
)
4420 struct amd_iommu
*iommu
;
4421 struct amd_iommu_pi_data
*pi_data
= vcpu_info
;
4422 struct vcpu_data
*vcpu_pi_info
= pi_data
->vcpu_data
;
4423 struct amd_ir_data
*ir_data
= data
->chip_data
;
4424 struct irte_ga
*irte
= (struct irte_ga
*) ir_data
->entry
;
4425 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4426 struct iommu_dev_data
*dev_data
= search_dev_data(irte_info
->devid
);
4429 * This device has never been set up for guest mode.
4430 * we should not modify the IRTE
4432 if (!dev_data
|| !dev_data
->use_vapic
)
4435 pi_data
->ir_data
= ir_data
;
4438 * SVM tries to set up for VAPIC mode, but we are in
4439 * legacy mode. So, we force legacy mode instead.
4441 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
4442 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4444 pi_data
->is_guest_mode
= false;
4447 iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4451 pi_data
->prev_ga_tag
= ir_data
->cached_ga_tag
;
4452 if (pi_data
->is_guest_mode
) {
4454 irte
->hi
.fields
.ga_root_ptr
= (pi_data
->base
>> 12);
4455 irte
->hi
.fields
.vector
= vcpu_pi_info
->vector
;
4456 irte
->lo
.fields_vapic
.ga_log_intr
= 1;
4457 irte
->lo
.fields_vapic
.guest_mode
= 1;
4458 irte
->lo
.fields_vapic
.ga_tag
= pi_data
->ga_tag
;
4460 ir_data
->cached_ga_tag
= pi_data
->ga_tag
;
4463 struct irq_cfg
*cfg
= irqd_cfg(data
);
4467 irte
->hi
.fields
.vector
= cfg
->vector
;
4468 irte
->lo
.fields_remap
.guest_mode
= 0;
4469 irte
->lo
.fields_remap
.destination
= cfg
->dest_apicid
;
4470 irte
->lo
.fields_remap
.int_type
= apic
->irq_delivery_mode
;
4471 irte
->lo
.fields_remap
.dm
= apic
->irq_dest_mode
;
4474 * This communicates the ga_tag back to the caller
4475 * so that it can do all the necessary clean up.
4477 ir_data
->cached_ga_tag
= 0;
4480 return modify_irte_ga(irte_info
->devid
, irte_info
->index
, irte
, ir_data
);
4483 static int amd_ir_set_affinity(struct irq_data
*data
,
4484 const struct cpumask
*mask
, bool force
)
4486 struct amd_ir_data
*ir_data
= data
->chip_data
;
4487 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4488 struct irq_cfg
*cfg
= irqd_cfg(data
);
4489 struct irq_data
*parent
= data
->parent_data
;
4490 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4496 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4497 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4501 * Atomically updates the IRTE with the new destination, vector
4502 * and flushes the interrupt entry cache.
4504 iommu
->irte_ops
->set_affinity(ir_data
->entry
, irte_info
->devid
,
4505 irte_info
->index
, cfg
->vector
, cfg
->dest_apicid
);
4508 * After this point, all the interrupts will start arriving
4509 * at the new destination. So, time to cleanup the previous
4510 * vector allocation.
4512 send_cleanup_vector(cfg
);
4514 return IRQ_SET_MASK_OK_DONE
;
4517 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4519 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4521 *msg
= ir_data
->msi_entry
;
4524 static struct irq_chip amd_ir_chip
= {
4526 .irq_ack
= ir_ack_apic_edge
,
4527 .irq_set_affinity
= amd_ir_set_affinity
,
4528 .irq_set_vcpu_affinity
= amd_ir_set_vcpu_affinity
,
4529 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4532 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4534 struct fwnode_handle
*fn
;
4536 fn
= irq_domain_alloc_named_id_fwnode("AMD-IR", iommu
->index
);
4539 iommu
->ir_domain
= irq_domain_create_tree(fn
, &amd_ir_domain_ops
, iommu
);
4540 irq_domain_free_fwnode(fn
);
4541 if (!iommu
->ir_domain
)
4544 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4545 iommu
->msi_domain
= arch_create_remap_msi_irq_domain(iommu
->ir_domain
,
4551 int amd_iommu_update_ga(int cpu
, bool is_run
, void *data
)
4553 unsigned long flags
;
4554 struct amd_iommu
*iommu
;
4555 struct irq_remap_table
*irt
;
4556 struct amd_ir_data
*ir_data
= (struct amd_ir_data
*)data
;
4557 int devid
= ir_data
->irq_2_irte
.devid
;
4558 struct irte_ga
*entry
= (struct irte_ga
*) ir_data
->entry
;
4559 struct irte_ga
*ref
= (struct irte_ga
*) ir_data
->ref
;
4561 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) ||
4562 !ref
|| !entry
|| !entry
->lo
.fields_vapic
.guest_mode
)
4565 iommu
= amd_iommu_rlookup_table
[devid
];
4569 irt
= get_irq_table(devid
, false);
4573 spin_lock_irqsave(&irt
->lock
, flags
);
4575 if (ref
->lo
.fields_vapic
.guest_mode
) {
4577 ref
->lo
.fields_vapic
.destination
= cpu
;
4578 ref
->lo
.fields_vapic
.is_run
= is_run
;
4582 spin_unlock_irqrestore(&irt
->lock
, flags
);
4584 iommu_flush_irt(iommu
, devid
);
4585 iommu_completion_wait(iommu
);
4588 EXPORT_SYMBOL(amd_iommu_update_ga
);