2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
57 #define AMD_IOMMU_MAPPING_ERROR 0
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
61 #define LOOP_TIMEOUT 100000
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
67 /* Reserved IOVA ranges */
68 #define MSI_RANGE_START (0xfee00000)
69 #define MSI_RANGE_END (0xfeefffff)
70 #define HT_RANGE_START (0xfd00000000ULL)
71 #define HT_RANGE_END (0xffffffffffULL)
74 * This bitmap is used to advertise the page sizes our hardware support
75 * to the IOMMU core, which will then use this information to split
76 * physically contiguous memory regions it is mapping into page sizes
79 * 512GB Pages are not supported due to a hardware bug
81 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83 static DEFINE_RWLOCK(amd_iommu_devtable_lock
);
85 /* List of all available dev_data structures */
86 static LIST_HEAD(dev_data_list
);
87 static DEFINE_SPINLOCK(dev_data_list_lock
);
89 LIST_HEAD(ioapic_map
);
91 LIST_HEAD(acpihid_map
);
94 * Domain for untranslated devices - only allocated
95 * if iommu=pt passed on kernel cmd line.
97 const struct iommu_ops amd_iommu_ops
;
99 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
100 int amd_iommu_max_glx_val
= -1;
102 static const struct dma_map_ops amd_iommu_dma_ops
;
105 * general struct to manage commands send to an IOMMU
111 struct kmem_cache
*amd_iommu_irq_cache
;
113 static void update_domain(struct protection_domain
*domain
);
114 static int protection_domain_init(struct protection_domain
*domain
);
115 static void detach_device(struct device
*dev
);
116 static void iova_domain_flush_tlb(struct iova_domain
*iovad
);
119 * Data container for a dma_ops specific protection domain
121 struct dma_ops_domain
{
122 /* generic protection domain information */
123 struct protection_domain domain
;
126 struct iova_domain iovad
;
129 static struct iova_domain reserved_iova_ranges
;
130 static struct lock_class_key reserved_rbtree_key
;
132 /****************************************************************************
136 ****************************************************************************/
138 static inline int match_hid_uid(struct device
*dev
,
139 struct acpihid_map_entry
*entry
)
141 const char *hid
, *uid
;
143 hid
= acpi_device_hid(ACPI_COMPANION(dev
));
144 uid
= acpi_device_uid(ACPI_COMPANION(dev
));
150 return strcmp(hid
, entry
->hid
);
153 return strcmp(hid
, entry
->hid
);
155 return (strcmp(hid
, entry
->hid
) || strcmp(uid
, entry
->uid
));
158 static inline u16
get_pci_device_id(struct device
*dev
)
160 struct pci_dev
*pdev
= to_pci_dev(dev
);
162 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
165 static inline int get_acpihid_device_id(struct device
*dev
,
166 struct acpihid_map_entry
**entry
)
168 struct acpihid_map_entry
*p
;
170 list_for_each_entry(p
, &acpihid_map
, list
) {
171 if (!match_hid_uid(dev
, p
)) {
180 static inline int get_device_id(struct device
*dev
)
185 devid
= get_pci_device_id(dev
);
187 devid
= get_acpihid_device_id(dev
, NULL
);
192 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
194 return container_of(dom
, struct protection_domain
, domain
);
197 static struct dma_ops_domain
* to_dma_ops_domain(struct protection_domain
*domain
)
199 BUG_ON(domain
->flags
!= PD_DMA_OPS_MASK
);
200 return container_of(domain
, struct dma_ops_domain
, domain
);
203 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
205 struct iommu_dev_data
*dev_data
;
208 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
212 dev_data
->devid
= devid
;
214 spin_lock_irqsave(&dev_data_list_lock
, flags
);
215 list_add_tail(&dev_data
->dev_data_list
, &dev_data_list
);
216 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
218 ratelimit_default_init(&dev_data
->rs
);
223 static struct iommu_dev_data
*search_dev_data(u16 devid
)
225 struct iommu_dev_data
*dev_data
;
228 spin_lock_irqsave(&dev_data_list_lock
, flags
);
229 list_for_each_entry(dev_data
, &dev_data_list
, dev_data_list
) {
230 if (dev_data
->devid
== devid
)
237 spin_unlock_irqrestore(&dev_data_list_lock
, flags
);
242 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
244 *(u16
*)data
= alias
;
248 static u16
get_alias(struct device
*dev
)
250 struct pci_dev
*pdev
= to_pci_dev(dev
);
251 u16 devid
, ivrs_alias
, pci_alias
;
253 /* The callers make sure that get_device_id() does not fail here */
254 devid
= get_device_id(dev
);
255 ivrs_alias
= amd_iommu_alias_table
[devid
];
256 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
258 if (ivrs_alias
== pci_alias
)
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
270 if (ivrs_alias
== devid
) {
271 if (!amd_iommu_rlookup_table
[pci_alias
]) {
272 amd_iommu_rlookup_table
[pci_alias
] =
273 amd_iommu_rlookup_table
[devid
];
274 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
275 amd_iommu_dev_table
[devid
].data
,
276 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
282 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
285 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
286 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
287 PCI_FUNC(pci_alias
));
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
293 if (pci_alias
== devid
&&
294 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
295 pci_add_dma_alias(pdev
, ivrs_alias
& 0xff);
296 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
304 static struct iommu_dev_data
*find_dev_data(u16 devid
)
306 struct iommu_dev_data
*dev_data
;
307 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
309 dev_data
= search_dev_data(devid
);
311 if (dev_data
== NULL
) {
312 dev_data
= alloc_dev_data(devid
);
314 if (translation_pre_enabled(iommu
))
315 dev_data
->defer_attach
= true;
321 struct iommu_dev_data
*get_dev_data(struct device
*dev
)
323 return dev
->archdata
.iommu
;
325 EXPORT_SYMBOL(get_dev_data
);
328 * Find or create an IOMMU group for a acpihid device.
330 static struct iommu_group
*acpihid_device_group(struct device
*dev
)
332 struct acpihid_map_entry
*p
, *entry
= NULL
;
335 devid
= get_acpihid_device_id(dev
, &entry
);
337 return ERR_PTR(devid
);
339 list_for_each_entry(p
, &acpihid_map
, list
) {
340 if ((devid
== p
->devid
) && p
->group
)
341 entry
->group
= p
->group
;
345 entry
->group
= generic_device_group(dev
);
347 iommu_group_ref_get(entry
->group
);
352 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
354 static const int caps
[] = {
357 PCI_EXT_CAP_ID_PASID
,
361 for (i
= 0; i
< 3; ++i
) {
362 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
370 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
372 struct iommu_dev_data
*dev_data
;
374 dev_data
= get_dev_data(&pdev
->dev
);
376 return dev_data
->errata
& (1 << erratum
) ? true : false;
380 * This function checks if the driver got a valid device from the caller to
381 * avoid dereferencing invalid pointers.
383 static bool check_device(struct device
*dev
)
387 if (!dev
|| !dev
->dma_mask
)
390 devid
= get_device_id(dev
);
394 /* Out of our scope? */
395 if (devid
> amd_iommu_last_bdf
)
398 if (amd_iommu_rlookup_table
[devid
] == NULL
)
404 static void init_iommu_group(struct device
*dev
)
406 struct iommu_group
*group
;
408 group
= iommu_group_get_for_dev(dev
);
412 iommu_group_put(group
);
415 static int iommu_init_device(struct device
*dev
)
417 struct iommu_dev_data
*dev_data
;
418 struct amd_iommu
*iommu
;
421 if (dev
->archdata
.iommu
)
424 devid
= get_device_id(dev
);
428 iommu
= amd_iommu_rlookup_table
[devid
];
430 dev_data
= find_dev_data(devid
);
434 dev_data
->alias
= get_alias(dev
);
436 if (dev_is_pci(dev
) && pci_iommuv2_capable(to_pci_dev(dev
))) {
437 struct amd_iommu
*iommu
;
439 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
440 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
443 dev
->archdata
.iommu
= dev_data
;
445 iommu_device_link(&iommu
->iommu
, dev
);
450 static void iommu_ignore_device(struct device
*dev
)
455 devid
= get_device_id(dev
);
459 alias
= get_alias(dev
);
461 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
462 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
464 amd_iommu_rlookup_table
[devid
] = NULL
;
465 amd_iommu_rlookup_table
[alias
] = NULL
;
468 static void iommu_uninit_device(struct device
*dev
)
470 struct iommu_dev_data
*dev_data
;
471 struct amd_iommu
*iommu
;
474 devid
= get_device_id(dev
);
478 iommu
= amd_iommu_rlookup_table
[devid
];
480 dev_data
= search_dev_data(devid
);
484 if (dev_data
->domain
)
487 iommu_device_unlink(&iommu
->iommu
, dev
);
489 iommu_group_remove_device(dev
);
495 * We keep dev_data around for unplugged devices and reuse it when the
496 * device is re-plugged - not doing so would introduce a ton of races.
500 /****************************************************************************
502 * Interrupt handling functions
504 ****************************************************************************/
506 static void dump_dte_entry(u16 devid
)
510 for (i
= 0; i
< 4; ++i
)
511 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i
,
512 amd_iommu_dev_table
[devid
].data
[i
]);
515 static void dump_command(unsigned long phys_addr
)
517 struct iommu_cmd
*cmd
= iommu_phys_to_virt(phys_addr
);
520 for (i
= 0; i
< 4; ++i
)
521 pr_err("AMD-Vi: CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
524 static void amd_iommu_report_page_fault(u16 devid
, u16 domain_id
,
525 u64 address
, int flags
)
527 struct iommu_dev_data
*dev_data
= NULL
;
528 struct pci_dev
*pdev
;
530 pdev
= pci_get_bus_and_slot(PCI_BUS_NUM(devid
), devid
& 0xff);
532 dev_data
= get_dev_data(&pdev
->dev
);
534 if (dev_data
&& __ratelimit(&dev_data
->rs
)) {
535 dev_err(&pdev
->dev
, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
536 domain_id
, address
, flags
);
537 } else if (printk_ratelimit()) {
538 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
539 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
540 domain_id
, address
, flags
);
547 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
549 int type
, devid
, domid
, flags
;
550 volatile u32
*event
= __evt
;
555 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
556 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
557 domid
= (event
[1] >> EVENT_DOMID_SHIFT
) & EVENT_DOMID_MASK
;
558 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
559 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
562 /* Did we hit the erratum? */
563 if (++count
== LOOP_TIMEOUT
) {
564 pr_err("AMD-Vi: No event written to event log\n");
571 if (type
== EVENT_TYPE_IO_FAULT
) {
572 amd_iommu_report_page_fault(devid
, domid
, address
, flags
);
575 printk(KERN_ERR
"AMD-Vi: Event logged [");
579 case EVENT_TYPE_ILL_DEV
:
580 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
581 "address=0x%016llx flags=0x%04x]\n",
582 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
584 dump_dte_entry(devid
);
586 case EVENT_TYPE_DEV_TAB_ERR
:
587 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
588 "address=0x%016llx flags=0x%04x]\n",
589 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
592 case EVENT_TYPE_PAGE_TAB_ERR
:
593 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
594 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
595 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
596 domid
, address
, flags
);
598 case EVENT_TYPE_ILL_CMD
:
599 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address
);
600 dump_command(address
);
602 case EVENT_TYPE_CMD_HARD_ERR
:
603 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
604 "flags=0x%04x]\n", address
, flags
);
606 case EVENT_TYPE_IOTLB_INV_TO
:
607 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
608 "address=0x%016llx]\n",
609 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
612 case EVENT_TYPE_INV_DEV_REQ
:
613 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
614 "address=0x%016llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
619 printk(KERN_ERR
"UNKNOWN type=0x%02x]\n", type
);
622 memset(__evt
, 0, 4 * sizeof(u32
));
625 static void iommu_poll_events(struct amd_iommu
*iommu
)
629 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
630 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
632 while (head
!= tail
) {
633 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
634 head
= (head
+ EVENT_ENTRY_SIZE
) % EVT_BUFFER_SIZE
;
637 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
640 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
642 struct amd_iommu_fault fault
;
644 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
645 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
649 fault
.address
= raw
[1];
650 fault
.pasid
= PPR_PASID(raw
[0]);
651 fault
.device_id
= PPR_DEVID(raw
[0]);
652 fault
.tag
= PPR_TAG(raw
[0]);
653 fault
.flags
= PPR_FLAGS(raw
[0]);
655 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
658 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
662 if (iommu
->ppr_log
== NULL
)
665 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
666 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
668 while (head
!= tail
) {
673 raw
= (u64
*)(iommu
->ppr_log
+ head
);
676 * Hardware bug: Interrupt may arrive before the entry is
677 * written to memory. If this happens we need to wait for the
680 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
681 if (PPR_REQ_TYPE(raw
[0]) != 0)
686 /* Avoid memcpy function-call overhead */
691 * To detect the hardware bug we need to clear the entry
694 raw
[0] = raw
[1] = 0UL;
696 /* Update head pointer of hardware ring-buffer */
697 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
698 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
700 /* Handle PPR entry */
701 iommu_handle_ppr_entry(iommu
, entry
);
703 /* Refresh ring-buffer information */
704 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
705 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
709 #ifdef CONFIG_IRQ_REMAP
710 static int (*iommu_ga_log_notifier
)(u32
);
712 int amd_iommu_register_ga_log_notifier(int (*notifier
)(u32
))
714 iommu_ga_log_notifier
= notifier
;
718 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier
);
720 static void iommu_poll_ga_log(struct amd_iommu
*iommu
)
722 u32 head
, tail
, cnt
= 0;
724 if (iommu
->ga_log
== NULL
)
727 head
= readl(iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
728 tail
= readl(iommu
->mmio_base
+ MMIO_GA_TAIL_OFFSET
);
730 while (head
!= tail
) {
734 raw
= (u64
*)(iommu
->ga_log
+ head
);
737 /* Avoid memcpy function-call overhead */
740 /* Update head pointer of hardware ring-buffer */
741 head
= (head
+ GA_ENTRY_SIZE
) % GA_LOG_SIZE
;
742 writel(head
, iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
744 /* Handle GA entry */
745 switch (GA_REQ_TYPE(log_entry
)) {
747 if (!iommu_ga_log_notifier
)
750 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
751 __func__
, GA_DEVID(log_entry
),
754 if (iommu_ga_log_notifier(GA_TAG(log_entry
)) != 0)
755 pr_err("AMD-Vi: GA log notifier failed.\n");
762 #endif /* CONFIG_IRQ_REMAP */
764 #define AMD_IOMMU_INT_MASK \
765 (MMIO_STATUS_EVT_INT_MASK | \
766 MMIO_STATUS_PPR_INT_MASK | \
767 MMIO_STATUS_GALOG_INT_MASK)
769 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
771 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
772 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
774 while (status
& AMD_IOMMU_INT_MASK
) {
775 /* Enable EVT and PPR and GA interrupts again */
776 writel(AMD_IOMMU_INT_MASK
,
777 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
779 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
780 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
781 iommu_poll_events(iommu
);
784 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
785 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
786 iommu_poll_ppr_log(iommu
);
789 #ifdef CONFIG_IRQ_REMAP
790 if (status
& MMIO_STATUS_GALOG_INT_MASK
) {
791 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
792 iommu_poll_ga_log(iommu
);
797 * Hardware bug: ERBT1312
798 * When re-enabling interrupt (by writing 1
799 * to clear the bit), the hardware might also try to set
800 * the interrupt bit in the event status register.
801 * In this scenario, the bit will be set, and disable
802 * subsequent interrupts.
804 * Workaround: The IOMMU driver should read back the
805 * status register and check if the interrupt bits are cleared.
806 * If not, driver will need to go through the interrupt handler
807 * again and re-clear the bits
809 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
814 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
816 return IRQ_WAKE_THREAD
;
819 /****************************************************************************
821 * IOMMU command queuing functions
823 ****************************************************************************/
825 static int wait_on_sem(volatile u64
*sem
)
829 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
834 if (i
== LOOP_TIMEOUT
) {
835 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
842 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
843 struct iommu_cmd
*cmd
)
847 target
= iommu
->cmd_buf
+ iommu
->cmd_buf_tail
;
849 iommu
->cmd_buf_tail
+= sizeof(*cmd
);
850 iommu
->cmd_buf_tail
%= CMD_BUFFER_SIZE
;
852 /* Copy command to buffer */
853 memcpy(target
, cmd
, sizeof(*cmd
));
855 /* Tell the IOMMU about it */
856 writel(iommu
->cmd_buf_tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
859 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
861 u64 paddr
= iommu_virt_to_phys((void *)address
);
863 WARN_ON(address
& 0x7ULL
);
865 memset(cmd
, 0, sizeof(*cmd
));
866 cmd
->data
[0] = lower_32_bits(paddr
) | CMD_COMPL_WAIT_STORE_MASK
;
867 cmd
->data
[1] = upper_32_bits(paddr
);
869 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
872 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
874 memset(cmd
, 0, sizeof(*cmd
));
875 cmd
->data
[0] = devid
;
876 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
879 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
880 size_t size
, u16 domid
, int pde
)
885 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
890 * If we have to flush more than one page, flush all
891 * TLB entries for this domain
893 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
897 address
&= PAGE_MASK
;
899 memset(cmd
, 0, sizeof(*cmd
));
900 cmd
->data
[1] |= domid
;
901 cmd
->data
[2] = lower_32_bits(address
);
902 cmd
->data
[3] = upper_32_bits(address
);
903 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
904 if (s
) /* size bit - we flush more than one 4kb page */
905 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
906 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
907 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
910 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
911 u64 address
, size_t size
)
916 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
921 * If we have to flush more than one page, flush all
922 * TLB entries for this domain
924 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
928 address
&= PAGE_MASK
;
930 memset(cmd
, 0, sizeof(*cmd
));
931 cmd
->data
[0] = devid
;
932 cmd
->data
[0] |= (qdep
& 0xff) << 24;
933 cmd
->data
[1] = devid
;
934 cmd
->data
[2] = lower_32_bits(address
);
935 cmd
->data
[3] = upper_32_bits(address
);
936 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
938 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
941 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
942 u64 address
, bool size
)
944 memset(cmd
, 0, sizeof(*cmd
));
946 address
&= ~(0xfffULL
);
948 cmd
->data
[0] = pasid
;
949 cmd
->data
[1] = domid
;
950 cmd
->data
[2] = lower_32_bits(address
);
951 cmd
->data
[3] = upper_32_bits(address
);
952 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
953 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
955 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
956 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
959 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
960 int qdep
, u64 address
, bool size
)
962 memset(cmd
, 0, sizeof(*cmd
));
964 address
&= ~(0xfffULL
);
966 cmd
->data
[0] = devid
;
967 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
968 cmd
->data
[0] |= (qdep
& 0xff) << 24;
969 cmd
->data
[1] = devid
;
970 cmd
->data
[1] |= (pasid
& 0xff) << 16;
971 cmd
->data
[2] = lower_32_bits(address
);
972 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
973 cmd
->data
[3] = upper_32_bits(address
);
975 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
976 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
979 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
980 int status
, int tag
, bool gn
)
982 memset(cmd
, 0, sizeof(*cmd
));
984 cmd
->data
[0] = devid
;
986 cmd
->data
[1] = pasid
;
987 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
989 cmd
->data
[3] = tag
& 0x1ff;
990 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
992 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
995 static void build_inv_all(struct iommu_cmd
*cmd
)
997 memset(cmd
, 0, sizeof(*cmd
));
998 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
1001 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
1003 memset(cmd
, 0, sizeof(*cmd
));
1004 cmd
->data
[0] = devid
;
1005 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
1009 * Writes the command to the IOMMUs command buffer and informs the
1010 * hardware about the new command.
1012 static int __iommu_queue_command_sync(struct amd_iommu
*iommu
,
1013 struct iommu_cmd
*cmd
,
1016 unsigned int count
= 0;
1017 u32 left
, next_tail
;
1019 next_tail
= (iommu
->cmd_buf_tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
1021 left
= (iommu
->cmd_buf_head
- next_tail
) % CMD_BUFFER_SIZE
;
1024 /* Skip udelay() the first time around */
1026 if (count
== LOOP_TIMEOUT
) {
1027 pr_err("AMD-Vi: Command buffer timeout\n");
1034 /* Update head and recheck remaining space */
1035 iommu
->cmd_buf_head
= readl(iommu
->mmio_base
+
1036 MMIO_CMD_HEAD_OFFSET
);
1041 copy_cmd_to_buffer(iommu
, cmd
);
1043 /* Do we need to make sure all commands are processed? */
1044 iommu
->need_sync
= sync
;
1049 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
1050 struct iommu_cmd
*cmd
,
1053 unsigned long flags
;
1056 spin_lock_irqsave(&iommu
->lock
, flags
);
1057 ret
= __iommu_queue_command_sync(iommu
, cmd
, sync
);
1058 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1063 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1065 return iommu_queue_command_sync(iommu
, cmd
, true);
1069 * This function queues a completion wait command into the command
1070 * buffer of an IOMMU
1072 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1074 struct iommu_cmd cmd
;
1075 unsigned long flags
;
1078 if (!iommu
->need_sync
)
1082 build_completion_wait(&cmd
, (u64
)&iommu
->cmd_sem
);
1084 spin_lock_irqsave(&iommu
->lock
, flags
);
1088 ret
= __iommu_queue_command_sync(iommu
, &cmd
, false);
1092 ret
= wait_on_sem(&iommu
->cmd_sem
);
1095 spin_unlock_irqrestore(&iommu
->lock
, flags
);
1100 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1102 struct iommu_cmd cmd
;
1104 build_inv_dte(&cmd
, devid
);
1106 return iommu_queue_command(iommu
, &cmd
);
1109 static void amd_iommu_flush_dte_all(struct amd_iommu
*iommu
)
1113 for (devid
= 0; devid
<= 0xffff; ++devid
)
1114 iommu_flush_dte(iommu
, devid
);
1116 iommu_completion_wait(iommu
);
1120 * This function uses heavy locking and may disable irqs for some time. But
1121 * this is no issue because it is only called during resume.
1123 static void amd_iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1127 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1128 struct iommu_cmd cmd
;
1129 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1131 iommu_queue_command(iommu
, &cmd
);
1134 iommu_completion_wait(iommu
);
1137 static void amd_iommu_flush_all(struct amd_iommu
*iommu
)
1139 struct iommu_cmd cmd
;
1141 build_inv_all(&cmd
);
1143 iommu_queue_command(iommu
, &cmd
);
1144 iommu_completion_wait(iommu
);
1147 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1149 struct iommu_cmd cmd
;
1151 build_inv_irt(&cmd
, devid
);
1153 iommu_queue_command(iommu
, &cmd
);
1156 static void amd_iommu_flush_irt_all(struct amd_iommu
*iommu
)
1160 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1161 iommu_flush_irt(iommu
, devid
);
1163 iommu_completion_wait(iommu
);
1166 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1168 if (iommu_feature(iommu
, FEATURE_IA
)) {
1169 amd_iommu_flush_all(iommu
);
1171 amd_iommu_flush_dte_all(iommu
);
1172 amd_iommu_flush_irt_all(iommu
);
1173 amd_iommu_flush_tlb_all(iommu
);
1178 * Command send function for flushing on-device TLB
1180 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1181 u64 address
, size_t size
)
1183 struct amd_iommu
*iommu
;
1184 struct iommu_cmd cmd
;
1187 qdep
= dev_data
->ats
.qdep
;
1188 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1190 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1192 return iommu_queue_command(iommu
, &cmd
);
1196 * Command send function for invalidating a device table entry
1198 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1200 struct amd_iommu
*iommu
;
1204 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1205 alias
= dev_data
->alias
;
1207 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1208 if (!ret
&& alias
!= dev_data
->devid
)
1209 ret
= iommu_flush_dte(iommu
, alias
);
1213 if (dev_data
->ats
.enabled
)
1214 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1220 * TLB invalidation function which is called from the mapping functions.
1221 * It invalidates a single PTE if the range to flush is within a single
1222 * page. Otherwise it flushes the whole TLB of the IOMMU.
1224 static void __domain_flush_pages(struct protection_domain
*domain
,
1225 u64 address
, size_t size
, int pde
)
1227 struct iommu_dev_data
*dev_data
;
1228 struct iommu_cmd cmd
;
1231 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1233 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1234 if (!domain
->dev_iommu
[i
])
1238 * Devices of this domain are behind this IOMMU
1239 * We need a TLB flush
1241 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1244 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1246 if (!dev_data
->ats
.enabled
)
1249 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1255 static void domain_flush_pages(struct protection_domain
*domain
,
1256 u64 address
, size_t size
)
1258 __domain_flush_pages(domain
, address
, size
, 0);
1261 /* Flush the whole IO/TLB for a given protection domain */
1262 static void domain_flush_tlb(struct protection_domain
*domain
)
1264 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1267 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1268 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1270 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1273 static void domain_flush_complete(struct protection_domain
*domain
)
1277 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1278 if (domain
&& !domain
->dev_iommu
[i
])
1282 * Devices of this domain are behind this IOMMU
1283 * We need to wait for completion of all commands.
1285 iommu_completion_wait(amd_iommus
[i
]);
1291 * This function flushes the DTEs for all devices in domain
1293 static void domain_flush_devices(struct protection_domain
*domain
)
1295 struct iommu_dev_data
*dev_data
;
1297 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1298 device_flush_dte(dev_data
);
1301 /****************************************************************************
1303 * The functions below are used the create the page table mappings for
1304 * unity mapped regions.
1306 ****************************************************************************/
1309 * This function is used to add another level to an IO page table. Adding
1310 * another level increases the size of the address space by 9 bits to a size up
1313 static bool increase_address_space(struct protection_domain
*domain
,
1318 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1319 /* address space already 64 bit large */
1322 pte
= (void *)get_zeroed_page(gfp
);
1326 *pte
= PM_LEVEL_PDE(domain
->mode
,
1327 iommu_virt_to_phys(domain
->pt_root
));
1328 domain
->pt_root
= pte
;
1330 domain
->updated
= true;
1335 static u64
*alloc_pte(struct protection_domain
*domain
,
1336 unsigned long address
,
1337 unsigned long page_size
,
1344 BUG_ON(!is_power_of_2(page_size
));
1346 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1347 increase_address_space(domain
, gfp
);
1349 level
= domain
->mode
- 1;
1350 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1351 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1352 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1354 while (level
> end_lvl
) {
1359 if (!IOMMU_PTE_PRESENT(__pte
)) {
1360 page
= (u64
*)get_zeroed_page(gfp
);
1364 __npte
= PM_LEVEL_PDE(level
, iommu_virt_to_phys(page
));
1366 /* pte could have been changed somewhere. */
1367 if (cmpxchg64(pte
, __pte
, __npte
) != __pte
) {
1368 free_page((unsigned long)page
);
1373 /* No level skipping support yet */
1374 if (PM_PTE_LEVEL(*pte
) != level
)
1379 pte
= IOMMU_PTE_PAGE(*pte
);
1381 if (pte_page
&& level
== end_lvl
)
1384 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1391 * This function checks if there is a PTE for a given dma address. If
1392 * there is one, it returns the pointer to it.
1394 static u64
*fetch_pte(struct protection_domain
*domain
,
1395 unsigned long address
,
1396 unsigned long *page_size
)
1401 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1404 level
= domain
->mode
- 1;
1405 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1406 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1411 if (!IOMMU_PTE_PRESENT(*pte
))
1415 if (PM_PTE_LEVEL(*pte
) == 7 ||
1416 PM_PTE_LEVEL(*pte
) == 0)
1419 /* No level skipping support yet */
1420 if (PM_PTE_LEVEL(*pte
) != level
)
1425 /* Walk to the next level */
1426 pte
= IOMMU_PTE_PAGE(*pte
);
1427 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1428 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1431 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1432 unsigned long pte_mask
;
1435 * If we have a series of large PTEs, make
1436 * sure to return a pointer to the first one.
1438 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1439 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1440 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1447 * Generic mapping functions. It maps a physical address into a DMA
1448 * address space. It allocates the page table pages if necessary.
1449 * In the future it can be extended to a generic mapping function
1450 * supporting all features of AMD IOMMU page tables like level skipping
1451 * and full 64 bit address spaces.
1453 static int iommu_map_page(struct protection_domain
*dom
,
1454 unsigned long bus_addr
,
1455 unsigned long phys_addr
,
1456 unsigned long page_size
,
1463 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1464 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1466 if (!(prot
& IOMMU_PROT_MASK
))
1469 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1470 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, gfp
);
1475 for (i
= 0; i
< count
; ++i
)
1476 if (IOMMU_PTE_PRESENT(pte
[i
]))
1480 __pte
= PAGE_SIZE_PTE(__sme_set(phys_addr
), page_size
);
1481 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_PR
| IOMMU_PTE_FC
;
1483 __pte
= __sme_set(phys_addr
) | IOMMU_PTE_PR
| IOMMU_PTE_FC
;
1485 if (prot
& IOMMU_PROT_IR
)
1486 __pte
|= IOMMU_PTE_IR
;
1487 if (prot
& IOMMU_PROT_IW
)
1488 __pte
|= IOMMU_PTE_IW
;
1490 for (i
= 0; i
< count
; ++i
)
1498 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1499 unsigned long bus_addr
,
1500 unsigned long page_size
)
1502 unsigned long long unmapped
;
1503 unsigned long unmap_size
;
1506 BUG_ON(!is_power_of_2(page_size
));
1510 while (unmapped
< page_size
) {
1512 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1517 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1518 for (i
= 0; i
< count
; i
++)
1522 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1523 unmapped
+= unmap_size
;
1526 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1531 /****************************************************************************
1533 * The next functions belong to the address allocator for the dma_ops
1534 * interface functions.
1536 ****************************************************************************/
1539 static unsigned long dma_ops_alloc_iova(struct device
*dev
,
1540 struct dma_ops_domain
*dma_dom
,
1541 unsigned int pages
, u64 dma_mask
)
1543 unsigned long pfn
= 0;
1545 pages
= __roundup_pow_of_two(pages
);
1547 if (dma_mask
> DMA_BIT_MASK(32))
1548 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1549 IOVA_PFN(DMA_BIT_MASK(32)), false);
1552 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1553 IOVA_PFN(dma_mask
), true);
1555 return (pfn
<< PAGE_SHIFT
);
1558 static void dma_ops_free_iova(struct dma_ops_domain
*dma_dom
,
1559 unsigned long address
,
1562 pages
= __roundup_pow_of_two(pages
);
1563 address
>>= PAGE_SHIFT
;
1565 free_iova_fast(&dma_dom
->iovad
, address
, pages
);
1568 /****************************************************************************
1570 * The next functions belong to the domain allocation. A domain is
1571 * allocated for every IOMMU as the default domain. If device isolation
1572 * is enabled, every device get its own domain. The most important thing
1573 * about domains is the page table mapping the DMA address space they
1576 ****************************************************************************/
1579 * This function adds a protection domain to the global protection domain list
1581 static void add_domain_to_list(struct protection_domain
*domain
)
1583 unsigned long flags
;
1585 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1586 list_add(&domain
->list
, &amd_iommu_pd_list
);
1587 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1591 * This function removes a protection domain to the global
1592 * protection domain list
1594 static void del_domain_from_list(struct protection_domain
*domain
)
1596 unsigned long flags
;
1598 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1599 list_del(&domain
->list
);
1600 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1603 static u16
domain_id_alloc(void)
1605 unsigned long flags
;
1608 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1609 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1611 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1612 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1615 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1620 static void domain_id_free(int id
)
1622 unsigned long flags
;
1624 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
1625 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1626 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1627 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
1630 #define DEFINE_FREE_PT_FN(LVL, FN) \
1631 static void free_pt_##LVL (unsigned long __pt) \
1639 for (i = 0; i < 512; ++i) { \
1640 /* PTE present? */ \
1641 if (!IOMMU_PTE_PRESENT(pt[i])) \
1645 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1646 PM_PTE_LEVEL(pt[i]) == 7) \
1649 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1652 free_page((unsigned long)pt); \
1655 DEFINE_FREE_PT_FN(l2
, free_page
)
1656 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1657 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1658 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1659 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1661 static void free_pagetable(struct protection_domain
*domain
)
1663 unsigned long root
= (unsigned long)domain
->pt_root
;
1665 switch (domain
->mode
) {
1666 case PAGE_MODE_NONE
:
1668 case PAGE_MODE_1_LEVEL
:
1671 case PAGE_MODE_2_LEVEL
:
1674 case PAGE_MODE_3_LEVEL
:
1677 case PAGE_MODE_4_LEVEL
:
1680 case PAGE_MODE_5_LEVEL
:
1683 case PAGE_MODE_6_LEVEL
:
1691 static void free_gcr3_tbl_level1(u64
*tbl
)
1696 for (i
= 0; i
< 512; ++i
) {
1697 if (!(tbl
[i
] & GCR3_VALID
))
1700 ptr
= iommu_phys_to_virt(tbl
[i
] & PAGE_MASK
);
1702 free_page((unsigned long)ptr
);
1706 static void free_gcr3_tbl_level2(u64
*tbl
)
1711 for (i
= 0; i
< 512; ++i
) {
1712 if (!(tbl
[i
] & GCR3_VALID
))
1715 ptr
= iommu_phys_to_virt(tbl
[i
] & PAGE_MASK
);
1717 free_gcr3_tbl_level1(ptr
);
1721 static void free_gcr3_table(struct protection_domain
*domain
)
1723 if (domain
->glx
== 2)
1724 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1725 else if (domain
->glx
== 1)
1726 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1728 BUG_ON(domain
->glx
!= 0);
1730 free_page((unsigned long)domain
->gcr3_tbl
);
1733 static void dma_ops_domain_flush_tlb(struct dma_ops_domain
*dom
)
1735 domain_flush_tlb(&dom
->domain
);
1736 domain_flush_complete(&dom
->domain
);
1739 static void iova_domain_flush_tlb(struct iova_domain
*iovad
)
1741 struct dma_ops_domain
*dom
;
1743 dom
= container_of(iovad
, struct dma_ops_domain
, iovad
);
1745 dma_ops_domain_flush_tlb(dom
);
1749 * Free a domain, only used if something went wrong in the
1750 * allocation path and we need to free an already allocated page table
1752 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1757 del_domain_from_list(&dom
->domain
);
1759 put_iova_domain(&dom
->iovad
);
1761 free_pagetable(&dom
->domain
);
1764 domain_id_free(dom
->domain
.id
);
1770 * Allocates a new protection domain usable for the dma_ops functions.
1771 * It also initializes the page table and the address allocator data
1772 * structures required for the dma_ops interface
1774 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1776 struct dma_ops_domain
*dma_dom
;
1778 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1782 if (protection_domain_init(&dma_dom
->domain
))
1785 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
1786 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1787 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1788 if (!dma_dom
->domain
.pt_root
)
1791 init_iova_domain(&dma_dom
->iovad
, PAGE_SIZE
, IOVA_START_PFN
);
1793 if (init_iova_flush_queue(&dma_dom
->iovad
, iova_domain_flush_tlb
, NULL
))
1796 /* Initialize reserved ranges */
1797 copy_reserved_iova(&reserved_iova_ranges
, &dma_dom
->iovad
);
1799 add_domain_to_list(&dma_dom
->domain
);
1804 dma_ops_domain_free(dma_dom
);
1810 * little helper function to check whether a given protection domain is a
1813 static bool dma_ops_domain(struct protection_domain
*domain
)
1815 return domain
->flags
& PD_DMA_OPS_MASK
;
1818 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
, bool ats
)
1823 if (domain
->mode
!= PAGE_MODE_NONE
)
1824 pte_root
= iommu_virt_to_phys(domain
->pt_root
);
1826 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1827 << DEV_ENTRY_MODE_SHIFT
;
1828 pte_root
|= DTE_FLAG_IR
| DTE_FLAG_IW
| DTE_FLAG_V
| DTE_FLAG_TV
;
1830 flags
= amd_iommu_dev_table
[devid
].data
[1];
1833 flags
|= DTE_FLAG_IOTLB
;
1835 if (domain
->flags
& PD_IOMMUV2_MASK
) {
1836 u64 gcr3
= iommu_virt_to_phys(domain
->gcr3_tbl
);
1837 u64 glx
= domain
->glx
;
1840 pte_root
|= DTE_FLAG_GV
;
1841 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
1843 /* First mask out possible old values for GCR3 table */
1844 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
1847 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
1850 /* Encode GCR3 table into DTE */
1851 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
1854 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
1857 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
1861 flags
&= ~DEV_DOMID_MASK
;
1862 flags
|= domain
->id
;
1864 amd_iommu_dev_table
[devid
].data
[1] = flags
;
1865 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
1868 static void clear_dte_entry(u16 devid
)
1870 /* remove entry from the device table seen by the hardware */
1871 amd_iommu_dev_table
[devid
].data
[0] = DTE_FLAG_V
| DTE_FLAG_TV
;
1872 amd_iommu_dev_table
[devid
].data
[1] &= DTE_FLAG_MASK
;
1874 amd_iommu_apply_erratum_63(devid
);
1877 static void do_attach(struct iommu_dev_data
*dev_data
,
1878 struct protection_domain
*domain
)
1880 struct amd_iommu
*iommu
;
1884 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1885 alias
= dev_data
->alias
;
1886 ats
= dev_data
->ats
.enabled
;
1888 /* Update data structures */
1889 dev_data
->domain
= domain
;
1890 list_add(&dev_data
->list
, &domain
->dev_list
);
1892 /* Do reference counting */
1893 domain
->dev_iommu
[iommu
->index
] += 1;
1894 domain
->dev_cnt
+= 1;
1896 /* Update device table */
1897 set_dte_entry(dev_data
->devid
, domain
, ats
);
1898 if (alias
!= dev_data
->devid
)
1899 set_dte_entry(alias
, domain
, ats
);
1901 device_flush_dte(dev_data
);
1904 static void do_detach(struct iommu_dev_data
*dev_data
)
1906 struct amd_iommu
*iommu
;
1910 * First check if the device is still attached. It might already
1911 * be detached from its domain because the generic
1912 * iommu_detach_group code detached it and we try again here in
1913 * our alias handling.
1915 if (!dev_data
->domain
)
1918 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1919 alias
= dev_data
->alias
;
1921 /* decrease reference counters */
1922 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
1923 dev_data
->domain
->dev_cnt
-= 1;
1925 /* Update data structures */
1926 dev_data
->domain
= NULL
;
1927 list_del(&dev_data
->list
);
1928 clear_dte_entry(dev_data
->devid
);
1929 if (alias
!= dev_data
->devid
)
1930 clear_dte_entry(alias
);
1932 /* Flush the DTE entry */
1933 device_flush_dte(dev_data
);
1937 * If a device is not yet associated with a domain, this function does
1938 * assigns it visible for the hardware
1940 static int __attach_device(struct iommu_dev_data
*dev_data
,
1941 struct protection_domain
*domain
)
1946 * Must be called with IRQs disabled. Warn here to detect early
1949 WARN_ON(!irqs_disabled());
1952 spin_lock(&domain
->lock
);
1955 if (dev_data
->domain
!= NULL
)
1958 /* Attach alias group root */
1959 do_attach(dev_data
, domain
);
1966 spin_unlock(&domain
->lock
);
1972 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
1974 pci_disable_ats(pdev
);
1975 pci_disable_pri(pdev
);
1976 pci_disable_pasid(pdev
);
1979 /* FIXME: Change generic reset-function to do the same */
1980 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
1985 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
1989 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
1990 control
|= PCI_PRI_CTRL_RESET
;
1991 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
1996 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2001 /* FIXME: Hardcode number of outstanding requests for now */
2003 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2005 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2007 /* Only allow access to user-accessible pages */
2008 ret
= pci_enable_pasid(pdev
, 0);
2012 /* First reset the PRI state of the device */
2013 ret
= pci_reset_pri(pdev
);
2018 ret
= pci_enable_pri(pdev
, reqs
);
2023 ret
= pri_reset_while_enabled(pdev
);
2028 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2035 pci_disable_pri(pdev
);
2036 pci_disable_pasid(pdev
);
2041 /* FIXME: Move this to PCI code */
2042 #define PCI_PRI_TLP_OFF (1 << 15)
2044 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2049 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2053 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2055 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2059 * If a device is not yet associated with a domain, this function
2060 * assigns it visible for the hardware
2062 static int attach_device(struct device
*dev
,
2063 struct protection_domain
*domain
)
2065 struct pci_dev
*pdev
;
2066 struct iommu_dev_data
*dev_data
;
2067 unsigned long flags
;
2070 dev_data
= get_dev_data(dev
);
2072 if (!dev_is_pci(dev
))
2073 goto skip_ats_check
;
2075 pdev
= to_pci_dev(dev
);
2076 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2077 if (!dev_data
->passthrough
)
2080 if (dev_data
->iommu_v2
) {
2081 if (pdev_iommuv2_enable(pdev
) != 0)
2084 dev_data
->ats
.enabled
= true;
2085 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2086 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2088 } else if (amd_iommu_iotlb_sup
&&
2089 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2090 dev_data
->ats
.enabled
= true;
2091 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2095 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2096 ret
= __attach_device(dev_data
, domain
);
2097 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2100 * We might boot into a crash-kernel here. The crashed kernel
2101 * left the caches in the IOMMU dirty. So we have to flush
2102 * here to evict all dirty stuff.
2104 domain_flush_tlb_pde(domain
);
2110 * Removes a device from a protection domain (unlocked)
2112 static void __detach_device(struct iommu_dev_data
*dev_data
)
2114 struct protection_domain
*domain
;
2117 * Must be called with IRQs disabled. Warn here to detect early
2120 WARN_ON(!irqs_disabled());
2122 if (WARN_ON(!dev_data
->domain
))
2125 domain
= dev_data
->domain
;
2127 spin_lock(&domain
->lock
);
2129 do_detach(dev_data
);
2131 spin_unlock(&domain
->lock
);
2135 * Removes a device from a protection domain (with devtable_lock held)
2137 static void detach_device(struct device
*dev
)
2139 struct protection_domain
*domain
;
2140 struct iommu_dev_data
*dev_data
;
2141 unsigned long flags
;
2143 dev_data
= get_dev_data(dev
);
2144 domain
= dev_data
->domain
;
2146 /* lock device table */
2147 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2148 __detach_device(dev_data
);
2149 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2151 if (!dev_is_pci(dev
))
2154 if (domain
->flags
& PD_IOMMUV2_MASK
&& dev_data
->iommu_v2
)
2155 pdev_iommuv2_disable(to_pci_dev(dev
));
2156 else if (dev_data
->ats
.enabled
)
2157 pci_disable_ats(to_pci_dev(dev
));
2159 dev_data
->ats
.enabled
= false;
2162 static int amd_iommu_add_device(struct device
*dev
)
2164 struct iommu_dev_data
*dev_data
;
2165 struct iommu_domain
*domain
;
2166 struct amd_iommu
*iommu
;
2169 if (!check_device(dev
) || get_dev_data(dev
))
2172 devid
= get_device_id(dev
);
2176 iommu
= amd_iommu_rlookup_table
[devid
];
2178 ret
= iommu_init_device(dev
);
2180 if (ret
!= -ENOTSUPP
)
2181 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2184 iommu_ignore_device(dev
);
2185 dev
->dma_ops
= &nommu_dma_ops
;
2188 init_iommu_group(dev
);
2190 dev_data
= get_dev_data(dev
);
2194 if (iommu_pass_through
|| dev_data
->iommu_v2
)
2195 iommu_request_dm_for_dev(dev
);
2197 /* Domains are initialized for this device - have a look what we ended up with */
2198 domain
= iommu_get_domain_for_dev(dev
);
2199 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
)
2200 dev_data
->passthrough
= true;
2202 dev
->dma_ops
= &amd_iommu_dma_ops
;
2205 iommu_completion_wait(iommu
);
2210 static void amd_iommu_remove_device(struct device
*dev
)
2212 struct amd_iommu
*iommu
;
2215 if (!check_device(dev
))
2218 devid
= get_device_id(dev
);
2222 iommu
= amd_iommu_rlookup_table
[devid
];
2224 iommu_uninit_device(dev
);
2225 iommu_completion_wait(iommu
);
2228 static struct iommu_group
*amd_iommu_device_group(struct device
*dev
)
2230 if (dev_is_pci(dev
))
2231 return pci_device_group(dev
);
2233 return acpihid_device_group(dev
);
2236 /*****************************************************************************
2238 * The next functions belong to the dma_ops mapping/unmapping code.
2240 *****************************************************************************/
2243 * In the dma_ops path we only have the struct device. This function
2244 * finds the corresponding IOMMU, the protection domain and the
2245 * requestor id for a given device.
2246 * If the device is not yet associated with a domain this is also done
2249 static struct protection_domain
*get_domain(struct device
*dev
)
2251 struct protection_domain
*domain
;
2252 struct iommu_domain
*io_domain
;
2254 if (!check_device(dev
))
2255 return ERR_PTR(-EINVAL
);
2257 domain
= get_dev_data(dev
)->domain
;
2258 if (domain
== NULL
&& get_dev_data(dev
)->defer_attach
) {
2259 get_dev_data(dev
)->defer_attach
= false;
2260 io_domain
= iommu_get_domain_for_dev(dev
);
2261 domain
= to_pdomain(io_domain
);
2262 attach_device(dev
, domain
);
2265 return ERR_PTR(-EBUSY
);
2267 if (!dma_ops_domain(domain
))
2268 return ERR_PTR(-EBUSY
);
2273 static void update_device_table(struct protection_domain
*domain
)
2275 struct iommu_dev_data
*dev_data
;
2277 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
2278 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
);
2280 if (dev_data
->devid
== dev_data
->alias
)
2283 /* There is an alias, update device table entry for it */
2284 set_dte_entry(dev_data
->alias
, domain
, dev_data
->ats
.enabled
);
2288 static void update_domain(struct protection_domain
*domain
)
2290 if (!domain
->updated
)
2293 update_device_table(domain
);
2295 domain_flush_devices(domain
);
2296 domain_flush_tlb_pde(domain
);
2298 domain
->updated
= false;
2301 static int dir2prot(enum dma_data_direction direction
)
2303 if (direction
== DMA_TO_DEVICE
)
2304 return IOMMU_PROT_IR
;
2305 else if (direction
== DMA_FROM_DEVICE
)
2306 return IOMMU_PROT_IW
;
2307 else if (direction
== DMA_BIDIRECTIONAL
)
2308 return IOMMU_PROT_IW
| IOMMU_PROT_IR
;
2314 * This function contains common code for mapping of a physically
2315 * contiguous memory region into DMA address space. It is used by all
2316 * mapping functions provided with this IOMMU driver.
2317 * Must be called with the domain lock held.
2319 static dma_addr_t
__map_single(struct device
*dev
,
2320 struct dma_ops_domain
*dma_dom
,
2323 enum dma_data_direction direction
,
2326 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2327 dma_addr_t address
, start
, ret
;
2332 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2335 address
= dma_ops_alloc_iova(dev
, dma_dom
, pages
, dma_mask
);
2336 if (address
== AMD_IOMMU_MAPPING_ERROR
)
2339 prot
= dir2prot(direction
);
2342 for (i
= 0; i
< pages
; ++i
) {
2343 ret
= iommu_map_page(&dma_dom
->domain
, start
, paddr
,
2344 PAGE_SIZE
, prot
, GFP_ATOMIC
);
2353 if (unlikely(amd_iommu_np_cache
)) {
2354 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2355 domain_flush_complete(&dma_dom
->domain
);
2363 for (--i
; i
>= 0; --i
) {
2365 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2368 domain_flush_tlb(&dma_dom
->domain
);
2369 domain_flush_complete(&dma_dom
->domain
);
2371 dma_ops_free_iova(dma_dom
, address
, pages
);
2373 return AMD_IOMMU_MAPPING_ERROR
;
2377 * Does the reverse of the __map_single function. Must be called with
2378 * the domain lock held too
2380 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2381 dma_addr_t dma_addr
,
2385 dma_addr_t i
, start
;
2388 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2389 dma_addr
&= PAGE_MASK
;
2392 for (i
= 0; i
< pages
; ++i
) {
2393 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2397 if (amd_iommu_unmap_flush
) {
2398 dma_ops_free_iova(dma_dom
, dma_addr
, pages
);
2399 domain_flush_tlb(&dma_dom
->domain
);
2400 domain_flush_complete(&dma_dom
->domain
);
2402 pages
= __roundup_pow_of_two(pages
);
2403 queue_iova(&dma_dom
->iovad
, dma_addr
>> PAGE_SHIFT
, pages
, 0);
2408 * The exported map_single function for dma_ops.
2410 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2411 unsigned long offset
, size_t size
,
2412 enum dma_data_direction dir
,
2413 unsigned long attrs
)
2415 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2416 struct protection_domain
*domain
;
2417 struct dma_ops_domain
*dma_dom
;
2420 domain
= get_domain(dev
);
2421 if (PTR_ERR(domain
) == -EINVAL
)
2422 return (dma_addr_t
)paddr
;
2423 else if (IS_ERR(domain
))
2424 return AMD_IOMMU_MAPPING_ERROR
;
2426 dma_mask
= *dev
->dma_mask
;
2427 dma_dom
= to_dma_ops_domain(domain
);
2429 return __map_single(dev
, dma_dom
, paddr
, size
, dir
, dma_mask
);
2433 * The exported unmap_single function for dma_ops.
2435 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2436 enum dma_data_direction dir
, unsigned long attrs
)
2438 struct protection_domain
*domain
;
2439 struct dma_ops_domain
*dma_dom
;
2441 domain
= get_domain(dev
);
2445 dma_dom
= to_dma_ops_domain(domain
);
2447 __unmap_single(dma_dom
, dma_addr
, size
, dir
);
2450 static int sg_num_pages(struct device
*dev
,
2451 struct scatterlist
*sglist
,
2454 unsigned long mask
, boundary_size
;
2455 struct scatterlist
*s
;
2458 mask
= dma_get_seg_boundary(dev
);
2459 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
2460 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
2462 for_each_sg(sglist
, s
, nelems
, i
) {
2465 s
->dma_address
= npages
<< PAGE_SHIFT
;
2466 p
= npages
% boundary_size
;
2467 n
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2468 if (p
+ n
> boundary_size
)
2469 npages
+= boundary_size
- p
;
2477 * The exported map_sg function for dma_ops (handles scatter-gather
2480 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2481 int nelems
, enum dma_data_direction direction
,
2482 unsigned long attrs
)
2484 int mapped_pages
= 0, npages
= 0, prot
= 0, i
;
2485 struct protection_domain
*domain
;
2486 struct dma_ops_domain
*dma_dom
;
2487 struct scatterlist
*s
;
2488 unsigned long address
;
2491 domain
= get_domain(dev
);
2495 dma_dom
= to_dma_ops_domain(domain
);
2496 dma_mask
= *dev
->dma_mask
;
2498 npages
= sg_num_pages(dev
, sglist
, nelems
);
2500 address
= dma_ops_alloc_iova(dev
, dma_dom
, npages
, dma_mask
);
2501 if (address
== AMD_IOMMU_MAPPING_ERROR
)
2504 prot
= dir2prot(direction
);
2506 /* Map all sg entries */
2507 for_each_sg(sglist
, s
, nelems
, i
) {
2508 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2510 for (j
= 0; j
< pages
; ++j
) {
2511 unsigned long bus_addr
, phys_addr
;
2514 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2515 phys_addr
= (sg_phys(s
) & PAGE_MASK
) + (j
<< PAGE_SHIFT
);
2516 ret
= iommu_map_page(domain
, bus_addr
, phys_addr
, PAGE_SIZE
, prot
, GFP_ATOMIC
);
2524 /* Everything is mapped - write the right values into s->dma_address */
2525 for_each_sg(sglist
, s
, nelems
, i
) {
2526 s
->dma_address
+= address
+ s
->offset
;
2527 s
->dma_length
= s
->length
;
2533 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2534 dev_name(dev
), npages
);
2536 for_each_sg(sglist
, s
, nelems
, i
) {
2537 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2539 for (j
= 0; j
< pages
; ++j
) {
2540 unsigned long bus_addr
;
2542 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2543 iommu_unmap_page(domain
, bus_addr
, PAGE_SIZE
);
2551 free_iova_fast(&dma_dom
->iovad
, address
, npages
);
2558 * The exported map_sg function for dma_ops (handles scatter-gather
2561 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2562 int nelems
, enum dma_data_direction dir
,
2563 unsigned long attrs
)
2565 struct protection_domain
*domain
;
2566 struct dma_ops_domain
*dma_dom
;
2567 unsigned long startaddr
;
2570 domain
= get_domain(dev
);
2574 startaddr
= sg_dma_address(sglist
) & PAGE_MASK
;
2575 dma_dom
= to_dma_ops_domain(domain
);
2576 npages
= sg_num_pages(dev
, sglist
, nelems
);
2578 __unmap_single(dma_dom
, startaddr
, npages
<< PAGE_SHIFT
, dir
);
2582 * The exported alloc_coherent function for dma_ops.
2584 static void *alloc_coherent(struct device
*dev
, size_t size
,
2585 dma_addr_t
*dma_addr
, gfp_t flag
,
2586 unsigned long attrs
)
2588 u64 dma_mask
= dev
->coherent_dma_mask
;
2589 struct protection_domain
*domain
;
2590 struct dma_ops_domain
*dma_dom
;
2593 domain
= get_domain(dev
);
2594 if (PTR_ERR(domain
) == -EINVAL
) {
2595 page
= alloc_pages(flag
, get_order(size
));
2596 *dma_addr
= page_to_phys(page
);
2597 return page_address(page
);
2598 } else if (IS_ERR(domain
))
2601 dma_dom
= to_dma_ops_domain(domain
);
2602 size
= PAGE_ALIGN(size
);
2603 dma_mask
= dev
->coherent_dma_mask
;
2604 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2607 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2609 if (!gfpflags_allow_blocking(flag
))
2612 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2613 get_order(size
), flag
);
2619 dma_mask
= *dev
->dma_mask
;
2621 *dma_addr
= __map_single(dev
, dma_dom
, page_to_phys(page
),
2622 size
, DMA_BIDIRECTIONAL
, dma_mask
);
2624 if (*dma_addr
== AMD_IOMMU_MAPPING_ERROR
)
2627 return page_address(page
);
2631 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2632 __free_pages(page
, get_order(size
));
2638 * The exported free_coherent function for dma_ops.
2640 static void free_coherent(struct device
*dev
, size_t size
,
2641 void *virt_addr
, dma_addr_t dma_addr
,
2642 unsigned long attrs
)
2644 struct protection_domain
*domain
;
2645 struct dma_ops_domain
*dma_dom
;
2648 page
= virt_to_page(virt_addr
);
2649 size
= PAGE_ALIGN(size
);
2651 domain
= get_domain(dev
);
2655 dma_dom
= to_dma_ops_domain(domain
);
2657 __unmap_single(dma_dom
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2660 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2661 __free_pages(page
, get_order(size
));
2665 * This function is called by the DMA layer to find out if we can handle a
2666 * particular device. It is part of the dma_ops.
2668 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2670 if (!x86_dma_supported(dev
, mask
))
2672 return check_device(dev
);
2675 static int amd_iommu_mapping_error(struct device
*dev
, dma_addr_t dma_addr
)
2677 return dma_addr
== AMD_IOMMU_MAPPING_ERROR
;
2680 static const struct dma_map_ops amd_iommu_dma_ops
= {
2681 .alloc
= alloc_coherent
,
2682 .free
= free_coherent
,
2683 .map_page
= map_page
,
2684 .unmap_page
= unmap_page
,
2686 .unmap_sg
= unmap_sg
,
2687 .dma_supported
= amd_iommu_dma_supported
,
2688 .mapping_error
= amd_iommu_mapping_error
,
2691 static int init_reserved_iova_ranges(void)
2693 struct pci_dev
*pdev
= NULL
;
2696 init_iova_domain(&reserved_iova_ranges
, PAGE_SIZE
, IOVA_START_PFN
);
2698 lockdep_set_class(&reserved_iova_ranges
.iova_rbtree_lock
,
2699 &reserved_rbtree_key
);
2701 /* MSI memory range */
2702 val
= reserve_iova(&reserved_iova_ranges
,
2703 IOVA_PFN(MSI_RANGE_START
), IOVA_PFN(MSI_RANGE_END
));
2705 pr_err("Reserving MSI range failed\n");
2709 /* HT memory range */
2710 val
= reserve_iova(&reserved_iova_ranges
,
2711 IOVA_PFN(HT_RANGE_START
), IOVA_PFN(HT_RANGE_END
));
2713 pr_err("Reserving HT range failed\n");
2718 * Memory used for PCI resources
2719 * FIXME: Check whether we can reserve the PCI-hole completly
2721 for_each_pci_dev(pdev
) {
2724 for (i
= 0; i
< PCI_NUM_RESOURCES
; ++i
) {
2725 struct resource
*r
= &pdev
->resource
[i
];
2727 if (!(r
->flags
& IORESOURCE_MEM
))
2730 val
= reserve_iova(&reserved_iova_ranges
,
2734 pr_err("Reserve pci-resource range failed\n");
2743 int __init
amd_iommu_init_api(void)
2747 ret
= iova_cache_get();
2751 ret
= init_reserved_iova_ranges();
2755 err
= bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2758 #ifdef CONFIG_ARM_AMBA
2759 err
= bus_set_iommu(&amba_bustype
, &amd_iommu_ops
);
2763 err
= bus_set_iommu(&platform_bus_type
, &amd_iommu_ops
);
2770 int __init
amd_iommu_init_dma_ops(void)
2772 swiotlb
= (iommu_pass_through
|| sme_me_mask
) ? 1 : 0;
2776 * In case we don't initialize SWIOTLB (actually the common case
2777 * when AMD IOMMU is enabled and SME is not active), make sure there
2778 * are global dma_ops set as a fall-back for devices not handled by
2779 * this driver (for example non-PCI devices). When SME is active,
2780 * make sure that swiotlb variable remains set so the global dma_ops
2781 * continue to be SWIOTLB.
2784 dma_ops
= &nommu_dma_ops
;
2786 if (amd_iommu_unmap_flush
)
2787 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2789 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2795 /*****************************************************************************
2797 * The following functions belong to the exported interface of AMD IOMMU
2799 * This interface allows access to lower level functions of the IOMMU
2800 * like protection domain handling and assignement of devices to domains
2801 * which is not possible with the dma_ops interface.
2803 *****************************************************************************/
2805 static void cleanup_domain(struct protection_domain
*domain
)
2807 struct iommu_dev_data
*entry
;
2808 unsigned long flags
;
2810 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2812 while (!list_empty(&domain
->dev_list
)) {
2813 entry
= list_first_entry(&domain
->dev_list
,
2814 struct iommu_dev_data
, list
);
2815 __detach_device(entry
);
2818 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2821 static void protection_domain_free(struct protection_domain
*domain
)
2826 del_domain_from_list(domain
);
2829 domain_id_free(domain
->id
);
2834 static int protection_domain_init(struct protection_domain
*domain
)
2836 spin_lock_init(&domain
->lock
);
2837 mutex_init(&domain
->api_lock
);
2838 domain
->id
= domain_id_alloc();
2841 INIT_LIST_HEAD(&domain
->dev_list
);
2846 static struct protection_domain
*protection_domain_alloc(void)
2848 struct protection_domain
*domain
;
2850 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2854 if (protection_domain_init(domain
))
2857 add_domain_to_list(domain
);
2867 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
2869 struct protection_domain
*pdomain
;
2870 struct dma_ops_domain
*dma_domain
;
2873 case IOMMU_DOMAIN_UNMANAGED
:
2874 pdomain
= protection_domain_alloc();
2878 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
2879 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2880 if (!pdomain
->pt_root
) {
2881 protection_domain_free(pdomain
);
2885 pdomain
->domain
.geometry
.aperture_start
= 0;
2886 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
2887 pdomain
->domain
.geometry
.force_aperture
= true;
2890 case IOMMU_DOMAIN_DMA
:
2891 dma_domain
= dma_ops_domain_alloc();
2893 pr_err("AMD-Vi: Failed to allocate\n");
2896 pdomain
= &dma_domain
->domain
;
2898 case IOMMU_DOMAIN_IDENTITY
:
2899 pdomain
= protection_domain_alloc();
2903 pdomain
->mode
= PAGE_MODE_NONE
;
2909 return &pdomain
->domain
;
2912 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
2914 struct protection_domain
*domain
;
2915 struct dma_ops_domain
*dma_dom
;
2917 domain
= to_pdomain(dom
);
2919 if (domain
->dev_cnt
> 0)
2920 cleanup_domain(domain
);
2922 BUG_ON(domain
->dev_cnt
!= 0);
2927 switch (dom
->type
) {
2928 case IOMMU_DOMAIN_DMA
:
2929 /* Now release the domain */
2930 dma_dom
= to_dma_ops_domain(domain
);
2931 dma_ops_domain_free(dma_dom
);
2934 if (domain
->mode
!= PAGE_MODE_NONE
)
2935 free_pagetable(domain
);
2937 if (domain
->flags
& PD_IOMMUV2_MASK
)
2938 free_gcr3_table(domain
);
2940 protection_domain_free(domain
);
2945 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
2948 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
2949 struct amd_iommu
*iommu
;
2952 if (!check_device(dev
))
2955 devid
= get_device_id(dev
);
2959 if (dev_data
->domain
!= NULL
)
2962 iommu
= amd_iommu_rlookup_table
[devid
];
2966 #ifdef CONFIG_IRQ_REMAP
2967 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) &&
2968 (dom
->type
== IOMMU_DOMAIN_UNMANAGED
))
2969 dev_data
->use_vapic
= 0;
2972 iommu_completion_wait(iommu
);
2975 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
2978 struct protection_domain
*domain
= to_pdomain(dom
);
2979 struct iommu_dev_data
*dev_data
;
2980 struct amd_iommu
*iommu
;
2983 if (!check_device(dev
))
2986 dev_data
= dev
->archdata
.iommu
;
2988 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
2992 if (dev_data
->domain
)
2995 ret
= attach_device(dev
, domain
);
2997 #ifdef CONFIG_IRQ_REMAP
2998 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
2999 if (dom
->type
== IOMMU_DOMAIN_UNMANAGED
)
3000 dev_data
->use_vapic
= 1;
3002 dev_data
->use_vapic
= 0;
3006 iommu_completion_wait(iommu
);
3011 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3012 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3014 struct protection_domain
*domain
= to_pdomain(dom
);
3018 if (domain
->mode
== PAGE_MODE_NONE
)
3021 if (iommu_prot
& IOMMU_READ
)
3022 prot
|= IOMMU_PROT_IR
;
3023 if (iommu_prot
& IOMMU_WRITE
)
3024 prot
|= IOMMU_PROT_IW
;
3026 mutex_lock(&domain
->api_lock
);
3027 ret
= iommu_map_page(domain
, iova
, paddr
, page_size
, prot
, GFP_KERNEL
);
3028 mutex_unlock(&domain
->api_lock
);
3033 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3036 struct protection_domain
*domain
= to_pdomain(dom
);
3039 if (domain
->mode
== PAGE_MODE_NONE
)
3042 mutex_lock(&domain
->api_lock
);
3043 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3044 mutex_unlock(&domain
->api_lock
);
3046 domain_flush_tlb_pde(domain
);
3047 domain_flush_complete(domain
);
3052 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3055 struct protection_domain
*domain
= to_pdomain(dom
);
3056 unsigned long offset_mask
, pte_pgsize
;
3059 if (domain
->mode
== PAGE_MODE_NONE
)
3062 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3064 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3067 offset_mask
= pte_pgsize
- 1;
3068 __pte
= *pte
& PM_ADDR_MASK
;
3070 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3073 static bool amd_iommu_capable(enum iommu_cap cap
)
3076 case IOMMU_CAP_CACHE_COHERENCY
:
3078 case IOMMU_CAP_INTR_REMAP
:
3079 return (irq_remapping_enabled
== 1);
3080 case IOMMU_CAP_NOEXEC
:
3087 static void amd_iommu_get_resv_regions(struct device
*dev
,
3088 struct list_head
*head
)
3090 struct iommu_resv_region
*region
;
3091 struct unity_map_entry
*entry
;
3094 devid
= get_device_id(dev
);
3098 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3102 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3105 length
= entry
->address_end
- entry
->address_start
;
3106 if (entry
->prot
& IOMMU_PROT_IR
)
3108 if (entry
->prot
& IOMMU_PROT_IW
)
3109 prot
|= IOMMU_WRITE
;
3111 region
= iommu_alloc_resv_region(entry
->address_start
,
3115 pr_err("Out of memory allocating dm-regions for %s\n",
3119 list_add_tail(®ion
->list
, head
);
3122 region
= iommu_alloc_resv_region(MSI_RANGE_START
,
3123 MSI_RANGE_END
- MSI_RANGE_START
+ 1,
3127 list_add_tail(®ion
->list
, head
);
3129 region
= iommu_alloc_resv_region(HT_RANGE_START
,
3130 HT_RANGE_END
- HT_RANGE_START
+ 1,
3131 0, IOMMU_RESV_RESERVED
);
3134 list_add_tail(®ion
->list
, head
);
3137 static void amd_iommu_put_resv_regions(struct device
*dev
,
3138 struct list_head
*head
)
3140 struct iommu_resv_region
*entry
, *next
;
3142 list_for_each_entry_safe(entry
, next
, head
, list
)
3146 static void amd_iommu_apply_resv_region(struct device
*dev
,
3147 struct iommu_domain
*domain
,
3148 struct iommu_resv_region
*region
)
3150 struct dma_ops_domain
*dma_dom
= to_dma_ops_domain(to_pdomain(domain
));
3151 unsigned long start
, end
;
3153 start
= IOVA_PFN(region
->start
);
3154 end
= IOVA_PFN(region
->start
+ region
->length
- 1);
3156 WARN_ON_ONCE(reserve_iova(&dma_dom
->iovad
, start
, end
) == NULL
);
3159 static bool amd_iommu_is_attach_deferred(struct iommu_domain
*domain
,
3162 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3163 return dev_data
->defer_attach
;
3166 const struct iommu_ops amd_iommu_ops
= {
3167 .capable
= amd_iommu_capable
,
3168 .domain_alloc
= amd_iommu_domain_alloc
,
3169 .domain_free
= amd_iommu_domain_free
,
3170 .attach_dev
= amd_iommu_attach_device
,
3171 .detach_dev
= amd_iommu_detach_device
,
3172 .map
= amd_iommu_map
,
3173 .unmap
= amd_iommu_unmap
,
3174 .map_sg
= default_iommu_map_sg
,
3175 .iova_to_phys
= amd_iommu_iova_to_phys
,
3176 .add_device
= amd_iommu_add_device
,
3177 .remove_device
= amd_iommu_remove_device
,
3178 .device_group
= amd_iommu_device_group
,
3179 .get_resv_regions
= amd_iommu_get_resv_regions
,
3180 .put_resv_regions
= amd_iommu_put_resv_regions
,
3181 .apply_resv_region
= amd_iommu_apply_resv_region
,
3182 .is_attach_deferred
= amd_iommu_is_attach_deferred
,
3183 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3186 /*****************************************************************************
3188 * The next functions do a basic initialization of IOMMU for pass through
3191 * In passthrough mode the IOMMU is initialized and enabled but not used for
3192 * DMA-API translation.
3194 *****************************************************************************/
3196 /* IOMMUv2 specific functions */
3197 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3199 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3201 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3203 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3205 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3207 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3209 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3211 struct protection_domain
*domain
= to_pdomain(dom
);
3212 unsigned long flags
;
3214 spin_lock_irqsave(&domain
->lock
, flags
);
3216 /* Update data structure */
3217 domain
->mode
= PAGE_MODE_NONE
;
3218 domain
->updated
= true;
3220 /* Make changes visible to IOMMUs */
3221 update_domain(domain
);
3223 /* Page-table is not visible to IOMMU anymore, so free it */
3224 free_pagetable(domain
);
3226 spin_unlock_irqrestore(&domain
->lock
, flags
);
3228 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3230 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3232 struct protection_domain
*domain
= to_pdomain(dom
);
3233 unsigned long flags
;
3236 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3239 /* Number of GCR3 table levels required */
3240 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3243 if (levels
> amd_iommu_max_glx_val
)
3246 spin_lock_irqsave(&domain
->lock
, flags
);
3249 * Save us all sanity checks whether devices already in the
3250 * domain support IOMMUv2. Just force that the domain has no
3251 * devices attached when it is switched into IOMMUv2 mode.
3254 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3258 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3259 if (domain
->gcr3_tbl
== NULL
)
3262 domain
->glx
= levels
;
3263 domain
->flags
|= PD_IOMMUV2_MASK
;
3264 domain
->updated
= true;
3266 update_domain(domain
);
3271 spin_unlock_irqrestore(&domain
->lock
, flags
);
3275 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3277 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3278 u64 address
, bool size
)
3280 struct iommu_dev_data
*dev_data
;
3281 struct iommu_cmd cmd
;
3284 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3287 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3290 * IOMMU TLB needs to be flushed before Device TLB to
3291 * prevent device TLB refill from IOMMU TLB
3293 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
3294 if (domain
->dev_iommu
[i
] == 0)
3297 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3302 /* Wait until IOMMU TLB flushes are complete */
3303 domain_flush_complete(domain
);
3305 /* Now flush device TLBs */
3306 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3307 struct amd_iommu
*iommu
;
3311 There might be non-IOMMUv2 capable devices in an IOMMUv2
3314 if (!dev_data
->ats
.enabled
)
3317 qdep
= dev_data
->ats
.qdep
;
3318 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3320 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3321 qdep
, address
, size
);
3323 ret
= iommu_queue_command(iommu
, &cmd
);
3328 /* Wait until all device TLBs are flushed */
3329 domain_flush_complete(domain
);
3338 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3341 return __flush_pasid(domain
, pasid
, address
, false);
3344 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3347 struct protection_domain
*domain
= to_pdomain(dom
);
3348 unsigned long flags
;
3351 spin_lock_irqsave(&domain
->lock
, flags
);
3352 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3353 spin_unlock_irqrestore(&domain
->lock
, flags
);
3357 EXPORT_SYMBOL(amd_iommu_flush_page
);
3359 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3361 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3365 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3367 struct protection_domain
*domain
= to_pdomain(dom
);
3368 unsigned long flags
;
3371 spin_lock_irqsave(&domain
->lock
, flags
);
3372 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3373 spin_unlock_irqrestore(&domain
->lock
, flags
);
3377 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3379 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3386 index
= (pasid
>> (9 * level
)) & 0x1ff;
3392 if (!(*pte
& GCR3_VALID
)) {
3396 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3400 *pte
= iommu_virt_to_phys(root
) | GCR3_VALID
;
3403 root
= iommu_phys_to_virt(*pte
& PAGE_MASK
);
3411 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3416 if (domain
->mode
!= PAGE_MODE_NONE
)
3419 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3423 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3425 return __amd_iommu_flush_tlb(domain
, pasid
);
3428 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3432 if (domain
->mode
!= PAGE_MODE_NONE
)
3435 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3441 return __amd_iommu_flush_tlb(domain
, pasid
);
3444 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3447 struct protection_domain
*domain
= to_pdomain(dom
);
3448 unsigned long flags
;
3451 spin_lock_irqsave(&domain
->lock
, flags
);
3452 ret
= __set_gcr3(domain
, pasid
, cr3
);
3453 spin_unlock_irqrestore(&domain
->lock
, flags
);
3457 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3459 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3461 struct protection_domain
*domain
= to_pdomain(dom
);
3462 unsigned long flags
;
3465 spin_lock_irqsave(&domain
->lock
, flags
);
3466 ret
= __clear_gcr3(domain
, pasid
);
3467 spin_unlock_irqrestore(&domain
->lock
, flags
);
3471 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3473 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3474 int status
, int tag
)
3476 struct iommu_dev_data
*dev_data
;
3477 struct amd_iommu
*iommu
;
3478 struct iommu_cmd cmd
;
3480 dev_data
= get_dev_data(&pdev
->dev
);
3481 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3483 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3484 tag
, dev_data
->pri_tlp
);
3486 return iommu_queue_command(iommu
, &cmd
);
3488 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3490 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3492 struct protection_domain
*pdomain
;
3494 pdomain
= get_domain(&pdev
->dev
);
3495 if (IS_ERR(pdomain
))
3498 /* Only return IOMMUv2 domains */
3499 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3502 return &pdomain
->domain
;
3504 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3506 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3508 struct iommu_dev_data
*dev_data
;
3510 if (!amd_iommu_v2_supported())
3513 dev_data
= get_dev_data(&pdev
->dev
);
3514 dev_data
->errata
|= (1 << erratum
);
3516 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3518 int amd_iommu_device_info(struct pci_dev
*pdev
,
3519 struct amd_iommu_device_info
*info
)
3524 if (pdev
== NULL
|| info
== NULL
)
3527 if (!amd_iommu_v2_supported())
3530 memset(info
, 0, sizeof(*info
));
3532 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3534 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3536 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3538 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3540 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3544 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3545 max_pasids
= min(max_pasids
, (1 << 20));
3547 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3548 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3550 features
= pci_pasid_features(pdev
);
3551 if (features
& PCI_PASID_CAP_EXEC
)
3552 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3553 if (features
& PCI_PASID_CAP_PRIV
)
3554 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3559 EXPORT_SYMBOL(amd_iommu_device_info
);
3561 #ifdef CONFIG_IRQ_REMAP
3563 /*****************************************************************************
3565 * Interrupt Remapping Implementation
3567 *****************************************************************************/
3569 static struct irq_chip amd_ir_chip
;
3571 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3575 dte
= amd_iommu_dev_table
[devid
].data
[2];
3576 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3577 dte
|= iommu_virt_to_phys(table
->table
);
3578 dte
|= DTE_IRQ_REMAP_INTCTL
;
3579 dte
|= DTE_IRQ_TABLE_LEN
;
3580 dte
|= DTE_IRQ_REMAP_ENABLE
;
3582 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3585 static struct irq_remap_table
*get_irq_table(u16 devid
, bool ioapic
)
3587 struct irq_remap_table
*table
= NULL
;
3588 struct amd_iommu
*iommu
;
3589 unsigned long flags
;
3592 write_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
3594 iommu
= amd_iommu_rlookup_table
[devid
];
3598 table
= irq_lookup_table
[devid
];
3602 alias
= amd_iommu_alias_table
[devid
];
3603 table
= irq_lookup_table
[alias
];
3605 irq_lookup_table
[devid
] = table
;
3606 set_dte_irq_entry(devid
, table
);
3607 iommu_flush_dte(iommu
, devid
);
3611 /* Nothing there yet, allocate new irq remapping table */
3612 table
= kzalloc(sizeof(*table
), GFP_ATOMIC
);
3616 /* Initialize table spin-lock */
3617 spin_lock_init(&table
->lock
);
3620 /* Keep the first 32 indexes free for IOAPIC interrupts */
3621 table
->min_index
= 32;
3623 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_ATOMIC
);
3624 if (!table
->table
) {
3630 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
3631 memset(table
->table
, 0,
3632 MAX_IRQS_PER_TABLE
* sizeof(u32
));
3634 memset(table
->table
, 0,
3635 (MAX_IRQS_PER_TABLE
* (sizeof(u64
) * 2)));
3640 for (i
= 0; i
< 32; ++i
)
3641 iommu
->irte_ops
->set_allocated(table
, i
);
3644 irq_lookup_table
[devid
] = table
;
3645 set_dte_irq_entry(devid
, table
);
3646 iommu_flush_dte(iommu
, devid
);
3647 if (devid
!= alias
) {
3648 irq_lookup_table
[alias
] = table
;
3649 set_dte_irq_entry(alias
, table
);
3650 iommu_flush_dte(iommu
, alias
);
3654 iommu_completion_wait(iommu
);
3657 write_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
3662 static int alloc_irq_index(u16 devid
, int count
, bool align
)
3664 struct irq_remap_table
*table
;
3665 int index
, c
, alignment
= 1;
3666 unsigned long flags
;
3667 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
3672 table
= get_irq_table(devid
, false);
3677 alignment
= roundup_pow_of_two(count
);
3679 spin_lock_irqsave(&table
->lock
, flags
);
3681 /* Scan table for free entries */
3682 for (index
= ALIGN(table
->min_index
, alignment
), c
= 0;
3683 index
< MAX_IRQS_PER_TABLE
;) {
3684 if (!iommu
->irte_ops
->is_allocated(table
, index
)) {
3688 index
= ALIGN(index
+ 1, alignment
);
3694 iommu
->irte_ops
->set_allocated(table
, index
- c
+ 1);
3706 spin_unlock_irqrestore(&table
->lock
, flags
);
3711 static int modify_irte_ga(u16 devid
, int index
, struct irte_ga
*irte
,
3712 struct amd_ir_data
*data
)
3714 struct irq_remap_table
*table
;
3715 struct amd_iommu
*iommu
;
3716 unsigned long flags
;
3717 struct irte_ga
*entry
;
3719 iommu
= amd_iommu_rlookup_table
[devid
];
3723 table
= get_irq_table(devid
, false);
3727 spin_lock_irqsave(&table
->lock
, flags
);
3729 entry
= (struct irte_ga
*)table
->table
;
3730 entry
= &entry
[index
];
3731 entry
->lo
.fields_remap
.valid
= 0;
3732 entry
->hi
.val
= irte
->hi
.val
;
3733 entry
->lo
.val
= irte
->lo
.val
;
3734 entry
->lo
.fields_remap
.valid
= 1;
3738 spin_unlock_irqrestore(&table
->lock
, flags
);
3740 iommu_flush_irt(iommu
, devid
);
3741 iommu_completion_wait(iommu
);
3746 static int modify_irte(u16 devid
, int index
, union irte
*irte
)
3748 struct irq_remap_table
*table
;
3749 struct amd_iommu
*iommu
;
3750 unsigned long flags
;
3752 iommu
= amd_iommu_rlookup_table
[devid
];
3756 table
= get_irq_table(devid
, false);
3760 spin_lock_irqsave(&table
->lock
, flags
);
3761 table
->table
[index
] = irte
->val
;
3762 spin_unlock_irqrestore(&table
->lock
, flags
);
3764 iommu_flush_irt(iommu
, devid
);
3765 iommu_completion_wait(iommu
);
3770 static void free_irte(u16 devid
, int index
)
3772 struct irq_remap_table
*table
;
3773 struct amd_iommu
*iommu
;
3774 unsigned long flags
;
3776 iommu
= amd_iommu_rlookup_table
[devid
];
3780 table
= get_irq_table(devid
, false);
3784 spin_lock_irqsave(&table
->lock
, flags
);
3785 iommu
->irte_ops
->clear_allocated(table
, index
);
3786 spin_unlock_irqrestore(&table
->lock
, flags
);
3788 iommu_flush_irt(iommu
, devid
);
3789 iommu_completion_wait(iommu
);
3792 static void irte_prepare(void *entry
,
3793 u32 delivery_mode
, u32 dest_mode
,
3794 u8 vector
, u32 dest_apicid
, int devid
)
3796 union irte
*irte
= (union irte
*) entry
;
3799 irte
->fields
.vector
= vector
;
3800 irte
->fields
.int_type
= delivery_mode
;
3801 irte
->fields
.destination
= dest_apicid
;
3802 irte
->fields
.dm
= dest_mode
;
3803 irte
->fields
.valid
= 1;
3806 static void irte_ga_prepare(void *entry
,
3807 u32 delivery_mode
, u32 dest_mode
,
3808 u8 vector
, u32 dest_apicid
, int devid
)
3810 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3814 irte
->lo
.fields_remap
.int_type
= delivery_mode
;
3815 irte
->lo
.fields_remap
.dm
= dest_mode
;
3816 irte
->hi
.fields
.vector
= vector
;
3817 irte
->lo
.fields_remap
.destination
= dest_apicid
;
3818 irte
->lo
.fields_remap
.valid
= 1;
3821 static void irte_activate(void *entry
, u16 devid
, u16 index
)
3823 union irte
*irte
= (union irte
*) entry
;
3825 irte
->fields
.valid
= 1;
3826 modify_irte(devid
, index
, irte
);
3829 static void irte_ga_activate(void *entry
, u16 devid
, u16 index
)
3831 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3833 irte
->lo
.fields_remap
.valid
= 1;
3834 modify_irte_ga(devid
, index
, irte
, NULL
);
3837 static void irte_deactivate(void *entry
, u16 devid
, u16 index
)
3839 union irte
*irte
= (union irte
*) entry
;
3841 irte
->fields
.valid
= 0;
3842 modify_irte(devid
, index
, irte
);
3845 static void irte_ga_deactivate(void *entry
, u16 devid
, u16 index
)
3847 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3849 irte
->lo
.fields_remap
.valid
= 0;
3850 modify_irte_ga(devid
, index
, irte
, NULL
);
3853 static void irte_set_affinity(void *entry
, u16 devid
, u16 index
,
3854 u8 vector
, u32 dest_apicid
)
3856 union irte
*irte
= (union irte
*) entry
;
3858 irte
->fields
.vector
= vector
;
3859 irte
->fields
.destination
= dest_apicid
;
3860 modify_irte(devid
, index
, irte
);
3863 static void irte_ga_set_affinity(void *entry
, u16 devid
, u16 index
,
3864 u8 vector
, u32 dest_apicid
)
3866 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3867 struct iommu_dev_data
*dev_data
= search_dev_data(devid
);
3869 if (!dev_data
|| !dev_data
->use_vapic
||
3870 !irte
->lo
.fields_remap
.guest_mode
) {
3871 irte
->hi
.fields
.vector
= vector
;
3872 irte
->lo
.fields_remap
.destination
= dest_apicid
;
3873 modify_irte_ga(devid
, index
, irte
, NULL
);
3877 #define IRTE_ALLOCATED (~1U)
3878 static void irte_set_allocated(struct irq_remap_table
*table
, int index
)
3880 table
->table
[index
] = IRTE_ALLOCATED
;
3883 static void irte_ga_set_allocated(struct irq_remap_table
*table
, int index
)
3885 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3886 struct irte_ga
*irte
= &ptr
[index
];
3888 memset(&irte
->lo
.val
, 0, sizeof(u64
));
3889 memset(&irte
->hi
.val
, 0, sizeof(u64
));
3890 irte
->hi
.fields
.vector
= 0xff;
3893 static bool irte_is_allocated(struct irq_remap_table
*table
, int index
)
3895 union irte
*ptr
= (union irte
*)table
->table
;
3896 union irte
*irte
= &ptr
[index
];
3898 return irte
->val
!= 0;
3901 static bool irte_ga_is_allocated(struct irq_remap_table
*table
, int index
)
3903 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3904 struct irte_ga
*irte
= &ptr
[index
];
3906 return irte
->hi
.fields
.vector
!= 0;
3909 static void irte_clear_allocated(struct irq_remap_table
*table
, int index
)
3911 table
->table
[index
] = 0;
3914 static void irte_ga_clear_allocated(struct irq_remap_table
*table
, int index
)
3916 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3917 struct irte_ga
*irte
= &ptr
[index
];
3919 memset(&irte
->lo
.val
, 0, sizeof(u64
));
3920 memset(&irte
->hi
.val
, 0, sizeof(u64
));
3923 static int get_devid(struct irq_alloc_info
*info
)
3927 switch (info
->type
) {
3928 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
3929 devid
= get_ioapic_devid(info
->ioapic_id
);
3931 case X86_IRQ_ALLOC_TYPE_HPET
:
3932 devid
= get_hpet_devid(info
->hpet_id
);
3934 case X86_IRQ_ALLOC_TYPE_MSI
:
3935 case X86_IRQ_ALLOC_TYPE_MSIX
:
3936 devid
= get_device_id(&info
->msi_dev
->dev
);
3946 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
3948 struct amd_iommu
*iommu
;
3954 devid
= get_devid(info
);
3956 iommu
= amd_iommu_rlookup_table
[devid
];
3958 return iommu
->ir_domain
;
3964 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
3966 struct amd_iommu
*iommu
;
3972 switch (info
->type
) {
3973 case X86_IRQ_ALLOC_TYPE_MSI
:
3974 case X86_IRQ_ALLOC_TYPE_MSIX
:
3975 devid
= get_device_id(&info
->msi_dev
->dev
);
3979 iommu
= amd_iommu_rlookup_table
[devid
];
3981 return iommu
->msi_domain
;
3990 struct irq_remap_ops amd_iommu_irq_ops
= {
3991 .prepare
= amd_iommu_prepare
,
3992 .enable
= amd_iommu_enable
,
3993 .disable
= amd_iommu_disable
,
3994 .reenable
= amd_iommu_reenable
,
3995 .enable_faulting
= amd_iommu_enable_faulting
,
3996 .get_ir_irq_domain
= get_ir_irq_domain
,
3997 .get_irq_domain
= get_irq_domain
,
4000 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
4001 struct irq_cfg
*irq_cfg
,
4002 struct irq_alloc_info
*info
,
4003 int devid
, int index
, int sub_handle
)
4005 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4006 struct msi_msg
*msg
= &data
->msi_entry
;
4007 struct IO_APIC_route_entry
*entry
;
4008 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
4013 data
->irq_2_irte
.devid
= devid
;
4014 data
->irq_2_irte
.index
= index
+ sub_handle
;
4015 iommu
->irte_ops
->prepare(data
->entry
, apic
->irq_delivery_mode
,
4016 apic
->irq_dest_mode
, irq_cfg
->vector
,
4017 irq_cfg
->dest_apicid
, devid
);
4019 switch (info
->type
) {
4020 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4021 /* Setup IOAPIC entry */
4022 entry
= info
->ioapic_entry
;
4023 info
->ioapic_entry
= NULL
;
4024 memset(entry
, 0, sizeof(*entry
));
4025 entry
->vector
= index
;
4027 entry
->trigger
= info
->ioapic_trigger
;
4028 entry
->polarity
= info
->ioapic_polarity
;
4029 /* Mask level triggered irqs. */
4030 if (info
->ioapic_trigger
)
4034 case X86_IRQ_ALLOC_TYPE_HPET
:
4035 case X86_IRQ_ALLOC_TYPE_MSI
:
4036 case X86_IRQ_ALLOC_TYPE_MSIX
:
4037 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4038 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4039 msg
->data
= irte_info
->index
;
4048 struct amd_irte_ops irte_32_ops
= {
4049 .prepare
= irte_prepare
,
4050 .activate
= irte_activate
,
4051 .deactivate
= irte_deactivate
,
4052 .set_affinity
= irte_set_affinity
,
4053 .set_allocated
= irte_set_allocated
,
4054 .is_allocated
= irte_is_allocated
,
4055 .clear_allocated
= irte_clear_allocated
,
4058 struct amd_irte_ops irte_128_ops
= {
4059 .prepare
= irte_ga_prepare
,
4060 .activate
= irte_ga_activate
,
4061 .deactivate
= irte_ga_deactivate
,
4062 .set_affinity
= irte_ga_set_affinity
,
4063 .set_allocated
= irte_ga_set_allocated
,
4064 .is_allocated
= irte_ga_is_allocated
,
4065 .clear_allocated
= irte_ga_clear_allocated
,
4068 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4069 unsigned int nr_irqs
, void *arg
)
4071 struct irq_alloc_info
*info
= arg
;
4072 struct irq_data
*irq_data
;
4073 struct amd_ir_data
*data
= NULL
;
4074 struct irq_cfg
*cfg
;
4080 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4081 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4085 * With IRQ remapping enabled, don't need contiguous CPU vectors
4086 * to support multiple MSI interrupts.
4088 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4089 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4091 devid
= get_devid(info
);
4095 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4099 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4100 if (get_irq_table(devid
, true))
4101 index
= info
->ioapic_pin
;
4105 bool align
= (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
);
4107 index
= alloc_irq_index(devid
, nr_irqs
, align
);
4110 pr_warn("Failed to allocate IRTE\n");
4112 goto out_free_parent
;
4115 for (i
= 0; i
< nr_irqs
; i
++) {
4116 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4117 cfg
= irqd_cfg(irq_data
);
4118 if (!irq_data
|| !cfg
) {
4124 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4128 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
4129 data
->entry
= kzalloc(sizeof(union irte
), GFP_KERNEL
);
4131 data
->entry
= kzalloc(sizeof(struct irte_ga
),
4138 irq_data
->hwirq
= (devid
<< 16) + i
;
4139 irq_data
->chip_data
= data
;
4140 irq_data
->chip
= &amd_ir_chip
;
4141 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4142 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4148 for (i
--; i
>= 0; i
--) {
4149 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4151 kfree(irq_data
->chip_data
);
4153 for (i
= 0; i
< nr_irqs
; i
++)
4154 free_irte(devid
, index
+ i
);
4156 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4160 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4161 unsigned int nr_irqs
)
4163 struct irq_2_irte
*irte_info
;
4164 struct irq_data
*irq_data
;
4165 struct amd_ir_data
*data
;
4168 for (i
= 0; i
< nr_irqs
; i
++) {
4169 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4170 if (irq_data
&& irq_data
->chip_data
) {
4171 data
= irq_data
->chip_data
;
4172 irte_info
= &data
->irq_2_irte
;
4173 free_irte(irte_info
->devid
, irte_info
->index
);
4178 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4181 static void amd_ir_update_irte(struct irq_data
*irqd
, struct amd_iommu
*iommu
,
4182 struct amd_ir_data
*ir_data
,
4183 struct irq_2_irte
*irte_info
,
4184 struct irq_cfg
*cfg
);
4186 static int irq_remapping_activate(struct irq_domain
*domain
,
4187 struct irq_data
*irq_data
, bool early
)
4189 struct amd_ir_data
*data
= irq_data
->chip_data
;
4190 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4191 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4192 struct irq_cfg
*cfg
= irqd_cfg(irq_data
);
4197 iommu
->irte_ops
->activate(data
->entry
, irte_info
->devid
,
4199 amd_ir_update_irte(irq_data
, iommu
, data
, irte_info
, cfg
);
4203 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4204 struct irq_data
*irq_data
)
4206 struct amd_ir_data
*data
= irq_data
->chip_data
;
4207 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4208 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4211 iommu
->irte_ops
->deactivate(data
->entry
, irte_info
->devid
,
4215 static const struct irq_domain_ops amd_ir_domain_ops
= {
4216 .alloc
= irq_remapping_alloc
,
4217 .free
= irq_remapping_free
,
4218 .activate
= irq_remapping_activate
,
4219 .deactivate
= irq_remapping_deactivate
,
4222 static int amd_ir_set_vcpu_affinity(struct irq_data
*data
, void *vcpu_info
)
4224 struct amd_iommu
*iommu
;
4225 struct amd_iommu_pi_data
*pi_data
= vcpu_info
;
4226 struct vcpu_data
*vcpu_pi_info
= pi_data
->vcpu_data
;
4227 struct amd_ir_data
*ir_data
= data
->chip_data
;
4228 struct irte_ga
*irte
= (struct irte_ga
*) ir_data
->entry
;
4229 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4230 struct iommu_dev_data
*dev_data
= search_dev_data(irte_info
->devid
);
4233 * This device has never been set up for guest mode.
4234 * we should not modify the IRTE
4236 if (!dev_data
|| !dev_data
->use_vapic
)
4239 pi_data
->ir_data
= ir_data
;
4242 * SVM tries to set up for VAPIC mode, but we are in
4243 * legacy mode. So, we force legacy mode instead.
4245 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
4246 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4248 pi_data
->is_guest_mode
= false;
4251 iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4255 pi_data
->prev_ga_tag
= ir_data
->cached_ga_tag
;
4256 if (pi_data
->is_guest_mode
) {
4258 irte
->hi
.fields
.ga_root_ptr
= (pi_data
->base
>> 12);
4259 irte
->hi
.fields
.vector
= vcpu_pi_info
->vector
;
4260 irte
->lo
.fields_vapic
.ga_log_intr
= 1;
4261 irte
->lo
.fields_vapic
.guest_mode
= 1;
4262 irte
->lo
.fields_vapic
.ga_tag
= pi_data
->ga_tag
;
4264 ir_data
->cached_ga_tag
= pi_data
->ga_tag
;
4267 struct irq_cfg
*cfg
= irqd_cfg(data
);
4271 irte
->hi
.fields
.vector
= cfg
->vector
;
4272 irte
->lo
.fields_remap
.guest_mode
= 0;
4273 irte
->lo
.fields_remap
.destination
= cfg
->dest_apicid
;
4274 irte
->lo
.fields_remap
.int_type
= apic
->irq_delivery_mode
;
4275 irte
->lo
.fields_remap
.dm
= apic
->irq_dest_mode
;
4278 * This communicates the ga_tag back to the caller
4279 * so that it can do all the necessary clean up.
4281 ir_data
->cached_ga_tag
= 0;
4284 return modify_irte_ga(irte_info
->devid
, irte_info
->index
, irte
, ir_data
);
4288 static void amd_ir_update_irte(struct irq_data
*irqd
, struct amd_iommu
*iommu
,
4289 struct amd_ir_data
*ir_data
,
4290 struct irq_2_irte
*irte_info
,
4291 struct irq_cfg
*cfg
)
4295 * Atomically updates the IRTE with the new destination, vector
4296 * and flushes the interrupt entry cache.
4298 iommu
->irte_ops
->set_affinity(ir_data
->entry
, irte_info
->devid
,
4299 irte_info
->index
, cfg
->vector
,
4303 static int amd_ir_set_affinity(struct irq_data
*data
,
4304 const struct cpumask
*mask
, bool force
)
4306 struct amd_ir_data
*ir_data
= data
->chip_data
;
4307 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4308 struct irq_cfg
*cfg
= irqd_cfg(data
);
4309 struct irq_data
*parent
= data
->parent_data
;
4310 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4316 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4317 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4320 amd_ir_update_irte(data
, iommu
, ir_data
, irte_info
, cfg
);
4322 * After this point, all the interrupts will start arriving
4323 * at the new destination. So, time to cleanup the previous
4324 * vector allocation.
4326 send_cleanup_vector(cfg
);
4328 return IRQ_SET_MASK_OK_DONE
;
4331 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4333 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4335 *msg
= ir_data
->msi_entry
;
4338 static struct irq_chip amd_ir_chip
= {
4340 .irq_ack
= ir_ack_apic_edge
,
4341 .irq_set_affinity
= amd_ir_set_affinity
,
4342 .irq_set_vcpu_affinity
= amd_ir_set_vcpu_affinity
,
4343 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4346 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4348 struct fwnode_handle
*fn
;
4350 fn
= irq_domain_alloc_named_id_fwnode("AMD-IR", iommu
->index
);
4353 iommu
->ir_domain
= irq_domain_create_tree(fn
, &amd_ir_domain_ops
, iommu
);
4354 irq_domain_free_fwnode(fn
);
4355 if (!iommu
->ir_domain
)
4358 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4359 iommu
->msi_domain
= arch_create_remap_msi_irq_domain(iommu
->ir_domain
,
4365 int amd_iommu_update_ga(int cpu
, bool is_run
, void *data
)
4367 unsigned long flags
;
4368 struct amd_iommu
*iommu
;
4369 struct irq_remap_table
*irt
;
4370 struct amd_ir_data
*ir_data
= (struct amd_ir_data
*)data
;
4371 int devid
= ir_data
->irq_2_irte
.devid
;
4372 struct irte_ga
*entry
= (struct irte_ga
*) ir_data
->entry
;
4373 struct irte_ga
*ref
= (struct irte_ga
*) ir_data
->ref
;
4375 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) ||
4376 !ref
|| !entry
|| !entry
->lo
.fields_vapic
.guest_mode
)
4379 iommu
= amd_iommu_rlookup_table
[devid
];
4383 irt
= get_irq_table(devid
, false);
4387 spin_lock_irqsave(&irt
->lock
, flags
);
4389 if (ref
->lo
.fields_vapic
.guest_mode
) {
4391 ref
->lo
.fields_vapic
.destination
= cpu
;
4392 ref
->lo
.fields_vapic
.is_run
= is_run
;
4396 spin_unlock_irqrestore(&irt
->lock
, flags
);
4398 iommu_flush_irt(iommu
, devid
);
4399 iommu_completion_wait(iommu
);
4402 EXPORT_SYMBOL(amd_iommu_update_ga
);