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iommu/amd: Enforce alignment for MSI IRQs
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define AMD_IOMMU_MAPPING_ERROR 0
58
59 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
60
61 #define LOOP_TIMEOUT 100000
62
63 /* IO virtual address start page frame number */
64 #define IOVA_START_PFN (1)
65 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
66 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
67
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
73
74 /*
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
78 * that we support.
79 *
80 * 512GB Pages are not supported due to a hardware bug
81 */
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
83
84 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
85
86 /* List of all available dev_data structures */
87 static LIST_HEAD(dev_data_list);
88 static DEFINE_SPINLOCK(dev_data_list_lock);
89
90 LIST_HEAD(ioapic_map);
91 LIST_HEAD(hpet_map);
92 LIST_HEAD(acpihid_map);
93
94 /*
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
97 */
98 const struct iommu_ops amd_iommu_ops;
99
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
101 int amd_iommu_max_glx_val = -1;
102
103 static const struct dma_map_ops amd_iommu_dma_ops;
104
105 /*
106 * general struct to manage commands send to an IOMMU
107 */
108 struct iommu_cmd {
109 u32 data[4];
110 };
111
112 struct kmem_cache *amd_iommu_irq_cache;
113
114 static void update_domain(struct protection_domain *domain);
115 static int protection_domain_init(struct protection_domain *domain);
116 static void detach_device(struct device *dev);
117 static void iova_domain_flush_tlb(struct iova_domain *iovad);
118
119 /*
120 * Data container for a dma_ops specific protection domain
121 */
122 struct dma_ops_domain {
123 /* generic protection domain information */
124 struct protection_domain domain;
125
126 /* IOVA RB-Tree */
127 struct iova_domain iovad;
128 };
129
130 static struct iova_domain reserved_iova_ranges;
131 static struct lock_class_key reserved_rbtree_key;
132
133 /****************************************************************************
134 *
135 * Helper functions
136 *
137 ****************************************************************************/
138
139 static inline int match_hid_uid(struct device *dev,
140 struct acpihid_map_entry *entry)
141 {
142 const char *hid, *uid;
143
144 hid = acpi_device_hid(ACPI_COMPANION(dev));
145 uid = acpi_device_uid(ACPI_COMPANION(dev));
146
147 if (!hid || !(*hid))
148 return -ENODEV;
149
150 if (!uid || !(*uid))
151 return strcmp(hid, entry->hid);
152
153 if (!(*entry->uid))
154 return strcmp(hid, entry->hid);
155
156 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
157 }
158
159 static inline u16 get_pci_device_id(struct device *dev)
160 {
161 struct pci_dev *pdev = to_pci_dev(dev);
162
163 return PCI_DEVID(pdev->bus->number, pdev->devfn);
164 }
165
166 static inline int get_acpihid_device_id(struct device *dev,
167 struct acpihid_map_entry **entry)
168 {
169 struct acpihid_map_entry *p;
170
171 list_for_each_entry(p, &acpihid_map, list) {
172 if (!match_hid_uid(dev, p)) {
173 if (entry)
174 *entry = p;
175 return p->devid;
176 }
177 }
178 return -EINVAL;
179 }
180
181 static inline int get_device_id(struct device *dev)
182 {
183 int devid;
184
185 if (dev_is_pci(dev))
186 devid = get_pci_device_id(dev);
187 else
188 devid = get_acpihid_device_id(dev, NULL);
189
190 return devid;
191 }
192
193 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
194 {
195 return container_of(dom, struct protection_domain, domain);
196 }
197
198 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
199 {
200 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
201 return container_of(domain, struct dma_ops_domain, domain);
202 }
203
204 static struct iommu_dev_data *alloc_dev_data(u16 devid)
205 {
206 struct iommu_dev_data *dev_data;
207 unsigned long flags;
208
209 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
210 if (!dev_data)
211 return NULL;
212
213 dev_data->devid = devid;
214
215 spin_lock_irqsave(&dev_data_list_lock, flags);
216 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
217 spin_unlock_irqrestore(&dev_data_list_lock, flags);
218
219 ratelimit_default_init(&dev_data->rs);
220
221 return dev_data;
222 }
223
224 static struct iommu_dev_data *search_dev_data(u16 devid)
225 {
226 struct iommu_dev_data *dev_data;
227 unsigned long flags;
228
229 spin_lock_irqsave(&dev_data_list_lock, flags);
230 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
231 if (dev_data->devid == devid)
232 goto out_unlock;
233 }
234
235 dev_data = NULL;
236
237 out_unlock:
238 spin_unlock_irqrestore(&dev_data_list_lock, flags);
239
240 return dev_data;
241 }
242
243 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
244 {
245 *(u16 *)data = alias;
246 return 0;
247 }
248
249 static u16 get_alias(struct device *dev)
250 {
251 struct pci_dev *pdev = to_pci_dev(dev);
252 u16 devid, ivrs_alias, pci_alias;
253
254 /* The callers make sure that get_device_id() does not fail here */
255 devid = get_device_id(dev);
256 ivrs_alias = amd_iommu_alias_table[devid];
257 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
258
259 if (ivrs_alias == pci_alias)
260 return ivrs_alias;
261
262 /*
263 * DMA alias showdown
264 *
265 * The IVRS is fairly reliable in telling us about aliases, but it
266 * can't know about every screwy device. If we don't have an IVRS
267 * reported alias, use the PCI reported alias. In that case we may
268 * still need to initialize the rlookup and dev_table entries if the
269 * alias is to a non-existent device.
270 */
271 if (ivrs_alias == devid) {
272 if (!amd_iommu_rlookup_table[pci_alias]) {
273 amd_iommu_rlookup_table[pci_alias] =
274 amd_iommu_rlookup_table[devid];
275 memcpy(amd_iommu_dev_table[pci_alias].data,
276 amd_iommu_dev_table[devid].data,
277 sizeof(amd_iommu_dev_table[pci_alias].data));
278 }
279
280 return pci_alias;
281 }
282
283 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
284 "for device %s[%04x:%04x], kernel reported alias "
285 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
286 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
287 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
288 PCI_FUNC(pci_alias));
289
290 /*
291 * If we don't have a PCI DMA alias and the IVRS alias is on the same
292 * bus, then the IVRS table may know about a quirk that we don't.
293 */
294 if (pci_alias == devid &&
295 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
296 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
297 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
298 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
299 dev_name(dev));
300 }
301
302 return ivrs_alias;
303 }
304
305 static struct iommu_dev_data *find_dev_data(u16 devid)
306 {
307 struct iommu_dev_data *dev_data;
308 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
309
310 dev_data = search_dev_data(devid);
311
312 if (dev_data == NULL) {
313 dev_data = alloc_dev_data(devid);
314
315 if (translation_pre_enabled(iommu))
316 dev_data->defer_attach = true;
317 }
318
319 return dev_data;
320 }
321
322 struct iommu_dev_data *get_dev_data(struct device *dev)
323 {
324 return dev->archdata.iommu;
325 }
326 EXPORT_SYMBOL(get_dev_data);
327
328 /*
329 * Find or create an IOMMU group for a acpihid device.
330 */
331 static struct iommu_group *acpihid_device_group(struct device *dev)
332 {
333 struct acpihid_map_entry *p, *entry = NULL;
334 int devid;
335
336 devid = get_acpihid_device_id(dev, &entry);
337 if (devid < 0)
338 return ERR_PTR(devid);
339
340 list_for_each_entry(p, &acpihid_map, list) {
341 if ((devid == p->devid) && p->group)
342 entry->group = p->group;
343 }
344
345 if (!entry->group)
346 entry->group = generic_device_group(dev);
347 else
348 iommu_group_ref_get(entry->group);
349
350 return entry->group;
351 }
352
353 static bool pci_iommuv2_capable(struct pci_dev *pdev)
354 {
355 static const int caps[] = {
356 PCI_EXT_CAP_ID_ATS,
357 PCI_EXT_CAP_ID_PRI,
358 PCI_EXT_CAP_ID_PASID,
359 };
360 int i, pos;
361
362 for (i = 0; i < 3; ++i) {
363 pos = pci_find_ext_capability(pdev, caps[i]);
364 if (pos == 0)
365 return false;
366 }
367
368 return true;
369 }
370
371 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
372 {
373 struct iommu_dev_data *dev_data;
374
375 dev_data = get_dev_data(&pdev->dev);
376
377 return dev_data->errata & (1 << erratum) ? true : false;
378 }
379
380 /*
381 * This function checks if the driver got a valid device from the caller to
382 * avoid dereferencing invalid pointers.
383 */
384 static bool check_device(struct device *dev)
385 {
386 int devid;
387
388 if (!dev || !dev->dma_mask)
389 return false;
390
391 devid = get_device_id(dev);
392 if (devid < 0)
393 return false;
394
395 /* Out of our scope? */
396 if (devid > amd_iommu_last_bdf)
397 return false;
398
399 if (amd_iommu_rlookup_table[devid] == NULL)
400 return false;
401
402 return true;
403 }
404
405 static void init_iommu_group(struct device *dev)
406 {
407 struct iommu_group *group;
408
409 group = iommu_group_get_for_dev(dev);
410 if (IS_ERR(group))
411 return;
412
413 iommu_group_put(group);
414 }
415
416 static int iommu_init_device(struct device *dev)
417 {
418 struct iommu_dev_data *dev_data;
419 struct amd_iommu *iommu;
420 int devid;
421
422 if (dev->archdata.iommu)
423 return 0;
424
425 devid = get_device_id(dev);
426 if (devid < 0)
427 return devid;
428
429 iommu = amd_iommu_rlookup_table[devid];
430
431 dev_data = find_dev_data(devid);
432 if (!dev_data)
433 return -ENOMEM;
434
435 dev_data->alias = get_alias(dev);
436
437 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
438 struct amd_iommu *iommu;
439
440 iommu = amd_iommu_rlookup_table[dev_data->devid];
441 dev_data->iommu_v2 = iommu->is_iommu_v2;
442 }
443
444 dev->archdata.iommu = dev_data;
445
446 iommu_device_link(&iommu->iommu, dev);
447
448 return 0;
449 }
450
451 static void iommu_ignore_device(struct device *dev)
452 {
453 u16 alias;
454 int devid;
455
456 devid = get_device_id(dev);
457 if (devid < 0)
458 return;
459
460 alias = get_alias(dev);
461
462 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
463 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
464
465 amd_iommu_rlookup_table[devid] = NULL;
466 amd_iommu_rlookup_table[alias] = NULL;
467 }
468
469 static void iommu_uninit_device(struct device *dev)
470 {
471 struct iommu_dev_data *dev_data;
472 struct amd_iommu *iommu;
473 int devid;
474
475 devid = get_device_id(dev);
476 if (devid < 0)
477 return;
478
479 iommu = amd_iommu_rlookup_table[devid];
480
481 dev_data = search_dev_data(devid);
482 if (!dev_data)
483 return;
484
485 if (dev_data->domain)
486 detach_device(dev);
487
488 iommu_device_unlink(&iommu->iommu, dev);
489
490 iommu_group_remove_device(dev);
491
492 /* Remove dma-ops */
493 dev->dma_ops = NULL;
494
495 /*
496 * We keep dev_data around for unplugged devices and reuse it when the
497 * device is re-plugged - not doing so would introduce a ton of races.
498 */
499 }
500
501 /****************************************************************************
502 *
503 * Interrupt handling functions
504 *
505 ****************************************************************************/
506
507 static void dump_dte_entry(u16 devid)
508 {
509 int i;
510
511 for (i = 0; i < 4; ++i)
512 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
513 amd_iommu_dev_table[devid].data[i]);
514 }
515
516 static void dump_command(unsigned long phys_addr)
517 {
518 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
519 int i;
520
521 for (i = 0; i < 4; ++i)
522 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
523 }
524
525 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
526 u64 address, int flags)
527 {
528 struct iommu_dev_data *dev_data = NULL;
529 struct pci_dev *pdev;
530
531 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
532 if (pdev)
533 dev_data = get_dev_data(&pdev->dev);
534
535 if (dev_data && __ratelimit(&dev_data->rs)) {
536 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
537 domain_id, address, flags);
538 } else if (printk_ratelimit()) {
539 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
540 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
541 domain_id, address, flags);
542 }
543
544 if (pdev)
545 pci_dev_put(pdev);
546 }
547
548 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 {
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 if (type == EVENT_TYPE_IO_FAULT) {
573 amd_iommu_report_page_fault(devid, domid, address, flags);
574 return;
575 } else {
576 printk(KERN_ERR "AMD-Vi: Event logged [");
577 }
578
579 switch (type) {
580 case EVENT_TYPE_ILL_DEV:
581 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
582 "address=0x%016llx flags=0x%04x]\n",
583 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
584 address, flags);
585 dump_dte_entry(devid);
586 break;
587 case EVENT_TYPE_DEV_TAB_ERR:
588 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
589 "address=0x%016llx flags=0x%04x]\n",
590 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
591 address, flags);
592 break;
593 case EVENT_TYPE_PAGE_TAB_ERR:
594 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
595 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
596 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
597 domid, address, flags);
598 break;
599 case EVENT_TYPE_ILL_CMD:
600 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
601 dump_command(address);
602 break;
603 case EVENT_TYPE_CMD_HARD_ERR:
604 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
605 "flags=0x%04x]\n", address, flags);
606 break;
607 case EVENT_TYPE_IOTLB_INV_TO:
608 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
609 "address=0x%016llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 address);
612 break;
613 case EVENT_TYPE_INV_DEV_REQ:
614 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 address, flags);
618 break;
619 default:
620 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
621 }
622
623 memset(__evt, 0, 4 * sizeof(u32));
624 }
625
626 static void iommu_poll_events(struct amd_iommu *iommu)
627 {
628 u32 head, tail;
629
630 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
631 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
632
633 while (head != tail) {
634 iommu_print_event(iommu, iommu->evt_buf + head);
635 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
636 }
637
638 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 }
640
641 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
642 {
643 struct amd_iommu_fault fault;
644
645 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
646 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
647 return;
648 }
649
650 fault.address = raw[1];
651 fault.pasid = PPR_PASID(raw[0]);
652 fault.device_id = PPR_DEVID(raw[0]);
653 fault.tag = PPR_TAG(raw[0]);
654 fault.flags = PPR_FLAGS(raw[0]);
655
656 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
657 }
658
659 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
660 {
661 u32 head, tail;
662
663 if (iommu->ppr_log == NULL)
664 return;
665
666 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
668
669 while (head != tail) {
670 volatile u64 *raw;
671 u64 entry[2];
672 int i;
673
674 raw = (u64 *)(iommu->ppr_log + head);
675
676 /*
677 * Hardware bug: Interrupt may arrive before the entry is
678 * written to memory. If this happens we need to wait for the
679 * entry to arrive.
680 */
681 for (i = 0; i < LOOP_TIMEOUT; ++i) {
682 if (PPR_REQ_TYPE(raw[0]) != 0)
683 break;
684 udelay(1);
685 }
686
687 /* Avoid memcpy function-call overhead */
688 entry[0] = raw[0];
689 entry[1] = raw[1];
690
691 /*
692 * To detect the hardware bug we need to clear the entry
693 * back to zero.
694 */
695 raw[0] = raw[1] = 0UL;
696
697 /* Update head pointer of hardware ring-buffer */
698 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
699 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700
701 /* Handle PPR entry */
702 iommu_handle_ppr_entry(iommu, entry);
703
704 /* Refresh ring-buffer information */
705 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
706 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
707 }
708 }
709
710 #ifdef CONFIG_IRQ_REMAP
711 static int (*iommu_ga_log_notifier)(u32);
712
713 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
714 {
715 iommu_ga_log_notifier = notifier;
716
717 return 0;
718 }
719 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
720
721 static void iommu_poll_ga_log(struct amd_iommu *iommu)
722 {
723 u32 head, tail, cnt = 0;
724
725 if (iommu->ga_log == NULL)
726 return;
727
728 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
729 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
730
731 while (head != tail) {
732 volatile u64 *raw;
733 u64 log_entry;
734
735 raw = (u64 *)(iommu->ga_log + head);
736 cnt++;
737
738 /* Avoid memcpy function-call overhead */
739 log_entry = *raw;
740
741 /* Update head pointer of hardware ring-buffer */
742 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
743 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
744
745 /* Handle GA entry */
746 switch (GA_REQ_TYPE(log_entry)) {
747 case GA_GUEST_NR:
748 if (!iommu_ga_log_notifier)
749 break;
750
751 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
752 __func__, GA_DEVID(log_entry),
753 GA_TAG(log_entry));
754
755 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
756 pr_err("AMD-Vi: GA log notifier failed.\n");
757 break;
758 default:
759 break;
760 }
761 }
762 }
763 #endif /* CONFIG_IRQ_REMAP */
764
765 #define AMD_IOMMU_INT_MASK \
766 (MMIO_STATUS_EVT_INT_MASK | \
767 MMIO_STATUS_PPR_INT_MASK | \
768 MMIO_STATUS_GALOG_INT_MASK)
769
770 irqreturn_t amd_iommu_int_thread(int irq, void *data)
771 {
772 struct amd_iommu *iommu = (struct amd_iommu *) data;
773 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
774
775 while (status & AMD_IOMMU_INT_MASK) {
776 /* Enable EVT and PPR and GA interrupts again */
777 writel(AMD_IOMMU_INT_MASK,
778 iommu->mmio_base + MMIO_STATUS_OFFSET);
779
780 if (status & MMIO_STATUS_EVT_INT_MASK) {
781 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
782 iommu_poll_events(iommu);
783 }
784
785 if (status & MMIO_STATUS_PPR_INT_MASK) {
786 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
787 iommu_poll_ppr_log(iommu);
788 }
789
790 #ifdef CONFIG_IRQ_REMAP
791 if (status & MMIO_STATUS_GALOG_INT_MASK) {
792 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
793 iommu_poll_ga_log(iommu);
794 }
795 #endif
796
797 /*
798 * Hardware bug: ERBT1312
799 * When re-enabling interrupt (by writing 1
800 * to clear the bit), the hardware might also try to set
801 * the interrupt bit in the event status register.
802 * In this scenario, the bit will be set, and disable
803 * subsequent interrupts.
804 *
805 * Workaround: The IOMMU driver should read back the
806 * status register and check if the interrupt bits are cleared.
807 * If not, driver will need to go through the interrupt handler
808 * again and re-clear the bits
809 */
810 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
811 }
812 return IRQ_HANDLED;
813 }
814
815 irqreturn_t amd_iommu_int_handler(int irq, void *data)
816 {
817 return IRQ_WAKE_THREAD;
818 }
819
820 /****************************************************************************
821 *
822 * IOMMU command queuing functions
823 *
824 ****************************************************************************/
825
826 static int wait_on_sem(volatile u64 *sem)
827 {
828 int i = 0;
829
830 while (*sem == 0 && i < LOOP_TIMEOUT) {
831 udelay(1);
832 i += 1;
833 }
834
835 if (i == LOOP_TIMEOUT) {
836 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
837 return -EIO;
838 }
839
840 return 0;
841 }
842
843 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
844 struct iommu_cmd *cmd)
845 {
846 u8 *target;
847
848 target = iommu->cmd_buf + iommu->cmd_buf_tail;
849
850 iommu->cmd_buf_tail += sizeof(*cmd);
851 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
852
853 /* Copy command to buffer */
854 memcpy(target, cmd, sizeof(*cmd));
855
856 /* Tell the IOMMU about it */
857 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
858 }
859
860 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
861 {
862 u64 paddr = iommu_virt_to_phys((void *)address);
863
864 WARN_ON(address & 0x7ULL);
865
866 memset(cmd, 0, sizeof(*cmd));
867 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
868 cmd->data[1] = upper_32_bits(paddr);
869 cmd->data[2] = 1;
870 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
871 }
872
873 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
874 {
875 memset(cmd, 0, sizeof(*cmd));
876 cmd->data[0] = devid;
877 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
878 }
879
880 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
881 size_t size, u16 domid, int pde)
882 {
883 u64 pages;
884 bool s;
885
886 pages = iommu_num_pages(address, size, PAGE_SIZE);
887 s = false;
888
889 if (pages > 1) {
890 /*
891 * If we have to flush more than one page, flush all
892 * TLB entries for this domain
893 */
894 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
895 s = true;
896 }
897
898 address &= PAGE_MASK;
899
900 memset(cmd, 0, sizeof(*cmd));
901 cmd->data[1] |= domid;
902 cmd->data[2] = lower_32_bits(address);
903 cmd->data[3] = upper_32_bits(address);
904 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
905 if (s) /* size bit - we flush more than one 4kb page */
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
907 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
908 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
909 }
910
911 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
912 u64 address, size_t size)
913 {
914 u64 pages;
915 bool s;
916
917 pages = iommu_num_pages(address, size, PAGE_SIZE);
918 s = false;
919
920 if (pages > 1) {
921 /*
922 * If we have to flush more than one page, flush all
923 * TLB entries for this domain
924 */
925 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
926 s = true;
927 }
928
929 address &= PAGE_MASK;
930
931 memset(cmd, 0, sizeof(*cmd));
932 cmd->data[0] = devid;
933 cmd->data[0] |= (qdep & 0xff) << 24;
934 cmd->data[1] = devid;
935 cmd->data[2] = lower_32_bits(address);
936 cmd->data[3] = upper_32_bits(address);
937 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
938 if (s)
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
940 }
941
942 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
943 u64 address, bool size)
944 {
945 memset(cmd, 0, sizeof(*cmd));
946
947 address &= ~(0xfffULL);
948
949 cmd->data[0] = pasid;
950 cmd->data[1] = domid;
951 cmd->data[2] = lower_32_bits(address);
952 cmd->data[3] = upper_32_bits(address);
953 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
955 if (size)
956 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
957 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
958 }
959
960 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
961 int qdep, u64 address, bool size)
962 {
963 memset(cmd, 0, sizeof(*cmd));
964
965 address &= ~(0xfffULL);
966
967 cmd->data[0] = devid;
968 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
969 cmd->data[0] |= (qdep & 0xff) << 24;
970 cmd->data[1] = devid;
971 cmd->data[1] |= (pasid & 0xff) << 16;
972 cmd->data[2] = lower_32_bits(address);
973 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
974 cmd->data[3] = upper_32_bits(address);
975 if (size)
976 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
977 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
978 }
979
980 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
981 int status, int tag, bool gn)
982 {
983 memset(cmd, 0, sizeof(*cmd));
984
985 cmd->data[0] = devid;
986 if (gn) {
987 cmd->data[1] = pasid;
988 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
989 }
990 cmd->data[3] = tag & 0x1ff;
991 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
992
993 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
994 }
995
996 static void build_inv_all(struct iommu_cmd *cmd)
997 {
998 memset(cmd, 0, sizeof(*cmd));
999 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1000 }
1001
1002 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1003 {
1004 memset(cmd, 0, sizeof(*cmd));
1005 cmd->data[0] = devid;
1006 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1007 }
1008
1009 /*
1010 * Writes the command to the IOMMUs command buffer and informs the
1011 * hardware about the new command.
1012 */
1013 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1014 struct iommu_cmd *cmd,
1015 bool sync)
1016 {
1017 unsigned int count = 0;
1018 u32 left, next_tail;
1019
1020 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1021 again:
1022 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1023
1024 if (left <= 0x20) {
1025 /* Skip udelay() the first time around */
1026 if (count++) {
1027 if (count == LOOP_TIMEOUT) {
1028 pr_err("AMD-Vi: Command buffer timeout\n");
1029 return -EIO;
1030 }
1031
1032 udelay(1);
1033 }
1034
1035 /* Update head and recheck remaining space */
1036 iommu->cmd_buf_head = readl(iommu->mmio_base +
1037 MMIO_CMD_HEAD_OFFSET);
1038
1039 goto again;
1040 }
1041
1042 copy_cmd_to_buffer(iommu, cmd);
1043
1044 /* Do we need to make sure all commands are processed? */
1045 iommu->need_sync = sync;
1046
1047 return 0;
1048 }
1049
1050 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1051 struct iommu_cmd *cmd,
1052 bool sync)
1053 {
1054 unsigned long flags;
1055 int ret;
1056
1057 spin_lock_irqsave(&iommu->lock, flags);
1058 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1059 spin_unlock_irqrestore(&iommu->lock, flags);
1060
1061 return ret;
1062 }
1063
1064 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1065 {
1066 return iommu_queue_command_sync(iommu, cmd, true);
1067 }
1068
1069 /*
1070 * This function queues a completion wait command into the command
1071 * buffer of an IOMMU
1072 */
1073 static int iommu_completion_wait(struct amd_iommu *iommu)
1074 {
1075 struct iommu_cmd cmd;
1076 unsigned long flags;
1077 int ret;
1078
1079 if (!iommu->need_sync)
1080 return 0;
1081
1082
1083 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1084
1085 spin_lock_irqsave(&iommu->lock, flags);
1086
1087 iommu->cmd_sem = 0;
1088
1089 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1090 if (ret)
1091 goto out_unlock;
1092
1093 ret = wait_on_sem(&iommu->cmd_sem);
1094
1095 out_unlock:
1096 spin_unlock_irqrestore(&iommu->lock, flags);
1097
1098 return ret;
1099 }
1100
1101 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1102 {
1103 struct iommu_cmd cmd;
1104
1105 build_inv_dte(&cmd, devid);
1106
1107 return iommu_queue_command(iommu, &cmd);
1108 }
1109
1110 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1111 {
1112 u32 devid;
1113
1114 for (devid = 0; devid <= 0xffff; ++devid)
1115 iommu_flush_dte(iommu, devid);
1116
1117 iommu_completion_wait(iommu);
1118 }
1119
1120 /*
1121 * This function uses heavy locking and may disable irqs for some time. But
1122 * this is no issue because it is only called during resume.
1123 */
1124 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1125 {
1126 u32 dom_id;
1127
1128 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1129 struct iommu_cmd cmd;
1130 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1131 dom_id, 1);
1132 iommu_queue_command(iommu, &cmd);
1133 }
1134
1135 iommu_completion_wait(iommu);
1136 }
1137
1138 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1139 {
1140 struct iommu_cmd cmd;
1141
1142 build_inv_all(&cmd);
1143
1144 iommu_queue_command(iommu, &cmd);
1145 iommu_completion_wait(iommu);
1146 }
1147
1148 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1149 {
1150 struct iommu_cmd cmd;
1151
1152 build_inv_irt(&cmd, devid);
1153
1154 iommu_queue_command(iommu, &cmd);
1155 }
1156
1157 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1158 {
1159 u32 devid;
1160
1161 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1162 iommu_flush_irt(iommu, devid);
1163
1164 iommu_completion_wait(iommu);
1165 }
1166
1167 void iommu_flush_all_caches(struct amd_iommu *iommu)
1168 {
1169 if (iommu_feature(iommu, FEATURE_IA)) {
1170 amd_iommu_flush_all(iommu);
1171 } else {
1172 amd_iommu_flush_dte_all(iommu);
1173 amd_iommu_flush_irt_all(iommu);
1174 amd_iommu_flush_tlb_all(iommu);
1175 }
1176 }
1177
1178 /*
1179 * Command send function for flushing on-device TLB
1180 */
1181 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1182 u64 address, size_t size)
1183 {
1184 struct amd_iommu *iommu;
1185 struct iommu_cmd cmd;
1186 int qdep;
1187
1188 qdep = dev_data->ats.qdep;
1189 iommu = amd_iommu_rlookup_table[dev_data->devid];
1190
1191 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1192
1193 return iommu_queue_command(iommu, &cmd);
1194 }
1195
1196 /*
1197 * Command send function for invalidating a device table entry
1198 */
1199 static int device_flush_dte(struct iommu_dev_data *dev_data)
1200 {
1201 struct amd_iommu *iommu;
1202 u16 alias;
1203 int ret;
1204
1205 iommu = amd_iommu_rlookup_table[dev_data->devid];
1206 alias = dev_data->alias;
1207
1208 ret = iommu_flush_dte(iommu, dev_data->devid);
1209 if (!ret && alias != dev_data->devid)
1210 ret = iommu_flush_dte(iommu, alias);
1211 if (ret)
1212 return ret;
1213
1214 if (dev_data->ats.enabled)
1215 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1216
1217 return ret;
1218 }
1219
1220 /*
1221 * TLB invalidation function which is called from the mapping functions.
1222 * It invalidates a single PTE if the range to flush is within a single
1223 * page. Otherwise it flushes the whole TLB of the IOMMU.
1224 */
1225 static void __domain_flush_pages(struct protection_domain *domain,
1226 u64 address, size_t size, int pde)
1227 {
1228 struct iommu_dev_data *dev_data;
1229 struct iommu_cmd cmd;
1230 int ret = 0, i;
1231
1232 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1233
1234 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1235 if (!domain->dev_iommu[i])
1236 continue;
1237
1238 /*
1239 * Devices of this domain are behind this IOMMU
1240 * We need a TLB flush
1241 */
1242 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1243 }
1244
1245 list_for_each_entry(dev_data, &domain->dev_list, list) {
1246
1247 if (!dev_data->ats.enabled)
1248 continue;
1249
1250 ret |= device_flush_iotlb(dev_data, address, size);
1251 }
1252
1253 WARN_ON(ret);
1254 }
1255
1256 static void domain_flush_pages(struct protection_domain *domain,
1257 u64 address, size_t size)
1258 {
1259 __domain_flush_pages(domain, address, size, 0);
1260 }
1261
1262 /* Flush the whole IO/TLB for a given protection domain */
1263 static void domain_flush_tlb(struct protection_domain *domain)
1264 {
1265 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1266 }
1267
1268 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1269 static void domain_flush_tlb_pde(struct protection_domain *domain)
1270 {
1271 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1272 }
1273
1274 static void domain_flush_complete(struct protection_domain *domain)
1275 {
1276 int i;
1277
1278 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1279 if (domain && !domain->dev_iommu[i])
1280 continue;
1281
1282 /*
1283 * Devices of this domain are behind this IOMMU
1284 * We need to wait for completion of all commands.
1285 */
1286 iommu_completion_wait(amd_iommus[i]);
1287 }
1288 }
1289
1290
1291 /*
1292 * This function flushes the DTEs for all devices in domain
1293 */
1294 static void domain_flush_devices(struct protection_domain *domain)
1295 {
1296 struct iommu_dev_data *dev_data;
1297
1298 list_for_each_entry(dev_data, &domain->dev_list, list)
1299 device_flush_dte(dev_data);
1300 }
1301
1302 /****************************************************************************
1303 *
1304 * The functions below are used the create the page table mappings for
1305 * unity mapped regions.
1306 *
1307 ****************************************************************************/
1308
1309 /*
1310 * This function is used to add another level to an IO page table. Adding
1311 * another level increases the size of the address space by 9 bits to a size up
1312 * to 64 bits.
1313 */
1314 static bool increase_address_space(struct protection_domain *domain,
1315 gfp_t gfp)
1316 {
1317 u64 *pte;
1318
1319 if (domain->mode == PAGE_MODE_6_LEVEL)
1320 /* address space already 64 bit large */
1321 return false;
1322
1323 pte = (void *)get_zeroed_page(gfp);
1324 if (!pte)
1325 return false;
1326
1327 *pte = PM_LEVEL_PDE(domain->mode,
1328 iommu_virt_to_phys(domain->pt_root));
1329 domain->pt_root = pte;
1330 domain->mode += 1;
1331 domain->updated = true;
1332
1333 return true;
1334 }
1335
1336 static u64 *alloc_pte(struct protection_domain *domain,
1337 unsigned long address,
1338 unsigned long page_size,
1339 u64 **pte_page,
1340 gfp_t gfp)
1341 {
1342 int level, end_lvl;
1343 u64 *pte, *page;
1344
1345 BUG_ON(!is_power_of_2(page_size));
1346
1347 while (address > PM_LEVEL_SIZE(domain->mode))
1348 increase_address_space(domain, gfp);
1349
1350 level = domain->mode - 1;
1351 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1352 address = PAGE_SIZE_ALIGN(address, page_size);
1353 end_lvl = PAGE_SIZE_LEVEL(page_size);
1354
1355 while (level > end_lvl) {
1356 u64 __pte, __npte;
1357
1358 __pte = *pte;
1359
1360 if (!IOMMU_PTE_PRESENT(__pte)) {
1361 page = (u64 *)get_zeroed_page(gfp);
1362 if (!page)
1363 return NULL;
1364
1365 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1366
1367 /* pte could have been changed somewhere. */
1368 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1369 free_page((unsigned long)page);
1370 continue;
1371 }
1372 }
1373
1374 /* No level skipping support yet */
1375 if (PM_PTE_LEVEL(*pte) != level)
1376 return NULL;
1377
1378 level -= 1;
1379
1380 pte = IOMMU_PTE_PAGE(*pte);
1381
1382 if (pte_page && level == end_lvl)
1383 *pte_page = pte;
1384
1385 pte = &pte[PM_LEVEL_INDEX(level, address)];
1386 }
1387
1388 return pte;
1389 }
1390
1391 /*
1392 * This function checks if there is a PTE for a given dma address. If
1393 * there is one, it returns the pointer to it.
1394 */
1395 static u64 *fetch_pte(struct protection_domain *domain,
1396 unsigned long address,
1397 unsigned long *page_size)
1398 {
1399 int level;
1400 u64 *pte;
1401
1402 if (address > PM_LEVEL_SIZE(domain->mode))
1403 return NULL;
1404
1405 level = domain->mode - 1;
1406 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1407 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1408
1409 while (level > 0) {
1410
1411 /* Not Present */
1412 if (!IOMMU_PTE_PRESENT(*pte))
1413 return NULL;
1414
1415 /* Large PTE */
1416 if (PM_PTE_LEVEL(*pte) == 7 ||
1417 PM_PTE_LEVEL(*pte) == 0)
1418 break;
1419
1420 /* No level skipping support yet */
1421 if (PM_PTE_LEVEL(*pte) != level)
1422 return NULL;
1423
1424 level -= 1;
1425
1426 /* Walk to the next level */
1427 pte = IOMMU_PTE_PAGE(*pte);
1428 pte = &pte[PM_LEVEL_INDEX(level, address)];
1429 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1430 }
1431
1432 if (PM_PTE_LEVEL(*pte) == 0x07) {
1433 unsigned long pte_mask;
1434
1435 /*
1436 * If we have a series of large PTEs, make
1437 * sure to return a pointer to the first one.
1438 */
1439 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1440 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1441 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1442 }
1443
1444 return pte;
1445 }
1446
1447 /*
1448 * Generic mapping functions. It maps a physical address into a DMA
1449 * address space. It allocates the page table pages if necessary.
1450 * In the future it can be extended to a generic mapping function
1451 * supporting all features of AMD IOMMU page tables like level skipping
1452 * and full 64 bit address spaces.
1453 */
1454 static int iommu_map_page(struct protection_domain *dom,
1455 unsigned long bus_addr,
1456 unsigned long phys_addr,
1457 unsigned long page_size,
1458 int prot,
1459 gfp_t gfp)
1460 {
1461 u64 __pte, *pte;
1462 int i, count;
1463
1464 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1465 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1466
1467 if (!(prot & IOMMU_PROT_MASK))
1468 return -EINVAL;
1469
1470 count = PAGE_SIZE_PTE_COUNT(page_size);
1471 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1472
1473 if (!pte)
1474 return -ENOMEM;
1475
1476 for (i = 0; i < count; ++i)
1477 if (IOMMU_PTE_PRESENT(pte[i]))
1478 return -EBUSY;
1479
1480 if (count > 1) {
1481 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1482 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1483 } else
1484 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1485
1486 if (prot & IOMMU_PROT_IR)
1487 __pte |= IOMMU_PTE_IR;
1488 if (prot & IOMMU_PROT_IW)
1489 __pte |= IOMMU_PTE_IW;
1490
1491 for (i = 0; i < count; ++i)
1492 pte[i] = __pte;
1493
1494 update_domain(dom);
1495
1496 return 0;
1497 }
1498
1499 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1500 unsigned long bus_addr,
1501 unsigned long page_size)
1502 {
1503 unsigned long long unmapped;
1504 unsigned long unmap_size;
1505 u64 *pte;
1506
1507 BUG_ON(!is_power_of_2(page_size));
1508
1509 unmapped = 0;
1510
1511 while (unmapped < page_size) {
1512
1513 pte = fetch_pte(dom, bus_addr, &unmap_size);
1514
1515 if (pte) {
1516 int i, count;
1517
1518 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1519 for (i = 0; i < count; i++)
1520 pte[i] = 0ULL;
1521 }
1522
1523 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1524 unmapped += unmap_size;
1525 }
1526
1527 BUG_ON(unmapped && !is_power_of_2(unmapped));
1528
1529 return unmapped;
1530 }
1531
1532 /****************************************************************************
1533 *
1534 * The next functions belong to the address allocator for the dma_ops
1535 * interface functions.
1536 *
1537 ****************************************************************************/
1538
1539
1540 static unsigned long dma_ops_alloc_iova(struct device *dev,
1541 struct dma_ops_domain *dma_dom,
1542 unsigned int pages, u64 dma_mask)
1543 {
1544 unsigned long pfn = 0;
1545
1546 pages = __roundup_pow_of_two(pages);
1547
1548 if (dma_mask > DMA_BIT_MASK(32))
1549 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1550 IOVA_PFN(DMA_BIT_MASK(32)));
1551
1552 if (!pfn)
1553 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1554
1555 return (pfn << PAGE_SHIFT);
1556 }
1557
1558 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1559 unsigned long address,
1560 unsigned int pages)
1561 {
1562 pages = __roundup_pow_of_two(pages);
1563 address >>= PAGE_SHIFT;
1564
1565 free_iova_fast(&dma_dom->iovad, address, pages);
1566 }
1567
1568 /****************************************************************************
1569 *
1570 * The next functions belong to the domain allocation. A domain is
1571 * allocated for every IOMMU as the default domain. If device isolation
1572 * is enabled, every device get its own domain. The most important thing
1573 * about domains is the page table mapping the DMA address space they
1574 * contain.
1575 *
1576 ****************************************************************************/
1577
1578 /*
1579 * This function adds a protection domain to the global protection domain list
1580 */
1581 static void add_domain_to_list(struct protection_domain *domain)
1582 {
1583 unsigned long flags;
1584
1585 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1586 list_add(&domain->list, &amd_iommu_pd_list);
1587 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1588 }
1589
1590 /*
1591 * This function removes a protection domain to the global
1592 * protection domain list
1593 */
1594 static void del_domain_from_list(struct protection_domain *domain)
1595 {
1596 unsigned long flags;
1597
1598 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1599 list_del(&domain->list);
1600 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1601 }
1602
1603 static u16 domain_id_alloc(void)
1604 {
1605 unsigned long flags;
1606 int id;
1607
1608 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1609 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1610 BUG_ON(id == 0);
1611 if (id > 0 && id < MAX_DOMAIN_ID)
1612 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1613 else
1614 id = 0;
1615 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1616
1617 return id;
1618 }
1619
1620 static void domain_id_free(int id)
1621 {
1622 unsigned long flags;
1623
1624 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1625 if (id > 0 && id < MAX_DOMAIN_ID)
1626 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1627 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1628 }
1629
1630 #define DEFINE_FREE_PT_FN(LVL, FN) \
1631 static void free_pt_##LVL (unsigned long __pt) \
1632 { \
1633 unsigned long p; \
1634 u64 *pt; \
1635 int i; \
1636 \
1637 pt = (u64 *)__pt; \
1638 \
1639 for (i = 0; i < 512; ++i) { \
1640 /* PTE present? */ \
1641 if (!IOMMU_PTE_PRESENT(pt[i])) \
1642 continue; \
1643 \
1644 /* Large PTE? */ \
1645 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1646 PM_PTE_LEVEL(pt[i]) == 7) \
1647 continue; \
1648 \
1649 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1650 FN(p); \
1651 } \
1652 free_page((unsigned long)pt); \
1653 }
1654
1655 DEFINE_FREE_PT_FN(l2, free_page)
1656 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1657 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1658 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1659 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1660
1661 static void free_pagetable(struct protection_domain *domain)
1662 {
1663 unsigned long root = (unsigned long)domain->pt_root;
1664
1665 switch (domain->mode) {
1666 case PAGE_MODE_NONE:
1667 break;
1668 case PAGE_MODE_1_LEVEL:
1669 free_page(root);
1670 break;
1671 case PAGE_MODE_2_LEVEL:
1672 free_pt_l2(root);
1673 break;
1674 case PAGE_MODE_3_LEVEL:
1675 free_pt_l3(root);
1676 break;
1677 case PAGE_MODE_4_LEVEL:
1678 free_pt_l4(root);
1679 break;
1680 case PAGE_MODE_5_LEVEL:
1681 free_pt_l5(root);
1682 break;
1683 case PAGE_MODE_6_LEVEL:
1684 free_pt_l6(root);
1685 break;
1686 default:
1687 BUG();
1688 }
1689 }
1690
1691 static void free_gcr3_tbl_level1(u64 *tbl)
1692 {
1693 u64 *ptr;
1694 int i;
1695
1696 for (i = 0; i < 512; ++i) {
1697 if (!(tbl[i] & GCR3_VALID))
1698 continue;
1699
1700 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1701
1702 free_page((unsigned long)ptr);
1703 }
1704 }
1705
1706 static void free_gcr3_tbl_level2(u64 *tbl)
1707 {
1708 u64 *ptr;
1709 int i;
1710
1711 for (i = 0; i < 512; ++i) {
1712 if (!(tbl[i] & GCR3_VALID))
1713 continue;
1714
1715 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1716
1717 free_gcr3_tbl_level1(ptr);
1718 }
1719 }
1720
1721 static void free_gcr3_table(struct protection_domain *domain)
1722 {
1723 if (domain->glx == 2)
1724 free_gcr3_tbl_level2(domain->gcr3_tbl);
1725 else if (domain->glx == 1)
1726 free_gcr3_tbl_level1(domain->gcr3_tbl);
1727 else
1728 BUG_ON(domain->glx != 0);
1729
1730 free_page((unsigned long)domain->gcr3_tbl);
1731 }
1732
1733 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1734 {
1735 domain_flush_tlb(&dom->domain);
1736 domain_flush_complete(&dom->domain);
1737 }
1738
1739 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1740 {
1741 struct dma_ops_domain *dom;
1742
1743 dom = container_of(iovad, struct dma_ops_domain, iovad);
1744
1745 dma_ops_domain_flush_tlb(dom);
1746 }
1747
1748 /*
1749 * Free a domain, only used if something went wrong in the
1750 * allocation path and we need to free an already allocated page table
1751 */
1752 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1753 {
1754 if (!dom)
1755 return;
1756
1757 del_domain_from_list(&dom->domain);
1758
1759 put_iova_domain(&dom->iovad);
1760
1761 free_pagetable(&dom->domain);
1762
1763 if (dom->domain.id)
1764 domain_id_free(dom->domain.id);
1765
1766 kfree(dom);
1767 }
1768
1769 /*
1770 * Allocates a new protection domain usable for the dma_ops functions.
1771 * It also initializes the page table and the address allocator data
1772 * structures required for the dma_ops interface
1773 */
1774 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1775 {
1776 struct dma_ops_domain *dma_dom;
1777
1778 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1779 if (!dma_dom)
1780 return NULL;
1781
1782 if (protection_domain_init(&dma_dom->domain))
1783 goto free_dma_dom;
1784
1785 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1786 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1787 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1788 if (!dma_dom->domain.pt_root)
1789 goto free_dma_dom;
1790
1791 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1792 IOVA_START_PFN, DMA_32BIT_PFN);
1793
1794 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1795 goto free_dma_dom;
1796
1797 /* Initialize reserved ranges */
1798 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1799
1800 add_domain_to_list(&dma_dom->domain);
1801
1802 return dma_dom;
1803
1804 free_dma_dom:
1805 dma_ops_domain_free(dma_dom);
1806
1807 return NULL;
1808 }
1809
1810 /*
1811 * little helper function to check whether a given protection domain is a
1812 * dma_ops domain
1813 */
1814 static bool dma_ops_domain(struct protection_domain *domain)
1815 {
1816 return domain->flags & PD_DMA_OPS_MASK;
1817 }
1818
1819 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1820 {
1821 u64 pte_root = 0;
1822 u64 flags = 0;
1823
1824 if (domain->mode != PAGE_MODE_NONE)
1825 pte_root = iommu_virt_to_phys(domain->pt_root);
1826
1827 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1828 << DEV_ENTRY_MODE_SHIFT;
1829 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1830
1831 flags = amd_iommu_dev_table[devid].data[1];
1832
1833 if (ats)
1834 flags |= DTE_FLAG_IOTLB;
1835
1836 if (domain->flags & PD_IOMMUV2_MASK) {
1837 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1838 u64 glx = domain->glx;
1839 u64 tmp;
1840
1841 pte_root |= DTE_FLAG_GV;
1842 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1843
1844 /* First mask out possible old values for GCR3 table */
1845 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1846 flags &= ~tmp;
1847
1848 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1849 flags &= ~tmp;
1850
1851 /* Encode GCR3 table into DTE */
1852 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1853 pte_root |= tmp;
1854
1855 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1856 flags |= tmp;
1857
1858 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1859 flags |= tmp;
1860 }
1861
1862 flags &= ~DEV_DOMID_MASK;
1863 flags |= domain->id;
1864
1865 amd_iommu_dev_table[devid].data[1] = flags;
1866 amd_iommu_dev_table[devid].data[0] = pte_root;
1867 }
1868
1869 static void clear_dte_entry(u16 devid)
1870 {
1871 /* remove entry from the device table seen by the hardware */
1872 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1873 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1874
1875 amd_iommu_apply_erratum_63(devid);
1876 }
1877
1878 static void do_attach(struct iommu_dev_data *dev_data,
1879 struct protection_domain *domain)
1880 {
1881 struct amd_iommu *iommu;
1882 u16 alias;
1883 bool ats;
1884
1885 iommu = amd_iommu_rlookup_table[dev_data->devid];
1886 alias = dev_data->alias;
1887 ats = dev_data->ats.enabled;
1888
1889 /* Update data structures */
1890 dev_data->domain = domain;
1891 list_add(&dev_data->list, &domain->dev_list);
1892
1893 /* Do reference counting */
1894 domain->dev_iommu[iommu->index] += 1;
1895 domain->dev_cnt += 1;
1896
1897 /* Update device table */
1898 set_dte_entry(dev_data->devid, domain, ats);
1899 if (alias != dev_data->devid)
1900 set_dte_entry(alias, domain, ats);
1901
1902 device_flush_dte(dev_data);
1903 }
1904
1905 static void do_detach(struct iommu_dev_data *dev_data)
1906 {
1907 struct amd_iommu *iommu;
1908 u16 alias;
1909
1910 /*
1911 * First check if the device is still attached. It might already
1912 * be detached from its domain because the generic
1913 * iommu_detach_group code detached it and we try again here in
1914 * our alias handling.
1915 */
1916 if (!dev_data->domain)
1917 return;
1918
1919 iommu = amd_iommu_rlookup_table[dev_data->devid];
1920 alias = dev_data->alias;
1921
1922 /* decrease reference counters */
1923 dev_data->domain->dev_iommu[iommu->index] -= 1;
1924 dev_data->domain->dev_cnt -= 1;
1925
1926 /* Update data structures */
1927 dev_data->domain = NULL;
1928 list_del(&dev_data->list);
1929 clear_dte_entry(dev_data->devid);
1930 if (alias != dev_data->devid)
1931 clear_dte_entry(alias);
1932
1933 /* Flush the DTE entry */
1934 device_flush_dte(dev_data);
1935 }
1936
1937 /*
1938 * If a device is not yet associated with a domain, this function does
1939 * assigns it visible for the hardware
1940 */
1941 static int __attach_device(struct iommu_dev_data *dev_data,
1942 struct protection_domain *domain)
1943 {
1944 int ret;
1945
1946 /*
1947 * Must be called with IRQs disabled. Warn here to detect early
1948 * when its not.
1949 */
1950 WARN_ON(!irqs_disabled());
1951
1952 /* lock domain */
1953 spin_lock(&domain->lock);
1954
1955 ret = -EBUSY;
1956 if (dev_data->domain != NULL)
1957 goto out_unlock;
1958
1959 /* Attach alias group root */
1960 do_attach(dev_data, domain);
1961
1962 ret = 0;
1963
1964 out_unlock:
1965
1966 /* ready */
1967 spin_unlock(&domain->lock);
1968
1969 return ret;
1970 }
1971
1972
1973 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1974 {
1975 pci_disable_ats(pdev);
1976 pci_disable_pri(pdev);
1977 pci_disable_pasid(pdev);
1978 }
1979
1980 /* FIXME: Change generic reset-function to do the same */
1981 static int pri_reset_while_enabled(struct pci_dev *pdev)
1982 {
1983 u16 control;
1984 int pos;
1985
1986 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1987 if (!pos)
1988 return -EINVAL;
1989
1990 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1991 control |= PCI_PRI_CTRL_RESET;
1992 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1993
1994 return 0;
1995 }
1996
1997 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1998 {
1999 bool reset_enable;
2000 int reqs, ret;
2001
2002 /* FIXME: Hardcode number of outstanding requests for now */
2003 reqs = 32;
2004 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2005 reqs = 1;
2006 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2007
2008 /* Only allow access to user-accessible pages */
2009 ret = pci_enable_pasid(pdev, 0);
2010 if (ret)
2011 goto out_err;
2012
2013 /* First reset the PRI state of the device */
2014 ret = pci_reset_pri(pdev);
2015 if (ret)
2016 goto out_err;
2017
2018 /* Enable PRI */
2019 ret = pci_enable_pri(pdev, reqs);
2020 if (ret)
2021 goto out_err;
2022
2023 if (reset_enable) {
2024 ret = pri_reset_while_enabled(pdev);
2025 if (ret)
2026 goto out_err;
2027 }
2028
2029 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2030 if (ret)
2031 goto out_err;
2032
2033 return 0;
2034
2035 out_err:
2036 pci_disable_pri(pdev);
2037 pci_disable_pasid(pdev);
2038
2039 return ret;
2040 }
2041
2042 /* FIXME: Move this to PCI code */
2043 #define PCI_PRI_TLP_OFF (1 << 15)
2044
2045 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2046 {
2047 u16 status;
2048 int pos;
2049
2050 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2051 if (!pos)
2052 return false;
2053
2054 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2055
2056 return (status & PCI_PRI_TLP_OFF) ? true : false;
2057 }
2058
2059 /*
2060 * If a device is not yet associated with a domain, this function
2061 * assigns it visible for the hardware
2062 */
2063 static int attach_device(struct device *dev,
2064 struct protection_domain *domain)
2065 {
2066 struct pci_dev *pdev;
2067 struct iommu_dev_data *dev_data;
2068 unsigned long flags;
2069 int ret;
2070
2071 dev_data = get_dev_data(dev);
2072
2073 if (!dev_is_pci(dev))
2074 goto skip_ats_check;
2075
2076 pdev = to_pci_dev(dev);
2077 if (domain->flags & PD_IOMMUV2_MASK) {
2078 if (!dev_data->passthrough)
2079 return -EINVAL;
2080
2081 if (dev_data->iommu_v2) {
2082 if (pdev_iommuv2_enable(pdev) != 0)
2083 return -EINVAL;
2084
2085 dev_data->ats.enabled = true;
2086 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2087 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2088 }
2089 } else if (amd_iommu_iotlb_sup &&
2090 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2091 dev_data->ats.enabled = true;
2092 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2093 }
2094
2095 skip_ats_check:
2096 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2097 ret = __attach_device(dev_data, domain);
2098 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2099
2100 /*
2101 * We might boot into a crash-kernel here. The crashed kernel
2102 * left the caches in the IOMMU dirty. So we have to flush
2103 * here to evict all dirty stuff.
2104 */
2105 domain_flush_tlb_pde(domain);
2106
2107 return ret;
2108 }
2109
2110 /*
2111 * Removes a device from a protection domain (unlocked)
2112 */
2113 static void __detach_device(struct iommu_dev_data *dev_data)
2114 {
2115 struct protection_domain *domain;
2116
2117 /*
2118 * Must be called with IRQs disabled. Warn here to detect early
2119 * when its not.
2120 */
2121 WARN_ON(!irqs_disabled());
2122
2123 if (WARN_ON(!dev_data->domain))
2124 return;
2125
2126 domain = dev_data->domain;
2127
2128 spin_lock(&domain->lock);
2129
2130 do_detach(dev_data);
2131
2132 spin_unlock(&domain->lock);
2133 }
2134
2135 /*
2136 * Removes a device from a protection domain (with devtable_lock held)
2137 */
2138 static void detach_device(struct device *dev)
2139 {
2140 struct protection_domain *domain;
2141 struct iommu_dev_data *dev_data;
2142 unsigned long flags;
2143
2144 dev_data = get_dev_data(dev);
2145 domain = dev_data->domain;
2146
2147 /* lock device table */
2148 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2149 __detach_device(dev_data);
2150 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2151
2152 if (!dev_is_pci(dev))
2153 return;
2154
2155 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2156 pdev_iommuv2_disable(to_pci_dev(dev));
2157 else if (dev_data->ats.enabled)
2158 pci_disable_ats(to_pci_dev(dev));
2159
2160 dev_data->ats.enabled = false;
2161 }
2162
2163 static int amd_iommu_add_device(struct device *dev)
2164 {
2165 struct iommu_dev_data *dev_data;
2166 struct iommu_domain *domain;
2167 struct amd_iommu *iommu;
2168 int ret, devid;
2169
2170 if (!check_device(dev) || get_dev_data(dev))
2171 return 0;
2172
2173 devid = get_device_id(dev);
2174 if (devid < 0)
2175 return devid;
2176
2177 iommu = amd_iommu_rlookup_table[devid];
2178
2179 ret = iommu_init_device(dev);
2180 if (ret) {
2181 if (ret != -ENOTSUPP)
2182 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2183 dev_name(dev));
2184
2185 iommu_ignore_device(dev);
2186 dev->dma_ops = &nommu_dma_ops;
2187 goto out;
2188 }
2189 init_iommu_group(dev);
2190
2191 dev_data = get_dev_data(dev);
2192
2193 BUG_ON(!dev_data);
2194
2195 if (iommu_pass_through || dev_data->iommu_v2)
2196 iommu_request_dm_for_dev(dev);
2197
2198 /* Domains are initialized for this device - have a look what we ended up with */
2199 domain = iommu_get_domain_for_dev(dev);
2200 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2201 dev_data->passthrough = true;
2202 else
2203 dev->dma_ops = &amd_iommu_dma_ops;
2204
2205 out:
2206 iommu_completion_wait(iommu);
2207
2208 return 0;
2209 }
2210
2211 static void amd_iommu_remove_device(struct device *dev)
2212 {
2213 struct amd_iommu *iommu;
2214 int devid;
2215
2216 if (!check_device(dev))
2217 return;
2218
2219 devid = get_device_id(dev);
2220 if (devid < 0)
2221 return;
2222
2223 iommu = amd_iommu_rlookup_table[devid];
2224
2225 iommu_uninit_device(dev);
2226 iommu_completion_wait(iommu);
2227 }
2228
2229 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2230 {
2231 if (dev_is_pci(dev))
2232 return pci_device_group(dev);
2233
2234 return acpihid_device_group(dev);
2235 }
2236
2237 /*****************************************************************************
2238 *
2239 * The next functions belong to the dma_ops mapping/unmapping code.
2240 *
2241 *****************************************************************************/
2242
2243 /*
2244 * In the dma_ops path we only have the struct device. This function
2245 * finds the corresponding IOMMU, the protection domain and the
2246 * requestor id for a given device.
2247 * If the device is not yet associated with a domain this is also done
2248 * in this function.
2249 */
2250 static struct protection_domain *get_domain(struct device *dev)
2251 {
2252 struct protection_domain *domain;
2253 struct iommu_domain *io_domain;
2254
2255 if (!check_device(dev))
2256 return ERR_PTR(-EINVAL);
2257
2258 domain = get_dev_data(dev)->domain;
2259 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2260 get_dev_data(dev)->defer_attach = false;
2261 io_domain = iommu_get_domain_for_dev(dev);
2262 domain = to_pdomain(io_domain);
2263 attach_device(dev, domain);
2264 }
2265 if (domain == NULL)
2266 return ERR_PTR(-EBUSY);
2267
2268 if (!dma_ops_domain(domain))
2269 return ERR_PTR(-EBUSY);
2270
2271 return domain;
2272 }
2273
2274 static void update_device_table(struct protection_domain *domain)
2275 {
2276 struct iommu_dev_data *dev_data;
2277
2278 list_for_each_entry(dev_data, &domain->dev_list, list) {
2279 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2280
2281 if (dev_data->devid == dev_data->alias)
2282 continue;
2283
2284 /* There is an alias, update device table entry for it */
2285 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2286 }
2287 }
2288
2289 static void update_domain(struct protection_domain *domain)
2290 {
2291 if (!domain->updated)
2292 return;
2293
2294 update_device_table(domain);
2295
2296 domain_flush_devices(domain);
2297 domain_flush_tlb_pde(domain);
2298
2299 domain->updated = false;
2300 }
2301
2302 static int dir2prot(enum dma_data_direction direction)
2303 {
2304 if (direction == DMA_TO_DEVICE)
2305 return IOMMU_PROT_IR;
2306 else if (direction == DMA_FROM_DEVICE)
2307 return IOMMU_PROT_IW;
2308 else if (direction == DMA_BIDIRECTIONAL)
2309 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2310 else
2311 return 0;
2312 }
2313
2314 /*
2315 * This function contains common code for mapping of a physically
2316 * contiguous memory region into DMA address space. It is used by all
2317 * mapping functions provided with this IOMMU driver.
2318 * Must be called with the domain lock held.
2319 */
2320 static dma_addr_t __map_single(struct device *dev,
2321 struct dma_ops_domain *dma_dom,
2322 phys_addr_t paddr,
2323 size_t size,
2324 enum dma_data_direction direction,
2325 u64 dma_mask)
2326 {
2327 dma_addr_t offset = paddr & ~PAGE_MASK;
2328 dma_addr_t address, start, ret;
2329 unsigned int pages;
2330 int prot = 0;
2331 int i;
2332
2333 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2334 paddr &= PAGE_MASK;
2335
2336 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2337 if (address == AMD_IOMMU_MAPPING_ERROR)
2338 goto out;
2339
2340 prot = dir2prot(direction);
2341
2342 start = address;
2343 for (i = 0; i < pages; ++i) {
2344 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2345 PAGE_SIZE, prot, GFP_ATOMIC);
2346 if (ret)
2347 goto out_unmap;
2348
2349 paddr += PAGE_SIZE;
2350 start += PAGE_SIZE;
2351 }
2352 address += offset;
2353
2354 if (unlikely(amd_iommu_np_cache)) {
2355 domain_flush_pages(&dma_dom->domain, address, size);
2356 domain_flush_complete(&dma_dom->domain);
2357 }
2358
2359 out:
2360 return address;
2361
2362 out_unmap:
2363
2364 for (--i; i >= 0; --i) {
2365 start -= PAGE_SIZE;
2366 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2367 }
2368
2369 domain_flush_tlb(&dma_dom->domain);
2370 domain_flush_complete(&dma_dom->domain);
2371
2372 dma_ops_free_iova(dma_dom, address, pages);
2373
2374 return AMD_IOMMU_MAPPING_ERROR;
2375 }
2376
2377 /*
2378 * Does the reverse of the __map_single function. Must be called with
2379 * the domain lock held too
2380 */
2381 static void __unmap_single(struct dma_ops_domain *dma_dom,
2382 dma_addr_t dma_addr,
2383 size_t size,
2384 int dir)
2385 {
2386 dma_addr_t flush_addr;
2387 dma_addr_t i, start;
2388 unsigned int pages;
2389
2390 flush_addr = dma_addr;
2391 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2392 dma_addr &= PAGE_MASK;
2393 start = dma_addr;
2394
2395 for (i = 0; i < pages; ++i) {
2396 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2397 start += PAGE_SIZE;
2398 }
2399
2400 if (amd_iommu_unmap_flush) {
2401 dma_ops_free_iova(dma_dom, dma_addr, pages);
2402 domain_flush_tlb(&dma_dom->domain);
2403 domain_flush_complete(&dma_dom->domain);
2404 } else {
2405 pages = __roundup_pow_of_two(pages);
2406 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2407 }
2408 }
2409
2410 /*
2411 * The exported map_single function for dma_ops.
2412 */
2413 static dma_addr_t map_page(struct device *dev, struct page *page,
2414 unsigned long offset, size_t size,
2415 enum dma_data_direction dir,
2416 unsigned long attrs)
2417 {
2418 phys_addr_t paddr = page_to_phys(page) + offset;
2419 struct protection_domain *domain;
2420 struct dma_ops_domain *dma_dom;
2421 u64 dma_mask;
2422
2423 domain = get_domain(dev);
2424 if (PTR_ERR(domain) == -EINVAL)
2425 return (dma_addr_t)paddr;
2426 else if (IS_ERR(domain))
2427 return AMD_IOMMU_MAPPING_ERROR;
2428
2429 dma_mask = *dev->dma_mask;
2430 dma_dom = to_dma_ops_domain(domain);
2431
2432 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2433 }
2434
2435 /*
2436 * The exported unmap_single function for dma_ops.
2437 */
2438 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2439 enum dma_data_direction dir, unsigned long attrs)
2440 {
2441 struct protection_domain *domain;
2442 struct dma_ops_domain *dma_dom;
2443
2444 domain = get_domain(dev);
2445 if (IS_ERR(domain))
2446 return;
2447
2448 dma_dom = to_dma_ops_domain(domain);
2449
2450 __unmap_single(dma_dom, dma_addr, size, dir);
2451 }
2452
2453 static int sg_num_pages(struct device *dev,
2454 struct scatterlist *sglist,
2455 int nelems)
2456 {
2457 unsigned long mask, boundary_size;
2458 struct scatterlist *s;
2459 int i, npages = 0;
2460
2461 mask = dma_get_seg_boundary(dev);
2462 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2463 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2464
2465 for_each_sg(sglist, s, nelems, i) {
2466 int p, n;
2467
2468 s->dma_address = npages << PAGE_SHIFT;
2469 p = npages % boundary_size;
2470 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2471 if (p + n > boundary_size)
2472 npages += boundary_size - p;
2473 npages += n;
2474 }
2475
2476 return npages;
2477 }
2478
2479 /*
2480 * The exported map_sg function for dma_ops (handles scatter-gather
2481 * lists).
2482 */
2483 static int map_sg(struct device *dev, struct scatterlist *sglist,
2484 int nelems, enum dma_data_direction direction,
2485 unsigned long attrs)
2486 {
2487 int mapped_pages = 0, npages = 0, prot = 0, i;
2488 struct protection_domain *domain;
2489 struct dma_ops_domain *dma_dom;
2490 struct scatterlist *s;
2491 unsigned long address;
2492 u64 dma_mask;
2493
2494 domain = get_domain(dev);
2495 if (IS_ERR(domain))
2496 return 0;
2497
2498 dma_dom = to_dma_ops_domain(domain);
2499 dma_mask = *dev->dma_mask;
2500
2501 npages = sg_num_pages(dev, sglist, nelems);
2502
2503 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2504 if (address == AMD_IOMMU_MAPPING_ERROR)
2505 goto out_err;
2506
2507 prot = dir2prot(direction);
2508
2509 /* Map all sg entries */
2510 for_each_sg(sglist, s, nelems, i) {
2511 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2512
2513 for (j = 0; j < pages; ++j) {
2514 unsigned long bus_addr, phys_addr;
2515 int ret;
2516
2517 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2518 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2519 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2520 if (ret)
2521 goto out_unmap;
2522
2523 mapped_pages += 1;
2524 }
2525 }
2526
2527 /* Everything is mapped - write the right values into s->dma_address */
2528 for_each_sg(sglist, s, nelems, i) {
2529 s->dma_address += address + s->offset;
2530 s->dma_length = s->length;
2531 }
2532
2533 return nelems;
2534
2535 out_unmap:
2536 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2537 dev_name(dev), npages);
2538
2539 for_each_sg(sglist, s, nelems, i) {
2540 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2541
2542 for (j = 0; j < pages; ++j) {
2543 unsigned long bus_addr;
2544
2545 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2546 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2547
2548 if (--mapped_pages)
2549 goto out_free_iova;
2550 }
2551 }
2552
2553 out_free_iova:
2554 free_iova_fast(&dma_dom->iovad, address, npages);
2555
2556 out_err:
2557 return 0;
2558 }
2559
2560 /*
2561 * The exported map_sg function for dma_ops (handles scatter-gather
2562 * lists).
2563 */
2564 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2565 int nelems, enum dma_data_direction dir,
2566 unsigned long attrs)
2567 {
2568 struct protection_domain *domain;
2569 struct dma_ops_domain *dma_dom;
2570 unsigned long startaddr;
2571 int npages = 2;
2572
2573 domain = get_domain(dev);
2574 if (IS_ERR(domain))
2575 return;
2576
2577 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2578 dma_dom = to_dma_ops_domain(domain);
2579 npages = sg_num_pages(dev, sglist, nelems);
2580
2581 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2582 }
2583
2584 /*
2585 * The exported alloc_coherent function for dma_ops.
2586 */
2587 static void *alloc_coherent(struct device *dev, size_t size,
2588 dma_addr_t *dma_addr, gfp_t flag,
2589 unsigned long attrs)
2590 {
2591 u64 dma_mask = dev->coherent_dma_mask;
2592 struct protection_domain *domain;
2593 struct dma_ops_domain *dma_dom;
2594 struct page *page;
2595
2596 domain = get_domain(dev);
2597 if (PTR_ERR(domain) == -EINVAL) {
2598 page = alloc_pages(flag, get_order(size));
2599 *dma_addr = page_to_phys(page);
2600 return page_address(page);
2601 } else if (IS_ERR(domain))
2602 return NULL;
2603
2604 dma_dom = to_dma_ops_domain(domain);
2605 size = PAGE_ALIGN(size);
2606 dma_mask = dev->coherent_dma_mask;
2607 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2608 flag |= __GFP_ZERO;
2609
2610 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2611 if (!page) {
2612 if (!gfpflags_allow_blocking(flag))
2613 return NULL;
2614
2615 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2616 get_order(size), flag);
2617 if (!page)
2618 return NULL;
2619 }
2620
2621 if (!dma_mask)
2622 dma_mask = *dev->dma_mask;
2623
2624 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2625 size, DMA_BIDIRECTIONAL, dma_mask);
2626
2627 if (*dma_addr == AMD_IOMMU_MAPPING_ERROR)
2628 goto out_free;
2629
2630 return page_address(page);
2631
2632 out_free:
2633
2634 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2635 __free_pages(page, get_order(size));
2636
2637 return NULL;
2638 }
2639
2640 /*
2641 * The exported free_coherent function for dma_ops.
2642 */
2643 static void free_coherent(struct device *dev, size_t size,
2644 void *virt_addr, dma_addr_t dma_addr,
2645 unsigned long attrs)
2646 {
2647 struct protection_domain *domain;
2648 struct dma_ops_domain *dma_dom;
2649 struct page *page;
2650
2651 page = virt_to_page(virt_addr);
2652 size = PAGE_ALIGN(size);
2653
2654 domain = get_domain(dev);
2655 if (IS_ERR(domain))
2656 goto free_mem;
2657
2658 dma_dom = to_dma_ops_domain(domain);
2659
2660 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2661
2662 free_mem:
2663 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2664 __free_pages(page, get_order(size));
2665 }
2666
2667 /*
2668 * This function is called by the DMA layer to find out if we can handle a
2669 * particular device. It is part of the dma_ops.
2670 */
2671 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2672 {
2673 if (!x86_dma_supported(dev, mask))
2674 return 0;
2675 return check_device(dev);
2676 }
2677
2678 static int amd_iommu_mapping_error(struct device *dev, dma_addr_t dma_addr)
2679 {
2680 return dma_addr == AMD_IOMMU_MAPPING_ERROR;
2681 }
2682
2683 static const struct dma_map_ops amd_iommu_dma_ops = {
2684 .alloc = alloc_coherent,
2685 .free = free_coherent,
2686 .map_page = map_page,
2687 .unmap_page = unmap_page,
2688 .map_sg = map_sg,
2689 .unmap_sg = unmap_sg,
2690 .dma_supported = amd_iommu_dma_supported,
2691 .mapping_error = amd_iommu_mapping_error,
2692 };
2693
2694 static int init_reserved_iova_ranges(void)
2695 {
2696 struct pci_dev *pdev = NULL;
2697 struct iova *val;
2698
2699 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2700 IOVA_START_PFN, DMA_32BIT_PFN);
2701
2702 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2703 &reserved_rbtree_key);
2704
2705 /* MSI memory range */
2706 val = reserve_iova(&reserved_iova_ranges,
2707 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2708 if (!val) {
2709 pr_err("Reserving MSI range failed\n");
2710 return -ENOMEM;
2711 }
2712
2713 /* HT memory range */
2714 val = reserve_iova(&reserved_iova_ranges,
2715 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2716 if (!val) {
2717 pr_err("Reserving HT range failed\n");
2718 return -ENOMEM;
2719 }
2720
2721 /*
2722 * Memory used for PCI resources
2723 * FIXME: Check whether we can reserve the PCI-hole completly
2724 */
2725 for_each_pci_dev(pdev) {
2726 int i;
2727
2728 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2729 struct resource *r = &pdev->resource[i];
2730
2731 if (!(r->flags & IORESOURCE_MEM))
2732 continue;
2733
2734 val = reserve_iova(&reserved_iova_ranges,
2735 IOVA_PFN(r->start),
2736 IOVA_PFN(r->end));
2737 if (!val) {
2738 pr_err("Reserve pci-resource range failed\n");
2739 return -ENOMEM;
2740 }
2741 }
2742 }
2743
2744 return 0;
2745 }
2746
2747 int __init amd_iommu_init_api(void)
2748 {
2749 int ret, err = 0;
2750
2751 ret = iova_cache_get();
2752 if (ret)
2753 return ret;
2754
2755 ret = init_reserved_iova_ranges();
2756 if (ret)
2757 return ret;
2758
2759 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2760 if (err)
2761 return err;
2762 #ifdef CONFIG_ARM_AMBA
2763 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2764 if (err)
2765 return err;
2766 #endif
2767 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2768 if (err)
2769 return err;
2770
2771 return 0;
2772 }
2773
2774 int __init amd_iommu_init_dma_ops(void)
2775 {
2776 swiotlb = iommu_pass_through ? 1 : 0;
2777 iommu_detected = 1;
2778
2779 /*
2780 * In case we don't initialize SWIOTLB (actually the common case
2781 * when AMD IOMMU is enabled), make sure there are global
2782 * dma_ops set as a fall-back for devices not handled by this
2783 * driver (for example non-PCI devices).
2784 */
2785 if (!swiotlb)
2786 dma_ops = &nommu_dma_ops;
2787
2788 if (amd_iommu_unmap_flush)
2789 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2790 else
2791 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2792
2793 return 0;
2794
2795 }
2796
2797 /*****************************************************************************
2798 *
2799 * The following functions belong to the exported interface of AMD IOMMU
2800 *
2801 * This interface allows access to lower level functions of the IOMMU
2802 * like protection domain handling and assignement of devices to domains
2803 * which is not possible with the dma_ops interface.
2804 *
2805 *****************************************************************************/
2806
2807 static void cleanup_domain(struct protection_domain *domain)
2808 {
2809 struct iommu_dev_data *entry;
2810 unsigned long flags;
2811
2812 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2813
2814 while (!list_empty(&domain->dev_list)) {
2815 entry = list_first_entry(&domain->dev_list,
2816 struct iommu_dev_data, list);
2817 __detach_device(entry);
2818 }
2819
2820 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2821 }
2822
2823 static void protection_domain_free(struct protection_domain *domain)
2824 {
2825 if (!domain)
2826 return;
2827
2828 del_domain_from_list(domain);
2829
2830 if (domain->id)
2831 domain_id_free(domain->id);
2832
2833 kfree(domain);
2834 }
2835
2836 static int protection_domain_init(struct protection_domain *domain)
2837 {
2838 spin_lock_init(&domain->lock);
2839 mutex_init(&domain->api_lock);
2840 domain->id = domain_id_alloc();
2841 if (!domain->id)
2842 return -ENOMEM;
2843 INIT_LIST_HEAD(&domain->dev_list);
2844
2845 return 0;
2846 }
2847
2848 static struct protection_domain *protection_domain_alloc(void)
2849 {
2850 struct protection_domain *domain;
2851
2852 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2853 if (!domain)
2854 return NULL;
2855
2856 if (protection_domain_init(domain))
2857 goto out_err;
2858
2859 add_domain_to_list(domain);
2860
2861 return domain;
2862
2863 out_err:
2864 kfree(domain);
2865
2866 return NULL;
2867 }
2868
2869 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2870 {
2871 struct protection_domain *pdomain;
2872 struct dma_ops_domain *dma_domain;
2873
2874 switch (type) {
2875 case IOMMU_DOMAIN_UNMANAGED:
2876 pdomain = protection_domain_alloc();
2877 if (!pdomain)
2878 return NULL;
2879
2880 pdomain->mode = PAGE_MODE_3_LEVEL;
2881 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2882 if (!pdomain->pt_root) {
2883 protection_domain_free(pdomain);
2884 return NULL;
2885 }
2886
2887 pdomain->domain.geometry.aperture_start = 0;
2888 pdomain->domain.geometry.aperture_end = ~0ULL;
2889 pdomain->domain.geometry.force_aperture = true;
2890
2891 break;
2892 case IOMMU_DOMAIN_DMA:
2893 dma_domain = dma_ops_domain_alloc();
2894 if (!dma_domain) {
2895 pr_err("AMD-Vi: Failed to allocate\n");
2896 return NULL;
2897 }
2898 pdomain = &dma_domain->domain;
2899 break;
2900 case IOMMU_DOMAIN_IDENTITY:
2901 pdomain = protection_domain_alloc();
2902 if (!pdomain)
2903 return NULL;
2904
2905 pdomain->mode = PAGE_MODE_NONE;
2906 break;
2907 default:
2908 return NULL;
2909 }
2910
2911 return &pdomain->domain;
2912 }
2913
2914 static void amd_iommu_domain_free(struct iommu_domain *dom)
2915 {
2916 struct protection_domain *domain;
2917 struct dma_ops_domain *dma_dom;
2918
2919 domain = to_pdomain(dom);
2920
2921 if (domain->dev_cnt > 0)
2922 cleanup_domain(domain);
2923
2924 BUG_ON(domain->dev_cnt != 0);
2925
2926 if (!dom)
2927 return;
2928
2929 switch (dom->type) {
2930 case IOMMU_DOMAIN_DMA:
2931 /* Now release the domain */
2932 dma_dom = to_dma_ops_domain(domain);
2933 dma_ops_domain_free(dma_dom);
2934 break;
2935 default:
2936 if (domain->mode != PAGE_MODE_NONE)
2937 free_pagetable(domain);
2938
2939 if (domain->flags & PD_IOMMUV2_MASK)
2940 free_gcr3_table(domain);
2941
2942 protection_domain_free(domain);
2943 break;
2944 }
2945 }
2946
2947 static void amd_iommu_detach_device(struct iommu_domain *dom,
2948 struct device *dev)
2949 {
2950 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2951 struct amd_iommu *iommu;
2952 int devid;
2953
2954 if (!check_device(dev))
2955 return;
2956
2957 devid = get_device_id(dev);
2958 if (devid < 0)
2959 return;
2960
2961 if (dev_data->domain != NULL)
2962 detach_device(dev);
2963
2964 iommu = amd_iommu_rlookup_table[devid];
2965 if (!iommu)
2966 return;
2967
2968 #ifdef CONFIG_IRQ_REMAP
2969 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2970 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2971 dev_data->use_vapic = 0;
2972 #endif
2973
2974 iommu_completion_wait(iommu);
2975 }
2976
2977 static int amd_iommu_attach_device(struct iommu_domain *dom,
2978 struct device *dev)
2979 {
2980 struct protection_domain *domain = to_pdomain(dom);
2981 struct iommu_dev_data *dev_data;
2982 struct amd_iommu *iommu;
2983 int ret;
2984
2985 if (!check_device(dev))
2986 return -EINVAL;
2987
2988 dev_data = dev->archdata.iommu;
2989
2990 iommu = amd_iommu_rlookup_table[dev_data->devid];
2991 if (!iommu)
2992 return -EINVAL;
2993
2994 if (dev_data->domain)
2995 detach_device(dev);
2996
2997 ret = attach_device(dev, domain);
2998
2999 #ifdef CONFIG_IRQ_REMAP
3000 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3001 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3002 dev_data->use_vapic = 1;
3003 else
3004 dev_data->use_vapic = 0;
3005 }
3006 #endif
3007
3008 iommu_completion_wait(iommu);
3009
3010 return ret;
3011 }
3012
3013 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3014 phys_addr_t paddr, size_t page_size, int iommu_prot)
3015 {
3016 struct protection_domain *domain = to_pdomain(dom);
3017 int prot = 0;
3018 int ret;
3019
3020 if (domain->mode == PAGE_MODE_NONE)
3021 return -EINVAL;
3022
3023 if (iommu_prot & IOMMU_READ)
3024 prot |= IOMMU_PROT_IR;
3025 if (iommu_prot & IOMMU_WRITE)
3026 prot |= IOMMU_PROT_IW;
3027
3028 mutex_lock(&domain->api_lock);
3029 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3030 mutex_unlock(&domain->api_lock);
3031
3032 return ret;
3033 }
3034
3035 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3036 size_t page_size)
3037 {
3038 struct protection_domain *domain = to_pdomain(dom);
3039 size_t unmap_size;
3040
3041 if (domain->mode == PAGE_MODE_NONE)
3042 return -EINVAL;
3043
3044 mutex_lock(&domain->api_lock);
3045 unmap_size = iommu_unmap_page(domain, iova, page_size);
3046 mutex_unlock(&domain->api_lock);
3047
3048 domain_flush_tlb_pde(domain);
3049
3050 return unmap_size;
3051 }
3052
3053 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3054 dma_addr_t iova)
3055 {
3056 struct protection_domain *domain = to_pdomain(dom);
3057 unsigned long offset_mask, pte_pgsize;
3058 u64 *pte, __pte;
3059
3060 if (domain->mode == PAGE_MODE_NONE)
3061 return iova;
3062
3063 pte = fetch_pte(domain, iova, &pte_pgsize);
3064
3065 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3066 return 0;
3067
3068 offset_mask = pte_pgsize - 1;
3069 __pte = *pte & PM_ADDR_MASK;
3070
3071 return (__pte & ~offset_mask) | (iova & offset_mask);
3072 }
3073
3074 static bool amd_iommu_capable(enum iommu_cap cap)
3075 {
3076 switch (cap) {
3077 case IOMMU_CAP_CACHE_COHERENCY:
3078 return true;
3079 case IOMMU_CAP_INTR_REMAP:
3080 return (irq_remapping_enabled == 1);
3081 case IOMMU_CAP_NOEXEC:
3082 return false;
3083 }
3084
3085 return false;
3086 }
3087
3088 static void amd_iommu_get_resv_regions(struct device *dev,
3089 struct list_head *head)
3090 {
3091 struct iommu_resv_region *region;
3092 struct unity_map_entry *entry;
3093 int devid;
3094
3095 devid = get_device_id(dev);
3096 if (devid < 0)
3097 return;
3098
3099 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3100 size_t length;
3101 int prot = 0;
3102
3103 if (devid < entry->devid_start || devid > entry->devid_end)
3104 continue;
3105
3106 length = entry->address_end - entry->address_start;
3107 if (entry->prot & IOMMU_PROT_IR)
3108 prot |= IOMMU_READ;
3109 if (entry->prot & IOMMU_PROT_IW)
3110 prot |= IOMMU_WRITE;
3111
3112 region = iommu_alloc_resv_region(entry->address_start,
3113 length, prot,
3114 IOMMU_RESV_DIRECT);
3115 if (!region) {
3116 pr_err("Out of memory allocating dm-regions for %s\n",
3117 dev_name(dev));
3118 return;
3119 }
3120 list_add_tail(&region->list, head);
3121 }
3122
3123 region = iommu_alloc_resv_region(MSI_RANGE_START,
3124 MSI_RANGE_END - MSI_RANGE_START + 1,
3125 0, IOMMU_RESV_MSI);
3126 if (!region)
3127 return;
3128 list_add_tail(&region->list, head);
3129
3130 region = iommu_alloc_resv_region(HT_RANGE_START,
3131 HT_RANGE_END - HT_RANGE_START + 1,
3132 0, IOMMU_RESV_RESERVED);
3133 if (!region)
3134 return;
3135 list_add_tail(&region->list, head);
3136 }
3137
3138 static void amd_iommu_put_resv_regions(struct device *dev,
3139 struct list_head *head)
3140 {
3141 struct iommu_resv_region *entry, *next;
3142
3143 list_for_each_entry_safe(entry, next, head, list)
3144 kfree(entry);
3145 }
3146
3147 static void amd_iommu_apply_resv_region(struct device *dev,
3148 struct iommu_domain *domain,
3149 struct iommu_resv_region *region)
3150 {
3151 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3152 unsigned long start, end;
3153
3154 start = IOVA_PFN(region->start);
3155 end = IOVA_PFN(region->start + region->length);
3156
3157 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3158 }
3159
3160 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3161 struct device *dev)
3162 {
3163 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3164 return dev_data->defer_attach;
3165 }
3166
3167 const struct iommu_ops amd_iommu_ops = {
3168 .capable = amd_iommu_capable,
3169 .domain_alloc = amd_iommu_domain_alloc,
3170 .domain_free = amd_iommu_domain_free,
3171 .attach_dev = amd_iommu_attach_device,
3172 .detach_dev = amd_iommu_detach_device,
3173 .map = amd_iommu_map,
3174 .unmap = amd_iommu_unmap,
3175 .map_sg = default_iommu_map_sg,
3176 .iova_to_phys = amd_iommu_iova_to_phys,
3177 .add_device = amd_iommu_add_device,
3178 .remove_device = amd_iommu_remove_device,
3179 .device_group = amd_iommu_device_group,
3180 .get_resv_regions = amd_iommu_get_resv_regions,
3181 .put_resv_regions = amd_iommu_put_resv_regions,
3182 .apply_resv_region = amd_iommu_apply_resv_region,
3183 .is_attach_deferred = amd_iommu_is_attach_deferred,
3184 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3185 };
3186
3187 /*****************************************************************************
3188 *
3189 * The next functions do a basic initialization of IOMMU for pass through
3190 * mode
3191 *
3192 * In passthrough mode the IOMMU is initialized and enabled but not used for
3193 * DMA-API translation.
3194 *
3195 *****************************************************************************/
3196
3197 /* IOMMUv2 specific functions */
3198 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3199 {
3200 return atomic_notifier_chain_register(&ppr_notifier, nb);
3201 }
3202 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3203
3204 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3205 {
3206 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3207 }
3208 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3209
3210 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3211 {
3212 struct protection_domain *domain = to_pdomain(dom);
3213 unsigned long flags;
3214
3215 spin_lock_irqsave(&domain->lock, flags);
3216
3217 /* Update data structure */
3218 domain->mode = PAGE_MODE_NONE;
3219 domain->updated = true;
3220
3221 /* Make changes visible to IOMMUs */
3222 update_domain(domain);
3223
3224 /* Page-table is not visible to IOMMU anymore, so free it */
3225 free_pagetable(domain);
3226
3227 spin_unlock_irqrestore(&domain->lock, flags);
3228 }
3229 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3230
3231 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3232 {
3233 struct protection_domain *domain = to_pdomain(dom);
3234 unsigned long flags;
3235 int levels, ret;
3236
3237 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3238 return -EINVAL;
3239
3240 /* Number of GCR3 table levels required */
3241 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3242 levels += 1;
3243
3244 if (levels > amd_iommu_max_glx_val)
3245 return -EINVAL;
3246
3247 spin_lock_irqsave(&domain->lock, flags);
3248
3249 /*
3250 * Save us all sanity checks whether devices already in the
3251 * domain support IOMMUv2. Just force that the domain has no
3252 * devices attached when it is switched into IOMMUv2 mode.
3253 */
3254 ret = -EBUSY;
3255 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3256 goto out;
3257
3258 ret = -ENOMEM;
3259 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3260 if (domain->gcr3_tbl == NULL)
3261 goto out;
3262
3263 domain->glx = levels;
3264 domain->flags |= PD_IOMMUV2_MASK;
3265 domain->updated = true;
3266
3267 update_domain(domain);
3268
3269 ret = 0;
3270
3271 out:
3272 spin_unlock_irqrestore(&domain->lock, flags);
3273
3274 return ret;
3275 }
3276 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3277
3278 static int __flush_pasid(struct protection_domain *domain, int pasid,
3279 u64 address, bool size)
3280 {
3281 struct iommu_dev_data *dev_data;
3282 struct iommu_cmd cmd;
3283 int i, ret;
3284
3285 if (!(domain->flags & PD_IOMMUV2_MASK))
3286 return -EINVAL;
3287
3288 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3289
3290 /*
3291 * IOMMU TLB needs to be flushed before Device TLB to
3292 * prevent device TLB refill from IOMMU TLB
3293 */
3294 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3295 if (domain->dev_iommu[i] == 0)
3296 continue;
3297
3298 ret = iommu_queue_command(amd_iommus[i], &cmd);
3299 if (ret != 0)
3300 goto out;
3301 }
3302
3303 /* Wait until IOMMU TLB flushes are complete */
3304 domain_flush_complete(domain);
3305
3306 /* Now flush device TLBs */
3307 list_for_each_entry(dev_data, &domain->dev_list, list) {
3308 struct amd_iommu *iommu;
3309 int qdep;
3310
3311 /*
3312 There might be non-IOMMUv2 capable devices in an IOMMUv2
3313 * domain.
3314 */
3315 if (!dev_data->ats.enabled)
3316 continue;
3317
3318 qdep = dev_data->ats.qdep;
3319 iommu = amd_iommu_rlookup_table[dev_data->devid];
3320
3321 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3322 qdep, address, size);
3323
3324 ret = iommu_queue_command(iommu, &cmd);
3325 if (ret != 0)
3326 goto out;
3327 }
3328
3329 /* Wait until all device TLBs are flushed */
3330 domain_flush_complete(domain);
3331
3332 ret = 0;
3333
3334 out:
3335
3336 return ret;
3337 }
3338
3339 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3340 u64 address)
3341 {
3342 return __flush_pasid(domain, pasid, address, false);
3343 }
3344
3345 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3346 u64 address)
3347 {
3348 struct protection_domain *domain = to_pdomain(dom);
3349 unsigned long flags;
3350 int ret;
3351
3352 spin_lock_irqsave(&domain->lock, flags);
3353 ret = __amd_iommu_flush_page(domain, pasid, address);
3354 spin_unlock_irqrestore(&domain->lock, flags);
3355
3356 return ret;
3357 }
3358 EXPORT_SYMBOL(amd_iommu_flush_page);
3359
3360 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3361 {
3362 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3363 true);
3364 }
3365
3366 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3367 {
3368 struct protection_domain *domain = to_pdomain(dom);
3369 unsigned long flags;
3370 int ret;
3371
3372 spin_lock_irqsave(&domain->lock, flags);
3373 ret = __amd_iommu_flush_tlb(domain, pasid);
3374 spin_unlock_irqrestore(&domain->lock, flags);
3375
3376 return ret;
3377 }
3378 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3379
3380 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3381 {
3382 int index;
3383 u64 *pte;
3384
3385 while (true) {
3386
3387 index = (pasid >> (9 * level)) & 0x1ff;
3388 pte = &root[index];
3389
3390 if (level == 0)
3391 break;
3392
3393 if (!(*pte & GCR3_VALID)) {
3394 if (!alloc)
3395 return NULL;
3396
3397 root = (void *)get_zeroed_page(GFP_ATOMIC);
3398 if (root == NULL)
3399 return NULL;
3400
3401 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3402 }
3403
3404 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3405
3406 level -= 1;
3407 }
3408
3409 return pte;
3410 }
3411
3412 static int __set_gcr3(struct protection_domain *domain, int pasid,
3413 unsigned long cr3)
3414 {
3415 u64 *pte;
3416
3417 if (domain->mode != PAGE_MODE_NONE)
3418 return -EINVAL;
3419
3420 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3421 if (pte == NULL)
3422 return -ENOMEM;
3423
3424 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3425
3426 return __amd_iommu_flush_tlb(domain, pasid);
3427 }
3428
3429 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3430 {
3431 u64 *pte;
3432
3433 if (domain->mode != PAGE_MODE_NONE)
3434 return -EINVAL;
3435
3436 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3437 if (pte == NULL)
3438 return 0;
3439
3440 *pte = 0;
3441
3442 return __amd_iommu_flush_tlb(domain, pasid);
3443 }
3444
3445 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3446 unsigned long cr3)
3447 {
3448 struct protection_domain *domain = to_pdomain(dom);
3449 unsigned long flags;
3450 int ret;
3451
3452 spin_lock_irqsave(&domain->lock, flags);
3453 ret = __set_gcr3(domain, pasid, cr3);
3454 spin_unlock_irqrestore(&domain->lock, flags);
3455
3456 return ret;
3457 }
3458 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3459
3460 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3461 {
3462 struct protection_domain *domain = to_pdomain(dom);
3463 unsigned long flags;
3464 int ret;
3465
3466 spin_lock_irqsave(&domain->lock, flags);
3467 ret = __clear_gcr3(domain, pasid);
3468 spin_unlock_irqrestore(&domain->lock, flags);
3469
3470 return ret;
3471 }
3472 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3473
3474 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3475 int status, int tag)
3476 {
3477 struct iommu_dev_data *dev_data;
3478 struct amd_iommu *iommu;
3479 struct iommu_cmd cmd;
3480
3481 dev_data = get_dev_data(&pdev->dev);
3482 iommu = amd_iommu_rlookup_table[dev_data->devid];
3483
3484 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3485 tag, dev_data->pri_tlp);
3486
3487 return iommu_queue_command(iommu, &cmd);
3488 }
3489 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3490
3491 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3492 {
3493 struct protection_domain *pdomain;
3494
3495 pdomain = get_domain(&pdev->dev);
3496 if (IS_ERR(pdomain))
3497 return NULL;
3498
3499 /* Only return IOMMUv2 domains */
3500 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3501 return NULL;
3502
3503 return &pdomain->domain;
3504 }
3505 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3506
3507 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3508 {
3509 struct iommu_dev_data *dev_data;
3510
3511 if (!amd_iommu_v2_supported())
3512 return;
3513
3514 dev_data = get_dev_data(&pdev->dev);
3515 dev_data->errata |= (1 << erratum);
3516 }
3517 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3518
3519 int amd_iommu_device_info(struct pci_dev *pdev,
3520 struct amd_iommu_device_info *info)
3521 {
3522 int max_pasids;
3523 int pos;
3524
3525 if (pdev == NULL || info == NULL)
3526 return -EINVAL;
3527
3528 if (!amd_iommu_v2_supported())
3529 return -EINVAL;
3530
3531 memset(info, 0, sizeof(*info));
3532
3533 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3534 if (pos)
3535 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3536
3537 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3538 if (pos)
3539 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3540
3541 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3542 if (pos) {
3543 int features;
3544
3545 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3546 max_pasids = min(max_pasids, (1 << 20));
3547
3548 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3549 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3550
3551 features = pci_pasid_features(pdev);
3552 if (features & PCI_PASID_CAP_EXEC)
3553 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3554 if (features & PCI_PASID_CAP_PRIV)
3555 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3556 }
3557
3558 return 0;
3559 }
3560 EXPORT_SYMBOL(amd_iommu_device_info);
3561
3562 #ifdef CONFIG_IRQ_REMAP
3563
3564 /*****************************************************************************
3565 *
3566 * Interrupt Remapping Implementation
3567 *
3568 *****************************************************************************/
3569
3570 static struct irq_chip amd_ir_chip;
3571
3572 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3573 {
3574 u64 dte;
3575
3576 dte = amd_iommu_dev_table[devid].data[2];
3577 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3578 dte |= iommu_virt_to_phys(table->table);
3579 dte |= DTE_IRQ_REMAP_INTCTL;
3580 dte |= DTE_IRQ_TABLE_LEN;
3581 dte |= DTE_IRQ_REMAP_ENABLE;
3582
3583 amd_iommu_dev_table[devid].data[2] = dte;
3584 }
3585
3586 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3587 {
3588 struct irq_remap_table *table = NULL;
3589 struct amd_iommu *iommu;
3590 unsigned long flags;
3591 u16 alias;
3592
3593 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3594
3595 iommu = amd_iommu_rlookup_table[devid];
3596 if (!iommu)
3597 goto out_unlock;
3598
3599 table = irq_lookup_table[devid];
3600 if (table)
3601 goto out_unlock;
3602
3603 alias = amd_iommu_alias_table[devid];
3604 table = irq_lookup_table[alias];
3605 if (table) {
3606 irq_lookup_table[devid] = table;
3607 set_dte_irq_entry(devid, table);
3608 iommu_flush_dte(iommu, devid);
3609 goto out;
3610 }
3611
3612 /* Nothing there yet, allocate new irq remapping table */
3613 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3614 if (!table)
3615 goto out_unlock;
3616
3617 /* Initialize table spin-lock */
3618 spin_lock_init(&table->lock);
3619
3620 if (ioapic)
3621 /* Keep the first 32 indexes free for IOAPIC interrupts */
3622 table->min_index = 32;
3623
3624 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3625 if (!table->table) {
3626 kfree(table);
3627 table = NULL;
3628 goto out_unlock;
3629 }
3630
3631 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3632 memset(table->table, 0,
3633 MAX_IRQS_PER_TABLE * sizeof(u32));
3634 else
3635 memset(table->table, 0,
3636 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3637
3638 if (ioapic) {
3639 int i;
3640
3641 for (i = 0; i < 32; ++i)
3642 iommu->irte_ops->set_allocated(table, i);
3643 }
3644
3645 irq_lookup_table[devid] = table;
3646 set_dte_irq_entry(devid, table);
3647 iommu_flush_dte(iommu, devid);
3648 if (devid != alias) {
3649 irq_lookup_table[alias] = table;
3650 set_dte_irq_entry(alias, table);
3651 iommu_flush_dte(iommu, alias);
3652 }
3653
3654 out:
3655 iommu_completion_wait(iommu);
3656
3657 out_unlock:
3658 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3659
3660 return table;
3661 }
3662
3663 static int alloc_irq_index(u16 devid, int count, bool align)
3664 {
3665 struct irq_remap_table *table;
3666 int index, c, alignment = 1;
3667 unsigned long flags;
3668 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3669
3670 if (!iommu)
3671 return -ENODEV;
3672
3673 table = get_irq_table(devid, false);
3674 if (!table)
3675 return -ENODEV;
3676
3677 if (align)
3678 alignment = roundup_pow_of_two(count);
3679
3680 spin_lock_irqsave(&table->lock, flags);
3681
3682 /* Scan table for free entries */
3683 for (index = ALIGN(table->min_index, alignment), c = 0;
3684 index < MAX_IRQS_PER_TABLE;
3685 index++) {
3686 if (!iommu->irte_ops->is_allocated(table, index)) {
3687 c += 1;
3688 } else {
3689 c = 0;
3690 index = ALIGN(index, alignment);
3691 continue;
3692 }
3693
3694 if (c == count) {
3695 for (; c != 0; --c)
3696 iommu->irte_ops->set_allocated(table, index - c + 1);
3697
3698 index -= count - 1;
3699 goto out;
3700 }
3701 }
3702
3703 index = -ENOSPC;
3704
3705 out:
3706 spin_unlock_irqrestore(&table->lock, flags);
3707
3708 return index;
3709 }
3710
3711 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3712 struct amd_ir_data *data)
3713 {
3714 struct irq_remap_table *table;
3715 struct amd_iommu *iommu;
3716 unsigned long flags;
3717 struct irte_ga *entry;
3718
3719 iommu = amd_iommu_rlookup_table[devid];
3720 if (iommu == NULL)
3721 return -EINVAL;
3722
3723 table = get_irq_table(devid, false);
3724 if (!table)
3725 return -ENOMEM;
3726
3727 spin_lock_irqsave(&table->lock, flags);
3728
3729 entry = (struct irte_ga *)table->table;
3730 entry = &entry[index];
3731 entry->lo.fields_remap.valid = 0;
3732 entry->hi.val = irte->hi.val;
3733 entry->lo.val = irte->lo.val;
3734 entry->lo.fields_remap.valid = 1;
3735 if (data)
3736 data->ref = entry;
3737
3738 spin_unlock_irqrestore(&table->lock, flags);
3739
3740 iommu_flush_irt(iommu, devid);
3741 iommu_completion_wait(iommu);
3742
3743 return 0;
3744 }
3745
3746 static int modify_irte(u16 devid, int index, union irte *irte)
3747 {
3748 struct irq_remap_table *table;
3749 struct amd_iommu *iommu;
3750 unsigned long flags;
3751
3752 iommu = amd_iommu_rlookup_table[devid];
3753 if (iommu == NULL)
3754 return -EINVAL;
3755
3756 table = get_irq_table(devid, false);
3757 if (!table)
3758 return -ENOMEM;
3759
3760 spin_lock_irqsave(&table->lock, flags);
3761 table->table[index] = irte->val;
3762 spin_unlock_irqrestore(&table->lock, flags);
3763
3764 iommu_flush_irt(iommu, devid);
3765 iommu_completion_wait(iommu);
3766
3767 return 0;
3768 }
3769
3770 static void free_irte(u16 devid, int index)
3771 {
3772 struct irq_remap_table *table;
3773 struct amd_iommu *iommu;
3774 unsigned long flags;
3775
3776 iommu = amd_iommu_rlookup_table[devid];
3777 if (iommu == NULL)
3778 return;
3779
3780 table = get_irq_table(devid, false);
3781 if (!table)
3782 return;
3783
3784 spin_lock_irqsave(&table->lock, flags);
3785 iommu->irte_ops->clear_allocated(table, index);
3786 spin_unlock_irqrestore(&table->lock, flags);
3787
3788 iommu_flush_irt(iommu, devid);
3789 iommu_completion_wait(iommu);
3790 }
3791
3792 static void irte_prepare(void *entry,
3793 u32 delivery_mode, u32 dest_mode,
3794 u8 vector, u32 dest_apicid, int devid)
3795 {
3796 union irte *irte = (union irte *) entry;
3797
3798 irte->val = 0;
3799 irte->fields.vector = vector;
3800 irte->fields.int_type = delivery_mode;
3801 irte->fields.destination = dest_apicid;
3802 irte->fields.dm = dest_mode;
3803 irte->fields.valid = 1;
3804 }
3805
3806 static void irte_ga_prepare(void *entry,
3807 u32 delivery_mode, u32 dest_mode,
3808 u8 vector, u32 dest_apicid, int devid)
3809 {
3810 struct irte_ga *irte = (struct irte_ga *) entry;
3811
3812 irte->lo.val = 0;
3813 irte->hi.val = 0;
3814 irte->lo.fields_remap.int_type = delivery_mode;
3815 irte->lo.fields_remap.dm = dest_mode;
3816 irte->hi.fields.vector = vector;
3817 irte->lo.fields_remap.destination = dest_apicid;
3818 irte->lo.fields_remap.valid = 1;
3819 }
3820
3821 static void irte_activate(void *entry, u16 devid, u16 index)
3822 {
3823 union irte *irte = (union irte *) entry;
3824
3825 irte->fields.valid = 1;
3826 modify_irte(devid, index, irte);
3827 }
3828
3829 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3830 {
3831 struct irte_ga *irte = (struct irte_ga *) entry;
3832
3833 irte->lo.fields_remap.valid = 1;
3834 modify_irte_ga(devid, index, irte, NULL);
3835 }
3836
3837 static void irte_deactivate(void *entry, u16 devid, u16 index)
3838 {
3839 union irte *irte = (union irte *) entry;
3840
3841 irte->fields.valid = 0;
3842 modify_irte(devid, index, irte);
3843 }
3844
3845 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3846 {
3847 struct irte_ga *irte = (struct irte_ga *) entry;
3848
3849 irte->lo.fields_remap.valid = 0;
3850 modify_irte_ga(devid, index, irte, NULL);
3851 }
3852
3853 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3854 u8 vector, u32 dest_apicid)
3855 {
3856 union irte *irte = (union irte *) entry;
3857
3858 irte->fields.vector = vector;
3859 irte->fields.destination = dest_apicid;
3860 modify_irte(devid, index, irte);
3861 }
3862
3863 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3864 u8 vector, u32 dest_apicid)
3865 {
3866 struct irte_ga *irte = (struct irte_ga *) entry;
3867 struct iommu_dev_data *dev_data = search_dev_data(devid);
3868
3869 if (!dev_data || !dev_data->use_vapic ||
3870 !irte->lo.fields_remap.guest_mode) {
3871 irte->hi.fields.vector = vector;
3872 irte->lo.fields_remap.destination = dest_apicid;
3873 modify_irte_ga(devid, index, irte, NULL);
3874 }
3875 }
3876
3877 #define IRTE_ALLOCATED (~1U)
3878 static void irte_set_allocated(struct irq_remap_table *table, int index)
3879 {
3880 table->table[index] = IRTE_ALLOCATED;
3881 }
3882
3883 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3884 {
3885 struct irte_ga *ptr = (struct irte_ga *)table->table;
3886 struct irte_ga *irte = &ptr[index];
3887
3888 memset(&irte->lo.val, 0, sizeof(u64));
3889 memset(&irte->hi.val, 0, sizeof(u64));
3890 irte->hi.fields.vector = 0xff;
3891 }
3892
3893 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3894 {
3895 union irte *ptr = (union irte *)table->table;
3896 union irte *irte = &ptr[index];
3897
3898 return irte->val != 0;
3899 }
3900
3901 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3902 {
3903 struct irte_ga *ptr = (struct irte_ga *)table->table;
3904 struct irte_ga *irte = &ptr[index];
3905
3906 return irte->hi.fields.vector != 0;
3907 }
3908
3909 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3910 {
3911 table->table[index] = 0;
3912 }
3913
3914 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3915 {
3916 struct irte_ga *ptr = (struct irte_ga *)table->table;
3917 struct irte_ga *irte = &ptr[index];
3918
3919 memset(&irte->lo.val, 0, sizeof(u64));
3920 memset(&irte->hi.val, 0, sizeof(u64));
3921 }
3922
3923 static int get_devid(struct irq_alloc_info *info)
3924 {
3925 int devid = -1;
3926
3927 switch (info->type) {
3928 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3929 devid = get_ioapic_devid(info->ioapic_id);
3930 break;
3931 case X86_IRQ_ALLOC_TYPE_HPET:
3932 devid = get_hpet_devid(info->hpet_id);
3933 break;
3934 case X86_IRQ_ALLOC_TYPE_MSI:
3935 case X86_IRQ_ALLOC_TYPE_MSIX:
3936 devid = get_device_id(&info->msi_dev->dev);
3937 break;
3938 default:
3939 BUG_ON(1);
3940 break;
3941 }
3942
3943 return devid;
3944 }
3945
3946 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3947 {
3948 struct amd_iommu *iommu;
3949 int devid;
3950
3951 if (!info)
3952 return NULL;
3953
3954 devid = get_devid(info);
3955 if (devid >= 0) {
3956 iommu = amd_iommu_rlookup_table[devid];
3957 if (iommu)
3958 return iommu->ir_domain;
3959 }
3960
3961 return NULL;
3962 }
3963
3964 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3965 {
3966 struct amd_iommu *iommu;
3967 int devid;
3968
3969 if (!info)
3970 return NULL;
3971
3972 switch (info->type) {
3973 case X86_IRQ_ALLOC_TYPE_MSI:
3974 case X86_IRQ_ALLOC_TYPE_MSIX:
3975 devid = get_device_id(&info->msi_dev->dev);
3976 if (devid < 0)
3977 return NULL;
3978
3979 iommu = amd_iommu_rlookup_table[devid];
3980 if (iommu)
3981 return iommu->msi_domain;
3982 break;
3983 default:
3984 break;
3985 }
3986
3987 return NULL;
3988 }
3989
3990 struct irq_remap_ops amd_iommu_irq_ops = {
3991 .prepare = amd_iommu_prepare,
3992 .enable = amd_iommu_enable,
3993 .disable = amd_iommu_disable,
3994 .reenable = amd_iommu_reenable,
3995 .enable_faulting = amd_iommu_enable_faulting,
3996 .get_ir_irq_domain = get_ir_irq_domain,
3997 .get_irq_domain = get_irq_domain,
3998 };
3999
4000 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4001 struct irq_cfg *irq_cfg,
4002 struct irq_alloc_info *info,
4003 int devid, int index, int sub_handle)
4004 {
4005 struct irq_2_irte *irte_info = &data->irq_2_irte;
4006 struct msi_msg *msg = &data->msi_entry;
4007 struct IO_APIC_route_entry *entry;
4008 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4009
4010 if (!iommu)
4011 return;
4012
4013 data->irq_2_irte.devid = devid;
4014 data->irq_2_irte.index = index + sub_handle;
4015 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4016 apic->irq_dest_mode, irq_cfg->vector,
4017 irq_cfg->dest_apicid, devid);
4018
4019 switch (info->type) {
4020 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4021 /* Setup IOAPIC entry */
4022 entry = info->ioapic_entry;
4023 info->ioapic_entry = NULL;
4024 memset(entry, 0, sizeof(*entry));
4025 entry->vector = index;
4026 entry->mask = 0;
4027 entry->trigger = info->ioapic_trigger;
4028 entry->polarity = info->ioapic_polarity;
4029 /* Mask level triggered irqs. */
4030 if (info->ioapic_trigger)
4031 entry->mask = 1;
4032 break;
4033
4034 case X86_IRQ_ALLOC_TYPE_HPET:
4035 case X86_IRQ_ALLOC_TYPE_MSI:
4036 case X86_IRQ_ALLOC_TYPE_MSIX:
4037 msg->address_hi = MSI_ADDR_BASE_HI;
4038 msg->address_lo = MSI_ADDR_BASE_LO;
4039 msg->data = irte_info->index;
4040 break;
4041
4042 default:
4043 BUG_ON(1);
4044 break;
4045 }
4046 }
4047
4048 struct amd_irte_ops irte_32_ops = {
4049 .prepare = irte_prepare,
4050 .activate = irte_activate,
4051 .deactivate = irte_deactivate,
4052 .set_affinity = irte_set_affinity,
4053 .set_allocated = irte_set_allocated,
4054 .is_allocated = irte_is_allocated,
4055 .clear_allocated = irte_clear_allocated,
4056 };
4057
4058 struct amd_irte_ops irte_128_ops = {
4059 .prepare = irte_ga_prepare,
4060 .activate = irte_ga_activate,
4061 .deactivate = irte_ga_deactivate,
4062 .set_affinity = irte_ga_set_affinity,
4063 .set_allocated = irte_ga_set_allocated,
4064 .is_allocated = irte_ga_is_allocated,
4065 .clear_allocated = irte_ga_clear_allocated,
4066 };
4067
4068 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4069 unsigned int nr_irqs, void *arg)
4070 {
4071 struct irq_alloc_info *info = arg;
4072 struct irq_data *irq_data;
4073 struct amd_ir_data *data = NULL;
4074 struct irq_cfg *cfg;
4075 int i, ret, devid;
4076 int index = -1;
4077
4078 if (!info)
4079 return -EINVAL;
4080 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4081 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4082 return -EINVAL;
4083
4084 /*
4085 * With IRQ remapping enabled, don't need contiguous CPU vectors
4086 * to support multiple MSI interrupts.
4087 */
4088 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4089 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4090
4091 devid = get_devid(info);
4092 if (devid < 0)
4093 return -EINVAL;
4094
4095 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4096 if (ret < 0)
4097 return ret;
4098
4099 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4100 if (get_irq_table(devid, true))
4101 index = info->ioapic_pin;
4102 else
4103 ret = -ENOMEM;
4104 } else {
4105 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4106
4107 index = alloc_irq_index(devid, nr_irqs, align);
4108 }
4109 if (index < 0) {
4110 pr_warn("Failed to allocate IRTE\n");
4111 ret = index;
4112 goto out_free_parent;
4113 }
4114
4115 for (i = 0; i < nr_irqs; i++) {
4116 irq_data = irq_domain_get_irq_data(domain, virq + i);
4117 cfg = irqd_cfg(irq_data);
4118 if (!irq_data || !cfg) {
4119 ret = -EINVAL;
4120 goto out_free_data;
4121 }
4122
4123 ret = -ENOMEM;
4124 data = kzalloc(sizeof(*data), GFP_KERNEL);
4125 if (!data)
4126 goto out_free_data;
4127
4128 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4129 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4130 else
4131 data->entry = kzalloc(sizeof(struct irte_ga),
4132 GFP_KERNEL);
4133 if (!data->entry) {
4134 kfree(data);
4135 goto out_free_data;
4136 }
4137
4138 irq_data->hwirq = (devid << 16) + i;
4139 irq_data->chip_data = data;
4140 irq_data->chip = &amd_ir_chip;
4141 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4142 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4143 }
4144
4145 return 0;
4146
4147 out_free_data:
4148 for (i--; i >= 0; i--) {
4149 irq_data = irq_domain_get_irq_data(domain, virq + i);
4150 if (irq_data)
4151 kfree(irq_data->chip_data);
4152 }
4153 for (i = 0; i < nr_irqs; i++)
4154 free_irte(devid, index + i);
4155 out_free_parent:
4156 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4157 return ret;
4158 }
4159
4160 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4161 unsigned int nr_irqs)
4162 {
4163 struct irq_2_irte *irte_info;
4164 struct irq_data *irq_data;
4165 struct amd_ir_data *data;
4166 int i;
4167
4168 for (i = 0; i < nr_irqs; i++) {
4169 irq_data = irq_domain_get_irq_data(domain, virq + i);
4170 if (irq_data && irq_data->chip_data) {
4171 data = irq_data->chip_data;
4172 irte_info = &data->irq_2_irte;
4173 free_irte(irte_info->devid, irte_info->index);
4174 kfree(data->entry);
4175 kfree(data);
4176 }
4177 }
4178 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4179 }
4180
4181 static void irq_remapping_activate(struct irq_domain *domain,
4182 struct irq_data *irq_data)
4183 {
4184 struct amd_ir_data *data = irq_data->chip_data;
4185 struct irq_2_irte *irte_info = &data->irq_2_irte;
4186 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4187
4188 if (iommu)
4189 iommu->irte_ops->activate(data->entry, irte_info->devid,
4190 irte_info->index);
4191 }
4192
4193 static void irq_remapping_deactivate(struct irq_domain *domain,
4194 struct irq_data *irq_data)
4195 {
4196 struct amd_ir_data *data = irq_data->chip_data;
4197 struct irq_2_irte *irte_info = &data->irq_2_irte;
4198 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4199
4200 if (iommu)
4201 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4202 irte_info->index);
4203 }
4204
4205 static const struct irq_domain_ops amd_ir_domain_ops = {
4206 .alloc = irq_remapping_alloc,
4207 .free = irq_remapping_free,
4208 .activate = irq_remapping_activate,
4209 .deactivate = irq_remapping_deactivate,
4210 };
4211
4212 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4213 {
4214 struct amd_iommu *iommu;
4215 struct amd_iommu_pi_data *pi_data = vcpu_info;
4216 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4217 struct amd_ir_data *ir_data = data->chip_data;
4218 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4219 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4220 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4221
4222 /* Note:
4223 * This device has never been set up for guest mode.
4224 * we should not modify the IRTE
4225 */
4226 if (!dev_data || !dev_data->use_vapic)
4227 return 0;
4228
4229 pi_data->ir_data = ir_data;
4230
4231 /* Note:
4232 * SVM tries to set up for VAPIC mode, but we are in
4233 * legacy mode. So, we force legacy mode instead.
4234 */
4235 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4236 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4237 __func__);
4238 pi_data->is_guest_mode = false;
4239 }
4240
4241 iommu = amd_iommu_rlookup_table[irte_info->devid];
4242 if (iommu == NULL)
4243 return -EINVAL;
4244
4245 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4246 if (pi_data->is_guest_mode) {
4247 /* Setting */
4248 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4249 irte->hi.fields.vector = vcpu_pi_info->vector;
4250 irte->lo.fields_vapic.ga_log_intr = 1;
4251 irte->lo.fields_vapic.guest_mode = 1;
4252 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4253
4254 ir_data->cached_ga_tag = pi_data->ga_tag;
4255 } else {
4256 /* Un-Setting */
4257 struct irq_cfg *cfg = irqd_cfg(data);
4258
4259 irte->hi.val = 0;
4260 irte->lo.val = 0;
4261 irte->hi.fields.vector = cfg->vector;
4262 irte->lo.fields_remap.guest_mode = 0;
4263 irte->lo.fields_remap.destination = cfg->dest_apicid;
4264 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4265 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4266
4267 /*
4268 * This communicates the ga_tag back to the caller
4269 * so that it can do all the necessary clean up.
4270 */
4271 ir_data->cached_ga_tag = 0;
4272 }
4273
4274 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4275 }
4276
4277 static int amd_ir_set_affinity(struct irq_data *data,
4278 const struct cpumask *mask, bool force)
4279 {
4280 struct amd_ir_data *ir_data = data->chip_data;
4281 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4282 struct irq_cfg *cfg = irqd_cfg(data);
4283 struct irq_data *parent = data->parent_data;
4284 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4285 int ret;
4286
4287 if (!iommu)
4288 return -ENODEV;
4289
4290 ret = parent->chip->irq_set_affinity(parent, mask, force);
4291 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4292 return ret;
4293
4294 /*
4295 * Atomically updates the IRTE with the new destination, vector
4296 * and flushes the interrupt entry cache.
4297 */
4298 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4299 irte_info->index, cfg->vector, cfg->dest_apicid);
4300
4301 /*
4302 * After this point, all the interrupts will start arriving
4303 * at the new destination. So, time to cleanup the previous
4304 * vector allocation.
4305 */
4306 send_cleanup_vector(cfg);
4307
4308 return IRQ_SET_MASK_OK_DONE;
4309 }
4310
4311 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4312 {
4313 struct amd_ir_data *ir_data = irq_data->chip_data;
4314
4315 *msg = ir_data->msi_entry;
4316 }
4317
4318 static struct irq_chip amd_ir_chip = {
4319 .name = "AMD-IR",
4320 .irq_ack = ir_ack_apic_edge,
4321 .irq_set_affinity = amd_ir_set_affinity,
4322 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4323 .irq_compose_msi_msg = ir_compose_msi_msg,
4324 };
4325
4326 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4327 {
4328 struct fwnode_handle *fn;
4329
4330 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4331 if (!fn)
4332 return -ENOMEM;
4333 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4334 irq_domain_free_fwnode(fn);
4335 if (!iommu->ir_domain)
4336 return -ENOMEM;
4337
4338 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4339 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4340 "AMD-IR-MSI",
4341 iommu->index);
4342 return 0;
4343 }
4344
4345 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4346 {
4347 unsigned long flags;
4348 struct amd_iommu *iommu;
4349 struct irq_remap_table *irt;
4350 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4351 int devid = ir_data->irq_2_irte.devid;
4352 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4353 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4354
4355 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4356 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4357 return 0;
4358
4359 iommu = amd_iommu_rlookup_table[devid];
4360 if (!iommu)
4361 return -ENODEV;
4362
4363 irt = get_irq_table(devid, false);
4364 if (!irt)
4365 return -ENODEV;
4366
4367 spin_lock_irqsave(&irt->lock, flags);
4368
4369 if (ref->lo.fields_vapic.guest_mode) {
4370 if (cpu >= 0)
4371 ref->lo.fields_vapic.destination = cpu;
4372 ref->lo.fields_vapic.is_run = is_run;
4373 barrier();
4374 }
4375
4376 spin_unlock_irqrestore(&irt->lock, flags);
4377
4378 iommu_flush_irt(iommu, devid);
4379 iommu_completion_wait(iommu);
4380 return 0;
4381 }
4382 EXPORT_SYMBOL(amd_iommu_update_ga);
4383 #endif
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