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[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
59 #define LOOP_TIMEOUT 100000
60
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
71
72 /*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
78 * 512GB Pages are not supported due to a hardware bug
79 */
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
81
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
87
88 LIST_HEAD(ioapic_map);
89 LIST_HEAD(hpet_map);
90 LIST_HEAD(acpihid_map);
91
92 #define FLUSH_QUEUE_SIZE 256
93
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
96 unsigned long pages;
97 struct dma_ops_domain *dma_dom;
98 };
99
100 struct flush_queue {
101 spinlock_t lock;
102 unsigned next;
103 struct flush_queue_entry *entries;
104 };
105
106 static DEFINE_PER_CPU(struct flush_queue, flush_queue);
107
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
110
111 /*
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
114 */
115 const struct iommu_ops amd_iommu_ops;
116
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
119
120 static const struct dma_map_ops amd_iommu_dma_ops;
121
122 /*
123 * This struct contains device specific data for the IOMMU
124 */
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
133 struct {
134 bool enabled;
135 int qdep;
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
138 PPR completions */
139 u32 errata; /* Bitmap for errata to apply */
140 bool use_vapic; /* Enable device to use vapic mode */
141
142 struct ratelimit_state rs; /* Ratelimit IOPF messages */
143 };
144
145 /*
146 * general struct to manage commands send to an IOMMU
147 */
148 struct iommu_cmd {
149 u32 data[4];
150 };
151
152 struct kmem_cache *amd_iommu_irq_cache;
153
154 static void update_domain(struct protection_domain *domain);
155 static int protection_domain_init(struct protection_domain *domain);
156 static void detach_device(struct device *dev);
157
158 /*
159 * Data container for a dma_ops specific protection domain
160 */
161 struct dma_ops_domain {
162 /* generic protection domain information */
163 struct protection_domain domain;
164
165 /* IOVA RB-Tree */
166 struct iova_domain iovad;
167 };
168
169 static struct iova_domain reserved_iova_ranges;
170 static struct lock_class_key reserved_rbtree_key;
171
172 /****************************************************************************
173 *
174 * Helper functions
175 *
176 ****************************************************************************/
177
178 static inline int match_hid_uid(struct device *dev,
179 struct acpihid_map_entry *entry)
180 {
181 const char *hid, *uid;
182
183 hid = acpi_device_hid(ACPI_COMPANION(dev));
184 uid = acpi_device_uid(ACPI_COMPANION(dev));
185
186 if (!hid || !(*hid))
187 return -ENODEV;
188
189 if (!uid || !(*uid))
190 return strcmp(hid, entry->hid);
191
192 if (!(*entry->uid))
193 return strcmp(hid, entry->hid);
194
195 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
196 }
197
198 static inline u16 get_pci_device_id(struct device *dev)
199 {
200 struct pci_dev *pdev = to_pci_dev(dev);
201
202 return PCI_DEVID(pdev->bus->number, pdev->devfn);
203 }
204
205 static inline int get_acpihid_device_id(struct device *dev,
206 struct acpihid_map_entry **entry)
207 {
208 struct acpihid_map_entry *p;
209
210 list_for_each_entry(p, &acpihid_map, list) {
211 if (!match_hid_uid(dev, p)) {
212 if (entry)
213 *entry = p;
214 return p->devid;
215 }
216 }
217 return -EINVAL;
218 }
219
220 static inline int get_device_id(struct device *dev)
221 {
222 int devid;
223
224 if (dev_is_pci(dev))
225 devid = get_pci_device_id(dev);
226 else
227 devid = get_acpihid_device_id(dev, NULL);
228
229 return devid;
230 }
231
232 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
233 {
234 return container_of(dom, struct protection_domain, domain);
235 }
236
237 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
238 {
239 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
240 return container_of(domain, struct dma_ops_domain, domain);
241 }
242
243 static struct iommu_dev_data *alloc_dev_data(u16 devid)
244 {
245 struct iommu_dev_data *dev_data;
246 unsigned long flags;
247
248 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
249 if (!dev_data)
250 return NULL;
251
252 dev_data->devid = devid;
253
254 spin_lock_irqsave(&dev_data_list_lock, flags);
255 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
256 spin_unlock_irqrestore(&dev_data_list_lock, flags);
257
258 ratelimit_default_init(&dev_data->rs);
259
260 return dev_data;
261 }
262
263 static struct iommu_dev_data *search_dev_data(u16 devid)
264 {
265 struct iommu_dev_data *dev_data;
266 unsigned long flags;
267
268 spin_lock_irqsave(&dev_data_list_lock, flags);
269 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
270 if (dev_data->devid == devid)
271 goto out_unlock;
272 }
273
274 dev_data = NULL;
275
276 out_unlock:
277 spin_unlock_irqrestore(&dev_data_list_lock, flags);
278
279 return dev_data;
280 }
281
282 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
283 {
284 *(u16 *)data = alias;
285 return 0;
286 }
287
288 static u16 get_alias(struct device *dev)
289 {
290 struct pci_dev *pdev = to_pci_dev(dev);
291 u16 devid, ivrs_alias, pci_alias;
292
293 /* The callers make sure that get_device_id() does not fail here */
294 devid = get_device_id(dev);
295 ivrs_alias = amd_iommu_alias_table[devid];
296 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
297
298 if (ivrs_alias == pci_alias)
299 return ivrs_alias;
300
301 /*
302 * DMA alias showdown
303 *
304 * The IVRS is fairly reliable in telling us about aliases, but it
305 * can't know about every screwy device. If we don't have an IVRS
306 * reported alias, use the PCI reported alias. In that case we may
307 * still need to initialize the rlookup and dev_table entries if the
308 * alias is to a non-existent device.
309 */
310 if (ivrs_alias == devid) {
311 if (!amd_iommu_rlookup_table[pci_alias]) {
312 amd_iommu_rlookup_table[pci_alias] =
313 amd_iommu_rlookup_table[devid];
314 memcpy(amd_iommu_dev_table[pci_alias].data,
315 amd_iommu_dev_table[devid].data,
316 sizeof(amd_iommu_dev_table[pci_alias].data));
317 }
318
319 return pci_alias;
320 }
321
322 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
323 "for device %s[%04x:%04x], kernel reported alias "
324 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
325 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
326 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
327 PCI_FUNC(pci_alias));
328
329 /*
330 * If we don't have a PCI DMA alias and the IVRS alias is on the same
331 * bus, then the IVRS table may know about a quirk that we don't.
332 */
333 if (pci_alias == devid &&
334 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
335 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
336 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
337 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
338 dev_name(dev));
339 }
340
341 return ivrs_alias;
342 }
343
344 static struct iommu_dev_data *find_dev_data(u16 devid)
345 {
346 struct iommu_dev_data *dev_data;
347
348 dev_data = search_dev_data(devid);
349
350 if (dev_data == NULL)
351 dev_data = alloc_dev_data(devid);
352
353 return dev_data;
354 }
355
356 static struct iommu_dev_data *get_dev_data(struct device *dev)
357 {
358 return dev->archdata.iommu;
359 }
360
361 /*
362 * Find or create an IOMMU group for a acpihid device.
363 */
364 static struct iommu_group *acpihid_device_group(struct device *dev)
365 {
366 struct acpihid_map_entry *p, *entry = NULL;
367 int devid;
368
369 devid = get_acpihid_device_id(dev, &entry);
370 if (devid < 0)
371 return ERR_PTR(devid);
372
373 list_for_each_entry(p, &acpihid_map, list) {
374 if ((devid == p->devid) && p->group)
375 entry->group = p->group;
376 }
377
378 if (!entry->group)
379 entry->group = generic_device_group(dev);
380 else
381 iommu_group_ref_get(entry->group);
382
383 return entry->group;
384 }
385
386 static bool pci_iommuv2_capable(struct pci_dev *pdev)
387 {
388 static const int caps[] = {
389 PCI_EXT_CAP_ID_ATS,
390 PCI_EXT_CAP_ID_PRI,
391 PCI_EXT_CAP_ID_PASID,
392 };
393 int i, pos;
394
395 for (i = 0; i < 3; ++i) {
396 pos = pci_find_ext_capability(pdev, caps[i]);
397 if (pos == 0)
398 return false;
399 }
400
401 return true;
402 }
403
404 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
405 {
406 struct iommu_dev_data *dev_data;
407
408 dev_data = get_dev_data(&pdev->dev);
409
410 return dev_data->errata & (1 << erratum) ? true : false;
411 }
412
413 /*
414 * This function checks if the driver got a valid device from the caller to
415 * avoid dereferencing invalid pointers.
416 */
417 static bool check_device(struct device *dev)
418 {
419 int devid;
420
421 if (!dev || !dev->dma_mask)
422 return false;
423
424 devid = get_device_id(dev);
425 if (devid < 0)
426 return false;
427
428 /* Out of our scope? */
429 if (devid > amd_iommu_last_bdf)
430 return false;
431
432 if (amd_iommu_rlookup_table[devid] == NULL)
433 return false;
434
435 return true;
436 }
437
438 static void init_iommu_group(struct device *dev)
439 {
440 struct iommu_group *group;
441
442 group = iommu_group_get_for_dev(dev);
443 if (IS_ERR(group))
444 return;
445
446 iommu_group_put(group);
447 }
448
449 static int iommu_init_device(struct device *dev)
450 {
451 struct iommu_dev_data *dev_data;
452 struct amd_iommu *iommu;
453 int devid;
454
455 if (dev->archdata.iommu)
456 return 0;
457
458 devid = get_device_id(dev);
459 if (devid < 0)
460 return devid;
461
462 iommu = amd_iommu_rlookup_table[devid];
463
464 dev_data = find_dev_data(devid);
465 if (!dev_data)
466 return -ENOMEM;
467
468 dev_data->alias = get_alias(dev);
469
470 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
471 struct amd_iommu *iommu;
472
473 iommu = amd_iommu_rlookup_table[dev_data->devid];
474 dev_data->iommu_v2 = iommu->is_iommu_v2;
475 }
476
477 dev->archdata.iommu = dev_data;
478
479 iommu_device_link(&iommu->iommu, dev);
480
481 return 0;
482 }
483
484 static void iommu_ignore_device(struct device *dev)
485 {
486 u16 alias;
487 int devid;
488
489 devid = get_device_id(dev);
490 if (devid < 0)
491 return;
492
493 alias = get_alias(dev);
494
495 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
496 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
497
498 amd_iommu_rlookup_table[devid] = NULL;
499 amd_iommu_rlookup_table[alias] = NULL;
500 }
501
502 static void iommu_uninit_device(struct device *dev)
503 {
504 struct iommu_dev_data *dev_data;
505 struct amd_iommu *iommu;
506 int devid;
507
508 devid = get_device_id(dev);
509 if (devid < 0)
510 return;
511
512 iommu = amd_iommu_rlookup_table[devid];
513
514 dev_data = search_dev_data(devid);
515 if (!dev_data)
516 return;
517
518 if (dev_data->domain)
519 detach_device(dev);
520
521 iommu_device_unlink(&iommu->iommu, dev);
522
523 iommu_group_remove_device(dev);
524
525 /* Remove dma-ops */
526 dev->dma_ops = NULL;
527
528 /*
529 * We keep dev_data around for unplugged devices and reuse it when the
530 * device is re-plugged - not doing so would introduce a ton of races.
531 */
532 }
533
534 /****************************************************************************
535 *
536 * Interrupt handling functions
537 *
538 ****************************************************************************/
539
540 static void dump_dte_entry(u16 devid)
541 {
542 int i;
543
544 for (i = 0; i < 4; ++i)
545 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
546 amd_iommu_dev_table[devid].data[i]);
547 }
548
549 static void dump_command(unsigned long phys_addr)
550 {
551 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
552 int i;
553
554 for (i = 0; i < 4; ++i)
555 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
556 }
557
558 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
559 u64 address, int flags)
560 {
561 struct iommu_dev_data *dev_data = NULL;
562 struct pci_dev *pdev;
563
564 pdev = pci_get_bus_and_slot(PCI_BUS_NUM(devid), devid & 0xff);
565 if (pdev)
566 dev_data = get_dev_data(&pdev->dev);
567
568 if (dev_data && __ratelimit(&dev_data->rs)) {
569 dev_err(&pdev->dev, "AMD-Vi: Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%016llx flags=0x%04x]\n",
570 domain_id, address, flags);
571 } else if (printk_ratelimit()) {
572 pr_err("AMD-Vi: Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%016llx flags=0x%04x]\n",
573 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
574 domain_id, address, flags);
575 }
576
577 if (pdev)
578 pci_dev_put(pdev);
579 }
580
581 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
582 {
583 int type, devid, domid, flags;
584 volatile u32 *event = __evt;
585 int count = 0;
586 u64 address;
587
588 retry:
589 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
590 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
591 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
592 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
593 address = (u64)(((u64)event[3]) << 32) | event[2];
594
595 if (type == 0) {
596 /* Did we hit the erratum? */
597 if (++count == LOOP_TIMEOUT) {
598 pr_err("AMD-Vi: No event written to event log\n");
599 return;
600 }
601 udelay(1);
602 goto retry;
603 }
604
605 if (type == EVENT_TYPE_IO_FAULT) {
606 amd_iommu_report_page_fault(devid, domid, address, flags);
607 return;
608 } else {
609 printk(KERN_ERR "AMD-Vi: Event logged [");
610 }
611
612 switch (type) {
613 case EVENT_TYPE_ILL_DEV:
614 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
615 "address=0x%016llx flags=0x%04x]\n",
616 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
617 address, flags);
618 dump_dte_entry(devid);
619 break;
620 case EVENT_TYPE_DEV_TAB_ERR:
621 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
622 "address=0x%016llx flags=0x%04x]\n",
623 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
624 address, flags);
625 break;
626 case EVENT_TYPE_PAGE_TAB_ERR:
627 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
628 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
629 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
630 domid, address, flags);
631 break;
632 case EVENT_TYPE_ILL_CMD:
633 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
634 dump_command(address);
635 break;
636 case EVENT_TYPE_CMD_HARD_ERR:
637 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
638 "flags=0x%04x]\n", address, flags);
639 break;
640 case EVENT_TYPE_IOTLB_INV_TO:
641 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
642 "address=0x%016llx]\n",
643 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
644 address);
645 break;
646 case EVENT_TYPE_INV_DEV_REQ:
647 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
648 "address=0x%016llx flags=0x%04x]\n",
649 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
650 address, flags);
651 break;
652 default:
653 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
654 }
655
656 memset(__evt, 0, 4 * sizeof(u32));
657 }
658
659 static void iommu_poll_events(struct amd_iommu *iommu)
660 {
661 u32 head, tail;
662
663 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
664 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
665
666 while (head != tail) {
667 iommu_print_event(iommu, iommu->evt_buf + head);
668 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
669 }
670
671 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
672 }
673
674 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
675 {
676 struct amd_iommu_fault fault;
677
678 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
679 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
680 return;
681 }
682
683 fault.address = raw[1];
684 fault.pasid = PPR_PASID(raw[0]);
685 fault.device_id = PPR_DEVID(raw[0]);
686 fault.tag = PPR_TAG(raw[0]);
687 fault.flags = PPR_FLAGS(raw[0]);
688
689 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
690 }
691
692 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
693 {
694 u32 head, tail;
695
696 if (iommu->ppr_log == NULL)
697 return;
698
699 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
701
702 while (head != tail) {
703 volatile u64 *raw;
704 u64 entry[2];
705 int i;
706
707 raw = (u64 *)(iommu->ppr_log + head);
708
709 /*
710 * Hardware bug: Interrupt may arrive before the entry is
711 * written to memory. If this happens we need to wait for the
712 * entry to arrive.
713 */
714 for (i = 0; i < LOOP_TIMEOUT; ++i) {
715 if (PPR_REQ_TYPE(raw[0]) != 0)
716 break;
717 udelay(1);
718 }
719
720 /* Avoid memcpy function-call overhead */
721 entry[0] = raw[0];
722 entry[1] = raw[1];
723
724 /*
725 * To detect the hardware bug we need to clear the entry
726 * back to zero.
727 */
728 raw[0] = raw[1] = 0UL;
729
730 /* Update head pointer of hardware ring-buffer */
731 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
732 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
733
734 /* Handle PPR entry */
735 iommu_handle_ppr_entry(iommu, entry);
736
737 /* Refresh ring-buffer information */
738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740 }
741 }
742
743 #ifdef CONFIG_IRQ_REMAP
744 static int (*iommu_ga_log_notifier)(u32);
745
746 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
747 {
748 iommu_ga_log_notifier = notifier;
749
750 return 0;
751 }
752 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
753
754 static void iommu_poll_ga_log(struct amd_iommu *iommu)
755 {
756 u32 head, tail, cnt = 0;
757
758 if (iommu->ga_log == NULL)
759 return;
760
761 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
762 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
763
764 while (head != tail) {
765 volatile u64 *raw;
766 u64 log_entry;
767
768 raw = (u64 *)(iommu->ga_log + head);
769 cnt++;
770
771 /* Avoid memcpy function-call overhead */
772 log_entry = *raw;
773
774 /* Update head pointer of hardware ring-buffer */
775 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
776 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
777
778 /* Handle GA entry */
779 switch (GA_REQ_TYPE(log_entry)) {
780 case GA_GUEST_NR:
781 if (!iommu_ga_log_notifier)
782 break;
783
784 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
785 __func__, GA_DEVID(log_entry),
786 GA_TAG(log_entry));
787
788 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
789 pr_err("AMD-Vi: GA log notifier failed.\n");
790 break;
791 default:
792 break;
793 }
794 }
795 }
796 #endif /* CONFIG_IRQ_REMAP */
797
798 #define AMD_IOMMU_INT_MASK \
799 (MMIO_STATUS_EVT_INT_MASK | \
800 MMIO_STATUS_PPR_INT_MASK | \
801 MMIO_STATUS_GALOG_INT_MASK)
802
803 irqreturn_t amd_iommu_int_thread(int irq, void *data)
804 {
805 struct amd_iommu *iommu = (struct amd_iommu *) data;
806 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
807
808 while (status & AMD_IOMMU_INT_MASK) {
809 /* Enable EVT and PPR and GA interrupts again */
810 writel(AMD_IOMMU_INT_MASK,
811 iommu->mmio_base + MMIO_STATUS_OFFSET);
812
813 if (status & MMIO_STATUS_EVT_INT_MASK) {
814 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
815 iommu_poll_events(iommu);
816 }
817
818 if (status & MMIO_STATUS_PPR_INT_MASK) {
819 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
820 iommu_poll_ppr_log(iommu);
821 }
822
823 #ifdef CONFIG_IRQ_REMAP
824 if (status & MMIO_STATUS_GALOG_INT_MASK) {
825 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
826 iommu_poll_ga_log(iommu);
827 }
828 #endif
829
830 /*
831 * Hardware bug: ERBT1312
832 * When re-enabling interrupt (by writing 1
833 * to clear the bit), the hardware might also try to set
834 * the interrupt bit in the event status register.
835 * In this scenario, the bit will be set, and disable
836 * subsequent interrupts.
837 *
838 * Workaround: The IOMMU driver should read back the
839 * status register and check if the interrupt bits are cleared.
840 * If not, driver will need to go through the interrupt handler
841 * again and re-clear the bits
842 */
843 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
844 }
845 return IRQ_HANDLED;
846 }
847
848 irqreturn_t amd_iommu_int_handler(int irq, void *data)
849 {
850 return IRQ_WAKE_THREAD;
851 }
852
853 /****************************************************************************
854 *
855 * IOMMU command queuing functions
856 *
857 ****************************************************************************/
858
859 static int wait_on_sem(volatile u64 *sem)
860 {
861 int i = 0;
862
863 while (*sem == 0 && i < LOOP_TIMEOUT) {
864 udelay(1);
865 i += 1;
866 }
867
868 if (i == LOOP_TIMEOUT) {
869 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
870 return -EIO;
871 }
872
873 return 0;
874 }
875
876 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
877 struct iommu_cmd *cmd)
878 {
879 u8 *target;
880
881 target = iommu->cmd_buf + iommu->cmd_buf_tail;
882
883 iommu->cmd_buf_tail += sizeof(*cmd);
884 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
885
886 /* Copy command to buffer */
887 memcpy(target, cmd, sizeof(*cmd));
888
889 /* Tell the IOMMU about it */
890 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
891 }
892
893 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
894 {
895 WARN_ON(address & 0x7ULL);
896
897 memset(cmd, 0, sizeof(*cmd));
898 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
899 cmd->data[1] = upper_32_bits(__pa(address));
900 cmd->data[2] = 1;
901 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
902 }
903
904 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
905 {
906 memset(cmd, 0, sizeof(*cmd));
907 cmd->data[0] = devid;
908 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
909 }
910
911 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
912 size_t size, u16 domid, int pde)
913 {
914 u64 pages;
915 bool s;
916
917 pages = iommu_num_pages(address, size, PAGE_SIZE);
918 s = false;
919
920 if (pages > 1) {
921 /*
922 * If we have to flush more than one page, flush all
923 * TLB entries for this domain
924 */
925 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
926 s = true;
927 }
928
929 address &= PAGE_MASK;
930
931 memset(cmd, 0, sizeof(*cmd));
932 cmd->data[1] |= domid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
936 if (s) /* size bit - we flush more than one 4kb page */
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
940 }
941
942 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
943 u64 address, size_t size)
944 {
945 u64 pages;
946 bool s;
947
948 pages = iommu_num_pages(address, size, PAGE_SIZE);
949 s = false;
950
951 if (pages > 1) {
952 /*
953 * If we have to flush more than one page, flush all
954 * TLB entries for this domain
955 */
956 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
957 s = true;
958 }
959
960 address &= PAGE_MASK;
961
962 memset(cmd, 0, sizeof(*cmd));
963 cmd->data[0] = devid;
964 cmd->data[0] |= (qdep & 0xff) << 24;
965 cmd->data[1] = devid;
966 cmd->data[2] = lower_32_bits(address);
967 cmd->data[3] = upper_32_bits(address);
968 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
969 if (s)
970 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
971 }
972
973 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
974 u64 address, bool size)
975 {
976 memset(cmd, 0, sizeof(*cmd));
977
978 address &= ~(0xfffULL);
979
980 cmd->data[0] = pasid;
981 cmd->data[1] = domid;
982 cmd->data[2] = lower_32_bits(address);
983 cmd->data[3] = upper_32_bits(address);
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
985 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
986 if (size)
987 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
988 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
989 }
990
991 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
992 int qdep, u64 address, bool size)
993 {
994 memset(cmd, 0, sizeof(*cmd));
995
996 address &= ~(0xfffULL);
997
998 cmd->data[0] = devid;
999 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
1000 cmd->data[0] |= (qdep & 0xff) << 24;
1001 cmd->data[1] = devid;
1002 cmd->data[1] |= (pasid & 0xff) << 16;
1003 cmd->data[2] = lower_32_bits(address);
1004 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
1005 cmd->data[3] = upper_32_bits(address);
1006 if (size)
1007 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
1008 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
1009 }
1010
1011 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
1012 int status, int tag, bool gn)
1013 {
1014 memset(cmd, 0, sizeof(*cmd));
1015
1016 cmd->data[0] = devid;
1017 if (gn) {
1018 cmd->data[1] = pasid;
1019 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
1020 }
1021 cmd->data[3] = tag & 0x1ff;
1022 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1023
1024 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1025 }
1026
1027 static void build_inv_all(struct iommu_cmd *cmd)
1028 {
1029 memset(cmd, 0, sizeof(*cmd));
1030 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1031 }
1032
1033 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1034 {
1035 memset(cmd, 0, sizeof(*cmd));
1036 cmd->data[0] = devid;
1037 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1038 }
1039
1040 /*
1041 * Writes the command to the IOMMUs command buffer and informs the
1042 * hardware about the new command.
1043 */
1044 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1045 struct iommu_cmd *cmd,
1046 bool sync)
1047 {
1048 bool read_head = true;
1049 u32 left, next_tail;
1050
1051 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1052 again:
1053 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1054
1055 if (left <= 0x20) {
1056 struct iommu_cmd sync_cmd;
1057 int ret;
1058
1059 if (read_head) {
1060 /* Update head and recheck remaining space */
1061 iommu->cmd_buf_head = readl(iommu->mmio_base +
1062 MMIO_CMD_HEAD_OFFSET);
1063 read_head = false;
1064 goto again;
1065 }
1066
1067 read_head = true;
1068
1069 iommu->cmd_sem = 0;
1070
1071 build_completion_wait(&sync_cmd, (u64)&iommu->cmd_sem);
1072 copy_cmd_to_buffer(iommu, &sync_cmd);
1073
1074 if ((ret = wait_on_sem(&iommu->cmd_sem)) != 0)
1075 return ret;
1076
1077 goto again;
1078 }
1079
1080 copy_cmd_to_buffer(iommu, cmd);
1081
1082 /* We need to sync now to make sure all commands are processed */
1083 iommu->need_sync = sync;
1084
1085 return 0;
1086 }
1087
1088 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1089 struct iommu_cmd *cmd,
1090 bool sync)
1091 {
1092 unsigned long flags;
1093 int ret;
1094
1095 spin_lock_irqsave(&iommu->lock, flags);
1096 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1097 spin_unlock_irqrestore(&iommu->lock, flags);
1098
1099 return ret;
1100 }
1101
1102 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1103 {
1104 return iommu_queue_command_sync(iommu, cmd, true);
1105 }
1106
1107 /*
1108 * This function queues a completion wait command into the command
1109 * buffer of an IOMMU
1110 */
1111 static int iommu_completion_wait(struct amd_iommu *iommu)
1112 {
1113 struct iommu_cmd cmd;
1114 unsigned long flags;
1115 int ret;
1116
1117 if (!iommu->need_sync)
1118 return 0;
1119
1120
1121 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1122
1123 spin_lock_irqsave(&iommu->lock, flags);
1124
1125 iommu->cmd_sem = 0;
1126
1127 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1128 if (ret)
1129 goto out_unlock;
1130
1131 ret = wait_on_sem(&iommu->cmd_sem);
1132
1133 out_unlock:
1134 spin_unlock_irqrestore(&iommu->lock, flags);
1135
1136 return ret;
1137 }
1138
1139 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1140 {
1141 struct iommu_cmd cmd;
1142
1143 build_inv_dte(&cmd, devid);
1144
1145 return iommu_queue_command(iommu, &cmd);
1146 }
1147
1148 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1149 {
1150 u32 devid;
1151
1152 for (devid = 0; devid <= 0xffff; ++devid)
1153 iommu_flush_dte(iommu, devid);
1154
1155 iommu_completion_wait(iommu);
1156 }
1157
1158 /*
1159 * This function uses heavy locking and may disable irqs for some time. But
1160 * this is no issue because it is only called during resume.
1161 */
1162 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1163 {
1164 u32 dom_id;
1165
1166 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1167 struct iommu_cmd cmd;
1168 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1169 dom_id, 1);
1170 iommu_queue_command(iommu, &cmd);
1171 }
1172
1173 iommu_completion_wait(iommu);
1174 }
1175
1176 static void iommu_flush_all(struct amd_iommu *iommu)
1177 {
1178 struct iommu_cmd cmd;
1179
1180 build_inv_all(&cmd);
1181
1182 iommu_queue_command(iommu, &cmd);
1183 iommu_completion_wait(iommu);
1184 }
1185
1186 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1187 {
1188 struct iommu_cmd cmd;
1189
1190 build_inv_irt(&cmd, devid);
1191
1192 iommu_queue_command(iommu, &cmd);
1193 }
1194
1195 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1196 {
1197 u32 devid;
1198
1199 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1200 iommu_flush_irt(iommu, devid);
1201
1202 iommu_completion_wait(iommu);
1203 }
1204
1205 void iommu_flush_all_caches(struct amd_iommu *iommu)
1206 {
1207 if (iommu_feature(iommu, FEATURE_IA)) {
1208 iommu_flush_all(iommu);
1209 } else {
1210 iommu_flush_dte_all(iommu);
1211 iommu_flush_irt_all(iommu);
1212 iommu_flush_tlb_all(iommu);
1213 }
1214 }
1215
1216 /*
1217 * Command send function for flushing on-device TLB
1218 */
1219 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1220 u64 address, size_t size)
1221 {
1222 struct amd_iommu *iommu;
1223 struct iommu_cmd cmd;
1224 int qdep;
1225
1226 qdep = dev_data->ats.qdep;
1227 iommu = amd_iommu_rlookup_table[dev_data->devid];
1228
1229 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1230
1231 return iommu_queue_command(iommu, &cmd);
1232 }
1233
1234 /*
1235 * Command send function for invalidating a device table entry
1236 */
1237 static int device_flush_dte(struct iommu_dev_data *dev_data)
1238 {
1239 struct amd_iommu *iommu;
1240 u16 alias;
1241 int ret;
1242
1243 iommu = amd_iommu_rlookup_table[dev_data->devid];
1244 alias = dev_data->alias;
1245
1246 ret = iommu_flush_dte(iommu, dev_data->devid);
1247 if (!ret && alias != dev_data->devid)
1248 ret = iommu_flush_dte(iommu, alias);
1249 if (ret)
1250 return ret;
1251
1252 if (dev_data->ats.enabled)
1253 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1254
1255 return ret;
1256 }
1257
1258 /*
1259 * TLB invalidation function which is called from the mapping functions.
1260 * It invalidates a single PTE if the range to flush is within a single
1261 * page. Otherwise it flushes the whole TLB of the IOMMU.
1262 */
1263 static void __domain_flush_pages(struct protection_domain *domain,
1264 u64 address, size_t size, int pde)
1265 {
1266 struct iommu_dev_data *dev_data;
1267 struct iommu_cmd cmd;
1268 int ret = 0, i;
1269
1270 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1271
1272 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1273 if (!domain->dev_iommu[i])
1274 continue;
1275
1276 /*
1277 * Devices of this domain are behind this IOMMU
1278 * We need a TLB flush
1279 */
1280 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1281 }
1282
1283 list_for_each_entry(dev_data, &domain->dev_list, list) {
1284
1285 if (!dev_data->ats.enabled)
1286 continue;
1287
1288 ret |= device_flush_iotlb(dev_data, address, size);
1289 }
1290
1291 WARN_ON(ret);
1292 }
1293
1294 static void domain_flush_pages(struct protection_domain *domain,
1295 u64 address, size_t size)
1296 {
1297 __domain_flush_pages(domain, address, size, 0);
1298 }
1299
1300 /* Flush the whole IO/TLB for a given protection domain */
1301 static void domain_flush_tlb(struct protection_domain *domain)
1302 {
1303 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1304 }
1305
1306 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1307 static void domain_flush_tlb_pde(struct protection_domain *domain)
1308 {
1309 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1310 }
1311
1312 static void domain_flush_complete(struct protection_domain *domain)
1313 {
1314 int i;
1315
1316 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1317 if (domain && !domain->dev_iommu[i])
1318 continue;
1319
1320 /*
1321 * Devices of this domain are behind this IOMMU
1322 * We need to wait for completion of all commands.
1323 */
1324 iommu_completion_wait(amd_iommus[i]);
1325 }
1326 }
1327
1328
1329 /*
1330 * This function flushes the DTEs for all devices in domain
1331 */
1332 static void domain_flush_devices(struct protection_domain *domain)
1333 {
1334 struct iommu_dev_data *dev_data;
1335
1336 list_for_each_entry(dev_data, &domain->dev_list, list)
1337 device_flush_dte(dev_data);
1338 }
1339
1340 /****************************************************************************
1341 *
1342 * The functions below are used the create the page table mappings for
1343 * unity mapped regions.
1344 *
1345 ****************************************************************************/
1346
1347 /*
1348 * This function is used to add another level to an IO page table. Adding
1349 * another level increases the size of the address space by 9 bits to a size up
1350 * to 64 bits.
1351 */
1352 static bool increase_address_space(struct protection_domain *domain,
1353 gfp_t gfp)
1354 {
1355 u64 *pte;
1356
1357 if (domain->mode == PAGE_MODE_6_LEVEL)
1358 /* address space already 64 bit large */
1359 return false;
1360
1361 pte = (void *)get_zeroed_page(gfp);
1362 if (!pte)
1363 return false;
1364
1365 *pte = PM_LEVEL_PDE(domain->mode,
1366 virt_to_phys(domain->pt_root));
1367 domain->pt_root = pte;
1368 domain->mode += 1;
1369 domain->updated = true;
1370
1371 return true;
1372 }
1373
1374 static u64 *alloc_pte(struct protection_domain *domain,
1375 unsigned long address,
1376 unsigned long page_size,
1377 u64 **pte_page,
1378 gfp_t gfp)
1379 {
1380 int level, end_lvl;
1381 u64 *pte, *page;
1382
1383 BUG_ON(!is_power_of_2(page_size));
1384
1385 while (address > PM_LEVEL_SIZE(domain->mode))
1386 increase_address_space(domain, gfp);
1387
1388 level = domain->mode - 1;
1389 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1390 address = PAGE_SIZE_ALIGN(address, page_size);
1391 end_lvl = PAGE_SIZE_LEVEL(page_size);
1392
1393 while (level > end_lvl) {
1394 u64 __pte, __npte;
1395
1396 __pte = *pte;
1397
1398 if (!IOMMU_PTE_PRESENT(__pte)) {
1399 page = (u64 *)get_zeroed_page(gfp);
1400 if (!page)
1401 return NULL;
1402
1403 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1404
1405 /* pte could have been changed somewhere. */
1406 if (cmpxchg64(pte, __pte, __npte) != __pte) {
1407 free_page((unsigned long)page);
1408 continue;
1409 }
1410 }
1411
1412 /* No level skipping support yet */
1413 if (PM_PTE_LEVEL(*pte) != level)
1414 return NULL;
1415
1416 level -= 1;
1417
1418 pte = IOMMU_PTE_PAGE(*pte);
1419
1420 if (pte_page && level == end_lvl)
1421 *pte_page = pte;
1422
1423 pte = &pte[PM_LEVEL_INDEX(level, address)];
1424 }
1425
1426 return pte;
1427 }
1428
1429 /*
1430 * This function checks if there is a PTE for a given dma address. If
1431 * there is one, it returns the pointer to it.
1432 */
1433 static u64 *fetch_pte(struct protection_domain *domain,
1434 unsigned long address,
1435 unsigned long *page_size)
1436 {
1437 int level;
1438 u64 *pte;
1439
1440 if (address > PM_LEVEL_SIZE(domain->mode))
1441 return NULL;
1442
1443 level = domain->mode - 1;
1444 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1445 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1446
1447 while (level > 0) {
1448
1449 /* Not Present */
1450 if (!IOMMU_PTE_PRESENT(*pte))
1451 return NULL;
1452
1453 /* Large PTE */
1454 if (PM_PTE_LEVEL(*pte) == 7 ||
1455 PM_PTE_LEVEL(*pte) == 0)
1456 break;
1457
1458 /* No level skipping support yet */
1459 if (PM_PTE_LEVEL(*pte) != level)
1460 return NULL;
1461
1462 level -= 1;
1463
1464 /* Walk to the next level */
1465 pte = IOMMU_PTE_PAGE(*pte);
1466 pte = &pte[PM_LEVEL_INDEX(level, address)];
1467 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1468 }
1469
1470 if (PM_PTE_LEVEL(*pte) == 0x07) {
1471 unsigned long pte_mask;
1472
1473 /*
1474 * If we have a series of large PTEs, make
1475 * sure to return a pointer to the first one.
1476 */
1477 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1478 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1479 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1480 }
1481
1482 return pte;
1483 }
1484
1485 /*
1486 * Generic mapping functions. It maps a physical address into a DMA
1487 * address space. It allocates the page table pages if necessary.
1488 * In the future it can be extended to a generic mapping function
1489 * supporting all features of AMD IOMMU page tables like level skipping
1490 * and full 64 bit address spaces.
1491 */
1492 static int iommu_map_page(struct protection_domain *dom,
1493 unsigned long bus_addr,
1494 unsigned long phys_addr,
1495 unsigned long page_size,
1496 int prot,
1497 gfp_t gfp)
1498 {
1499 u64 __pte, *pte;
1500 int i, count;
1501
1502 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1503 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1504
1505 if (!(prot & IOMMU_PROT_MASK))
1506 return -EINVAL;
1507
1508 count = PAGE_SIZE_PTE_COUNT(page_size);
1509 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1510
1511 if (!pte)
1512 return -ENOMEM;
1513
1514 for (i = 0; i < count; ++i)
1515 if (IOMMU_PTE_PRESENT(pte[i]))
1516 return -EBUSY;
1517
1518 if (count > 1) {
1519 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1520 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1521 } else
1522 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1523
1524 if (prot & IOMMU_PROT_IR)
1525 __pte |= IOMMU_PTE_IR;
1526 if (prot & IOMMU_PROT_IW)
1527 __pte |= IOMMU_PTE_IW;
1528
1529 for (i = 0; i < count; ++i)
1530 pte[i] = __pte;
1531
1532 update_domain(dom);
1533
1534 return 0;
1535 }
1536
1537 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1538 unsigned long bus_addr,
1539 unsigned long page_size)
1540 {
1541 unsigned long long unmapped;
1542 unsigned long unmap_size;
1543 u64 *pte;
1544
1545 BUG_ON(!is_power_of_2(page_size));
1546
1547 unmapped = 0;
1548
1549 while (unmapped < page_size) {
1550
1551 pte = fetch_pte(dom, bus_addr, &unmap_size);
1552
1553 if (pte) {
1554 int i, count;
1555
1556 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1557 for (i = 0; i < count; i++)
1558 pte[i] = 0ULL;
1559 }
1560
1561 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1562 unmapped += unmap_size;
1563 }
1564
1565 BUG_ON(unmapped && !is_power_of_2(unmapped));
1566
1567 return unmapped;
1568 }
1569
1570 /****************************************************************************
1571 *
1572 * The next functions belong to the address allocator for the dma_ops
1573 * interface functions.
1574 *
1575 ****************************************************************************/
1576
1577
1578 static unsigned long dma_ops_alloc_iova(struct device *dev,
1579 struct dma_ops_domain *dma_dom,
1580 unsigned int pages, u64 dma_mask)
1581 {
1582 unsigned long pfn = 0;
1583
1584 pages = __roundup_pow_of_two(pages);
1585
1586 if (dma_mask > DMA_BIT_MASK(32))
1587 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1588 IOVA_PFN(DMA_BIT_MASK(32)));
1589
1590 if (!pfn)
1591 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1592
1593 return (pfn << PAGE_SHIFT);
1594 }
1595
1596 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1597 unsigned long address,
1598 unsigned int pages)
1599 {
1600 pages = __roundup_pow_of_two(pages);
1601 address >>= PAGE_SHIFT;
1602
1603 free_iova_fast(&dma_dom->iovad, address, pages);
1604 }
1605
1606 /****************************************************************************
1607 *
1608 * The next functions belong to the domain allocation. A domain is
1609 * allocated for every IOMMU as the default domain. If device isolation
1610 * is enabled, every device get its own domain. The most important thing
1611 * about domains is the page table mapping the DMA address space they
1612 * contain.
1613 *
1614 ****************************************************************************/
1615
1616 /*
1617 * This function adds a protection domain to the global protection domain list
1618 */
1619 static void add_domain_to_list(struct protection_domain *domain)
1620 {
1621 unsigned long flags;
1622
1623 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1624 list_add(&domain->list, &amd_iommu_pd_list);
1625 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1626 }
1627
1628 /*
1629 * This function removes a protection domain to the global
1630 * protection domain list
1631 */
1632 static void del_domain_from_list(struct protection_domain *domain)
1633 {
1634 unsigned long flags;
1635
1636 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1637 list_del(&domain->list);
1638 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1639 }
1640
1641 static u16 domain_id_alloc(void)
1642 {
1643 unsigned long flags;
1644 int id;
1645
1646 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1647 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1648 BUG_ON(id == 0);
1649 if (id > 0 && id < MAX_DOMAIN_ID)
1650 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1651 else
1652 id = 0;
1653 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1654
1655 return id;
1656 }
1657
1658 static void domain_id_free(int id)
1659 {
1660 unsigned long flags;
1661
1662 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1663 if (id > 0 && id < MAX_DOMAIN_ID)
1664 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1665 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1666 }
1667
1668 #define DEFINE_FREE_PT_FN(LVL, FN) \
1669 static void free_pt_##LVL (unsigned long __pt) \
1670 { \
1671 unsigned long p; \
1672 u64 *pt; \
1673 int i; \
1674 \
1675 pt = (u64 *)__pt; \
1676 \
1677 for (i = 0; i < 512; ++i) { \
1678 /* PTE present? */ \
1679 if (!IOMMU_PTE_PRESENT(pt[i])) \
1680 continue; \
1681 \
1682 /* Large PTE? */ \
1683 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1684 PM_PTE_LEVEL(pt[i]) == 7) \
1685 continue; \
1686 \
1687 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1688 FN(p); \
1689 } \
1690 free_page((unsigned long)pt); \
1691 }
1692
1693 DEFINE_FREE_PT_FN(l2, free_page)
1694 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1695 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1696 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1697 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1698
1699 static void free_pagetable(struct protection_domain *domain)
1700 {
1701 unsigned long root = (unsigned long)domain->pt_root;
1702
1703 switch (domain->mode) {
1704 case PAGE_MODE_NONE:
1705 break;
1706 case PAGE_MODE_1_LEVEL:
1707 free_page(root);
1708 break;
1709 case PAGE_MODE_2_LEVEL:
1710 free_pt_l2(root);
1711 break;
1712 case PAGE_MODE_3_LEVEL:
1713 free_pt_l3(root);
1714 break;
1715 case PAGE_MODE_4_LEVEL:
1716 free_pt_l4(root);
1717 break;
1718 case PAGE_MODE_5_LEVEL:
1719 free_pt_l5(root);
1720 break;
1721 case PAGE_MODE_6_LEVEL:
1722 free_pt_l6(root);
1723 break;
1724 default:
1725 BUG();
1726 }
1727 }
1728
1729 static void free_gcr3_tbl_level1(u64 *tbl)
1730 {
1731 u64 *ptr;
1732 int i;
1733
1734 for (i = 0; i < 512; ++i) {
1735 if (!(tbl[i] & GCR3_VALID))
1736 continue;
1737
1738 ptr = __va(tbl[i] & PAGE_MASK);
1739
1740 free_page((unsigned long)ptr);
1741 }
1742 }
1743
1744 static void free_gcr3_tbl_level2(u64 *tbl)
1745 {
1746 u64 *ptr;
1747 int i;
1748
1749 for (i = 0; i < 512; ++i) {
1750 if (!(tbl[i] & GCR3_VALID))
1751 continue;
1752
1753 ptr = __va(tbl[i] & PAGE_MASK);
1754
1755 free_gcr3_tbl_level1(ptr);
1756 }
1757 }
1758
1759 static void free_gcr3_table(struct protection_domain *domain)
1760 {
1761 if (domain->glx == 2)
1762 free_gcr3_tbl_level2(domain->gcr3_tbl);
1763 else if (domain->glx == 1)
1764 free_gcr3_tbl_level1(domain->gcr3_tbl);
1765 else
1766 BUG_ON(domain->glx != 0);
1767
1768 free_page((unsigned long)domain->gcr3_tbl);
1769 }
1770
1771 /*
1772 * Free a domain, only used if something went wrong in the
1773 * allocation path and we need to free an already allocated page table
1774 */
1775 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1776 {
1777 if (!dom)
1778 return;
1779
1780 del_domain_from_list(&dom->domain);
1781
1782 put_iova_domain(&dom->iovad);
1783
1784 free_pagetable(&dom->domain);
1785
1786 if (dom->domain.id)
1787 domain_id_free(dom->domain.id);
1788
1789 kfree(dom);
1790 }
1791
1792 /*
1793 * Allocates a new protection domain usable for the dma_ops functions.
1794 * It also initializes the page table and the address allocator data
1795 * structures required for the dma_ops interface
1796 */
1797 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1798 {
1799 struct dma_ops_domain *dma_dom;
1800
1801 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1802 if (!dma_dom)
1803 return NULL;
1804
1805 if (protection_domain_init(&dma_dom->domain))
1806 goto free_dma_dom;
1807
1808 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1809 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1810 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1811 if (!dma_dom->domain.pt_root)
1812 goto free_dma_dom;
1813
1814 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1815 IOVA_START_PFN, DMA_32BIT_PFN);
1816
1817 /* Initialize reserved ranges */
1818 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1819
1820 add_domain_to_list(&dma_dom->domain);
1821
1822 return dma_dom;
1823
1824 free_dma_dom:
1825 dma_ops_domain_free(dma_dom);
1826
1827 return NULL;
1828 }
1829
1830 /*
1831 * little helper function to check whether a given protection domain is a
1832 * dma_ops domain
1833 */
1834 static bool dma_ops_domain(struct protection_domain *domain)
1835 {
1836 return domain->flags & PD_DMA_OPS_MASK;
1837 }
1838
1839 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1840 {
1841 u64 pte_root = 0;
1842 u64 flags = 0;
1843
1844 if (domain->mode != PAGE_MODE_NONE)
1845 pte_root = virt_to_phys(domain->pt_root);
1846
1847 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1848 << DEV_ENTRY_MODE_SHIFT;
1849 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1850
1851 flags = amd_iommu_dev_table[devid].data[1];
1852
1853 if (ats)
1854 flags |= DTE_FLAG_IOTLB;
1855
1856 if (domain->flags & PD_IOMMUV2_MASK) {
1857 u64 gcr3 = __pa(domain->gcr3_tbl);
1858 u64 glx = domain->glx;
1859 u64 tmp;
1860
1861 pte_root |= DTE_FLAG_GV;
1862 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1863
1864 /* First mask out possible old values for GCR3 table */
1865 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1866 flags &= ~tmp;
1867
1868 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1869 flags &= ~tmp;
1870
1871 /* Encode GCR3 table into DTE */
1872 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1873 pte_root |= tmp;
1874
1875 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1876 flags |= tmp;
1877
1878 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1879 flags |= tmp;
1880 }
1881
1882 flags &= ~(0xffffUL);
1883 flags |= domain->id;
1884
1885 amd_iommu_dev_table[devid].data[1] = flags;
1886 amd_iommu_dev_table[devid].data[0] = pte_root;
1887 }
1888
1889 static void clear_dte_entry(u16 devid)
1890 {
1891 /* remove entry from the device table seen by the hardware */
1892 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1893 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1894
1895 amd_iommu_apply_erratum_63(devid);
1896 }
1897
1898 static void do_attach(struct iommu_dev_data *dev_data,
1899 struct protection_domain *domain)
1900 {
1901 struct amd_iommu *iommu;
1902 u16 alias;
1903 bool ats;
1904
1905 iommu = amd_iommu_rlookup_table[dev_data->devid];
1906 alias = dev_data->alias;
1907 ats = dev_data->ats.enabled;
1908
1909 /* Update data structures */
1910 dev_data->domain = domain;
1911 list_add(&dev_data->list, &domain->dev_list);
1912
1913 /* Do reference counting */
1914 domain->dev_iommu[iommu->index] += 1;
1915 domain->dev_cnt += 1;
1916
1917 /* Update device table */
1918 set_dte_entry(dev_data->devid, domain, ats);
1919 if (alias != dev_data->devid)
1920 set_dte_entry(alias, domain, ats);
1921
1922 device_flush_dte(dev_data);
1923 }
1924
1925 static void do_detach(struct iommu_dev_data *dev_data)
1926 {
1927 struct amd_iommu *iommu;
1928 u16 alias;
1929
1930 /*
1931 * First check if the device is still attached. It might already
1932 * be detached from its domain because the generic
1933 * iommu_detach_group code detached it and we try again here in
1934 * our alias handling.
1935 */
1936 if (!dev_data->domain)
1937 return;
1938
1939 iommu = amd_iommu_rlookup_table[dev_data->devid];
1940 alias = dev_data->alias;
1941
1942 /* decrease reference counters */
1943 dev_data->domain->dev_iommu[iommu->index] -= 1;
1944 dev_data->domain->dev_cnt -= 1;
1945
1946 /* Update data structures */
1947 dev_data->domain = NULL;
1948 list_del(&dev_data->list);
1949 clear_dte_entry(dev_data->devid);
1950 if (alias != dev_data->devid)
1951 clear_dte_entry(alias);
1952
1953 /* Flush the DTE entry */
1954 device_flush_dte(dev_data);
1955 }
1956
1957 /*
1958 * If a device is not yet associated with a domain, this function does
1959 * assigns it visible for the hardware
1960 */
1961 static int __attach_device(struct iommu_dev_data *dev_data,
1962 struct protection_domain *domain)
1963 {
1964 int ret;
1965
1966 /*
1967 * Must be called with IRQs disabled. Warn here to detect early
1968 * when its not.
1969 */
1970 WARN_ON(!irqs_disabled());
1971
1972 /* lock domain */
1973 spin_lock(&domain->lock);
1974
1975 ret = -EBUSY;
1976 if (dev_data->domain != NULL)
1977 goto out_unlock;
1978
1979 /* Attach alias group root */
1980 do_attach(dev_data, domain);
1981
1982 ret = 0;
1983
1984 out_unlock:
1985
1986 /* ready */
1987 spin_unlock(&domain->lock);
1988
1989 return ret;
1990 }
1991
1992
1993 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1994 {
1995 pci_disable_ats(pdev);
1996 pci_disable_pri(pdev);
1997 pci_disable_pasid(pdev);
1998 }
1999
2000 /* FIXME: Change generic reset-function to do the same */
2001 static int pri_reset_while_enabled(struct pci_dev *pdev)
2002 {
2003 u16 control;
2004 int pos;
2005
2006 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2007 if (!pos)
2008 return -EINVAL;
2009
2010 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2011 control |= PCI_PRI_CTRL_RESET;
2012 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2013
2014 return 0;
2015 }
2016
2017 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2018 {
2019 bool reset_enable;
2020 int reqs, ret;
2021
2022 /* FIXME: Hardcode number of outstanding requests for now */
2023 reqs = 32;
2024 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2025 reqs = 1;
2026 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2027
2028 /* Only allow access to user-accessible pages */
2029 ret = pci_enable_pasid(pdev, 0);
2030 if (ret)
2031 goto out_err;
2032
2033 /* First reset the PRI state of the device */
2034 ret = pci_reset_pri(pdev);
2035 if (ret)
2036 goto out_err;
2037
2038 /* Enable PRI */
2039 ret = pci_enable_pri(pdev, reqs);
2040 if (ret)
2041 goto out_err;
2042
2043 if (reset_enable) {
2044 ret = pri_reset_while_enabled(pdev);
2045 if (ret)
2046 goto out_err;
2047 }
2048
2049 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2050 if (ret)
2051 goto out_err;
2052
2053 return 0;
2054
2055 out_err:
2056 pci_disable_pri(pdev);
2057 pci_disable_pasid(pdev);
2058
2059 return ret;
2060 }
2061
2062 /* FIXME: Move this to PCI code */
2063 #define PCI_PRI_TLP_OFF (1 << 15)
2064
2065 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2066 {
2067 u16 status;
2068 int pos;
2069
2070 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2071 if (!pos)
2072 return false;
2073
2074 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2075
2076 return (status & PCI_PRI_TLP_OFF) ? true : false;
2077 }
2078
2079 /*
2080 * If a device is not yet associated with a domain, this function
2081 * assigns it visible for the hardware
2082 */
2083 static int attach_device(struct device *dev,
2084 struct protection_domain *domain)
2085 {
2086 struct pci_dev *pdev;
2087 struct iommu_dev_data *dev_data;
2088 unsigned long flags;
2089 int ret;
2090
2091 dev_data = get_dev_data(dev);
2092
2093 if (!dev_is_pci(dev))
2094 goto skip_ats_check;
2095
2096 pdev = to_pci_dev(dev);
2097 if (domain->flags & PD_IOMMUV2_MASK) {
2098 if (!dev_data->passthrough)
2099 return -EINVAL;
2100
2101 if (dev_data->iommu_v2) {
2102 if (pdev_iommuv2_enable(pdev) != 0)
2103 return -EINVAL;
2104
2105 dev_data->ats.enabled = true;
2106 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2107 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2108 }
2109 } else if (amd_iommu_iotlb_sup &&
2110 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2111 dev_data->ats.enabled = true;
2112 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2113 }
2114
2115 skip_ats_check:
2116 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2117 ret = __attach_device(dev_data, domain);
2118 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2119
2120 /*
2121 * We might boot into a crash-kernel here. The crashed kernel
2122 * left the caches in the IOMMU dirty. So we have to flush
2123 * here to evict all dirty stuff.
2124 */
2125 domain_flush_tlb_pde(domain);
2126
2127 return ret;
2128 }
2129
2130 /*
2131 * Removes a device from a protection domain (unlocked)
2132 */
2133 static void __detach_device(struct iommu_dev_data *dev_data)
2134 {
2135 struct protection_domain *domain;
2136
2137 /*
2138 * Must be called with IRQs disabled. Warn here to detect early
2139 * when its not.
2140 */
2141 WARN_ON(!irqs_disabled());
2142
2143 if (WARN_ON(!dev_data->domain))
2144 return;
2145
2146 domain = dev_data->domain;
2147
2148 spin_lock(&domain->lock);
2149
2150 do_detach(dev_data);
2151
2152 spin_unlock(&domain->lock);
2153 }
2154
2155 /*
2156 * Removes a device from a protection domain (with devtable_lock held)
2157 */
2158 static void detach_device(struct device *dev)
2159 {
2160 struct protection_domain *domain;
2161 struct iommu_dev_data *dev_data;
2162 unsigned long flags;
2163
2164 dev_data = get_dev_data(dev);
2165 domain = dev_data->domain;
2166
2167 /* lock device table */
2168 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2169 __detach_device(dev_data);
2170 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2171
2172 if (!dev_is_pci(dev))
2173 return;
2174
2175 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2176 pdev_iommuv2_disable(to_pci_dev(dev));
2177 else if (dev_data->ats.enabled)
2178 pci_disable_ats(to_pci_dev(dev));
2179
2180 dev_data->ats.enabled = false;
2181 }
2182
2183 static int amd_iommu_add_device(struct device *dev)
2184 {
2185 struct iommu_dev_data *dev_data;
2186 struct iommu_domain *domain;
2187 struct amd_iommu *iommu;
2188 int ret, devid;
2189
2190 if (!check_device(dev) || get_dev_data(dev))
2191 return 0;
2192
2193 devid = get_device_id(dev);
2194 if (devid < 0)
2195 return devid;
2196
2197 iommu = amd_iommu_rlookup_table[devid];
2198
2199 ret = iommu_init_device(dev);
2200 if (ret) {
2201 if (ret != -ENOTSUPP)
2202 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2203 dev_name(dev));
2204
2205 iommu_ignore_device(dev);
2206 dev->dma_ops = &nommu_dma_ops;
2207 goto out;
2208 }
2209 init_iommu_group(dev);
2210
2211 dev_data = get_dev_data(dev);
2212
2213 BUG_ON(!dev_data);
2214
2215 if (iommu_pass_through || dev_data->iommu_v2)
2216 iommu_request_dm_for_dev(dev);
2217
2218 /* Domains are initialized for this device - have a look what we ended up with */
2219 domain = iommu_get_domain_for_dev(dev);
2220 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2221 dev_data->passthrough = true;
2222 else
2223 dev->dma_ops = &amd_iommu_dma_ops;
2224
2225 out:
2226 iommu_completion_wait(iommu);
2227
2228 return 0;
2229 }
2230
2231 static void amd_iommu_remove_device(struct device *dev)
2232 {
2233 struct amd_iommu *iommu;
2234 int devid;
2235
2236 if (!check_device(dev))
2237 return;
2238
2239 devid = get_device_id(dev);
2240 if (devid < 0)
2241 return;
2242
2243 iommu = amd_iommu_rlookup_table[devid];
2244
2245 iommu_uninit_device(dev);
2246 iommu_completion_wait(iommu);
2247 }
2248
2249 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2250 {
2251 if (dev_is_pci(dev))
2252 return pci_device_group(dev);
2253
2254 return acpihid_device_group(dev);
2255 }
2256
2257 /*****************************************************************************
2258 *
2259 * The next functions belong to the dma_ops mapping/unmapping code.
2260 *
2261 *****************************************************************************/
2262
2263 static void __queue_flush(struct flush_queue *queue)
2264 {
2265 struct protection_domain *domain;
2266 unsigned long flags;
2267 int idx;
2268
2269 /* First flush TLB of all known domains */
2270 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2271 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2272 domain_flush_tlb(domain);
2273 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2274
2275 /* Wait until flushes have completed */
2276 domain_flush_complete(NULL);
2277
2278 for (idx = 0; idx < queue->next; ++idx) {
2279 struct flush_queue_entry *entry;
2280
2281 entry = queue->entries + idx;
2282
2283 free_iova_fast(&entry->dma_dom->iovad,
2284 entry->iova_pfn,
2285 entry->pages);
2286
2287 /* Not really necessary, just to make sure we catch any bugs */
2288 entry->dma_dom = NULL;
2289 }
2290
2291 queue->next = 0;
2292 }
2293
2294 static void queue_flush_all(void)
2295 {
2296 int cpu;
2297
2298 for_each_possible_cpu(cpu) {
2299 struct flush_queue *queue;
2300 unsigned long flags;
2301
2302 queue = per_cpu_ptr(&flush_queue, cpu);
2303 spin_lock_irqsave(&queue->lock, flags);
2304 if (queue->next > 0)
2305 __queue_flush(queue);
2306 spin_unlock_irqrestore(&queue->lock, flags);
2307 }
2308 }
2309
2310 static void queue_flush_timeout(unsigned long unsused)
2311 {
2312 atomic_set(&queue_timer_on, 0);
2313 queue_flush_all();
2314 }
2315
2316 static void queue_add(struct dma_ops_domain *dma_dom,
2317 unsigned long address, unsigned long pages)
2318 {
2319 struct flush_queue_entry *entry;
2320 struct flush_queue *queue;
2321 unsigned long flags;
2322 int idx;
2323
2324 pages = __roundup_pow_of_two(pages);
2325 address >>= PAGE_SHIFT;
2326
2327 queue = get_cpu_ptr(&flush_queue);
2328 spin_lock_irqsave(&queue->lock, flags);
2329
2330 if (queue->next == FLUSH_QUEUE_SIZE)
2331 __queue_flush(queue);
2332
2333 idx = queue->next++;
2334 entry = queue->entries + idx;
2335
2336 entry->iova_pfn = address;
2337 entry->pages = pages;
2338 entry->dma_dom = dma_dom;
2339
2340 spin_unlock_irqrestore(&queue->lock, flags);
2341
2342 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2343 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2344
2345 put_cpu_ptr(&flush_queue);
2346 }
2347
2348
2349 /*
2350 * In the dma_ops path we only have the struct device. This function
2351 * finds the corresponding IOMMU, the protection domain and the
2352 * requestor id for a given device.
2353 * If the device is not yet associated with a domain this is also done
2354 * in this function.
2355 */
2356 static struct protection_domain *get_domain(struct device *dev)
2357 {
2358 struct protection_domain *domain;
2359
2360 if (!check_device(dev))
2361 return ERR_PTR(-EINVAL);
2362
2363 domain = get_dev_data(dev)->domain;
2364 if (!dma_ops_domain(domain))
2365 return ERR_PTR(-EBUSY);
2366
2367 return domain;
2368 }
2369
2370 static void update_device_table(struct protection_domain *domain)
2371 {
2372 struct iommu_dev_data *dev_data;
2373
2374 list_for_each_entry(dev_data, &domain->dev_list, list) {
2375 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2376
2377 if (dev_data->devid == dev_data->alias)
2378 continue;
2379
2380 /* There is an alias, update device table entry for it */
2381 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2382 }
2383 }
2384
2385 static void update_domain(struct protection_domain *domain)
2386 {
2387 if (!domain->updated)
2388 return;
2389
2390 update_device_table(domain);
2391
2392 domain_flush_devices(domain);
2393 domain_flush_tlb_pde(domain);
2394
2395 domain->updated = false;
2396 }
2397
2398 static int dir2prot(enum dma_data_direction direction)
2399 {
2400 if (direction == DMA_TO_DEVICE)
2401 return IOMMU_PROT_IR;
2402 else if (direction == DMA_FROM_DEVICE)
2403 return IOMMU_PROT_IW;
2404 else if (direction == DMA_BIDIRECTIONAL)
2405 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2406 else
2407 return 0;
2408 }
2409 /*
2410 * This function contains common code for mapping of a physically
2411 * contiguous memory region into DMA address space. It is used by all
2412 * mapping functions provided with this IOMMU driver.
2413 * Must be called with the domain lock held.
2414 */
2415 static dma_addr_t __map_single(struct device *dev,
2416 struct dma_ops_domain *dma_dom,
2417 phys_addr_t paddr,
2418 size_t size,
2419 enum dma_data_direction direction,
2420 u64 dma_mask)
2421 {
2422 dma_addr_t offset = paddr & ~PAGE_MASK;
2423 dma_addr_t address, start, ret;
2424 unsigned int pages;
2425 int prot = 0;
2426 int i;
2427
2428 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2429 paddr &= PAGE_MASK;
2430
2431 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2432 if (address == DMA_ERROR_CODE)
2433 goto out;
2434
2435 prot = dir2prot(direction);
2436
2437 start = address;
2438 for (i = 0; i < pages; ++i) {
2439 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2440 PAGE_SIZE, prot, GFP_ATOMIC);
2441 if (ret)
2442 goto out_unmap;
2443
2444 paddr += PAGE_SIZE;
2445 start += PAGE_SIZE;
2446 }
2447 address += offset;
2448
2449 if (unlikely(amd_iommu_np_cache)) {
2450 domain_flush_pages(&dma_dom->domain, address, size);
2451 domain_flush_complete(&dma_dom->domain);
2452 }
2453
2454 out:
2455 return address;
2456
2457 out_unmap:
2458
2459 for (--i; i >= 0; --i) {
2460 start -= PAGE_SIZE;
2461 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2462 }
2463
2464 domain_flush_tlb(&dma_dom->domain);
2465 domain_flush_complete(&dma_dom->domain);
2466
2467 dma_ops_free_iova(dma_dom, address, pages);
2468
2469 return DMA_ERROR_CODE;
2470 }
2471
2472 /*
2473 * Does the reverse of the __map_single function. Must be called with
2474 * the domain lock held too
2475 */
2476 static void __unmap_single(struct dma_ops_domain *dma_dom,
2477 dma_addr_t dma_addr,
2478 size_t size,
2479 int dir)
2480 {
2481 dma_addr_t flush_addr;
2482 dma_addr_t i, start;
2483 unsigned int pages;
2484
2485 flush_addr = dma_addr;
2486 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2487 dma_addr &= PAGE_MASK;
2488 start = dma_addr;
2489
2490 for (i = 0; i < pages; ++i) {
2491 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2492 start += PAGE_SIZE;
2493 }
2494
2495 if (amd_iommu_unmap_flush) {
2496 dma_ops_free_iova(dma_dom, dma_addr, pages);
2497 domain_flush_tlb(&dma_dom->domain);
2498 domain_flush_complete(&dma_dom->domain);
2499 } else {
2500 queue_add(dma_dom, dma_addr, pages);
2501 }
2502 }
2503
2504 /*
2505 * The exported map_single function for dma_ops.
2506 */
2507 static dma_addr_t map_page(struct device *dev, struct page *page,
2508 unsigned long offset, size_t size,
2509 enum dma_data_direction dir,
2510 unsigned long attrs)
2511 {
2512 phys_addr_t paddr = page_to_phys(page) + offset;
2513 struct protection_domain *domain;
2514 struct dma_ops_domain *dma_dom;
2515 u64 dma_mask;
2516
2517 domain = get_domain(dev);
2518 if (PTR_ERR(domain) == -EINVAL)
2519 return (dma_addr_t)paddr;
2520 else if (IS_ERR(domain))
2521 return DMA_ERROR_CODE;
2522
2523 dma_mask = *dev->dma_mask;
2524 dma_dom = to_dma_ops_domain(domain);
2525
2526 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2527 }
2528
2529 /*
2530 * The exported unmap_single function for dma_ops.
2531 */
2532 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2533 enum dma_data_direction dir, unsigned long attrs)
2534 {
2535 struct protection_domain *domain;
2536 struct dma_ops_domain *dma_dom;
2537
2538 domain = get_domain(dev);
2539 if (IS_ERR(domain))
2540 return;
2541
2542 dma_dom = to_dma_ops_domain(domain);
2543
2544 __unmap_single(dma_dom, dma_addr, size, dir);
2545 }
2546
2547 static int sg_num_pages(struct device *dev,
2548 struct scatterlist *sglist,
2549 int nelems)
2550 {
2551 unsigned long mask, boundary_size;
2552 struct scatterlist *s;
2553 int i, npages = 0;
2554
2555 mask = dma_get_seg_boundary(dev);
2556 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2557 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2558
2559 for_each_sg(sglist, s, nelems, i) {
2560 int p, n;
2561
2562 s->dma_address = npages << PAGE_SHIFT;
2563 p = npages % boundary_size;
2564 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2565 if (p + n > boundary_size)
2566 npages += boundary_size - p;
2567 npages += n;
2568 }
2569
2570 return npages;
2571 }
2572
2573 /*
2574 * The exported map_sg function for dma_ops (handles scatter-gather
2575 * lists).
2576 */
2577 static int map_sg(struct device *dev, struct scatterlist *sglist,
2578 int nelems, enum dma_data_direction direction,
2579 unsigned long attrs)
2580 {
2581 int mapped_pages = 0, npages = 0, prot = 0, i;
2582 struct protection_domain *domain;
2583 struct dma_ops_domain *dma_dom;
2584 struct scatterlist *s;
2585 unsigned long address;
2586 u64 dma_mask;
2587
2588 domain = get_domain(dev);
2589 if (IS_ERR(domain))
2590 return 0;
2591
2592 dma_dom = to_dma_ops_domain(domain);
2593 dma_mask = *dev->dma_mask;
2594
2595 npages = sg_num_pages(dev, sglist, nelems);
2596
2597 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2598 if (address == DMA_ERROR_CODE)
2599 goto out_err;
2600
2601 prot = dir2prot(direction);
2602
2603 /* Map all sg entries */
2604 for_each_sg(sglist, s, nelems, i) {
2605 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2606
2607 for (j = 0; j < pages; ++j) {
2608 unsigned long bus_addr, phys_addr;
2609 int ret;
2610
2611 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2612 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2613 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2614 if (ret)
2615 goto out_unmap;
2616
2617 mapped_pages += 1;
2618 }
2619 }
2620
2621 /* Everything is mapped - write the right values into s->dma_address */
2622 for_each_sg(sglist, s, nelems, i) {
2623 s->dma_address += address + s->offset;
2624 s->dma_length = s->length;
2625 }
2626
2627 return nelems;
2628
2629 out_unmap:
2630 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2631 dev_name(dev), npages);
2632
2633 for_each_sg(sglist, s, nelems, i) {
2634 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2635
2636 for (j = 0; j < pages; ++j) {
2637 unsigned long bus_addr;
2638
2639 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2640 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2641
2642 if (--mapped_pages)
2643 goto out_free_iova;
2644 }
2645 }
2646
2647 out_free_iova:
2648 free_iova_fast(&dma_dom->iovad, address, npages);
2649
2650 out_err:
2651 return 0;
2652 }
2653
2654 /*
2655 * The exported map_sg function for dma_ops (handles scatter-gather
2656 * lists).
2657 */
2658 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2659 int nelems, enum dma_data_direction dir,
2660 unsigned long attrs)
2661 {
2662 struct protection_domain *domain;
2663 struct dma_ops_domain *dma_dom;
2664 unsigned long startaddr;
2665 int npages = 2;
2666
2667 domain = get_domain(dev);
2668 if (IS_ERR(domain))
2669 return;
2670
2671 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2672 dma_dom = to_dma_ops_domain(domain);
2673 npages = sg_num_pages(dev, sglist, nelems);
2674
2675 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2676 }
2677
2678 /*
2679 * The exported alloc_coherent function for dma_ops.
2680 */
2681 static void *alloc_coherent(struct device *dev, size_t size,
2682 dma_addr_t *dma_addr, gfp_t flag,
2683 unsigned long attrs)
2684 {
2685 u64 dma_mask = dev->coherent_dma_mask;
2686 struct protection_domain *domain;
2687 struct dma_ops_domain *dma_dom;
2688 struct page *page;
2689
2690 domain = get_domain(dev);
2691 if (PTR_ERR(domain) == -EINVAL) {
2692 page = alloc_pages(flag, get_order(size));
2693 *dma_addr = page_to_phys(page);
2694 return page_address(page);
2695 } else if (IS_ERR(domain))
2696 return NULL;
2697
2698 dma_dom = to_dma_ops_domain(domain);
2699 size = PAGE_ALIGN(size);
2700 dma_mask = dev->coherent_dma_mask;
2701 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2702 flag |= __GFP_ZERO;
2703
2704 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2705 if (!page) {
2706 if (!gfpflags_allow_blocking(flag))
2707 return NULL;
2708
2709 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2710 get_order(size), flag);
2711 if (!page)
2712 return NULL;
2713 }
2714
2715 if (!dma_mask)
2716 dma_mask = *dev->dma_mask;
2717
2718 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2719 size, DMA_BIDIRECTIONAL, dma_mask);
2720
2721 if (*dma_addr == DMA_ERROR_CODE)
2722 goto out_free;
2723
2724 return page_address(page);
2725
2726 out_free:
2727
2728 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2729 __free_pages(page, get_order(size));
2730
2731 return NULL;
2732 }
2733
2734 /*
2735 * The exported free_coherent function for dma_ops.
2736 */
2737 static void free_coherent(struct device *dev, size_t size,
2738 void *virt_addr, dma_addr_t dma_addr,
2739 unsigned long attrs)
2740 {
2741 struct protection_domain *domain;
2742 struct dma_ops_domain *dma_dom;
2743 struct page *page;
2744
2745 page = virt_to_page(virt_addr);
2746 size = PAGE_ALIGN(size);
2747
2748 domain = get_domain(dev);
2749 if (IS_ERR(domain))
2750 goto free_mem;
2751
2752 dma_dom = to_dma_ops_domain(domain);
2753
2754 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2755
2756 free_mem:
2757 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2758 __free_pages(page, get_order(size));
2759 }
2760
2761 /*
2762 * This function is called by the DMA layer to find out if we can handle a
2763 * particular device. It is part of the dma_ops.
2764 */
2765 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2766 {
2767 return check_device(dev);
2768 }
2769
2770 static const struct dma_map_ops amd_iommu_dma_ops = {
2771 .alloc = alloc_coherent,
2772 .free = free_coherent,
2773 .map_page = map_page,
2774 .unmap_page = unmap_page,
2775 .map_sg = map_sg,
2776 .unmap_sg = unmap_sg,
2777 .dma_supported = amd_iommu_dma_supported,
2778 };
2779
2780 static int init_reserved_iova_ranges(void)
2781 {
2782 struct pci_dev *pdev = NULL;
2783 struct iova *val;
2784
2785 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2786 IOVA_START_PFN, DMA_32BIT_PFN);
2787
2788 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2789 &reserved_rbtree_key);
2790
2791 /* MSI memory range */
2792 val = reserve_iova(&reserved_iova_ranges,
2793 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2794 if (!val) {
2795 pr_err("Reserving MSI range failed\n");
2796 return -ENOMEM;
2797 }
2798
2799 /* HT memory range */
2800 val = reserve_iova(&reserved_iova_ranges,
2801 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2802 if (!val) {
2803 pr_err("Reserving HT range failed\n");
2804 return -ENOMEM;
2805 }
2806
2807 /*
2808 * Memory used for PCI resources
2809 * FIXME: Check whether we can reserve the PCI-hole completly
2810 */
2811 for_each_pci_dev(pdev) {
2812 int i;
2813
2814 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2815 struct resource *r = &pdev->resource[i];
2816
2817 if (!(r->flags & IORESOURCE_MEM))
2818 continue;
2819
2820 val = reserve_iova(&reserved_iova_ranges,
2821 IOVA_PFN(r->start),
2822 IOVA_PFN(r->end));
2823 if (!val) {
2824 pr_err("Reserve pci-resource range failed\n");
2825 return -ENOMEM;
2826 }
2827 }
2828 }
2829
2830 return 0;
2831 }
2832
2833 int __init amd_iommu_init_api(void)
2834 {
2835 int ret, cpu, err = 0;
2836
2837 ret = iova_cache_get();
2838 if (ret)
2839 return ret;
2840
2841 ret = init_reserved_iova_ranges();
2842 if (ret)
2843 return ret;
2844
2845 for_each_possible_cpu(cpu) {
2846 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2847
2848 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2849 sizeof(*queue->entries),
2850 GFP_KERNEL);
2851 if (!queue->entries)
2852 goto out_put_iova;
2853
2854 spin_lock_init(&queue->lock);
2855 }
2856
2857 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2858 if (err)
2859 return err;
2860 #ifdef CONFIG_ARM_AMBA
2861 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2862 if (err)
2863 return err;
2864 #endif
2865 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2866 if (err)
2867 return err;
2868 return 0;
2869
2870 out_put_iova:
2871 for_each_possible_cpu(cpu) {
2872 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2873
2874 kfree(queue->entries);
2875 }
2876
2877 return -ENOMEM;
2878 }
2879
2880 int __init amd_iommu_init_dma_ops(void)
2881 {
2882 setup_timer(&queue_timer, queue_flush_timeout, 0);
2883 atomic_set(&queue_timer_on, 0);
2884
2885 swiotlb = iommu_pass_through ? 1 : 0;
2886 iommu_detected = 1;
2887
2888 /*
2889 * In case we don't initialize SWIOTLB (actually the common case
2890 * when AMD IOMMU is enabled), make sure there are global
2891 * dma_ops set as a fall-back for devices not handled by this
2892 * driver (for example non-PCI devices).
2893 */
2894 if (!swiotlb)
2895 dma_ops = &nommu_dma_ops;
2896
2897 if (amd_iommu_unmap_flush)
2898 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2899 else
2900 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2901
2902 return 0;
2903
2904 }
2905
2906 /*****************************************************************************
2907 *
2908 * The following functions belong to the exported interface of AMD IOMMU
2909 *
2910 * This interface allows access to lower level functions of the IOMMU
2911 * like protection domain handling and assignement of devices to domains
2912 * which is not possible with the dma_ops interface.
2913 *
2914 *****************************************************************************/
2915
2916 static void cleanup_domain(struct protection_domain *domain)
2917 {
2918 struct iommu_dev_data *entry;
2919 unsigned long flags;
2920
2921 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2922
2923 while (!list_empty(&domain->dev_list)) {
2924 entry = list_first_entry(&domain->dev_list,
2925 struct iommu_dev_data, list);
2926 __detach_device(entry);
2927 }
2928
2929 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2930 }
2931
2932 static void protection_domain_free(struct protection_domain *domain)
2933 {
2934 if (!domain)
2935 return;
2936
2937 del_domain_from_list(domain);
2938
2939 if (domain->id)
2940 domain_id_free(domain->id);
2941
2942 kfree(domain);
2943 }
2944
2945 static int protection_domain_init(struct protection_domain *domain)
2946 {
2947 spin_lock_init(&domain->lock);
2948 mutex_init(&domain->api_lock);
2949 domain->id = domain_id_alloc();
2950 if (!domain->id)
2951 return -ENOMEM;
2952 INIT_LIST_HEAD(&domain->dev_list);
2953
2954 return 0;
2955 }
2956
2957 static struct protection_domain *protection_domain_alloc(void)
2958 {
2959 struct protection_domain *domain;
2960
2961 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2962 if (!domain)
2963 return NULL;
2964
2965 if (protection_domain_init(domain))
2966 goto out_err;
2967
2968 add_domain_to_list(domain);
2969
2970 return domain;
2971
2972 out_err:
2973 kfree(domain);
2974
2975 return NULL;
2976 }
2977
2978 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2979 {
2980 struct protection_domain *pdomain;
2981 struct dma_ops_domain *dma_domain;
2982
2983 switch (type) {
2984 case IOMMU_DOMAIN_UNMANAGED:
2985 pdomain = protection_domain_alloc();
2986 if (!pdomain)
2987 return NULL;
2988
2989 pdomain->mode = PAGE_MODE_3_LEVEL;
2990 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2991 if (!pdomain->pt_root) {
2992 protection_domain_free(pdomain);
2993 return NULL;
2994 }
2995
2996 pdomain->domain.geometry.aperture_start = 0;
2997 pdomain->domain.geometry.aperture_end = ~0ULL;
2998 pdomain->domain.geometry.force_aperture = true;
2999
3000 break;
3001 case IOMMU_DOMAIN_DMA:
3002 dma_domain = dma_ops_domain_alloc();
3003 if (!dma_domain) {
3004 pr_err("AMD-Vi: Failed to allocate\n");
3005 return NULL;
3006 }
3007 pdomain = &dma_domain->domain;
3008 break;
3009 case IOMMU_DOMAIN_IDENTITY:
3010 pdomain = protection_domain_alloc();
3011 if (!pdomain)
3012 return NULL;
3013
3014 pdomain->mode = PAGE_MODE_NONE;
3015 break;
3016 default:
3017 return NULL;
3018 }
3019
3020 return &pdomain->domain;
3021 }
3022
3023 static void amd_iommu_domain_free(struct iommu_domain *dom)
3024 {
3025 struct protection_domain *domain;
3026 struct dma_ops_domain *dma_dom;
3027
3028 domain = to_pdomain(dom);
3029
3030 if (domain->dev_cnt > 0)
3031 cleanup_domain(domain);
3032
3033 BUG_ON(domain->dev_cnt != 0);
3034
3035 if (!dom)
3036 return;
3037
3038 switch (dom->type) {
3039 case IOMMU_DOMAIN_DMA:
3040 /*
3041 * First make sure the domain is no longer referenced from the
3042 * flush queue
3043 */
3044 queue_flush_all();
3045
3046 /* Now release the domain */
3047 dma_dom = to_dma_ops_domain(domain);
3048 dma_ops_domain_free(dma_dom);
3049 break;
3050 default:
3051 if (domain->mode != PAGE_MODE_NONE)
3052 free_pagetable(domain);
3053
3054 if (domain->flags & PD_IOMMUV2_MASK)
3055 free_gcr3_table(domain);
3056
3057 protection_domain_free(domain);
3058 break;
3059 }
3060 }
3061
3062 static void amd_iommu_detach_device(struct iommu_domain *dom,
3063 struct device *dev)
3064 {
3065 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3066 struct amd_iommu *iommu;
3067 int devid;
3068
3069 if (!check_device(dev))
3070 return;
3071
3072 devid = get_device_id(dev);
3073 if (devid < 0)
3074 return;
3075
3076 if (dev_data->domain != NULL)
3077 detach_device(dev);
3078
3079 iommu = amd_iommu_rlookup_table[devid];
3080 if (!iommu)
3081 return;
3082
3083 #ifdef CONFIG_IRQ_REMAP
3084 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3085 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3086 dev_data->use_vapic = 0;
3087 #endif
3088
3089 iommu_completion_wait(iommu);
3090 }
3091
3092 static int amd_iommu_attach_device(struct iommu_domain *dom,
3093 struct device *dev)
3094 {
3095 struct protection_domain *domain = to_pdomain(dom);
3096 struct iommu_dev_data *dev_data;
3097 struct amd_iommu *iommu;
3098 int ret;
3099
3100 if (!check_device(dev))
3101 return -EINVAL;
3102
3103 dev_data = dev->archdata.iommu;
3104
3105 iommu = amd_iommu_rlookup_table[dev_data->devid];
3106 if (!iommu)
3107 return -EINVAL;
3108
3109 if (dev_data->domain)
3110 detach_device(dev);
3111
3112 ret = attach_device(dev, domain);
3113
3114 #ifdef CONFIG_IRQ_REMAP
3115 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3116 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3117 dev_data->use_vapic = 1;
3118 else
3119 dev_data->use_vapic = 0;
3120 }
3121 #endif
3122
3123 iommu_completion_wait(iommu);
3124
3125 return ret;
3126 }
3127
3128 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3129 phys_addr_t paddr, size_t page_size, int iommu_prot)
3130 {
3131 struct protection_domain *domain = to_pdomain(dom);
3132 int prot = 0;
3133 int ret;
3134
3135 if (domain->mode == PAGE_MODE_NONE)
3136 return -EINVAL;
3137
3138 if (iommu_prot & IOMMU_READ)
3139 prot |= IOMMU_PROT_IR;
3140 if (iommu_prot & IOMMU_WRITE)
3141 prot |= IOMMU_PROT_IW;
3142
3143 mutex_lock(&domain->api_lock);
3144 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3145 mutex_unlock(&domain->api_lock);
3146
3147 return ret;
3148 }
3149
3150 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3151 size_t page_size)
3152 {
3153 struct protection_domain *domain = to_pdomain(dom);
3154 size_t unmap_size;
3155
3156 if (domain->mode == PAGE_MODE_NONE)
3157 return -EINVAL;
3158
3159 mutex_lock(&domain->api_lock);
3160 unmap_size = iommu_unmap_page(domain, iova, page_size);
3161 mutex_unlock(&domain->api_lock);
3162
3163 domain_flush_tlb_pde(domain);
3164
3165 return unmap_size;
3166 }
3167
3168 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3169 dma_addr_t iova)
3170 {
3171 struct protection_domain *domain = to_pdomain(dom);
3172 unsigned long offset_mask, pte_pgsize;
3173 u64 *pte, __pte;
3174
3175 if (domain->mode == PAGE_MODE_NONE)
3176 return iova;
3177
3178 pte = fetch_pte(domain, iova, &pte_pgsize);
3179
3180 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3181 return 0;
3182
3183 offset_mask = pte_pgsize - 1;
3184 __pte = *pte & PM_ADDR_MASK;
3185
3186 return (__pte & ~offset_mask) | (iova & offset_mask);
3187 }
3188
3189 static bool amd_iommu_capable(enum iommu_cap cap)
3190 {
3191 switch (cap) {
3192 case IOMMU_CAP_CACHE_COHERENCY:
3193 return true;
3194 case IOMMU_CAP_INTR_REMAP:
3195 return (irq_remapping_enabled == 1);
3196 case IOMMU_CAP_NOEXEC:
3197 return false;
3198 }
3199
3200 return false;
3201 }
3202
3203 static void amd_iommu_get_resv_regions(struct device *dev,
3204 struct list_head *head)
3205 {
3206 struct iommu_resv_region *region;
3207 struct unity_map_entry *entry;
3208 int devid;
3209
3210 devid = get_device_id(dev);
3211 if (devid < 0)
3212 return;
3213
3214 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3215 size_t length;
3216 int prot = 0;
3217
3218 if (devid < entry->devid_start || devid > entry->devid_end)
3219 continue;
3220
3221 length = entry->address_end - entry->address_start;
3222 if (entry->prot & IOMMU_PROT_IR)
3223 prot |= IOMMU_READ;
3224 if (entry->prot & IOMMU_PROT_IW)
3225 prot |= IOMMU_WRITE;
3226
3227 region = iommu_alloc_resv_region(entry->address_start,
3228 length, prot,
3229 IOMMU_RESV_DIRECT);
3230 if (!region) {
3231 pr_err("Out of memory allocating dm-regions for %s\n",
3232 dev_name(dev));
3233 return;
3234 }
3235 list_add_tail(&region->list, head);
3236 }
3237
3238 region = iommu_alloc_resv_region(MSI_RANGE_START,
3239 MSI_RANGE_END - MSI_RANGE_START + 1,
3240 0, IOMMU_RESV_MSI);
3241 if (!region)
3242 return;
3243 list_add_tail(&region->list, head);
3244
3245 region = iommu_alloc_resv_region(HT_RANGE_START,
3246 HT_RANGE_END - HT_RANGE_START + 1,
3247 0, IOMMU_RESV_RESERVED);
3248 if (!region)
3249 return;
3250 list_add_tail(&region->list, head);
3251 }
3252
3253 static void amd_iommu_put_resv_regions(struct device *dev,
3254 struct list_head *head)
3255 {
3256 struct iommu_resv_region *entry, *next;
3257
3258 list_for_each_entry_safe(entry, next, head, list)
3259 kfree(entry);
3260 }
3261
3262 static void amd_iommu_apply_resv_region(struct device *dev,
3263 struct iommu_domain *domain,
3264 struct iommu_resv_region *region)
3265 {
3266 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3267 unsigned long start, end;
3268
3269 start = IOVA_PFN(region->start);
3270 end = IOVA_PFN(region->start + region->length);
3271
3272 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3273 }
3274
3275 const struct iommu_ops amd_iommu_ops = {
3276 .capable = amd_iommu_capable,
3277 .domain_alloc = amd_iommu_domain_alloc,
3278 .domain_free = amd_iommu_domain_free,
3279 .attach_dev = amd_iommu_attach_device,
3280 .detach_dev = amd_iommu_detach_device,
3281 .map = amd_iommu_map,
3282 .unmap = amd_iommu_unmap,
3283 .map_sg = default_iommu_map_sg,
3284 .iova_to_phys = amd_iommu_iova_to_phys,
3285 .add_device = amd_iommu_add_device,
3286 .remove_device = amd_iommu_remove_device,
3287 .device_group = amd_iommu_device_group,
3288 .get_resv_regions = amd_iommu_get_resv_regions,
3289 .put_resv_regions = amd_iommu_put_resv_regions,
3290 .apply_resv_region = amd_iommu_apply_resv_region,
3291 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3292 };
3293
3294 /*****************************************************************************
3295 *
3296 * The next functions do a basic initialization of IOMMU for pass through
3297 * mode
3298 *
3299 * In passthrough mode the IOMMU is initialized and enabled but not used for
3300 * DMA-API translation.
3301 *
3302 *****************************************************************************/
3303
3304 /* IOMMUv2 specific functions */
3305 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3306 {
3307 return atomic_notifier_chain_register(&ppr_notifier, nb);
3308 }
3309 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3310
3311 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3312 {
3313 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3314 }
3315 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3316
3317 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3318 {
3319 struct protection_domain *domain = to_pdomain(dom);
3320 unsigned long flags;
3321
3322 spin_lock_irqsave(&domain->lock, flags);
3323
3324 /* Update data structure */
3325 domain->mode = PAGE_MODE_NONE;
3326 domain->updated = true;
3327
3328 /* Make changes visible to IOMMUs */
3329 update_domain(domain);
3330
3331 /* Page-table is not visible to IOMMU anymore, so free it */
3332 free_pagetable(domain);
3333
3334 spin_unlock_irqrestore(&domain->lock, flags);
3335 }
3336 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3337
3338 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3339 {
3340 struct protection_domain *domain = to_pdomain(dom);
3341 unsigned long flags;
3342 int levels, ret;
3343
3344 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3345 return -EINVAL;
3346
3347 /* Number of GCR3 table levels required */
3348 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3349 levels += 1;
3350
3351 if (levels > amd_iommu_max_glx_val)
3352 return -EINVAL;
3353
3354 spin_lock_irqsave(&domain->lock, flags);
3355
3356 /*
3357 * Save us all sanity checks whether devices already in the
3358 * domain support IOMMUv2. Just force that the domain has no
3359 * devices attached when it is switched into IOMMUv2 mode.
3360 */
3361 ret = -EBUSY;
3362 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3363 goto out;
3364
3365 ret = -ENOMEM;
3366 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3367 if (domain->gcr3_tbl == NULL)
3368 goto out;
3369
3370 domain->glx = levels;
3371 domain->flags |= PD_IOMMUV2_MASK;
3372 domain->updated = true;
3373
3374 update_domain(domain);
3375
3376 ret = 0;
3377
3378 out:
3379 spin_unlock_irqrestore(&domain->lock, flags);
3380
3381 return ret;
3382 }
3383 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3384
3385 static int __flush_pasid(struct protection_domain *domain, int pasid,
3386 u64 address, bool size)
3387 {
3388 struct iommu_dev_data *dev_data;
3389 struct iommu_cmd cmd;
3390 int i, ret;
3391
3392 if (!(domain->flags & PD_IOMMUV2_MASK))
3393 return -EINVAL;
3394
3395 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3396
3397 /*
3398 * IOMMU TLB needs to be flushed before Device TLB to
3399 * prevent device TLB refill from IOMMU TLB
3400 */
3401 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3402 if (domain->dev_iommu[i] == 0)
3403 continue;
3404
3405 ret = iommu_queue_command(amd_iommus[i], &cmd);
3406 if (ret != 0)
3407 goto out;
3408 }
3409
3410 /* Wait until IOMMU TLB flushes are complete */
3411 domain_flush_complete(domain);
3412
3413 /* Now flush device TLBs */
3414 list_for_each_entry(dev_data, &domain->dev_list, list) {
3415 struct amd_iommu *iommu;
3416 int qdep;
3417
3418 /*
3419 There might be non-IOMMUv2 capable devices in an IOMMUv2
3420 * domain.
3421 */
3422 if (!dev_data->ats.enabled)
3423 continue;
3424
3425 qdep = dev_data->ats.qdep;
3426 iommu = amd_iommu_rlookup_table[dev_data->devid];
3427
3428 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3429 qdep, address, size);
3430
3431 ret = iommu_queue_command(iommu, &cmd);
3432 if (ret != 0)
3433 goto out;
3434 }
3435
3436 /* Wait until all device TLBs are flushed */
3437 domain_flush_complete(domain);
3438
3439 ret = 0;
3440
3441 out:
3442
3443 return ret;
3444 }
3445
3446 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3447 u64 address)
3448 {
3449 return __flush_pasid(domain, pasid, address, false);
3450 }
3451
3452 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3453 u64 address)
3454 {
3455 struct protection_domain *domain = to_pdomain(dom);
3456 unsigned long flags;
3457 int ret;
3458
3459 spin_lock_irqsave(&domain->lock, flags);
3460 ret = __amd_iommu_flush_page(domain, pasid, address);
3461 spin_unlock_irqrestore(&domain->lock, flags);
3462
3463 return ret;
3464 }
3465 EXPORT_SYMBOL(amd_iommu_flush_page);
3466
3467 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3468 {
3469 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3470 true);
3471 }
3472
3473 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3474 {
3475 struct protection_domain *domain = to_pdomain(dom);
3476 unsigned long flags;
3477 int ret;
3478
3479 spin_lock_irqsave(&domain->lock, flags);
3480 ret = __amd_iommu_flush_tlb(domain, pasid);
3481 spin_unlock_irqrestore(&domain->lock, flags);
3482
3483 return ret;
3484 }
3485 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3486
3487 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3488 {
3489 int index;
3490 u64 *pte;
3491
3492 while (true) {
3493
3494 index = (pasid >> (9 * level)) & 0x1ff;
3495 pte = &root[index];
3496
3497 if (level == 0)
3498 break;
3499
3500 if (!(*pte & GCR3_VALID)) {
3501 if (!alloc)
3502 return NULL;
3503
3504 root = (void *)get_zeroed_page(GFP_ATOMIC);
3505 if (root == NULL)
3506 return NULL;
3507
3508 *pte = __pa(root) | GCR3_VALID;
3509 }
3510
3511 root = __va(*pte & PAGE_MASK);
3512
3513 level -= 1;
3514 }
3515
3516 return pte;
3517 }
3518
3519 static int __set_gcr3(struct protection_domain *domain, int pasid,
3520 unsigned long cr3)
3521 {
3522 u64 *pte;
3523
3524 if (domain->mode != PAGE_MODE_NONE)
3525 return -EINVAL;
3526
3527 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3528 if (pte == NULL)
3529 return -ENOMEM;
3530
3531 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3532
3533 return __amd_iommu_flush_tlb(domain, pasid);
3534 }
3535
3536 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3537 {
3538 u64 *pte;
3539
3540 if (domain->mode != PAGE_MODE_NONE)
3541 return -EINVAL;
3542
3543 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3544 if (pte == NULL)
3545 return 0;
3546
3547 *pte = 0;
3548
3549 return __amd_iommu_flush_tlb(domain, pasid);
3550 }
3551
3552 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3553 unsigned long cr3)
3554 {
3555 struct protection_domain *domain = to_pdomain(dom);
3556 unsigned long flags;
3557 int ret;
3558
3559 spin_lock_irqsave(&domain->lock, flags);
3560 ret = __set_gcr3(domain, pasid, cr3);
3561 spin_unlock_irqrestore(&domain->lock, flags);
3562
3563 return ret;
3564 }
3565 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3566
3567 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3568 {
3569 struct protection_domain *domain = to_pdomain(dom);
3570 unsigned long flags;
3571 int ret;
3572
3573 spin_lock_irqsave(&domain->lock, flags);
3574 ret = __clear_gcr3(domain, pasid);
3575 spin_unlock_irqrestore(&domain->lock, flags);
3576
3577 return ret;
3578 }
3579 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3580
3581 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3582 int status, int tag)
3583 {
3584 struct iommu_dev_data *dev_data;
3585 struct amd_iommu *iommu;
3586 struct iommu_cmd cmd;
3587
3588 dev_data = get_dev_data(&pdev->dev);
3589 iommu = amd_iommu_rlookup_table[dev_data->devid];
3590
3591 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3592 tag, dev_data->pri_tlp);
3593
3594 return iommu_queue_command(iommu, &cmd);
3595 }
3596 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3597
3598 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3599 {
3600 struct protection_domain *pdomain;
3601
3602 pdomain = get_domain(&pdev->dev);
3603 if (IS_ERR(pdomain))
3604 return NULL;
3605
3606 /* Only return IOMMUv2 domains */
3607 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3608 return NULL;
3609
3610 return &pdomain->domain;
3611 }
3612 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3613
3614 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3615 {
3616 struct iommu_dev_data *dev_data;
3617
3618 if (!amd_iommu_v2_supported())
3619 return;
3620
3621 dev_data = get_dev_data(&pdev->dev);
3622 dev_data->errata |= (1 << erratum);
3623 }
3624 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3625
3626 int amd_iommu_device_info(struct pci_dev *pdev,
3627 struct amd_iommu_device_info *info)
3628 {
3629 int max_pasids;
3630 int pos;
3631
3632 if (pdev == NULL || info == NULL)
3633 return -EINVAL;
3634
3635 if (!amd_iommu_v2_supported())
3636 return -EINVAL;
3637
3638 memset(info, 0, sizeof(*info));
3639
3640 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3641 if (pos)
3642 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3643
3644 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3645 if (pos)
3646 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3647
3648 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3649 if (pos) {
3650 int features;
3651
3652 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3653 max_pasids = min(max_pasids, (1 << 20));
3654
3655 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3656 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3657
3658 features = pci_pasid_features(pdev);
3659 if (features & PCI_PASID_CAP_EXEC)
3660 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3661 if (features & PCI_PASID_CAP_PRIV)
3662 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3663 }
3664
3665 return 0;
3666 }
3667 EXPORT_SYMBOL(amd_iommu_device_info);
3668
3669 #ifdef CONFIG_IRQ_REMAP
3670
3671 /*****************************************************************************
3672 *
3673 * Interrupt Remapping Implementation
3674 *
3675 *****************************************************************************/
3676
3677 static struct irq_chip amd_ir_chip;
3678
3679 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3680 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3681 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3682 #define DTE_IRQ_REMAP_ENABLE 1ULL
3683
3684 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3685 {
3686 u64 dte;
3687
3688 dte = amd_iommu_dev_table[devid].data[2];
3689 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3690 dte |= virt_to_phys(table->table);
3691 dte |= DTE_IRQ_REMAP_INTCTL;
3692 dte |= DTE_IRQ_TABLE_LEN;
3693 dte |= DTE_IRQ_REMAP_ENABLE;
3694
3695 amd_iommu_dev_table[devid].data[2] = dte;
3696 }
3697
3698 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3699 {
3700 struct irq_remap_table *table = NULL;
3701 struct amd_iommu *iommu;
3702 unsigned long flags;
3703 u16 alias;
3704
3705 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3706
3707 iommu = amd_iommu_rlookup_table[devid];
3708 if (!iommu)
3709 goto out_unlock;
3710
3711 table = irq_lookup_table[devid];
3712 if (table)
3713 goto out_unlock;
3714
3715 alias = amd_iommu_alias_table[devid];
3716 table = irq_lookup_table[alias];
3717 if (table) {
3718 irq_lookup_table[devid] = table;
3719 set_dte_irq_entry(devid, table);
3720 iommu_flush_dte(iommu, devid);
3721 goto out;
3722 }
3723
3724 /* Nothing there yet, allocate new irq remapping table */
3725 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3726 if (!table)
3727 goto out_unlock;
3728
3729 /* Initialize table spin-lock */
3730 spin_lock_init(&table->lock);
3731
3732 if (ioapic)
3733 /* Keep the first 32 indexes free for IOAPIC interrupts */
3734 table->min_index = 32;
3735
3736 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3737 if (!table->table) {
3738 kfree(table);
3739 table = NULL;
3740 goto out_unlock;
3741 }
3742
3743 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3744 memset(table->table, 0,
3745 MAX_IRQS_PER_TABLE * sizeof(u32));
3746 else
3747 memset(table->table, 0,
3748 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3749
3750 if (ioapic) {
3751 int i;
3752
3753 for (i = 0; i < 32; ++i)
3754 iommu->irte_ops->set_allocated(table, i);
3755 }
3756
3757 irq_lookup_table[devid] = table;
3758 set_dte_irq_entry(devid, table);
3759 iommu_flush_dte(iommu, devid);
3760 if (devid != alias) {
3761 irq_lookup_table[alias] = table;
3762 set_dte_irq_entry(alias, table);
3763 iommu_flush_dte(iommu, alias);
3764 }
3765
3766 out:
3767 iommu_completion_wait(iommu);
3768
3769 out_unlock:
3770 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3771
3772 return table;
3773 }
3774
3775 static int alloc_irq_index(u16 devid, int count)
3776 {
3777 struct irq_remap_table *table;
3778 unsigned long flags;
3779 int index, c;
3780 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3781
3782 if (!iommu)
3783 return -ENODEV;
3784
3785 table = get_irq_table(devid, false);
3786 if (!table)
3787 return -ENODEV;
3788
3789 spin_lock_irqsave(&table->lock, flags);
3790
3791 /* Scan table for free entries */
3792 for (c = 0, index = table->min_index;
3793 index < MAX_IRQS_PER_TABLE;
3794 ++index) {
3795 if (!iommu->irte_ops->is_allocated(table, index))
3796 c += 1;
3797 else
3798 c = 0;
3799
3800 if (c == count) {
3801 for (; c != 0; --c)
3802 iommu->irte_ops->set_allocated(table, index - c + 1);
3803
3804 index -= count - 1;
3805 goto out;
3806 }
3807 }
3808
3809 index = -ENOSPC;
3810
3811 out:
3812 spin_unlock_irqrestore(&table->lock, flags);
3813
3814 return index;
3815 }
3816
3817 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3818 struct amd_ir_data *data)
3819 {
3820 struct irq_remap_table *table;
3821 struct amd_iommu *iommu;
3822 unsigned long flags;
3823 struct irte_ga *entry;
3824
3825 iommu = amd_iommu_rlookup_table[devid];
3826 if (iommu == NULL)
3827 return -EINVAL;
3828
3829 table = get_irq_table(devid, false);
3830 if (!table)
3831 return -ENOMEM;
3832
3833 spin_lock_irqsave(&table->lock, flags);
3834
3835 entry = (struct irte_ga *)table->table;
3836 entry = &entry[index];
3837 entry->lo.fields_remap.valid = 0;
3838 entry->hi.val = irte->hi.val;
3839 entry->lo.val = irte->lo.val;
3840 entry->lo.fields_remap.valid = 1;
3841 if (data)
3842 data->ref = entry;
3843
3844 spin_unlock_irqrestore(&table->lock, flags);
3845
3846 iommu_flush_irt(iommu, devid);
3847 iommu_completion_wait(iommu);
3848
3849 return 0;
3850 }
3851
3852 static int modify_irte(u16 devid, int index, union irte *irte)
3853 {
3854 struct irq_remap_table *table;
3855 struct amd_iommu *iommu;
3856 unsigned long flags;
3857
3858 iommu = amd_iommu_rlookup_table[devid];
3859 if (iommu == NULL)
3860 return -EINVAL;
3861
3862 table = get_irq_table(devid, false);
3863 if (!table)
3864 return -ENOMEM;
3865
3866 spin_lock_irqsave(&table->lock, flags);
3867 table->table[index] = irte->val;
3868 spin_unlock_irqrestore(&table->lock, flags);
3869
3870 iommu_flush_irt(iommu, devid);
3871 iommu_completion_wait(iommu);
3872
3873 return 0;
3874 }
3875
3876 static void free_irte(u16 devid, int index)
3877 {
3878 struct irq_remap_table *table;
3879 struct amd_iommu *iommu;
3880 unsigned long flags;
3881
3882 iommu = amd_iommu_rlookup_table[devid];
3883 if (iommu == NULL)
3884 return;
3885
3886 table = get_irq_table(devid, false);
3887 if (!table)
3888 return;
3889
3890 spin_lock_irqsave(&table->lock, flags);
3891 iommu->irte_ops->clear_allocated(table, index);
3892 spin_unlock_irqrestore(&table->lock, flags);
3893
3894 iommu_flush_irt(iommu, devid);
3895 iommu_completion_wait(iommu);
3896 }
3897
3898 static void irte_prepare(void *entry,
3899 u32 delivery_mode, u32 dest_mode,
3900 u8 vector, u32 dest_apicid, int devid)
3901 {
3902 union irte *irte = (union irte *) entry;
3903
3904 irte->val = 0;
3905 irte->fields.vector = vector;
3906 irte->fields.int_type = delivery_mode;
3907 irte->fields.destination = dest_apicid;
3908 irte->fields.dm = dest_mode;
3909 irte->fields.valid = 1;
3910 }
3911
3912 static void irte_ga_prepare(void *entry,
3913 u32 delivery_mode, u32 dest_mode,
3914 u8 vector, u32 dest_apicid, int devid)
3915 {
3916 struct irte_ga *irte = (struct irte_ga *) entry;
3917 struct iommu_dev_data *dev_data = search_dev_data(devid);
3918
3919 irte->lo.val = 0;
3920 irte->hi.val = 0;
3921 irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0;
3922 irte->lo.fields_remap.int_type = delivery_mode;
3923 irte->lo.fields_remap.dm = dest_mode;
3924 irte->hi.fields.vector = vector;
3925 irte->lo.fields_remap.destination = dest_apicid;
3926 irte->lo.fields_remap.valid = 1;
3927 }
3928
3929 static void irte_activate(void *entry, u16 devid, u16 index)
3930 {
3931 union irte *irte = (union irte *) entry;
3932
3933 irte->fields.valid = 1;
3934 modify_irte(devid, index, irte);
3935 }
3936
3937 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3938 {
3939 struct irte_ga *irte = (struct irte_ga *) entry;
3940
3941 irte->lo.fields_remap.valid = 1;
3942 modify_irte_ga(devid, index, irte, NULL);
3943 }
3944
3945 static void irte_deactivate(void *entry, u16 devid, u16 index)
3946 {
3947 union irte *irte = (union irte *) entry;
3948
3949 irte->fields.valid = 0;
3950 modify_irte(devid, index, irte);
3951 }
3952
3953 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3954 {
3955 struct irte_ga *irte = (struct irte_ga *) entry;
3956
3957 irte->lo.fields_remap.valid = 0;
3958 modify_irte_ga(devid, index, irte, NULL);
3959 }
3960
3961 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3962 u8 vector, u32 dest_apicid)
3963 {
3964 union irte *irte = (union irte *) entry;
3965
3966 irte->fields.vector = vector;
3967 irte->fields.destination = dest_apicid;
3968 modify_irte(devid, index, irte);
3969 }
3970
3971 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3972 u8 vector, u32 dest_apicid)
3973 {
3974 struct irte_ga *irte = (struct irte_ga *) entry;
3975 struct iommu_dev_data *dev_data = search_dev_data(devid);
3976
3977 if (!dev_data || !dev_data->use_vapic) {
3978 irte->hi.fields.vector = vector;
3979 irte->lo.fields_remap.destination = dest_apicid;
3980 irte->lo.fields_remap.guest_mode = 0;
3981 modify_irte_ga(devid, index, irte, NULL);
3982 }
3983 }
3984
3985 #define IRTE_ALLOCATED (~1U)
3986 static void irte_set_allocated(struct irq_remap_table *table, int index)
3987 {
3988 table->table[index] = IRTE_ALLOCATED;
3989 }
3990
3991 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3992 {
3993 struct irte_ga *ptr = (struct irte_ga *)table->table;
3994 struct irte_ga *irte = &ptr[index];
3995
3996 memset(&irte->lo.val, 0, sizeof(u64));
3997 memset(&irte->hi.val, 0, sizeof(u64));
3998 irte->hi.fields.vector = 0xff;
3999 }
4000
4001 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4002 {
4003 union irte *ptr = (union irte *)table->table;
4004 union irte *irte = &ptr[index];
4005
4006 return irte->val != 0;
4007 }
4008
4009 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4010 {
4011 struct irte_ga *ptr = (struct irte_ga *)table->table;
4012 struct irte_ga *irte = &ptr[index];
4013
4014 return irte->hi.fields.vector != 0;
4015 }
4016
4017 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4018 {
4019 table->table[index] = 0;
4020 }
4021
4022 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4023 {
4024 struct irte_ga *ptr = (struct irte_ga *)table->table;
4025 struct irte_ga *irte = &ptr[index];
4026
4027 memset(&irte->lo.val, 0, sizeof(u64));
4028 memset(&irte->hi.val, 0, sizeof(u64));
4029 }
4030
4031 static int get_devid(struct irq_alloc_info *info)
4032 {
4033 int devid = -1;
4034
4035 switch (info->type) {
4036 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4037 devid = get_ioapic_devid(info->ioapic_id);
4038 break;
4039 case X86_IRQ_ALLOC_TYPE_HPET:
4040 devid = get_hpet_devid(info->hpet_id);
4041 break;
4042 case X86_IRQ_ALLOC_TYPE_MSI:
4043 case X86_IRQ_ALLOC_TYPE_MSIX:
4044 devid = get_device_id(&info->msi_dev->dev);
4045 break;
4046 default:
4047 BUG_ON(1);
4048 break;
4049 }
4050
4051 return devid;
4052 }
4053
4054 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4055 {
4056 struct amd_iommu *iommu;
4057 int devid;
4058
4059 if (!info)
4060 return NULL;
4061
4062 devid = get_devid(info);
4063 if (devid >= 0) {
4064 iommu = amd_iommu_rlookup_table[devid];
4065 if (iommu)
4066 return iommu->ir_domain;
4067 }
4068
4069 return NULL;
4070 }
4071
4072 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4073 {
4074 struct amd_iommu *iommu;
4075 int devid;
4076
4077 if (!info)
4078 return NULL;
4079
4080 switch (info->type) {
4081 case X86_IRQ_ALLOC_TYPE_MSI:
4082 case X86_IRQ_ALLOC_TYPE_MSIX:
4083 devid = get_device_id(&info->msi_dev->dev);
4084 if (devid < 0)
4085 return NULL;
4086
4087 iommu = amd_iommu_rlookup_table[devid];
4088 if (iommu)
4089 return iommu->msi_domain;
4090 break;
4091 default:
4092 break;
4093 }
4094
4095 return NULL;
4096 }
4097
4098 struct irq_remap_ops amd_iommu_irq_ops = {
4099 .prepare = amd_iommu_prepare,
4100 .enable = amd_iommu_enable,
4101 .disable = amd_iommu_disable,
4102 .reenable = amd_iommu_reenable,
4103 .enable_faulting = amd_iommu_enable_faulting,
4104 .get_ir_irq_domain = get_ir_irq_domain,
4105 .get_irq_domain = get_irq_domain,
4106 };
4107
4108 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4109 struct irq_cfg *irq_cfg,
4110 struct irq_alloc_info *info,
4111 int devid, int index, int sub_handle)
4112 {
4113 struct irq_2_irte *irte_info = &data->irq_2_irte;
4114 struct msi_msg *msg = &data->msi_entry;
4115 struct IO_APIC_route_entry *entry;
4116 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4117
4118 if (!iommu)
4119 return;
4120
4121 data->irq_2_irte.devid = devid;
4122 data->irq_2_irte.index = index + sub_handle;
4123 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4124 apic->irq_dest_mode, irq_cfg->vector,
4125 irq_cfg->dest_apicid, devid);
4126
4127 switch (info->type) {
4128 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4129 /* Setup IOAPIC entry */
4130 entry = info->ioapic_entry;
4131 info->ioapic_entry = NULL;
4132 memset(entry, 0, sizeof(*entry));
4133 entry->vector = index;
4134 entry->mask = 0;
4135 entry->trigger = info->ioapic_trigger;
4136 entry->polarity = info->ioapic_polarity;
4137 /* Mask level triggered irqs. */
4138 if (info->ioapic_trigger)
4139 entry->mask = 1;
4140 break;
4141
4142 case X86_IRQ_ALLOC_TYPE_HPET:
4143 case X86_IRQ_ALLOC_TYPE_MSI:
4144 case X86_IRQ_ALLOC_TYPE_MSIX:
4145 msg->address_hi = MSI_ADDR_BASE_HI;
4146 msg->address_lo = MSI_ADDR_BASE_LO;
4147 msg->data = irte_info->index;
4148 break;
4149
4150 default:
4151 BUG_ON(1);
4152 break;
4153 }
4154 }
4155
4156 struct amd_irte_ops irte_32_ops = {
4157 .prepare = irte_prepare,
4158 .activate = irte_activate,
4159 .deactivate = irte_deactivate,
4160 .set_affinity = irte_set_affinity,
4161 .set_allocated = irte_set_allocated,
4162 .is_allocated = irte_is_allocated,
4163 .clear_allocated = irte_clear_allocated,
4164 };
4165
4166 struct amd_irte_ops irte_128_ops = {
4167 .prepare = irte_ga_prepare,
4168 .activate = irte_ga_activate,
4169 .deactivate = irte_ga_deactivate,
4170 .set_affinity = irte_ga_set_affinity,
4171 .set_allocated = irte_ga_set_allocated,
4172 .is_allocated = irte_ga_is_allocated,
4173 .clear_allocated = irte_ga_clear_allocated,
4174 };
4175
4176 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4177 unsigned int nr_irqs, void *arg)
4178 {
4179 struct irq_alloc_info *info = arg;
4180 struct irq_data *irq_data;
4181 struct amd_ir_data *data = NULL;
4182 struct irq_cfg *cfg;
4183 int i, ret, devid;
4184 int index = -1;
4185
4186 if (!info)
4187 return -EINVAL;
4188 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4189 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4190 return -EINVAL;
4191
4192 /*
4193 * With IRQ remapping enabled, don't need contiguous CPU vectors
4194 * to support multiple MSI interrupts.
4195 */
4196 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4197 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4198
4199 devid = get_devid(info);
4200 if (devid < 0)
4201 return -EINVAL;
4202
4203 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4204 if (ret < 0)
4205 return ret;
4206
4207 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4208 if (get_irq_table(devid, true))
4209 index = info->ioapic_pin;
4210 else
4211 ret = -ENOMEM;
4212 } else {
4213 index = alloc_irq_index(devid, nr_irqs);
4214 }
4215 if (index < 0) {
4216 pr_warn("Failed to allocate IRTE\n");
4217 ret = index;
4218 goto out_free_parent;
4219 }
4220
4221 for (i = 0; i < nr_irqs; i++) {
4222 irq_data = irq_domain_get_irq_data(domain, virq + i);
4223 cfg = irqd_cfg(irq_data);
4224 if (!irq_data || !cfg) {
4225 ret = -EINVAL;
4226 goto out_free_data;
4227 }
4228
4229 ret = -ENOMEM;
4230 data = kzalloc(sizeof(*data), GFP_KERNEL);
4231 if (!data)
4232 goto out_free_data;
4233
4234 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4235 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4236 else
4237 data->entry = kzalloc(sizeof(struct irte_ga),
4238 GFP_KERNEL);
4239 if (!data->entry) {
4240 kfree(data);
4241 goto out_free_data;
4242 }
4243
4244 irq_data->hwirq = (devid << 16) + i;
4245 irq_data->chip_data = data;
4246 irq_data->chip = &amd_ir_chip;
4247 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4248 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4249 }
4250
4251 return 0;
4252
4253 out_free_data:
4254 for (i--; i >= 0; i--) {
4255 irq_data = irq_domain_get_irq_data(domain, virq + i);
4256 if (irq_data)
4257 kfree(irq_data->chip_data);
4258 }
4259 for (i = 0; i < nr_irqs; i++)
4260 free_irte(devid, index + i);
4261 out_free_parent:
4262 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4263 return ret;
4264 }
4265
4266 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4267 unsigned int nr_irqs)
4268 {
4269 struct irq_2_irte *irte_info;
4270 struct irq_data *irq_data;
4271 struct amd_ir_data *data;
4272 int i;
4273
4274 for (i = 0; i < nr_irqs; i++) {
4275 irq_data = irq_domain_get_irq_data(domain, virq + i);
4276 if (irq_data && irq_data->chip_data) {
4277 data = irq_data->chip_data;
4278 irte_info = &data->irq_2_irte;
4279 free_irte(irte_info->devid, irte_info->index);
4280 kfree(data->entry);
4281 kfree(data);
4282 }
4283 }
4284 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4285 }
4286
4287 static void irq_remapping_activate(struct irq_domain *domain,
4288 struct irq_data *irq_data)
4289 {
4290 struct amd_ir_data *data = irq_data->chip_data;
4291 struct irq_2_irte *irte_info = &data->irq_2_irte;
4292 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4293
4294 if (iommu)
4295 iommu->irte_ops->activate(data->entry, irte_info->devid,
4296 irte_info->index);
4297 }
4298
4299 static void irq_remapping_deactivate(struct irq_domain *domain,
4300 struct irq_data *irq_data)
4301 {
4302 struct amd_ir_data *data = irq_data->chip_data;
4303 struct irq_2_irte *irte_info = &data->irq_2_irte;
4304 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4305
4306 if (iommu)
4307 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4308 irte_info->index);
4309 }
4310
4311 static const struct irq_domain_ops amd_ir_domain_ops = {
4312 .alloc = irq_remapping_alloc,
4313 .free = irq_remapping_free,
4314 .activate = irq_remapping_activate,
4315 .deactivate = irq_remapping_deactivate,
4316 };
4317
4318 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4319 {
4320 struct amd_iommu *iommu;
4321 struct amd_iommu_pi_data *pi_data = vcpu_info;
4322 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4323 struct amd_ir_data *ir_data = data->chip_data;
4324 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4325 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4326 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4327
4328 /* Note:
4329 * This device has never been set up for guest mode.
4330 * we should not modify the IRTE
4331 */
4332 if (!dev_data || !dev_data->use_vapic)
4333 return 0;
4334
4335 pi_data->ir_data = ir_data;
4336
4337 /* Note:
4338 * SVM tries to set up for VAPIC mode, but we are in
4339 * legacy mode. So, we force legacy mode instead.
4340 */
4341 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4342 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4343 __func__);
4344 pi_data->is_guest_mode = false;
4345 }
4346
4347 iommu = amd_iommu_rlookup_table[irte_info->devid];
4348 if (iommu == NULL)
4349 return -EINVAL;
4350
4351 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4352 if (pi_data->is_guest_mode) {
4353 /* Setting */
4354 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4355 irte->hi.fields.vector = vcpu_pi_info->vector;
4356 irte->lo.fields_vapic.guest_mode = 1;
4357 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4358
4359 ir_data->cached_ga_tag = pi_data->ga_tag;
4360 } else {
4361 /* Un-Setting */
4362 struct irq_cfg *cfg = irqd_cfg(data);
4363
4364 irte->hi.val = 0;
4365 irte->lo.val = 0;
4366 irte->hi.fields.vector = cfg->vector;
4367 irte->lo.fields_remap.guest_mode = 0;
4368 irte->lo.fields_remap.destination = cfg->dest_apicid;
4369 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4370 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4371
4372 /*
4373 * This communicates the ga_tag back to the caller
4374 * so that it can do all the necessary clean up.
4375 */
4376 ir_data->cached_ga_tag = 0;
4377 }
4378
4379 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4380 }
4381
4382 static int amd_ir_set_affinity(struct irq_data *data,
4383 const struct cpumask *mask, bool force)
4384 {
4385 struct amd_ir_data *ir_data = data->chip_data;
4386 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4387 struct irq_cfg *cfg = irqd_cfg(data);
4388 struct irq_data *parent = data->parent_data;
4389 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4390 int ret;
4391
4392 if (!iommu)
4393 return -ENODEV;
4394
4395 ret = parent->chip->irq_set_affinity(parent, mask, force);
4396 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4397 return ret;
4398
4399 /*
4400 * Atomically updates the IRTE with the new destination, vector
4401 * and flushes the interrupt entry cache.
4402 */
4403 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4404 irte_info->index, cfg->vector, cfg->dest_apicid);
4405
4406 /*
4407 * After this point, all the interrupts will start arriving
4408 * at the new destination. So, time to cleanup the previous
4409 * vector allocation.
4410 */
4411 send_cleanup_vector(cfg);
4412
4413 return IRQ_SET_MASK_OK_DONE;
4414 }
4415
4416 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4417 {
4418 struct amd_ir_data *ir_data = irq_data->chip_data;
4419
4420 *msg = ir_data->msi_entry;
4421 }
4422
4423 static struct irq_chip amd_ir_chip = {
4424 .irq_ack = ir_ack_apic_edge,
4425 .irq_set_affinity = amd_ir_set_affinity,
4426 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4427 .irq_compose_msi_msg = ir_compose_msi_msg,
4428 };
4429
4430 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4431 {
4432 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4433 if (!iommu->ir_domain)
4434 return -ENOMEM;
4435
4436 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4437 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4438
4439 return 0;
4440 }
4441
4442 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4443 {
4444 unsigned long flags;
4445 struct amd_iommu *iommu;
4446 struct irq_remap_table *irt;
4447 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4448 int devid = ir_data->irq_2_irte.devid;
4449 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4450 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4451
4452 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4453 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4454 return 0;
4455
4456 iommu = amd_iommu_rlookup_table[devid];
4457 if (!iommu)
4458 return -ENODEV;
4459
4460 irt = get_irq_table(devid, false);
4461 if (!irt)
4462 return -ENODEV;
4463
4464 spin_lock_irqsave(&irt->lock, flags);
4465
4466 if (ref->lo.fields_vapic.guest_mode) {
4467 if (cpu >= 0)
4468 ref->lo.fields_vapic.destination = cpu;
4469 ref->lo.fields_vapic.is_run = is_run;
4470 barrier();
4471 }
4472
4473 spin_unlock_irqrestore(&irt->lock, flags);
4474
4475 iommu_flush_irt(iommu, devid);
4476 iommu_completion_wait(iommu);
4477 return 0;
4478 }
4479 EXPORT_SYMBOL(amd_iommu_update_ga);
4480 #endif
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