2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #define pr_fmt(fmt) "AMD-Vi: " fmt
22 #include <linux/ratelimit.h>
23 #include <linux/pci.h>
24 #include <linux/acpi.h>
25 #include <linux/amba/bus.h>
26 #include <linux/platform_device.h>
27 #include <linux/pci-ats.h>
28 #include <linux/bitmap.h>
29 #include <linux/slab.h>
30 #include <linux/debugfs.h>
31 #include <linux/scatterlist.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dma-direct.h>
34 #include <linux/iommu-helper.h>
35 #include <linux/iommu.h>
36 #include <linux/delay.h>
37 #include <linux/amd-iommu.h>
38 #include <linux/notifier.h>
39 #include <linux/export.h>
40 #include <linux/irq.h>
41 #include <linux/msi.h>
42 #include <linux/dma-contiguous.h>
43 #include <linux/irqdomain.h>
44 #include <linux/percpu.h>
45 #include <linux/iova.h>
46 #include <asm/irq_remapping.h>
47 #include <asm/io_apic.h>
49 #include <asm/hw_irq.h>
50 #include <asm/msidef.h>
51 #include <asm/proto.h>
52 #include <asm/iommu.h>
56 #include "amd_iommu_proto.h"
57 #include "amd_iommu_types.h"
58 #include "irq_remapping.h"
60 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
62 #define LOOP_TIMEOUT 100000
64 /* IO virtual address start page frame number */
65 #define IOVA_START_PFN (1)
66 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
68 /* Reserved IOVA ranges */
69 #define MSI_RANGE_START (0xfee00000)
70 #define MSI_RANGE_END (0xfeefffff)
71 #define HT_RANGE_START (0xfd00000000ULL)
72 #define HT_RANGE_END (0xffffffffffULL)
75 * This bitmap is used to advertise the page sizes our hardware support
76 * to the IOMMU core, which will then use this information to split
77 * physically contiguous memory regions it is mapping into page sizes
80 * 512GB Pages are not supported due to a hardware bug
82 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
84 static DEFINE_SPINLOCK(amd_iommu_devtable_lock
);
85 static DEFINE_SPINLOCK(pd_bitmap_lock
);
87 /* List of all available dev_data structures */
88 static LLIST_HEAD(dev_data_list
);
90 LIST_HEAD(ioapic_map
);
92 LIST_HEAD(acpihid_map
);
95 * Domain for untranslated devices - only allocated
96 * if iommu=pt passed on kernel cmd line.
98 const struct iommu_ops amd_iommu_ops
;
100 static ATOMIC_NOTIFIER_HEAD(ppr_notifier
);
101 int amd_iommu_max_glx_val
= -1;
103 static const struct dma_map_ops amd_iommu_dma_ops
;
106 * general struct to manage commands send to an IOMMU
112 struct kmem_cache
*amd_iommu_irq_cache
;
114 static void update_domain(struct protection_domain
*domain
);
115 static int protection_domain_init(struct protection_domain
*domain
);
116 static void detach_device(struct device
*dev
);
117 static void iova_domain_flush_tlb(struct iova_domain
*iovad
);
120 * Data container for a dma_ops specific protection domain
122 struct dma_ops_domain
{
123 /* generic protection domain information */
124 struct protection_domain domain
;
127 struct iova_domain iovad
;
130 static struct iova_domain reserved_iova_ranges
;
131 static struct lock_class_key reserved_rbtree_key
;
133 /****************************************************************************
137 ****************************************************************************/
139 static inline int match_hid_uid(struct device
*dev
,
140 struct acpihid_map_entry
*entry
)
142 const char *hid
, *uid
;
144 hid
= acpi_device_hid(ACPI_COMPANION(dev
));
145 uid
= acpi_device_uid(ACPI_COMPANION(dev
));
151 return strcmp(hid
, entry
->hid
);
154 return strcmp(hid
, entry
->hid
);
156 return (strcmp(hid
, entry
->hid
) || strcmp(uid
, entry
->uid
));
159 static inline u16
get_pci_device_id(struct device
*dev
)
161 struct pci_dev
*pdev
= to_pci_dev(dev
);
163 return PCI_DEVID(pdev
->bus
->number
, pdev
->devfn
);
166 static inline int get_acpihid_device_id(struct device
*dev
,
167 struct acpihid_map_entry
**entry
)
169 struct acpihid_map_entry
*p
;
171 list_for_each_entry(p
, &acpihid_map
, list
) {
172 if (!match_hid_uid(dev
, p
)) {
181 static inline int get_device_id(struct device
*dev
)
186 devid
= get_pci_device_id(dev
);
188 devid
= get_acpihid_device_id(dev
, NULL
);
193 static struct protection_domain
*to_pdomain(struct iommu_domain
*dom
)
195 return container_of(dom
, struct protection_domain
, domain
);
198 static struct dma_ops_domain
* to_dma_ops_domain(struct protection_domain
*domain
)
200 BUG_ON(domain
->flags
!= PD_DMA_OPS_MASK
);
201 return container_of(domain
, struct dma_ops_domain
, domain
);
204 static struct iommu_dev_data
*alloc_dev_data(u16 devid
)
206 struct iommu_dev_data
*dev_data
;
208 dev_data
= kzalloc(sizeof(*dev_data
), GFP_KERNEL
);
212 dev_data
->devid
= devid
;
213 ratelimit_default_init(&dev_data
->rs
);
215 llist_add(&dev_data
->dev_data_list
, &dev_data_list
);
219 static struct iommu_dev_data
*search_dev_data(u16 devid
)
221 struct iommu_dev_data
*dev_data
;
222 struct llist_node
*node
;
224 if (llist_empty(&dev_data_list
))
227 node
= dev_data_list
.first
;
228 llist_for_each_entry(dev_data
, node
, dev_data_list
) {
229 if (dev_data
->devid
== devid
)
236 static int __last_alias(struct pci_dev
*pdev
, u16 alias
, void *data
)
238 *(u16
*)data
= alias
;
242 static u16
get_alias(struct device
*dev
)
244 struct pci_dev
*pdev
= to_pci_dev(dev
);
245 u16 devid
, ivrs_alias
, pci_alias
;
247 /* The callers make sure that get_device_id() does not fail here */
248 devid
= get_device_id(dev
);
250 /* For ACPI HID devices, we simply return the devid as such */
251 if (!dev_is_pci(dev
))
254 ivrs_alias
= amd_iommu_alias_table
[devid
];
256 pci_for_each_dma_alias(pdev
, __last_alias
, &pci_alias
);
258 if (ivrs_alias
== pci_alias
)
264 * The IVRS is fairly reliable in telling us about aliases, but it
265 * can't know about every screwy device. If we don't have an IVRS
266 * reported alias, use the PCI reported alias. In that case we may
267 * still need to initialize the rlookup and dev_table entries if the
268 * alias is to a non-existent device.
270 if (ivrs_alias
== devid
) {
271 if (!amd_iommu_rlookup_table
[pci_alias
]) {
272 amd_iommu_rlookup_table
[pci_alias
] =
273 amd_iommu_rlookup_table
[devid
];
274 memcpy(amd_iommu_dev_table
[pci_alias
].data
,
275 amd_iommu_dev_table
[devid
].data
,
276 sizeof(amd_iommu_dev_table
[pci_alias
].data
));
282 pr_info("Using IVRS reported alias %02x:%02x.%d "
283 "for device %s[%04x:%04x], kernel reported alias "
284 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias
), PCI_SLOT(ivrs_alias
),
285 PCI_FUNC(ivrs_alias
), dev_name(dev
), pdev
->vendor
, pdev
->device
,
286 PCI_BUS_NUM(pci_alias
), PCI_SLOT(pci_alias
),
287 PCI_FUNC(pci_alias
));
290 * If we don't have a PCI DMA alias and the IVRS alias is on the same
291 * bus, then the IVRS table may know about a quirk that we don't.
293 if (pci_alias
== devid
&&
294 PCI_BUS_NUM(ivrs_alias
) == pdev
->bus
->number
) {
295 pci_add_dma_alias(pdev
, ivrs_alias
& 0xff);
296 pr_info("Added PCI DMA alias %02x.%d for %s\n",
297 PCI_SLOT(ivrs_alias
), PCI_FUNC(ivrs_alias
),
304 static struct iommu_dev_data
*find_dev_data(u16 devid
)
306 struct iommu_dev_data
*dev_data
;
307 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
309 dev_data
= search_dev_data(devid
);
311 if (dev_data
== NULL
) {
312 dev_data
= alloc_dev_data(devid
);
316 if (translation_pre_enabled(iommu
))
317 dev_data
->defer_attach
= true;
323 struct iommu_dev_data
*get_dev_data(struct device
*dev
)
325 return dev
->archdata
.iommu
;
327 EXPORT_SYMBOL(get_dev_data
);
330 * Find or create an IOMMU group for a acpihid device.
332 static struct iommu_group
*acpihid_device_group(struct device
*dev
)
334 struct acpihid_map_entry
*p
, *entry
= NULL
;
337 devid
= get_acpihid_device_id(dev
, &entry
);
339 return ERR_PTR(devid
);
341 list_for_each_entry(p
, &acpihid_map
, list
) {
342 if ((devid
== p
->devid
) && p
->group
)
343 entry
->group
= p
->group
;
347 entry
->group
= generic_device_group(dev
);
349 iommu_group_ref_get(entry
->group
);
354 static bool pci_iommuv2_capable(struct pci_dev
*pdev
)
356 static const int caps
[] = {
359 PCI_EXT_CAP_ID_PASID
,
363 if (pci_ats_disabled())
366 for (i
= 0; i
< 3; ++i
) {
367 pos
= pci_find_ext_capability(pdev
, caps
[i
]);
375 static bool pdev_pri_erratum(struct pci_dev
*pdev
, u32 erratum
)
377 struct iommu_dev_data
*dev_data
;
379 dev_data
= get_dev_data(&pdev
->dev
);
381 return dev_data
->errata
& (1 << erratum
) ? true : false;
385 * This function checks if the driver got a valid device from the caller to
386 * avoid dereferencing invalid pointers.
388 static bool check_device(struct device
*dev
)
392 if (!dev
|| !dev
->dma_mask
)
395 devid
= get_device_id(dev
);
399 /* Out of our scope? */
400 if (devid
> amd_iommu_last_bdf
)
403 if (amd_iommu_rlookup_table
[devid
] == NULL
)
409 static void init_iommu_group(struct device
*dev
)
411 struct iommu_group
*group
;
413 group
= iommu_group_get_for_dev(dev
);
417 iommu_group_put(group
);
420 static int iommu_init_device(struct device
*dev
)
422 struct iommu_dev_data
*dev_data
;
423 struct amd_iommu
*iommu
;
426 if (dev
->archdata
.iommu
)
429 devid
= get_device_id(dev
);
433 iommu
= amd_iommu_rlookup_table
[devid
];
435 dev_data
= find_dev_data(devid
);
439 dev_data
->alias
= get_alias(dev
);
442 * By default we use passthrough mode for IOMMUv2 capable device.
443 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
444 * invalid address), we ignore the capability for the device so
445 * it'll be forced to go into translation mode.
447 if ((iommu_pass_through
|| !amd_iommu_force_isolation
) &&
448 dev_is_pci(dev
) && pci_iommuv2_capable(to_pci_dev(dev
))) {
449 struct amd_iommu
*iommu
;
451 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
452 dev_data
->iommu_v2
= iommu
->is_iommu_v2
;
455 dev
->archdata
.iommu
= dev_data
;
457 iommu_device_link(&iommu
->iommu
, dev
);
462 static void iommu_ignore_device(struct device
*dev
)
467 devid
= get_device_id(dev
);
471 alias
= get_alias(dev
);
473 memset(&amd_iommu_dev_table
[devid
], 0, sizeof(struct dev_table_entry
));
474 memset(&amd_iommu_dev_table
[alias
], 0, sizeof(struct dev_table_entry
));
476 amd_iommu_rlookup_table
[devid
] = NULL
;
477 amd_iommu_rlookup_table
[alias
] = NULL
;
480 static void iommu_uninit_device(struct device
*dev
)
482 struct iommu_dev_data
*dev_data
;
483 struct amd_iommu
*iommu
;
486 devid
= get_device_id(dev
);
490 iommu
= amd_iommu_rlookup_table
[devid
];
492 dev_data
= search_dev_data(devid
);
496 if (dev_data
->domain
)
499 iommu_device_unlink(&iommu
->iommu
, dev
);
501 iommu_group_remove_device(dev
);
507 * We keep dev_data around for unplugged devices and reuse it when the
508 * device is re-plugged - not doing so would introduce a ton of races.
512 /****************************************************************************
514 * Interrupt handling functions
516 ****************************************************************************/
518 static void dump_dte_entry(u16 devid
)
522 for (i
= 0; i
< 4; ++i
)
523 pr_err("DTE[%d]: %016llx\n", i
,
524 amd_iommu_dev_table
[devid
].data
[i
]);
527 static void dump_command(unsigned long phys_addr
)
529 struct iommu_cmd
*cmd
= iommu_phys_to_virt(phys_addr
);
532 for (i
= 0; i
< 4; ++i
)
533 pr_err("CMD[%d]: %08x\n", i
, cmd
->data
[i
]);
536 static void amd_iommu_report_page_fault(u16 devid
, u16 domain_id
,
537 u64 address
, int flags
)
539 struct iommu_dev_data
*dev_data
= NULL
;
540 struct pci_dev
*pdev
;
542 pdev
= pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid
),
545 dev_data
= get_dev_data(&pdev
->dev
);
547 if (dev_data
&& __ratelimit(&dev_data
->rs
)) {
548 dev_err(&pdev
->dev
, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
549 domain_id
, address
, flags
);
550 } else if (printk_ratelimit()) {
551 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
552 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
553 domain_id
, address
, flags
);
560 static void iommu_print_event(struct amd_iommu
*iommu
, void *__evt
)
562 struct device
*dev
= iommu
->iommu
.dev
;
563 int type
, devid
, pasid
, flags
, tag
;
564 volatile u32
*event
= __evt
;
569 type
= (event
[1] >> EVENT_TYPE_SHIFT
) & EVENT_TYPE_MASK
;
570 devid
= (event
[0] >> EVENT_DEVID_SHIFT
) & EVENT_DEVID_MASK
;
571 pasid
= PPR_PASID(*(u64
*)&event
[0]);
572 flags
= (event
[1] >> EVENT_FLAGS_SHIFT
) & EVENT_FLAGS_MASK
;
573 address
= (u64
)(((u64
)event
[3]) << 32) | event
[2];
576 /* Did we hit the erratum? */
577 if (++count
== LOOP_TIMEOUT
) {
578 pr_err("No event written to event log\n");
585 if (type
== EVENT_TYPE_IO_FAULT
) {
586 amd_iommu_report_page_fault(devid
, pasid
, address
, flags
);
591 case EVENT_TYPE_ILL_DEV
:
592 dev_err(dev
, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
593 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
594 pasid
, address
, flags
);
595 dump_dte_entry(devid
);
597 case EVENT_TYPE_DEV_TAB_ERR
:
598 dev_err(dev
, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
599 "address=0x%llx flags=0x%04x]\n",
600 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
603 case EVENT_TYPE_PAGE_TAB_ERR
:
604 dev_err(dev
, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
605 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
606 pasid
, address
, flags
);
608 case EVENT_TYPE_ILL_CMD
:
609 dev_err(dev
, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address
);
610 dump_command(address
);
612 case EVENT_TYPE_CMD_HARD_ERR
:
613 dev_err(dev
, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
616 case EVENT_TYPE_IOTLB_INV_TO
:
617 dev_err(dev
, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
618 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
621 case EVENT_TYPE_INV_DEV_REQ
:
622 dev_err(dev
, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
623 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
624 pasid
, address
, flags
);
626 case EVENT_TYPE_INV_PPR_REQ
:
627 pasid
= ((event
[0] >> 16) & 0xFFFF)
628 | ((event
[1] << 6) & 0xF0000);
629 tag
= event
[1] & 0x03FF;
630 dev_err(dev
, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
631 PCI_BUS_NUM(devid
), PCI_SLOT(devid
), PCI_FUNC(devid
),
632 pasid
, address
, flags
);
635 dev_err(dev
, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
636 event
[0], event
[1], event
[2], event
[3]);
639 memset(__evt
, 0, 4 * sizeof(u32
));
642 static void iommu_poll_events(struct amd_iommu
*iommu
)
646 head
= readl(iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
647 tail
= readl(iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
649 while (head
!= tail
) {
650 iommu_print_event(iommu
, iommu
->evt_buf
+ head
);
651 head
= (head
+ EVENT_ENTRY_SIZE
) % EVT_BUFFER_SIZE
;
654 writel(head
, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
657 static void iommu_handle_ppr_entry(struct amd_iommu
*iommu
, u64
*raw
)
659 struct amd_iommu_fault fault
;
661 if (PPR_REQ_TYPE(raw
[0]) != PPR_REQ_FAULT
) {
662 pr_err_ratelimited("Unknown PPR request received\n");
666 fault
.address
= raw
[1];
667 fault
.pasid
= PPR_PASID(raw
[0]);
668 fault
.device_id
= PPR_DEVID(raw
[0]);
669 fault
.tag
= PPR_TAG(raw
[0]);
670 fault
.flags
= PPR_FLAGS(raw
[0]);
672 atomic_notifier_call_chain(&ppr_notifier
, 0, &fault
);
675 static void iommu_poll_ppr_log(struct amd_iommu
*iommu
)
679 if (iommu
->ppr_log
== NULL
)
682 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
683 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
685 while (head
!= tail
) {
690 raw
= (u64
*)(iommu
->ppr_log
+ head
);
693 * Hardware bug: Interrupt may arrive before the entry is
694 * written to memory. If this happens we need to wait for the
697 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
698 if (PPR_REQ_TYPE(raw
[0]) != 0)
703 /* Avoid memcpy function-call overhead */
708 * To detect the hardware bug we need to clear the entry
711 raw
[0] = raw
[1] = 0UL;
713 /* Update head pointer of hardware ring-buffer */
714 head
= (head
+ PPR_ENTRY_SIZE
) % PPR_LOG_SIZE
;
715 writel(head
, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
717 /* Handle PPR entry */
718 iommu_handle_ppr_entry(iommu
, entry
);
720 /* Refresh ring-buffer information */
721 head
= readl(iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
722 tail
= readl(iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
726 #ifdef CONFIG_IRQ_REMAP
727 static int (*iommu_ga_log_notifier
)(u32
);
729 int amd_iommu_register_ga_log_notifier(int (*notifier
)(u32
))
731 iommu_ga_log_notifier
= notifier
;
735 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier
);
737 static void iommu_poll_ga_log(struct amd_iommu
*iommu
)
739 u32 head
, tail
, cnt
= 0;
741 if (iommu
->ga_log
== NULL
)
744 head
= readl(iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
745 tail
= readl(iommu
->mmio_base
+ MMIO_GA_TAIL_OFFSET
);
747 while (head
!= tail
) {
751 raw
= (u64
*)(iommu
->ga_log
+ head
);
754 /* Avoid memcpy function-call overhead */
757 /* Update head pointer of hardware ring-buffer */
758 head
= (head
+ GA_ENTRY_SIZE
) % GA_LOG_SIZE
;
759 writel(head
, iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
761 /* Handle GA entry */
762 switch (GA_REQ_TYPE(log_entry
)) {
764 if (!iommu_ga_log_notifier
)
767 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
768 __func__
, GA_DEVID(log_entry
),
771 if (iommu_ga_log_notifier(GA_TAG(log_entry
)) != 0)
772 pr_err("GA log notifier failed.\n");
779 #endif /* CONFIG_IRQ_REMAP */
781 #define AMD_IOMMU_INT_MASK \
782 (MMIO_STATUS_EVT_INT_MASK | \
783 MMIO_STATUS_PPR_INT_MASK | \
784 MMIO_STATUS_GALOG_INT_MASK)
786 irqreturn_t
amd_iommu_int_thread(int irq
, void *data
)
788 struct amd_iommu
*iommu
= (struct amd_iommu
*) data
;
789 u32 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
791 while (status
& AMD_IOMMU_INT_MASK
) {
792 /* Enable EVT and PPR and GA interrupts again */
793 writel(AMD_IOMMU_INT_MASK
,
794 iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
796 if (status
& MMIO_STATUS_EVT_INT_MASK
) {
797 pr_devel("Processing IOMMU Event Log\n");
798 iommu_poll_events(iommu
);
801 if (status
& MMIO_STATUS_PPR_INT_MASK
) {
802 pr_devel("Processing IOMMU PPR Log\n");
803 iommu_poll_ppr_log(iommu
);
806 #ifdef CONFIG_IRQ_REMAP
807 if (status
& MMIO_STATUS_GALOG_INT_MASK
) {
808 pr_devel("Processing IOMMU GA Log\n");
809 iommu_poll_ga_log(iommu
);
814 * Hardware bug: ERBT1312
815 * When re-enabling interrupt (by writing 1
816 * to clear the bit), the hardware might also try to set
817 * the interrupt bit in the event status register.
818 * In this scenario, the bit will be set, and disable
819 * subsequent interrupts.
821 * Workaround: The IOMMU driver should read back the
822 * status register and check if the interrupt bits are cleared.
823 * If not, driver will need to go through the interrupt handler
824 * again and re-clear the bits
826 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
831 irqreturn_t
amd_iommu_int_handler(int irq
, void *data
)
833 return IRQ_WAKE_THREAD
;
836 /****************************************************************************
838 * IOMMU command queuing functions
840 ****************************************************************************/
842 static int wait_on_sem(volatile u64
*sem
)
846 while (*sem
== 0 && i
< LOOP_TIMEOUT
) {
851 if (i
== LOOP_TIMEOUT
) {
852 pr_alert("Completion-Wait loop timed out\n");
859 static void copy_cmd_to_buffer(struct amd_iommu
*iommu
,
860 struct iommu_cmd
*cmd
)
864 target
= iommu
->cmd_buf
+ iommu
->cmd_buf_tail
;
866 iommu
->cmd_buf_tail
+= sizeof(*cmd
);
867 iommu
->cmd_buf_tail
%= CMD_BUFFER_SIZE
;
869 /* Copy command to buffer */
870 memcpy(target
, cmd
, sizeof(*cmd
));
872 /* Tell the IOMMU about it */
873 writel(iommu
->cmd_buf_tail
, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
876 static void build_completion_wait(struct iommu_cmd
*cmd
, u64 address
)
878 u64 paddr
= iommu_virt_to_phys((void *)address
);
880 WARN_ON(address
& 0x7ULL
);
882 memset(cmd
, 0, sizeof(*cmd
));
883 cmd
->data
[0] = lower_32_bits(paddr
) | CMD_COMPL_WAIT_STORE_MASK
;
884 cmd
->data
[1] = upper_32_bits(paddr
);
886 CMD_SET_TYPE(cmd
, CMD_COMPL_WAIT
);
889 static void build_inv_dte(struct iommu_cmd
*cmd
, u16 devid
)
891 memset(cmd
, 0, sizeof(*cmd
));
892 cmd
->data
[0] = devid
;
893 CMD_SET_TYPE(cmd
, CMD_INV_DEV_ENTRY
);
896 static void build_inv_iommu_pages(struct iommu_cmd
*cmd
, u64 address
,
897 size_t size
, u16 domid
, int pde
)
902 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
907 * If we have to flush more than one page, flush all
908 * TLB entries for this domain
910 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
914 address
&= PAGE_MASK
;
916 memset(cmd
, 0, sizeof(*cmd
));
917 cmd
->data
[1] |= domid
;
918 cmd
->data
[2] = lower_32_bits(address
);
919 cmd
->data
[3] = upper_32_bits(address
);
920 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
921 if (s
) /* size bit - we flush more than one 4kb page */
922 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
923 if (pde
) /* PDE bit - we want to flush everything, not only the PTEs */
924 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
927 static void build_inv_iotlb_pages(struct iommu_cmd
*cmd
, u16 devid
, int qdep
,
928 u64 address
, size_t size
)
933 pages
= iommu_num_pages(address
, size
, PAGE_SIZE
);
938 * If we have to flush more than one page, flush all
939 * TLB entries for this domain
941 address
= CMD_INV_IOMMU_ALL_PAGES_ADDRESS
;
945 address
&= PAGE_MASK
;
947 memset(cmd
, 0, sizeof(*cmd
));
948 cmd
->data
[0] = devid
;
949 cmd
->data
[0] |= (qdep
& 0xff) << 24;
950 cmd
->data
[1] = devid
;
951 cmd
->data
[2] = lower_32_bits(address
);
952 cmd
->data
[3] = upper_32_bits(address
);
953 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
955 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
958 static void build_inv_iommu_pasid(struct iommu_cmd
*cmd
, u16 domid
, int pasid
,
959 u64 address
, bool size
)
961 memset(cmd
, 0, sizeof(*cmd
));
963 address
&= ~(0xfffULL
);
965 cmd
->data
[0] = pasid
;
966 cmd
->data
[1] = domid
;
967 cmd
->data
[2] = lower_32_bits(address
);
968 cmd
->data
[3] = upper_32_bits(address
);
969 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK
;
970 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
972 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
973 CMD_SET_TYPE(cmd
, CMD_INV_IOMMU_PAGES
);
976 static void build_inv_iotlb_pasid(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
977 int qdep
, u64 address
, bool size
)
979 memset(cmd
, 0, sizeof(*cmd
));
981 address
&= ~(0xfffULL
);
983 cmd
->data
[0] = devid
;
984 cmd
->data
[0] |= ((pasid
>> 8) & 0xff) << 16;
985 cmd
->data
[0] |= (qdep
& 0xff) << 24;
986 cmd
->data
[1] = devid
;
987 cmd
->data
[1] |= (pasid
& 0xff) << 16;
988 cmd
->data
[2] = lower_32_bits(address
);
989 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_GN_MASK
;
990 cmd
->data
[3] = upper_32_bits(address
);
992 cmd
->data
[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK
;
993 CMD_SET_TYPE(cmd
, CMD_INV_IOTLB_PAGES
);
996 static void build_complete_ppr(struct iommu_cmd
*cmd
, u16 devid
, int pasid
,
997 int status
, int tag
, bool gn
)
999 memset(cmd
, 0, sizeof(*cmd
));
1001 cmd
->data
[0] = devid
;
1003 cmd
->data
[1] = pasid
;
1004 cmd
->data
[2] = CMD_INV_IOMMU_PAGES_GN_MASK
;
1006 cmd
->data
[3] = tag
& 0x1ff;
1007 cmd
->data
[3] |= (status
& PPR_STATUS_MASK
) << PPR_STATUS_SHIFT
;
1009 CMD_SET_TYPE(cmd
, CMD_COMPLETE_PPR
);
1012 static void build_inv_all(struct iommu_cmd
*cmd
)
1014 memset(cmd
, 0, sizeof(*cmd
));
1015 CMD_SET_TYPE(cmd
, CMD_INV_ALL
);
1018 static void build_inv_irt(struct iommu_cmd
*cmd
, u16 devid
)
1020 memset(cmd
, 0, sizeof(*cmd
));
1021 cmd
->data
[0] = devid
;
1022 CMD_SET_TYPE(cmd
, CMD_INV_IRT
);
1026 * Writes the command to the IOMMUs command buffer and informs the
1027 * hardware about the new command.
1029 static int __iommu_queue_command_sync(struct amd_iommu
*iommu
,
1030 struct iommu_cmd
*cmd
,
1033 unsigned int count
= 0;
1034 u32 left
, next_tail
;
1036 next_tail
= (iommu
->cmd_buf_tail
+ sizeof(*cmd
)) % CMD_BUFFER_SIZE
;
1038 left
= (iommu
->cmd_buf_head
- next_tail
) % CMD_BUFFER_SIZE
;
1041 /* Skip udelay() the first time around */
1043 if (count
== LOOP_TIMEOUT
) {
1044 pr_err("Command buffer timeout\n");
1051 /* Update head and recheck remaining space */
1052 iommu
->cmd_buf_head
= readl(iommu
->mmio_base
+
1053 MMIO_CMD_HEAD_OFFSET
);
1058 copy_cmd_to_buffer(iommu
, cmd
);
1060 /* Do we need to make sure all commands are processed? */
1061 iommu
->need_sync
= sync
;
1066 static int iommu_queue_command_sync(struct amd_iommu
*iommu
,
1067 struct iommu_cmd
*cmd
,
1070 unsigned long flags
;
1073 raw_spin_lock_irqsave(&iommu
->lock
, flags
);
1074 ret
= __iommu_queue_command_sync(iommu
, cmd
, sync
);
1075 raw_spin_unlock_irqrestore(&iommu
->lock
, flags
);
1080 static int iommu_queue_command(struct amd_iommu
*iommu
, struct iommu_cmd
*cmd
)
1082 return iommu_queue_command_sync(iommu
, cmd
, true);
1086 * This function queues a completion wait command into the command
1087 * buffer of an IOMMU
1089 static int iommu_completion_wait(struct amd_iommu
*iommu
)
1091 struct iommu_cmd cmd
;
1092 unsigned long flags
;
1095 if (!iommu
->need_sync
)
1099 build_completion_wait(&cmd
, (u64
)&iommu
->cmd_sem
);
1101 raw_spin_lock_irqsave(&iommu
->lock
, flags
);
1105 ret
= __iommu_queue_command_sync(iommu
, &cmd
, false);
1109 ret
= wait_on_sem(&iommu
->cmd_sem
);
1112 raw_spin_unlock_irqrestore(&iommu
->lock
, flags
);
1117 static int iommu_flush_dte(struct amd_iommu
*iommu
, u16 devid
)
1119 struct iommu_cmd cmd
;
1121 build_inv_dte(&cmd
, devid
);
1123 return iommu_queue_command(iommu
, &cmd
);
1126 static void amd_iommu_flush_dte_all(struct amd_iommu
*iommu
)
1130 for (devid
= 0; devid
<= 0xffff; ++devid
)
1131 iommu_flush_dte(iommu
, devid
);
1133 iommu_completion_wait(iommu
);
1137 * This function uses heavy locking and may disable irqs for some time. But
1138 * this is no issue because it is only called during resume.
1140 static void amd_iommu_flush_tlb_all(struct amd_iommu
*iommu
)
1144 for (dom_id
= 0; dom_id
<= 0xffff; ++dom_id
) {
1145 struct iommu_cmd cmd
;
1146 build_inv_iommu_pages(&cmd
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
1148 iommu_queue_command(iommu
, &cmd
);
1151 iommu_completion_wait(iommu
);
1154 static void amd_iommu_flush_all(struct amd_iommu
*iommu
)
1156 struct iommu_cmd cmd
;
1158 build_inv_all(&cmd
);
1160 iommu_queue_command(iommu
, &cmd
);
1161 iommu_completion_wait(iommu
);
1164 static void iommu_flush_irt(struct amd_iommu
*iommu
, u16 devid
)
1166 struct iommu_cmd cmd
;
1168 build_inv_irt(&cmd
, devid
);
1170 iommu_queue_command(iommu
, &cmd
);
1173 static void amd_iommu_flush_irt_all(struct amd_iommu
*iommu
)
1177 for (devid
= 0; devid
<= MAX_DEV_TABLE_ENTRIES
; devid
++)
1178 iommu_flush_irt(iommu
, devid
);
1180 iommu_completion_wait(iommu
);
1183 void iommu_flush_all_caches(struct amd_iommu
*iommu
)
1185 if (iommu_feature(iommu
, FEATURE_IA
)) {
1186 amd_iommu_flush_all(iommu
);
1188 amd_iommu_flush_dte_all(iommu
);
1189 amd_iommu_flush_irt_all(iommu
);
1190 amd_iommu_flush_tlb_all(iommu
);
1195 * Command send function for flushing on-device TLB
1197 static int device_flush_iotlb(struct iommu_dev_data
*dev_data
,
1198 u64 address
, size_t size
)
1200 struct amd_iommu
*iommu
;
1201 struct iommu_cmd cmd
;
1204 qdep
= dev_data
->ats
.qdep
;
1205 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1207 build_inv_iotlb_pages(&cmd
, dev_data
->devid
, qdep
, address
, size
);
1209 return iommu_queue_command(iommu
, &cmd
);
1213 * Command send function for invalidating a device table entry
1215 static int device_flush_dte(struct iommu_dev_data
*dev_data
)
1217 struct amd_iommu
*iommu
;
1221 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1222 alias
= dev_data
->alias
;
1224 ret
= iommu_flush_dte(iommu
, dev_data
->devid
);
1225 if (!ret
&& alias
!= dev_data
->devid
)
1226 ret
= iommu_flush_dte(iommu
, alias
);
1230 if (dev_data
->ats
.enabled
)
1231 ret
= device_flush_iotlb(dev_data
, 0, ~0UL);
1237 * TLB invalidation function which is called from the mapping functions.
1238 * It invalidates a single PTE if the range to flush is within a single
1239 * page. Otherwise it flushes the whole TLB of the IOMMU.
1241 static void __domain_flush_pages(struct protection_domain
*domain
,
1242 u64 address
, size_t size
, int pde
)
1244 struct iommu_dev_data
*dev_data
;
1245 struct iommu_cmd cmd
;
1248 build_inv_iommu_pages(&cmd
, address
, size
, domain
->id
, pde
);
1250 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1251 if (!domain
->dev_iommu
[i
])
1255 * Devices of this domain are behind this IOMMU
1256 * We need a TLB flush
1258 ret
|= iommu_queue_command(amd_iommus
[i
], &cmd
);
1261 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
1263 if (!dev_data
->ats
.enabled
)
1266 ret
|= device_flush_iotlb(dev_data
, address
, size
);
1272 static void domain_flush_pages(struct protection_domain
*domain
,
1273 u64 address
, size_t size
)
1275 __domain_flush_pages(domain
, address
, size
, 0);
1278 /* Flush the whole IO/TLB for a given protection domain */
1279 static void domain_flush_tlb(struct protection_domain
*domain
)
1281 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 0);
1284 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1285 static void domain_flush_tlb_pde(struct protection_domain
*domain
)
1287 __domain_flush_pages(domain
, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
, 1);
1290 static void domain_flush_complete(struct protection_domain
*domain
)
1294 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
1295 if (domain
&& !domain
->dev_iommu
[i
])
1299 * Devices of this domain are behind this IOMMU
1300 * We need to wait for completion of all commands.
1302 iommu_completion_wait(amd_iommus
[i
]);
1308 * This function flushes the DTEs for all devices in domain
1310 static void domain_flush_devices(struct protection_domain
*domain
)
1312 struct iommu_dev_data
*dev_data
;
1314 list_for_each_entry(dev_data
, &domain
->dev_list
, list
)
1315 device_flush_dte(dev_data
);
1318 /****************************************************************************
1320 * The functions below are used the create the page table mappings for
1321 * unity mapped regions.
1323 ****************************************************************************/
1325 static void free_page_list(struct page
*freelist
)
1327 while (freelist
!= NULL
) {
1328 unsigned long p
= (unsigned long)page_address(freelist
);
1329 freelist
= freelist
->freelist
;
1334 static struct page
*free_pt_page(unsigned long pt
, struct page
*freelist
)
1336 struct page
*p
= virt_to_page((void *)pt
);
1338 p
->freelist
= freelist
;
1343 #define DEFINE_FREE_PT_FN(LVL, FN) \
1344 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1352 for (i = 0; i < 512; ++i) { \
1353 /* PTE present? */ \
1354 if (!IOMMU_PTE_PRESENT(pt[i])) \
1358 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1359 PM_PTE_LEVEL(pt[i]) == 7) \
1362 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1363 freelist = FN(p, freelist); \
1366 return free_pt_page((unsigned long)pt, freelist); \
1369 DEFINE_FREE_PT_FN(l2
, free_pt_page
)
1370 DEFINE_FREE_PT_FN(l3
, free_pt_l2
)
1371 DEFINE_FREE_PT_FN(l4
, free_pt_l3
)
1372 DEFINE_FREE_PT_FN(l5
, free_pt_l4
)
1373 DEFINE_FREE_PT_FN(l6
, free_pt_l5
)
1375 static struct page
*free_sub_pt(unsigned long root
, int mode
,
1376 struct page
*freelist
)
1379 case PAGE_MODE_NONE
:
1380 case PAGE_MODE_7_LEVEL
:
1382 case PAGE_MODE_1_LEVEL
:
1383 freelist
= free_pt_page(root
, freelist
);
1385 case PAGE_MODE_2_LEVEL
:
1386 freelist
= free_pt_l2(root
, freelist
);
1388 case PAGE_MODE_3_LEVEL
:
1389 freelist
= free_pt_l3(root
, freelist
);
1391 case PAGE_MODE_4_LEVEL
:
1392 freelist
= free_pt_l4(root
, freelist
);
1394 case PAGE_MODE_5_LEVEL
:
1395 freelist
= free_pt_l5(root
, freelist
);
1397 case PAGE_MODE_6_LEVEL
:
1398 freelist
= free_pt_l6(root
, freelist
);
1407 static void free_pagetable(struct protection_domain
*domain
)
1409 unsigned long root
= (unsigned long)domain
->pt_root
;
1410 struct page
*freelist
= NULL
;
1412 BUG_ON(domain
->mode
< PAGE_MODE_NONE
||
1413 domain
->mode
> PAGE_MODE_6_LEVEL
);
1415 free_sub_pt(root
, domain
->mode
, freelist
);
1417 free_page_list(freelist
);
1421 * This function is used to add another level to an IO page table. Adding
1422 * another level increases the size of the address space by 9 bits to a size up
1425 static bool increase_address_space(struct protection_domain
*domain
,
1430 if (domain
->mode
== PAGE_MODE_6_LEVEL
)
1431 /* address space already 64 bit large */
1434 pte
= (void *)get_zeroed_page(gfp
);
1438 *pte
= PM_LEVEL_PDE(domain
->mode
,
1439 iommu_virt_to_phys(domain
->pt_root
));
1440 domain
->pt_root
= pte
;
1442 domain
->updated
= true;
1447 static u64
*alloc_pte(struct protection_domain
*domain
,
1448 unsigned long address
,
1449 unsigned long page_size
,
1456 BUG_ON(!is_power_of_2(page_size
));
1458 while (address
> PM_LEVEL_SIZE(domain
->mode
))
1459 increase_address_space(domain
, gfp
);
1461 level
= domain
->mode
- 1;
1462 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1463 address
= PAGE_SIZE_ALIGN(address
, page_size
);
1464 end_lvl
= PAGE_SIZE_LEVEL(page_size
);
1466 while (level
> end_lvl
) {
1471 pte_level
= PM_PTE_LEVEL(__pte
);
1473 if (!IOMMU_PTE_PRESENT(__pte
) ||
1474 pte_level
== PAGE_MODE_7_LEVEL
) {
1475 page
= (u64
*)get_zeroed_page(gfp
);
1479 __npte
= PM_LEVEL_PDE(level
, iommu_virt_to_phys(page
));
1481 /* pte could have been changed somewhere. */
1482 if (cmpxchg64(pte
, __pte
, __npte
) != __pte
)
1483 free_page((unsigned long)page
);
1484 else if (pte_level
== PAGE_MODE_7_LEVEL
)
1485 domain
->updated
= true;
1490 /* No level skipping support yet */
1491 if (pte_level
!= level
)
1496 pte
= IOMMU_PTE_PAGE(__pte
);
1498 if (pte_page
&& level
== end_lvl
)
1501 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1508 * This function checks if there is a PTE for a given dma address. If
1509 * there is one, it returns the pointer to it.
1511 static u64
*fetch_pte(struct protection_domain
*domain
,
1512 unsigned long address
,
1513 unsigned long *page_size
)
1520 if (address
> PM_LEVEL_SIZE(domain
->mode
))
1523 level
= domain
->mode
- 1;
1524 pte
= &domain
->pt_root
[PM_LEVEL_INDEX(level
, address
)];
1525 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1530 if (!IOMMU_PTE_PRESENT(*pte
))
1534 if (PM_PTE_LEVEL(*pte
) == 7 ||
1535 PM_PTE_LEVEL(*pte
) == 0)
1538 /* No level skipping support yet */
1539 if (PM_PTE_LEVEL(*pte
) != level
)
1544 /* Walk to the next level */
1545 pte
= IOMMU_PTE_PAGE(*pte
);
1546 pte
= &pte
[PM_LEVEL_INDEX(level
, address
)];
1547 *page_size
= PTE_LEVEL_PAGE_SIZE(level
);
1550 if (PM_PTE_LEVEL(*pte
) == 0x07) {
1551 unsigned long pte_mask
;
1554 * If we have a series of large PTEs, make
1555 * sure to return a pointer to the first one.
1557 *page_size
= pte_mask
= PTE_PAGE_SIZE(*pte
);
1558 pte_mask
= ~((PAGE_SIZE_PTE_COUNT(pte_mask
) << 3) - 1);
1559 pte
= (u64
*)(((unsigned long)pte
) & pte_mask
);
1565 static struct page
*free_clear_pte(u64
*pte
, u64 pteval
, struct page
*freelist
)
1570 while (cmpxchg64(pte
, pteval
, 0) != pteval
) {
1571 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1575 if (!IOMMU_PTE_PRESENT(pteval
))
1578 pt
= (unsigned long)IOMMU_PTE_PAGE(pteval
);
1579 mode
= IOMMU_PTE_MODE(pteval
);
1581 return free_sub_pt(pt
, mode
, freelist
);
1585 * Generic mapping functions. It maps a physical address into a DMA
1586 * address space. It allocates the page table pages if necessary.
1587 * In the future it can be extended to a generic mapping function
1588 * supporting all features of AMD IOMMU page tables like level skipping
1589 * and full 64 bit address spaces.
1591 static int iommu_map_page(struct protection_domain
*dom
,
1592 unsigned long bus_addr
,
1593 unsigned long phys_addr
,
1594 unsigned long page_size
,
1598 struct page
*freelist
= NULL
;
1602 BUG_ON(!IS_ALIGNED(bus_addr
, page_size
));
1603 BUG_ON(!IS_ALIGNED(phys_addr
, page_size
));
1605 if (!(prot
& IOMMU_PROT_MASK
))
1608 count
= PAGE_SIZE_PTE_COUNT(page_size
);
1609 pte
= alloc_pte(dom
, bus_addr
, page_size
, NULL
, gfp
);
1614 for (i
= 0; i
< count
; ++i
)
1615 freelist
= free_clear_pte(&pte
[i
], pte
[i
], freelist
);
1617 if (freelist
!= NULL
)
1618 dom
->updated
= true;
1621 __pte
= PAGE_SIZE_PTE(__sme_set(phys_addr
), page_size
);
1622 __pte
|= PM_LEVEL_ENC(7) | IOMMU_PTE_PR
| IOMMU_PTE_FC
;
1624 __pte
= __sme_set(phys_addr
) | IOMMU_PTE_PR
| IOMMU_PTE_FC
;
1626 if (prot
& IOMMU_PROT_IR
)
1627 __pte
|= IOMMU_PTE_IR
;
1628 if (prot
& IOMMU_PROT_IW
)
1629 __pte
|= IOMMU_PTE_IW
;
1631 for (i
= 0; i
< count
; ++i
)
1636 /* Everything flushed out, free pages now */
1637 free_page_list(freelist
);
1642 static unsigned long iommu_unmap_page(struct protection_domain
*dom
,
1643 unsigned long bus_addr
,
1644 unsigned long page_size
)
1646 unsigned long long unmapped
;
1647 unsigned long unmap_size
;
1650 BUG_ON(!is_power_of_2(page_size
));
1654 while (unmapped
< page_size
) {
1656 pte
= fetch_pte(dom
, bus_addr
, &unmap_size
);
1661 count
= PAGE_SIZE_PTE_COUNT(unmap_size
);
1662 for (i
= 0; i
< count
; i
++)
1666 bus_addr
= (bus_addr
& ~(unmap_size
- 1)) + unmap_size
;
1667 unmapped
+= unmap_size
;
1670 BUG_ON(unmapped
&& !is_power_of_2(unmapped
));
1675 /****************************************************************************
1677 * The next functions belong to the address allocator for the dma_ops
1678 * interface functions.
1680 ****************************************************************************/
1683 static unsigned long dma_ops_alloc_iova(struct device
*dev
,
1684 struct dma_ops_domain
*dma_dom
,
1685 unsigned int pages
, u64 dma_mask
)
1687 unsigned long pfn
= 0;
1689 pages
= __roundup_pow_of_two(pages
);
1691 if (dma_mask
> DMA_BIT_MASK(32))
1692 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1693 IOVA_PFN(DMA_BIT_MASK(32)), false);
1696 pfn
= alloc_iova_fast(&dma_dom
->iovad
, pages
,
1697 IOVA_PFN(dma_mask
), true);
1699 return (pfn
<< PAGE_SHIFT
);
1702 static void dma_ops_free_iova(struct dma_ops_domain
*dma_dom
,
1703 unsigned long address
,
1706 pages
= __roundup_pow_of_two(pages
);
1707 address
>>= PAGE_SHIFT
;
1709 free_iova_fast(&dma_dom
->iovad
, address
, pages
);
1712 /****************************************************************************
1714 * The next functions belong to the domain allocation. A domain is
1715 * allocated for every IOMMU as the default domain. If device isolation
1716 * is enabled, every device get its own domain. The most important thing
1717 * about domains is the page table mapping the DMA address space they
1720 ****************************************************************************/
1723 * This function adds a protection domain to the global protection domain list
1725 static void add_domain_to_list(struct protection_domain
*domain
)
1727 unsigned long flags
;
1729 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1730 list_add(&domain
->list
, &amd_iommu_pd_list
);
1731 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1735 * This function removes a protection domain to the global
1736 * protection domain list
1738 static void del_domain_from_list(struct protection_domain
*domain
)
1740 unsigned long flags
;
1742 spin_lock_irqsave(&amd_iommu_pd_lock
, flags
);
1743 list_del(&domain
->list
);
1744 spin_unlock_irqrestore(&amd_iommu_pd_lock
, flags
);
1747 static u16
domain_id_alloc(void)
1751 spin_lock(&pd_bitmap_lock
);
1752 id
= find_first_zero_bit(amd_iommu_pd_alloc_bitmap
, MAX_DOMAIN_ID
);
1754 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1755 __set_bit(id
, amd_iommu_pd_alloc_bitmap
);
1758 spin_unlock(&pd_bitmap_lock
);
1763 static void domain_id_free(int id
)
1765 spin_lock(&pd_bitmap_lock
);
1766 if (id
> 0 && id
< MAX_DOMAIN_ID
)
1767 __clear_bit(id
, amd_iommu_pd_alloc_bitmap
);
1768 spin_unlock(&pd_bitmap_lock
);
1771 static void free_gcr3_tbl_level1(u64
*tbl
)
1776 for (i
= 0; i
< 512; ++i
) {
1777 if (!(tbl
[i
] & GCR3_VALID
))
1780 ptr
= iommu_phys_to_virt(tbl
[i
] & PAGE_MASK
);
1782 free_page((unsigned long)ptr
);
1786 static void free_gcr3_tbl_level2(u64
*tbl
)
1791 for (i
= 0; i
< 512; ++i
) {
1792 if (!(tbl
[i
] & GCR3_VALID
))
1795 ptr
= iommu_phys_to_virt(tbl
[i
] & PAGE_MASK
);
1797 free_gcr3_tbl_level1(ptr
);
1801 static void free_gcr3_table(struct protection_domain
*domain
)
1803 if (domain
->glx
== 2)
1804 free_gcr3_tbl_level2(domain
->gcr3_tbl
);
1805 else if (domain
->glx
== 1)
1806 free_gcr3_tbl_level1(domain
->gcr3_tbl
);
1808 BUG_ON(domain
->glx
!= 0);
1810 free_page((unsigned long)domain
->gcr3_tbl
);
1813 static void dma_ops_domain_flush_tlb(struct dma_ops_domain
*dom
)
1815 domain_flush_tlb(&dom
->domain
);
1816 domain_flush_complete(&dom
->domain
);
1819 static void iova_domain_flush_tlb(struct iova_domain
*iovad
)
1821 struct dma_ops_domain
*dom
;
1823 dom
= container_of(iovad
, struct dma_ops_domain
, iovad
);
1825 dma_ops_domain_flush_tlb(dom
);
1829 * Free a domain, only used if something went wrong in the
1830 * allocation path and we need to free an already allocated page table
1832 static void dma_ops_domain_free(struct dma_ops_domain
*dom
)
1837 del_domain_from_list(&dom
->domain
);
1839 put_iova_domain(&dom
->iovad
);
1841 free_pagetable(&dom
->domain
);
1844 domain_id_free(dom
->domain
.id
);
1850 * Allocates a new protection domain usable for the dma_ops functions.
1851 * It also initializes the page table and the address allocator data
1852 * structures required for the dma_ops interface
1854 static struct dma_ops_domain
*dma_ops_domain_alloc(void)
1856 struct dma_ops_domain
*dma_dom
;
1858 dma_dom
= kzalloc(sizeof(struct dma_ops_domain
), GFP_KERNEL
);
1862 if (protection_domain_init(&dma_dom
->domain
))
1865 dma_dom
->domain
.mode
= PAGE_MODE_3_LEVEL
;
1866 dma_dom
->domain
.pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
1867 dma_dom
->domain
.flags
= PD_DMA_OPS_MASK
;
1868 if (!dma_dom
->domain
.pt_root
)
1871 init_iova_domain(&dma_dom
->iovad
, PAGE_SIZE
, IOVA_START_PFN
);
1873 if (init_iova_flush_queue(&dma_dom
->iovad
, iova_domain_flush_tlb
, NULL
))
1876 /* Initialize reserved ranges */
1877 copy_reserved_iova(&reserved_iova_ranges
, &dma_dom
->iovad
);
1879 add_domain_to_list(&dma_dom
->domain
);
1884 dma_ops_domain_free(dma_dom
);
1890 * little helper function to check whether a given protection domain is a
1893 static bool dma_ops_domain(struct protection_domain
*domain
)
1895 return domain
->flags
& PD_DMA_OPS_MASK
;
1898 static void set_dte_entry(u16 devid
, struct protection_domain
*domain
,
1904 if (domain
->mode
!= PAGE_MODE_NONE
)
1905 pte_root
= iommu_virt_to_phys(domain
->pt_root
);
1907 pte_root
|= (domain
->mode
& DEV_ENTRY_MODE_MASK
)
1908 << DEV_ENTRY_MODE_SHIFT
;
1909 pte_root
|= DTE_FLAG_IR
| DTE_FLAG_IW
| DTE_FLAG_V
| DTE_FLAG_TV
;
1911 flags
= amd_iommu_dev_table
[devid
].data
[1];
1914 flags
|= DTE_FLAG_IOTLB
;
1917 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
1919 if (iommu_feature(iommu
, FEATURE_EPHSUP
))
1920 pte_root
|= 1ULL << DEV_ENTRY_PPR
;
1923 if (domain
->flags
& PD_IOMMUV2_MASK
) {
1924 u64 gcr3
= iommu_virt_to_phys(domain
->gcr3_tbl
);
1925 u64 glx
= domain
->glx
;
1928 pte_root
|= DTE_FLAG_GV
;
1929 pte_root
|= (glx
& DTE_GLX_MASK
) << DTE_GLX_SHIFT
;
1931 /* First mask out possible old values for GCR3 table */
1932 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
1935 tmp
= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
1938 /* Encode GCR3 table into DTE */
1939 tmp
= DTE_GCR3_VAL_A(gcr3
) << DTE_GCR3_SHIFT_A
;
1942 tmp
= DTE_GCR3_VAL_B(gcr3
) << DTE_GCR3_SHIFT_B
;
1945 tmp
= DTE_GCR3_VAL_C(gcr3
) << DTE_GCR3_SHIFT_C
;
1949 flags
&= ~DEV_DOMID_MASK
;
1950 flags
|= domain
->id
;
1952 amd_iommu_dev_table
[devid
].data
[1] = flags
;
1953 amd_iommu_dev_table
[devid
].data
[0] = pte_root
;
1956 static void clear_dte_entry(u16 devid
)
1958 /* remove entry from the device table seen by the hardware */
1959 amd_iommu_dev_table
[devid
].data
[0] = DTE_FLAG_V
| DTE_FLAG_TV
;
1960 amd_iommu_dev_table
[devid
].data
[1] &= DTE_FLAG_MASK
;
1962 amd_iommu_apply_erratum_63(devid
);
1965 static void do_attach(struct iommu_dev_data
*dev_data
,
1966 struct protection_domain
*domain
)
1968 struct amd_iommu
*iommu
;
1972 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1973 alias
= dev_data
->alias
;
1974 ats
= dev_data
->ats
.enabled
;
1976 /* Update data structures */
1977 dev_data
->domain
= domain
;
1978 list_add(&dev_data
->list
, &domain
->dev_list
);
1980 /* Do reference counting */
1981 domain
->dev_iommu
[iommu
->index
] += 1;
1982 domain
->dev_cnt
+= 1;
1984 /* Update device table */
1985 set_dte_entry(dev_data
->devid
, domain
, ats
, dev_data
->iommu_v2
);
1986 if (alias
!= dev_data
->devid
)
1987 set_dte_entry(alias
, domain
, ats
, dev_data
->iommu_v2
);
1989 device_flush_dte(dev_data
);
1992 static void do_detach(struct iommu_dev_data
*dev_data
)
1994 struct amd_iommu
*iommu
;
1997 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
1998 alias
= dev_data
->alias
;
2000 /* decrease reference counters */
2001 dev_data
->domain
->dev_iommu
[iommu
->index
] -= 1;
2002 dev_data
->domain
->dev_cnt
-= 1;
2004 /* Update data structures */
2005 dev_data
->domain
= NULL
;
2006 list_del(&dev_data
->list
);
2007 clear_dte_entry(dev_data
->devid
);
2008 if (alias
!= dev_data
->devid
)
2009 clear_dte_entry(alias
);
2011 /* Flush the DTE entry */
2012 device_flush_dte(dev_data
);
2016 * If a device is not yet associated with a domain, this function makes the
2017 * device visible in the domain
2019 static int __attach_device(struct iommu_dev_data
*dev_data
,
2020 struct protection_domain
*domain
)
2025 spin_lock(&domain
->lock
);
2028 if (dev_data
->domain
!= NULL
)
2031 /* Attach alias group root */
2032 do_attach(dev_data
, domain
);
2039 spin_unlock(&domain
->lock
);
2045 static void pdev_iommuv2_disable(struct pci_dev
*pdev
)
2047 pci_disable_ats(pdev
);
2048 pci_disable_pri(pdev
);
2049 pci_disable_pasid(pdev
);
2052 /* FIXME: Change generic reset-function to do the same */
2053 static int pri_reset_while_enabled(struct pci_dev
*pdev
)
2058 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2062 pci_read_config_word(pdev
, pos
+ PCI_PRI_CTRL
, &control
);
2063 control
|= PCI_PRI_CTRL_RESET
;
2064 pci_write_config_word(pdev
, pos
+ PCI_PRI_CTRL
, control
);
2069 static int pdev_iommuv2_enable(struct pci_dev
*pdev
)
2074 /* FIXME: Hardcode number of outstanding requests for now */
2076 if (pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE
))
2078 reset_enable
= pdev_pri_erratum(pdev
, AMD_PRI_DEV_ERRATUM_ENABLE_RESET
);
2080 /* Only allow access to user-accessible pages */
2081 ret
= pci_enable_pasid(pdev
, 0);
2085 /* First reset the PRI state of the device */
2086 ret
= pci_reset_pri(pdev
);
2091 ret
= pci_enable_pri(pdev
, reqs
);
2096 ret
= pri_reset_while_enabled(pdev
);
2101 ret
= pci_enable_ats(pdev
, PAGE_SHIFT
);
2108 pci_disable_pri(pdev
);
2109 pci_disable_pasid(pdev
);
2114 /* FIXME: Move this to PCI code */
2115 #define PCI_PRI_TLP_OFF (1 << 15)
2117 static bool pci_pri_tlp_required(struct pci_dev
*pdev
)
2122 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
2126 pci_read_config_word(pdev
, pos
+ PCI_PRI_STATUS
, &status
);
2128 return (status
& PCI_PRI_TLP_OFF
) ? true : false;
2132 * If a device is not yet associated with a domain, this function makes the
2133 * device visible in the domain
2135 static int attach_device(struct device
*dev
,
2136 struct protection_domain
*domain
)
2138 struct pci_dev
*pdev
;
2139 struct iommu_dev_data
*dev_data
;
2140 unsigned long flags
;
2143 dev_data
= get_dev_data(dev
);
2145 if (!dev_is_pci(dev
))
2146 goto skip_ats_check
;
2148 pdev
= to_pci_dev(dev
);
2149 if (domain
->flags
& PD_IOMMUV2_MASK
) {
2150 if (!dev_data
->passthrough
)
2153 if (dev_data
->iommu_v2
) {
2154 if (pdev_iommuv2_enable(pdev
) != 0)
2157 dev_data
->ats
.enabled
= true;
2158 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2159 dev_data
->pri_tlp
= pci_pri_tlp_required(pdev
);
2161 } else if (amd_iommu_iotlb_sup
&&
2162 pci_enable_ats(pdev
, PAGE_SHIFT
) == 0) {
2163 dev_data
->ats
.enabled
= true;
2164 dev_data
->ats
.qdep
= pci_ats_queue_depth(pdev
);
2168 spin_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2169 ret
= __attach_device(dev_data
, domain
);
2170 spin_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2173 * We might boot into a crash-kernel here. The crashed kernel
2174 * left the caches in the IOMMU dirty. So we have to flush
2175 * here to evict all dirty stuff.
2177 domain_flush_tlb_pde(domain
);
2183 * Removes a device from a protection domain (unlocked)
2185 static void __detach_device(struct iommu_dev_data
*dev_data
)
2187 struct protection_domain
*domain
;
2189 domain
= dev_data
->domain
;
2191 spin_lock(&domain
->lock
);
2193 do_detach(dev_data
);
2195 spin_unlock(&domain
->lock
);
2199 * Removes a device from a protection domain (with devtable_lock held)
2201 static void detach_device(struct device
*dev
)
2203 struct protection_domain
*domain
;
2204 struct iommu_dev_data
*dev_data
;
2205 unsigned long flags
;
2207 dev_data
= get_dev_data(dev
);
2208 domain
= dev_data
->domain
;
2211 * First check if the device is still attached. It might already
2212 * be detached from its domain because the generic
2213 * iommu_detach_group code detached it and we try again here in
2214 * our alias handling.
2216 if (WARN_ON(!dev_data
->domain
))
2219 /* lock device table */
2220 spin_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2221 __detach_device(dev_data
);
2222 spin_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2224 if (!dev_is_pci(dev
))
2227 if (domain
->flags
& PD_IOMMUV2_MASK
&& dev_data
->iommu_v2
)
2228 pdev_iommuv2_disable(to_pci_dev(dev
));
2229 else if (dev_data
->ats
.enabled
)
2230 pci_disable_ats(to_pci_dev(dev
));
2232 dev_data
->ats
.enabled
= false;
2235 static int amd_iommu_add_device(struct device
*dev
)
2237 struct iommu_dev_data
*dev_data
;
2238 struct iommu_domain
*domain
;
2239 struct amd_iommu
*iommu
;
2242 if (!check_device(dev
) || get_dev_data(dev
))
2245 devid
= get_device_id(dev
);
2249 iommu
= amd_iommu_rlookup_table
[devid
];
2251 ret
= iommu_init_device(dev
);
2253 if (ret
!= -ENOTSUPP
)
2254 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2257 iommu_ignore_device(dev
);
2258 dev
->dma_ops
= NULL
;
2261 init_iommu_group(dev
);
2263 dev_data
= get_dev_data(dev
);
2267 if (iommu_pass_through
|| dev_data
->iommu_v2
)
2268 iommu_request_dm_for_dev(dev
);
2270 /* Domains are initialized for this device - have a look what we ended up with */
2271 domain
= iommu_get_domain_for_dev(dev
);
2272 if (domain
->type
== IOMMU_DOMAIN_IDENTITY
)
2273 dev_data
->passthrough
= true;
2275 dev
->dma_ops
= &amd_iommu_dma_ops
;
2278 iommu_completion_wait(iommu
);
2283 static void amd_iommu_remove_device(struct device
*dev
)
2285 struct amd_iommu
*iommu
;
2288 if (!check_device(dev
))
2291 devid
= get_device_id(dev
);
2295 iommu
= amd_iommu_rlookup_table
[devid
];
2297 iommu_uninit_device(dev
);
2298 iommu_completion_wait(iommu
);
2301 static struct iommu_group
*amd_iommu_device_group(struct device
*dev
)
2303 if (dev_is_pci(dev
))
2304 return pci_device_group(dev
);
2306 return acpihid_device_group(dev
);
2309 /*****************************************************************************
2311 * The next functions belong to the dma_ops mapping/unmapping code.
2313 *****************************************************************************/
2316 * In the dma_ops path we only have the struct device. This function
2317 * finds the corresponding IOMMU, the protection domain and the
2318 * requestor id for a given device.
2319 * If the device is not yet associated with a domain this is also done
2322 static struct protection_domain
*get_domain(struct device
*dev
)
2324 struct protection_domain
*domain
;
2325 struct iommu_domain
*io_domain
;
2327 if (!check_device(dev
))
2328 return ERR_PTR(-EINVAL
);
2330 domain
= get_dev_data(dev
)->domain
;
2331 if (domain
== NULL
&& get_dev_data(dev
)->defer_attach
) {
2332 get_dev_data(dev
)->defer_attach
= false;
2333 io_domain
= iommu_get_domain_for_dev(dev
);
2334 domain
= to_pdomain(io_domain
);
2335 attach_device(dev
, domain
);
2338 return ERR_PTR(-EBUSY
);
2340 if (!dma_ops_domain(domain
))
2341 return ERR_PTR(-EBUSY
);
2346 static void update_device_table(struct protection_domain
*domain
)
2348 struct iommu_dev_data
*dev_data
;
2350 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
2351 set_dte_entry(dev_data
->devid
, domain
, dev_data
->ats
.enabled
,
2352 dev_data
->iommu_v2
);
2354 if (dev_data
->devid
== dev_data
->alias
)
2357 /* There is an alias, update device table entry for it */
2358 set_dte_entry(dev_data
->alias
, domain
, dev_data
->ats
.enabled
,
2359 dev_data
->iommu_v2
);
2363 static void update_domain(struct protection_domain
*domain
)
2365 if (!domain
->updated
)
2368 update_device_table(domain
);
2370 domain_flush_devices(domain
);
2371 domain_flush_tlb_pde(domain
);
2373 domain
->updated
= false;
2376 static int dir2prot(enum dma_data_direction direction
)
2378 if (direction
== DMA_TO_DEVICE
)
2379 return IOMMU_PROT_IR
;
2380 else if (direction
== DMA_FROM_DEVICE
)
2381 return IOMMU_PROT_IW
;
2382 else if (direction
== DMA_BIDIRECTIONAL
)
2383 return IOMMU_PROT_IW
| IOMMU_PROT_IR
;
2389 * This function contains common code for mapping of a physically
2390 * contiguous memory region into DMA address space. It is used by all
2391 * mapping functions provided with this IOMMU driver.
2392 * Must be called with the domain lock held.
2394 static dma_addr_t
__map_single(struct device
*dev
,
2395 struct dma_ops_domain
*dma_dom
,
2398 enum dma_data_direction direction
,
2401 dma_addr_t offset
= paddr
& ~PAGE_MASK
;
2402 dma_addr_t address
, start
, ret
;
2407 pages
= iommu_num_pages(paddr
, size
, PAGE_SIZE
);
2410 address
= dma_ops_alloc_iova(dev
, dma_dom
, pages
, dma_mask
);
2414 prot
= dir2prot(direction
);
2417 for (i
= 0; i
< pages
; ++i
) {
2418 ret
= iommu_map_page(&dma_dom
->domain
, start
, paddr
,
2419 PAGE_SIZE
, prot
, GFP_ATOMIC
);
2428 if (unlikely(amd_iommu_np_cache
)) {
2429 domain_flush_pages(&dma_dom
->domain
, address
, size
);
2430 domain_flush_complete(&dma_dom
->domain
);
2438 for (--i
; i
>= 0; --i
) {
2440 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2443 domain_flush_tlb(&dma_dom
->domain
);
2444 domain_flush_complete(&dma_dom
->domain
);
2446 dma_ops_free_iova(dma_dom
, address
, pages
);
2448 return DMA_MAPPING_ERROR
;
2452 * Does the reverse of the __map_single function. Must be called with
2453 * the domain lock held too
2455 static void __unmap_single(struct dma_ops_domain
*dma_dom
,
2456 dma_addr_t dma_addr
,
2460 dma_addr_t i
, start
;
2463 pages
= iommu_num_pages(dma_addr
, size
, PAGE_SIZE
);
2464 dma_addr
&= PAGE_MASK
;
2467 for (i
= 0; i
< pages
; ++i
) {
2468 iommu_unmap_page(&dma_dom
->domain
, start
, PAGE_SIZE
);
2472 if (amd_iommu_unmap_flush
) {
2473 domain_flush_tlb(&dma_dom
->domain
);
2474 domain_flush_complete(&dma_dom
->domain
);
2475 dma_ops_free_iova(dma_dom
, dma_addr
, pages
);
2477 pages
= __roundup_pow_of_two(pages
);
2478 queue_iova(&dma_dom
->iovad
, dma_addr
>> PAGE_SHIFT
, pages
, 0);
2483 * The exported map_single function for dma_ops.
2485 static dma_addr_t
map_page(struct device
*dev
, struct page
*page
,
2486 unsigned long offset
, size_t size
,
2487 enum dma_data_direction dir
,
2488 unsigned long attrs
)
2490 phys_addr_t paddr
= page_to_phys(page
) + offset
;
2491 struct protection_domain
*domain
;
2492 struct dma_ops_domain
*dma_dom
;
2495 domain
= get_domain(dev
);
2496 if (PTR_ERR(domain
) == -EINVAL
)
2497 return (dma_addr_t
)paddr
;
2498 else if (IS_ERR(domain
))
2499 return DMA_MAPPING_ERROR
;
2501 dma_mask
= *dev
->dma_mask
;
2502 dma_dom
= to_dma_ops_domain(domain
);
2504 return __map_single(dev
, dma_dom
, paddr
, size
, dir
, dma_mask
);
2508 * The exported unmap_single function for dma_ops.
2510 static void unmap_page(struct device
*dev
, dma_addr_t dma_addr
, size_t size
,
2511 enum dma_data_direction dir
, unsigned long attrs
)
2513 struct protection_domain
*domain
;
2514 struct dma_ops_domain
*dma_dom
;
2516 domain
= get_domain(dev
);
2520 dma_dom
= to_dma_ops_domain(domain
);
2522 __unmap_single(dma_dom
, dma_addr
, size
, dir
);
2525 static int sg_num_pages(struct device
*dev
,
2526 struct scatterlist
*sglist
,
2529 unsigned long mask
, boundary_size
;
2530 struct scatterlist
*s
;
2533 mask
= dma_get_seg_boundary(dev
);
2534 boundary_size
= mask
+ 1 ? ALIGN(mask
+ 1, PAGE_SIZE
) >> PAGE_SHIFT
:
2535 1UL << (BITS_PER_LONG
- PAGE_SHIFT
);
2537 for_each_sg(sglist
, s
, nelems
, i
) {
2540 s
->dma_address
= npages
<< PAGE_SHIFT
;
2541 p
= npages
% boundary_size
;
2542 n
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2543 if (p
+ n
> boundary_size
)
2544 npages
+= boundary_size
- p
;
2552 * The exported map_sg function for dma_ops (handles scatter-gather
2555 static int map_sg(struct device
*dev
, struct scatterlist
*sglist
,
2556 int nelems
, enum dma_data_direction direction
,
2557 unsigned long attrs
)
2559 int mapped_pages
= 0, npages
= 0, prot
= 0, i
;
2560 struct protection_domain
*domain
;
2561 struct dma_ops_domain
*dma_dom
;
2562 struct scatterlist
*s
;
2563 unsigned long address
;
2566 domain
= get_domain(dev
);
2570 dma_dom
= to_dma_ops_domain(domain
);
2571 dma_mask
= *dev
->dma_mask
;
2573 npages
= sg_num_pages(dev
, sglist
, nelems
);
2575 address
= dma_ops_alloc_iova(dev
, dma_dom
, npages
, dma_mask
);
2576 if (address
== DMA_MAPPING_ERROR
)
2579 prot
= dir2prot(direction
);
2581 /* Map all sg entries */
2582 for_each_sg(sglist
, s
, nelems
, i
) {
2583 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2585 for (j
= 0; j
< pages
; ++j
) {
2586 unsigned long bus_addr
, phys_addr
;
2589 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2590 phys_addr
= (sg_phys(s
) & PAGE_MASK
) + (j
<< PAGE_SHIFT
);
2591 ret
= iommu_map_page(domain
, bus_addr
, phys_addr
, PAGE_SIZE
, prot
, GFP_ATOMIC
);
2599 /* Everything is mapped - write the right values into s->dma_address */
2600 for_each_sg(sglist
, s
, nelems
, i
) {
2601 s
->dma_address
+= address
+ s
->offset
;
2602 s
->dma_length
= s
->length
;
2608 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2609 dev_name(dev
), npages
);
2611 for_each_sg(sglist
, s
, nelems
, i
) {
2612 int j
, pages
= iommu_num_pages(sg_phys(s
), s
->length
, PAGE_SIZE
);
2614 for (j
= 0; j
< pages
; ++j
) {
2615 unsigned long bus_addr
;
2617 bus_addr
= address
+ s
->dma_address
+ (j
<< PAGE_SHIFT
);
2618 iommu_unmap_page(domain
, bus_addr
, PAGE_SIZE
);
2626 free_iova_fast(&dma_dom
->iovad
, address
, npages
);
2633 * The exported map_sg function for dma_ops (handles scatter-gather
2636 static void unmap_sg(struct device
*dev
, struct scatterlist
*sglist
,
2637 int nelems
, enum dma_data_direction dir
,
2638 unsigned long attrs
)
2640 struct protection_domain
*domain
;
2641 struct dma_ops_domain
*dma_dom
;
2642 unsigned long startaddr
;
2645 domain
= get_domain(dev
);
2649 startaddr
= sg_dma_address(sglist
) & PAGE_MASK
;
2650 dma_dom
= to_dma_ops_domain(domain
);
2651 npages
= sg_num_pages(dev
, sglist
, nelems
);
2653 __unmap_single(dma_dom
, startaddr
, npages
<< PAGE_SHIFT
, dir
);
2657 * The exported alloc_coherent function for dma_ops.
2659 static void *alloc_coherent(struct device
*dev
, size_t size
,
2660 dma_addr_t
*dma_addr
, gfp_t flag
,
2661 unsigned long attrs
)
2663 u64 dma_mask
= dev
->coherent_dma_mask
;
2664 struct protection_domain
*domain
;
2665 struct dma_ops_domain
*dma_dom
;
2668 domain
= get_domain(dev
);
2669 if (PTR_ERR(domain
) == -EINVAL
) {
2670 page
= alloc_pages(flag
, get_order(size
));
2671 *dma_addr
= page_to_phys(page
);
2672 return page_address(page
);
2673 } else if (IS_ERR(domain
))
2676 dma_dom
= to_dma_ops_domain(domain
);
2677 size
= PAGE_ALIGN(size
);
2678 dma_mask
= dev
->coherent_dma_mask
;
2679 flag
&= ~(__GFP_DMA
| __GFP_HIGHMEM
| __GFP_DMA32
);
2682 page
= alloc_pages(flag
| __GFP_NOWARN
, get_order(size
));
2684 if (!gfpflags_allow_blocking(flag
))
2687 page
= dma_alloc_from_contiguous(dev
, size
>> PAGE_SHIFT
,
2688 get_order(size
), flag
& __GFP_NOWARN
);
2694 dma_mask
= *dev
->dma_mask
;
2696 *dma_addr
= __map_single(dev
, dma_dom
, page_to_phys(page
),
2697 size
, DMA_BIDIRECTIONAL
, dma_mask
);
2699 if (*dma_addr
== DMA_MAPPING_ERROR
)
2702 return page_address(page
);
2706 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2707 __free_pages(page
, get_order(size
));
2713 * The exported free_coherent function for dma_ops.
2715 static void free_coherent(struct device
*dev
, size_t size
,
2716 void *virt_addr
, dma_addr_t dma_addr
,
2717 unsigned long attrs
)
2719 struct protection_domain
*domain
;
2720 struct dma_ops_domain
*dma_dom
;
2723 page
= virt_to_page(virt_addr
);
2724 size
= PAGE_ALIGN(size
);
2726 domain
= get_domain(dev
);
2730 dma_dom
= to_dma_ops_domain(domain
);
2732 __unmap_single(dma_dom
, dma_addr
, size
, DMA_BIDIRECTIONAL
);
2735 if (!dma_release_from_contiguous(dev
, page
, size
>> PAGE_SHIFT
))
2736 __free_pages(page
, get_order(size
));
2740 * This function is called by the DMA layer to find out if we can handle a
2741 * particular device. It is part of the dma_ops.
2743 static int amd_iommu_dma_supported(struct device
*dev
, u64 mask
)
2745 if (!dma_direct_supported(dev
, mask
))
2747 return check_device(dev
);
2750 static const struct dma_map_ops amd_iommu_dma_ops
= {
2751 .alloc
= alloc_coherent
,
2752 .free
= free_coherent
,
2753 .map_page
= map_page
,
2754 .unmap_page
= unmap_page
,
2756 .unmap_sg
= unmap_sg
,
2757 .dma_supported
= amd_iommu_dma_supported
,
2760 static int init_reserved_iova_ranges(void)
2762 struct pci_dev
*pdev
= NULL
;
2765 init_iova_domain(&reserved_iova_ranges
, PAGE_SIZE
, IOVA_START_PFN
);
2767 lockdep_set_class(&reserved_iova_ranges
.iova_rbtree_lock
,
2768 &reserved_rbtree_key
);
2770 /* MSI memory range */
2771 val
= reserve_iova(&reserved_iova_ranges
,
2772 IOVA_PFN(MSI_RANGE_START
), IOVA_PFN(MSI_RANGE_END
));
2774 pr_err("Reserving MSI range failed\n");
2778 /* HT memory range */
2779 val
= reserve_iova(&reserved_iova_ranges
,
2780 IOVA_PFN(HT_RANGE_START
), IOVA_PFN(HT_RANGE_END
));
2782 pr_err("Reserving HT range failed\n");
2787 * Memory used for PCI resources
2788 * FIXME: Check whether we can reserve the PCI-hole completly
2790 for_each_pci_dev(pdev
) {
2793 for (i
= 0; i
< PCI_NUM_RESOURCES
; ++i
) {
2794 struct resource
*r
= &pdev
->resource
[i
];
2796 if (!(r
->flags
& IORESOURCE_MEM
))
2799 val
= reserve_iova(&reserved_iova_ranges
,
2803 pr_err("Reserve pci-resource range failed\n");
2812 int __init
amd_iommu_init_api(void)
2816 ret
= iova_cache_get();
2820 ret
= init_reserved_iova_ranges();
2824 err
= bus_set_iommu(&pci_bus_type
, &amd_iommu_ops
);
2827 #ifdef CONFIG_ARM_AMBA
2828 err
= bus_set_iommu(&amba_bustype
, &amd_iommu_ops
);
2832 err
= bus_set_iommu(&platform_bus_type
, &amd_iommu_ops
);
2839 int __init
amd_iommu_init_dma_ops(void)
2841 swiotlb
= (iommu_pass_through
|| sme_me_mask
) ? 1 : 0;
2844 if (amd_iommu_unmap_flush
)
2845 pr_info("IO/TLB flush on unmap enabled\n");
2847 pr_info("Lazy IO/TLB flushing enabled\n");
2853 /*****************************************************************************
2855 * The following functions belong to the exported interface of AMD IOMMU
2857 * This interface allows access to lower level functions of the IOMMU
2858 * like protection domain handling and assignement of devices to domains
2859 * which is not possible with the dma_ops interface.
2861 *****************************************************************************/
2863 static void cleanup_domain(struct protection_domain
*domain
)
2865 struct iommu_dev_data
*entry
;
2866 unsigned long flags
;
2868 spin_lock_irqsave(&amd_iommu_devtable_lock
, flags
);
2870 while (!list_empty(&domain
->dev_list
)) {
2871 entry
= list_first_entry(&domain
->dev_list
,
2872 struct iommu_dev_data
, list
);
2873 BUG_ON(!entry
->domain
);
2874 __detach_device(entry
);
2877 spin_unlock_irqrestore(&amd_iommu_devtable_lock
, flags
);
2880 static void protection_domain_free(struct protection_domain
*domain
)
2885 del_domain_from_list(domain
);
2888 domain_id_free(domain
->id
);
2893 static int protection_domain_init(struct protection_domain
*domain
)
2895 spin_lock_init(&domain
->lock
);
2896 mutex_init(&domain
->api_lock
);
2897 domain
->id
= domain_id_alloc();
2900 INIT_LIST_HEAD(&domain
->dev_list
);
2905 static struct protection_domain
*protection_domain_alloc(void)
2907 struct protection_domain
*domain
;
2909 domain
= kzalloc(sizeof(*domain
), GFP_KERNEL
);
2913 if (protection_domain_init(domain
))
2916 add_domain_to_list(domain
);
2926 static struct iommu_domain
*amd_iommu_domain_alloc(unsigned type
)
2928 struct protection_domain
*pdomain
;
2929 struct dma_ops_domain
*dma_domain
;
2932 case IOMMU_DOMAIN_UNMANAGED
:
2933 pdomain
= protection_domain_alloc();
2937 pdomain
->mode
= PAGE_MODE_3_LEVEL
;
2938 pdomain
->pt_root
= (void *)get_zeroed_page(GFP_KERNEL
);
2939 if (!pdomain
->pt_root
) {
2940 protection_domain_free(pdomain
);
2944 pdomain
->domain
.geometry
.aperture_start
= 0;
2945 pdomain
->domain
.geometry
.aperture_end
= ~0ULL;
2946 pdomain
->domain
.geometry
.force_aperture
= true;
2949 case IOMMU_DOMAIN_DMA
:
2950 dma_domain
= dma_ops_domain_alloc();
2952 pr_err("Failed to allocate\n");
2955 pdomain
= &dma_domain
->domain
;
2957 case IOMMU_DOMAIN_IDENTITY
:
2958 pdomain
= protection_domain_alloc();
2962 pdomain
->mode
= PAGE_MODE_NONE
;
2968 return &pdomain
->domain
;
2971 static void amd_iommu_domain_free(struct iommu_domain
*dom
)
2973 struct protection_domain
*domain
;
2974 struct dma_ops_domain
*dma_dom
;
2976 domain
= to_pdomain(dom
);
2978 if (domain
->dev_cnt
> 0)
2979 cleanup_domain(domain
);
2981 BUG_ON(domain
->dev_cnt
!= 0);
2986 switch (dom
->type
) {
2987 case IOMMU_DOMAIN_DMA
:
2988 /* Now release the domain */
2989 dma_dom
= to_dma_ops_domain(domain
);
2990 dma_ops_domain_free(dma_dom
);
2993 if (domain
->mode
!= PAGE_MODE_NONE
)
2994 free_pagetable(domain
);
2996 if (domain
->flags
& PD_IOMMUV2_MASK
)
2997 free_gcr3_table(domain
);
2999 protection_domain_free(domain
);
3004 static void amd_iommu_detach_device(struct iommu_domain
*dom
,
3007 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3008 struct amd_iommu
*iommu
;
3011 if (!check_device(dev
))
3014 devid
= get_device_id(dev
);
3018 if (dev_data
->domain
!= NULL
)
3021 iommu
= amd_iommu_rlookup_table
[devid
];
3025 #ifdef CONFIG_IRQ_REMAP
3026 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) &&
3027 (dom
->type
== IOMMU_DOMAIN_UNMANAGED
))
3028 dev_data
->use_vapic
= 0;
3031 iommu_completion_wait(iommu
);
3034 static int amd_iommu_attach_device(struct iommu_domain
*dom
,
3037 struct protection_domain
*domain
= to_pdomain(dom
);
3038 struct iommu_dev_data
*dev_data
;
3039 struct amd_iommu
*iommu
;
3042 if (!check_device(dev
))
3045 dev_data
= dev
->archdata
.iommu
;
3047 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3051 if (dev_data
->domain
)
3054 ret
= attach_device(dev
, domain
);
3056 #ifdef CONFIG_IRQ_REMAP
3057 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
3058 if (dom
->type
== IOMMU_DOMAIN_UNMANAGED
)
3059 dev_data
->use_vapic
= 1;
3061 dev_data
->use_vapic
= 0;
3065 iommu_completion_wait(iommu
);
3070 static int amd_iommu_map(struct iommu_domain
*dom
, unsigned long iova
,
3071 phys_addr_t paddr
, size_t page_size
, int iommu_prot
)
3073 struct protection_domain
*domain
= to_pdomain(dom
);
3077 if (domain
->mode
== PAGE_MODE_NONE
)
3080 if (iommu_prot
& IOMMU_READ
)
3081 prot
|= IOMMU_PROT_IR
;
3082 if (iommu_prot
& IOMMU_WRITE
)
3083 prot
|= IOMMU_PROT_IW
;
3085 mutex_lock(&domain
->api_lock
);
3086 ret
= iommu_map_page(domain
, iova
, paddr
, page_size
, prot
, GFP_KERNEL
);
3087 mutex_unlock(&domain
->api_lock
);
3092 static size_t amd_iommu_unmap(struct iommu_domain
*dom
, unsigned long iova
,
3095 struct protection_domain
*domain
= to_pdomain(dom
);
3098 if (domain
->mode
== PAGE_MODE_NONE
)
3101 mutex_lock(&domain
->api_lock
);
3102 unmap_size
= iommu_unmap_page(domain
, iova
, page_size
);
3103 mutex_unlock(&domain
->api_lock
);
3108 static phys_addr_t
amd_iommu_iova_to_phys(struct iommu_domain
*dom
,
3111 struct protection_domain
*domain
= to_pdomain(dom
);
3112 unsigned long offset_mask
, pte_pgsize
;
3115 if (domain
->mode
== PAGE_MODE_NONE
)
3118 pte
= fetch_pte(domain
, iova
, &pte_pgsize
);
3120 if (!pte
|| !IOMMU_PTE_PRESENT(*pte
))
3123 offset_mask
= pte_pgsize
- 1;
3124 __pte
= __sme_clr(*pte
& PM_ADDR_MASK
);
3126 return (__pte
& ~offset_mask
) | (iova
& offset_mask
);
3129 static bool amd_iommu_capable(enum iommu_cap cap
)
3132 case IOMMU_CAP_CACHE_COHERENCY
:
3134 case IOMMU_CAP_INTR_REMAP
:
3135 return (irq_remapping_enabled
== 1);
3136 case IOMMU_CAP_NOEXEC
:
3145 static void amd_iommu_get_resv_regions(struct device
*dev
,
3146 struct list_head
*head
)
3148 struct iommu_resv_region
*region
;
3149 struct unity_map_entry
*entry
;
3152 devid
= get_device_id(dev
);
3156 list_for_each_entry(entry
, &amd_iommu_unity_map
, list
) {
3160 if (devid
< entry
->devid_start
|| devid
> entry
->devid_end
)
3163 length
= entry
->address_end
- entry
->address_start
;
3164 if (entry
->prot
& IOMMU_PROT_IR
)
3166 if (entry
->prot
& IOMMU_PROT_IW
)
3167 prot
|= IOMMU_WRITE
;
3169 region
= iommu_alloc_resv_region(entry
->address_start
,
3173 pr_err("Out of memory allocating dm-regions for %s\n",
3177 list_add_tail(®ion
->list
, head
);
3180 region
= iommu_alloc_resv_region(MSI_RANGE_START
,
3181 MSI_RANGE_END
- MSI_RANGE_START
+ 1,
3185 list_add_tail(®ion
->list
, head
);
3187 region
= iommu_alloc_resv_region(HT_RANGE_START
,
3188 HT_RANGE_END
- HT_RANGE_START
+ 1,
3189 0, IOMMU_RESV_RESERVED
);
3192 list_add_tail(®ion
->list
, head
);
3195 static void amd_iommu_put_resv_regions(struct device
*dev
,
3196 struct list_head
*head
)
3198 struct iommu_resv_region
*entry
, *next
;
3200 list_for_each_entry_safe(entry
, next
, head
, list
)
3204 static void amd_iommu_apply_resv_region(struct device
*dev
,
3205 struct iommu_domain
*domain
,
3206 struct iommu_resv_region
*region
)
3208 struct dma_ops_domain
*dma_dom
= to_dma_ops_domain(to_pdomain(domain
));
3209 unsigned long start
, end
;
3211 start
= IOVA_PFN(region
->start
);
3212 end
= IOVA_PFN(region
->start
+ region
->length
- 1);
3214 WARN_ON_ONCE(reserve_iova(&dma_dom
->iovad
, start
, end
) == NULL
);
3217 static bool amd_iommu_is_attach_deferred(struct iommu_domain
*domain
,
3220 struct iommu_dev_data
*dev_data
= dev
->archdata
.iommu
;
3221 return dev_data
->defer_attach
;
3224 static void amd_iommu_flush_iotlb_all(struct iommu_domain
*domain
)
3226 struct protection_domain
*dom
= to_pdomain(domain
);
3228 domain_flush_tlb_pde(dom
);
3229 domain_flush_complete(dom
);
3232 static void amd_iommu_iotlb_range_add(struct iommu_domain
*domain
,
3233 unsigned long iova
, size_t size
)
3237 const struct iommu_ops amd_iommu_ops
= {
3238 .capable
= amd_iommu_capable
,
3239 .domain_alloc
= amd_iommu_domain_alloc
,
3240 .domain_free
= amd_iommu_domain_free
,
3241 .attach_dev
= amd_iommu_attach_device
,
3242 .detach_dev
= amd_iommu_detach_device
,
3243 .map
= amd_iommu_map
,
3244 .unmap
= amd_iommu_unmap
,
3245 .iova_to_phys
= amd_iommu_iova_to_phys
,
3246 .add_device
= amd_iommu_add_device
,
3247 .remove_device
= amd_iommu_remove_device
,
3248 .device_group
= amd_iommu_device_group
,
3249 .get_resv_regions
= amd_iommu_get_resv_regions
,
3250 .put_resv_regions
= amd_iommu_put_resv_regions
,
3251 .apply_resv_region
= amd_iommu_apply_resv_region
,
3252 .is_attach_deferred
= amd_iommu_is_attach_deferred
,
3253 .pgsize_bitmap
= AMD_IOMMU_PGSIZES
,
3254 .flush_iotlb_all
= amd_iommu_flush_iotlb_all
,
3255 .iotlb_range_add
= amd_iommu_iotlb_range_add
,
3256 .iotlb_sync
= amd_iommu_flush_iotlb_all
,
3259 /*****************************************************************************
3261 * The next functions do a basic initialization of IOMMU for pass through
3264 * In passthrough mode the IOMMU is initialized and enabled but not used for
3265 * DMA-API translation.
3267 *****************************************************************************/
3269 /* IOMMUv2 specific functions */
3270 int amd_iommu_register_ppr_notifier(struct notifier_block
*nb
)
3272 return atomic_notifier_chain_register(&ppr_notifier
, nb
);
3274 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier
);
3276 int amd_iommu_unregister_ppr_notifier(struct notifier_block
*nb
)
3278 return atomic_notifier_chain_unregister(&ppr_notifier
, nb
);
3280 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier
);
3282 void amd_iommu_domain_direct_map(struct iommu_domain
*dom
)
3284 struct protection_domain
*domain
= to_pdomain(dom
);
3285 unsigned long flags
;
3287 spin_lock_irqsave(&domain
->lock
, flags
);
3289 /* Update data structure */
3290 domain
->mode
= PAGE_MODE_NONE
;
3291 domain
->updated
= true;
3293 /* Make changes visible to IOMMUs */
3294 update_domain(domain
);
3296 /* Page-table is not visible to IOMMU anymore, so free it */
3297 free_pagetable(domain
);
3299 spin_unlock_irqrestore(&domain
->lock
, flags
);
3301 EXPORT_SYMBOL(amd_iommu_domain_direct_map
);
3303 int amd_iommu_domain_enable_v2(struct iommu_domain
*dom
, int pasids
)
3305 struct protection_domain
*domain
= to_pdomain(dom
);
3306 unsigned long flags
;
3309 if (pasids
<= 0 || pasids
> (PASID_MASK
+ 1))
3312 /* Number of GCR3 table levels required */
3313 for (levels
= 0; (pasids
- 1) & ~0x1ff; pasids
>>= 9)
3316 if (levels
> amd_iommu_max_glx_val
)
3319 spin_lock_irqsave(&domain
->lock
, flags
);
3322 * Save us all sanity checks whether devices already in the
3323 * domain support IOMMUv2. Just force that the domain has no
3324 * devices attached when it is switched into IOMMUv2 mode.
3327 if (domain
->dev_cnt
> 0 || domain
->flags
& PD_IOMMUV2_MASK
)
3331 domain
->gcr3_tbl
= (void *)get_zeroed_page(GFP_ATOMIC
);
3332 if (domain
->gcr3_tbl
== NULL
)
3335 domain
->glx
= levels
;
3336 domain
->flags
|= PD_IOMMUV2_MASK
;
3337 domain
->updated
= true;
3339 update_domain(domain
);
3344 spin_unlock_irqrestore(&domain
->lock
, flags
);
3348 EXPORT_SYMBOL(amd_iommu_domain_enable_v2
);
3350 static int __flush_pasid(struct protection_domain
*domain
, int pasid
,
3351 u64 address
, bool size
)
3353 struct iommu_dev_data
*dev_data
;
3354 struct iommu_cmd cmd
;
3357 if (!(domain
->flags
& PD_IOMMUV2_MASK
))
3360 build_inv_iommu_pasid(&cmd
, domain
->id
, pasid
, address
, size
);
3363 * IOMMU TLB needs to be flushed before Device TLB to
3364 * prevent device TLB refill from IOMMU TLB
3366 for (i
= 0; i
< amd_iommu_get_num_iommus(); ++i
) {
3367 if (domain
->dev_iommu
[i
] == 0)
3370 ret
= iommu_queue_command(amd_iommus
[i
], &cmd
);
3375 /* Wait until IOMMU TLB flushes are complete */
3376 domain_flush_complete(domain
);
3378 /* Now flush device TLBs */
3379 list_for_each_entry(dev_data
, &domain
->dev_list
, list
) {
3380 struct amd_iommu
*iommu
;
3384 There might be non-IOMMUv2 capable devices in an IOMMUv2
3387 if (!dev_data
->ats
.enabled
)
3390 qdep
= dev_data
->ats
.qdep
;
3391 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3393 build_inv_iotlb_pasid(&cmd
, dev_data
->devid
, pasid
,
3394 qdep
, address
, size
);
3396 ret
= iommu_queue_command(iommu
, &cmd
);
3401 /* Wait until all device TLBs are flushed */
3402 domain_flush_complete(domain
);
3411 static int __amd_iommu_flush_page(struct protection_domain
*domain
, int pasid
,
3414 return __flush_pasid(domain
, pasid
, address
, false);
3417 int amd_iommu_flush_page(struct iommu_domain
*dom
, int pasid
,
3420 struct protection_domain
*domain
= to_pdomain(dom
);
3421 unsigned long flags
;
3424 spin_lock_irqsave(&domain
->lock
, flags
);
3425 ret
= __amd_iommu_flush_page(domain
, pasid
, address
);
3426 spin_unlock_irqrestore(&domain
->lock
, flags
);
3430 EXPORT_SYMBOL(amd_iommu_flush_page
);
3432 static int __amd_iommu_flush_tlb(struct protection_domain
*domain
, int pasid
)
3434 return __flush_pasid(domain
, pasid
, CMD_INV_IOMMU_ALL_PAGES_ADDRESS
,
3438 int amd_iommu_flush_tlb(struct iommu_domain
*dom
, int pasid
)
3440 struct protection_domain
*domain
= to_pdomain(dom
);
3441 unsigned long flags
;
3444 spin_lock_irqsave(&domain
->lock
, flags
);
3445 ret
= __amd_iommu_flush_tlb(domain
, pasid
);
3446 spin_unlock_irqrestore(&domain
->lock
, flags
);
3450 EXPORT_SYMBOL(amd_iommu_flush_tlb
);
3452 static u64
*__get_gcr3_pte(u64
*root
, int level
, int pasid
, bool alloc
)
3459 index
= (pasid
>> (9 * level
)) & 0x1ff;
3465 if (!(*pte
& GCR3_VALID
)) {
3469 root
= (void *)get_zeroed_page(GFP_ATOMIC
);
3473 *pte
= iommu_virt_to_phys(root
) | GCR3_VALID
;
3476 root
= iommu_phys_to_virt(*pte
& PAGE_MASK
);
3484 static int __set_gcr3(struct protection_domain
*domain
, int pasid
,
3489 if (domain
->mode
!= PAGE_MODE_NONE
)
3492 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, true);
3496 *pte
= (cr3
& PAGE_MASK
) | GCR3_VALID
;
3498 return __amd_iommu_flush_tlb(domain
, pasid
);
3501 static int __clear_gcr3(struct protection_domain
*domain
, int pasid
)
3505 if (domain
->mode
!= PAGE_MODE_NONE
)
3508 pte
= __get_gcr3_pte(domain
->gcr3_tbl
, domain
->glx
, pasid
, false);
3514 return __amd_iommu_flush_tlb(domain
, pasid
);
3517 int amd_iommu_domain_set_gcr3(struct iommu_domain
*dom
, int pasid
,
3520 struct protection_domain
*domain
= to_pdomain(dom
);
3521 unsigned long flags
;
3524 spin_lock_irqsave(&domain
->lock
, flags
);
3525 ret
= __set_gcr3(domain
, pasid
, cr3
);
3526 spin_unlock_irqrestore(&domain
->lock
, flags
);
3530 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3
);
3532 int amd_iommu_domain_clear_gcr3(struct iommu_domain
*dom
, int pasid
)
3534 struct protection_domain
*domain
= to_pdomain(dom
);
3535 unsigned long flags
;
3538 spin_lock_irqsave(&domain
->lock
, flags
);
3539 ret
= __clear_gcr3(domain
, pasid
);
3540 spin_unlock_irqrestore(&domain
->lock
, flags
);
3544 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3
);
3546 int amd_iommu_complete_ppr(struct pci_dev
*pdev
, int pasid
,
3547 int status
, int tag
)
3549 struct iommu_dev_data
*dev_data
;
3550 struct amd_iommu
*iommu
;
3551 struct iommu_cmd cmd
;
3553 dev_data
= get_dev_data(&pdev
->dev
);
3554 iommu
= amd_iommu_rlookup_table
[dev_data
->devid
];
3556 build_complete_ppr(&cmd
, dev_data
->devid
, pasid
, status
,
3557 tag
, dev_data
->pri_tlp
);
3559 return iommu_queue_command(iommu
, &cmd
);
3561 EXPORT_SYMBOL(amd_iommu_complete_ppr
);
3563 struct iommu_domain
*amd_iommu_get_v2_domain(struct pci_dev
*pdev
)
3565 struct protection_domain
*pdomain
;
3567 pdomain
= get_domain(&pdev
->dev
);
3568 if (IS_ERR(pdomain
))
3571 /* Only return IOMMUv2 domains */
3572 if (!(pdomain
->flags
& PD_IOMMUV2_MASK
))
3575 return &pdomain
->domain
;
3577 EXPORT_SYMBOL(amd_iommu_get_v2_domain
);
3579 void amd_iommu_enable_device_erratum(struct pci_dev
*pdev
, u32 erratum
)
3581 struct iommu_dev_data
*dev_data
;
3583 if (!amd_iommu_v2_supported())
3586 dev_data
= get_dev_data(&pdev
->dev
);
3587 dev_data
->errata
|= (1 << erratum
);
3589 EXPORT_SYMBOL(amd_iommu_enable_device_erratum
);
3591 int amd_iommu_device_info(struct pci_dev
*pdev
,
3592 struct amd_iommu_device_info
*info
)
3597 if (pdev
== NULL
|| info
== NULL
)
3600 if (!amd_iommu_v2_supported())
3603 memset(info
, 0, sizeof(*info
));
3605 if (!pci_ats_disabled()) {
3606 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ATS
);
3608 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_ATS_SUP
;
3611 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PRI
);
3613 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRI_SUP
;
3615 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_PASID
);
3619 max_pasids
= 1 << (9 * (amd_iommu_max_glx_val
+ 1));
3620 max_pasids
= min(max_pasids
, (1 << 20));
3622 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PASID_SUP
;
3623 info
->max_pasids
= min(pci_max_pasids(pdev
), max_pasids
);
3625 features
= pci_pasid_features(pdev
);
3626 if (features
& PCI_PASID_CAP_EXEC
)
3627 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP
;
3628 if (features
& PCI_PASID_CAP_PRIV
)
3629 info
->flags
|= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP
;
3634 EXPORT_SYMBOL(amd_iommu_device_info
);
3636 #ifdef CONFIG_IRQ_REMAP
3638 /*****************************************************************************
3640 * Interrupt Remapping Implementation
3642 *****************************************************************************/
3644 static struct irq_chip amd_ir_chip
;
3645 static DEFINE_SPINLOCK(iommu_table_lock
);
3647 static void set_dte_irq_entry(u16 devid
, struct irq_remap_table
*table
)
3651 dte
= amd_iommu_dev_table
[devid
].data
[2];
3652 dte
&= ~DTE_IRQ_PHYS_ADDR_MASK
;
3653 dte
|= iommu_virt_to_phys(table
->table
);
3654 dte
|= DTE_IRQ_REMAP_INTCTL
;
3655 dte
|= DTE_IRQ_TABLE_LEN
;
3656 dte
|= DTE_IRQ_REMAP_ENABLE
;
3658 amd_iommu_dev_table
[devid
].data
[2] = dte
;
3661 static struct irq_remap_table
*get_irq_table(u16 devid
)
3663 struct irq_remap_table
*table
;
3665 if (WARN_ONCE(!amd_iommu_rlookup_table
[devid
],
3666 "%s: no iommu for devid %x\n", __func__
, devid
))
3669 table
= irq_lookup_table
[devid
];
3670 if (WARN_ONCE(!table
, "%s: no table for devid %x\n", __func__
, devid
))
3676 static struct irq_remap_table
*__alloc_irq_table(void)
3678 struct irq_remap_table
*table
;
3680 table
= kzalloc(sizeof(*table
), GFP_KERNEL
);
3684 table
->table
= kmem_cache_alloc(amd_iommu_irq_cache
, GFP_KERNEL
);
3685 if (!table
->table
) {
3689 raw_spin_lock_init(&table
->lock
);
3691 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
3692 memset(table
->table
, 0,
3693 MAX_IRQS_PER_TABLE
* sizeof(u32
));
3695 memset(table
->table
, 0,
3696 (MAX_IRQS_PER_TABLE
* (sizeof(u64
) * 2)));
3700 static void set_remap_table_entry(struct amd_iommu
*iommu
, u16 devid
,
3701 struct irq_remap_table
*table
)
3703 irq_lookup_table
[devid
] = table
;
3704 set_dte_irq_entry(devid
, table
);
3705 iommu_flush_dte(iommu
, devid
);
3708 static struct irq_remap_table
*alloc_irq_table(u16 devid
)
3710 struct irq_remap_table
*table
= NULL
;
3711 struct irq_remap_table
*new_table
= NULL
;
3712 struct amd_iommu
*iommu
;
3713 unsigned long flags
;
3716 spin_lock_irqsave(&iommu_table_lock
, flags
);
3718 iommu
= amd_iommu_rlookup_table
[devid
];
3722 table
= irq_lookup_table
[devid
];
3726 alias
= amd_iommu_alias_table
[devid
];
3727 table
= irq_lookup_table
[alias
];
3729 set_remap_table_entry(iommu
, devid
, table
);
3732 spin_unlock_irqrestore(&iommu_table_lock
, flags
);
3734 /* Nothing there yet, allocate new irq remapping table */
3735 new_table
= __alloc_irq_table();
3739 spin_lock_irqsave(&iommu_table_lock
, flags
);
3741 table
= irq_lookup_table
[devid
];
3745 table
= irq_lookup_table
[alias
];
3747 set_remap_table_entry(iommu
, devid
, table
);
3754 set_remap_table_entry(iommu
, devid
, table
);
3756 set_remap_table_entry(iommu
, alias
, table
);
3759 iommu_completion_wait(iommu
);
3762 spin_unlock_irqrestore(&iommu_table_lock
, flags
);
3765 kmem_cache_free(amd_iommu_irq_cache
, new_table
->table
);
3771 static int alloc_irq_index(u16 devid
, int count
, bool align
)
3773 struct irq_remap_table
*table
;
3774 int index
, c
, alignment
= 1;
3775 unsigned long flags
;
3776 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
3781 table
= alloc_irq_table(devid
);
3786 alignment
= roundup_pow_of_two(count
);
3788 raw_spin_lock_irqsave(&table
->lock
, flags
);
3790 /* Scan table for free entries */
3791 for (index
= ALIGN(table
->min_index
, alignment
), c
= 0;
3792 index
< MAX_IRQS_PER_TABLE
;) {
3793 if (!iommu
->irte_ops
->is_allocated(table
, index
)) {
3797 index
= ALIGN(index
+ 1, alignment
);
3803 iommu
->irte_ops
->set_allocated(table
, index
- c
+ 1);
3815 raw_spin_unlock_irqrestore(&table
->lock
, flags
);
3820 static int modify_irte_ga(u16 devid
, int index
, struct irte_ga
*irte
,
3821 struct amd_ir_data
*data
)
3823 struct irq_remap_table
*table
;
3824 struct amd_iommu
*iommu
;
3825 unsigned long flags
;
3826 struct irte_ga
*entry
;
3828 iommu
= amd_iommu_rlookup_table
[devid
];
3832 table
= get_irq_table(devid
);
3836 raw_spin_lock_irqsave(&table
->lock
, flags
);
3838 entry
= (struct irte_ga
*)table
->table
;
3839 entry
= &entry
[index
];
3840 entry
->lo
.fields_remap
.valid
= 0;
3841 entry
->hi
.val
= irte
->hi
.val
;
3842 entry
->lo
.val
= irte
->lo
.val
;
3843 entry
->lo
.fields_remap
.valid
= 1;
3847 raw_spin_unlock_irqrestore(&table
->lock
, flags
);
3849 iommu_flush_irt(iommu
, devid
);
3850 iommu_completion_wait(iommu
);
3855 static int modify_irte(u16 devid
, int index
, union irte
*irte
)
3857 struct irq_remap_table
*table
;
3858 struct amd_iommu
*iommu
;
3859 unsigned long flags
;
3861 iommu
= amd_iommu_rlookup_table
[devid
];
3865 table
= get_irq_table(devid
);
3869 raw_spin_lock_irqsave(&table
->lock
, flags
);
3870 table
->table
[index
] = irte
->val
;
3871 raw_spin_unlock_irqrestore(&table
->lock
, flags
);
3873 iommu_flush_irt(iommu
, devid
);
3874 iommu_completion_wait(iommu
);
3879 static void free_irte(u16 devid
, int index
)
3881 struct irq_remap_table
*table
;
3882 struct amd_iommu
*iommu
;
3883 unsigned long flags
;
3885 iommu
= amd_iommu_rlookup_table
[devid
];
3889 table
= get_irq_table(devid
);
3893 raw_spin_lock_irqsave(&table
->lock
, flags
);
3894 iommu
->irte_ops
->clear_allocated(table
, index
);
3895 raw_spin_unlock_irqrestore(&table
->lock
, flags
);
3897 iommu_flush_irt(iommu
, devid
);
3898 iommu_completion_wait(iommu
);
3901 static void irte_prepare(void *entry
,
3902 u32 delivery_mode
, u32 dest_mode
,
3903 u8 vector
, u32 dest_apicid
, int devid
)
3905 union irte
*irte
= (union irte
*) entry
;
3908 irte
->fields
.vector
= vector
;
3909 irte
->fields
.int_type
= delivery_mode
;
3910 irte
->fields
.destination
= dest_apicid
;
3911 irte
->fields
.dm
= dest_mode
;
3912 irte
->fields
.valid
= 1;
3915 static void irte_ga_prepare(void *entry
,
3916 u32 delivery_mode
, u32 dest_mode
,
3917 u8 vector
, u32 dest_apicid
, int devid
)
3919 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3923 irte
->lo
.fields_remap
.int_type
= delivery_mode
;
3924 irte
->lo
.fields_remap
.dm
= dest_mode
;
3925 irte
->hi
.fields
.vector
= vector
;
3926 irte
->lo
.fields_remap
.destination
= APICID_TO_IRTE_DEST_LO(dest_apicid
);
3927 irte
->hi
.fields
.destination
= APICID_TO_IRTE_DEST_HI(dest_apicid
);
3928 irte
->lo
.fields_remap
.valid
= 1;
3931 static void irte_activate(void *entry
, u16 devid
, u16 index
)
3933 union irte
*irte
= (union irte
*) entry
;
3935 irte
->fields
.valid
= 1;
3936 modify_irte(devid
, index
, irte
);
3939 static void irte_ga_activate(void *entry
, u16 devid
, u16 index
)
3941 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3943 irte
->lo
.fields_remap
.valid
= 1;
3944 modify_irte_ga(devid
, index
, irte
, NULL
);
3947 static void irte_deactivate(void *entry
, u16 devid
, u16 index
)
3949 union irte
*irte
= (union irte
*) entry
;
3951 irte
->fields
.valid
= 0;
3952 modify_irte(devid
, index
, irte
);
3955 static void irte_ga_deactivate(void *entry
, u16 devid
, u16 index
)
3957 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3959 irte
->lo
.fields_remap
.valid
= 0;
3960 modify_irte_ga(devid
, index
, irte
, NULL
);
3963 static void irte_set_affinity(void *entry
, u16 devid
, u16 index
,
3964 u8 vector
, u32 dest_apicid
)
3966 union irte
*irte
= (union irte
*) entry
;
3968 irte
->fields
.vector
= vector
;
3969 irte
->fields
.destination
= dest_apicid
;
3970 modify_irte(devid
, index
, irte
);
3973 static void irte_ga_set_affinity(void *entry
, u16 devid
, u16 index
,
3974 u8 vector
, u32 dest_apicid
)
3976 struct irte_ga
*irte
= (struct irte_ga
*) entry
;
3978 if (!irte
->lo
.fields_remap
.guest_mode
) {
3979 irte
->hi
.fields
.vector
= vector
;
3980 irte
->lo
.fields_remap
.destination
=
3981 APICID_TO_IRTE_DEST_LO(dest_apicid
);
3982 irte
->hi
.fields
.destination
=
3983 APICID_TO_IRTE_DEST_HI(dest_apicid
);
3984 modify_irte_ga(devid
, index
, irte
, NULL
);
3988 #define IRTE_ALLOCATED (~1U)
3989 static void irte_set_allocated(struct irq_remap_table
*table
, int index
)
3991 table
->table
[index
] = IRTE_ALLOCATED
;
3994 static void irte_ga_set_allocated(struct irq_remap_table
*table
, int index
)
3996 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
3997 struct irte_ga
*irte
= &ptr
[index
];
3999 memset(&irte
->lo
.val
, 0, sizeof(u64
));
4000 memset(&irte
->hi
.val
, 0, sizeof(u64
));
4001 irte
->hi
.fields
.vector
= 0xff;
4004 static bool irte_is_allocated(struct irq_remap_table
*table
, int index
)
4006 union irte
*ptr
= (union irte
*)table
->table
;
4007 union irte
*irte
= &ptr
[index
];
4009 return irte
->val
!= 0;
4012 static bool irte_ga_is_allocated(struct irq_remap_table
*table
, int index
)
4014 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
4015 struct irte_ga
*irte
= &ptr
[index
];
4017 return irte
->hi
.fields
.vector
!= 0;
4020 static void irte_clear_allocated(struct irq_remap_table
*table
, int index
)
4022 table
->table
[index
] = 0;
4025 static void irte_ga_clear_allocated(struct irq_remap_table
*table
, int index
)
4027 struct irte_ga
*ptr
= (struct irte_ga
*)table
->table
;
4028 struct irte_ga
*irte
= &ptr
[index
];
4030 memset(&irte
->lo
.val
, 0, sizeof(u64
));
4031 memset(&irte
->hi
.val
, 0, sizeof(u64
));
4034 static int get_devid(struct irq_alloc_info
*info
)
4038 switch (info
->type
) {
4039 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4040 devid
= get_ioapic_devid(info
->ioapic_id
);
4042 case X86_IRQ_ALLOC_TYPE_HPET
:
4043 devid
= get_hpet_devid(info
->hpet_id
);
4045 case X86_IRQ_ALLOC_TYPE_MSI
:
4046 case X86_IRQ_ALLOC_TYPE_MSIX
:
4047 devid
= get_device_id(&info
->msi_dev
->dev
);
4057 static struct irq_domain
*get_ir_irq_domain(struct irq_alloc_info
*info
)
4059 struct amd_iommu
*iommu
;
4065 devid
= get_devid(info
);
4067 iommu
= amd_iommu_rlookup_table
[devid
];
4069 return iommu
->ir_domain
;
4075 static struct irq_domain
*get_irq_domain(struct irq_alloc_info
*info
)
4077 struct amd_iommu
*iommu
;
4083 switch (info
->type
) {
4084 case X86_IRQ_ALLOC_TYPE_MSI
:
4085 case X86_IRQ_ALLOC_TYPE_MSIX
:
4086 devid
= get_device_id(&info
->msi_dev
->dev
);
4090 iommu
= amd_iommu_rlookup_table
[devid
];
4092 return iommu
->msi_domain
;
4101 struct irq_remap_ops amd_iommu_irq_ops
= {
4102 .prepare
= amd_iommu_prepare
,
4103 .enable
= amd_iommu_enable
,
4104 .disable
= amd_iommu_disable
,
4105 .reenable
= amd_iommu_reenable
,
4106 .enable_faulting
= amd_iommu_enable_faulting
,
4107 .get_ir_irq_domain
= get_ir_irq_domain
,
4108 .get_irq_domain
= get_irq_domain
,
4111 static void irq_remapping_prepare_irte(struct amd_ir_data
*data
,
4112 struct irq_cfg
*irq_cfg
,
4113 struct irq_alloc_info
*info
,
4114 int devid
, int index
, int sub_handle
)
4116 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4117 struct msi_msg
*msg
= &data
->msi_entry
;
4118 struct IO_APIC_route_entry
*entry
;
4119 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
4124 data
->irq_2_irte
.devid
= devid
;
4125 data
->irq_2_irte
.index
= index
+ sub_handle
;
4126 iommu
->irte_ops
->prepare(data
->entry
, apic
->irq_delivery_mode
,
4127 apic
->irq_dest_mode
, irq_cfg
->vector
,
4128 irq_cfg
->dest_apicid
, devid
);
4130 switch (info
->type
) {
4131 case X86_IRQ_ALLOC_TYPE_IOAPIC
:
4132 /* Setup IOAPIC entry */
4133 entry
= info
->ioapic_entry
;
4134 info
->ioapic_entry
= NULL
;
4135 memset(entry
, 0, sizeof(*entry
));
4136 entry
->vector
= index
;
4138 entry
->trigger
= info
->ioapic_trigger
;
4139 entry
->polarity
= info
->ioapic_polarity
;
4140 /* Mask level triggered irqs. */
4141 if (info
->ioapic_trigger
)
4145 case X86_IRQ_ALLOC_TYPE_HPET
:
4146 case X86_IRQ_ALLOC_TYPE_MSI
:
4147 case X86_IRQ_ALLOC_TYPE_MSIX
:
4148 msg
->address_hi
= MSI_ADDR_BASE_HI
;
4149 msg
->address_lo
= MSI_ADDR_BASE_LO
;
4150 msg
->data
= irte_info
->index
;
4159 struct amd_irte_ops irte_32_ops
= {
4160 .prepare
= irte_prepare
,
4161 .activate
= irte_activate
,
4162 .deactivate
= irte_deactivate
,
4163 .set_affinity
= irte_set_affinity
,
4164 .set_allocated
= irte_set_allocated
,
4165 .is_allocated
= irte_is_allocated
,
4166 .clear_allocated
= irte_clear_allocated
,
4169 struct amd_irte_ops irte_128_ops
= {
4170 .prepare
= irte_ga_prepare
,
4171 .activate
= irte_ga_activate
,
4172 .deactivate
= irte_ga_deactivate
,
4173 .set_affinity
= irte_ga_set_affinity
,
4174 .set_allocated
= irte_ga_set_allocated
,
4175 .is_allocated
= irte_ga_is_allocated
,
4176 .clear_allocated
= irte_ga_clear_allocated
,
4179 static int irq_remapping_alloc(struct irq_domain
*domain
, unsigned int virq
,
4180 unsigned int nr_irqs
, void *arg
)
4182 struct irq_alloc_info
*info
= arg
;
4183 struct irq_data
*irq_data
;
4184 struct amd_ir_data
*data
= NULL
;
4185 struct irq_cfg
*cfg
;
4191 if (nr_irqs
> 1 && info
->type
!= X86_IRQ_ALLOC_TYPE_MSI
&&
4192 info
->type
!= X86_IRQ_ALLOC_TYPE_MSIX
)
4196 * With IRQ remapping enabled, don't need contiguous CPU vectors
4197 * to support multiple MSI interrupts.
4199 if (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
)
4200 info
->flags
&= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS
;
4202 devid
= get_devid(info
);
4206 ret
= irq_domain_alloc_irqs_parent(domain
, virq
, nr_irqs
, arg
);
4210 if (info
->type
== X86_IRQ_ALLOC_TYPE_IOAPIC
) {
4211 struct irq_remap_table
*table
;
4212 struct amd_iommu
*iommu
;
4214 table
= alloc_irq_table(devid
);
4216 if (!table
->min_index
) {
4218 * Keep the first 32 indexes free for IOAPIC
4221 table
->min_index
= 32;
4222 iommu
= amd_iommu_rlookup_table
[devid
];
4223 for (i
= 0; i
< 32; ++i
)
4224 iommu
->irte_ops
->set_allocated(table
, i
);
4226 WARN_ON(table
->min_index
!= 32);
4227 index
= info
->ioapic_pin
;
4232 bool align
= (info
->type
== X86_IRQ_ALLOC_TYPE_MSI
);
4234 index
= alloc_irq_index(devid
, nr_irqs
, align
);
4237 pr_warn("Failed to allocate IRTE\n");
4239 goto out_free_parent
;
4242 for (i
= 0; i
< nr_irqs
; i
++) {
4243 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4244 cfg
= irqd_cfg(irq_data
);
4245 if (!irq_data
|| !cfg
) {
4251 data
= kzalloc(sizeof(*data
), GFP_KERNEL
);
4255 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
4256 data
->entry
= kzalloc(sizeof(union irte
), GFP_KERNEL
);
4258 data
->entry
= kzalloc(sizeof(struct irte_ga
),
4265 irq_data
->hwirq
= (devid
<< 16) + i
;
4266 irq_data
->chip_data
= data
;
4267 irq_data
->chip
= &amd_ir_chip
;
4268 irq_remapping_prepare_irte(data
, cfg
, info
, devid
, index
, i
);
4269 irq_set_status_flags(virq
+ i
, IRQ_MOVE_PCNTXT
);
4275 for (i
--; i
>= 0; i
--) {
4276 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4278 kfree(irq_data
->chip_data
);
4280 for (i
= 0; i
< nr_irqs
; i
++)
4281 free_irte(devid
, index
+ i
);
4283 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4287 static void irq_remapping_free(struct irq_domain
*domain
, unsigned int virq
,
4288 unsigned int nr_irqs
)
4290 struct irq_2_irte
*irte_info
;
4291 struct irq_data
*irq_data
;
4292 struct amd_ir_data
*data
;
4295 for (i
= 0; i
< nr_irqs
; i
++) {
4296 irq_data
= irq_domain_get_irq_data(domain
, virq
+ i
);
4297 if (irq_data
&& irq_data
->chip_data
) {
4298 data
= irq_data
->chip_data
;
4299 irte_info
= &data
->irq_2_irte
;
4300 free_irte(irte_info
->devid
, irte_info
->index
);
4305 irq_domain_free_irqs_common(domain
, virq
, nr_irqs
);
4308 static void amd_ir_update_irte(struct irq_data
*irqd
, struct amd_iommu
*iommu
,
4309 struct amd_ir_data
*ir_data
,
4310 struct irq_2_irte
*irte_info
,
4311 struct irq_cfg
*cfg
);
4313 static int irq_remapping_activate(struct irq_domain
*domain
,
4314 struct irq_data
*irq_data
, bool reserve
)
4316 struct amd_ir_data
*data
= irq_data
->chip_data
;
4317 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4318 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4319 struct irq_cfg
*cfg
= irqd_cfg(irq_data
);
4324 iommu
->irte_ops
->activate(data
->entry
, irte_info
->devid
,
4326 amd_ir_update_irte(irq_data
, iommu
, data
, irte_info
, cfg
);
4330 static void irq_remapping_deactivate(struct irq_domain
*domain
,
4331 struct irq_data
*irq_data
)
4333 struct amd_ir_data
*data
= irq_data
->chip_data
;
4334 struct irq_2_irte
*irte_info
= &data
->irq_2_irte
;
4335 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4338 iommu
->irte_ops
->deactivate(data
->entry
, irte_info
->devid
,
4342 static const struct irq_domain_ops amd_ir_domain_ops
= {
4343 .alloc
= irq_remapping_alloc
,
4344 .free
= irq_remapping_free
,
4345 .activate
= irq_remapping_activate
,
4346 .deactivate
= irq_remapping_deactivate
,
4349 static int amd_ir_set_vcpu_affinity(struct irq_data
*data
, void *vcpu_info
)
4351 struct amd_iommu
*iommu
;
4352 struct amd_iommu_pi_data
*pi_data
= vcpu_info
;
4353 struct vcpu_data
*vcpu_pi_info
= pi_data
->vcpu_data
;
4354 struct amd_ir_data
*ir_data
= data
->chip_data
;
4355 struct irte_ga
*irte
= (struct irte_ga
*) ir_data
->entry
;
4356 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4357 struct iommu_dev_data
*dev_data
= search_dev_data(irte_info
->devid
);
4360 * This device has never been set up for guest mode.
4361 * we should not modify the IRTE
4363 if (!dev_data
|| !dev_data
->use_vapic
)
4366 pi_data
->ir_data
= ir_data
;
4369 * SVM tries to set up for VAPIC mode, but we are in
4370 * legacy mode. So, we force legacy mode instead.
4372 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
)) {
4373 pr_debug("%s: Fall back to using intr legacy remap\n",
4375 pi_data
->is_guest_mode
= false;
4378 iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4382 pi_data
->prev_ga_tag
= ir_data
->cached_ga_tag
;
4383 if (pi_data
->is_guest_mode
) {
4385 irte
->hi
.fields
.ga_root_ptr
= (pi_data
->base
>> 12);
4386 irte
->hi
.fields
.vector
= vcpu_pi_info
->vector
;
4387 irte
->lo
.fields_vapic
.ga_log_intr
= 1;
4388 irte
->lo
.fields_vapic
.guest_mode
= 1;
4389 irte
->lo
.fields_vapic
.ga_tag
= pi_data
->ga_tag
;
4391 ir_data
->cached_ga_tag
= pi_data
->ga_tag
;
4394 struct irq_cfg
*cfg
= irqd_cfg(data
);
4398 irte
->hi
.fields
.vector
= cfg
->vector
;
4399 irte
->lo
.fields_remap
.guest_mode
= 0;
4400 irte
->lo
.fields_remap
.destination
=
4401 APICID_TO_IRTE_DEST_LO(cfg
->dest_apicid
);
4402 irte
->hi
.fields
.destination
=
4403 APICID_TO_IRTE_DEST_HI(cfg
->dest_apicid
);
4404 irte
->lo
.fields_remap
.int_type
= apic
->irq_delivery_mode
;
4405 irte
->lo
.fields_remap
.dm
= apic
->irq_dest_mode
;
4408 * This communicates the ga_tag back to the caller
4409 * so that it can do all the necessary clean up.
4411 ir_data
->cached_ga_tag
= 0;
4414 return modify_irte_ga(irte_info
->devid
, irte_info
->index
, irte
, ir_data
);
4418 static void amd_ir_update_irte(struct irq_data
*irqd
, struct amd_iommu
*iommu
,
4419 struct amd_ir_data
*ir_data
,
4420 struct irq_2_irte
*irte_info
,
4421 struct irq_cfg
*cfg
)
4425 * Atomically updates the IRTE with the new destination, vector
4426 * and flushes the interrupt entry cache.
4428 iommu
->irte_ops
->set_affinity(ir_data
->entry
, irte_info
->devid
,
4429 irte_info
->index
, cfg
->vector
,
4433 static int amd_ir_set_affinity(struct irq_data
*data
,
4434 const struct cpumask
*mask
, bool force
)
4436 struct amd_ir_data
*ir_data
= data
->chip_data
;
4437 struct irq_2_irte
*irte_info
= &ir_data
->irq_2_irte
;
4438 struct irq_cfg
*cfg
= irqd_cfg(data
);
4439 struct irq_data
*parent
= data
->parent_data
;
4440 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[irte_info
->devid
];
4446 ret
= parent
->chip
->irq_set_affinity(parent
, mask
, force
);
4447 if (ret
< 0 || ret
== IRQ_SET_MASK_OK_DONE
)
4450 amd_ir_update_irte(data
, iommu
, ir_data
, irte_info
, cfg
);
4452 * After this point, all the interrupts will start arriving
4453 * at the new destination. So, time to cleanup the previous
4454 * vector allocation.
4456 send_cleanup_vector(cfg
);
4458 return IRQ_SET_MASK_OK_DONE
;
4461 static void ir_compose_msi_msg(struct irq_data
*irq_data
, struct msi_msg
*msg
)
4463 struct amd_ir_data
*ir_data
= irq_data
->chip_data
;
4465 *msg
= ir_data
->msi_entry
;
4468 static struct irq_chip amd_ir_chip
= {
4470 .irq_ack
= apic_ack_irq
,
4471 .irq_set_affinity
= amd_ir_set_affinity
,
4472 .irq_set_vcpu_affinity
= amd_ir_set_vcpu_affinity
,
4473 .irq_compose_msi_msg
= ir_compose_msi_msg
,
4476 int amd_iommu_create_irq_domain(struct amd_iommu
*iommu
)
4478 struct fwnode_handle
*fn
;
4480 fn
= irq_domain_alloc_named_id_fwnode("AMD-IR", iommu
->index
);
4483 iommu
->ir_domain
= irq_domain_create_tree(fn
, &amd_ir_domain_ops
, iommu
);
4484 irq_domain_free_fwnode(fn
);
4485 if (!iommu
->ir_domain
)
4488 iommu
->ir_domain
->parent
= arch_get_ir_parent_domain();
4489 iommu
->msi_domain
= arch_create_remap_msi_irq_domain(iommu
->ir_domain
,
4495 int amd_iommu_update_ga(int cpu
, bool is_run
, void *data
)
4497 unsigned long flags
;
4498 struct amd_iommu
*iommu
;
4499 struct irq_remap_table
*table
;
4500 struct amd_ir_data
*ir_data
= (struct amd_ir_data
*)data
;
4501 int devid
= ir_data
->irq_2_irte
.devid
;
4502 struct irte_ga
*entry
= (struct irte_ga
*) ir_data
->entry
;
4503 struct irte_ga
*ref
= (struct irte_ga
*) ir_data
->ref
;
4505 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) ||
4506 !ref
|| !entry
|| !entry
->lo
.fields_vapic
.guest_mode
)
4509 iommu
= amd_iommu_rlookup_table
[devid
];
4513 table
= get_irq_table(devid
);
4517 raw_spin_lock_irqsave(&table
->lock
, flags
);
4519 if (ref
->lo
.fields_vapic
.guest_mode
) {
4521 ref
->lo
.fields_vapic
.destination
=
4522 APICID_TO_IRTE_DEST_LO(cpu
);
4523 ref
->hi
.fields
.destination
=
4524 APICID_TO_IRTE_DEST_HI(cpu
);
4526 ref
->lo
.fields_vapic
.is_run
= is_run
;
4530 raw_spin_unlock_irqrestore(&table
->lock
, flags
);
4532 iommu_flush_irt(iommu
, devid
);
4533 iommu_completion_wait(iommu
);
4536 EXPORT_SYMBOL(amd_iommu_update_ga
);