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Merge tag 'configfs-for-5.3' of git://git.infradead.org/users/hch/configfs
[mirror_ubuntu-eoan-kernel.git] / drivers / iommu / amd_iommu.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
37 #include <asm/apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
42 #include <asm/gart.h>
43 #include <asm/dma.h>
44
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
48
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
50
51 #define LOOP_TIMEOUT 100000
52
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
56
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
62
63 /*
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
67 * that we support.
68 *
69 * 512GB Pages are not supported due to a hardware bug
70 */
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
72
73 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
75
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
78
79 LIST_HEAD(ioapic_map);
80 LIST_HEAD(hpet_map);
81 LIST_HEAD(acpihid_map);
82
83 /*
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
86 */
87 const struct iommu_ops amd_iommu_ops;
88
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
91
92 static const struct dma_map_ops amd_iommu_dma_ops;
93
94 /*
95 * general struct to manage commands send to an IOMMU
96 */
97 struct iommu_cmd {
98 u32 data[4];
99 };
100
101 struct kmem_cache *amd_iommu_irq_cache;
102
103 static void update_domain(struct protection_domain *domain);
104 static int protection_domain_init(struct protection_domain *domain);
105 static void detach_device(struct device *dev);
106 static void iova_domain_flush_tlb(struct iova_domain *iovad);
107
108 /*
109 * Data container for a dma_ops specific protection domain
110 */
111 struct dma_ops_domain {
112 /* generic protection domain information */
113 struct protection_domain domain;
114
115 /* IOVA RB-Tree */
116 struct iova_domain iovad;
117 };
118
119 static struct iova_domain reserved_iova_ranges;
120 static struct lock_class_key reserved_rbtree_key;
121
122 /****************************************************************************
123 *
124 * Helper functions
125 *
126 ****************************************************************************/
127
128 static inline int match_hid_uid(struct device *dev,
129 struct acpihid_map_entry *entry)
130 {
131 struct acpi_device *adev = ACPI_COMPANION(dev);
132 const char *hid, *uid;
133
134 if (!adev)
135 return -ENODEV;
136
137 hid = acpi_device_hid(adev);
138 uid = acpi_device_uid(adev);
139
140 if (!hid || !(*hid))
141 return -ENODEV;
142
143 if (!uid || !(*uid))
144 return strcmp(hid, entry->hid);
145
146 if (!(*entry->uid))
147 return strcmp(hid, entry->hid);
148
149 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
150 }
151
152 static inline u16 get_pci_device_id(struct device *dev)
153 {
154 struct pci_dev *pdev = to_pci_dev(dev);
155
156 return pci_dev_id(pdev);
157 }
158
159 static inline int get_acpihid_device_id(struct device *dev,
160 struct acpihid_map_entry **entry)
161 {
162 struct acpihid_map_entry *p;
163
164 list_for_each_entry(p, &acpihid_map, list) {
165 if (!match_hid_uid(dev, p)) {
166 if (entry)
167 *entry = p;
168 return p->devid;
169 }
170 }
171 return -EINVAL;
172 }
173
174 static inline int get_device_id(struct device *dev)
175 {
176 int devid;
177
178 if (dev_is_pci(dev))
179 devid = get_pci_device_id(dev);
180 else
181 devid = get_acpihid_device_id(dev, NULL);
182
183 return devid;
184 }
185
186 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
187 {
188 return container_of(dom, struct protection_domain, domain);
189 }
190
191 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
192 {
193 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
194 return container_of(domain, struct dma_ops_domain, domain);
195 }
196
197 static struct iommu_dev_data *alloc_dev_data(u16 devid)
198 {
199 struct iommu_dev_data *dev_data;
200
201 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
202 if (!dev_data)
203 return NULL;
204
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
207
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
209 return dev_data;
210 }
211
212 static struct iommu_dev_data *search_dev_data(u16 devid)
213 {
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
216
217 if (llist_empty(&dev_data_list))
218 return NULL;
219
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
223 return dev_data;
224 }
225
226 return NULL;
227 }
228
229 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
230 {
231 *(u16 *)data = alias;
232 return 0;
233 }
234
235 static u16 get_alias(struct device *dev)
236 {
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
239
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
242
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
245 return devid;
246
247 ivrs_alias = amd_iommu_alias_table[devid];
248
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
250
251 if (ivrs_alias == pci_alias)
252 return ivrs_alias;
253
254 /*
255 * DMA alias showdown
256 *
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
262 */
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
270 }
271
272 return pci_alias;
273 }
274
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
281
282 /*
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
285 */
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
291 }
292
293 return ivrs_alias;
294 }
295
296 static struct iommu_dev_data *find_dev_data(u16 devid)
297 {
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
300
301 dev_data = search_dev_data(devid);
302
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
305 if (!dev_data)
306 return NULL;
307
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
310 }
311
312 return dev_data;
313 }
314
315 struct iommu_dev_data *get_dev_data(struct device *dev)
316 {
317 return dev->archdata.iommu;
318 }
319 EXPORT_SYMBOL(get_dev_data);
320
321 /*
322 * Find or create an IOMMU group for a acpihid device.
323 */
324 static struct iommu_group *acpihid_device_group(struct device *dev)
325 {
326 struct acpihid_map_entry *p, *entry = NULL;
327 int devid;
328
329 devid = get_acpihid_device_id(dev, &entry);
330 if (devid < 0)
331 return ERR_PTR(devid);
332
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
336 }
337
338 if (!entry->group)
339 entry->group = generic_device_group(dev);
340 else
341 iommu_group_ref_get(entry->group);
342
343 return entry->group;
344 }
345
346 static bool pci_iommuv2_capable(struct pci_dev *pdev)
347 {
348 static const int caps[] = {
349 PCI_EXT_CAP_ID_ATS,
350 PCI_EXT_CAP_ID_PRI,
351 PCI_EXT_CAP_ID_PASID,
352 };
353 int i, pos;
354
355 if (pci_ats_disabled())
356 return false;
357
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
360 if (pos == 0)
361 return false;
362 }
363
364 return true;
365 }
366
367 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
368 {
369 struct iommu_dev_data *dev_data;
370
371 dev_data = get_dev_data(&pdev->dev);
372
373 return dev_data->errata & (1 << erratum) ? true : false;
374 }
375
376 /*
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
379 */
380 static bool check_device(struct device *dev)
381 {
382 int devid;
383
384 if (!dev || !dev->dma_mask)
385 return false;
386
387 devid = get_device_id(dev);
388 if (devid < 0)
389 return false;
390
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
393 return false;
394
395 if (amd_iommu_rlookup_table[devid] == NULL)
396 return false;
397
398 return true;
399 }
400
401 static void init_iommu_group(struct device *dev)
402 {
403 struct iommu_group *group;
404
405 group = iommu_group_get_for_dev(dev);
406 if (IS_ERR(group))
407 return;
408
409 iommu_group_put(group);
410 }
411
412 static int iommu_init_device(struct device *dev)
413 {
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
416 int devid;
417
418 if (dev->archdata.iommu)
419 return 0;
420
421 devid = get_device_id(dev);
422 if (devid < 0)
423 return devid;
424
425 iommu = amd_iommu_rlookup_table[devid];
426
427 dev_data = find_dev_data(devid);
428 if (!dev_data)
429 return -ENOMEM;
430
431 dev_data->alias = get_alias(dev);
432
433 /*
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
438 */
439 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
442
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
445 }
446
447 dev->archdata.iommu = dev_data;
448
449 iommu_device_link(&iommu->iommu, dev);
450
451 return 0;
452 }
453
454 static void iommu_ignore_device(struct device *dev)
455 {
456 u16 alias;
457 int devid;
458
459 devid = get_device_id(dev);
460 if (devid < 0)
461 return;
462
463 alias = get_alias(dev);
464
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
467
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
470 }
471
472 static void iommu_uninit_device(struct device *dev)
473 {
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
476 int devid;
477
478 devid = get_device_id(dev);
479 if (devid < 0)
480 return;
481
482 iommu = amd_iommu_rlookup_table[devid];
483
484 dev_data = search_dev_data(devid);
485 if (!dev_data)
486 return;
487
488 if (dev_data->domain)
489 detach_device(dev);
490
491 iommu_device_unlink(&iommu->iommu, dev);
492
493 iommu_group_remove_device(dev);
494
495 /* Remove dma-ops */
496 dev->dma_ops = NULL;
497
498 /*
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
501 */
502 }
503
504 /****************************************************************************
505 *
506 * Interrupt handling functions
507 *
508 ****************************************************************************/
509
510 static void dump_dte_entry(u16 devid)
511 {
512 int i;
513
514 for (i = 0; i < 4; ++i)
515 pr_err("DTE[%d]: %016llx\n", i,
516 amd_iommu_dev_table[devid].data[i]);
517 }
518
519 static void dump_command(unsigned long phys_addr)
520 {
521 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
522 int i;
523
524 for (i = 0; i < 4; ++i)
525 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
526 }
527
528 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
529 u64 address, int flags)
530 {
531 struct iommu_dev_data *dev_data = NULL;
532 struct pci_dev *pdev;
533
534 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
535 devid & 0xff);
536 if (pdev)
537 dev_data = get_dev_data(&pdev->dev);
538
539 if (dev_data && __ratelimit(&dev_data->rs)) {
540 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
541 domain_id, address, flags);
542 } else if (printk_ratelimit()) {
543 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 domain_id, address, flags);
546 }
547
548 if (pdev)
549 pci_dev_put(pdev);
550 }
551
552 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
553 {
554 struct device *dev = iommu->iommu.dev;
555 int type, devid, pasid, flags, tag;
556 volatile u32 *event = __evt;
557 int count = 0;
558 u64 address;
559
560 retry:
561 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
562 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
563 pasid = PPR_PASID(*(u64 *)&event[0]);
564 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
565 address = (u64)(((u64)event[3]) << 32) | event[2];
566
567 if (type == 0) {
568 /* Did we hit the erratum? */
569 if (++count == LOOP_TIMEOUT) {
570 pr_err("No event written to event log\n");
571 return;
572 }
573 udelay(1);
574 goto retry;
575 }
576
577 if (type == EVENT_TYPE_IO_FAULT) {
578 amd_iommu_report_page_fault(devid, pasid, address, flags);
579 return;
580 }
581
582 switch (type) {
583 case EVENT_TYPE_ILL_DEV:
584 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 pasid, address, flags);
587 dump_dte_entry(devid);
588 break;
589 case EVENT_TYPE_DEV_TAB_ERR:
590 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
591 "address=0x%llx flags=0x%04x]\n",
592 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
593 address, flags);
594 break;
595 case EVENT_TYPE_PAGE_TAB_ERR:
596 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
602 dump_command(address);
603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
606 address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 address);
612 break;
613 case EVENT_TYPE_INV_DEV_REQ:
614 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 pasid, address, flags);
617 break;
618 case EVENT_TYPE_INV_PPR_REQ:
619 pasid = ((event[0] >> 16) & 0xFFFF)
620 | ((event[1] << 6) & 0xF0000);
621 tag = event[1] & 0x03FF;
622 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
623 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
624 pasid, address, flags, tag);
625 break;
626 default:
627 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
628 event[0], event[1], event[2], event[3]);
629 }
630
631 memset(__evt, 0, 4 * sizeof(u32));
632 }
633
634 static void iommu_poll_events(struct amd_iommu *iommu)
635 {
636 u32 head, tail;
637
638 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
640
641 while (head != tail) {
642 iommu_print_event(iommu, iommu->evt_buf + head);
643 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
644 }
645
646 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
647 }
648
649 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
650 {
651 struct amd_iommu_fault fault;
652
653 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
654 pr_err_ratelimited("Unknown PPR request received\n");
655 return;
656 }
657
658 fault.address = raw[1];
659 fault.pasid = PPR_PASID(raw[0]);
660 fault.device_id = PPR_DEVID(raw[0]);
661 fault.tag = PPR_TAG(raw[0]);
662 fault.flags = PPR_FLAGS(raw[0]);
663
664 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
665 }
666
667 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
668 {
669 u32 head, tail;
670
671 if (iommu->ppr_log == NULL)
672 return;
673
674 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
675 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
676
677 while (head != tail) {
678 volatile u64 *raw;
679 u64 entry[2];
680 int i;
681
682 raw = (u64 *)(iommu->ppr_log + head);
683
684 /*
685 * Hardware bug: Interrupt may arrive before the entry is
686 * written to memory. If this happens we need to wait for the
687 * entry to arrive.
688 */
689 for (i = 0; i < LOOP_TIMEOUT; ++i) {
690 if (PPR_REQ_TYPE(raw[0]) != 0)
691 break;
692 udelay(1);
693 }
694
695 /* Avoid memcpy function-call overhead */
696 entry[0] = raw[0];
697 entry[1] = raw[1];
698
699 /*
700 * To detect the hardware bug we need to clear the entry
701 * back to zero.
702 */
703 raw[0] = raw[1] = 0UL;
704
705 /* Update head pointer of hardware ring-buffer */
706 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
707 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
708
709 /* Handle PPR entry */
710 iommu_handle_ppr_entry(iommu, entry);
711
712 /* Refresh ring-buffer information */
713 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
715 }
716 }
717
718 #ifdef CONFIG_IRQ_REMAP
719 static int (*iommu_ga_log_notifier)(u32);
720
721 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
722 {
723 iommu_ga_log_notifier = notifier;
724
725 return 0;
726 }
727 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
728
729 static void iommu_poll_ga_log(struct amd_iommu *iommu)
730 {
731 u32 head, tail, cnt = 0;
732
733 if (iommu->ga_log == NULL)
734 return;
735
736 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
737 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
738
739 while (head != tail) {
740 volatile u64 *raw;
741 u64 log_entry;
742
743 raw = (u64 *)(iommu->ga_log + head);
744 cnt++;
745
746 /* Avoid memcpy function-call overhead */
747 log_entry = *raw;
748
749 /* Update head pointer of hardware ring-buffer */
750 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
751 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
752
753 /* Handle GA entry */
754 switch (GA_REQ_TYPE(log_entry)) {
755 case GA_GUEST_NR:
756 if (!iommu_ga_log_notifier)
757 break;
758
759 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
760 __func__, GA_DEVID(log_entry),
761 GA_TAG(log_entry));
762
763 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
764 pr_err("GA log notifier failed.\n");
765 break;
766 default:
767 break;
768 }
769 }
770 }
771 #endif /* CONFIG_IRQ_REMAP */
772
773 #define AMD_IOMMU_INT_MASK \
774 (MMIO_STATUS_EVT_INT_MASK | \
775 MMIO_STATUS_PPR_INT_MASK | \
776 MMIO_STATUS_GALOG_INT_MASK)
777
778 irqreturn_t amd_iommu_int_thread(int irq, void *data)
779 {
780 struct amd_iommu *iommu = (struct amd_iommu *) data;
781 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
782
783 while (status & AMD_IOMMU_INT_MASK) {
784 /* Enable EVT and PPR and GA interrupts again */
785 writel(AMD_IOMMU_INT_MASK,
786 iommu->mmio_base + MMIO_STATUS_OFFSET);
787
788 if (status & MMIO_STATUS_EVT_INT_MASK) {
789 pr_devel("Processing IOMMU Event Log\n");
790 iommu_poll_events(iommu);
791 }
792
793 if (status & MMIO_STATUS_PPR_INT_MASK) {
794 pr_devel("Processing IOMMU PPR Log\n");
795 iommu_poll_ppr_log(iommu);
796 }
797
798 #ifdef CONFIG_IRQ_REMAP
799 if (status & MMIO_STATUS_GALOG_INT_MASK) {
800 pr_devel("Processing IOMMU GA Log\n");
801 iommu_poll_ga_log(iommu);
802 }
803 #endif
804
805 /*
806 * Hardware bug: ERBT1312
807 * When re-enabling interrupt (by writing 1
808 * to clear the bit), the hardware might also try to set
809 * the interrupt bit in the event status register.
810 * In this scenario, the bit will be set, and disable
811 * subsequent interrupts.
812 *
813 * Workaround: The IOMMU driver should read back the
814 * status register and check if the interrupt bits are cleared.
815 * If not, driver will need to go through the interrupt handler
816 * again and re-clear the bits
817 */
818 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
819 }
820 return IRQ_HANDLED;
821 }
822
823 irqreturn_t amd_iommu_int_handler(int irq, void *data)
824 {
825 return IRQ_WAKE_THREAD;
826 }
827
828 /****************************************************************************
829 *
830 * IOMMU command queuing functions
831 *
832 ****************************************************************************/
833
834 static int wait_on_sem(volatile u64 *sem)
835 {
836 int i = 0;
837
838 while (*sem == 0 && i < LOOP_TIMEOUT) {
839 udelay(1);
840 i += 1;
841 }
842
843 if (i == LOOP_TIMEOUT) {
844 pr_alert("Completion-Wait loop timed out\n");
845 return -EIO;
846 }
847
848 return 0;
849 }
850
851 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
852 struct iommu_cmd *cmd)
853 {
854 u8 *target;
855
856 target = iommu->cmd_buf + iommu->cmd_buf_tail;
857
858 iommu->cmd_buf_tail += sizeof(*cmd);
859 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
860
861 /* Copy command to buffer */
862 memcpy(target, cmd, sizeof(*cmd));
863
864 /* Tell the IOMMU about it */
865 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
866 }
867
868 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
869 {
870 u64 paddr = iommu_virt_to_phys((void *)address);
871
872 WARN_ON(address & 0x7ULL);
873
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
876 cmd->data[1] = upper_32_bits(paddr);
877 cmd->data[2] = 1;
878 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
879 }
880
881 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
882 {
883 memset(cmd, 0, sizeof(*cmd));
884 cmd->data[0] = devid;
885 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
886 }
887
888 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
889 size_t size, u16 domid, int pde)
890 {
891 u64 pages;
892 bool s;
893
894 pages = iommu_num_pages(address, size, PAGE_SIZE);
895 s = false;
896
897 if (pages > 1) {
898 /*
899 * If we have to flush more than one page, flush all
900 * TLB entries for this domain
901 */
902 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
903 s = true;
904 }
905
906 address &= PAGE_MASK;
907
908 memset(cmd, 0, sizeof(*cmd));
909 cmd->data[1] |= domid;
910 cmd->data[2] = lower_32_bits(address);
911 cmd->data[3] = upper_32_bits(address);
912 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
913 if (s) /* size bit - we flush more than one 4kb page */
914 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
915 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 }
918
919 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
920 u64 address, size_t size)
921 {
922 u64 pages;
923 bool s;
924
925 pages = iommu_num_pages(address, size, PAGE_SIZE);
926 s = false;
927
928 if (pages > 1) {
929 /*
930 * If we have to flush more than one page, flush all
931 * TLB entries for this domain
932 */
933 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
934 s = true;
935 }
936
937 address &= PAGE_MASK;
938
939 memset(cmd, 0, sizeof(*cmd));
940 cmd->data[0] = devid;
941 cmd->data[0] |= (qdep & 0xff) << 24;
942 cmd->data[1] = devid;
943 cmd->data[2] = lower_32_bits(address);
944 cmd->data[3] = upper_32_bits(address);
945 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
946 if (s)
947 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
948 }
949
950 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
951 u64 address, bool size)
952 {
953 memset(cmd, 0, sizeof(*cmd));
954
955 address &= ~(0xfffULL);
956
957 cmd->data[0] = pasid;
958 cmd->data[1] = domid;
959 cmd->data[2] = lower_32_bits(address);
960 cmd->data[3] = upper_32_bits(address);
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
963 if (size)
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
965 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
966 }
967
968 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
969 int qdep, u64 address, bool size)
970 {
971 memset(cmd, 0, sizeof(*cmd));
972
973 address &= ~(0xfffULL);
974
975 cmd->data[0] = devid;
976 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
977 cmd->data[0] |= (qdep & 0xff) << 24;
978 cmd->data[1] = devid;
979 cmd->data[1] |= (pasid & 0xff) << 16;
980 cmd->data[2] = lower_32_bits(address);
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
982 cmd->data[3] = upper_32_bits(address);
983 if (size)
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
985 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
986 }
987
988 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
989 int status, int tag, bool gn)
990 {
991 memset(cmd, 0, sizeof(*cmd));
992
993 cmd->data[0] = devid;
994 if (gn) {
995 cmd->data[1] = pasid;
996 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
997 }
998 cmd->data[3] = tag & 0x1ff;
999 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1000
1001 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1002 }
1003
1004 static void build_inv_all(struct iommu_cmd *cmd)
1005 {
1006 memset(cmd, 0, sizeof(*cmd));
1007 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1008 }
1009
1010 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1011 {
1012 memset(cmd, 0, sizeof(*cmd));
1013 cmd->data[0] = devid;
1014 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1015 }
1016
1017 /*
1018 * Writes the command to the IOMMUs command buffer and informs the
1019 * hardware about the new command.
1020 */
1021 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1022 struct iommu_cmd *cmd,
1023 bool sync)
1024 {
1025 unsigned int count = 0;
1026 u32 left, next_tail;
1027
1028 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1029 again:
1030 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1031
1032 if (left <= 0x20) {
1033 /* Skip udelay() the first time around */
1034 if (count++) {
1035 if (count == LOOP_TIMEOUT) {
1036 pr_err("Command buffer timeout\n");
1037 return -EIO;
1038 }
1039
1040 udelay(1);
1041 }
1042
1043 /* Update head and recheck remaining space */
1044 iommu->cmd_buf_head = readl(iommu->mmio_base +
1045 MMIO_CMD_HEAD_OFFSET);
1046
1047 goto again;
1048 }
1049
1050 copy_cmd_to_buffer(iommu, cmd);
1051
1052 /* Do we need to make sure all commands are processed? */
1053 iommu->need_sync = sync;
1054
1055 return 0;
1056 }
1057
1058 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1059 struct iommu_cmd *cmd,
1060 bool sync)
1061 {
1062 unsigned long flags;
1063 int ret;
1064
1065 raw_spin_lock_irqsave(&iommu->lock, flags);
1066 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1067 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1068
1069 return ret;
1070 }
1071
1072 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1073 {
1074 return iommu_queue_command_sync(iommu, cmd, true);
1075 }
1076
1077 /*
1078 * This function queues a completion wait command into the command
1079 * buffer of an IOMMU
1080 */
1081 static int iommu_completion_wait(struct amd_iommu *iommu)
1082 {
1083 struct iommu_cmd cmd;
1084 unsigned long flags;
1085 int ret;
1086
1087 if (!iommu->need_sync)
1088 return 0;
1089
1090
1091 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1092
1093 raw_spin_lock_irqsave(&iommu->lock, flags);
1094
1095 iommu->cmd_sem = 0;
1096
1097 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1098 if (ret)
1099 goto out_unlock;
1100
1101 ret = wait_on_sem(&iommu->cmd_sem);
1102
1103 out_unlock:
1104 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1105
1106 return ret;
1107 }
1108
1109 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1110 {
1111 struct iommu_cmd cmd;
1112
1113 build_inv_dte(&cmd, devid);
1114
1115 return iommu_queue_command(iommu, &cmd);
1116 }
1117
1118 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1119 {
1120 u32 devid;
1121
1122 for (devid = 0; devid <= 0xffff; ++devid)
1123 iommu_flush_dte(iommu, devid);
1124
1125 iommu_completion_wait(iommu);
1126 }
1127
1128 /*
1129 * This function uses heavy locking and may disable irqs for some time. But
1130 * this is no issue because it is only called during resume.
1131 */
1132 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1133 {
1134 u32 dom_id;
1135
1136 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1137 struct iommu_cmd cmd;
1138 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1139 dom_id, 1);
1140 iommu_queue_command(iommu, &cmd);
1141 }
1142
1143 iommu_completion_wait(iommu);
1144 }
1145
1146 static void amd_iommu_flush_tlb_domid(struct amd_iommu *iommu, u32 dom_id)
1147 {
1148 struct iommu_cmd cmd;
1149
1150 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1151 dom_id, 1);
1152 iommu_queue_command(iommu, &cmd);
1153
1154 iommu_completion_wait(iommu);
1155 }
1156
1157 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1158 {
1159 struct iommu_cmd cmd;
1160
1161 build_inv_all(&cmd);
1162
1163 iommu_queue_command(iommu, &cmd);
1164 iommu_completion_wait(iommu);
1165 }
1166
1167 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1168 {
1169 struct iommu_cmd cmd;
1170
1171 build_inv_irt(&cmd, devid);
1172
1173 iommu_queue_command(iommu, &cmd);
1174 }
1175
1176 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1177 {
1178 u32 devid;
1179
1180 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1181 iommu_flush_irt(iommu, devid);
1182
1183 iommu_completion_wait(iommu);
1184 }
1185
1186 void iommu_flush_all_caches(struct amd_iommu *iommu)
1187 {
1188 if (iommu_feature(iommu, FEATURE_IA)) {
1189 amd_iommu_flush_all(iommu);
1190 } else {
1191 amd_iommu_flush_dte_all(iommu);
1192 amd_iommu_flush_irt_all(iommu);
1193 amd_iommu_flush_tlb_all(iommu);
1194 }
1195 }
1196
1197 /*
1198 * Command send function for flushing on-device TLB
1199 */
1200 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1201 u64 address, size_t size)
1202 {
1203 struct amd_iommu *iommu;
1204 struct iommu_cmd cmd;
1205 int qdep;
1206
1207 qdep = dev_data->ats.qdep;
1208 iommu = amd_iommu_rlookup_table[dev_data->devid];
1209
1210 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1211
1212 return iommu_queue_command(iommu, &cmd);
1213 }
1214
1215 /*
1216 * Command send function for invalidating a device table entry
1217 */
1218 static int device_flush_dte(struct iommu_dev_data *dev_data)
1219 {
1220 struct amd_iommu *iommu;
1221 u16 alias;
1222 int ret;
1223
1224 iommu = amd_iommu_rlookup_table[dev_data->devid];
1225 alias = dev_data->alias;
1226
1227 ret = iommu_flush_dte(iommu, dev_data->devid);
1228 if (!ret && alias != dev_data->devid)
1229 ret = iommu_flush_dte(iommu, alias);
1230 if (ret)
1231 return ret;
1232
1233 if (dev_data->ats.enabled)
1234 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1235
1236 return ret;
1237 }
1238
1239 /*
1240 * TLB invalidation function which is called from the mapping functions.
1241 * It invalidates a single PTE if the range to flush is within a single
1242 * page. Otherwise it flushes the whole TLB of the IOMMU.
1243 */
1244 static void __domain_flush_pages(struct protection_domain *domain,
1245 u64 address, size_t size, int pde)
1246 {
1247 struct iommu_dev_data *dev_data;
1248 struct iommu_cmd cmd;
1249 int ret = 0, i;
1250
1251 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1252
1253 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1254 if (!domain->dev_iommu[i])
1255 continue;
1256
1257 /*
1258 * Devices of this domain are behind this IOMMU
1259 * We need a TLB flush
1260 */
1261 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1262 }
1263
1264 list_for_each_entry(dev_data, &domain->dev_list, list) {
1265
1266 if (!dev_data->ats.enabled)
1267 continue;
1268
1269 ret |= device_flush_iotlb(dev_data, address, size);
1270 }
1271
1272 WARN_ON(ret);
1273 }
1274
1275 static void domain_flush_pages(struct protection_domain *domain,
1276 u64 address, size_t size)
1277 {
1278 __domain_flush_pages(domain, address, size, 0);
1279 }
1280
1281 /* Flush the whole IO/TLB for a given protection domain */
1282 static void domain_flush_tlb(struct protection_domain *domain)
1283 {
1284 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1285 }
1286
1287 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1288 static void domain_flush_tlb_pde(struct protection_domain *domain)
1289 {
1290 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1291 }
1292
1293 static void domain_flush_complete(struct protection_domain *domain)
1294 {
1295 int i;
1296
1297 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1298 if (domain && !domain->dev_iommu[i])
1299 continue;
1300
1301 /*
1302 * Devices of this domain are behind this IOMMU
1303 * We need to wait for completion of all commands.
1304 */
1305 iommu_completion_wait(amd_iommus[i]);
1306 }
1307 }
1308
1309 /* Flush the not present cache if it exists */
1310 static void domain_flush_np_cache(struct protection_domain *domain,
1311 dma_addr_t iova, size_t size)
1312 {
1313 if (unlikely(amd_iommu_np_cache)) {
1314 domain_flush_pages(domain, iova, size);
1315 domain_flush_complete(domain);
1316 }
1317 }
1318
1319
1320 /*
1321 * This function flushes the DTEs for all devices in domain
1322 */
1323 static void domain_flush_devices(struct protection_domain *domain)
1324 {
1325 struct iommu_dev_data *dev_data;
1326
1327 list_for_each_entry(dev_data, &domain->dev_list, list)
1328 device_flush_dte(dev_data);
1329 }
1330
1331 /****************************************************************************
1332 *
1333 * The functions below are used the create the page table mappings for
1334 * unity mapped regions.
1335 *
1336 ****************************************************************************/
1337
1338 static void free_page_list(struct page *freelist)
1339 {
1340 while (freelist != NULL) {
1341 unsigned long p = (unsigned long)page_address(freelist);
1342 freelist = freelist->freelist;
1343 free_page(p);
1344 }
1345 }
1346
1347 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1348 {
1349 struct page *p = virt_to_page((void *)pt);
1350
1351 p->freelist = freelist;
1352
1353 return p;
1354 }
1355
1356 #define DEFINE_FREE_PT_FN(LVL, FN) \
1357 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1358 { \
1359 unsigned long p; \
1360 u64 *pt; \
1361 int i; \
1362 \
1363 pt = (u64 *)__pt; \
1364 \
1365 for (i = 0; i < 512; ++i) { \
1366 /* PTE present? */ \
1367 if (!IOMMU_PTE_PRESENT(pt[i])) \
1368 continue; \
1369 \
1370 /* Large PTE? */ \
1371 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1372 PM_PTE_LEVEL(pt[i]) == 7) \
1373 continue; \
1374 \
1375 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1376 freelist = FN(p, freelist); \
1377 } \
1378 \
1379 return free_pt_page((unsigned long)pt, freelist); \
1380 }
1381
1382 DEFINE_FREE_PT_FN(l2, free_pt_page)
1383 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1384 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1385 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1386 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1387
1388 static struct page *free_sub_pt(unsigned long root, int mode,
1389 struct page *freelist)
1390 {
1391 switch (mode) {
1392 case PAGE_MODE_NONE:
1393 case PAGE_MODE_7_LEVEL:
1394 break;
1395 case PAGE_MODE_1_LEVEL:
1396 freelist = free_pt_page(root, freelist);
1397 break;
1398 case PAGE_MODE_2_LEVEL:
1399 freelist = free_pt_l2(root, freelist);
1400 break;
1401 case PAGE_MODE_3_LEVEL:
1402 freelist = free_pt_l3(root, freelist);
1403 break;
1404 case PAGE_MODE_4_LEVEL:
1405 freelist = free_pt_l4(root, freelist);
1406 break;
1407 case PAGE_MODE_5_LEVEL:
1408 freelist = free_pt_l5(root, freelist);
1409 break;
1410 case PAGE_MODE_6_LEVEL:
1411 freelist = free_pt_l6(root, freelist);
1412 break;
1413 default:
1414 BUG();
1415 }
1416
1417 return freelist;
1418 }
1419
1420 static void free_pagetable(struct protection_domain *domain)
1421 {
1422 unsigned long root = (unsigned long)domain->pt_root;
1423 struct page *freelist = NULL;
1424
1425 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1426 domain->mode > PAGE_MODE_6_LEVEL);
1427
1428 free_sub_pt(root, domain->mode, freelist);
1429
1430 free_page_list(freelist);
1431 }
1432
1433 /*
1434 * This function is used to add another level to an IO page table. Adding
1435 * another level increases the size of the address space by 9 bits to a size up
1436 * to 64 bits.
1437 */
1438 static void increase_address_space(struct protection_domain *domain,
1439 gfp_t gfp)
1440 {
1441 unsigned long flags;
1442 u64 *pte;
1443
1444 spin_lock_irqsave(&domain->lock, flags);
1445
1446 if (WARN_ON_ONCE(domain->mode == PAGE_MODE_6_LEVEL))
1447 /* address space already 64 bit large */
1448 goto out;
1449
1450 pte = (void *)get_zeroed_page(gfp);
1451 if (!pte)
1452 goto out;
1453
1454 *pte = PM_LEVEL_PDE(domain->mode,
1455 iommu_virt_to_phys(domain->pt_root));
1456 domain->pt_root = pte;
1457 domain->mode += 1;
1458 domain->updated = true;
1459
1460 out:
1461 spin_unlock_irqrestore(&domain->lock, flags);
1462
1463 return;
1464 }
1465
1466 static u64 *alloc_pte(struct protection_domain *domain,
1467 unsigned long address,
1468 unsigned long page_size,
1469 u64 **pte_page,
1470 gfp_t gfp)
1471 {
1472 int level, end_lvl;
1473 u64 *pte, *page;
1474
1475 BUG_ON(!is_power_of_2(page_size));
1476
1477 while (address > PM_LEVEL_SIZE(domain->mode))
1478 increase_address_space(domain, gfp);
1479
1480 level = domain->mode - 1;
1481 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1482 address = PAGE_SIZE_ALIGN(address, page_size);
1483 end_lvl = PAGE_SIZE_LEVEL(page_size);
1484
1485 while (level > end_lvl) {
1486 u64 __pte, __npte;
1487 int pte_level;
1488
1489 __pte = *pte;
1490 pte_level = PM_PTE_LEVEL(__pte);
1491
1492 if (!IOMMU_PTE_PRESENT(__pte) ||
1493 pte_level == PAGE_MODE_7_LEVEL) {
1494 page = (u64 *)get_zeroed_page(gfp);
1495 if (!page)
1496 return NULL;
1497
1498 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1499
1500 /* pte could have been changed somewhere. */
1501 if (cmpxchg64(pte, __pte, __npte) != __pte)
1502 free_page((unsigned long)page);
1503 else if (pte_level == PAGE_MODE_7_LEVEL)
1504 domain->updated = true;
1505
1506 continue;
1507 }
1508
1509 /* No level skipping support yet */
1510 if (pte_level != level)
1511 return NULL;
1512
1513 level -= 1;
1514
1515 pte = IOMMU_PTE_PAGE(__pte);
1516
1517 if (pte_page && level == end_lvl)
1518 *pte_page = pte;
1519
1520 pte = &pte[PM_LEVEL_INDEX(level, address)];
1521 }
1522
1523 return pte;
1524 }
1525
1526 /*
1527 * This function checks if there is a PTE for a given dma address. If
1528 * there is one, it returns the pointer to it.
1529 */
1530 static u64 *fetch_pte(struct protection_domain *domain,
1531 unsigned long address,
1532 unsigned long *page_size)
1533 {
1534 int level;
1535 u64 *pte;
1536
1537 *page_size = 0;
1538
1539 if (address > PM_LEVEL_SIZE(domain->mode))
1540 return NULL;
1541
1542 level = domain->mode - 1;
1543 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1544 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1545
1546 while (level > 0) {
1547
1548 /* Not Present */
1549 if (!IOMMU_PTE_PRESENT(*pte))
1550 return NULL;
1551
1552 /* Large PTE */
1553 if (PM_PTE_LEVEL(*pte) == 7 ||
1554 PM_PTE_LEVEL(*pte) == 0)
1555 break;
1556
1557 /* No level skipping support yet */
1558 if (PM_PTE_LEVEL(*pte) != level)
1559 return NULL;
1560
1561 level -= 1;
1562
1563 /* Walk to the next level */
1564 pte = IOMMU_PTE_PAGE(*pte);
1565 pte = &pte[PM_LEVEL_INDEX(level, address)];
1566 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1567 }
1568
1569 if (PM_PTE_LEVEL(*pte) == 0x07) {
1570 unsigned long pte_mask;
1571
1572 /*
1573 * If we have a series of large PTEs, make
1574 * sure to return a pointer to the first one.
1575 */
1576 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1577 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1578 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1579 }
1580
1581 return pte;
1582 }
1583
1584 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1585 {
1586 unsigned long pt;
1587 int mode;
1588
1589 while (cmpxchg64(pte, pteval, 0) != pteval) {
1590 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1591 pteval = *pte;
1592 }
1593
1594 if (!IOMMU_PTE_PRESENT(pteval))
1595 return freelist;
1596
1597 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1598 mode = IOMMU_PTE_MODE(pteval);
1599
1600 return free_sub_pt(pt, mode, freelist);
1601 }
1602
1603 /*
1604 * Generic mapping functions. It maps a physical address into a DMA
1605 * address space. It allocates the page table pages if necessary.
1606 * In the future it can be extended to a generic mapping function
1607 * supporting all features of AMD IOMMU page tables like level skipping
1608 * and full 64 bit address spaces.
1609 */
1610 static int iommu_map_page(struct protection_domain *dom,
1611 unsigned long bus_addr,
1612 unsigned long phys_addr,
1613 unsigned long page_size,
1614 int prot,
1615 gfp_t gfp)
1616 {
1617 struct page *freelist = NULL;
1618 u64 __pte, *pte;
1619 int i, count;
1620
1621 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1622 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1623
1624 if (!(prot & IOMMU_PROT_MASK))
1625 return -EINVAL;
1626
1627 count = PAGE_SIZE_PTE_COUNT(page_size);
1628 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1629
1630 if (!pte)
1631 return -ENOMEM;
1632
1633 for (i = 0; i < count; ++i)
1634 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1635
1636 if (freelist != NULL)
1637 dom->updated = true;
1638
1639 if (count > 1) {
1640 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1641 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1642 } else
1643 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1644
1645 if (prot & IOMMU_PROT_IR)
1646 __pte |= IOMMU_PTE_IR;
1647 if (prot & IOMMU_PROT_IW)
1648 __pte |= IOMMU_PTE_IW;
1649
1650 for (i = 0; i < count; ++i)
1651 pte[i] = __pte;
1652
1653 update_domain(dom);
1654
1655 /* Everything flushed out, free pages now */
1656 free_page_list(freelist);
1657
1658 return 0;
1659 }
1660
1661 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1662 unsigned long bus_addr,
1663 unsigned long page_size)
1664 {
1665 unsigned long long unmapped;
1666 unsigned long unmap_size;
1667 u64 *pte;
1668
1669 BUG_ON(!is_power_of_2(page_size));
1670
1671 unmapped = 0;
1672
1673 while (unmapped < page_size) {
1674
1675 pte = fetch_pte(dom, bus_addr, &unmap_size);
1676
1677 if (pte) {
1678 int i, count;
1679
1680 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1681 for (i = 0; i < count; i++)
1682 pte[i] = 0ULL;
1683 }
1684
1685 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1686 unmapped += unmap_size;
1687 }
1688
1689 BUG_ON(unmapped && !is_power_of_2(unmapped));
1690
1691 return unmapped;
1692 }
1693
1694 /****************************************************************************
1695 *
1696 * The next functions belong to the address allocator for the dma_ops
1697 * interface functions.
1698 *
1699 ****************************************************************************/
1700
1701
1702 static unsigned long dma_ops_alloc_iova(struct device *dev,
1703 struct dma_ops_domain *dma_dom,
1704 unsigned int pages, u64 dma_mask)
1705 {
1706 unsigned long pfn = 0;
1707
1708 pages = __roundup_pow_of_two(pages);
1709
1710 if (dma_mask > DMA_BIT_MASK(32))
1711 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1712 IOVA_PFN(DMA_BIT_MASK(32)), false);
1713
1714 if (!pfn)
1715 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1716 IOVA_PFN(dma_mask), true);
1717
1718 return (pfn << PAGE_SHIFT);
1719 }
1720
1721 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1722 unsigned long address,
1723 unsigned int pages)
1724 {
1725 pages = __roundup_pow_of_two(pages);
1726 address >>= PAGE_SHIFT;
1727
1728 free_iova_fast(&dma_dom->iovad, address, pages);
1729 }
1730
1731 /****************************************************************************
1732 *
1733 * The next functions belong to the domain allocation. A domain is
1734 * allocated for every IOMMU as the default domain. If device isolation
1735 * is enabled, every device get its own domain. The most important thing
1736 * about domains is the page table mapping the DMA address space they
1737 * contain.
1738 *
1739 ****************************************************************************/
1740
1741 static u16 domain_id_alloc(void)
1742 {
1743 int id;
1744
1745 spin_lock(&pd_bitmap_lock);
1746 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1747 BUG_ON(id == 0);
1748 if (id > 0 && id < MAX_DOMAIN_ID)
1749 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1750 else
1751 id = 0;
1752 spin_unlock(&pd_bitmap_lock);
1753
1754 return id;
1755 }
1756
1757 static void domain_id_free(int id)
1758 {
1759 spin_lock(&pd_bitmap_lock);
1760 if (id > 0 && id < MAX_DOMAIN_ID)
1761 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1762 spin_unlock(&pd_bitmap_lock);
1763 }
1764
1765 static void free_gcr3_tbl_level1(u64 *tbl)
1766 {
1767 u64 *ptr;
1768 int i;
1769
1770 for (i = 0; i < 512; ++i) {
1771 if (!(tbl[i] & GCR3_VALID))
1772 continue;
1773
1774 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1775
1776 free_page((unsigned long)ptr);
1777 }
1778 }
1779
1780 static void free_gcr3_tbl_level2(u64 *tbl)
1781 {
1782 u64 *ptr;
1783 int i;
1784
1785 for (i = 0; i < 512; ++i) {
1786 if (!(tbl[i] & GCR3_VALID))
1787 continue;
1788
1789 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1790
1791 free_gcr3_tbl_level1(ptr);
1792 }
1793 }
1794
1795 static void free_gcr3_table(struct protection_domain *domain)
1796 {
1797 if (domain->glx == 2)
1798 free_gcr3_tbl_level2(domain->gcr3_tbl);
1799 else if (domain->glx == 1)
1800 free_gcr3_tbl_level1(domain->gcr3_tbl);
1801 else
1802 BUG_ON(domain->glx != 0);
1803
1804 free_page((unsigned long)domain->gcr3_tbl);
1805 }
1806
1807 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1808 {
1809 domain_flush_tlb(&dom->domain);
1810 domain_flush_complete(&dom->domain);
1811 }
1812
1813 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1814 {
1815 struct dma_ops_domain *dom;
1816
1817 dom = container_of(iovad, struct dma_ops_domain, iovad);
1818
1819 dma_ops_domain_flush_tlb(dom);
1820 }
1821
1822 /*
1823 * Free a domain, only used if something went wrong in the
1824 * allocation path and we need to free an already allocated page table
1825 */
1826 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1827 {
1828 if (!dom)
1829 return;
1830
1831 put_iova_domain(&dom->iovad);
1832
1833 free_pagetable(&dom->domain);
1834
1835 if (dom->domain.id)
1836 domain_id_free(dom->domain.id);
1837
1838 kfree(dom);
1839 }
1840
1841 /*
1842 * Allocates a new protection domain usable for the dma_ops functions.
1843 * It also initializes the page table and the address allocator data
1844 * structures required for the dma_ops interface
1845 */
1846 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1847 {
1848 struct dma_ops_domain *dma_dom;
1849
1850 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1851 if (!dma_dom)
1852 return NULL;
1853
1854 if (protection_domain_init(&dma_dom->domain))
1855 goto free_dma_dom;
1856
1857 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1858 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1859 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1860 if (!dma_dom->domain.pt_root)
1861 goto free_dma_dom;
1862
1863 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1864
1865 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1866 goto free_dma_dom;
1867
1868 /* Initialize reserved ranges */
1869 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1870
1871 return dma_dom;
1872
1873 free_dma_dom:
1874 dma_ops_domain_free(dma_dom);
1875
1876 return NULL;
1877 }
1878
1879 /*
1880 * little helper function to check whether a given protection domain is a
1881 * dma_ops domain
1882 */
1883 static bool dma_ops_domain(struct protection_domain *domain)
1884 {
1885 return domain->flags & PD_DMA_OPS_MASK;
1886 }
1887
1888 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1889 bool ats, bool ppr)
1890 {
1891 u64 pte_root = 0;
1892 u64 flags = 0;
1893 u32 old_domid;
1894
1895 if (domain->mode != PAGE_MODE_NONE)
1896 pte_root = iommu_virt_to_phys(domain->pt_root);
1897
1898 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1899 << DEV_ENTRY_MODE_SHIFT;
1900 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1901
1902 flags = amd_iommu_dev_table[devid].data[1];
1903
1904 if (ats)
1905 flags |= DTE_FLAG_IOTLB;
1906
1907 if (ppr) {
1908 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1909
1910 if (iommu_feature(iommu, FEATURE_EPHSUP))
1911 pte_root |= 1ULL << DEV_ENTRY_PPR;
1912 }
1913
1914 if (domain->flags & PD_IOMMUV2_MASK) {
1915 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1916 u64 glx = domain->glx;
1917 u64 tmp;
1918
1919 pte_root |= DTE_FLAG_GV;
1920 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1921
1922 /* First mask out possible old values for GCR3 table */
1923 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1924 flags &= ~tmp;
1925
1926 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1927 flags &= ~tmp;
1928
1929 /* Encode GCR3 table into DTE */
1930 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1931 pte_root |= tmp;
1932
1933 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1934 flags |= tmp;
1935
1936 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1937 flags |= tmp;
1938 }
1939
1940 flags &= ~DEV_DOMID_MASK;
1941 flags |= domain->id;
1942
1943 old_domid = amd_iommu_dev_table[devid].data[1] & DEV_DOMID_MASK;
1944 amd_iommu_dev_table[devid].data[1] = flags;
1945 amd_iommu_dev_table[devid].data[0] = pte_root;
1946
1947 /*
1948 * A kdump kernel might be replacing a domain ID that was copied from
1949 * the previous kernel--if so, it needs to flush the translation cache
1950 * entries for the old domain ID that is being overwritten
1951 */
1952 if (old_domid) {
1953 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1954
1955 amd_iommu_flush_tlb_domid(iommu, old_domid);
1956 }
1957 }
1958
1959 static void clear_dte_entry(u16 devid)
1960 {
1961 /* remove entry from the device table seen by the hardware */
1962 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1963 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1964
1965 amd_iommu_apply_erratum_63(devid);
1966 }
1967
1968 static void do_attach(struct iommu_dev_data *dev_data,
1969 struct protection_domain *domain)
1970 {
1971 struct amd_iommu *iommu;
1972 u16 alias;
1973 bool ats;
1974
1975 iommu = amd_iommu_rlookup_table[dev_data->devid];
1976 alias = dev_data->alias;
1977 ats = dev_data->ats.enabled;
1978
1979 /* Update data structures */
1980 dev_data->domain = domain;
1981 list_add(&dev_data->list, &domain->dev_list);
1982
1983 /* Do reference counting */
1984 domain->dev_iommu[iommu->index] += 1;
1985 domain->dev_cnt += 1;
1986
1987 /* Update device table */
1988 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1989 if (alias != dev_data->devid)
1990 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1991
1992 device_flush_dte(dev_data);
1993 }
1994
1995 static void do_detach(struct iommu_dev_data *dev_data)
1996 {
1997 struct protection_domain *domain = dev_data->domain;
1998 struct amd_iommu *iommu;
1999 u16 alias;
2000
2001 iommu = amd_iommu_rlookup_table[dev_data->devid];
2002 alias = dev_data->alias;
2003
2004 /* Update data structures */
2005 dev_data->domain = NULL;
2006 list_del(&dev_data->list);
2007 clear_dte_entry(dev_data->devid);
2008 if (alias != dev_data->devid)
2009 clear_dte_entry(alias);
2010
2011 /* Flush the DTE entry */
2012 device_flush_dte(dev_data);
2013
2014 /* Flush IOTLB */
2015 domain_flush_tlb_pde(domain);
2016
2017 /* Wait for the flushes to finish */
2018 domain_flush_complete(domain);
2019
2020 /* decrease reference counters - needs to happen after the flushes */
2021 domain->dev_iommu[iommu->index] -= 1;
2022 domain->dev_cnt -= 1;
2023 }
2024
2025 /*
2026 * If a device is not yet associated with a domain, this function makes the
2027 * device visible in the domain
2028 */
2029 static int __attach_device(struct iommu_dev_data *dev_data,
2030 struct protection_domain *domain)
2031 {
2032 int ret;
2033
2034 /* lock domain */
2035 spin_lock(&domain->lock);
2036
2037 ret = -EBUSY;
2038 if (dev_data->domain != NULL)
2039 goto out_unlock;
2040
2041 /* Attach alias group root */
2042 do_attach(dev_data, domain);
2043
2044 ret = 0;
2045
2046 out_unlock:
2047
2048 /* ready */
2049 spin_unlock(&domain->lock);
2050
2051 return ret;
2052 }
2053
2054
2055 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2056 {
2057 pci_disable_ats(pdev);
2058 pci_disable_pri(pdev);
2059 pci_disable_pasid(pdev);
2060 }
2061
2062 /* FIXME: Change generic reset-function to do the same */
2063 static int pri_reset_while_enabled(struct pci_dev *pdev)
2064 {
2065 u16 control;
2066 int pos;
2067
2068 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2069 if (!pos)
2070 return -EINVAL;
2071
2072 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2073 control |= PCI_PRI_CTRL_RESET;
2074 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2075
2076 return 0;
2077 }
2078
2079 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2080 {
2081 bool reset_enable;
2082 int reqs, ret;
2083
2084 /* FIXME: Hardcode number of outstanding requests for now */
2085 reqs = 32;
2086 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2087 reqs = 1;
2088 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2089
2090 /* Only allow access to user-accessible pages */
2091 ret = pci_enable_pasid(pdev, 0);
2092 if (ret)
2093 goto out_err;
2094
2095 /* First reset the PRI state of the device */
2096 ret = pci_reset_pri(pdev);
2097 if (ret)
2098 goto out_err;
2099
2100 /* Enable PRI */
2101 ret = pci_enable_pri(pdev, reqs);
2102 if (ret)
2103 goto out_err;
2104
2105 if (reset_enable) {
2106 ret = pri_reset_while_enabled(pdev);
2107 if (ret)
2108 goto out_err;
2109 }
2110
2111 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2112 if (ret)
2113 goto out_err;
2114
2115 return 0;
2116
2117 out_err:
2118 pci_disable_pri(pdev);
2119 pci_disable_pasid(pdev);
2120
2121 return ret;
2122 }
2123
2124 /*
2125 * If a device is not yet associated with a domain, this function makes the
2126 * device visible in the domain
2127 */
2128 static int attach_device(struct device *dev,
2129 struct protection_domain *domain)
2130 {
2131 struct pci_dev *pdev;
2132 struct iommu_dev_data *dev_data;
2133 unsigned long flags;
2134 int ret;
2135
2136 dev_data = get_dev_data(dev);
2137
2138 if (!dev_is_pci(dev))
2139 goto skip_ats_check;
2140
2141 pdev = to_pci_dev(dev);
2142 if (domain->flags & PD_IOMMUV2_MASK) {
2143 if (!dev_data->passthrough)
2144 return -EINVAL;
2145
2146 if (dev_data->iommu_v2) {
2147 if (pdev_iommuv2_enable(pdev) != 0)
2148 return -EINVAL;
2149
2150 dev_data->ats.enabled = true;
2151 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2152 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2153 }
2154 } else if (amd_iommu_iotlb_sup &&
2155 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2156 dev_data->ats.enabled = true;
2157 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2158 }
2159
2160 skip_ats_check:
2161 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2162 ret = __attach_device(dev_data, domain);
2163 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2164
2165 /*
2166 * We might boot into a crash-kernel here. The crashed kernel
2167 * left the caches in the IOMMU dirty. So we have to flush
2168 * here to evict all dirty stuff.
2169 */
2170 domain_flush_tlb_pde(domain);
2171
2172 return ret;
2173 }
2174
2175 /*
2176 * Removes a device from a protection domain (unlocked)
2177 */
2178 static void __detach_device(struct iommu_dev_data *dev_data)
2179 {
2180 struct protection_domain *domain;
2181
2182 domain = dev_data->domain;
2183
2184 spin_lock(&domain->lock);
2185
2186 do_detach(dev_data);
2187
2188 spin_unlock(&domain->lock);
2189 }
2190
2191 /*
2192 * Removes a device from a protection domain (with devtable_lock held)
2193 */
2194 static void detach_device(struct device *dev)
2195 {
2196 struct protection_domain *domain;
2197 struct iommu_dev_data *dev_data;
2198 unsigned long flags;
2199
2200 dev_data = get_dev_data(dev);
2201 domain = dev_data->domain;
2202
2203 /*
2204 * First check if the device is still attached. It might already
2205 * be detached from its domain because the generic
2206 * iommu_detach_group code detached it and we try again here in
2207 * our alias handling.
2208 */
2209 if (WARN_ON(!dev_data->domain))
2210 return;
2211
2212 /* lock device table */
2213 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2214 __detach_device(dev_data);
2215 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2216
2217 if (!dev_is_pci(dev))
2218 return;
2219
2220 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2221 pdev_iommuv2_disable(to_pci_dev(dev));
2222 else if (dev_data->ats.enabled)
2223 pci_disable_ats(to_pci_dev(dev));
2224
2225 dev_data->ats.enabled = false;
2226 }
2227
2228 static int amd_iommu_add_device(struct device *dev)
2229 {
2230 struct iommu_dev_data *dev_data;
2231 struct iommu_domain *domain;
2232 struct amd_iommu *iommu;
2233 int ret, devid;
2234
2235 if (!check_device(dev) || get_dev_data(dev))
2236 return 0;
2237
2238 devid = get_device_id(dev);
2239 if (devid < 0)
2240 return devid;
2241
2242 iommu = amd_iommu_rlookup_table[devid];
2243
2244 ret = iommu_init_device(dev);
2245 if (ret) {
2246 if (ret != -ENOTSUPP)
2247 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2248
2249 iommu_ignore_device(dev);
2250 dev->dma_ops = NULL;
2251 goto out;
2252 }
2253 init_iommu_group(dev);
2254
2255 dev_data = get_dev_data(dev);
2256
2257 BUG_ON(!dev_data);
2258
2259 if (iommu_pass_through || dev_data->iommu_v2)
2260 iommu_request_dm_for_dev(dev);
2261
2262 /* Domains are initialized for this device - have a look what we ended up with */
2263 domain = iommu_get_domain_for_dev(dev);
2264 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2265 dev_data->passthrough = true;
2266 else
2267 dev->dma_ops = &amd_iommu_dma_ops;
2268
2269 out:
2270 iommu_completion_wait(iommu);
2271
2272 return 0;
2273 }
2274
2275 static void amd_iommu_remove_device(struct device *dev)
2276 {
2277 struct amd_iommu *iommu;
2278 int devid;
2279
2280 if (!check_device(dev))
2281 return;
2282
2283 devid = get_device_id(dev);
2284 if (devid < 0)
2285 return;
2286
2287 iommu = amd_iommu_rlookup_table[devid];
2288
2289 iommu_uninit_device(dev);
2290 iommu_completion_wait(iommu);
2291 }
2292
2293 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2294 {
2295 if (dev_is_pci(dev))
2296 return pci_device_group(dev);
2297
2298 return acpihid_device_group(dev);
2299 }
2300
2301 /*****************************************************************************
2302 *
2303 * The next functions belong to the dma_ops mapping/unmapping code.
2304 *
2305 *****************************************************************************/
2306
2307 /*
2308 * In the dma_ops path we only have the struct device. This function
2309 * finds the corresponding IOMMU, the protection domain and the
2310 * requestor id for a given device.
2311 * If the device is not yet associated with a domain this is also done
2312 * in this function.
2313 */
2314 static struct protection_domain *get_domain(struct device *dev)
2315 {
2316 struct protection_domain *domain;
2317 struct iommu_domain *io_domain;
2318
2319 if (!check_device(dev))
2320 return ERR_PTR(-EINVAL);
2321
2322 domain = get_dev_data(dev)->domain;
2323 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2324 get_dev_data(dev)->defer_attach = false;
2325 io_domain = iommu_get_domain_for_dev(dev);
2326 domain = to_pdomain(io_domain);
2327 attach_device(dev, domain);
2328 }
2329 if (domain == NULL)
2330 return ERR_PTR(-EBUSY);
2331
2332 if (!dma_ops_domain(domain))
2333 return ERR_PTR(-EBUSY);
2334
2335 return domain;
2336 }
2337
2338 static void update_device_table(struct protection_domain *domain)
2339 {
2340 struct iommu_dev_data *dev_data;
2341
2342 list_for_each_entry(dev_data, &domain->dev_list, list) {
2343 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2344 dev_data->iommu_v2);
2345
2346 if (dev_data->devid == dev_data->alias)
2347 continue;
2348
2349 /* There is an alias, update device table entry for it */
2350 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2351 dev_data->iommu_v2);
2352 }
2353 }
2354
2355 static void update_domain(struct protection_domain *domain)
2356 {
2357 if (!domain->updated)
2358 return;
2359
2360 update_device_table(domain);
2361
2362 domain_flush_devices(domain);
2363 domain_flush_tlb_pde(domain);
2364
2365 domain->updated = false;
2366 }
2367
2368 static int dir2prot(enum dma_data_direction direction)
2369 {
2370 if (direction == DMA_TO_DEVICE)
2371 return IOMMU_PROT_IR;
2372 else if (direction == DMA_FROM_DEVICE)
2373 return IOMMU_PROT_IW;
2374 else if (direction == DMA_BIDIRECTIONAL)
2375 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2376 else
2377 return 0;
2378 }
2379
2380 /*
2381 * This function contains common code for mapping of a physically
2382 * contiguous memory region into DMA address space. It is used by all
2383 * mapping functions provided with this IOMMU driver.
2384 * Must be called with the domain lock held.
2385 */
2386 static dma_addr_t __map_single(struct device *dev,
2387 struct dma_ops_domain *dma_dom,
2388 phys_addr_t paddr,
2389 size_t size,
2390 enum dma_data_direction direction,
2391 u64 dma_mask)
2392 {
2393 dma_addr_t offset = paddr & ~PAGE_MASK;
2394 dma_addr_t address, start, ret;
2395 unsigned int pages;
2396 int prot = 0;
2397 int i;
2398
2399 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2400 paddr &= PAGE_MASK;
2401
2402 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2403 if (!address)
2404 goto out;
2405
2406 prot = dir2prot(direction);
2407
2408 start = address;
2409 for (i = 0; i < pages; ++i) {
2410 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2411 PAGE_SIZE, prot, GFP_ATOMIC);
2412 if (ret)
2413 goto out_unmap;
2414
2415 paddr += PAGE_SIZE;
2416 start += PAGE_SIZE;
2417 }
2418 address += offset;
2419
2420 domain_flush_np_cache(&dma_dom->domain, address, size);
2421
2422 out:
2423 return address;
2424
2425 out_unmap:
2426
2427 for (--i; i >= 0; --i) {
2428 start -= PAGE_SIZE;
2429 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2430 }
2431
2432 domain_flush_tlb(&dma_dom->domain);
2433 domain_flush_complete(&dma_dom->domain);
2434
2435 dma_ops_free_iova(dma_dom, address, pages);
2436
2437 return DMA_MAPPING_ERROR;
2438 }
2439
2440 /*
2441 * Does the reverse of the __map_single function. Must be called with
2442 * the domain lock held too
2443 */
2444 static void __unmap_single(struct dma_ops_domain *dma_dom,
2445 dma_addr_t dma_addr,
2446 size_t size,
2447 int dir)
2448 {
2449 dma_addr_t i, start;
2450 unsigned int pages;
2451
2452 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2453 dma_addr &= PAGE_MASK;
2454 start = dma_addr;
2455
2456 for (i = 0; i < pages; ++i) {
2457 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2458 start += PAGE_SIZE;
2459 }
2460
2461 if (amd_iommu_unmap_flush) {
2462 domain_flush_tlb(&dma_dom->domain);
2463 domain_flush_complete(&dma_dom->domain);
2464 dma_ops_free_iova(dma_dom, dma_addr, pages);
2465 } else {
2466 pages = __roundup_pow_of_two(pages);
2467 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2468 }
2469 }
2470
2471 /*
2472 * The exported map_single function for dma_ops.
2473 */
2474 static dma_addr_t map_page(struct device *dev, struct page *page,
2475 unsigned long offset, size_t size,
2476 enum dma_data_direction dir,
2477 unsigned long attrs)
2478 {
2479 phys_addr_t paddr = page_to_phys(page) + offset;
2480 struct protection_domain *domain;
2481 struct dma_ops_domain *dma_dom;
2482 u64 dma_mask;
2483
2484 domain = get_domain(dev);
2485 if (PTR_ERR(domain) == -EINVAL)
2486 return (dma_addr_t)paddr;
2487 else if (IS_ERR(domain))
2488 return DMA_MAPPING_ERROR;
2489
2490 dma_mask = *dev->dma_mask;
2491 dma_dom = to_dma_ops_domain(domain);
2492
2493 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2494 }
2495
2496 /*
2497 * The exported unmap_single function for dma_ops.
2498 */
2499 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2500 enum dma_data_direction dir, unsigned long attrs)
2501 {
2502 struct protection_domain *domain;
2503 struct dma_ops_domain *dma_dom;
2504
2505 domain = get_domain(dev);
2506 if (IS_ERR(domain))
2507 return;
2508
2509 dma_dom = to_dma_ops_domain(domain);
2510
2511 __unmap_single(dma_dom, dma_addr, size, dir);
2512 }
2513
2514 static int sg_num_pages(struct device *dev,
2515 struct scatterlist *sglist,
2516 int nelems)
2517 {
2518 unsigned long mask, boundary_size;
2519 struct scatterlist *s;
2520 int i, npages = 0;
2521
2522 mask = dma_get_seg_boundary(dev);
2523 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2524 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2525
2526 for_each_sg(sglist, s, nelems, i) {
2527 int p, n;
2528
2529 s->dma_address = npages << PAGE_SHIFT;
2530 p = npages % boundary_size;
2531 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2532 if (p + n > boundary_size)
2533 npages += boundary_size - p;
2534 npages += n;
2535 }
2536
2537 return npages;
2538 }
2539
2540 /*
2541 * The exported map_sg function for dma_ops (handles scatter-gather
2542 * lists).
2543 */
2544 static int map_sg(struct device *dev, struct scatterlist *sglist,
2545 int nelems, enum dma_data_direction direction,
2546 unsigned long attrs)
2547 {
2548 int mapped_pages = 0, npages = 0, prot = 0, i;
2549 struct protection_domain *domain;
2550 struct dma_ops_domain *dma_dom;
2551 struct scatterlist *s;
2552 unsigned long address;
2553 u64 dma_mask;
2554 int ret;
2555
2556 domain = get_domain(dev);
2557 if (IS_ERR(domain))
2558 return 0;
2559
2560 dma_dom = to_dma_ops_domain(domain);
2561 dma_mask = *dev->dma_mask;
2562
2563 npages = sg_num_pages(dev, sglist, nelems);
2564
2565 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2566 if (!address)
2567 goto out_err;
2568
2569 prot = dir2prot(direction);
2570
2571 /* Map all sg entries */
2572 for_each_sg(sglist, s, nelems, i) {
2573 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2574
2575 for (j = 0; j < pages; ++j) {
2576 unsigned long bus_addr, phys_addr;
2577
2578 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2579 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2580 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2581 if (ret)
2582 goto out_unmap;
2583
2584 mapped_pages += 1;
2585 }
2586 }
2587
2588 /* Everything is mapped - write the right values into s->dma_address */
2589 for_each_sg(sglist, s, nelems, i) {
2590 /*
2591 * Add in the remaining piece of the scatter-gather offset that
2592 * was masked out when we were determining the physical address
2593 * via (sg_phys(s) & PAGE_MASK) earlier.
2594 */
2595 s->dma_address += address + (s->offset & ~PAGE_MASK);
2596 s->dma_length = s->length;
2597 }
2598
2599 if (s)
2600 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2601
2602 return nelems;
2603
2604 out_unmap:
2605 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2606 npages, ret);
2607
2608 for_each_sg(sglist, s, nelems, i) {
2609 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2610
2611 for (j = 0; j < pages; ++j) {
2612 unsigned long bus_addr;
2613
2614 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2615 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2616
2617 if (--mapped_pages == 0)
2618 goto out_free_iova;
2619 }
2620 }
2621
2622 out_free_iova:
2623 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2624
2625 out_err:
2626 return 0;
2627 }
2628
2629 /*
2630 * The exported map_sg function for dma_ops (handles scatter-gather
2631 * lists).
2632 */
2633 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2634 int nelems, enum dma_data_direction dir,
2635 unsigned long attrs)
2636 {
2637 struct protection_domain *domain;
2638 struct dma_ops_domain *dma_dom;
2639 unsigned long startaddr;
2640 int npages;
2641
2642 domain = get_domain(dev);
2643 if (IS_ERR(domain))
2644 return;
2645
2646 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2647 dma_dom = to_dma_ops_domain(domain);
2648 npages = sg_num_pages(dev, sglist, nelems);
2649
2650 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2651 }
2652
2653 /*
2654 * The exported alloc_coherent function for dma_ops.
2655 */
2656 static void *alloc_coherent(struct device *dev, size_t size,
2657 dma_addr_t *dma_addr, gfp_t flag,
2658 unsigned long attrs)
2659 {
2660 u64 dma_mask = dev->coherent_dma_mask;
2661 struct protection_domain *domain;
2662 struct dma_ops_domain *dma_dom;
2663 struct page *page;
2664
2665 domain = get_domain(dev);
2666 if (PTR_ERR(domain) == -EINVAL) {
2667 page = alloc_pages(flag, get_order(size));
2668 *dma_addr = page_to_phys(page);
2669 return page_address(page);
2670 } else if (IS_ERR(domain))
2671 return NULL;
2672
2673 dma_dom = to_dma_ops_domain(domain);
2674 size = PAGE_ALIGN(size);
2675 dma_mask = dev->coherent_dma_mask;
2676 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2677 flag |= __GFP_ZERO;
2678
2679 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2680 if (!page) {
2681 if (!gfpflags_allow_blocking(flag))
2682 return NULL;
2683
2684 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2685 get_order(size), flag & __GFP_NOWARN);
2686 if (!page)
2687 return NULL;
2688 }
2689
2690 if (!dma_mask)
2691 dma_mask = *dev->dma_mask;
2692
2693 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2694 size, DMA_BIDIRECTIONAL, dma_mask);
2695
2696 if (*dma_addr == DMA_MAPPING_ERROR)
2697 goto out_free;
2698
2699 return page_address(page);
2700
2701 out_free:
2702
2703 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2704 __free_pages(page, get_order(size));
2705
2706 return NULL;
2707 }
2708
2709 /*
2710 * The exported free_coherent function for dma_ops.
2711 */
2712 static void free_coherent(struct device *dev, size_t size,
2713 void *virt_addr, dma_addr_t dma_addr,
2714 unsigned long attrs)
2715 {
2716 struct protection_domain *domain;
2717 struct dma_ops_domain *dma_dom;
2718 struct page *page;
2719
2720 page = virt_to_page(virt_addr);
2721 size = PAGE_ALIGN(size);
2722
2723 domain = get_domain(dev);
2724 if (IS_ERR(domain))
2725 goto free_mem;
2726
2727 dma_dom = to_dma_ops_domain(domain);
2728
2729 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2730
2731 free_mem:
2732 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2733 __free_pages(page, get_order(size));
2734 }
2735
2736 /*
2737 * This function is called by the DMA layer to find out if we can handle a
2738 * particular device. It is part of the dma_ops.
2739 */
2740 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2741 {
2742 if (!dma_direct_supported(dev, mask))
2743 return 0;
2744 return check_device(dev);
2745 }
2746
2747 static const struct dma_map_ops amd_iommu_dma_ops = {
2748 .alloc = alloc_coherent,
2749 .free = free_coherent,
2750 .map_page = map_page,
2751 .unmap_page = unmap_page,
2752 .map_sg = map_sg,
2753 .unmap_sg = unmap_sg,
2754 .dma_supported = amd_iommu_dma_supported,
2755 };
2756
2757 static int init_reserved_iova_ranges(void)
2758 {
2759 struct pci_dev *pdev = NULL;
2760 struct iova *val;
2761
2762 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2763
2764 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2765 &reserved_rbtree_key);
2766
2767 /* MSI memory range */
2768 val = reserve_iova(&reserved_iova_ranges,
2769 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2770 if (!val) {
2771 pr_err("Reserving MSI range failed\n");
2772 return -ENOMEM;
2773 }
2774
2775 /* HT memory range */
2776 val = reserve_iova(&reserved_iova_ranges,
2777 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2778 if (!val) {
2779 pr_err("Reserving HT range failed\n");
2780 return -ENOMEM;
2781 }
2782
2783 /*
2784 * Memory used for PCI resources
2785 * FIXME: Check whether we can reserve the PCI-hole completly
2786 */
2787 for_each_pci_dev(pdev) {
2788 int i;
2789
2790 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2791 struct resource *r = &pdev->resource[i];
2792
2793 if (!(r->flags & IORESOURCE_MEM))
2794 continue;
2795
2796 val = reserve_iova(&reserved_iova_ranges,
2797 IOVA_PFN(r->start),
2798 IOVA_PFN(r->end));
2799 if (!val) {
2800 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2801 return -ENOMEM;
2802 }
2803 }
2804 }
2805
2806 return 0;
2807 }
2808
2809 int __init amd_iommu_init_api(void)
2810 {
2811 int ret, err = 0;
2812
2813 ret = iova_cache_get();
2814 if (ret)
2815 return ret;
2816
2817 ret = init_reserved_iova_ranges();
2818 if (ret)
2819 return ret;
2820
2821 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2822 if (err)
2823 return err;
2824 #ifdef CONFIG_ARM_AMBA
2825 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2826 if (err)
2827 return err;
2828 #endif
2829 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2830 if (err)
2831 return err;
2832
2833 return 0;
2834 }
2835
2836 int __init amd_iommu_init_dma_ops(void)
2837 {
2838 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2839 iommu_detected = 1;
2840
2841 if (amd_iommu_unmap_flush)
2842 pr_info("IO/TLB flush on unmap enabled\n");
2843 else
2844 pr_info("Lazy IO/TLB flushing enabled\n");
2845
2846 return 0;
2847
2848 }
2849
2850 /*****************************************************************************
2851 *
2852 * The following functions belong to the exported interface of AMD IOMMU
2853 *
2854 * This interface allows access to lower level functions of the IOMMU
2855 * like protection domain handling and assignement of devices to domains
2856 * which is not possible with the dma_ops interface.
2857 *
2858 *****************************************************************************/
2859
2860 static void cleanup_domain(struct protection_domain *domain)
2861 {
2862 struct iommu_dev_data *entry;
2863 unsigned long flags;
2864
2865 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2866
2867 while (!list_empty(&domain->dev_list)) {
2868 entry = list_first_entry(&domain->dev_list,
2869 struct iommu_dev_data, list);
2870 BUG_ON(!entry->domain);
2871 __detach_device(entry);
2872 }
2873
2874 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2875 }
2876
2877 static void protection_domain_free(struct protection_domain *domain)
2878 {
2879 if (!domain)
2880 return;
2881
2882 if (domain->id)
2883 domain_id_free(domain->id);
2884
2885 kfree(domain);
2886 }
2887
2888 static int protection_domain_init(struct protection_domain *domain)
2889 {
2890 spin_lock_init(&domain->lock);
2891 mutex_init(&domain->api_lock);
2892 domain->id = domain_id_alloc();
2893 if (!domain->id)
2894 return -ENOMEM;
2895 INIT_LIST_HEAD(&domain->dev_list);
2896
2897 return 0;
2898 }
2899
2900 static struct protection_domain *protection_domain_alloc(void)
2901 {
2902 struct protection_domain *domain;
2903
2904 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2905 if (!domain)
2906 return NULL;
2907
2908 if (protection_domain_init(domain))
2909 goto out_err;
2910
2911 return domain;
2912
2913 out_err:
2914 kfree(domain);
2915
2916 return NULL;
2917 }
2918
2919 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2920 {
2921 struct protection_domain *pdomain;
2922 struct dma_ops_domain *dma_domain;
2923
2924 switch (type) {
2925 case IOMMU_DOMAIN_UNMANAGED:
2926 pdomain = protection_domain_alloc();
2927 if (!pdomain)
2928 return NULL;
2929
2930 pdomain->mode = PAGE_MODE_3_LEVEL;
2931 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2932 if (!pdomain->pt_root) {
2933 protection_domain_free(pdomain);
2934 return NULL;
2935 }
2936
2937 pdomain->domain.geometry.aperture_start = 0;
2938 pdomain->domain.geometry.aperture_end = ~0ULL;
2939 pdomain->domain.geometry.force_aperture = true;
2940
2941 break;
2942 case IOMMU_DOMAIN_DMA:
2943 dma_domain = dma_ops_domain_alloc();
2944 if (!dma_domain) {
2945 pr_err("Failed to allocate\n");
2946 return NULL;
2947 }
2948 pdomain = &dma_domain->domain;
2949 break;
2950 case IOMMU_DOMAIN_IDENTITY:
2951 pdomain = protection_domain_alloc();
2952 if (!pdomain)
2953 return NULL;
2954
2955 pdomain->mode = PAGE_MODE_NONE;
2956 break;
2957 default:
2958 return NULL;
2959 }
2960
2961 return &pdomain->domain;
2962 }
2963
2964 static void amd_iommu_domain_free(struct iommu_domain *dom)
2965 {
2966 struct protection_domain *domain;
2967 struct dma_ops_domain *dma_dom;
2968
2969 domain = to_pdomain(dom);
2970
2971 if (domain->dev_cnt > 0)
2972 cleanup_domain(domain);
2973
2974 BUG_ON(domain->dev_cnt != 0);
2975
2976 if (!dom)
2977 return;
2978
2979 switch (dom->type) {
2980 case IOMMU_DOMAIN_DMA:
2981 /* Now release the domain */
2982 dma_dom = to_dma_ops_domain(domain);
2983 dma_ops_domain_free(dma_dom);
2984 break;
2985 default:
2986 if (domain->mode != PAGE_MODE_NONE)
2987 free_pagetable(domain);
2988
2989 if (domain->flags & PD_IOMMUV2_MASK)
2990 free_gcr3_table(domain);
2991
2992 protection_domain_free(domain);
2993 break;
2994 }
2995 }
2996
2997 static void amd_iommu_detach_device(struct iommu_domain *dom,
2998 struct device *dev)
2999 {
3000 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3001 struct amd_iommu *iommu;
3002 int devid;
3003
3004 if (!check_device(dev))
3005 return;
3006
3007 devid = get_device_id(dev);
3008 if (devid < 0)
3009 return;
3010
3011 if (dev_data->domain != NULL)
3012 detach_device(dev);
3013
3014 iommu = amd_iommu_rlookup_table[devid];
3015 if (!iommu)
3016 return;
3017
3018 #ifdef CONFIG_IRQ_REMAP
3019 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3020 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3021 dev_data->use_vapic = 0;
3022 #endif
3023
3024 iommu_completion_wait(iommu);
3025 }
3026
3027 static int amd_iommu_attach_device(struct iommu_domain *dom,
3028 struct device *dev)
3029 {
3030 struct protection_domain *domain = to_pdomain(dom);
3031 struct iommu_dev_data *dev_data;
3032 struct amd_iommu *iommu;
3033 int ret;
3034
3035 if (!check_device(dev))
3036 return -EINVAL;
3037
3038 dev_data = dev->archdata.iommu;
3039
3040 iommu = amd_iommu_rlookup_table[dev_data->devid];
3041 if (!iommu)
3042 return -EINVAL;
3043
3044 if (dev_data->domain)
3045 detach_device(dev);
3046
3047 ret = attach_device(dev, domain);
3048
3049 #ifdef CONFIG_IRQ_REMAP
3050 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3051 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3052 dev_data->use_vapic = 1;
3053 else
3054 dev_data->use_vapic = 0;
3055 }
3056 #endif
3057
3058 iommu_completion_wait(iommu);
3059
3060 return ret;
3061 }
3062
3063 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3064 phys_addr_t paddr, size_t page_size, int iommu_prot)
3065 {
3066 struct protection_domain *domain = to_pdomain(dom);
3067 int prot = 0;
3068 int ret;
3069
3070 if (domain->mode == PAGE_MODE_NONE)
3071 return -EINVAL;
3072
3073 if (iommu_prot & IOMMU_READ)
3074 prot |= IOMMU_PROT_IR;
3075 if (iommu_prot & IOMMU_WRITE)
3076 prot |= IOMMU_PROT_IW;
3077
3078 mutex_lock(&domain->api_lock);
3079 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3080 mutex_unlock(&domain->api_lock);
3081
3082 domain_flush_np_cache(domain, iova, page_size);
3083
3084 return ret;
3085 }
3086
3087 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3088 size_t page_size)
3089 {
3090 struct protection_domain *domain = to_pdomain(dom);
3091 size_t unmap_size;
3092
3093 if (domain->mode == PAGE_MODE_NONE)
3094 return 0;
3095
3096 mutex_lock(&domain->api_lock);
3097 unmap_size = iommu_unmap_page(domain, iova, page_size);
3098 mutex_unlock(&domain->api_lock);
3099
3100 return unmap_size;
3101 }
3102
3103 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3104 dma_addr_t iova)
3105 {
3106 struct protection_domain *domain = to_pdomain(dom);
3107 unsigned long offset_mask, pte_pgsize;
3108 u64 *pte, __pte;
3109
3110 if (domain->mode == PAGE_MODE_NONE)
3111 return iova;
3112
3113 pte = fetch_pte(domain, iova, &pte_pgsize);
3114
3115 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3116 return 0;
3117
3118 offset_mask = pte_pgsize - 1;
3119 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3120
3121 return (__pte & ~offset_mask) | (iova & offset_mask);
3122 }
3123
3124 static bool amd_iommu_capable(enum iommu_cap cap)
3125 {
3126 switch (cap) {
3127 case IOMMU_CAP_CACHE_COHERENCY:
3128 return true;
3129 case IOMMU_CAP_INTR_REMAP:
3130 return (irq_remapping_enabled == 1);
3131 case IOMMU_CAP_NOEXEC:
3132 return false;
3133 default:
3134 break;
3135 }
3136
3137 return false;
3138 }
3139
3140 static void amd_iommu_get_resv_regions(struct device *dev,
3141 struct list_head *head)
3142 {
3143 struct iommu_resv_region *region;
3144 struct unity_map_entry *entry;
3145 int devid;
3146
3147 devid = get_device_id(dev);
3148 if (devid < 0)
3149 return;
3150
3151 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3152 int type, prot = 0;
3153 size_t length;
3154
3155 if (devid < entry->devid_start || devid > entry->devid_end)
3156 continue;
3157
3158 type = IOMMU_RESV_DIRECT;
3159 length = entry->address_end - entry->address_start;
3160 if (entry->prot & IOMMU_PROT_IR)
3161 prot |= IOMMU_READ;
3162 if (entry->prot & IOMMU_PROT_IW)
3163 prot |= IOMMU_WRITE;
3164 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3165 /* Exclusion range */
3166 type = IOMMU_RESV_RESERVED;
3167
3168 region = iommu_alloc_resv_region(entry->address_start,
3169 length, prot, type);
3170 if (!region) {
3171 dev_err(dev, "Out of memory allocating dm-regions\n");
3172 return;
3173 }
3174 list_add_tail(&region->list, head);
3175 }
3176
3177 region = iommu_alloc_resv_region(MSI_RANGE_START,
3178 MSI_RANGE_END - MSI_RANGE_START + 1,
3179 0, IOMMU_RESV_MSI);
3180 if (!region)
3181 return;
3182 list_add_tail(&region->list, head);
3183
3184 region = iommu_alloc_resv_region(HT_RANGE_START,
3185 HT_RANGE_END - HT_RANGE_START + 1,
3186 0, IOMMU_RESV_RESERVED);
3187 if (!region)
3188 return;
3189 list_add_tail(&region->list, head);
3190 }
3191
3192 static void amd_iommu_put_resv_regions(struct device *dev,
3193 struct list_head *head)
3194 {
3195 struct iommu_resv_region *entry, *next;
3196
3197 list_for_each_entry_safe(entry, next, head, list)
3198 kfree(entry);
3199 }
3200
3201 static void amd_iommu_apply_resv_region(struct device *dev,
3202 struct iommu_domain *domain,
3203 struct iommu_resv_region *region)
3204 {
3205 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3206 unsigned long start, end;
3207
3208 start = IOVA_PFN(region->start);
3209 end = IOVA_PFN(region->start + region->length - 1);
3210
3211 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3212 }
3213
3214 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3215 struct device *dev)
3216 {
3217 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3218 return dev_data->defer_attach;
3219 }
3220
3221 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3222 {
3223 struct protection_domain *dom = to_pdomain(domain);
3224
3225 domain_flush_tlb_pde(dom);
3226 domain_flush_complete(dom);
3227 }
3228
3229 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3230 unsigned long iova, size_t size)
3231 {
3232 }
3233
3234 const struct iommu_ops amd_iommu_ops = {
3235 .capable = amd_iommu_capable,
3236 .domain_alloc = amd_iommu_domain_alloc,
3237 .domain_free = amd_iommu_domain_free,
3238 .attach_dev = amd_iommu_attach_device,
3239 .detach_dev = amd_iommu_detach_device,
3240 .map = amd_iommu_map,
3241 .unmap = amd_iommu_unmap,
3242 .iova_to_phys = amd_iommu_iova_to_phys,
3243 .add_device = amd_iommu_add_device,
3244 .remove_device = amd_iommu_remove_device,
3245 .device_group = amd_iommu_device_group,
3246 .get_resv_regions = amd_iommu_get_resv_regions,
3247 .put_resv_regions = amd_iommu_put_resv_regions,
3248 .apply_resv_region = amd_iommu_apply_resv_region,
3249 .is_attach_deferred = amd_iommu_is_attach_deferred,
3250 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3251 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3252 .iotlb_range_add = amd_iommu_iotlb_range_add,
3253 .iotlb_sync = amd_iommu_flush_iotlb_all,
3254 };
3255
3256 /*****************************************************************************
3257 *
3258 * The next functions do a basic initialization of IOMMU for pass through
3259 * mode
3260 *
3261 * In passthrough mode the IOMMU is initialized and enabled but not used for
3262 * DMA-API translation.
3263 *
3264 *****************************************************************************/
3265
3266 /* IOMMUv2 specific functions */
3267 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3268 {
3269 return atomic_notifier_chain_register(&ppr_notifier, nb);
3270 }
3271 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3272
3273 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3274 {
3275 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3276 }
3277 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3278
3279 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3280 {
3281 struct protection_domain *domain = to_pdomain(dom);
3282 unsigned long flags;
3283
3284 spin_lock_irqsave(&domain->lock, flags);
3285
3286 /* Update data structure */
3287 domain->mode = PAGE_MODE_NONE;
3288 domain->updated = true;
3289
3290 /* Make changes visible to IOMMUs */
3291 update_domain(domain);
3292
3293 /* Page-table is not visible to IOMMU anymore, so free it */
3294 free_pagetable(domain);
3295
3296 spin_unlock_irqrestore(&domain->lock, flags);
3297 }
3298 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3299
3300 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3301 {
3302 struct protection_domain *domain = to_pdomain(dom);
3303 unsigned long flags;
3304 int levels, ret;
3305
3306 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3307 return -EINVAL;
3308
3309 /* Number of GCR3 table levels required */
3310 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3311 levels += 1;
3312
3313 if (levels > amd_iommu_max_glx_val)
3314 return -EINVAL;
3315
3316 spin_lock_irqsave(&domain->lock, flags);
3317
3318 /*
3319 * Save us all sanity checks whether devices already in the
3320 * domain support IOMMUv2. Just force that the domain has no
3321 * devices attached when it is switched into IOMMUv2 mode.
3322 */
3323 ret = -EBUSY;
3324 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3325 goto out;
3326
3327 ret = -ENOMEM;
3328 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3329 if (domain->gcr3_tbl == NULL)
3330 goto out;
3331
3332 domain->glx = levels;
3333 domain->flags |= PD_IOMMUV2_MASK;
3334 domain->updated = true;
3335
3336 update_domain(domain);
3337
3338 ret = 0;
3339
3340 out:
3341 spin_unlock_irqrestore(&domain->lock, flags);
3342
3343 return ret;
3344 }
3345 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3346
3347 static int __flush_pasid(struct protection_domain *domain, int pasid,
3348 u64 address, bool size)
3349 {
3350 struct iommu_dev_data *dev_data;
3351 struct iommu_cmd cmd;
3352 int i, ret;
3353
3354 if (!(domain->flags & PD_IOMMUV2_MASK))
3355 return -EINVAL;
3356
3357 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3358
3359 /*
3360 * IOMMU TLB needs to be flushed before Device TLB to
3361 * prevent device TLB refill from IOMMU TLB
3362 */
3363 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3364 if (domain->dev_iommu[i] == 0)
3365 continue;
3366
3367 ret = iommu_queue_command(amd_iommus[i], &cmd);
3368 if (ret != 0)
3369 goto out;
3370 }
3371
3372 /* Wait until IOMMU TLB flushes are complete */
3373 domain_flush_complete(domain);
3374
3375 /* Now flush device TLBs */
3376 list_for_each_entry(dev_data, &domain->dev_list, list) {
3377 struct amd_iommu *iommu;
3378 int qdep;
3379
3380 /*
3381 There might be non-IOMMUv2 capable devices in an IOMMUv2
3382 * domain.
3383 */
3384 if (!dev_data->ats.enabled)
3385 continue;
3386
3387 qdep = dev_data->ats.qdep;
3388 iommu = amd_iommu_rlookup_table[dev_data->devid];
3389
3390 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3391 qdep, address, size);
3392
3393 ret = iommu_queue_command(iommu, &cmd);
3394 if (ret != 0)
3395 goto out;
3396 }
3397
3398 /* Wait until all device TLBs are flushed */
3399 domain_flush_complete(domain);
3400
3401 ret = 0;
3402
3403 out:
3404
3405 return ret;
3406 }
3407
3408 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3409 u64 address)
3410 {
3411 return __flush_pasid(domain, pasid, address, false);
3412 }
3413
3414 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3415 u64 address)
3416 {
3417 struct protection_domain *domain = to_pdomain(dom);
3418 unsigned long flags;
3419 int ret;
3420
3421 spin_lock_irqsave(&domain->lock, flags);
3422 ret = __amd_iommu_flush_page(domain, pasid, address);
3423 spin_unlock_irqrestore(&domain->lock, flags);
3424
3425 return ret;
3426 }
3427 EXPORT_SYMBOL(amd_iommu_flush_page);
3428
3429 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3430 {
3431 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3432 true);
3433 }
3434
3435 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3436 {
3437 struct protection_domain *domain = to_pdomain(dom);
3438 unsigned long flags;
3439 int ret;
3440
3441 spin_lock_irqsave(&domain->lock, flags);
3442 ret = __amd_iommu_flush_tlb(domain, pasid);
3443 spin_unlock_irqrestore(&domain->lock, flags);
3444
3445 return ret;
3446 }
3447 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3448
3449 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3450 {
3451 int index;
3452 u64 *pte;
3453
3454 while (true) {
3455
3456 index = (pasid >> (9 * level)) & 0x1ff;
3457 pte = &root[index];
3458
3459 if (level == 0)
3460 break;
3461
3462 if (!(*pte & GCR3_VALID)) {
3463 if (!alloc)
3464 return NULL;
3465
3466 root = (void *)get_zeroed_page(GFP_ATOMIC);
3467 if (root == NULL)
3468 return NULL;
3469
3470 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3471 }
3472
3473 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3474
3475 level -= 1;
3476 }
3477
3478 return pte;
3479 }
3480
3481 static int __set_gcr3(struct protection_domain *domain, int pasid,
3482 unsigned long cr3)
3483 {
3484 u64 *pte;
3485
3486 if (domain->mode != PAGE_MODE_NONE)
3487 return -EINVAL;
3488
3489 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3490 if (pte == NULL)
3491 return -ENOMEM;
3492
3493 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3494
3495 return __amd_iommu_flush_tlb(domain, pasid);
3496 }
3497
3498 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3499 {
3500 u64 *pte;
3501
3502 if (domain->mode != PAGE_MODE_NONE)
3503 return -EINVAL;
3504
3505 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3506 if (pte == NULL)
3507 return 0;
3508
3509 *pte = 0;
3510
3511 return __amd_iommu_flush_tlb(domain, pasid);
3512 }
3513
3514 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3515 unsigned long cr3)
3516 {
3517 struct protection_domain *domain = to_pdomain(dom);
3518 unsigned long flags;
3519 int ret;
3520
3521 spin_lock_irqsave(&domain->lock, flags);
3522 ret = __set_gcr3(domain, pasid, cr3);
3523 spin_unlock_irqrestore(&domain->lock, flags);
3524
3525 return ret;
3526 }
3527 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3528
3529 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3530 {
3531 struct protection_domain *domain = to_pdomain(dom);
3532 unsigned long flags;
3533 int ret;
3534
3535 spin_lock_irqsave(&domain->lock, flags);
3536 ret = __clear_gcr3(domain, pasid);
3537 spin_unlock_irqrestore(&domain->lock, flags);
3538
3539 return ret;
3540 }
3541 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3542
3543 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3544 int status, int tag)
3545 {
3546 struct iommu_dev_data *dev_data;
3547 struct amd_iommu *iommu;
3548 struct iommu_cmd cmd;
3549
3550 dev_data = get_dev_data(&pdev->dev);
3551 iommu = amd_iommu_rlookup_table[dev_data->devid];
3552
3553 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3554 tag, dev_data->pri_tlp);
3555
3556 return iommu_queue_command(iommu, &cmd);
3557 }
3558 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3559
3560 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3561 {
3562 struct protection_domain *pdomain;
3563
3564 pdomain = get_domain(&pdev->dev);
3565 if (IS_ERR(pdomain))
3566 return NULL;
3567
3568 /* Only return IOMMUv2 domains */
3569 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3570 return NULL;
3571
3572 return &pdomain->domain;
3573 }
3574 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3575
3576 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3577 {
3578 struct iommu_dev_data *dev_data;
3579
3580 if (!amd_iommu_v2_supported())
3581 return;
3582
3583 dev_data = get_dev_data(&pdev->dev);
3584 dev_data->errata |= (1 << erratum);
3585 }
3586 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3587
3588 int amd_iommu_device_info(struct pci_dev *pdev,
3589 struct amd_iommu_device_info *info)
3590 {
3591 int max_pasids;
3592 int pos;
3593
3594 if (pdev == NULL || info == NULL)
3595 return -EINVAL;
3596
3597 if (!amd_iommu_v2_supported())
3598 return -EINVAL;
3599
3600 memset(info, 0, sizeof(*info));
3601
3602 if (!pci_ats_disabled()) {
3603 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3604 if (pos)
3605 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3606 }
3607
3608 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3609 if (pos)
3610 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3611
3612 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3613 if (pos) {
3614 int features;
3615
3616 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3617 max_pasids = min(max_pasids, (1 << 20));
3618
3619 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3620 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3621
3622 features = pci_pasid_features(pdev);
3623 if (features & PCI_PASID_CAP_EXEC)
3624 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3625 if (features & PCI_PASID_CAP_PRIV)
3626 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3627 }
3628
3629 return 0;
3630 }
3631 EXPORT_SYMBOL(amd_iommu_device_info);
3632
3633 #ifdef CONFIG_IRQ_REMAP
3634
3635 /*****************************************************************************
3636 *
3637 * Interrupt Remapping Implementation
3638 *
3639 *****************************************************************************/
3640
3641 static struct irq_chip amd_ir_chip;
3642 static DEFINE_SPINLOCK(iommu_table_lock);
3643
3644 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3645 {
3646 u64 dte;
3647
3648 dte = amd_iommu_dev_table[devid].data[2];
3649 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3650 dte |= iommu_virt_to_phys(table->table);
3651 dte |= DTE_IRQ_REMAP_INTCTL;
3652 dte |= DTE_IRQ_TABLE_LEN;
3653 dte |= DTE_IRQ_REMAP_ENABLE;
3654
3655 amd_iommu_dev_table[devid].data[2] = dte;
3656 }
3657
3658 static struct irq_remap_table *get_irq_table(u16 devid)
3659 {
3660 struct irq_remap_table *table;
3661
3662 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3663 "%s: no iommu for devid %x\n", __func__, devid))
3664 return NULL;
3665
3666 table = irq_lookup_table[devid];
3667 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3668 return NULL;
3669
3670 return table;
3671 }
3672
3673 static struct irq_remap_table *__alloc_irq_table(void)
3674 {
3675 struct irq_remap_table *table;
3676
3677 table = kzalloc(sizeof(*table), GFP_KERNEL);
3678 if (!table)
3679 return NULL;
3680
3681 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3682 if (!table->table) {
3683 kfree(table);
3684 return NULL;
3685 }
3686 raw_spin_lock_init(&table->lock);
3687
3688 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3689 memset(table->table, 0,
3690 MAX_IRQS_PER_TABLE * sizeof(u32));
3691 else
3692 memset(table->table, 0,
3693 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3694 return table;
3695 }
3696
3697 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3698 struct irq_remap_table *table)
3699 {
3700 irq_lookup_table[devid] = table;
3701 set_dte_irq_entry(devid, table);
3702 iommu_flush_dte(iommu, devid);
3703 }
3704
3705 static struct irq_remap_table *alloc_irq_table(u16 devid)
3706 {
3707 struct irq_remap_table *table = NULL;
3708 struct irq_remap_table *new_table = NULL;
3709 struct amd_iommu *iommu;
3710 unsigned long flags;
3711 u16 alias;
3712
3713 spin_lock_irqsave(&iommu_table_lock, flags);
3714
3715 iommu = amd_iommu_rlookup_table[devid];
3716 if (!iommu)
3717 goto out_unlock;
3718
3719 table = irq_lookup_table[devid];
3720 if (table)
3721 goto out_unlock;
3722
3723 alias = amd_iommu_alias_table[devid];
3724 table = irq_lookup_table[alias];
3725 if (table) {
3726 set_remap_table_entry(iommu, devid, table);
3727 goto out_wait;
3728 }
3729 spin_unlock_irqrestore(&iommu_table_lock, flags);
3730
3731 /* Nothing there yet, allocate new irq remapping table */
3732 new_table = __alloc_irq_table();
3733 if (!new_table)
3734 return NULL;
3735
3736 spin_lock_irqsave(&iommu_table_lock, flags);
3737
3738 table = irq_lookup_table[devid];
3739 if (table)
3740 goto out_unlock;
3741
3742 table = irq_lookup_table[alias];
3743 if (table) {
3744 set_remap_table_entry(iommu, devid, table);
3745 goto out_wait;
3746 }
3747
3748 table = new_table;
3749 new_table = NULL;
3750
3751 set_remap_table_entry(iommu, devid, table);
3752 if (devid != alias)
3753 set_remap_table_entry(iommu, alias, table);
3754
3755 out_wait:
3756 iommu_completion_wait(iommu);
3757
3758 out_unlock:
3759 spin_unlock_irqrestore(&iommu_table_lock, flags);
3760
3761 if (new_table) {
3762 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3763 kfree(new_table);
3764 }
3765 return table;
3766 }
3767
3768 static int alloc_irq_index(u16 devid, int count, bool align)
3769 {
3770 struct irq_remap_table *table;
3771 int index, c, alignment = 1;
3772 unsigned long flags;
3773 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3774
3775 if (!iommu)
3776 return -ENODEV;
3777
3778 table = alloc_irq_table(devid);
3779 if (!table)
3780 return -ENODEV;
3781
3782 if (align)
3783 alignment = roundup_pow_of_two(count);
3784
3785 raw_spin_lock_irqsave(&table->lock, flags);
3786
3787 /* Scan table for free entries */
3788 for (index = ALIGN(table->min_index, alignment), c = 0;
3789 index < MAX_IRQS_PER_TABLE;) {
3790 if (!iommu->irte_ops->is_allocated(table, index)) {
3791 c += 1;
3792 } else {
3793 c = 0;
3794 index = ALIGN(index + 1, alignment);
3795 continue;
3796 }
3797
3798 if (c == count) {
3799 for (; c != 0; --c)
3800 iommu->irte_ops->set_allocated(table, index - c + 1);
3801
3802 index -= count - 1;
3803 goto out;
3804 }
3805
3806 index++;
3807 }
3808
3809 index = -ENOSPC;
3810
3811 out:
3812 raw_spin_unlock_irqrestore(&table->lock, flags);
3813
3814 return index;
3815 }
3816
3817 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3818 struct amd_ir_data *data)
3819 {
3820 struct irq_remap_table *table;
3821 struct amd_iommu *iommu;
3822 unsigned long flags;
3823 struct irte_ga *entry;
3824
3825 iommu = amd_iommu_rlookup_table[devid];
3826 if (iommu == NULL)
3827 return -EINVAL;
3828
3829 table = get_irq_table(devid);
3830 if (!table)
3831 return -ENOMEM;
3832
3833 raw_spin_lock_irqsave(&table->lock, flags);
3834
3835 entry = (struct irte_ga *)table->table;
3836 entry = &entry[index];
3837 entry->lo.fields_remap.valid = 0;
3838 entry->hi.val = irte->hi.val;
3839 entry->lo.val = irte->lo.val;
3840 entry->lo.fields_remap.valid = 1;
3841 if (data)
3842 data->ref = entry;
3843
3844 raw_spin_unlock_irqrestore(&table->lock, flags);
3845
3846 iommu_flush_irt(iommu, devid);
3847 iommu_completion_wait(iommu);
3848
3849 return 0;
3850 }
3851
3852 static int modify_irte(u16 devid, int index, union irte *irte)
3853 {
3854 struct irq_remap_table *table;
3855 struct amd_iommu *iommu;
3856 unsigned long flags;
3857
3858 iommu = amd_iommu_rlookup_table[devid];
3859 if (iommu == NULL)
3860 return -EINVAL;
3861
3862 table = get_irq_table(devid);
3863 if (!table)
3864 return -ENOMEM;
3865
3866 raw_spin_lock_irqsave(&table->lock, flags);
3867 table->table[index] = irte->val;
3868 raw_spin_unlock_irqrestore(&table->lock, flags);
3869
3870 iommu_flush_irt(iommu, devid);
3871 iommu_completion_wait(iommu);
3872
3873 return 0;
3874 }
3875
3876 static void free_irte(u16 devid, int index)
3877 {
3878 struct irq_remap_table *table;
3879 struct amd_iommu *iommu;
3880 unsigned long flags;
3881
3882 iommu = amd_iommu_rlookup_table[devid];
3883 if (iommu == NULL)
3884 return;
3885
3886 table = get_irq_table(devid);
3887 if (!table)
3888 return;
3889
3890 raw_spin_lock_irqsave(&table->lock, flags);
3891 iommu->irte_ops->clear_allocated(table, index);
3892 raw_spin_unlock_irqrestore(&table->lock, flags);
3893
3894 iommu_flush_irt(iommu, devid);
3895 iommu_completion_wait(iommu);
3896 }
3897
3898 static void irte_prepare(void *entry,
3899 u32 delivery_mode, u32 dest_mode,
3900 u8 vector, u32 dest_apicid, int devid)
3901 {
3902 union irte *irte = (union irte *) entry;
3903
3904 irte->val = 0;
3905 irte->fields.vector = vector;
3906 irte->fields.int_type = delivery_mode;
3907 irte->fields.destination = dest_apicid;
3908 irte->fields.dm = dest_mode;
3909 irte->fields.valid = 1;
3910 }
3911
3912 static void irte_ga_prepare(void *entry,
3913 u32 delivery_mode, u32 dest_mode,
3914 u8 vector, u32 dest_apicid, int devid)
3915 {
3916 struct irte_ga *irte = (struct irte_ga *) entry;
3917
3918 irte->lo.val = 0;
3919 irte->hi.val = 0;
3920 irte->lo.fields_remap.int_type = delivery_mode;
3921 irte->lo.fields_remap.dm = dest_mode;
3922 irte->hi.fields.vector = vector;
3923 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3924 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3925 irte->lo.fields_remap.valid = 1;
3926 }
3927
3928 static void irte_activate(void *entry, u16 devid, u16 index)
3929 {
3930 union irte *irte = (union irte *) entry;
3931
3932 irte->fields.valid = 1;
3933 modify_irte(devid, index, irte);
3934 }
3935
3936 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3937 {
3938 struct irte_ga *irte = (struct irte_ga *) entry;
3939
3940 irte->lo.fields_remap.valid = 1;
3941 modify_irte_ga(devid, index, irte, NULL);
3942 }
3943
3944 static void irte_deactivate(void *entry, u16 devid, u16 index)
3945 {
3946 union irte *irte = (union irte *) entry;
3947
3948 irte->fields.valid = 0;
3949 modify_irte(devid, index, irte);
3950 }
3951
3952 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3953 {
3954 struct irte_ga *irte = (struct irte_ga *) entry;
3955
3956 irte->lo.fields_remap.valid = 0;
3957 modify_irte_ga(devid, index, irte, NULL);
3958 }
3959
3960 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3961 u8 vector, u32 dest_apicid)
3962 {
3963 union irte *irte = (union irte *) entry;
3964
3965 irte->fields.vector = vector;
3966 irte->fields.destination = dest_apicid;
3967 modify_irte(devid, index, irte);
3968 }
3969
3970 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3971 u8 vector, u32 dest_apicid)
3972 {
3973 struct irte_ga *irte = (struct irte_ga *) entry;
3974
3975 if (!irte->lo.fields_remap.guest_mode) {
3976 irte->hi.fields.vector = vector;
3977 irte->lo.fields_remap.destination =
3978 APICID_TO_IRTE_DEST_LO(dest_apicid);
3979 irte->hi.fields.destination =
3980 APICID_TO_IRTE_DEST_HI(dest_apicid);
3981 modify_irte_ga(devid, index, irte, NULL);
3982 }
3983 }
3984
3985 #define IRTE_ALLOCATED (~1U)
3986 static void irte_set_allocated(struct irq_remap_table *table, int index)
3987 {
3988 table->table[index] = IRTE_ALLOCATED;
3989 }
3990
3991 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3992 {
3993 struct irte_ga *ptr = (struct irte_ga *)table->table;
3994 struct irte_ga *irte = &ptr[index];
3995
3996 memset(&irte->lo.val, 0, sizeof(u64));
3997 memset(&irte->hi.val, 0, sizeof(u64));
3998 irte->hi.fields.vector = 0xff;
3999 }
4000
4001 static bool irte_is_allocated(struct irq_remap_table *table, int index)
4002 {
4003 union irte *ptr = (union irte *)table->table;
4004 union irte *irte = &ptr[index];
4005
4006 return irte->val != 0;
4007 }
4008
4009 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
4010 {
4011 struct irte_ga *ptr = (struct irte_ga *)table->table;
4012 struct irte_ga *irte = &ptr[index];
4013
4014 return irte->hi.fields.vector != 0;
4015 }
4016
4017 static void irte_clear_allocated(struct irq_remap_table *table, int index)
4018 {
4019 table->table[index] = 0;
4020 }
4021
4022 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
4023 {
4024 struct irte_ga *ptr = (struct irte_ga *)table->table;
4025 struct irte_ga *irte = &ptr[index];
4026
4027 memset(&irte->lo.val, 0, sizeof(u64));
4028 memset(&irte->hi.val, 0, sizeof(u64));
4029 }
4030
4031 static int get_devid(struct irq_alloc_info *info)
4032 {
4033 int devid = -1;
4034
4035 switch (info->type) {
4036 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4037 devid = get_ioapic_devid(info->ioapic_id);
4038 break;
4039 case X86_IRQ_ALLOC_TYPE_HPET:
4040 devid = get_hpet_devid(info->hpet_id);
4041 break;
4042 case X86_IRQ_ALLOC_TYPE_MSI:
4043 case X86_IRQ_ALLOC_TYPE_MSIX:
4044 devid = get_device_id(&info->msi_dev->dev);
4045 break;
4046 default:
4047 BUG_ON(1);
4048 break;
4049 }
4050
4051 return devid;
4052 }
4053
4054 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4055 {
4056 struct amd_iommu *iommu;
4057 int devid;
4058
4059 if (!info)
4060 return NULL;
4061
4062 devid = get_devid(info);
4063 if (devid >= 0) {
4064 iommu = amd_iommu_rlookup_table[devid];
4065 if (iommu)
4066 return iommu->ir_domain;
4067 }
4068
4069 return NULL;
4070 }
4071
4072 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4073 {
4074 struct amd_iommu *iommu;
4075 int devid;
4076
4077 if (!info)
4078 return NULL;
4079
4080 switch (info->type) {
4081 case X86_IRQ_ALLOC_TYPE_MSI:
4082 case X86_IRQ_ALLOC_TYPE_MSIX:
4083 devid = get_device_id(&info->msi_dev->dev);
4084 if (devid < 0)
4085 return NULL;
4086
4087 iommu = amd_iommu_rlookup_table[devid];
4088 if (iommu)
4089 return iommu->msi_domain;
4090 break;
4091 default:
4092 break;
4093 }
4094
4095 return NULL;
4096 }
4097
4098 struct irq_remap_ops amd_iommu_irq_ops = {
4099 .prepare = amd_iommu_prepare,
4100 .enable = amd_iommu_enable,
4101 .disable = amd_iommu_disable,
4102 .reenable = amd_iommu_reenable,
4103 .enable_faulting = amd_iommu_enable_faulting,
4104 .get_ir_irq_domain = get_ir_irq_domain,
4105 .get_irq_domain = get_irq_domain,
4106 };
4107
4108 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4109 struct irq_cfg *irq_cfg,
4110 struct irq_alloc_info *info,
4111 int devid, int index, int sub_handle)
4112 {
4113 struct irq_2_irte *irte_info = &data->irq_2_irte;
4114 struct msi_msg *msg = &data->msi_entry;
4115 struct IO_APIC_route_entry *entry;
4116 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4117
4118 if (!iommu)
4119 return;
4120
4121 data->irq_2_irte.devid = devid;
4122 data->irq_2_irte.index = index + sub_handle;
4123 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4124 apic->irq_dest_mode, irq_cfg->vector,
4125 irq_cfg->dest_apicid, devid);
4126
4127 switch (info->type) {
4128 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4129 /* Setup IOAPIC entry */
4130 entry = info->ioapic_entry;
4131 info->ioapic_entry = NULL;
4132 memset(entry, 0, sizeof(*entry));
4133 entry->vector = index;
4134 entry->mask = 0;
4135 entry->trigger = info->ioapic_trigger;
4136 entry->polarity = info->ioapic_polarity;
4137 /* Mask level triggered irqs. */
4138 if (info->ioapic_trigger)
4139 entry->mask = 1;
4140 break;
4141
4142 case X86_IRQ_ALLOC_TYPE_HPET:
4143 case X86_IRQ_ALLOC_TYPE_MSI:
4144 case X86_IRQ_ALLOC_TYPE_MSIX:
4145 msg->address_hi = MSI_ADDR_BASE_HI;
4146 msg->address_lo = MSI_ADDR_BASE_LO;
4147 msg->data = irte_info->index;
4148 break;
4149
4150 default:
4151 BUG_ON(1);
4152 break;
4153 }
4154 }
4155
4156 struct amd_irte_ops irte_32_ops = {
4157 .prepare = irte_prepare,
4158 .activate = irte_activate,
4159 .deactivate = irte_deactivate,
4160 .set_affinity = irte_set_affinity,
4161 .set_allocated = irte_set_allocated,
4162 .is_allocated = irte_is_allocated,
4163 .clear_allocated = irte_clear_allocated,
4164 };
4165
4166 struct amd_irte_ops irte_128_ops = {
4167 .prepare = irte_ga_prepare,
4168 .activate = irte_ga_activate,
4169 .deactivate = irte_ga_deactivate,
4170 .set_affinity = irte_ga_set_affinity,
4171 .set_allocated = irte_ga_set_allocated,
4172 .is_allocated = irte_ga_is_allocated,
4173 .clear_allocated = irte_ga_clear_allocated,
4174 };
4175
4176 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4177 unsigned int nr_irqs, void *arg)
4178 {
4179 struct irq_alloc_info *info = arg;
4180 struct irq_data *irq_data;
4181 struct amd_ir_data *data = NULL;
4182 struct irq_cfg *cfg;
4183 int i, ret, devid;
4184 int index;
4185
4186 if (!info)
4187 return -EINVAL;
4188 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4189 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4190 return -EINVAL;
4191
4192 /*
4193 * With IRQ remapping enabled, don't need contiguous CPU vectors
4194 * to support multiple MSI interrupts.
4195 */
4196 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4197 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4198
4199 devid = get_devid(info);
4200 if (devid < 0)
4201 return -EINVAL;
4202
4203 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4204 if (ret < 0)
4205 return ret;
4206
4207 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4208 struct irq_remap_table *table;
4209 struct amd_iommu *iommu;
4210
4211 table = alloc_irq_table(devid);
4212 if (table) {
4213 if (!table->min_index) {
4214 /*
4215 * Keep the first 32 indexes free for IOAPIC
4216 * interrupts.
4217 */
4218 table->min_index = 32;
4219 iommu = amd_iommu_rlookup_table[devid];
4220 for (i = 0; i < 32; ++i)
4221 iommu->irte_ops->set_allocated(table, i);
4222 }
4223 WARN_ON(table->min_index != 32);
4224 index = info->ioapic_pin;
4225 } else {
4226 index = -ENOMEM;
4227 }
4228 } else {
4229 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4230
4231 index = alloc_irq_index(devid, nr_irqs, align);
4232 }
4233 if (index < 0) {
4234 pr_warn("Failed to allocate IRTE\n");
4235 ret = index;
4236 goto out_free_parent;
4237 }
4238
4239 for (i = 0; i < nr_irqs; i++) {
4240 irq_data = irq_domain_get_irq_data(domain, virq + i);
4241 cfg = irqd_cfg(irq_data);
4242 if (!irq_data || !cfg) {
4243 ret = -EINVAL;
4244 goto out_free_data;
4245 }
4246
4247 ret = -ENOMEM;
4248 data = kzalloc(sizeof(*data), GFP_KERNEL);
4249 if (!data)
4250 goto out_free_data;
4251
4252 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4253 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4254 else
4255 data->entry = kzalloc(sizeof(struct irte_ga),
4256 GFP_KERNEL);
4257 if (!data->entry) {
4258 kfree(data);
4259 goto out_free_data;
4260 }
4261
4262 irq_data->hwirq = (devid << 16) + i;
4263 irq_data->chip_data = data;
4264 irq_data->chip = &amd_ir_chip;
4265 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4266 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4267 }
4268
4269 return 0;
4270
4271 out_free_data:
4272 for (i--; i >= 0; i--) {
4273 irq_data = irq_domain_get_irq_data(domain, virq + i);
4274 if (irq_data)
4275 kfree(irq_data->chip_data);
4276 }
4277 for (i = 0; i < nr_irqs; i++)
4278 free_irte(devid, index + i);
4279 out_free_parent:
4280 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4281 return ret;
4282 }
4283
4284 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4285 unsigned int nr_irqs)
4286 {
4287 struct irq_2_irte *irte_info;
4288 struct irq_data *irq_data;
4289 struct amd_ir_data *data;
4290 int i;
4291
4292 for (i = 0; i < nr_irqs; i++) {
4293 irq_data = irq_domain_get_irq_data(domain, virq + i);
4294 if (irq_data && irq_data->chip_data) {
4295 data = irq_data->chip_data;
4296 irte_info = &data->irq_2_irte;
4297 free_irte(irte_info->devid, irte_info->index);
4298 kfree(data->entry);
4299 kfree(data);
4300 }
4301 }
4302 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4303 }
4304
4305 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4306 struct amd_ir_data *ir_data,
4307 struct irq_2_irte *irte_info,
4308 struct irq_cfg *cfg);
4309
4310 static int irq_remapping_activate(struct irq_domain *domain,
4311 struct irq_data *irq_data, bool reserve)
4312 {
4313 struct amd_ir_data *data = irq_data->chip_data;
4314 struct irq_2_irte *irte_info = &data->irq_2_irte;
4315 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4316 struct irq_cfg *cfg = irqd_cfg(irq_data);
4317
4318 if (!iommu)
4319 return 0;
4320
4321 iommu->irte_ops->activate(data->entry, irte_info->devid,
4322 irte_info->index);
4323 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4324 return 0;
4325 }
4326
4327 static void irq_remapping_deactivate(struct irq_domain *domain,
4328 struct irq_data *irq_data)
4329 {
4330 struct amd_ir_data *data = irq_data->chip_data;
4331 struct irq_2_irte *irte_info = &data->irq_2_irte;
4332 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4333
4334 if (iommu)
4335 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4336 irte_info->index);
4337 }
4338
4339 static const struct irq_domain_ops amd_ir_domain_ops = {
4340 .alloc = irq_remapping_alloc,
4341 .free = irq_remapping_free,
4342 .activate = irq_remapping_activate,
4343 .deactivate = irq_remapping_deactivate,
4344 };
4345
4346 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4347 {
4348 struct amd_iommu *iommu;
4349 struct amd_iommu_pi_data *pi_data = vcpu_info;
4350 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4351 struct amd_ir_data *ir_data = data->chip_data;
4352 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4353 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4354 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4355
4356 /* Note:
4357 * This device has never been set up for guest mode.
4358 * we should not modify the IRTE
4359 */
4360 if (!dev_data || !dev_data->use_vapic)
4361 return 0;
4362
4363 pi_data->ir_data = ir_data;
4364
4365 /* Note:
4366 * SVM tries to set up for VAPIC mode, but we are in
4367 * legacy mode. So, we force legacy mode instead.
4368 */
4369 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4370 pr_debug("%s: Fall back to using intr legacy remap\n",
4371 __func__);
4372 pi_data->is_guest_mode = false;
4373 }
4374
4375 iommu = amd_iommu_rlookup_table[irte_info->devid];
4376 if (iommu == NULL)
4377 return -EINVAL;
4378
4379 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4380 if (pi_data->is_guest_mode) {
4381 /* Setting */
4382 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4383 irte->hi.fields.vector = vcpu_pi_info->vector;
4384 irte->lo.fields_vapic.ga_log_intr = 1;
4385 irte->lo.fields_vapic.guest_mode = 1;
4386 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4387
4388 ir_data->cached_ga_tag = pi_data->ga_tag;
4389 } else {
4390 /* Un-Setting */
4391 struct irq_cfg *cfg = irqd_cfg(data);
4392
4393 irte->hi.val = 0;
4394 irte->lo.val = 0;
4395 irte->hi.fields.vector = cfg->vector;
4396 irte->lo.fields_remap.guest_mode = 0;
4397 irte->lo.fields_remap.destination =
4398 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4399 irte->hi.fields.destination =
4400 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4401 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4402 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4403
4404 /*
4405 * This communicates the ga_tag back to the caller
4406 * so that it can do all the necessary clean up.
4407 */
4408 ir_data->cached_ga_tag = 0;
4409 }
4410
4411 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4412 }
4413
4414
4415 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4416 struct amd_ir_data *ir_data,
4417 struct irq_2_irte *irte_info,
4418 struct irq_cfg *cfg)
4419 {
4420
4421 /*
4422 * Atomically updates the IRTE with the new destination, vector
4423 * and flushes the interrupt entry cache.
4424 */
4425 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4426 irte_info->index, cfg->vector,
4427 cfg->dest_apicid);
4428 }
4429
4430 static int amd_ir_set_affinity(struct irq_data *data,
4431 const struct cpumask *mask, bool force)
4432 {
4433 struct amd_ir_data *ir_data = data->chip_data;
4434 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4435 struct irq_cfg *cfg = irqd_cfg(data);
4436 struct irq_data *parent = data->parent_data;
4437 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4438 int ret;
4439
4440 if (!iommu)
4441 return -ENODEV;
4442
4443 ret = parent->chip->irq_set_affinity(parent, mask, force);
4444 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4445 return ret;
4446
4447 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4448 /*
4449 * After this point, all the interrupts will start arriving
4450 * at the new destination. So, time to cleanup the previous
4451 * vector allocation.
4452 */
4453 send_cleanup_vector(cfg);
4454
4455 return IRQ_SET_MASK_OK_DONE;
4456 }
4457
4458 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4459 {
4460 struct amd_ir_data *ir_data = irq_data->chip_data;
4461
4462 *msg = ir_data->msi_entry;
4463 }
4464
4465 static struct irq_chip amd_ir_chip = {
4466 .name = "AMD-IR",
4467 .irq_ack = apic_ack_irq,
4468 .irq_set_affinity = amd_ir_set_affinity,
4469 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4470 .irq_compose_msi_msg = ir_compose_msi_msg,
4471 };
4472
4473 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4474 {
4475 struct fwnode_handle *fn;
4476
4477 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4478 if (!fn)
4479 return -ENOMEM;
4480 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4481 irq_domain_free_fwnode(fn);
4482 if (!iommu->ir_domain)
4483 return -ENOMEM;
4484
4485 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4486 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4487 "AMD-IR-MSI",
4488 iommu->index);
4489 return 0;
4490 }
4491
4492 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4493 {
4494 unsigned long flags;
4495 struct amd_iommu *iommu;
4496 struct irq_remap_table *table;
4497 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4498 int devid = ir_data->irq_2_irte.devid;
4499 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4500 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4501
4502 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4503 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4504 return 0;
4505
4506 iommu = amd_iommu_rlookup_table[devid];
4507 if (!iommu)
4508 return -ENODEV;
4509
4510 table = get_irq_table(devid);
4511 if (!table)
4512 return -ENODEV;
4513
4514 raw_spin_lock_irqsave(&table->lock, flags);
4515
4516 if (ref->lo.fields_vapic.guest_mode) {
4517 if (cpu >= 0) {
4518 ref->lo.fields_vapic.destination =
4519 APICID_TO_IRTE_DEST_LO(cpu);
4520 ref->hi.fields.destination =
4521 APICID_TO_IRTE_DEST_HI(cpu);
4522 }
4523 ref->lo.fields_vapic.is_run = is_run;
4524 barrier();
4525 }
4526
4527 raw_spin_unlock_irqrestore(&table->lock, flags);
4528
4529 iommu_flush_irt(iommu, devid);
4530 iommu_completion_wait(iommu);
4531 return 0;
4532 }
4533 EXPORT_SYMBOL(amd_iommu_update_ga);
4534 #endif
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