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Merge tag 'platform-drivers-x86-v4.1-1' of git://git.infradead.org/users/dvhart/linux...
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
39 #include <asm/apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
44 #include <asm/gart.h>
45 #include <asm/dma.h>
46
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static const struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * This struct contains device specific data for the IOMMU
93 */
94 struct iommu_dev_data {
95 struct list_head list; /* For domain->dev_list */
96 struct list_head dev_data_list; /* For global dev_data_list */
97 struct list_head alias_list; /* Link alias-groups together */
98 struct iommu_dev_data *alias_data;/* The alias dev_data */
99 struct protection_domain *domain; /* Domain the device is bound to */
100 u16 devid; /* PCI Device ID */
101 bool iommu_v2; /* Device can make use of IOMMUv2 */
102 bool passthrough; /* Default for device is pt_domain */
103 struct {
104 bool enabled;
105 int qdep;
106 } ats; /* ATS state */
107 bool pri_tlp; /* PASID TLB required for
108 PPR completions */
109 u32 errata; /* Bitmap for errata to apply */
110 };
111
112 /*
113 * general struct to manage commands send to an IOMMU
114 */
115 struct iommu_cmd {
116 u32 data[4];
117 };
118
119 struct kmem_cache *amd_iommu_irq_cache;
120
121 static void update_domain(struct protection_domain *domain);
122 static int __init alloc_passthrough_domain(void);
123
124 /****************************************************************************
125 *
126 * Helper functions
127 *
128 ****************************************************************************/
129
130 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
131 {
132 return container_of(dom, struct protection_domain, domain);
133 }
134
135 static struct iommu_dev_data *alloc_dev_data(u16 devid)
136 {
137 struct iommu_dev_data *dev_data;
138 unsigned long flags;
139
140 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
141 if (!dev_data)
142 return NULL;
143
144 INIT_LIST_HEAD(&dev_data->alias_list);
145
146 dev_data->devid = devid;
147
148 spin_lock_irqsave(&dev_data_list_lock, flags);
149 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
150 spin_unlock_irqrestore(&dev_data_list_lock, flags);
151
152 return dev_data;
153 }
154
155 static void free_dev_data(struct iommu_dev_data *dev_data)
156 {
157 unsigned long flags;
158
159 spin_lock_irqsave(&dev_data_list_lock, flags);
160 list_del(&dev_data->dev_data_list);
161 spin_unlock_irqrestore(&dev_data_list_lock, flags);
162
163 kfree(dev_data);
164 }
165
166 static struct iommu_dev_data *search_dev_data(u16 devid)
167 {
168 struct iommu_dev_data *dev_data;
169 unsigned long flags;
170
171 spin_lock_irqsave(&dev_data_list_lock, flags);
172 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
173 if (dev_data->devid == devid)
174 goto out_unlock;
175 }
176
177 dev_data = NULL;
178
179 out_unlock:
180 spin_unlock_irqrestore(&dev_data_list_lock, flags);
181
182 return dev_data;
183 }
184
185 static struct iommu_dev_data *find_dev_data(u16 devid)
186 {
187 struct iommu_dev_data *dev_data;
188
189 dev_data = search_dev_data(devid);
190
191 if (dev_data == NULL)
192 dev_data = alloc_dev_data(devid);
193
194 return dev_data;
195 }
196
197 static inline u16 get_device_id(struct device *dev)
198 {
199 struct pci_dev *pdev = to_pci_dev(dev);
200
201 return PCI_DEVID(pdev->bus->number, pdev->devfn);
202 }
203
204 static struct iommu_dev_data *get_dev_data(struct device *dev)
205 {
206 return dev->archdata.iommu;
207 }
208
209 static bool pci_iommuv2_capable(struct pci_dev *pdev)
210 {
211 static const int caps[] = {
212 PCI_EXT_CAP_ID_ATS,
213 PCI_EXT_CAP_ID_PRI,
214 PCI_EXT_CAP_ID_PASID,
215 };
216 int i, pos;
217
218 for (i = 0; i < 3; ++i) {
219 pos = pci_find_ext_capability(pdev, caps[i]);
220 if (pos == 0)
221 return false;
222 }
223
224 return true;
225 }
226
227 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
228 {
229 struct iommu_dev_data *dev_data;
230
231 dev_data = get_dev_data(&pdev->dev);
232
233 return dev_data->errata & (1 << erratum) ? true : false;
234 }
235
236 /*
237 * In this function the list of preallocated protection domains is traversed to
238 * find the domain for a specific device
239 */
240 static struct dma_ops_domain *find_protection_domain(u16 devid)
241 {
242 struct dma_ops_domain *entry, *ret = NULL;
243 unsigned long flags;
244 u16 alias = amd_iommu_alias_table[devid];
245
246 if (list_empty(&iommu_pd_list))
247 return NULL;
248
249 spin_lock_irqsave(&iommu_pd_list_lock, flags);
250
251 list_for_each_entry(entry, &iommu_pd_list, list) {
252 if (entry->target_dev == devid ||
253 entry->target_dev == alias) {
254 ret = entry;
255 break;
256 }
257 }
258
259 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
260
261 return ret;
262 }
263
264 /*
265 * This function checks if the driver got a valid device from the caller to
266 * avoid dereferencing invalid pointers.
267 */
268 static bool check_device(struct device *dev)
269 {
270 u16 devid;
271
272 if (!dev || !dev->dma_mask)
273 return false;
274
275 /* No PCI device */
276 if (!dev_is_pci(dev))
277 return false;
278
279 devid = get_device_id(dev);
280
281 /* Out of our scope? */
282 if (devid > amd_iommu_last_bdf)
283 return false;
284
285 if (amd_iommu_rlookup_table[devid] == NULL)
286 return false;
287
288 return true;
289 }
290
291 static void init_iommu_group(struct device *dev)
292 {
293 struct iommu_group *group;
294
295 group = iommu_group_get_for_dev(dev);
296 if (!IS_ERR(group))
297 iommu_group_put(group);
298 }
299
300 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
301 {
302 *(u16 *)data = alias;
303 return 0;
304 }
305
306 static u16 get_alias(struct device *dev)
307 {
308 struct pci_dev *pdev = to_pci_dev(dev);
309 u16 devid, ivrs_alias, pci_alias;
310
311 devid = get_device_id(dev);
312 ivrs_alias = amd_iommu_alias_table[devid];
313 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
314
315 if (ivrs_alias == pci_alias)
316 return ivrs_alias;
317
318 /*
319 * DMA alias showdown
320 *
321 * The IVRS is fairly reliable in telling us about aliases, but it
322 * can't know about every screwy device. If we don't have an IVRS
323 * reported alias, use the PCI reported alias. In that case we may
324 * still need to initialize the rlookup and dev_table entries if the
325 * alias is to a non-existent device.
326 */
327 if (ivrs_alias == devid) {
328 if (!amd_iommu_rlookup_table[pci_alias]) {
329 amd_iommu_rlookup_table[pci_alias] =
330 amd_iommu_rlookup_table[devid];
331 memcpy(amd_iommu_dev_table[pci_alias].data,
332 amd_iommu_dev_table[devid].data,
333 sizeof(amd_iommu_dev_table[pci_alias].data));
334 }
335
336 return pci_alias;
337 }
338
339 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
340 "for device %s[%04x:%04x], kernel reported alias "
341 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
342 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
343 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
344 PCI_FUNC(pci_alias));
345
346 /*
347 * If we don't have a PCI DMA alias and the IVRS alias is on the same
348 * bus, then the IVRS table may know about a quirk that we don't.
349 */
350 if (pci_alias == devid &&
351 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
352 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
353 pdev->dma_alias_devfn = ivrs_alias & 0xff;
354 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
355 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
356 dev_name(dev));
357 }
358
359 return ivrs_alias;
360 }
361
362 static int iommu_init_device(struct device *dev)
363 {
364 struct pci_dev *pdev = to_pci_dev(dev);
365 struct iommu_dev_data *dev_data;
366 u16 alias;
367
368 if (dev->archdata.iommu)
369 return 0;
370
371 dev_data = find_dev_data(get_device_id(dev));
372 if (!dev_data)
373 return -ENOMEM;
374
375 alias = get_alias(dev);
376
377 if (alias != dev_data->devid) {
378 struct iommu_dev_data *alias_data;
379
380 alias_data = find_dev_data(alias);
381 if (alias_data == NULL) {
382 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
383 dev_name(dev));
384 free_dev_data(dev_data);
385 return -ENOTSUPP;
386 }
387 dev_data->alias_data = alias_data;
388
389 /* Add device to the alias_list */
390 list_add(&dev_data->alias_list, &alias_data->alias_list);
391 }
392
393 if (pci_iommuv2_capable(pdev)) {
394 struct amd_iommu *iommu;
395
396 iommu = amd_iommu_rlookup_table[dev_data->devid];
397 dev_data->iommu_v2 = iommu->is_iommu_v2;
398 }
399
400 dev->archdata.iommu = dev_data;
401
402 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
403 dev);
404
405 return 0;
406 }
407
408 static void iommu_ignore_device(struct device *dev)
409 {
410 u16 devid, alias;
411
412 devid = get_device_id(dev);
413 alias = amd_iommu_alias_table[devid];
414
415 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
416 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
417
418 amd_iommu_rlookup_table[devid] = NULL;
419 amd_iommu_rlookup_table[alias] = NULL;
420 }
421
422 static void iommu_uninit_device(struct device *dev)
423 {
424 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
425
426 if (!dev_data)
427 return;
428
429 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
430 dev);
431
432 iommu_group_remove_device(dev);
433
434 /* Unlink from alias, it may change if another device is re-plugged */
435 dev_data->alias_data = NULL;
436
437 /*
438 * We keep dev_data around for unplugged devices and reuse it when the
439 * device is re-plugged - not doing so would introduce a ton of races.
440 */
441 }
442
443 void __init amd_iommu_uninit_devices(void)
444 {
445 struct iommu_dev_data *dev_data, *n;
446 struct pci_dev *pdev = NULL;
447
448 for_each_pci_dev(pdev) {
449
450 if (!check_device(&pdev->dev))
451 continue;
452
453 iommu_uninit_device(&pdev->dev);
454 }
455
456 /* Free all of our dev_data structures */
457 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
458 free_dev_data(dev_data);
459 }
460
461 int __init amd_iommu_init_devices(void)
462 {
463 struct pci_dev *pdev = NULL;
464 int ret = 0;
465
466 for_each_pci_dev(pdev) {
467
468 if (!check_device(&pdev->dev))
469 continue;
470
471 ret = iommu_init_device(&pdev->dev);
472 if (ret == -ENOTSUPP)
473 iommu_ignore_device(&pdev->dev);
474 else if (ret)
475 goto out_free;
476 }
477
478 /*
479 * Initialize IOMMU groups only after iommu_init_device() has
480 * had a chance to populate any IVRS defined aliases.
481 */
482 for_each_pci_dev(pdev) {
483 if (check_device(&pdev->dev))
484 init_iommu_group(&pdev->dev);
485 }
486
487 return 0;
488
489 out_free:
490
491 amd_iommu_uninit_devices();
492
493 return ret;
494 }
495 #ifdef CONFIG_AMD_IOMMU_STATS
496
497 /*
498 * Initialization code for statistics collection
499 */
500
501 DECLARE_STATS_COUNTER(compl_wait);
502 DECLARE_STATS_COUNTER(cnt_map_single);
503 DECLARE_STATS_COUNTER(cnt_unmap_single);
504 DECLARE_STATS_COUNTER(cnt_map_sg);
505 DECLARE_STATS_COUNTER(cnt_unmap_sg);
506 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
507 DECLARE_STATS_COUNTER(cnt_free_coherent);
508 DECLARE_STATS_COUNTER(cross_page);
509 DECLARE_STATS_COUNTER(domain_flush_single);
510 DECLARE_STATS_COUNTER(domain_flush_all);
511 DECLARE_STATS_COUNTER(alloced_io_mem);
512 DECLARE_STATS_COUNTER(total_map_requests);
513 DECLARE_STATS_COUNTER(complete_ppr);
514 DECLARE_STATS_COUNTER(invalidate_iotlb);
515 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
516 DECLARE_STATS_COUNTER(pri_requests);
517
518 static struct dentry *stats_dir;
519 static struct dentry *de_fflush;
520
521 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
522 {
523 if (stats_dir == NULL)
524 return;
525
526 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
527 &cnt->value);
528 }
529
530 static void amd_iommu_stats_init(void)
531 {
532 stats_dir = debugfs_create_dir("amd-iommu", NULL);
533 if (stats_dir == NULL)
534 return;
535
536 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
537 &amd_iommu_unmap_flush);
538
539 amd_iommu_stats_add(&compl_wait);
540 amd_iommu_stats_add(&cnt_map_single);
541 amd_iommu_stats_add(&cnt_unmap_single);
542 amd_iommu_stats_add(&cnt_map_sg);
543 amd_iommu_stats_add(&cnt_unmap_sg);
544 amd_iommu_stats_add(&cnt_alloc_coherent);
545 amd_iommu_stats_add(&cnt_free_coherent);
546 amd_iommu_stats_add(&cross_page);
547 amd_iommu_stats_add(&domain_flush_single);
548 amd_iommu_stats_add(&domain_flush_all);
549 amd_iommu_stats_add(&alloced_io_mem);
550 amd_iommu_stats_add(&total_map_requests);
551 amd_iommu_stats_add(&complete_ppr);
552 amd_iommu_stats_add(&invalidate_iotlb);
553 amd_iommu_stats_add(&invalidate_iotlb_all);
554 amd_iommu_stats_add(&pri_requests);
555 }
556
557 #endif
558
559 /****************************************************************************
560 *
561 * Interrupt handling functions
562 *
563 ****************************************************************************/
564
565 static void dump_dte_entry(u16 devid)
566 {
567 int i;
568
569 for (i = 0; i < 4; ++i)
570 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
571 amd_iommu_dev_table[devid].data[i]);
572 }
573
574 static void dump_command(unsigned long phys_addr)
575 {
576 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
577 int i;
578
579 for (i = 0; i < 4; ++i)
580 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
581 }
582
583 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
584 {
585 int type, devid, domid, flags;
586 volatile u32 *event = __evt;
587 int count = 0;
588 u64 address;
589
590 retry:
591 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
592 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
593 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
594 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
595 address = (u64)(((u64)event[3]) << 32) | event[2];
596
597 if (type == 0) {
598 /* Did we hit the erratum? */
599 if (++count == LOOP_TIMEOUT) {
600 pr_err("AMD-Vi: No event written to event log\n");
601 return;
602 }
603 udelay(1);
604 goto retry;
605 }
606
607 printk(KERN_ERR "AMD-Vi: Event logged [");
608
609 switch (type) {
610 case EVENT_TYPE_ILL_DEV:
611 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
612 "address=0x%016llx flags=0x%04x]\n",
613 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
614 address, flags);
615 dump_dte_entry(devid);
616 break;
617 case EVENT_TYPE_IO_FAULT:
618 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
619 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
620 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
621 domid, address, flags);
622 break;
623 case EVENT_TYPE_DEV_TAB_ERR:
624 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
625 "address=0x%016llx flags=0x%04x]\n",
626 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
627 address, flags);
628 break;
629 case EVENT_TYPE_PAGE_TAB_ERR:
630 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
631 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
632 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
633 domid, address, flags);
634 break;
635 case EVENT_TYPE_ILL_CMD:
636 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
637 dump_command(address);
638 break;
639 case EVENT_TYPE_CMD_HARD_ERR:
640 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
641 "flags=0x%04x]\n", address, flags);
642 break;
643 case EVENT_TYPE_IOTLB_INV_TO:
644 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
645 "address=0x%016llx]\n",
646 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
647 address);
648 break;
649 case EVENT_TYPE_INV_DEV_REQ:
650 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
651 "address=0x%016llx flags=0x%04x]\n",
652 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
653 address, flags);
654 break;
655 default:
656 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
657 }
658
659 memset(__evt, 0, 4 * sizeof(u32));
660 }
661
662 static void iommu_poll_events(struct amd_iommu *iommu)
663 {
664 u32 head, tail;
665
666 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
667 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
668
669 while (head != tail) {
670 iommu_print_event(iommu, iommu->evt_buf + head);
671 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
672 }
673
674 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
675 }
676
677 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
678 {
679 struct amd_iommu_fault fault;
680
681 INC_STATS_COUNTER(pri_requests);
682
683 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
684 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
685 return;
686 }
687
688 fault.address = raw[1];
689 fault.pasid = PPR_PASID(raw[0]);
690 fault.device_id = PPR_DEVID(raw[0]);
691 fault.tag = PPR_TAG(raw[0]);
692 fault.flags = PPR_FLAGS(raw[0]);
693
694 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
695 }
696
697 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
698 {
699 u32 head, tail;
700
701 if (iommu->ppr_log == NULL)
702 return;
703
704 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
705 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
706
707 while (head != tail) {
708 volatile u64 *raw;
709 u64 entry[2];
710 int i;
711
712 raw = (u64 *)(iommu->ppr_log + head);
713
714 /*
715 * Hardware bug: Interrupt may arrive before the entry is
716 * written to memory. If this happens we need to wait for the
717 * entry to arrive.
718 */
719 for (i = 0; i < LOOP_TIMEOUT; ++i) {
720 if (PPR_REQ_TYPE(raw[0]) != 0)
721 break;
722 udelay(1);
723 }
724
725 /* Avoid memcpy function-call overhead */
726 entry[0] = raw[0];
727 entry[1] = raw[1];
728
729 /*
730 * To detect the hardware bug we need to clear the entry
731 * back to zero.
732 */
733 raw[0] = raw[1] = 0UL;
734
735 /* Update head pointer of hardware ring-buffer */
736 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
737 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
738
739 /* Handle PPR entry */
740 iommu_handle_ppr_entry(iommu, entry);
741
742 /* Refresh ring-buffer information */
743 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
744 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
745 }
746 }
747
748 irqreturn_t amd_iommu_int_thread(int irq, void *data)
749 {
750 struct amd_iommu *iommu = (struct amd_iommu *) data;
751 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
752
753 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
754 /* Enable EVT and PPR interrupts again */
755 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
756 iommu->mmio_base + MMIO_STATUS_OFFSET);
757
758 if (status & MMIO_STATUS_EVT_INT_MASK) {
759 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
760 iommu_poll_events(iommu);
761 }
762
763 if (status & MMIO_STATUS_PPR_INT_MASK) {
764 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
765 iommu_poll_ppr_log(iommu);
766 }
767
768 /*
769 * Hardware bug: ERBT1312
770 * When re-enabling interrupt (by writing 1
771 * to clear the bit), the hardware might also try to set
772 * the interrupt bit in the event status register.
773 * In this scenario, the bit will be set, and disable
774 * subsequent interrupts.
775 *
776 * Workaround: The IOMMU driver should read back the
777 * status register and check if the interrupt bits are cleared.
778 * If not, driver will need to go through the interrupt handler
779 * again and re-clear the bits
780 */
781 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
782 }
783 return IRQ_HANDLED;
784 }
785
786 irqreturn_t amd_iommu_int_handler(int irq, void *data)
787 {
788 return IRQ_WAKE_THREAD;
789 }
790
791 /****************************************************************************
792 *
793 * IOMMU command queuing functions
794 *
795 ****************************************************************************/
796
797 static int wait_on_sem(volatile u64 *sem)
798 {
799 int i = 0;
800
801 while (*sem == 0 && i < LOOP_TIMEOUT) {
802 udelay(1);
803 i += 1;
804 }
805
806 if (i == LOOP_TIMEOUT) {
807 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
808 return -EIO;
809 }
810
811 return 0;
812 }
813
814 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
815 struct iommu_cmd *cmd,
816 u32 tail)
817 {
818 u8 *target;
819
820 target = iommu->cmd_buf + tail;
821 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
822
823 /* Copy command to buffer */
824 memcpy(target, cmd, sizeof(*cmd));
825
826 /* Tell the IOMMU about it */
827 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
828 }
829
830 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
831 {
832 WARN_ON(address & 0x7ULL);
833
834 memset(cmd, 0, sizeof(*cmd));
835 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
836 cmd->data[1] = upper_32_bits(__pa(address));
837 cmd->data[2] = 1;
838 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
839 }
840
841 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
842 {
843 memset(cmd, 0, sizeof(*cmd));
844 cmd->data[0] = devid;
845 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
846 }
847
848 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
849 size_t size, u16 domid, int pde)
850 {
851 u64 pages;
852 bool s;
853
854 pages = iommu_num_pages(address, size, PAGE_SIZE);
855 s = false;
856
857 if (pages > 1) {
858 /*
859 * If we have to flush more than one page, flush all
860 * TLB entries for this domain
861 */
862 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
863 s = true;
864 }
865
866 address &= PAGE_MASK;
867
868 memset(cmd, 0, sizeof(*cmd));
869 cmd->data[1] |= domid;
870 cmd->data[2] = lower_32_bits(address);
871 cmd->data[3] = upper_32_bits(address);
872 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
873 if (s) /* size bit - we flush more than one 4kb page */
874 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
875 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
876 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
877 }
878
879 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
880 u64 address, size_t size)
881 {
882 u64 pages;
883 bool s;
884
885 pages = iommu_num_pages(address, size, PAGE_SIZE);
886 s = false;
887
888 if (pages > 1) {
889 /*
890 * If we have to flush more than one page, flush all
891 * TLB entries for this domain
892 */
893 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
894 s = true;
895 }
896
897 address &= PAGE_MASK;
898
899 memset(cmd, 0, sizeof(*cmd));
900 cmd->data[0] = devid;
901 cmd->data[0] |= (qdep & 0xff) << 24;
902 cmd->data[1] = devid;
903 cmd->data[2] = lower_32_bits(address);
904 cmd->data[3] = upper_32_bits(address);
905 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
906 if (s)
907 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
908 }
909
910 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
911 u64 address, bool size)
912 {
913 memset(cmd, 0, sizeof(*cmd));
914
915 address &= ~(0xfffULL);
916
917 cmd->data[0] = pasid;
918 cmd->data[1] = domid;
919 cmd->data[2] = lower_32_bits(address);
920 cmd->data[3] = upper_32_bits(address);
921 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
922 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
923 if (size)
924 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
925 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
926 }
927
928 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
929 int qdep, u64 address, bool size)
930 {
931 memset(cmd, 0, sizeof(*cmd));
932
933 address &= ~(0xfffULL);
934
935 cmd->data[0] = devid;
936 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
937 cmd->data[0] |= (qdep & 0xff) << 24;
938 cmd->data[1] = devid;
939 cmd->data[1] |= (pasid & 0xff) << 16;
940 cmd->data[2] = lower_32_bits(address);
941 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
942 cmd->data[3] = upper_32_bits(address);
943 if (size)
944 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
945 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
946 }
947
948 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
949 int status, int tag, bool gn)
950 {
951 memset(cmd, 0, sizeof(*cmd));
952
953 cmd->data[0] = devid;
954 if (gn) {
955 cmd->data[1] = pasid;
956 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
957 }
958 cmd->data[3] = tag & 0x1ff;
959 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
960
961 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
962 }
963
964 static void build_inv_all(struct iommu_cmd *cmd)
965 {
966 memset(cmd, 0, sizeof(*cmd));
967 CMD_SET_TYPE(cmd, CMD_INV_ALL);
968 }
969
970 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
971 {
972 memset(cmd, 0, sizeof(*cmd));
973 cmd->data[0] = devid;
974 CMD_SET_TYPE(cmd, CMD_INV_IRT);
975 }
976
977 /*
978 * Writes the command to the IOMMUs command buffer and informs the
979 * hardware about the new command.
980 */
981 static int iommu_queue_command_sync(struct amd_iommu *iommu,
982 struct iommu_cmd *cmd,
983 bool sync)
984 {
985 u32 left, tail, head, next_tail;
986 unsigned long flags;
987
988 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
989
990 again:
991 spin_lock_irqsave(&iommu->lock, flags);
992
993 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
994 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
995 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
996 left = (head - next_tail) % iommu->cmd_buf_size;
997
998 if (left <= 2) {
999 struct iommu_cmd sync_cmd;
1000 volatile u64 sem = 0;
1001 int ret;
1002
1003 build_completion_wait(&sync_cmd, (u64)&sem);
1004 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1005
1006 spin_unlock_irqrestore(&iommu->lock, flags);
1007
1008 if ((ret = wait_on_sem(&sem)) != 0)
1009 return ret;
1010
1011 goto again;
1012 }
1013
1014 copy_cmd_to_buffer(iommu, cmd, tail);
1015
1016 /* We need to sync now to make sure all commands are processed */
1017 iommu->need_sync = sync;
1018
1019 spin_unlock_irqrestore(&iommu->lock, flags);
1020
1021 return 0;
1022 }
1023
1024 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1025 {
1026 return iommu_queue_command_sync(iommu, cmd, true);
1027 }
1028
1029 /*
1030 * This function queues a completion wait command into the command
1031 * buffer of an IOMMU
1032 */
1033 static int iommu_completion_wait(struct amd_iommu *iommu)
1034 {
1035 struct iommu_cmd cmd;
1036 volatile u64 sem = 0;
1037 int ret;
1038
1039 if (!iommu->need_sync)
1040 return 0;
1041
1042 build_completion_wait(&cmd, (u64)&sem);
1043
1044 ret = iommu_queue_command_sync(iommu, &cmd, false);
1045 if (ret)
1046 return ret;
1047
1048 return wait_on_sem(&sem);
1049 }
1050
1051 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1052 {
1053 struct iommu_cmd cmd;
1054
1055 build_inv_dte(&cmd, devid);
1056
1057 return iommu_queue_command(iommu, &cmd);
1058 }
1059
1060 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1061 {
1062 u32 devid;
1063
1064 for (devid = 0; devid <= 0xffff; ++devid)
1065 iommu_flush_dte(iommu, devid);
1066
1067 iommu_completion_wait(iommu);
1068 }
1069
1070 /*
1071 * This function uses heavy locking and may disable irqs for some time. But
1072 * this is no issue because it is only called during resume.
1073 */
1074 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1075 {
1076 u32 dom_id;
1077
1078 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1079 struct iommu_cmd cmd;
1080 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1081 dom_id, 1);
1082 iommu_queue_command(iommu, &cmd);
1083 }
1084
1085 iommu_completion_wait(iommu);
1086 }
1087
1088 static void iommu_flush_all(struct amd_iommu *iommu)
1089 {
1090 struct iommu_cmd cmd;
1091
1092 build_inv_all(&cmd);
1093
1094 iommu_queue_command(iommu, &cmd);
1095 iommu_completion_wait(iommu);
1096 }
1097
1098 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1099 {
1100 struct iommu_cmd cmd;
1101
1102 build_inv_irt(&cmd, devid);
1103
1104 iommu_queue_command(iommu, &cmd);
1105 }
1106
1107 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1108 {
1109 u32 devid;
1110
1111 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1112 iommu_flush_irt(iommu, devid);
1113
1114 iommu_completion_wait(iommu);
1115 }
1116
1117 void iommu_flush_all_caches(struct amd_iommu *iommu)
1118 {
1119 if (iommu_feature(iommu, FEATURE_IA)) {
1120 iommu_flush_all(iommu);
1121 } else {
1122 iommu_flush_dte_all(iommu);
1123 iommu_flush_irt_all(iommu);
1124 iommu_flush_tlb_all(iommu);
1125 }
1126 }
1127
1128 /*
1129 * Command send function for flushing on-device TLB
1130 */
1131 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1132 u64 address, size_t size)
1133 {
1134 struct amd_iommu *iommu;
1135 struct iommu_cmd cmd;
1136 int qdep;
1137
1138 qdep = dev_data->ats.qdep;
1139 iommu = amd_iommu_rlookup_table[dev_data->devid];
1140
1141 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1142
1143 return iommu_queue_command(iommu, &cmd);
1144 }
1145
1146 /*
1147 * Command send function for invalidating a device table entry
1148 */
1149 static int device_flush_dte(struct iommu_dev_data *dev_data)
1150 {
1151 struct amd_iommu *iommu;
1152 int ret;
1153
1154 iommu = amd_iommu_rlookup_table[dev_data->devid];
1155
1156 ret = iommu_flush_dte(iommu, dev_data->devid);
1157 if (ret)
1158 return ret;
1159
1160 if (dev_data->ats.enabled)
1161 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1162
1163 return ret;
1164 }
1165
1166 /*
1167 * TLB invalidation function which is called from the mapping functions.
1168 * It invalidates a single PTE if the range to flush is within a single
1169 * page. Otherwise it flushes the whole TLB of the IOMMU.
1170 */
1171 static void __domain_flush_pages(struct protection_domain *domain,
1172 u64 address, size_t size, int pde)
1173 {
1174 struct iommu_dev_data *dev_data;
1175 struct iommu_cmd cmd;
1176 int ret = 0, i;
1177
1178 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1179
1180 for (i = 0; i < amd_iommus_present; ++i) {
1181 if (!domain->dev_iommu[i])
1182 continue;
1183
1184 /*
1185 * Devices of this domain are behind this IOMMU
1186 * We need a TLB flush
1187 */
1188 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1189 }
1190
1191 list_for_each_entry(dev_data, &domain->dev_list, list) {
1192
1193 if (!dev_data->ats.enabled)
1194 continue;
1195
1196 ret |= device_flush_iotlb(dev_data, address, size);
1197 }
1198
1199 WARN_ON(ret);
1200 }
1201
1202 static void domain_flush_pages(struct protection_domain *domain,
1203 u64 address, size_t size)
1204 {
1205 __domain_flush_pages(domain, address, size, 0);
1206 }
1207
1208 /* Flush the whole IO/TLB for a given protection domain */
1209 static void domain_flush_tlb(struct protection_domain *domain)
1210 {
1211 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1212 }
1213
1214 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1215 static void domain_flush_tlb_pde(struct protection_domain *domain)
1216 {
1217 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1218 }
1219
1220 static void domain_flush_complete(struct protection_domain *domain)
1221 {
1222 int i;
1223
1224 for (i = 0; i < amd_iommus_present; ++i) {
1225 if (!domain->dev_iommu[i])
1226 continue;
1227
1228 /*
1229 * Devices of this domain are behind this IOMMU
1230 * We need to wait for completion of all commands.
1231 */
1232 iommu_completion_wait(amd_iommus[i]);
1233 }
1234 }
1235
1236
1237 /*
1238 * This function flushes the DTEs for all devices in domain
1239 */
1240 static void domain_flush_devices(struct protection_domain *domain)
1241 {
1242 struct iommu_dev_data *dev_data;
1243
1244 list_for_each_entry(dev_data, &domain->dev_list, list)
1245 device_flush_dte(dev_data);
1246 }
1247
1248 /****************************************************************************
1249 *
1250 * The functions below are used the create the page table mappings for
1251 * unity mapped regions.
1252 *
1253 ****************************************************************************/
1254
1255 /*
1256 * This function is used to add another level to an IO page table. Adding
1257 * another level increases the size of the address space by 9 bits to a size up
1258 * to 64 bits.
1259 */
1260 static bool increase_address_space(struct protection_domain *domain,
1261 gfp_t gfp)
1262 {
1263 u64 *pte;
1264
1265 if (domain->mode == PAGE_MODE_6_LEVEL)
1266 /* address space already 64 bit large */
1267 return false;
1268
1269 pte = (void *)get_zeroed_page(gfp);
1270 if (!pte)
1271 return false;
1272
1273 *pte = PM_LEVEL_PDE(domain->mode,
1274 virt_to_phys(domain->pt_root));
1275 domain->pt_root = pte;
1276 domain->mode += 1;
1277 domain->updated = true;
1278
1279 return true;
1280 }
1281
1282 static u64 *alloc_pte(struct protection_domain *domain,
1283 unsigned long address,
1284 unsigned long page_size,
1285 u64 **pte_page,
1286 gfp_t gfp)
1287 {
1288 int level, end_lvl;
1289 u64 *pte, *page;
1290
1291 BUG_ON(!is_power_of_2(page_size));
1292
1293 while (address > PM_LEVEL_SIZE(domain->mode))
1294 increase_address_space(domain, gfp);
1295
1296 level = domain->mode - 1;
1297 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1298 address = PAGE_SIZE_ALIGN(address, page_size);
1299 end_lvl = PAGE_SIZE_LEVEL(page_size);
1300
1301 while (level > end_lvl) {
1302 if (!IOMMU_PTE_PRESENT(*pte)) {
1303 page = (u64 *)get_zeroed_page(gfp);
1304 if (!page)
1305 return NULL;
1306 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1307 }
1308
1309 /* No level skipping support yet */
1310 if (PM_PTE_LEVEL(*pte) != level)
1311 return NULL;
1312
1313 level -= 1;
1314
1315 pte = IOMMU_PTE_PAGE(*pte);
1316
1317 if (pte_page && level == end_lvl)
1318 *pte_page = pte;
1319
1320 pte = &pte[PM_LEVEL_INDEX(level, address)];
1321 }
1322
1323 return pte;
1324 }
1325
1326 /*
1327 * This function checks if there is a PTE for a given dma address. If
1328 * there is one, it returns the pointer to it.
1329 */
1330 static u64 *fetch_pte(struct protection_domain *domain,
1331 unsigned long address,
1332 unsigned long *page_size)
1333 {
1334 int level;
1335 u64 *pte;
1336
1337 if (address > PM_LEVEL_SIZE(domain->mode))
1338 return NULL;
1339
1340 level = domain->mode - 1;
1341 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1342 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1343
1344 while (level > 0) {
1345
1346 /* Not Present */
1347 if (!IOMMU_PTE_PRESENT(*pte))
1348 return NULL;
1349
1350 /* Large PTE */
1351 if (PM_PTE_LEVEL(*pte) == 7 ||
1352 PM_PTE_LEVEL(*pte) == 0)
1353 break;
1354
1355 /* No level skipping support yet */
1356 if (PM_PTE_LEVEL(*pte) != level)
1357 return NULL;
1358
1359 level -= 1;
1360
1361 /* Walk to the next level */
1362 pte = IOMMU_PTE_PAGE(*pte);
1363 pte = &pte[PM_LEVEL_INDEX(level, address)];
1364 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1365 }
1366
1367 if (PM_PTE_LEVEL(*pte) == 0x07) {
1368 unsigned long pte_mask;
1369
1370 /*
1371 * If we have a series of large PTEs, make
1372 * sure to return a pointer to the first one.
1373 */
1374 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1375 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1376 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1377 }
1378
1379 return pte;
1380 }
1381
1382 /*
1383 * Generic mapping functions. It maps a physical address into a DMA
1384 * address space. It allocates the page table pages if necessary.
1385 * In the future it can be extended to a generic mapping function
1386 * supporting all features of AMD IOMMU page tables like level skipping
1387 * and full 64 bit address spaces.
1388 */
1389 static int iommu_map_page(struct protection_domain *dom,
1390 unsigned long bus_addr,
1391 unsigned long phys_addr,
1392 int prot,
1393 unsigned long page_size)
1394 {
1395 u64 __pte, *pte;
1396 int i, count;
1397
1398 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1399 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1400
1401 if (!(prot & IOMMU_PROT_MASK))
1402 return -EINVAL;
1403
1404 count = PAGE_SIZE_PTE_COUNT(page_size);
1405 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1406
1407 if (!pte)
1408 return -ENOMEM;
1409
1410 for (i = 0; i < count; ++i)
1411 if (IOMMU_PTE_PRESENT(pte[i]))
1412 return -EBUSY;
1413
1414 if (count > 1) {
1415 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1416 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1417 } else
1418 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1419
1420 if (prot & IOMMU_PROT_IR)
1421 __pte |= IOMMU_PTE_IR;
1422 if (prot & IOMMU_PROT_IW)
1423 __pte |= IOMMU_PTE_IW;
1424
1425 for (i = 0; i < count; ++i)
1426 pte[i] = __pte;
1427
1428 update_domain(dom);
1429
1430 return 0;
1431 }
1432
1433 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1434 unsigned long bus_addr,
1435 unsigned long page_size)
1436 {
1437 unsigned long long unmapped;
1438 unsigned long unmap_size;
1439 u64 *pte;
1440
1441 BUG_ON(!is_power_of_2(page_size));
1442
1443 unmapped = 0;
1444
1445 while (unmapped < page_size) {
1446
1447 pte = fetch_pte(dom, bus_addr, &unmap_size);
1448
1449 if (pte) {
1450 int i, count;
1451
1452 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1453 for (i = 0; i < count; i++)
1454 pte[i] = 0ULL;
1455 }
1456
1457 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1458 unmapped += unmap_size;
1459 }
1460
1461 BUG_ON(unmapped && !is_power_of_2(unmapped));
1462
1463 return unmapped;
1464 }
1465
1466 /*
1467 * This function checks if a specific unity mapping entry is needed for
1468 * this specific IOMMU.
1469 */
1470 static int iommu_for_unity_map(struct amd_iommu *iommu,
1471 struct unity_map_entry *entry)
1472 {
1473 u16 bdf, i;
1474
1475 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1476 bdf = amd_iommu_alias_table[i];
1477 if (amd_iommu_rlookup_table[bdf] == iommu)
1478 return 1;
1479 }
1480
1481 return 0;
1482 }
1483
1484 /*
1485 * This function actually applies the mapping to the page table of the
1486 * dma_ops domain.
1487 */
1488 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1489 struct unity_map_entry *e)
1490 {
1491 u64 addr;
1492 int ret;
1493
1494 for (addr = e->address_start; addr < e->address_end;
1495 addr += PAGE_SIZE) {
1496 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1497 PAGE_SIZE);
1498 if (ret)
1499 return ret;
1500 /*
1501 * if unity mapping is in aperture range mark the page
1502 * as allocated in the aperture
1503 */
1504 if (addr < dma_dom->aperture_size)
1505 __set_bit(addr >> PAGE_SHIFT,
1506 dma_dom->aperture[0]->bitmap);
1507 }
1508
1509 return 0;
1510 }
1511
1512 /*
1513 * Init the unity mappings for a specific IOMMU in the system
1514 *
1515 * Basically iterates over all unity mapping entries and applies them to
1516 * the default domain DMA of that IOMMU if necessary.
1517 */
1518 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1519 {
1520 struct unity_map_entry *entry;
1521 int ret;
1522
1523 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1524 if (!iommu_for_unity_map(iommu, entry))
1525 continue;
1526 ret = dma_ops_unity_map(iommu->default_dom, entry);
1527 if (ret)
1528 return ret;
1529 }
1530
1531 return 0;
1532 }
1533
1534 /*
1535 * Inits the unity mappings required for a specific device
1536 */
1537 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1538 u16 devid)
1539 {
1540 struct unity_map_entry *e;
1541 int ret;
1542
1543 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1544 if (!(devid >= e->devid_start && devid <= e->devid_end))
1545 continue;
1546 ret = dma_ops_unity_map(dma_dom, e);
1547 if (ret)
1548 return ret;
1549 }
1550
1551 return 0;
1552 }
1553
1554 /****************************************************************************
1555 *
1556 * The next functions belong to the address allocator for the dma_ops
1557 * interface functions. They work like the allocators in the other IOMMU
1558 * drivers. Its basically a bitmap which marks the allocated pages in
1559 * the aperture. Maybe it could be enhanced in the future to a more
1560 * efficient allocator.
1561 *
1562 ****************************************************************************/
1563
1564 /*
1565 * The address allocator core functions.
1566 *
1567 * called with domain->lock held
1568 */
1569
1570 /*
1571 * Used to reserve address ranges in the aperture (e.g. for exclusion
1572 * ranges.
1573 */
1574 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1575 unsigned long start_page,
1576 unsigned int pages)
1577 {
1578 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1579
1580 if (start_page + pages > last_page)
1581 pages = last_page - start_page;
1582
1583 for (i = start_page; i < start_page + pages; ++i) {
1584 int index = i / APERTURE_RANGE_PAGES;
1585 int page = i % APERTURE_RANGE_PAGES;
1586 __set_bit(page, dom->aperture[index]->bitmap);
1587 }
1588 }
1589
1590 /*
1591 * This function is used to add a new aperture range to an existing
1592 * aperture in case of dma_ops domain allocation or address allocation
1593 * failure.
1594 */
1595 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1596 bool populate, gfp_t gfp)
1597 {
1598 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1599 struct amd_iommu *iommu;
1600 unsigned long i, old_size, pte_pgsize;
1601
1602 #ifdef CONFIG_IOMMU_STRESS
1603 populate = false;
1604 #endif
1605
1606 if (index >= APERTURE_MAX_RANGES)
1607 return -ENOMEM;
1608
1609 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1610 if (!dma_dom->aperture[index])
1611 return -ENOMEM;
1612
1613 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1614 if (!dma_dom->aperture[index]->bitmap)
1615 goto out_free;
1616
1617 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1618
1619 if (populate) {
1620 unsigned long address = dma_dom->aperture_size;
1621 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1622 u64 *pte, *pte_page;
1623
1624 for (i = 0; i < num_ptes; ++i) {
1625 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1626 &pte_page, gfp);
1627 if (!pte)
1628 goto out_free;
1629
1630 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1631
1632 address += APERTURE_RANGE_SIZE / 64;
1633 }
1634 }
1635
1636 old_size = dma_dom->aperture_size;
1637 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1638
1639 /* Reserve address range used for MSI messages */
1640 if (old_size < MSI_ADDR_BASE_LO &&
1641 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1642 unsigned long spage;
1643 int pages;
1644
1645 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1646 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1647
1648 dma_ops_reserve_addresses(dma_dom, spage, pages);
1649 }
1650
1651 /* Initialize the exclusion range if necessary */
1652 for_each_iommu(iommu) {
1653 if (iommu->exclusion_start &&
1654 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1655 && iommu->exclusion_start < dma_dom->aperture_size) {
1656 unsigned long startpage;
1657 int pages = iommu_num_pages(iommu->exclusion_start,
1658 iommu->exclusion_length,
1659 PAGE_SIZE);
1660 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1661 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1662 }
1663 }
1664
1665 /*
1666 * Check for areas already mapped as present in the new aperture
1667 * range and mark those pages as reserved in the allocator. Such
1668 * mappings may already exist as a result of requested unity
1669 * mappings for devices.
1670 */
1671 for (i = dma_dom->aperture[index]->offset;
1672 i < dma_dom->aperture_size;
1673 i += pte_pgsize) {
1674 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1675 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1676 continue;
1677
1678 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1679 pte_pgsize >> 12);
1680 }
1681
1682 update_domain(&dma_dom->domain);
1683
1684 return 0;
1685
1686 out_free:
1687 update_domain(&dma_dom->domain);
1688
1689 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1690
1691 kfree(dma_dom->aperture[index]);
1692 dma_dom->aperture[index] = NULL;
1693
1694 return -ENOMEM;
1695 }
1696
1697 static unsigned long dma_ops_area_alloc(struct device *dev,
1698 struct dma_ops_domain *dom,
1699 unsigned int pages,
1700 unsigned long align_mask,
1701 u64 dma_mask,
1702 unsigned long start)
1703 {
1704 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1705 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1706 int i = start >> APERTURE_RANGE_SHIFT;
1707 unsigned long boundary_size;
1708 unsigned long address = -1;
1709 unsigned long limit;
1710
1711 next_bit >>= PAGE_SHIFT;
1712
1713 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
1714 PAGE_SIZE) >> PAGE_SHIFT;
1715
1716 for (;i < max_index; ++i) {
1717 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1718
1719 if (dom->aperture[i]->offset >= dma_mask)
1720 break;
1721
1722 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1723 dma_mask >> PAGE_SHIFT);
1724
1725 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1726 limit, next_bit, pages, 0,
1727 boundary_size, align_mask);
1728 if (address != -1) {
1729 address = dom->aperture[i]->offset +
1730 (address << PAGE_SHIFT);
1731 dom->next_address = address + (pages << PAGE_SHIFT);
1732 break;
1733 }
1734
1735 next_bit = 0;
1736 }
1737
1738 return address;
1739 }
1740
1741 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1742 struct dma_ops_domain *dom,
1743 unsigned int pages,
1744 unsigned long align_mask,
1745 u64 dma_mask)
1746 {
1747 unsigned long address;
1748
1749 #ifdef CONFIG_IOMMU_STRESS
1750 dom->next_address = 0;
1751 dom->need_flush = true;
1752 #endif
1753
1754 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1755 dma_mask, dom->next_address);
1756
1757 if (address == -1) {
1758 dom->next_address = 0;
1759 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1760 dma_mask, 0);
1761 dom->need_flush = true;
1762 }
1763
1764 if (unlikely(address == -1))
1765 address = DMA_ERROR_CODE;
1766
1767 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1768
1769 return address;
1770 }
1771
1772 /*
1773 * The address free function.
1774 *
1775 * called with domain->lock held
1776 */
1777 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1778 unsigned long address,
1779 unsigned int pages)
1780 {
1781 unsigned i = address >> APERTURE_RANGE_SHIFT;
1782 struct aperture_range *range = dom->aperture[i];
1783
1784 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1785
1786 #ifdef CONFIG_IOMMU_STRESS
1787 if (i < 4)
1788 return;
1789 #endif
1790
1791 if (address >= dom->next_address)
1792 dom->need_flush = true;
1793
1794 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1795
1796 bitmap_clear(range->bitmap, address, pages);
1797
1798 }
1799
1800 /****************************************************************************
1801 *
1802 * The next functions belong to the domain allocation. A domain is
1803 * allocated for every IOMMU as the default domain. If device isolation
1804 * is enabled, every device get its own domain. The most important thing
1805 * about domains is the page table mapping the DMA address space they
1806 * contain.
1807 *
1808 ****************************************************************************/
1809
1810 /*
1811 * This function adds a protection domain to the global protection domain list
1812 */
1813 static void add_domain_to_list(struct protection_domain *domain)
1814 {
1815 unsigned long flags;
1816
1817 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1818 list_add(&domain->list, &amd_iommu_pd_list);
1819 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1820 }
1821
1822 /*
1823 * This function removes a protection domain to the global
1824 * protection domain list
1825 */
1826 static void del_domain_from_list(struct protection_domain *domain)
1827 {
1828 unsigned long flags;
1829
1830 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1831 list_del(&domain->list);
1832 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1833 }
1834
1835 static u16 domain_id_alloc(void)
1836 {
1837 unsigned long flags;
1838 int id;
1839
1840 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1841 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1842 BUG_ON(id == 0);
1843 if (id > 0 && id < MAX_DOMAIN_ID)
1844 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1845 else
1846 id = 0;
1847 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1848
1849 return id;
1850 }
1851
1852 static void domain_id_free(int id)
1853 {
1854 unsigned long flags;
1855
1856 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1857 if (id > 0 && id < MAX_DOMAIN_ID)
1858 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1859 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1860 }
1861
1862 #define DEFINE_FREE_PT_FN(LVL, FN) \
1863 static void free_pt_##LVL (unsigned long __pt) \
1864 { \
1865 unsigned long p; \
1866 u64 *pt; \
1867 int i; \
1868 \
1869 pt = (u64 *)__pt; \
1870 \
1871 for (i = 0; i < 512; ++i) { \
1872 if (!IOMMU_PTE_PRESENT(pt[i])) \
1873 continue; \
1874 \
1875 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1876 FN(p); \
1877 } \
1878 free_page((unsigned long)pt); \
1879 }
1880
1881 DEFINE_FREE_PT_FN(l2, free_page)
1882 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1883 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1884 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1885 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1886
1887 static void free_pagetable(struct protection_domain *domain)
1888 {
1889 unsigned long root = (unsigned long)domain->pt_root;
1890
1891 switch (domain->mode) {
1892 case PAGE_MODE_NONE:
1893 break;
1894 case PAGE_MODE_1_LEVEL:
1895 free_page(root);
1896 break;
1897 case PAGE_MODE_2_LEVEL:
1898 free_pt_l2(root);
1899 break;
1900 case PAGE_MODE_3_LEVEL:
1901 free_pt_l3(root);
1902 break;
1903 case PAGE_MODE_4_LEVEL:
1904 free_pt_l4(root);
1905 break;
1906 case PAGE_MODE_5_LEVEL:
1907 free_pt_l5(root);
1908 break;
1909 case PAGE_MODE_6_LEVEL:
1910 free_pt_l6(root);
1911 break;
1912 default:
1913 BUG();
1914 }
1915 }
1916
1917 static void free_gcr3_tbl_level1(u64 *tbl)
1918 {
1919 u64 *ptr;
1920 int i;
1921
1922 for (i = 0; i < 512; ++i) {
1923 if (!(tbl[i] & GCR3_VALID))
1924 continue;
1925
1926 ptr = __va(tbl[i] & PAGE_MASK);
1927
1928 free_page((unsigned long)ptr);
1929 }
1930 }
1931
1932 static void free_gcr3_tbl_level2(u64 *tbl)
1933 {
1934 u64 *ptr;
1935 int i;
1936
1937 for (i = 0; i < 512; ++i) {
1938 if (!(tbl[i] & GCR3_VALID))
1939 continue;
1940
1941 ptr = __va(tbl[i] & PAGE_MASK);
1942
1943 free_gcr3_tbl_level1(ptr);
1944 }
1945 }
1946
1947 static void free_gcr3_table(struct protection_domain *domain)
1948 {
1949 if (domain->glx == 2)
1950 free_gcr3_tbl_level2(domain->gcr3_tbl);
1951 else if (domain->glx == 1)
1952 free_gcr3_tbl_level1(domain->gcr3_tbl);
1953 else if (domain->glx != 0)
1954 BUG();
1955
1956 free_page((unsigned long)domain->gcr3_tbl);
1957 }
1958
1959 /*
1960 * Free a domain, only used if something went wrong in the
1961 * allocation path and we need to free an already allocated page table
1962 */
1963 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1964 {
1965 int i;
1966
1967 if (!dom)
1968 return;
1969
1970 del_domain_from_list(&dom->domain);
1971
1972 free_pagetable(&dom->domain);
1973
1974 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1975 if (!dom->aperture[i])
1976 continue;
1977 free_page((unsigned long)dom->aperture[i]->bitmap);
1978 kfree(dom->aperture[i]);
1979 }
1980
1981 kfree(dom);
1982 }
1983
1984 /*
1985 * Allocates a new protection domain usable for the dma_ops functions.
1986 * It also initializes the page table and the address allocator data
1987 * structures required for the dma_ops interface
1988 */
1989 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1990 {
1991 struct dma_ops_domain *dma_dom;
1992
1993 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1994 if (!dma_dom)
1995 return NULL;
1996
1997 spin_lock_init(&dma_dom->domain.lock);
1998
1999 dma_dom->domain.id = domain_id_alloc();
2000 if (dma_dom->domain.id == 0)
2001 goto free_dma_dom;
2002 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2003 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2004 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2005 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2006 dma_dom->domain.priv = dma_dom;
2007 if (!dma_dom->domain.pt_root)
2008 goto free_dma_dom;
2009
2010 dma_dom->need_flush = false;
2011 dma_dom->target_dev = 0xffff;
2012
2013 add_domain_to_list(&dma_dom->domain);
2014
2015 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2016 goto free_dma_dom;
2017
2018 /*
2019 * mark the first page as allocated so we never return 0 as
2020 * a valid dma-address. So we can use 0 as error value
2021 */
2022 dma_dom->aperture[0]->bitmap[0] = 1;
2023 dma_dom->next_address = 0;
2024
2025
2026 return dma_dom;
2027
2028 free_dma_dom:
2029 dma_ops_domain_free(dma_dom);
2030
2031 return NULL;
2032 }
2033
2034 /*
2035 * little helper function to check whether a given protection domain is a
2036 * dma_ops domain
2037 */
2038 static bool dma_ops_domain(struct protection_domain *domain)
2039 {
2040 return domain->flags & PD_DMA_OPS_MASK;
2041 }
2042
2043 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2044 {
2045 u64 pte_root = 0;
2046 u64 flags = 0;
2047
2048 if (domain->mode != PAGE_MODE_NONE)
2049 pte_root = virt_to_phys(domain->pt_root);
2050
2051 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2052 << DEV_ENTRY_MODE_SHIFT;
2053 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2054
2055 flags = amd_iommu_dev_table[devid].data[1];
2056
2057 if (ats)
2058 flags |= DTE_FLAG_IOTLB;
2059
2060 if (domain->flags & PD_IOMMUV2_MASK) {
2061 u64 gcr3 = __pa(domain->gcr3_tbl);
2062 u64 glx = domain->glx;
2063 u64 tmp;
2064
2065 pte_root |= DTE_FLAG_GV;
2066 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2067
2068 /* First mask out possible old values for GCR3 table */
2069 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2070 flags &= ~tmp;
2071
2072 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2073 flags &= ~tmp;
2074
2075 /* Encode GCR3 table into DTE */
2076 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2077 pte_root |= tmp;
2078
2079 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2080 flags |= tmp;
2081
2082 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2083 flags |= tmp;
2084 }
2085
2086 flags &= ~(0xffffUL);
2087 flags |= domain->id;
2088
2089 amd_iommu_dev_table[devid].data[1] = flags;
2090 amd_iommu_dev_table[devid].data[0] = pte_root;
2091 }
2092
2093 static void clear_dte_entry(u16 devid)
2094 {
2095 /* remove entry from the device table seen by the hardware */
2096 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2097 amd_iommu_dev_table[devid].data[1] = 0;
2098
2099 amd_iommu_apply_erratum_63(devid);
2100 }
2101
2102 static void do_attach(struct iommu_dev_data *dev_data,
2103 struct protection_domain *domain)
2104 {
2105 struct amd_iommu *iommu;
2106 bool ats;
2107
2108 iommu = amd_iommu_rlookup_table[dev_data->devid];
2109 ats = dev_data->ats.enabled;
2110
2111 /* Update data structures */
2112 dev_data->domain = domain;
2113 list_add(&dev_data->list, &domain->dev_list);
2114 set_dte_entry(dev_data->devid, domain, ats);
2115
2116 /* Do reference counting */
2117 domain->dev_iommu[iommu->index] += 1;
2118 domain->dev_cnt += 1;
2119
2120 /* Flush the DTE entry */
2121 device_flush_dte(dev_data);
2122 }
2123
2124 static void do_detach(struct iommu_dev_data *dev_data)
2125 {
2126 struct amd_iommu *iommu;
2127
2128 iommu = amd_iommu_rlookup_table[dev_data->devid];
2129
2130 /* decrease reference counters */
2131 dev_data->domain->dev_iommu[iommu->index] -= 1;
2132 dev_data->domain->dev_cnt -= 1;
2133
2134 /* Update data structures */
2135 dev_data->domain = NULL;
2136 list_del(&dev_data->list);
2137 clear_dte_entry(dev_data->devid);
2138
2139 /* Flush the DTE entry */
2140 device_flush_dte(dev_data);
2141 }
2142
2143 /*
2144 * If a device is not yet associated with a domain, this function does
2145 * assigns it visible for the hardware
2146 */
2147 static int __attach_device(struct iommu_dev_data *dev_data,
2148 struct protection_domain *domain)
2149 {
2150 struct iommu_dev_data *head, *entry;
2151 int ret;
2152
2153 /* lock domain */
2154 spin_lock(&domain->lock);
2155
2156 head = dev_data;
2157
2158 if (head->alias_data != NULL)
2159 head = head->alias_data;
2160
2161 /* Now we have the root of the alias group, if any */
2162
2163 ret = -EBUSY;
2164 if (head->domain != NULL)
2165 goto out_unlock;
2166
2167 /* Attach alias group root */
2168 do_attach(head, domain);
2169
2170 /* Attach other devices in the alias group */
2171 list_for_each_entry(entry, &head->alias_list, alias_list)
2172 do_attach(entry, domain);
2173
2174 ret = 0;
2175
2176 out_unlock:
2177
2178 /* ready */
2179 spin_unlock(&domain->lock);
2180
2181 return ret;
2182 }
2183
2184
2185 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2186 {
2187 pci_disable_ats(pdev);
2188 pci_disable_pri(pdev);
2189 pci_disable_pasid(pdev);
2190 }
2191
2192 /* FIXME: Change generic reset-function to do the same */
2193 static int pri_reset_while_enabled(struct pci_dev *pdev)
2194 {
2195 u16 control;
2196 int pos;
2197
2198 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2199 if (!pos)
2200 return -EINVAL;
2201
2202 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2203 control |= PCI_PRI_CTRL_RESET;
2204 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2205
2206 return 0;
2207 }
2208
2209 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2210 {
2211 bool reset_enable;
2212 int reqs, ret;
2213
2214 /* FIXME: Hardcode number of outstanding requests for now */
2215 reqs = 32;
2216 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2217 reqs = 1;
2218 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2219
2220 /* Only allow access to user-accessible pages */
2221 ret = pci_enable_pasid(pdev, 0);
2222 if (ret)
2223 goto out_err;
2224
2225 /* First reset the PRI state of the device */
2226 ret = pci_reset_pri(pdev);
2227 if (ret)
2228 goto out_err;
2229
2230 /* Enable PRI */
2231 ret = pci_enable_pri(pdev, reqs);
2232 if (ret)
2233 goto out_err;
2234
2235 if (reset_enable) {
2236 ret = pri_reset_while_enabled(pdev);
2237 if (ret)
2238 goto out_err;
2239 }
2240
2241 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2242 if (ret)
2243 goto out_err;
2244
2245 return 0;
2246
2247 out_err:
2248 pci_disable_pri(pdev);
2249 pci_disable_pasid(pdev);
2250
2251 return ret;
2252 }
2253
2254 /* FIXME: Move this to PCI code */
2255 #define PCI_PRI_TLP_OFF (1 << 15)
2256
2257 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2258 {
2259 u16 status;
2260 int pos;
2261
2262 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2263 if (!pos)
2264 return false;
2265
2266 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2267
2268 return (status & PCI_PRI_TLP_OFF) ? true : false;
2269 }
2270
2271 /*
2272 * If a device is not yet associated with a domain, this function
2273 * assigns it visible for the hardware
2274 */
2275 static int attach_device(struct device *dev,
2276 struct protection_domain *domain)
2277 {
2278 struct pci_dev *pdev = to_pci_dev(dev);
2279 struct iommu_dev_data *dev_data;
2280 unsigned long flags;
2281 int ret;
2282
2283 dev_data = get_dev_data(dev);
2284
2285 if (domain->flags & PD_IOMMUV2_MASK) {
2286 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2287 return -EINVAL;
2288
2289 if (pdev_iommuv2_enable(pdev) != 0)
2290 return -EINVAL;
2291
2292 dev_data->ats.enabled = true;
2293 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2294 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2295 } else if (amd_iommu_iotlb_sup &&
2296 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2297 dev_data->ats.enabled = true;
2298 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2299 }
2300
2301 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2302 ret = __attach_device(dev_data, domain);
2303 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2304
2305 /*
2306 * We might boot into a crash-kernel here. The crashed kernel
2307 * left the caches in the IOMMU dirty. So we have to flush
2308 * here to evict all dirty stuff.
2309 */
2310 domain_flush_tlb_pde(domain);
2311
2312 return ret;
2313 }
2314
2315 /*
2316 * Removes a device from a protection domain (unlocked)
2317 */
2318 static void __detach_device(struct iommu_dev_data *dev_data)
2319 {
2320 struct iommu_dev_data *head, *entry;
2321 struct protection_domain *domain;
2322 unsigned long flags;
2323
2324 BUG_ON(!dev_data->domain);
2325
2326 domain = dev_data->domain;
2327
2328 spin_lock_irqsave(&domain->lock, flags);
2329
2330 head = dev_data;
2331 if (head->alias_data != NULL)
2332 head = head->alias_data;
2333
2334 list_for_each_entry(entry, &head->alias_list, alias_list)
2335 do_detach(entry);
2336
2337 do_detach(head);
2338
2339 spin_unlock_irqrestore(&domain->lock, flags);
2340
2341 /*
2342 * If we run in passthrough mode the device must be assigned to the
2343 * passthrough domain if it is detached from any other domain.
2344 * Make sure we can deassign from the pt_domain itself.
2345 */
2346 if (dev_data->passthrough &&
2347 (dev_data->domain == NULL && domain != pt_domain))
2348 __attach_device(dev_data, pt_domain);
2349 }
2350
2351 /*
2352 * Removes a device from a protection domain (with devtable_lock held)
2353 */
2354 static void detach_device(struct device *dev)
2355 {
2356 struct protection_domain *domain;
2357 struct iommu_dev_data *dev_data;
2358 unsigned long flags;
2359
2360 dev_data = get_dev_data(dev);
2361 domain = dev_data->domain;
2362
2363 /* lock device table */
2364 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2365 __detach_device(dev_data);
2366 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2367
2368 if (domain->flags & PD_IOMMUV2_MASK)
2369 pdev_iommuv2_disable(to_pci_dev(dev));
2370 else if (dev_data->ats.enabled)
2371 pci_disable_ats(to_pci_dev(dev));
2372
2373 dev_data->ats.enabled = false;
2374 }
2375
2376 /*
2377 * Find out the protection domain structure for a given PCI device. This
2378 * will give us the pointer to the page table root for example.
2379 */
2380 static struct protection_domain *domain_for_device(struct device *dev)
2381 {
2382 struct iommu_dev_data *dev_data;
2383 struct protection_domain *dom = NULL;
2384 unsigned long flags;
2385
2386 dev_data = get_dev_data(dev);
2387
2388 if (dev_data->domain)
2389 return dev_data->domain;
2390
2391 if (dev_data->alias_data != NULL) {
2392 struct iommu_dev_data *alias_data = dev_data->alias_data;
2393
2394 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2395 if (alias_data->domain != NULL) {
2396 __attach_device(dev_data, alias_data->domain);
2397 dom = alias_data->domain;
2398 }
2399 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2400 }
2401
2402 return dom;
2403 }
2404
2405 static int device_change_notifier(struct notifier_block *nb,
2406 unsigned long action, void *data)
2407 {
2408 struct dma_ops_domain *dma_domain;
2409 struct protection_domain *domain;
2410 struct iommu_dev_data *dev_data;
2411 struct device *dev = data;
2412 struct amd_iommu *iommu;
2413 unsigned long flags;
2414 u16 devid;
2415
2416 if (!check_device(dev))
2417 return 0;
2418
2419 devid = get_device_id(dev);
2420 iommu = amd_iommu_rlookup_table[devid];
2421 dev_data = get_dev_data(dev);
2422
2423 switch (action) {
2424 case BUS_NOTIFY_ADD_DEVICE:
2425
2426 iommu_init_device(dev);
2427 init_iommu_group(dev);
2428
2429 /*
2430 * dev_data is still NULL and
2431 * got initialized in iommu_init_device
2432 */
2433 dev_data = get_dev_data(dev);
2434
2435 if (iommu_pass_through || dev_data->iommu_v2) {
2436 dev_data->passthrough = true;
2437 attach_device(dev, pt_domain);
2438 break;
2439 }
2440
2441 domain = domain_for_device(dev);
2442
2443 /* allocate a protection domain if a device is added */
2444 dma_domain = find_protection_domain(devid);
2445 if (!dma_domain) {
2446 dma_domain = dma_ops_domain_alloc();
2447 if (!dma_domain)
2448 goto out;
2449 dma_domain->target_dev = devid;
2450
2451 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2452 list_add_tail(&dma_domain->list, &iommu_pd_list);
2453 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2454 }
2455
2456 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2457
2458 break;
2459 case BUS_NOTIFY_REMOVED_DEVICE:
2460
2461 iommu_uninit_device(dev);
2462
2463 default:
2464 goto out;
2465 }
2466
2467 iommu_completion_wait(iommu);
2468
2469 out:
2470 return 0;
2471 }
2472
2473 static struct notifier_block device_nb = {
2474 .notifier_call = device_change_notifier,
2475 };
2476
2477 void amd_iommu_init_notifier(void)
2478 {
2479 bus_register_notifier(&pci_bus_type, &device_nb);
2480 }
2481
2482 /*****************************************************************************
2483 *
2484 * The next functions belong to the dma_ops mapping/unmapping code.
2485 *
2486 *****************************************************************************/
2487
2488 /*
2489 * In the dma_ops path we only have the struct device. This function
2490 * finds the corresponding IOMMU, the protection domain and the
2491 * requestor id for a given device.
2492 * If the device is not yet associated with a domain this is also done
2493 * in this function.
2494 */
2495 static struct protection_domain *get_domain(struct device *dev)
2496 {
2497 struct protection_domain *domain;
2498 struct dma_ops_domain *dma_dom;
2499 u16 devid = get_device_id(dev);
2500
2501 if (!check_device(dev))
2502 return ERR_PTR(-EINVAL);
2503
2504 domain = domain_for_device(dev);
2505 if (domain != NULL && !dma_ops_domain(domain))
2506 return ERR_PTR(-EBUSY);
2507
2508 if (domain != NULL)
2509 return domain;
2510
2511 /* Device not bound yet - bind it */
2512 dma_dom = find_protection_domain(devid);
2513 if (!dma_dom)
2514 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2515 attach_device(dev, &dma_dom->domain);
2516 DUMP_printk("Using protection domain %d for device %s\n",
2517 dma_dom->domain.id, dev_name(dev));
2518
2519 return &dma_dom->domain;
2520 }
2521
2522 static void update_device_table(struct protection_domain *domain)
2523 {
2524 struct iommu_dev_data *dev_data;
2525
2526 list_for_each_entry(dev_data, &domain->dev_list, list)
2527 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2528 }
2529
2530 static void update_domain(struct protection_domain *domain)
2531 {
2532 if (!domain->updated)
2533 return;
2534
2535 update_device_table(domain);
2536
2537 domain_flush_devices(domain);
2538 domain_flush_tlb_pde(domain);
2539
2540 domain->updated = false;
2541 }
2542
2543 /*
2544 * This function fetches the PTE for a given address in the aperture
2545 */
2546 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2547 unsigned long address)
2548 {
2549 struct aperture_range *aperture;
2550 u64 *pte, *pte_page;
2551
2552 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2553 if (!aperture)
2554 return NULL;
2555
2556 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2557 if (!pte) {
2558 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2559 GFP_ATOMIC);
2560 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2561 } else
2562 pte += PM_LEVEL_INDEX(0, address);
2563
2564 update_domain(&dom->domain);
2565
2566 return pte;
2567 }
2568
2569 /*
2570 * This is the generic map function. It maps one 4kb page at paddr to
2571 * the given address in the DMA address space for the domain.
2572 */
2573 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2574 unsigned long address,
2575 phys_addr_t paddr,
2576 int direction)
2577 {
2578 u64 *pte, __pte;
2579
2580 WARN_ON(address > dom->aperture_size);
2581
2582 paddr &= PAGE_MASK;
2583
2584 pte = dma_ops_get_pte(dom, address);
2585 if (!pte)
2586 return DMA_ERROR_CODE;
2587
2588 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2589
2590 if (direction == DMA_TO_DEVICE)
2591 __pte |= IOMMU_PTE_IR;
2592 else if (direction == DMA_FROM_DEVICE)
2593 __pte |= IOMMU_PTE_IW;
2594 else if (direction == DMA_BIDIRECTIONAL)
2595 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2596
2597 WARN_ON(*pte);
2598
2599 *pte = __pte;
2600
2601 return (dma_addr_t)address;
2602 }
2603
2604 /*
2605 * The generic unmapping function for on page in the DMA address space.
2606 */
2607 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2608 unsigned long address)
2609 {
2610 struct aperture_range *aperture;
2611 u64 *pte;
2612
2613 if (address >= dom->aperture_size)
2614 return;
2615
2616 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2617 if (!aperture)
2618 return;
2619
2620 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2621 if (!pte)
2622 return;
2623
2624 pte += PM_LEVEL_INDEX(0, address);
2625
2626 WARN_ON(!*pte);
2627
2628 *pte = 0ULL;
2629 }
2630
2631 /*
2632 * This function contains common code for mapping of a physically
2633 * contiguous memory region into DMA address space. It is used by all
2634 * mapping functions provided with this IOMMU driver.
2635 * Must be called with the domain lock held.
2636 */
2637 static dma_addr_t __map_single(struct device *dev,
2638 struct dma_ops_domain *dma_dom,
2639 phys_addr_t paddr,
2640 size_t size,
2641 int dir,
2642 bool align,
2643 u64 dma_mask)
2644 {
2645 dma_addr_t offset = paddr & ~PAGE_MASK;
2646 dma_addr_t address, start, ret;
2647 unsigned int pages;
2648 unsigned long align_mask = 0;
2649 int i;
2650
2651 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2652 paddr &= PAGE_MASK;
2653
2654 INC_STATS_COUNTER(total_map_requests);
2655
2656 if (pages > 1)
2657 INC_STATS_COUNTER(cross_page);
2658
2659 if (align)
2660 align_mask = (1UL << get_order(size)) - 1;
2661
2662 retry:
2663 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2664 dma_mask);
2665 if (unlikely(address == DMA_ERROR_CODE)) {
2666 /*
2667 * setting next_address here will let the address
2668 * allocator only scan the new allocated range in the
2669 * first run. This is a small optimization.
2670 */
2671 dma_dom->next_address = dma_dom->aperture_size;
2672
2673 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2674 goto out;
2675
2676 /*
2677 * aperture was successfully enlarged by 128 MB, try
2678 * allocation again
2679 */
2680 goto retry;
2681 }
2682
2683 start = address;
2684 for (i = 0; i < pages; ++i) {
2685 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2686 if (ret == DMA_ERROR_CODE)
2687 goto out_unmap;
2688
2689 paddr += PAGE_SIZE;
2690 start += PAGE_SIZE;
2691 }
2692 address += offset;
2693
2694 ADD_STATS_COUNTER(alloced_io_mem, size);
2695
2696 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2697 domain_flush_tlb(&dma_dom->domain);
2698 dma_dom->need_flush = false;
2699 } else if (unlikely(amd_iommu_np_cache))
2700 domain_flush_pages(&dma_dom->domain, address, size);
2701
2702 out:
2703 return address;
2704
2705 out_unmap:
2706
2707 for (--i; i >= 0; --i) {
2708 start -= PAGE_SIZE;
2709 dma_ops_domain_unmap(dma_dom, start);
2710 }
2711
2712 dma_ops_free_addresses(dma_dom, address, pages);
2713
2714 return DMA_ERROR_CODE;
2715 }
2716
2717 /*
2718 * Does the reverse of the __map_single function. Must be called with
2719 * the domain lock held too
2720 */
2721 static void __unmap_single(struct dma_ops_domain *dma_dom,
2722 dma_addr_t dma_addr,
2723 size_t size,
2724 int dir)
2725 {
2726 dma_addr_t flush_addr;
2727 dma_addr_t i, start;
2728 unsigned int pages;
2729
2730 if ((dma_addr == DMA_ERROR_CODE) ||
2731 (dma_addr + size > dma_dom->aperture_size))
2732 return;
2733
2734 flush_addr = dma_addr;
2735 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2736 dma_addr &= PAGE_MASK;
2737 start = dma_addr;
2738
2739 for (i = 0; i < pages; ++i) {
2740 dma_ops_domain_unmap(dma_dom, start);
2741 start += PAGE_SIZE;
2742 }
2743
2744 SUB_STATS_COUNTER(alloced_io_mem, size);
2745
2746 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2747
2748 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2749 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2750 dma_dom->need_flush = false;
2751 }
2752 }
2753
2754 /*
2755 * The exported map_single function for dma_ops.
2756 */
2757 static dma_addr_t map_page(struct device *dev, struct page *page,
2758 unsigned long offset, size_t size,
2759 enum dma_data_direction dir,
2760 struct dma_attrs *attrs)
2761 {
2762 unsigned long flags;
2763 struct protection_domain *domain;
2764 dma_addr_t addr;
2765 u64 dma_mask;
2766 phys_addr_t paddr = page_to_phys(page) + offset;
2767
2768 INC_STATS_COUNTER(cnt_map_single);
2769
2770 domain = get_domain(dev);
2771 if (PTR_ERR(domain) == -EINVAL)
2772 return (dma_addr_t)paddr;
2773 else if (IS_ERR(domain))
2774 return DMA_ERROR_CODE;
2775
2776 dma_mask = *dev->dma_mask;
2777
2778 spin_lock_irqsave(&domain->lock, flags);
2779
2780 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2781 dma_mask);
2782 if (addr == DMA_ERROR_CODE)
2783 goto out;
2784
2785 domain_flush_complete(domain);
2786
2787 out:
2788 spin_unlock_irqrestore(&domain->lock, flags);
2789
2790 return addr;
2791 }
2792
2793 /*
2794 * The exported unmap_single function for dma_ops.
2795 */
2796 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2797 enum dma_data_direction dir, struct dma_attrs *attrs)
2798 {
2799 unsigned long flags;
2800 struct protection_domain *domain;
2801
2802 INC_STATS_COUNTER(cnt_unmap_single);
2803
2804 domain = get_domain(dev);
2805 if (IS_ERR(domain))
2806 return;
2807
2808 spin_lock_irqsave(&domain->lock, flags);
2809
2810 __unmap_single(domain->priv, dma_addr, size, dir);
2811
2812 domain_flush_complete(domain);
2813
2814 spin_unlock_irqrestore(&domain->lock, flags);
2815 }
2816
2817 /*
2818 * The exported map_sg function for dma_ops (handles scatter-gather
2819 * lists).
2820 */
2821 static int map_sg(struct device *dev, struct scatterlist *sglist,
2822 int nelems, enum dma_data_direction dir,
2823 struct dma_attrs *attrs)
2824 {
2825 unsigned long flags;
2826 struct protection_domain *domain;
2827 int i;
2828 struct scatterlist *s;
2829 phys_addr_t paddr;
2830 int mapped_elems = 0;
2831 u64 dma_mask;
2832
2833 INC_STATS_COUNTER(cnt_map_sg);
2834
2835 domain = get_domain(dev);
2836 if (IS_ERR(domain))
2837 return 0;
2838
2839 dma_mask = *dev->dma_mask;
2840
2841 spin_lock_irqsave(&domain->lock, flags);
2842
2843 for_each_sg(sglist, s, nelems, i) {
2844 paddr = sg_phys(s);
2845
2846 s->dma_address = __map_single(dev, domain->priv,
2847 paddr, s->length, dir, false,
2848 dma_mask);
2849
2850 if (s->dma_address) {
2851 s->dma_length = s->length;
2852 mapped_elems++;
2853 } else
2854 goto unmap;
2855 }
2856
2857 domain_flush_complete(domain);
2858
2859 out:
2860 spin_unlock_irqrestore(&domain->lock, flags);
2861
2862 return mapped_elems;
2863 unmap:
2864 for_each_sg(sglist, s, mapped_elems, i) {
2865 if (s->dma_address)
2866 __unmap_single(domain->priv, s->dma_address,
2867 s->dma_length, dir);
2868 s->dma_address = s->dma_length = 0;
2869 }
2870
2871 mapped_elems = 0;
2872
2873 goto out;
2874 }
2875
2876 /*
2877 * The exported map_sg function for dma_ops (handles scatter-gather
2878 * lists).
2879 */
2880 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2881 int nelems, enum dma_data_direction dir,
2882 struct dma_attrs *attrs)
2883 {
2884 unsigned long flags;
2885 struct protection_domain *domain;
2886 struct scatterlist *s;
2887 int i;
2888
2889 INC_STATS_COUNTER(cnt_unmap_sg);
2890
2891 domain = get_domain(dev);
2892 if (IS_ERR(domain))
2893 return;
2894
2895 spin_lock_irqsave(&domain->lock, flags);
2896
2897 for_each_sg(sglist, s, nelems, i) {
2898 __unmap_single(domain->priv, s->dma_address,
2899 s->dma_length, dir);
2900 s->dma_address = s->dma_length = 0;
2901 }
2902
2903 domain_flush_complete(domain);
2904
2905 spin_unlock_irqrestore(&domain->lock, flags);
2906 }
2907
2908 /*
2909 * The exported alloc_coherent function for dma_ops.
2910 */
2911 static void *alloc_coherent(struct device *dev, size_t size,
2912 dma_addr_t *dma_addr, gfp_t flag,
2913 struct dma_attrs *attrs)
2914 {
2915 u64 dma_mask = dev->coherent_dma_mask;
2916 struct protection_domain *domain;
2917 unsigned long flags;
2918 struct page *page;
2919
2920 INC_STATS_COUNTER(cnt_alloc_coherent);
2921
2922 domain = get_domain(dev);
2923 if (PTR_ERR(domain) == -EINVAL) {
2924 page = alloc_pages(flag, get_order(size));
2925 *dma_addr = page_to_phys(page);
2926 return page_address(page);
2927 } else if (IS_ERR(domain))
2928 return NULL;
2929
2930 size = PAGE_ALIGN(size);
2931 dma_mask = dev->coherent_dma_mask;
2932 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2933
2934 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2935 if (!page) {
2936 if (!(flag & __GFP_WAIT))
2937 return NULL;
2938
2939 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2940 get_order(size));
2941 if (!page)
2942 return NULL;
2943 }
2944
2945 if (!dma_mask)
2946 dma_mask = *dev->dma_mask;
2947
2948 spin_lock_irqsave(&domain->lock, flags);
2949
2950 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2951 size, DMA_BIDIRECTIONAL, true, dma_mask);
2952
2953 if (*dma_addr == DMA_ERROR_CODE) {
2954 spin_unlock_irqrestore(&domain->lock, flags);
2955 goto out_free;
2956 }
2957
2958 domain_flush_complete(domain);
2959
2960 spin_unlock_irqrestore(&domain->lock, flags);
2961
2962 return page_address(page);
2963
2964 out_free:
2965
2966 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2967 __free_pages(page, get_order(size));
2968
2969 return NULL;
2970 }
2971
2972 /*
2973 * The exported free_coherent function for dma_ops.
2974 */
2975 static void free_coherent(struct device *dev, size_t size,
2976 void *virt_addr, dma_addr_t dma_addr,
2977 struct dma_attrs *attrs)
2978 {
2979 struct protection_domain *domain;
2980 unsigned long flags;
2981 struct page *page;
2982
2983 INC_STATS_COUNTER(cnt_free_coherent);
2984
2985 page = virt_to_page(virt_addr);
2986 size = PAGE_ALIGN(size);
2987
2988 domain = get_domain(dev);
2989 if (IS_ERR(domain))
2990 goto free_mem;
2991
2992 spin_lock_irqsave(&domain->lock, flags);
2993
2994 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2995
2996 domain_flush_complete(domain);
2997
2998 spin_unlock_irqrestore(&domain->lock, flags);
2999
3000 free_mem:
3001 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
3002 __free_pages(page, get_order(size));
3003 }
3004
3005 /*
3006 * This function is called by the DMA layer to find out if we can handle a
3007 * particular device. It is part of the dma_ops.
3008 */
3009 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3010 {
3011 return check_device(dev);
3012 }
3013
3014 /*
3015 * The function for pre-allocating protection domains.
3016 *
3017 * If the driver core informs the DMA layer if a driver grabs a device
3018 * we don't need to preallocate the protection domains anymore.
3019 * For now we have to.
3020 */
3021 static void __init prealloc_protection_domains(void)
3022 {
3023 struct iommu_dev_data *dev_data;
3024 struct dma_ops_domain *dma_dom;
3025 struct pci_dev *dev = NULL;
3026 u16 devid;
3027
3028 for_each_pci_dev(dev) {
3029
3030 /* Do we handle this device? */
3031 if (!check_device(&dev->dev))
3032 continue;
3033
3034 dev_data = get_dev_data(&dev->dev);
3035 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3036 /* Make sure passthrough domain is allocated */
3037 alloc_passthrough_domain();
3038 dev_data->passthrough = true;
3039 attach_device(&dev->dev, pt_domain);
3040 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3041 dev_name(&dev->dev));
3042 }
3043
3044 /* Is there already any domain for it? */
3045 if (domain_for_device(&dev->dev))
3046 continue;
3047
3048 devid = get_device_id(&dev->dev);
3049
3050 dma_dom = dma_ops_domain_alloc();
3051 if (!dma_dom)
3052 continue;
3053 init_unity_mappings_for_device(dma_dom, devid);
3054 dma_dom->target_dev = devid;
3055
3056 attach_device(&dev->dev, &dma_dom->domain);
3057
3058 list_add_tail(&dma_dom->list, &iommu_pd_list);
3059 }
3060 }
3061
3062 static struct dma_map_ops amd_iommu_dma_ops = {
3063 .alloc = alloc_coherent,
3064 .free = free_coherent,
3065 .map_page = map_page,
3066 .unmap_page = unmap_page,
3067 .map_sg = map_sg,
3068 .unmap_sg = unmap_sg,
3069 .dma_supported = amd_iommu_dma_supported,
3070 };
3071
3072 static unsigned device_dma_ops_init(void)
3073 {
3074 struct iommu_dev_data *dev_data;
3075 struct pci_dev *pdev = NULL;
3076 unsigned unhandled = 0;
3077
3078 for_each_pci_dev(pdev) {
3079 if (!check_device(&pdev->dev)) {
3080
3081 iommu_ignore_device(&pdev->dev);
3082
3083 unhandled += 1;
3084 continue;
3085 }
3086
3087 dev_data = get_dev_data(&pdev->dev);
3088
3089 if (!dev_data->passthrough)
3090 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3091 else
3092 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3093 }
3094
3095 return unhandled;
3096 }
3097
3098 /*
3099 * The function which clues the AMD IOMMU driver into dma_ops.
3100 */
3101
3102 void __init amd_iommu_init_api(void)
3103 {
3104 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3105 }
3106
3107 int __init amd_iommu_init_dma_ops(void)
3108 {
3109 struct amd_iommu *iommu;
3110 int ret, unhandled;
3111
3112 /*
3113 * first allocate a default protection domain for every IOMMU we
3114 * found in the system. Devices not assigned to any other
3115 * protection domain will be assigned to the default one.
3116 */
3117 for_each_iommu(iommu) {
3118 iommu->default_dom = dma_ops_domain_alloc();
3119 if (iommu->default_dom == NULL)
3120 return -ENOMEM;
3121 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3122 ret = iommu_init_unity_mappings(iommu);
3123 if (ret)
3124 goto free_domains;
3125 }
3126
3127 /*
3128 * Pre-allocate the protection domains for each device.
3129 */
3130 prealloc_protection_domains();
3131
3132 iommu_detected = 1;
3133 swiotlb = 0;
3134
3135 /* Make the driver finally visible to the drivers */
3136 unhandled = device_dma_ops_init();
3137 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3138 /* There are unhandled devices - initialize swiotlb for them */
3139 swiotlb = 1;
3140 }
3141
3142 amd_iommu_stats_init();
3143
3144 if (amd_iommu_unmap_flush)
3145 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3146 else
3147 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3148
3149 return 0;
3150
3151 free_domains:
3152
3153 for_each_iommu(iommu) {
3154 dma_ops_domain_free(iommu->default_dom);
3155 }
3156
3157 return ret;
3158 }
3159
3160 /*****************************************************************************
3161 *
3162 * The following functions belong to the exported interface of AMD IOMMU
3163 *
3164 * This interface allows access to lower level functions of the IOMMU
3165 * like protection domain handling and assignement of devices to domains
3166 * which is not possible with the dma_ops interface.
3167 *
3168 *****************************************************************************/
3169
3170 static void cleanup_domain(struct protection_domain *domain)
3171 {
3172 struct iommu_dev_data *entry;
3173 unsigned long flags;
3174
3175 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3176
3177 while (!list_empty(&domain->dev_list)) {
3178 entry = list_first_entry(&domain->dev_list,
3179 struct iommu_dev_data, list);
3180 __detach_device(entry);
3181 }
3182
3183 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3184 }
3185
3186 static void protection_domain_free(struct protection_domain *domain)
3187 {
3188 if (!domain)
3189 return;
3190
3191 del_domain_from_list(domain);
3192
3193 if (domain->id)
3194 domain_id_free(domain->id);
3195
3196 kfree(domain);
3197 }
3198
3199 static struct protection_domain *protection_domain_alloc(void)
3200 {
3201 struct protection_domain *domain;
3202
3203 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3204 if (!domain)
3205 return NULL;
3206
3207 spin_lock_init(&domain->lock);
3208 mutex_init(&domain->api_lock);
3209 domain->id = domain_id_alloc();
3210 if (!domain->id)
3211 goto out_err;
3212 INIT_LIST_HEAD(&domain->dev_list);
3213
3214 add_domain_to_list(domain);
3215
3216 return domain;
3217
3218 out_err:
3219 kfree(domain);
3220
3221 return NULL;
3222 }
3223
3224 static int __init alloc_passthrough_domain(void)
3225 {
3226 if (pt_domain != NULL)
3227 return 0;
3228
3229 /* allocate passthrough domain */
3230 pt_domain = protection_domain_alloc();
3231 if (!pt_domain)
3232 return -ENOMEM;
3233
3234 pt_domain->mode = PAGE_MODE_NONE;
3235
3236 return 0;
3237 }
3238
3239 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
3240 {
3241 struct protection_domain *pdomain;
3242
3243 /* We only support unmanaged domains for now */
3244 if (type != IOMMU_DOMAIN_UNMANAGED)
3245 return NULL;
3246
3247 pdomain = protection_domain_alloc();
3248 if (!pdomain)
3249 goto out_free;
3250
3251 pdomain->mode = PAGE_MODE_3_LEVEL;
3252 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3253 if (!pdomain->pt_root)
3254 goto out_free;
3255
3256 pdomain->domain.geometry.aperture_start = 0;
3257 pdomain->domain.geometry.aperture_end = ~0ULL;
3258 pdomain->domain.geometry.force_aperture = true;
3259
3260 return &pdomain->domain;
3261
3262 out_free:
3263 protection_domain_free(pdomain);
3264
3265 return NULL;
3266 }
3267
3268 static void amd_iommu_domain_free(struct iommu_domain *dom)
3269 {
3270 struct protection_domain *domain;
3271
3272 if (!dom)
3273 return;
3274
3275 domain = to_pdomain(dom);
3276
3277 if (domain->dev_cnt > 0)
3278 cleanup_domain(domain);
3279
3280 BUG_ON(domain->dev_cnt != 0);
3281
3282 if (domain->mode != PAGE_MODE_NONE)
3283 free_pagetable(domain);
3284
3285 if (domain->flags & PD_IOMMUV2_MASK)
3286 free_gcr3_table(domain);
3287
3288 protection_domain_free(domain);
3289 }
3290
3291 static void amd_iommu_detach_device(struct iommu_domain *dom,
3292 struct device *dev)
3293 {
3294 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3295 struct amd_iommu *iommu;
3296 u16 devid;
3297
3298 if (!check_device(dev))
3299 return;
3300
3301 devid = get_device_id(dev);
3302
3303 if (dev_data->domain != NULL)
3304 detach_device(dev);
3305
3306 iommu = amd_iommu_rlookup_table[devid];
3307 if (!iommu)
3308 return;
3309
3310 iommu_completion_wait(iommu);
3311 }
3312
3313 static int amd_iommu_attach_device(struct iommu_domain *dom,
3314 struct device *dev)
3315 {
3316 struct protection_domain *domain = to_pdomain(dom);
3317 struct iommu_dev_data *dev_data;
3318 struct amd_iommu *iommu;
3319 int ret;
3320
3321 if (!check_device(dev))
3322 return -EINVAL;
3323
3324 dev_data = dev->archdata.iommu;
3325
3326 iommu = amd_iommu_rlookup_table[dev_data->devid];
3327 if (!iommu)
3328 return -EINVAL;
3329
3330 if (dev_data->domain)
3331 detach_device(dev);
3332
3333 ret = attach_device(dev, domain);
3334
3335 iommu_completion_wait(iommu);
3336
3337 return ret;
3338 }
3339
3340 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3341 phys_addr_t paddr, size_t page_size, int iommu_prot)
3342 {
3343 struct protection_domain *domain = to_pdomain(dom);
3344 int prot = 0;
3345 int ret;
3346
3347 if (domain->mode == PAGE_MODE_NONE)
3348 return -EINVAL;
3349
3350 if (iommu_prot & IOMMU_READ)
3351 prot |= IOMMU_PROT_IR;
3352 if (iommu_prot & IOMMU_WRITE)
3353 prot |= IOMMU_PROT_IW;
3354
3355 mutex_lock(&domain->api_lock);
3356 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3357 mutex_unlock(&domain->api_lock);
3358
3359 return ret;
3360 }
3361
3362 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3363 size_t page_size)
3364 {
3365 struct protection_domain *domain = to_pdomain(dom);
3366 size_t unmap_size;
3367
3368 if (domain->mode == PAGE_MODE_NONE)
3369 return -EINVAL;
3370
3371 mutex_lock(&domain->api_lock);
3372 unmap_size = iommu_unmap_page(domain, iova, page_size);
3373 mutex_unlock(&domain->api_lock);
3374
3375 domain_flush_tlb_pde(domain);
3376
3377 return unmap_size;
3378 }
3379
3380 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3381 dma_addr_t iova)
3382 {
3383 struct protection_domain *domain = to_pdomain(dom);
3384 unsigned long offset_mask, pte_pgsize;
3385 u64 *pte, __pte;
3386
3387 if (domain->mode == PAGE_MODE_NONE)
3388 return iova;
3389
3390 pte = fetch_pte(domain, iova, &pte_pgsize);
3391
3392 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3393 return 0;
3394
3395 offset_mask = pte_pgsize - 1;
3396 __pte = *pte & PM_ADDR_MASK;
3397
3398 return (__pte & ~offset_mask) | (iova & offset_mask);
3399 }
3400
3401 static bool amd_iommu_capable(enum iommu_cap cap)
3402 {
3403 switch (cap) {
3404 case IOMMU_CAP_CACHE_COHERENCY:
3405 return true;
3406 case IOMMU_CAP_INTR_REMAP:
3407 return (irq_remapping_enabled == 1);
3408 case IOMMU_CAP_NOEXEC:
3409 return false;
3410 }
3411
3412 return false;
3413 }
3414
3415 static const struct iommu_ops amd_iommu_ops = {
3416 .capable = amd_iommu_capable,
3417 .domain_alloc = amd_iommu_domain_alloc,
3418 .domain_free = amd_iommu_domain_free,
3419 .attach_dev = amd_iommu_attach_device,
3420 .detach_dev = amd_iommu_detach_device,
3421 .map = amd_iommu_map,
3422 .unmap = amd_iommu_unmap,
3423 .map_sg = default_iommu_map_sg,
3424 .iova_to_phys = amd_iommu_iova_to_phys,
3425 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3426 };
3427
3428 /*****************************************************************************
3429 *
3430 * The next functions do a basic initialization of IOMMU for pass through
3431 * mode
3432 *
3433 * In passthrough mode the IOMMU is initialized and enabled but not used for
3434 * DMA-API translation.
3435 *
3436 *****************************************************************************/
3437
3438 int __init amd_iommu_init_passthrough(void)
3439 {
3440 struct iommu_dev_data *dev_data;
3441 struct pci_dev *dev = NULL;
3442 int ret;
3443
3444 ret = alloc_passthrough_domain();
3445 if (ret)
3446 return ret;
3447
3448 for_each_pci_dev(dev) {
3449 if (!check_device(&dev->dev))
3450 continue;
3451
3452 dev_data = get_dev_data(&dev->dev);
3453 dev_data->passthrough = true;
3454
3455 attach_device(&dev->dev, pt_domain);
3456 }
3457
3458 amd_iommu_stats_init();
3459
3460 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3461
3462 return 0;
3463 }
3464
3465 /* IOMMUv2 specific functions */
3466 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3467 {
3468 return atomic_notifier_chain_register(&ppr_notifier, nb);
3469 }
3470 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3471
3472 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3473 {
3474 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3475 }
3476 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3477
3478 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3479 {
3480 struct protection_domain *domain = to_pdomain(dom);
3481 unsigned long flags;
3482
3483 spin_lock_irqsave(&domain->lock, flags);
3484
3485 /* Update data structure */
3486 domain->mode = PAGE_MODE_NONE;
3487 domain->updated = true;
3488
3489 /* Make changes visible to IOMMUs */
3490 update_domain(domain);
3491
3492 /* Page-table is not visible to IOMMU anymore, so free it */
3493 free_pagetable(domain);
3494
3495 spin_unlock_irqrestore(&domain->lock, flags);
3496 }
3497 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3498
3499 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3500 {
3501 struct protection_domain *domain = to_pdomain(dom);
3502 unsigned long flags;
3503 int levels, ret;
3504
3505 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3506 return -EINVAL;
3507
3508 /* Number of GCR3 table levels required */
3509 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3510 levels += 1;
3511
3512 if (levels > amd_iommu_max_glx_val)
3513 return -EINVAL;
3514
3515 spin_lock_irqsave(&domain->lock, flags);
3516
3517 /*
3518 * Save us all sanity checks whether devices already in the
3519 * domain support IOMMUv2. Just force that the domain has no
3520 * devices attached when it is switched into IOMMUv2 mode.
3521 */
3522 ret = -EBUSY;
3523 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3524 goto out;
3525
3526 ret = -ENOMEM;
3527 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3528 if (domain->gcr3_tbl == NULL)
3529 goto out;
3530
3531 domain->glx = levels;
3532 domain->flags |= PD_IOMMUV2_MASK;
3533 domain->updated = true;
3534
3535 update_domain(domain);
3536
3537 ret = 0;
3538
3539 out:
3540 spin_unlock_irqrestore(&domain->lock, flags);
3541
3542 return ret;
3543 }
3544 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3545
3546 static int __flush_pasid(struct protection_domain *domain, int pasid,
3547 u64 address, bool size)
3548 {
3549 struct iommu_dev_data *dev_data;
3550 struct iommu_cmd cmd;
3551 int i, ret;
3552
3553 if (!(domain->flags & PD_IOMMUV2_MASK))
3554 return -EINVAL;
3555
3556 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3557
3558 /*
3559 * IOMMU TLB needs to be flushed before Device TLB to
3560 * prevent device TLB refill from IOMMU TLB
3561 */
3562 for (i = 0; i < amd_iommus_present; ++i) {
3563 if (domain->dev_iommu[i] == 0)
3564 continue;
3565
3566 ret = iommu_queue_command(amd_iommus[i], &cmd);
3567 if (ret != 0)
3568 goto out;
3569 }
3570
3571 /* Wait until IOMMU TLB flushes are complete */
3572 domain_flush_complete(domain);
3573
3574 /* Now flush device TLBs */
3575 list_for_each_entry(dev_data, &domain->dev_list, list) {
3576 struct amd_iommu *iommu;
3577 int qdep;
3578
3579 BUG_ON(!dev_data->ats.enabled);
3580
3581 qdep = dev_data->ats.qdep;
3582 iommu = amd_iommu_rlookup_table[dev_data->devid];
3583
3584 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3585 qdep, address, size);
3586
3587 ret = iommu_queue_command(iommu, &cmd);
3588 if (ret != 0)
3589 goto out;
3590 }
3591
3592 /* Wait until all device TLBs are flushed */
3593 domain_flush_complete(domain);
3594
3595 ret = 0;
3596
3597 out:
3598
3599 return ret;
3600 }
3601
3602 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3603 u64 address)
3604 {
3605 INC_STATS_COUNTER(invalidate_iotlb);
3606
3607 return __flush_pasid(domain, pasid, address, false);
3608 }
3609
3610 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3611 u64 address)
3612 {
3613 struct protection_domain *domain = to_pdomain(dom);
3614 unsigned long flags;
3615 int ret;
3616
3617 spin_lock_irqsave(&domain->lock, flags);
3618 ret = __amd_iommu_flush_page(domain, pasid, address);
3619 spin_unlock_irqrestore(&domain->lock, flags);
3620
3621 return ret;
3622 }
3623 EXPORT_SYMBOL(amd_iommu_flush_page);
3624
3625 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3626 {
3627 INC_STATS_COUNTER(invalidate_iotlb_all);
3628
3629 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3630 true);
3631 }
3632
3633 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3634 {
3635 struct protection_domain *domain = to_pdomain(dom);
3636 unsigned long flags;
3637 int ret;
3638
3639 spin_lock_irqsave(&domain->lock, flags);
3640 ret = __amd_iommu_flush_tlb(domain, pasid);
3641 spin_unlock_irqrestore(&domain->lock, flags);
3642
3643 return ret;
3644 }
3645 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3646
3647 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3648 {
3649 int index;
3650 u64 *pte;
3651
3652 while (true) {
3653
3654 index = (pasid >> (9 * level)) & 0x1ff;
3655 pte = &root[index];
3656
3657 if (level == 0)
3658 break;
3659
3660 if (!(*pte & GCR3_VALID)) {
3661 if (!alloc)
3662 return NULL;
3663
3664 root = (void *)get_zeroed_page(GFP_ATOMIC);
3665 if (root == NULL)
3666 return NULL;
3667
3668 *pte = __pa(root) | GCR3_VALID;
3669 }
3670
3671 root = __va(*pte & PAGE_MASK);
3672
3673 level -= 1;
3674 }
3675
3676 return pte;
3677 }
3678
3679 static int __set_gcr3(struct protection_domain *domain, int pasid,
3680 unsigned long cr3)
3681 {
3682 u64 *pte;
3683
3684 if (domain->mode != PAGE_MODE_NONE)
3685 return -EINVAL;
3686
3687 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3688 if (pte == NULL)
3689 return -ENOMEM;
3690
3691 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3692
3693 return __amd_iommu_flush_tlb(domain, pasid);
3694 }
3695
3696 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3697 {
3698 u64 *pte;
3699
3700 if (domain->mode != PAGE_MODE_NONE)
3701 return -EINVAL;
3702
3703 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3704 if (pte == NULL)
3705 return 0;
3706
3707 *pte = 0;
3708
3709 return __amd_iommu_flush_tlb(domain, pasid);
3710 }
3711
3712 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3713 unsigned long cr3)
3714 {
3715 struct protection_domain *domain = to_pdomain(dom);
3716 unsigned long flags;
3717 int ret;
3718
3719 spin_lock_irqsave(&domain->lock, flags);
3720 ret = __set_gcr3(domain, pasid, cr3);
3721 spin_unlock_irqrestore(&domain->lock, flags);
3722
3723 return ret;
3724 }
3725 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3726
3727 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3728 {
3729 struct protection_domain *domain = to_pdomain(dom);
3730 unsigned long flags;
3731 int ret;
3732
3733 spin_lock_irqsave(&domain->lock, flags);
3734 ret = __clear_gcr3(domain, pasid);
3735 spin_unlock_irqrestore(&domain->lock, flags);
3736
3737 return ret;
3738 }
3739 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3740
3741 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3742 int status, int tag)
3743 {
3744 struct iommu_dev_data *dev_data;
3745 struct amd_iommu *iommu;
3746 struct iommu_cmd cmd;
3747
3748 INC_STATS_COUNTER(complete_ppr);
3749
3750 dev_data = get_dev_data(&pdev->dev);
3751 iommu = amd_iommu_rlookup_table[dev_data->devid];
3752
3753 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3754 tag, dev_data->pri_tlp);
3755
3756 return iommu_queue_command(iommu, &cmd);
3757 }
3758 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3759
3760 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3761 {
3762 struct protection_domain *pdomain;
3763
3764 pdomain = get_domain(&pdev->dev);
3765 if (IS_ERR(pdomain))
3766 return NULL;
3767
3768 /* Only return IOMMUv2 domains */
3769 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3770 return NULL;
3771
3772 return &pdomain->domain;
3773 }
3774 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3775
3776 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3777 {
3778 struct iommu_dev_data *dev_data;
3779
3780 if (!amd_iommu_v2_supported())
3781 return;
3782
3783 dev_data = get_dev_data(&pdev->dev);
3784 dev_data->errata |= (1 << erratum);
3785 }
3786 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3787
3788 int amd_iommu_device_info(struct pci_dev *pdev,
3789 struct amd_iommu_device_info *info)
3790 {
3791 int max_pasids;
3792 int pos;
3793
3794 if (pdev == NULL || info == NULL)
3795 return -EINVAL;
3796
3797 if (!amd_iommu_v2_supported())
3798 return -EINVAL;
3799
3800 memset(info, 0, sizeof(*info));
3801
3802 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3803 if (pos)
3804 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3805
3806 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3807 if (pos)
3808 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3809
3810 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3811 if (pos) {
3812 int features;
3813
3814 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3815 max_pasids = min(max_pasids, (1 << 20));
3816
3817 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3818 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3819
3820 features = pci_pasid_features(pdev);
3821 if (features & PCI_PASID_CAP_EXEC)
3822 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3823 if (features & PCI_PASID_CAP_PRIV)
3824 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3825 }
3826
3827 return 0;
3828 }
3829 EXPORT_SYMBOL(amd_iommu_device_info);
3830
3831 #ifdef CONFIG_IRQ_REMAP
3832
3833 /*****************************************************************************
3834 *
3835 * Interrupt Remapping Implementation
3836 *
3837 *****************************************************************************/
3838
3839 union irte {
3840 u32 val;
3841 struct {
3842 u32 valid : 1,
3843 no_fault : 1,
3844 int_type : 3,
3845 rq_eoi : 1,
3846 dm : 1,
3847 rsvd_1 : 1,
3848 destination : 8,
3849 vector : 8,
3850 rsvd_2 : 8;
3851 } fields;
3852 };
3853
3854 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3855 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3856 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3857 #define DTE_IRQ_REMAP_ENABLE 1ULL
3858
3859 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3860 {
3861 u64 dte;
3862
3863 dte = amd_iommu_dev_table[devid].data[2];
3864 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3865 dte |= virt_to_phys(table->table);
3866 dte |= DTE_IRQ_REMAP_INTCTL;
3867 dte |= DTE_IRQ_TABLE_LEN;
3868 dte |= DTE_IRQ_REMAP_ENABLE;
3869
3870 amd_iommu_dev_table[devid].data[2] = dte;
3871 }
3872
3873 #define IRTE_ALLOCATED (~1U)
3874
3875 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3876 {
3877 struct irq_remap_table *table = NULL;
3878 struct amd_iommu *iommu;
3879 unsigned long flags;
3880 u16 alias;
3881
3882 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3883
3884 iommu = amd_iommu_rlookup_table[devid];
3885 if (!iommu)
3886 goto out_unlock;
3887
3888 table = irq_lookup_table[devid];
3889 if (table)
3890 goto out;
3891
3892 alias = amd_iommu_alias_table[devid];
3893 table = irq_lookup_table[alias];
3894 if (table) {
3895 irq_lookup_table[devid] = table;
3896 set_dte_irq_entry(devid, table);
3897 iommu_flush_dte(iommu, devid);
3898 goto out;
3899 }
3900
3901 /* Nothing there yet, allocate new irq remapping table */
3902 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3903 if (!table)
3904 goto out;
3905
3906 /* Initialize table spin-lock */
3907 spin_lock_init(&table->lock);
3908
3909 if (ioapic)
3910 /* Keep the first 32 indexes free for IOAPIC interrupts */
3911 table->min_index = 32;
3912
3913 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3914 if (!table->table) {
3915 kfree(table);
3916 table = NULL;
3917 goto out;
3918 }
3919
3920 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3921
3922 if (ioapic) {
3923 int i;
3924
3925 for (i = 0; i < 32; ++i)
3926 table->table[i] = IRTE_ALLOCATED;
3927 }
3928
3929 irq_lookup_table[devid] = table;
3930 set_dte_irq_entry(devid, table);
3931 iommu_flush_dte(iommu, devid);
3932 if (devid != alias) {
3933 irq_lookup_table[alias] = table;
3934 set_dte_irq_entry(alias, table);
3935 iommu_flush_dte(iommu, alias);
3936 }
3937
3938 out:
3939 iommu_completion_wait(iommu);
3940
3941 out_unlock:
3942 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3943
3944 return table;
3945 }
3946
3947 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3948 {
3949 struct irq_remap_table *table;
3950 unsigned long flags;
3951 int index, c;
3952
3953 table = get_irq_table(devid, false);
3954 if (!table)
3955 return -ENODEV;
3956
3957 spin_lock_irqsave(&table->lock, flags);
3958
3959 /* Scan table for free entries */
3960 for (c = 0, index = table->min_index;
3961 index < MAX_IRQS_PER_TABLE;
3962 ++index) {
3963 if (table->table[index] == 0)
3964 c += 1;
3965 else
3966 c = 0;
3967
3968 if (c == count) {
3969 struct irq_2_irte *irte_info;
3970
3971 for (; c != 0; --c)
3972 table->table[index - c + 1] = IRTE_ALLOCATED;
3973
3974 index -= count - 1;
3975
3976 cfg->remapped = 1;
3977 irte_info = &cfg->irq_2_irte;
3978 irte_info->devid = devid;
3979 irte_info->index = index;
3980
3981 goto out;
3982 }
3983 }
3984
3985 index = -ENOSPC;
3986
3987 out:
3988 spin_unlock_irqrestore(&table->lock, flags);
3989
3990 return index;
3991 }
3992
3993 static int get_irte(u16 devid, int index, union irte *irte)
3994 {
3995 struct irq_remap_table *table;
3996 unsigned long flags;
3997
3998 table = get_irq_table(devid, false);
3999 if (!table)
4000 return -ENOMEM;
4001
4002 spin_lock_irqsave(&table->lock, flags);
4003 irte->val = table->table[index];
4004 spin_unlock_irqrestore(&table->lock, flags);
4005
4006 return 0;
4007 }
4008
4009 static int modify_irte(u16 devid, int index, union irte irte)
4010 {
4011 struct irq_remap_table *table;
4012 struct amd_iommu *iommu;
4013 unsigned long flags;
4014
4015 iommu = amd_iommu_rlookup_table[devid];
4016 if (iommu == NULL)
4017 return -EINVAL;
4018
4019 table = get_irq_table(devid, false);
4020 if (!table)
4021 return -ENOMEM;
4022
4023 spin_lock_irqsave(&table->lock, flags);
4024 table->table[index] = irte.val;
4025 spin_unlock_irqrestore(&table->lock, flags);
4026
4027 iommu_flush_irt(iommu, devid);
4028 iommu_completion_wait(iommu);
4029
4030 return 0;
4031 }
4032
4033 static void free_irte(u16 devid, int index)
4034 {
4035 struct irq_remap_table *table;
4036 struct amd_iommu *iommu;
4037 unsigned long flags;
4038
4039 iommu = amd_iommu_rlookup_table[devid];
4040 if (iommu == NULL)
4041 return;
4042
4043 table = get_irq_table(devid, false);
4044 if (!table)
4045 return;
4046
4047 spin_lock_irqsave(&table->lock, flags);
4048 table->table[index] = 0;
4049 spin_unlock_irqrestore(&table->lock, flags);
4050
4051 iommu_flush_irt(iommu, devid);
4052 iommu_completion_wait(iommu);
4053 }
4054
4055 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4056 unsigned int destination, int vector,
4057 struct io_apic_irq_attr *attr)
4058 {
4059 struct irq_remap_table *table;
4060 struct irq_2_irte *irte_info;
4061 struct irq_cfg *cfg;
4062 union irte irte;
4063 int ioapic_id;
4064 int index;
4065 int devid;
4066 int ret;
4067
4068 cfg = irq_cfg(irq);
4069 if (!cfg)
4070 return -EINVAL;
4071
4072 irte_info = &cfg->irq_2_irte;
4073 ioapic_id = mpc_ioapic_id(attr->ioapic);
4074 devid = get_ioapic_devid(ioapic_id);
4075
4076 if (devid < 0)
4077 return devid;
4078
4079 table = get_irq_table(devid, true);
4080 if (table == NULL)
4081 return -ENOMEM;
4082
4083 index = attr->ioapic_pin;
4084
4085 /* Setup IRQ remapping info */
4086 cfg->remapped = 1;
4087 irte_info->devid = devid;
4088 irte_info->index = index;
4089
4090 /* Setup IRTE for IOMMU */
4091 irte.val = 0;
4092 irte.fields.vector = vector;
4093 irte.fields.int_type = apic->irq_delivery_mode;
4094 irte.fields.destination = destination;
4095 irte.fields.dm = apic->irq_dest_mode;
4096 irte.fields.valid = 1;
4097
4098 ret = modify_irte(devid, index, irte);
4099 if (ret)
4100 return ret;
4101
4102 /* Setup IOAPIC entry */
4103 memset(entry, 0, sizeof(*entry));
4104
4105 entry->vector = index;
4106 entry->mask = 0;
4107 entry->trigger = attr->trigger;
4108 entry->polarity = attr->polarity;
4109
4110 /*
4111 * Mask level triggered irqs.
4112 */
4113 if (attr->trigger)
4114 entry->mask = 1;
4115
4116 return 0;
4117 }
4118
4119 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4120 bool force)
4121 {
4122 struct irq_2_irte *irte_info;
4123 unsigned int dest, irq;
4124 struct irq_cfg *cfg;
4125 union irte irte;
4126 int err;
4127
4128 if (!config_enabled(CONFIG_SMP))
4129 return -1;
4130
4131 cfg = irqd_cfg(data);
4132 irq = data->irq;
4133 irte_info = &cfg->irq_2_irte;
4134
4135 if (!cpumask_intersects(mask, cpu_online_mask))
4136 return -EINVAL;
4137
4138 if (get_irte(irte_info->devid, irte_info->index, &irte))
4139 return -EBUSY;
4140
4141 if (assign_irq_vector(irq, cfg, mask))
4142 return -EBUSY;
4143
4144 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4145 if (err) {
4146 if (assign_irq_vector(irq, cfg, data->affinity))
4147 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4148 return err;
4149 }
4150
4151 irte.fields.vector = cfg->vector;
4152 irte.fields.destination = dest;
4153
4154 modify_irte(irte_info->devid, irte_info->index, irte);
4155
4156 if (cfg->move_in_progress)
4157 send_cleanup_vector(cfg);
4158
4159 cpumask_copy(data->affinity, mask);
4160
4161 return 0;
4162 }
4163
4164 static int free_irq(int irq)
4165 {
4166 struct irq_2_irte *irte_info;
4167 struct irq_cfg *cfg;
4168
4169 cfg = irq_cfg(irq);
4170 if (!cfg)
4171 return -EINVAL;
4172
4173 irte_info = &cfg->irq_2_irte;
4174
4175 free_irte(irte_info->devid, irte_info->index);
4176
4177 return 0;
4178 }
4179
4180 static void compose_msi_msg(struct pci_dev *pdev,
4181 unsigned int irq, unsigned int dest,
4182 struct msi_msg *msg, u8 hpet_id)
4183 {
4184 struct irq_2_irte *irte_info;
4185 struct irq_cfg *cfg;
4186 union irte irte;
4187
4188 cfg = irq_cfg(irq);
4189 if (!cfg)
4190 return;
4191
4192 irte_info = &cfg->irq_2_irte;
4193
4194 irte.val = 0;
4195 irte.fields.vector = cfg->vector;
4196 irte.fields.int_type = apic->irq_delivery_mode;
4197 irte.fields.destination = dest;
4198 irte.fields.dm = apic->irq_dest_mode;
4199 irte.fields.valid = 1;
4200
4201 modify_irte(irte_info->devid, irte_info->index, irte);
4202
4203 msg->address_hi = MSI_ADDR_BASE_HI;
4204 msg->address_lo = MSI_ADDR_BASE_LO;
4205 msg->data = irte_info->index;
4206 }
4207
4208 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4209 {
4210 struct irq_cfg *cfg;
4211 int index;
4212 u16 devid;
4213
4214 if (!pdev)
4215 return -EINVAL;
4216
4217 cfg = irq_cfg(irq);
4218 if (!cfg)
4219 return -EINVAL;
4220
4221 devid = get_device_id(&pdev->dev);
4222 index = alloc_irq_index(cfg, devid, nvec);
4223
4224 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4225 }
4226
4227 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4228 int index, int offset)
4229 {
4230 struct irq_2_irte *irte_info;
4231 struct irq_cfg *cfg;
4232 u16 devid;
4233
4234 if (!pdev)
4235 return -EINVAL;
4236
4237 cfg = irq_cfg(irq);
4238 if (!cfg)
4239 return -EINVAL;
4240
4241 if (index >= MAX_IRQS_PER_TABLE)
4242 return 0;
4243
4244 devid = get_device_id(&pdev->dev);
4245 irte_info = &cfg->irq_2_irte;
4246
4247 cfg->remapped = 1;
4248 irte_info->devid = devid;
4249 irte_info->index = index + offset;
4250
4251 return 0;
4252 }
4253
4254 static int alloc_hpet_msi(unsigned int irq, unsigned int id)
4255 {
4256 struct irq_2_irte *irte_info;
4257 struct irq_cfg *cfg;
4258 int index, devid;
4259
4260 cfg = irq_cfg(irq);
4261 if (!cfg)
4262 return -EINVAL;
4263
4264 irte_info = &cfg->irq_2_irte;
4265 devid = get_hpet_devid(id);
4266 if (devid < 0)
4267 return devid;
4268
4269 index = alloc_irq_index(cfg, devid, 1);
4270 if (index < 0)
4271 return index;
4272
4273 cfg->remapped = 1;
4274 irte_info->devid = devid;
4275 irte_info->index = index;
4276
4277 return 0;
4278 }
4279
4280 struct irq_remap_ops amd_iommu_irq_ops = {
4281 .prepare = amd_iommu_prepare,
4282 .enable = amd_iommu_enable,
4283 .disable = amd_iommu_disable,
4284 .reenable = amd_iommu_reenable,
4285 .enable_faulting = amd_iommu_enable_faulting,
4286 .setup_ioapic_entry = setup_ioapic_entry,
4287 .set_affinity = set_affinity,
4288 .free_irq = free_irq,
4289 .compose_msi_msg = compose_msi_msg,
4290 .msi_alloc_irq = msi_alloc_irq,
4291 .msi_setup_irq = msi_setup_irq,
4292 .alloc_hpet_msi = alloc_hpet_msi,
4293 };
4294 #endif
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