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iommu/amd: fix a crash in iova_magazine_free_pfns
[mirror_ubuntu-eoan-kernel.git] / drivers / iommu / amd_iommu.c
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
4 * Author: Joerg Roedel <jroedel@suse.de>
5 * Leo Duran <leo.duran@amd.com>
6 */
7
8 #define pr_fmt(fmt) "AMD-Vi: " fmt
9 #define dev_fmt(fmt) pr_fmt(fmt)
10
11 #include <linux/ratelimit.h>
12 #include <linux/pci.h>
13 #include <linux/acpi.h>
14 #include <linux/amba/bus.h>
15 #include <linux/platform_device.h>
16 #include <linux/pci-ats.h>
17 #include <linux/bitmap.h>
18 #include <linux/slab.h>
19 #include <linux/debugfs.h>
20 #include <linux/scatterlist.h>
21 #include <linux/dma-mapping.h>
22 #include <linux/dma-direct.h>
23 #include <linux/iommu-helper.h>
24 #include <linux/iommu.h>
25 #include <linux/delay.h>
26 #include <linux/amd-iommu.h>
27 #include <linux/notifier.h>
28 #include <linux/export.h>
29 #include <linux/irq.h>
30 #include <linux/msi.h>
31 #include <linux/dma-contiguous.h>
32 #include <linux/irqdomain.h>
33 #include <linux/percpu.h>
34 #include <linux/iova.h>
35 #include <asm/irq_remapping.h>
36 #include <asm/io_apic.h>
37 #include <asm/apic.h>
38 #include <asm/hw_irq.h>
39 #include <asm/msidef.h>
40 #include <asm/proto.h>
41 #include <asm/iommu.h>
42 #include <asm/gart.h>
43 #include <asm/dma.h>
44
45 #include "amd_iommu_proto.h"
46 #include "amd_iommu_types.h"
47 #include "irq_remapping.h"
48
49 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
50
51 #define LOOP_TIMEOUT 100000
52
53 /* IO virtual address start page frame number */
54 #define IOVA_START_PFN (1)
55 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
56
57 /* Reserved IOVA ranges */
58 #define MSI_RANGE_START (0xfee00000)
59 #define MSI_RANGE_END (0xfeefffff)
60 #define HT_RANGE_START (0xfd00000000ULL)
61 #define HT_RANGE_END (0xffffffffffULL)
62
63 /*
64 * This bitmap is used to advertise the page sizes our hardware support
65 * to the IOMMU core, which will then use this information to split
66 * physically contiguous memory regions it is mapping into page sizes
67 * that we support.
68 *
69 * 512GB Pages are not supported due to a hardware bug
70 */
71 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
72
73 static DEFINE_SPINLOCK(amd_iommu_devtable_lock);
74 static DEFINE_SPINLOCK(pd_bitmap_lock);
75
76 /* List of all available dev_data structures */
77 static LLIST_HEAD(dev_data_list);
78
79 LIST_HEAD(ioapic_map);
80 LIST_HEAD(hpet_map);
81 LIST_HEAD(acpihid_map);
82
83 /*
84 * Domain for untranslated devices - only allocated
85 * if iommu=pt passed on kernel cmd line.
86 */
87 const struct iommu_ops amd_iommu_ops;
88
89 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
90 int amd_iommu_max_glx_val = -1;
91
92 static const struct dma_map_ops amd_iommu_dma_ops;
93
94 /*
95 * general struct to manage commands send to an IOMMU
96 */
97 struct iommu_cmd {
98 u32 data[4];
99 };
100
101 struct kmem_cache *amd_iommu_irq_cache;
102
103 static void update_domain(struct protection_domain *domain);
104 static int protection_domain_init(struct protection_domain *domain);
105 static void detach_device(struct device *dev);
106 static void iova_domain_flush_tlb(struct iova_domain *iovad);
107
108 /*
109 * Data container for a dma_ops specific protection domain
110 */
111 struct dma_ops_domain {
112 /* generic protection domain information */
113 struct protection_domain domain;
114
115 /* IOVA RB-Tree */
116 struct iova_domain iovad;
117 };
118
119 static struct iova_domain reserved_iova_ranges;
120 static struct lock_class_key reserved_rbtree_key;
121
122 /****************************************************************************
123 *
124 * Helper functions
125 *
126 ****************************************************************************/
127
128 static inline int match_hid_uid(struct device *dev,
129 struct acpihid_map_entry *entry)
130 {
131 struct acpi_device *adev = ACPI_COMPANION(dev);
132 const char *hid, *uid;
133
134 if (!adev)
135 return -ENODEV;
136
137 hid = acpi_device_hid(adev);
138 uid = acpi_device_uid(adev);
139
140 if (!hid || !(*hid))
141 return -ENODEV;
142
143 if (!uid || !(*uid))
144 return strcmp(hid, entry->hid);
145
146 if (!(*entry->uid))
147 return strcmp(hid, entry->hid);
148
149 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
150 }
151
152 static inline u16 get_pci_device_id(struct device *dev)
153 {
154 struct pci_dev *pdev = to_pci_dev(dev);
155
156 return pci_dev_id(pdev);
157 }
158
159 static inline int get_acpihid_device_id(struct device *dev,
160 struct acpihid_map_entry **entry)
161 {
162 struct acpihid_map_entry *p;
163
164 list_for_each_entry(p, &acpihid_map, list) {
165 if (!match_hid_uid(dev, p)) {
166 if (entry)
167 *entry = p;
168 return p->devid;
169 }
170 }
171 return -EINVAL;
172 }
173
174 static inline int get_device_id(struct device *dev)
175 {
176 int devid;
177
178 if (dev_is_pci(dev))
179 devid = get_pci_device_id(dev);
180 else
181 devid = get_acpihid_device_id(dev, NULL);
182
183 return devid;
184 }
185
186 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
187 {
188 return container_of(dom, struct protection_domain, domain);
189 }
190
191 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
192 {
193 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
194 return container_of(domain, struct dma_ops_domain, domain);
195 }
196
197 static struct iommu_dev_data *alloc_dev_data(u16 devid)
198 {
199 struct iommu_dev_data *dev_data;
200
201 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
202 if (!dev_data)
203 return NULL;
204
205 dev_data->devid = devid;
206 ratelimit_default_init(&dev_data->rs);
207
208 llist_add(&dev_data->dev_data_list, &dev_data_list);
209 return dev_data;
210 }
211
212 static struct iommu_dev_data *search_dev_data(u16 devid)
213 {
214 struct iommu_dev_data *dev_data;
215 struct llist_node *node;
216
217 if (llist_empty(&dev_data_list))
218 return NULL;
219
220 node = dev_data_list.first;
221 llist_for_each_entry(dev_data, node, dev_data_list) {
222 if (dev_data->devid == devid)
223 return dev_data;
224 }
225
226 return NULL;
227 }
228
229 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
230 {
231 *(u16 *)data = alias;
232 return 0;
233 }
234
235 static u16 get_alias(struct device *dev)
236 {
237 struct pci_dev *pdev = to_pci_dev(dev);
238 u16 devid, ivrs_alias, pci_alias;
239
240 /* The callers make sure that get_device_id() does not fail here */
241 devid = get_device_id(dev);
242
243 /* For ACPI HID devices, we simply return the devid as such */
244 if (!dev_is_pci(dev))
245 return devid;
246
247 ivrs_alias = amd_iommu_alias_table[devid];
248
249 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
250
251 if (ivrs_alias == pci_alias)
252 return ivrs_alias;
253
254 /*
255 * DMA alias showdown
256 *
257 * The IVRS is fairly reliable in telling us about aliases, but it
258 * can't know about every screwy device. If we don't have an IVRS
259 * reported alias, use the PCI reported alias. In that case we may
260 * still need to initialize the rlookup and dev_table entries if the
261 * alias is to a non-existent device.
262 */
263 if (ivrs_alias == devid) {
264 if (!amd_iommu_rlookup_table[pci_alias]) {
265 amd_iommu_rlookup_table[pci_alias] =
266 amd_iommu_rlookup_table[devid];
267 memcpy(amd_iommu_dev_table[pci_alias].data,
268 amd_iommu_dev_table[devid].data,
269 sizeof(amd_iommu_dev_table[pci_alias].data));
270 }
271
272 return pci_alias;
273 }
274
275 pci_info(pdev, "Using IVRS reported alias %02x:%02x.%d "
276 "for device [%04x:%04x], kernel reported alias "
277 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
278 PCI_FUNC(ivrs_alias), pdev->vendor, pdev->device,
279 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
280 PCI_FUNC(pci_alias));
281
282 /*
283 * If we don't have a PCI DMA alias and the IVRS alias is on the same
284 * bus, then the IVRS table may know about a quirk that we don't.
285 */
286 if (pci_alias == devid &&
287 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
288 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
289 pci_info(pdev, "Added PCI DMA alias %02x.%d\n",
290 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias));
291 }
292
293 return ivrs_alias;
294 }
295
296 static struct iommu_dev_data *find_dev_data(u16 devid)
297 {
298 struct iommu_dev_data *dev_data;
299 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
300
301 dev_data = search_dev_data(devid);
302
303 if (dev_data == NULL) {
304 dev_data = alloc_dev_data(devid);
305 if (!dev_data)
306 return NULL;
307
308 if (translation_pre_enabled(iommu))
309 dev_data->defer_attach = true;
310 }
311
312 return dev_data;
313 }
314
315 struct iommu_dev_data *get_dev_data(struct device *dev)
316 {
317 return dev->archdata.iommu;
318 }
319 EXPORT_SYMBOL(get_dev_data);
320
321 /*
322 * Find or create an IOMMU group for a acpihid device.
323 */
324 static struct iommu_group *acpihid_device_group(struct device *dev)
325 {
326 struct acpihid_map_entry *p, *entry = NULL;
327 int devid;
328
329 devid = get_acpihid_device_id(dev, &entry);
330 if (devid < 0)
331 return ERR_PTR(devid);
332
333 list_for_each_entry(p, &acpihid_map, list) {
334 if ((devid == p->devid) && p->group)
335 entry->group = p->group;
336 }
337
338 if (!entry->group)
339 entry->group = generic_device_group(dev);
340 else
341 iommu_group_ref_get(entry->group);
342
343 return entry->group;
344 }
345
346 static bool pci_iommuv2_capable(struct pci_dev *pdev)
347 {
348 static const int caps[] = {
349 PCI_EXT_CAP_ID_ATS,
350 PCI_EXT_CAP_ID_PRI,
351 PCI_EXT_CAP_ID_PASID,
352 };
353 int i, pos;
354
355 if (pci_ats_disabled())
356 return false;
357
358 for (i = 0; i < 3; ++i) {
359 pos = pci_find_ext_capability(pdev, caps[i]);
360 if (pos == 0)
361 return false;
362 }
363
364 return true;
365 }
366
367 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
368 {
369 struct iommu_dev_data *dev_data;
370
371 dev_data = get_dev_data(&pdev->dev);
372
373 return dev_data->errata & (1 << erratum) ? true : false;
374 }
375
376 /*
377 * This function checks if the driver got a valid device from the caller to
378 * avoid dereferencing invalid pointers.
379 */
380 static bool check_device(struct device *dev)
381 {
382 int devid;
383
384 if (!dev || !dev->dma_mask)
385 return false;
386
387 devid = get_device_id(dev);
388 if (devid < 0)
389 return false;
390
391 /* Out of our scope? */
392 if (devid > amd_iommu_last_bdf)
393 return false;
394
395 if (amd_iommu_rlookup_table[devid] == NULL)
396 return false;
397
398 return true;
399 }
400
401 static void init_iommu_group(struct device *dev)
402 {
403 struct iommu_group *group;
404
405 group = iommu_group_get_for_dev(dev);
406 if (IS_ERR(group))
407 return;
408
409 iommu_group_put(group);
410 }
411
412 static int iommu_init_device(struct device *dev)
413 {
414 struct iommu_dev_data *dev_data;
415 struct amd_iommu *iommu;
416 int devid;
417
418 if (dev->archdata.iommu)
419 return 0;
420
421 devid = get_device_id(dev);
422 if (devid < 0)
423 return devid;
424
425 iommu = amd_iommu_rlookup_table[devid];
426
427 dev_data = find_dev_data(devid);
428 if (!dev_data)
429 return -ENOMEM;
430
431 dev_data->alias = get_alias(dev);
432
433 /*
434 * By default we use passthrough mode for IOMMUv2 capable device.
435 * But if amd_iommu=force_isolation is set (e.g. to debug DMA to
436 * invalid address), we ignore the capability for the device so
437 * it'll be forced to go into translation mode.
438 */
439 if ((iommu_pass_through || !amd_iommu_force_isolation) &&
440 dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
441 struct amd_iommu *iommu;
442
443 iommu = amd_iommu_rlookup_table[dev_data->devid];
444 dev_data->iommu_v2 = iommu->is_iommu_v2;
445 }
446
447 dev->archdata.iommu = dev_data;
448
449 iommu_device_link(&iommu->iommu, dev);
450
451 return 0;
452 }
453
454 static void iommu_ignore_device(struct device *dev)
455 {
456 u16 alias;
457 int devid;
458
459 devid = get_device_id(dev);
460 if (devid < 0)
461 return;
462
463 alias = get_alias(dev);
464
465 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
466 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
467
468 amd_iommu_rlookup_table[devid] = NULL;
469 amd_iommu_rlookup_table[alias] = NULL;
470 }
471
472 static void iommu_uninit_device(struct device *dev)
473 {
474 struct iommu_dev_data *dev_data;
475 struct amd_iommu *iommu;
476 int devid;
477
478 devid = get_device_id(dev);
479 if (devid < 0)
480 return;
481
482 iommu = amd_iommu_rlookup_table[devid];
483
484 dev_data = search_dev_data(devid);
485 if (!dev_data)
486 return;
487
488 if (dev_data->domain)
489 detach_device(dev);
490
491 iommu_device_unlink(&iommu->iommu, dev);
492
493 iommu_group_remove_device(dev);
494
495 /* Remove dma-ops */
496 dev->dma_ops = NULL;
497
498 /*
499 * We keep dev_data around for unplugged devices and reuse it when the
500 * device is re-plugged - not doing so would introduce a ton of races.
501 */
502 }
503
504 /****************************************************************************
505 *
506 * Interrupt handling functions
507 *
508 ****************************************************************************/
509
510 static void dump_dte_entry(u16 devid)
511 {
512 int i;
513
514 for (i = 0; i < 4; ++i)
515 pr_err("DTE[%d]: %016llx\n", i,
516 amd_iommu_dev_table[devid].data[i]);
517 }
518
519 static void dump_command(unsigned long phys_addr)
520 {
521 struct iommu_cmd *cmd = iommu_phys_to_virt(phys_addr);
522 int i;
523
524 for (i = 0; i < 4; ++i)
525 pr_err("CMD[%d]: %08x\n", i, cmd->data[i]);
526 }
527
528 static void amd_iommu_report_page_fault(u16 devid, u16 domain_id,
529 u64 address, int flags)
530 {
531 struct iommu_dev_data *dev_data = NULL;
532 struct pci_dev *pdev;
533
534 pdev = pci_get_domain_bus_and_slot(0, PCI_BUS_NUM(devid),
535 devid & 0xff);
536 if (pdev)
537 dev_data = get_dev_data(&pdev->dev);
538
539 if (dev_data && __ratelimit(&dev_data->rs)) {
540 pci_err(pdev, "Event logged [IO_PAGE_FAULT domain=0x%04x address=0x%llx flags=0x%04x]\n",
541 domain_id, address, flags);
542 } else if (printk_ratelimit()) {
543 pr_err("Event logged [IO_PAGE_FAULT device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
544 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
545 domain_id, address, flags);
546 }
547
548 if (pdev)
549 pci_dev_put(pdev);
550 }
551
552 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
553 {
554 struct device *dev = iommu->iommu.dev;
555 int type, devid, pasid, flags, tag;
556 volatile u32 *event = __evt;
557 int count = 0;
558 u64 address;
559
560 retry:
561 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
562 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
563 pasid = PPR_PASID(*(u64 *)&event[0]);
564 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
565 address = (u64)(((u64)event[3]) << 32) | event[2];
566
567 if (type == 0) {
568 /* Did we hit the erratum? */
569 if (++count == LOOP_TIMEOUT) {
570 pr_err("No event written to event log\n");
571 return;
572 }
573 udelay(1);
574 goto retry;
575 }
576
577 if (type == EVENT_TYPE_IO_FAULT) {
578 amd_iommu_report_page_fault(devid, pasid, address, flags);
579 return;
580 }
581
582 switch (type) {
583 case EVENT_TYPE_ILL_DEV:
584 dev_err(dev, "Event logged [ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 pasid, address, flags);
587 dump_dte_entry(devid);
588 break;
589 case EVENT_TYPE_DEV_TAB_ERR:
590 dev_err(dev, "Event logged [DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
591 "address=0x%llx flags=0x%04x]\n",
592 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
593 address, flags);
594 break;
595 case EVENT_TYPE_PAGE_TAB_ERR:
596 dev_err(dev, "Event logged [PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x domain=0x%04x address=0x%llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 pasid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 dev_err(dev, "Event logged [ILLEGAL_COMMAND_ERROR address=0x%llx]\n", address);
602 dump_command(address);
603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 dev_err(dev, "Event logged [COMMAND_HARDWARE_ERROR address=0x%llx flags=0x%04x]\n",
606 address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 dev_err(dev, "Event logged [IOTLB_INV_TIMEOUT device=%02x:%02x.%x address=0x%llx]\n",
610 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
611 address);
612 break;
613 case EVENT_TYPE_INV_DEV_REQ:
614 dev_err(dev, "Event logged [INVALID_DEVICE_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 pasid, address, flags);
617 break;
618 case EVENT_TYPE_INV_PPR_REQ:
619 pasid = ((event[0] >> 16) & 0xFFFF)
620 | ((event[1] << 6) & 0xF0000);
621 tag = event[1] & 0x03FF;
622 dev_err(dev, "Event logged [INVALID_PPR_REQUEST device=%02x:%02x.%x pasid=0x%05x address=0x%llx flags=0x%04x tag=0x%03x]\n",
623 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
624 pasid, address, flags, tag);
625 break;
626 default:
627 dev_err(dev, "Event logged [UNKNOWN event[0]=0x%08x event[1]=0x%08x event[2]=0x%08x event[3]=0x%08x\n",
628 event[0], event[1], event[2], event[3]);
629 }
630
631 memset(__evt, 0, 4 * sizeof(u32));
632 }
633
634 static void iommu_poll_events(struct amd_iommu *iommu)
635 {
636 u32 head, tail;
637
638 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
639 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
640
641 while (head != tail) {
642 iommu_print_event(iommu, iommu->evt_buf + head);
643 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
644 }
645
646 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
647 }
648
649 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
650 {
651 struct amd_iommu_fault fault;
652
653 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
654 pr_err_ratelimited("Unknown PPR request received\n");
655 return;
656 }
657
658 fault.address = raw[1];
659 fault.pasid = PPR_PASID(raw[0]);
660 fault.device_id = PPR_DEVID(raw[0]);
661 fault.tag = PPR_TAG(raw[0]);
662 fault.flags = PPR_FLAGS(raw[0]);
663
664 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
665 }
666
667 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
668 {
669 u32 head, tail;
670
671 if (iommu->ppr_log == NULL)
672 return;
673
674 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
675 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
676
677 while (head != tail) {
678 volatile u64 *raw;
679 u64 entry[2];
680 int i;
681
682 raw = (u64 *)(iommu->ppr_log + head);
683
684 /*
685 * Hardware bug: Interrupt may arrive before the entry is
686 * written to memory. If this happens we need to wait for the
687 * entry to arrive.
688 */
689 for (i = 0; i < LOOP_TIMEOUT; ++i) {
690 if (PPR_REQ_TYPE(raw[0]) != 0)
691 break;
692 udelay(1);
693 }
694
695 /* Avoid memcpy function-call overhead */
696 entry[0] = raw[0];
697 entry[1] = raw[1];
698
699 /*
700 * To detect the hardware bug we need to clear the entry
701 * back to zero.
702 */
703 raw[0] = raw[1] = 0UL;
704
705 /* Update head pointer of hardware ring-buffer */
706 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
707 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
708
709 /* Handle PPR entry */
710 iommu_handle_ppr_entry(iommu, entry);
711
712 /* Refresh ring-buffer information */
713 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
714 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
715 }
716 }
717
718 #ifdef CONFIG_IRQ_REMAP
719 static int (*iommu_ga_log_notifier)(u32);
720
721 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
722 {
723 iommu_ga_log_notifier = notifier;
724
725 return 0;
726 }
727 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
728
729 static void iommu_poll_ga_log(struct amd_iommu *iommu)
730 {
731 u32 head, tail, cnt = 0;
732
733 if (iommu->ga_log == NULL)
734 return;
735
736 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
737 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
738
739 while (head != tail) {
740 volatile u64 *raw;
741 u64 log_entry;
742
743 raw = (u64 *)(iommu->ga_log + head);
744 cnt++;
745
746 /* Avoid memcpy function-call overhead */
747 log_entry = *raw;
748
749 /* Update head pointer of hardware ring-buffer */
750 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
751 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
752
753 /* Handle GA entry */
754 switch (GA_REQ_TYPE(log_entry)) {
755 case GA_GUEST_NR:
756 if (!iommu_ga_log_notifier)
757 break;
758
759 pr_debug("%s: devid=%#x, ga_tag=%#x\n",
760 __func__, GA_DEVID(log_entry),
761 GA_TAG(log_entry));
762
763 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
764 pr_err("GA log notifier failed.\n");
765 break;
766 default:
767 break;
768 }
769 }
770 }
771 #endif /* CONFIG_IRQ_REMAP */
772
773 #define AMD_IOMMU_INT_MASK \
774 (MMIO_STATUS_EVT_INT_MASK | \
775 MMIO_STATUS_PPR_INT_MASK | \
776 MMIO_STATUS_GALOG_INT_MASK)
777
778 irqreturn_t amd_iommu_int_thread(int irq, void *data)
779 {
780 struct amd_iommu *iommu = (struct amd_iommu *) data;
781 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
782
783 while (status & AMD_IOMMU_INT_MASK) {
784 /* Enable EVT and PPR and GA interrupts again */
785 writel(AMD_IOMMU_INT_MASK,
786 iommu->mmio_base + MMIO_STATUS_OFFSET);
787
788 if (status & MMIO_STATUS_EVT_INT_MASK) {
789 pr_devel("Processing IOMMU Event Log\n");
790 iommu_poll_events(iommu);
791 }
792
793 if (status & MMIO_STATUS_PPR_INT_MASK) {
794 pr_devel("Processing IOMMU PPR Log\n");
795 iommu_poll_ppr_log(iommu);
796 }
797
798 #ifdef CONFIG_IRQ_REMAP
799 if (status & MMIO_STATUS_GALOG_INT_MASK) {
800 pr_devel("Processing IOMMU GA Log\n");
801 iommu_poll_ga_log(iommu);
802 }
803 #endif
804
805 /*
806 * Hardware bug: ERBT1312
807 * When re-enabling interrupt (by writing 1
808 * to clear the bit), the hardware might also try to set
809 * the interrupt bit in the event status register.
810 * In this scenario, the bit will be set, and disable
811 * subsequent interrupts.
812 *
813 * Workaround: The IOMMU driver should read back the
814 * status register and check if the interrupt bits are cleared.
815 * If not, driver will need to go through the interrupt handler
816 * again and re-clear the bits
817 */
818 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
819 }
820 return IRQ_HANDLED;
821 }
822
823 irqreturn_t amd_iommu_int_handler(int irq, void *data)
824 {
825 return IRQ_WAKE_THREAD;
826 }
827
828 /****************************************************************************
829 *
830 * IOMMU command queuing functions
831 *
832 ****************************************************************************/
833
834 static int wait_on_sem(volatile u64 *sem)
835 {
836 int i = 0;
837
838 while (*sem == 0 && i < LOOP_TIMEOUT) {
839 udelay(1);
840 i += 1;
841 }
842
843 if (i == LOOP_TIMEOUT) {
844 pr_alert("Completion-Wait loop timed out\n");
845 return -EIO;
846 }
847
848 return 0;
849 }
850
851 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
852 struct iommu_cmd *cmd)
853 {
854 u8 *target;
855
856 target = iommu->cmd_buf + iommu->cmd_buf_tail;
857
858 iommu->cmd_buf_tail += sizeof(*cmd);
859 iommu->cmd_buf_tail %= CMD_BUFFER_SIZE;
860
861 /* Copy command to buffer */
862 memcpy(target, cmd, sizeof(*cmd));
863
864 /* Tell the IOMMU about it */
865 writel(iommu->cmd_buf_tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
866 }
867
868 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
869 {
870 u64 paddr = iommu_virt_to_phys((void *)address);
871
872 WARN_ON(address & 0x7ULL);
873
874 memset(cmd, 0, sizeof(*cmd));
875 cmd->data[0] = lower_32_bits(paddr) | CMD_COMPL_WAIT_STORE_MASK;
876 cmd->data[1] = upper_32_bits(paddr);
877 cmd->data[2] = 1;
878 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
879 }
880
881 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
882 {
883 memset(cmd, 0, sizeof(*cmd));
884 cmd->data[0] = devid;
885 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
886 }
887
888 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
889 size_t size, u16 domid, int pde)
890 {
891 u64 pages;
892 bool s;
893
894 pages = iommu_num_pages(address, size, PAGE_SIZE);
895 s = false;
896
897 if (pages > 1) {
898 /*
899 * If we have to flush more than one page, flush all
900 * TLB entries for this domain
901 */
902 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
903 s = true;
904 }
905
906 address &= PAGE_MASK;
907
908 memset(cmd, 0, sizeof(*cmd));
909 cmd->data[1] |= domid;
910 cmd->data[2] = lower_32_bits(address);
911 cmd->data[3] = upper_32_bits(address);
912 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
913 if (s) /* size bit - we flush more than one 4kb page */
914 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
915 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 }
918
919 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
920 u64 address, size_t size)
921 {
922 u64 pages;
923 bool s;
924
925 pages = iommu_num_pages(address, size, PAGE_SIZE);
926 s = false;
927
928 if (pages > 1) {
929 /*
930 * If we have to flush more than one page, flush all
931 * TLB entries for this domain
932 */
933 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
934 s = true;
935 }
936
937 address &= PAGE_MASK;
938
939 memset(cmd, 0, sizeof(*cmd));
940 cmd->data[0] = devid;
941 cmd->data[0] |= (qdep & 0xff) << 24;
942 cmd->data[1] = devid;
943 cmd->data[2] = lower_32_bits(address);
944 cmd->data[3] = upper_32_bits(address);
945 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
946 if (s)
947 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
948 }
949
950 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
951 u64 address, bool size)
952 {
953 memset(cmd, 0, sizeof(*cmd));
954
955 address &= ~(0xfffULL);
956
957 cmd->data[0] = pasid;
958 cmd->data[1] = domid;
959 cmd->data[2] = lower_32_bits(address);
960 cmd->data[3] = upper_32_bits(address);
961 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
962 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
963 if (size)
964 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
965 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
966 }
967
968 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
969 int qdep, u64 address, bool size)
970 {
971 memset(cmd, 0, sizeof(*cmd));
972
973 address &= ~(0xfffULL);
974
975 cmd->data[0] = devid;
976 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
977 cmd->data[0] |= (qdep & 0xff) << 24;
978 cmd->data[1] = devid;
979 cmd->data[1] |= (pasid & 0xff) << 16;
980 cmd->data[2] = lower_32_bits(address);
981 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
982 cmd->data[3] = upper_32_bits(address);
983 if (size)
984 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
985 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
986 }
987
988 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
989 int status, int tag, bool gn)
990 {
991 memset(cmd, 0, sizeof(*cmd));
992
993 cmd->data[0] = devid;
994 if (gn) {
995 cmd->data[1] = pasid;
996 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
997 }
998 cmd->data[3] = tag & 0x1ff;
999 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
1000
1001 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
1002 }
1003
1004 static void build_inv_all(struct iommu_cmd *cmd)
1005 {
1006 memset(cmd, 0, sizeof(*cmd));
1007 CMD_SET_TYPE(cmd, CMD_INV_ALL);
1008 }
1009
1010 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1011 {
1012 memset(cmd, 0, sizeof(*cmd));
1013 cmd->data[0] = devid;
1014 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1015 }
1016
1017 /*
1018 * Writes the command to the IOMMUs command buffer and informs the
1019 * hardware about the new command.
1020 */
1021 static int __iommu_queue_command_sync(struct amd_iommu *iommu,
1022 struct iommu_cmd *cmd,
1023 bool sync)
1024 {
1025 unsigned int count = 0;
1026 u32 left, next_tail;
1027
1028 next_tail = (iommu->cmd_buf_tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1029 again:
1030 left = (iommu->cmd_buf_head - next_tail) % CMD_BUFFER_SIZE;
1031
1032 if (left <= 0x20) {
1033 /* Skip udelay() the first time around */
1034 if (count++) {
1035 if (count == LOOP_TIMEOUT) {
1036 pr_err("Command buffer timeout\n");
1037 return -EIO;
1038 }
1039
1040 udelay(1);
1041 }
1042
1043 /* Update head and recheck remaining space */
1044 iommu->cmd_buf_head = readl(iommu->mmio_base +
1045 MMIO_CMD_HEAD_OFFSET);
1046
1047 goto again;
1048 }
1049
1050 copy_cmd_to_buffer(iommu, cmd);
1051
1052 /* Do we need to make sure all commands are processed? */
1053 iommu->need_sync = sync;
1054
1055 return 0;
1056 }
1057
1058 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1059 struct iommu_cmd *cmd,
1060 bool sync)
1061 {
1062 unsigned long flags;
1063 int ret;
1064
1065 raw_spin_lock_irqsave(&iommu->lock, flags);
1066 ret = __iommu_queue_command_sync(iommu, cmd, sync);
1067 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1068
1069 return ret;
1070 }
1071
1072 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1073 {
1074 return iommu_queue_command_sync(iommu, cmd, true);
1075 }
1076
1077 /*
1078 * This function queues a completion wait command into the command
1079 * buffer of an IOMMU
1080 */
1081 static int iommu_completion_wait(struct amd_iommu *iommu)
1082 {
1083 struct iommu_cmd cmd;
1084 unsigned long flags;
1085 int ret;
1086
1087 if (!iommu->need_sync)
1088 return 0;
1089
1090
1091 build_completion_wait(&cmd, (u64)&iommu->cmd_sem);
1092
1093 raw_spin_lock_irqsave(&iommu->lock, flags);
1094
1095 iommu->cmd_sem = 0;
1096
1097 ret = __iommu_queue_command_sync(iommu, &cmd, false);
1098 if (ret)
1099 goto out_unlock;
1100
1101 ret = wait_on_sem(&iommu->cmd_sem);
1102
1103 out_unlock:
1104 raw_spin_unlock_irqrestore(&iommu->lock, flags);
1105
1106 return ret;
1107 }
1108
1109 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1110 {
1111 struct iommu_cmd cmd;
1112
1113 build_inv_dte(&cmd, devid);
1114
1115 return iommu_queue_command(iommu, &cmd);
1116 }
1117
1118 static void amd_iommu_flush_dte_all(struct amd_iommu *iommu)
1119 {
1120 u32 devid;
1121
1122 for (devid = 0; devid <= 0xffff; ++devid)
1123 iommu_flush_dte(iommu, devid);
1124
1125 iommu_completion_wait(iommu);
1126 }
1127
1128 /*
1129 * This function uses heavy locking and may disable irqs for some time. But
1130 * this is no issue because it is only called during resume.
1131 */
1132 static void amd_iommu_flush_tlb_all(struct amd_iommu *iommu)
1133 {
1134 u32 dom_id;
1135
1136 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1137 struct iommu_cmd cmd;
1138 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1139 dom_id, 1);
1140 iommu_queue_command(iommu, &cmd);
1141 }
1142
1143 iommu_completion_wait(iommu);
1144 }
1145
1146 static void amd_iommu_flush_all(struct amd_iommu *iommu)
1147 {
1148 struct iommu_cmd cmd;
1149
1150 build_inv_all(&cmd);
1151
1152 iommu_queue_command(iommu, &cmd);
1153 iommu_completion_wait(iommu);
1154 }
1155
1156 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1157 {
1158 struct iommu_cmd cmd;
1159
1160 build_inv_irt(&cmd, devid);
1161
1162 iommu_queue_command(iommu, &cmd);
1163 }
1164
1165 static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
1166 {
1167 u32 devid;
1168
1169 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1170 iommu_flush_irt(iommu, devid);
1171
1172 iommu_completion_wait(iommu);
1173 }
1174
1175 void iommu_flush_all_caches(struct amd_iommu *iommu)
1176 {
1177 if (iommu_feature(iommu, FEATURE_IA)) {
1178 amd_iommu_flush_all(iommu);
1179 } else {
1180 amd_iommu_flush_dte_all(iommu);
1181 amd_iommu_flush_irt_all(iommu);
1182 amd_iommu_flush_tlb_all(iommu);
1183 }
1184 }
1185
1186 /*
1187 * Command send function for flushing on-device TLB
1188 */
1189 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1190 u64 address, size_t size)
1191 {
1192 struct amd_iommu *iommu;
1193 struct iommu_cmd cmd;
1194 int qdep;
1195
1196 qdep = dev_data->ats.qdep;
1197 iommu = amd_iommu_rlookup_table[dev_data->devid];
1198
1199 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1200
1201 return iommu_queue_command(iommu, &cmd);
1202 }
1203
1204 /*
1205 * Command send function for invalidating a device table entry
1206 */
1207 static int device_flush_dte(struct iommu_dev_data *dev_data)
1208 {
1209 struct amd_iommu *iommu;
1210 u16 alias;
1211 int ret;
1212
1213 iommu = amd_iommu_rlookup_table[dev_data->devid];
1214 alias = dev_data->alias;
1215
1216 ret = iommu_flush_dte(iommu, dev_data->devid);
1217 if (!ret && alias != dev_data->devid)
1218 ret = iommu_flush_dte(iommu, alias);
1219 if (ret)
1220 return ret;
1221
1222 if (dev_data->ats.enabled)
1223 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1224
1225 return ret;
1226 }
1227
1228 /*
1229 * TLB invalidation function which is called from the mapping functions.
1230 * It invalidates a single PTE if the range to flush is within a single
1231 * page. Otherwise it flushes the whole TLB of the IOMMU.
1232 */
1233 static void __domain_flush_pages(struct protection_domain *domain,
1234 u64 address, size_t size, int pde)
1235 {
1236 struct iommu_dev_data *dev_data;
1237 struct iommu_cmd cmd;
1238 int ret = 0, i;
1239
1240 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1241
1242 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1243 if (!domain->dev_iommu[i])
1244 continue;
1245
1246 /*
1247 * Devices of this domain are behind this IOMMU
1248 * We need a TLB flush
1249 */
1250 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1251 }
1252
1253 list_for_each_entry(dev_data, &domain->dev_list, list) {
1254
1255 if (!dev_data->ats.enabled)
1256 continue;
1257
1258 ret |= device_flush_iotlb(dev_data, address, size);
1259 }
1260
1261 WARN_ON(ret);
1262 }
1263
1264 static void domain_flush_pages(struct protection_domain *domain,
1265 u64 address, size_t size)
1266 {
1267 __domain_flush_pages(domain, address, size, 0);
1268 }
1269
1270 /* Flush the whole IO/TLB for a given protection domain */
1271 static void domain_flush_tlb(struct protection_domain *domain)
1272 {
1273 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1274 }
1275
1276 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1277 static void domain_flush_tlb_pde(struct protection_domain *domain)
1278 {
1279 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1280 }
1281
1282 static void domain_flush_complete(struct protection_domain *domain)
1283 {
1284 int i;
1285
1286 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
1287 if (domain && !domain->dev_iommu[i])
1288 continue;
1289
1290 /*
1291 * Devices of this domain are behind this IOMMU
1292 * We need to wait for completion of all commands.
1293 */
1294 iommu_completion_wait(amd_iommus[i]);
1295 }
1296 }
1297
1298 /* Flush the not present cache if it exists */
1299 static void domain_flush_np_cache(struct protection_domain *domain,
1300 dma_addr_t iova, size_t size)
1301 {
1302 if (unlikely(amd_iommu_np_cache)) {
1303 domain_flush_pages(domain, iova, size);
1304 domain_flush_complete(domain);
1305 }
1306 }
1307
1308
1309 /*
1310 * This function flushes the DTEs for all devices in domain
1311 */
1312 static void domain_flush_devices(struct protection_domain *domain)
1313 {
1314 struct iommu_dev_data *dev_data;
1315
1316 list_for_each_entry(dev_data, &domain->dev_list, list)
1317 device_flush_dte(dev_data);
1318 }
1319
1320 /****************************************************************************
1321 *
1322 * The functions below are used the create the page table mappings for
1323 * unity mapped regions.
1324 *
1325 ****************************************************************************/
1326
1327 static void free_page_list(struct page *freelist)
1328 {
1329 while (freelist != NULL) {
1330 unsigned long p = (unsigned long)page_address(freelist);
1331 freelist = freelist->freelist;
1332 free_page(p);
1333 }
1334 }
1335
1336 static struct page *free_pt_page(unsigned long pt, struct page *freelist)
1337 {
1338 struct page *p = virt_to_page((void *)pt);
1339
1340 p->freelist = freelist;
1341
1342 return p;
1343 }
1344
1345 #define DEFINE_FREE_PT_FN(LVL, FN) \
1346 static struct page *free_pt_##LVL (unsigned long __pt, struct page *freelist) \
1347 { \
1348 unsigned long p; \
1349 u64 *pt; \
1350 int i; \
1351 \
1352 pt = (u64 *)__pt; \
1353 \
1354 for (i = 0; i < 512; ++i) { \
1355 /* PTE present? */ \
1356 if (!IOMMU_PTE_PRESENT(pt[i])) \
1357 continue; \
1358 \
1359 /* Large PTE? */ \
1360 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1361 PM_PTE_LEVEL(pt[i]) == 7) \
1362 continue; \
1363 \
1364 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1365 freelist = FN(p, freelist); \
1366 } \
1367 \
1368 return free_pt_page((unsigned long)pt, freelist); \
1369 }
1370
1371 DEFINE_FREE_PT_FN(l2, free_pt_page)
1372 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1373 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1374 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1375 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1376
1377 static struct page *free_sub_pt(unsigned long root, int mode,
1378 struct page *freelist)
1379 {
1380 switch (mode) {
1381 case PAGE_MODE_NONE:
1382 case PAGE_MODE_7_LEVEL:
1383 break;
1384 case PAGE_MODE_1_LEVEL:
1385 freelist = free_pt_page(root, freelist);
1386 break;
1387 case PAGE_MODE_2_LEVEL:
1388 freelist = free_pt_l2(root, freelist);
1389 break;
1390 case PAGE_MODE_3_LEVEL:
1391 freelist = free_pt_l3(root, freelist);
1392 break;
1393 case PAGE_MODE_4_LEVEL:
1394 freelist = free_pt_l4(root, freelist);
1395 break;
1396 case PAGE_MODE_5_LEVEL:
1397 freelist = free_pt_l5(root, freelist);
1398 break;
1399 case PAGE_MODE_6_LEVEL:
1400 freelist = free_pt_l6(root, freelist);
1401 break;
1402 default:
1403 BUG();
1404 }
1405
1406 return freelist;
1407 }
1408
1409 static void free_pagetable(struct protection_domain *domain)
1410 {
1411 unsigned long root = (unsigned long)domain->pt_root;
1412 struct page *freelist = NULL;
1413
1414 BUG_ON(domain->mode < PAGE_MODE_NONE ||
1415 domain->mode > PAGE_MODE_6_LEVEL);
1416
1417 free_sub_pt(root, domain->mode, freelist);
1418
1419 free_page_list(freelist);
1420 }
1421
1422 /*
1423 * This function is used to add another level to an IO page table. Adding
1424 * another level increases the size of the address space by 9 bits to a size up
1425 * to 64 bits.
1426 */
1427 static bool increase_address_space(struct protection_domain *domain,
1428 gfp_t gfp)
1429 {
1430 u64 *pte;
1431
1432 if (domain->mode == PAGE_MODE_6_LEVEL)
1433 /* address space already 64 bit large */
1434 return false;
1435
1436 pte = (void *)get_zeroed_page(gfp);
1437 if (!pte)
1438 return false;
1439
1440 *pte = PM_LEVEL_PDE(domain->mode,
1441 iommu_virt_to_phys(domain->pt_root));
1442 domain->pt_root = pte;
1443 domain->mode += 1;
1444 domain->updated = true;
1445
1446 return true;
1447 }
1448
1449 static u64 *alloc_pte(struct protection_domain *domain,
1450 unsigned long address,
1451 unsigned long page_size,
1452 u64 **pte_page,
1453 gfp_t gfp)
1454 {
1455 int level, end_lvl;
1456 u64 *pte, *page;
1457
1458 BUG_ON(!is_power_of_2(page_size));
1459
1460 while (address > PM_LEVEL_SIZE(domain->mode))
1461 increase_address_space(domain, gfp);
1462
1463 level = domain->mode - 1;
1464 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1465 address = PAGE_SIZE_ALIGN(address, page_size);
1466 end_lvl = PAGE_SIZE_LEVEL(page_size);
1467
1468 while (level > end_lvl) {
1469 u64 __pte, __npte;
1470 int pte_level;
1471
1472 __pte = *pte;
1473 pte_level = PM_PTE_LEVEL(__pte);
1474
1475 if (!IOMMU_PTE_PRESENT(__pte) ||
1476 pte_level == PAGE_MODE_7_LEVEL) {
1477 page = (u64 *)get_zeroed_page(gfp);
1478 if (!page)
1479 return NULL;
1480
1481 __npte = PM_LEVEL_PDE(level, iommu_virt_to_phys(page));
1482
1483 /* pte could have been changed somewhere. */
1484 if (cmpxchg64(pte, __pte, __npte) != __pte)
1485 free_page((unsigned long)page);
1486 else if (pte_level == PAGE_MODE_7_LEVEL)
1487 domain->updated = true;
1488
1489 continue;
1490 }
1491
1492 /* No level skipping support yet */
1493 if (pte_level != level)
1494 return NULL;
1495
1496 level -= 1;
1497
1498 pte = IOMMU_PTE_PAGE(__pte);
1499
1500 if (pte_page && level == end_lvl)
1501 *pte_page = pte;
1502
1503 pte = &pte[PM_LEVEL_INDEX(level, address)];
1504 }
1505
1506 return pte;
1507 }
1508
1509 /*
1510 * This function checks if there is a PTE for a given dma address. If
1511 * there is one, it returns the pointer to it.
1512 */
1513 static u64 *fetch_pte(struct protection_domain *domain,
1514 unsigned long address,
1515 unsigned long *page_size)
1516 {
1517 int level;
1518 u64 *pte;
1519
1520 *page_size = 0;
1521
1522 if (address > PM_LEVEL_SIZE(domain->mode))
1523 return NULL;
1524
1525 level = domain->mode - 1;
1526 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1527 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1528
1529 while (level > 0) {
1530
1531 /* Not Present */
1532 if (!IOMMU_PTE_PRESENT(*pte))
1533 return NULL;
1534
1535 /* Large PTE */
1536 if (PM_PTE_LEVEL(*pte) == 7 ||
1537 PM_PTE_LEVEL(*pte) == 0)
1538 break;
1539
1540 /* No level skipping support yet */
1541 if (PM_PTE_LEVEL(*pte) != level)
1542 return NULL;
1543
1544 level -= 1;
1545
1546 /* Walk to the next level */
1547 pte = IOMMU_PTE_PAGE(*pte);
1548 pte = &pte[PM_LEVEL_INDEX(level, address)];
1549 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1550 }
1551
1552 if (PM_PTE_LEVEL(*pte) == 0x07) {
1553 unsigned long pte_mask;
1554
1555 /*
1556 * If we have a series of large PTEs, make
1557 * sure to return a pointer to the first one.
1558 */
1559 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1560 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1561 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1562 }
1563
1564 return pte;
1565 }
1566
1567 static struct page *free_clear_pte(u64 *pte, u64 pteval, struct page *freelist)
1568 {
1569 unsigned long pt;
1570 int mode;
1571
1572 while (cmpxchg64(pte, pteval, 0) != pteval) {
1573 pr_warn("AMD-Vi: IOMMU pte changed since we read it\n");
1574 pteval = *pte;
1575 }
1576
1577 if (!IOMMU_PTE_PRESENT(pteval))
1578 return freelist;
1579
1580 pt = (unsigned long)IOMMU_PTE_PAGE(pteval);
1581 mode = IOMMU_PTE_MODE(pteval);
1582
1583 return free_sub_pt(pt, mode, freelist);
1584 }
1585
1586 /*
1587 * Generic mapping functions. It maps a physical address into a DMA
1588 * address space. It allocates the page table pages if necessary.
1589 * In the future it can be extended to a generic mapping function
1590 * supporting all features of AMD IOMMU page tables like level skipping
1591 * and full 64 bit address spaces.
1592 */
1593 static int iommu_map_page(struct protection_domain *dom,
1594 unsigned long bus_addr,
1595 unsigned long phys_addr,
1596 unsigned long page_size,
1597 int prot,
1598 gfp_t gfp)
1599 {
1600 struct page *freelist = NULL;
1601 u64 __pte, *pte;
1602 int i, count;
1603
1604 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1605 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1606
1607 if (!(prot & IOMMU_PROT_MASK))
1608 return -EINVAL;
1609
1610 count = PAGE_SIZE_PTE_COUNT(page_size);
1611 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1612
1613 if (!pte)
1614 return -ENOMEM;
1615
1616 for (i = 0; i < count; ++i)
1617 freelist = free_clear_pte(&pte[i], pte[i], freelist);
1618
1619 if (freelist != NULL)
1620 dom->updated = true;
1621
1622 if (count > 1) {
1623 __pte = PAGE_SIZE_PTE(__sme_set(phys_addr), page_size);
1624 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1625 } else
1626 __pte = __sme_set(phys_addr) | IOMMU_PTE_PR | IOMMU_PTE_FC;
1627
1628 if (prot & IOMMU_PROT_IR)
1629 __pte |= IOMMU_PTE_IR;
1630 if (prot & IOMMU_PROT_IW)
1631 __pte |= IOMMU_PTE_IW;
1632
1633 for (i = 0; i < count; ++i)
1634 pte[i] = __pte;
1635
1636 update_domain(dom);
1637
1638 /* Everything flushed out, free pages now */
1639 free_page_list(freelist);
1640
1641 return 0;
1642 }
1643
1644 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1645 unsigned long bus_addr,
1646 unsigned long page_size)
1647 {
1648 unsigned long long unmapped;
1649 unsigned long unmap_size;
1650 u64 *pte;
1651
1652 BUG_ON(!is_power_of_2(page_size));
1653
1654 unmapped = 0;
1655
1656 while (unmapped < page_size) {
1657
1658 pte = fetch_pte(dom, bus_addr, &unmap_size);
1659
1660 if (pte) {
1661 int i, count;
1662
1663 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1664 for (i = 0; i < count; i++)
1665 pte[i] = 0ULL;
1666 }
1667
1668 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1669 unmapped += unmap_size;
1670 }
1671
1672 BUG_ON(unmapped && !is_power_of_2(unmapped));
1673
1674 return unmapped;
1675 }
1676
1677 /****************************************************************************
1678 *
1679 * The next functions belong to the address allocator for the dma_ops
1680 * interface functions.
1681 *
1682 ****************************************************************************/
1683
1684
1685 static unsigned long dma_ops_alloc_iova(struct device *dev,
1686 struct dma_ops_domain *dma_dom,
1687 unsigned int pages, u64 dma_mask)
1688 {
1689 unsigned long pfn = 0;
1690
1691 pages = __roundup_pow_of_two(pages);
1692
1693 if (dma_mask > DMA_BIT_MASK(32))
1694 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1695 IOVA_PFN(DMA_BIT_MASK(32)), false);
1696
1697 if (!pfn)
1698 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1699 IOVA_PFN(dma_mask), true);
1700
1701 return (pfn << PAGE_SHIFT);
1702 }
1703
1704 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1705 unsigned long address,
1706 unsigned int pages)
1707 {
1708 pages = __roundup_pow_of_two(pages);
1709 address >>= PAGE_SHIFT;
1710
1711 free_iova_fast(&dma_dom->iovad, address, pages);
1712 }
1713
1714 /****************************************************************************
1715 *
1716 * The next functions belong to the domain allocation. A domain is
1717 * allocated for every IOMMU as the default domain. If device isolation
1718 * is enabled, every device get its own domain. The most important thing
1719 * about domains is the page table mapping the DMA address space they
1720 * contain.
1721 *
1722 ****************************************************************************/
1723
1724 static u16 domain_id_alloc(void)
1725 {
1726 int id;
1727
1728 spin_lock(&pd_bitmap_lock);
1729 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1730 BUG_ON(id == 0);
1731 if (id > 0 && id < MAX_DOMAIN_ID)
1732 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1733 else
1734 id = 0;
1735 spin_unlock(&pd_bitmap_lock);
1736
1737 return id;
1738 }
1739
1740 static void domain_id_free(int id)
1741 {
1742 spin_lock(&pd_bitmap_lock);
1743 if (id > 0 && id < MAX_DOMAIN_ID)
1744 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1745 spin_unlock(&pd_bitmap_lock);
1746 }
1747
1748 static void free_gcr3_tbl_level1(u64 *tbl)
1749 {
1750 u64 *ptr;
1751 int i;
1752
1753 for (i = 0; i < 512; ++i) {
1754 if (!(tbl[i] & GCR3_VALID))
1755 continue;
1756
1757 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1758
1759 free_page((unsigned long)ptr);
1760 }
1761 }
1762
1763 static void free_gcr3_tbl_level2(u64 *tbl)
1764 {
1765 u64 *ptr;
1766 int i;
1767
1768 for (i = 0; i < 512; ++i) {
1769 if (!(tbl[i] & GCR3_VALID))
1770 continue;
1771
1772 ptr = iommu_phys_to_virt(tbl[i] & PAGE_MASK);
1773
1774 free_gcr3_tbl_level1(ptr);
1775 }
1776 }
1777
1778 static void free_gcr3_table(struct protection_domain *domain)
1779 {
1780 if (domain->glx == 2)
1781 free_gcr3_tbl_level2(domain->gcr3_tbl);
1782 else if (domain->glx == 1)
1783 free_gcr3_tbl_level1(domain->gcr3_tbl);
1784 else
1785 BUG_ON(domain->glx != 0);
1786
1787 free_page((unsigned long)domain->gcr3_tbl);
1788 }
1789
1790 static void dma_ops_domain_flush_tlb(struct dma_ops_domain *dom)
1791 {
1792 domain_flush_tlb(&dom->domain);
1793 domain_flush_complete(&dom->domain);
1794 }
1795
1796 static void iova_domain_flush_tlb(struct iova_domain *iovad)
1797 {
1798 struct dma_ops_domain *dom;
1799
1800 dom = container_of(iovad, struct dma_ops_domain, iovad);
1801
1802 dma_ops_domain_flush_tlb(dom);
1803 }
1804
1805 /*
1806 * Free a domain, only used if something went wrong in the
1807 * allocation path and we need to free an already allocated page table
1808 */
1809 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1810 {
1811 if (!dom)
1812 return;
1813
1814 put_iova_domain(&dom->iovad);
1815
1816 free_pagetable(&dom->domain);
1817
1818 if (dom->domain.id)
1819 domain_id_free(dom->domain.id);
1820
1821 kfree(dom);
1822 }
1823
1824 /*
1825 * Allocates a new protection domain usable for the dma_ops functions.
1826 * It also initializes the page table and the address allocator data
1827 * structures required for the dma_ops interface
1828 */
1829 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1830 {
1831 struct dma_ops_domain *dma_dom;
1832
1833 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1834 if (!dma_dom)
1835 return NULL;
1836
1837 if (protection_domain_init(&dma_dom->domain))
1838 goto free_dma_dom;
1839
1840 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1841 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1842 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1843 if (!dma_dom->domain.pt_root)
1844 goto free_dma_dom;
1845
1846 init_iova_domain(&dma_dom->iovad, PAGE_SIZE, IOVA_START_PFN);
1847
1848 if (init_iova_flush_queue(&dma_dom->iovad, iova_domain_flush_tlb, NULL))
1849 goto free_dma_dom;
1850
1851 /* Initialize reserved ranges */
1852 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1853
1854 return dma_dom;
1855
1856 free_dma_dom:
1857 dma_ops_domain_free(dma_dom);
1858
1859 return NULL;
1860 }
1861
1862 /*
1863 * little helper function to check whether a given protection domain is a
1864 * dma_ops domain
1865 */
1866 static bool dma_ops_domain(struct protection_domain *domain)
1867 {
1868 return domain->flags & PD_DMA_OPS_MASK;
1869 }
1870
1871 static void set_dte_entry(u16 devid, struct protection_domain *domain,
1872 bool ats, bool ppr)
1873 {
1874 u64 pte_root = 0;
1875 u64 flags = 0;
1876
1877 if (domain->mode != PAGE_MODE_NONE)
1878 pte_root = iommu_virt_to_phys(domain->pt_root);
1879
1880 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1881 << DEV_ENTRY_MODE_SHIFT;
1882 pte_root |= DTE_FLAG_IR | DTE_FLAG_IW | DTE_FLAG_V | DTE_FLAG_TV;
1883
1884 flags = amd_iommu_dev_table[devid].data[1];
1885
1886 if (ats)
1887 flags |= DTE_FLAG_IOTLB;
1888
1889 if (ppr) {
1890 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
1891
1892 if (iommu_feature(iommu, FEATURE_EPHSUP))
1893 pte_root |= 1ULL << DEV_ENTRY_PPR;
1894 }
1895
1896 if (domain->flags & PD_IOMMUV2_MASK) {
1897 u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
1898 u64 glx = domain->glx;
1899 u64 tmp;
1900
1901 pte_root |= DTE_FLAG_GV;
1902 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1903
1904 /* First mask out possible old values for GCR3 table */
1905 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1906 flags &= ~tmp;
1907
1908 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1909 flags &= ~tmp;
1910
1911 /* Encode GCR3 table into DTE */
1912 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1913 pte_root |= tmp;
1914
1915 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1916 flags |= tmp;
1917
1918 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1919 flags |= tmp;
1920 }
1921
1922 flags &= ~DEV_DOMID_MASK;
1923 flags |= domain->id;
1924
1925 amd_iommu_dev_table[devid].data[1] = flags;
1926 amd_iommu_dev_table[devid].data[0] = pte_root;
1927 }
1928
1929 static void clear_dte_entry(u16 devid)
1930 {
1931 /* remove entry from the device table seen by the hardware */
1932 amd_iommu_dev_table[devid].data[0] = DTE_FLAG_V | DTE_FLAG_TV;
1933 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1934
1935 amd_iommu_apply_erratum_63(devid);
1936 }
1937
1938 static void do_attach(struct iommu_dev_data *dev_data,
1939 struct protection_domain *domain)
1940 {
1941 struct amd_iommu *iommu;
1942 u16 alias;
1943 bool ats;
1944
1945 iommu = amd_iommu_rlookup_table[dev_data->devid];
1946 alias = dev_data->alias;
1947 ats = dev_data->ats.enabled;
1948
1949 /* Update data structures */
1950 dev_data->domain = domain;
1951 list_add(&dev_data->list, &domain->dev_list);
1952
1953 /* Do reference counting */
1954 domain->dev_iommu[iommu->index] += 1;
1955 domain->dev_cnt += 1;
1956
1957 /* Update device table */
1958 set_dte_entry(dev_data->devid, domain, ats, dev_data->iommu_v2);
1959 if (alias != dev_data->devid)
1960 set_dte_entry(alias, domain, ats, dev_data->iommu_v2);
1961
1962 device_flush_dte(dev_data);
1963 }
1964
1965 static void do_detach(struct iommu_dev_data *dev_data)
1966 {
1967 struct protection_domain *domain = dev_data->domain;
1968 struct amd_iommu *iommu;
1969 u16 alias;
1970
1971 iommu = amd_iommu_rlookup_table[dev_data->devid];
1972 alias = dev_data->alias;
1973
1974 /* Update data structures */
1975 dev_data->domain = NULL;
1976 list_del(&dev_data->list);
1977 clear_dte_entry(dev_data->devid);
1978 if (alias != dev_data->devid)
1979 clear_dte_entry(alias);
1980
1981 /* Flush the DTE entry */
1982 device_flush_dte(dev_data);
1983
1984 /* Flush IOTLB */
1985 domain_flush_tlb_pde(domain);
1986
1987 /* Wait for the flushes to finish */
1988 domain_flush_complete(domain);
1989
1990 /* decrease reference counters - needs to happen after the flushes */
1991 domain->dev_iommu[iommu->index] -= 1;
1992 domain->dev_cnt -= 1;
1993 }
1994
1995 /*
1996 * If a device is not yet associated with a domain, this function makes the
1997 * device visible in the domain
1998 */
1999 static int __attach_device(struct iommu_dev_data *dev_data,
2000 struct protection_domain *domain)
2001 {
2002 int ret;
2003
2004 /* lock domain */
2005 spin_lock(&domain->lock);
2006
2007 ret = -EBUSY;
2008 if (dev_data->domain != NULL)
2009 goto out_unlock;
2010
2011 /* Attach alias group root */
2012 do_attach(dev_data, domain);
2013
2014 ret = 0;
2015
2016 out_unlock:
2017
2018 /* ready */
2019 spin_unlock(&domain->lock);
2020
2021 return ret;
2022 }
2023
2024
2025 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2026 {
2027 pci_disable_ats(pdev);
2028 pci_disable_pri(pdev);
2029 pci_disable_pasid(pdev);
2030 }
2031
2032 /* FIXME: Change generic reset-function to do the same */
2033 static int pri_reset_while_enabled(struct pci_dev *pdev)
2034 {
2035 u16 control;
2036 int pos;
2037
2038 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2039 if (!pos)
2040 return -EINVAL;
2041
2042 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2043 control |= PCI_PRI_CTRL_RESET;
2044 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2045
2046 return 0;
2047 }
2048
2049 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2050 {
2051 bool reset_enable;
2052 int reqs, ret;
2053
2054 /* FIXME: Hardcode number of outstanding requests for now */
2055 reqs = 32;
2056 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2057 reqs = 1;
2058 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2059
2060 /* Only allow access to user-accessible pages */
2061 ret = pci_enable_pasid(pdev, 0);
2062 if (ret)
2063 goto out_err;
2064
2065 /* First reset the PRI state of the device */
2066 ret = pci_reset_pri(pdev);
2067 if (ret)
2068 goto out_err;
2069
2070 /* Enable PRI */
2071 ret = pci_enable_pri(pdev, reqs);
2072 if (ret)
2073 goto out_err;
2074
2075 if (reset_enable) {
2076 ret = pri_reset_while_enabled(pdev);
2077 if (ret)
2078 goto out_err;
2079 }
2080
2081 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2082 if (ret)
2083 goto out_err;
2084
2085 return 0;
2086
2087 out_err:
2088 pci_disable_pri(pdev);
2089 pci_disable_pasid(pdev);
2090
2091 return ret;
2092 }
2093
2094 /*
2095 * If a device is not yet associated with a domain, this function makes the
2096 * device visible in the domain
2097 */
2098 static int attach_device(struct device *dev,
2099 struct protection_domain *domain)
2100 {
2101 struct pci_dev *pdev;
2102 struct iommu_dev_data *dev_data;
2103 unsigned long flags;
2104 int ret;
2105
2106 dev_data = get_dev_data(dev);
2107
2108 if (!dev_is_pci(dev))
2109 goto skip_ats_check;
2110
2111 pdev = to_pci_dev(dev);
2112 if (domain->flags & PD_IOMMUV2_MASK) {
2113 if (!dev_data->passthrough)
2114 return -EINVAL;
2115
2116 if (dev_data->iommu_v2) {
2117 if (pdev_iommuv2_enable(pdev) != 0)
2118 return -EINVAL;
2119
2120 dev_data->ats.enabled = true;
2121 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2122 dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
2123 }
2124 } else if (amd_iommu_iotlb_sup &&
2125 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2126 dev_data->ats.enabled = true;
2127 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2128 }
2129
2130 skip_ats_check:
2131 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2132 ret = __attach_device(dev_data, domain);
2133 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2134
2135 /*
2136 * We might boot into a crash-kernel here. The crashed kernel
2137 * left the caches in the IOMMU dirty. So we have to flush
2138 * here to evict all dirty stuff.
2139 */
2140 domain_flush_tlb_pde(domain);
2141
2142 return ret;
2143 }
2144
2145 /*
2146 * Removes a device from a protection domain (unlocked)
2147 */
2148 static void __detach_device(struct iommu_dev_data *dev_data)
2149 {
2150 struct protection_domain *domain;
2151
2152 domain = dev_data->domain;
2153
2154 spin_lock(&domain->lock);
2155
2156 do_detach(dev_data);
2157
2158 spin_unlock(&domain->lock);
2159 }
2160
2161 /*
2162 * Removes a device from a protection domain (with devtable_lock held)
2163 */
2164 static void detach_device(struct device *dev)
2165 {
2166 struct protection_domain *domain;
2167 struct iommu_dev_data *dev_data;
2168 unsigned long flags;
2169
2170 dev_data = get_dev_data(dev);
2171 domain = dev_data->domain;
2172
2173 /*
2174 * First check if the device is still attached. It might already
2175 * be detached from its domain because the generic
2176 * iommu_detach_group code detached it and we try again here in
2177 * our alias handling.
2178 */
2179 if (WARN_ON(!dev_data->domain))
2180 return;
2181
2182 /* lock device table */
2183 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2184 __detach_device(dev_data);
2185 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2186
2187 if (!dev_is_pci(dev))
2188 return;
2189
2190 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2191 pdev_iommuv2_disable(to_pci_dev(dev));
2192 else if (dev_data->ats.enabled)
2193 pci_disable_ats(to_pci_dev(dev));
2194
2195 dev_data->ats.enabled = false;
2196 }
2197
2198 static int amd_iommu_add_device(struct device *dev)
2199 {
2200 struct iommu_dev_data *dev_data;
2201 struct iommu_domain *domain;
2202 struct amd_iommu *iommu;
2203 int ret, devid;
2204
2205 if (!check_device(dev) || get_dev_data(dev))
2206 return 0;
2207
2208 devid = get_device_id(dev);
2209 if (devid < 0)
2210 return devid;
2211
2212 iommu = amd_iommu_rlookup_table[devid];
2213
2214 ret = iommu_init_device(dev);
2215 if (ret) {
2216 if (ret != -ENOTSUPP)
2217 dev_err(dev, "Failed to initialize - trying to proceed anyway\n");
2218
2219 iommu_ignore_device(dev);
2220 dev->dma_ops = NULL;
2221 goto out;
2222 }
2223 init_iommu_group(dev);
2224
2225 dev_data = get_dev_data(dev);
2226
2227 BUG_ON(!dev_data);
2228
2229 if (iommu_pass_through || dev_data->iommu_v2)
2230 iommu_request_dm_for_dev(dev);
2231
2232 /* Domains are initialized for this device - have a look what we ended up with */
2233 domain = iommu_get_domain_for_dev(dev);
2234 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2235 dev_data->passthrough = true;
2236 else
2237 dev->dma_ops = &amd_iommu_dma_ops;
2238
2239 out:
2240 iommu_completion_wait(iommu);
2241
2242 return 0;
2243 }
2244
2245 static void amd_iommu_remove_device(struct device *dev)
2246 {
2247 struct amd_iommu *iommu;
2248 int devid;
2249
2250 if (!check_device(dev))
2251 return;
2252
2253 devid = get_device_id(dev);
2254 if (devid < 0)
2255 return;
2256
2257 iommu = amd_iommu_rlookup_table[devid];
2258
2259 iommu_uninit_device(dev);
2260 iommu_completion_wait(iommu);
2261 }
2262
2263 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2264 {
2265 if (dev_is_pci(dev))
2266 return pci_device_group(dev);
2267
2268 return acpihid_device_group(dev);
2269 }
2270
2271 /*****************************************************************************
2272 *
2273 * The next functions belong to the dma_ops mapping/unmapping code.
2274 *
2275 *****************************************************************************/
2276
2277 /*
2278 * In the dma_ops path we only have the struct device. This function
2279 * finds the corresponding IOMMU, the protection domain and the
2280 * requestor id for a given device.
2281 * If the device is not yet associated with a domain this is also done
2282 * in this function.
2283 */
2284 static struct protection_domain *get_domain(struct device *dev)
2285 {
2286 struct protection_domain *domain;
2287 struct iommu_domain *io_domain;
2288
2289 if (!check_device(dev))
2290 return ERR_PTR(-EINVAL);
2291
2292 domain = get_dev_data(dev)->domain;
2293 if (domain == NULL && get_dev_data(dev)->defer_attach) {
2294 get_dev_data(dev)->defer_attach = false;
2295 io_domain = iommu_get_domain_for_dev(dev);
2296 domain = to_pdomain(io_domain);
2297 attach_device(dev, domain);
2298 }
2299 if (domain == NULL)
2300 return ERR_PTR(-EBUSY);
2301
2302 if (!dma_ops_domain(domain))
2303 return ERR_PTR(-EBUSY);
2304
2305 return domain;
2306 }
2307
2308 static void update_device_table(struct protection_domain *domain)
2309 {
2310 struct iommu_dev_data *dev_data;
2311
2312 list_for_each_entry(dev_data, &domain->dev_list, list) {
2313 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled,
2314 dev_data->iommu_v2);
2315
2316 if (dev_data->devid == dev_data->alias)
2317 continue;
2318
2319 /* There is an alias, update device table entry for it */
2320 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled,
2321 dev_data->iommu_v2);
2322 }
2323 }
2324
2325 static void update_domain(struct protection_domain *domain)
2326 {
2327 if (!domain->updated)
2328 return;
2329
2330 update_device_table(domain);
2331
2332 domain_flush_devices(domain);
2333 domain_flush_tlb_pde(domain);
2334
2335 domain->updated = false;
2336 }
2337
2338 static int dir2prot(enum dma_data_direction direction)
2339 {
2340 if (direction == DMA_TO_DEVICE)
2341 return IOMMU_PROT_IR;
2342 else if (direction == DMA_FROM_DEVICE)
2343 return IOMMU_PROT_IW;
2344 else if (direction == DMA_BIDIRECTIONAL)
2345 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2346 else
2347 return 0;
2348 }
2349
2350 /*
2351 * This function contains common code for mapping of a physically
2352 * contiguous memory region into DMA address space. It is used by all
2353 * mapping functions provided with this IOMMU driver.
2354 * Must be called with the domain lock held.
2355 */
2356 static dma_addr_t __map_single(struct device *dev,
2357 struct dma_ops_domain *dma_dom,
2358 phys_addr_t paddr,
2359 size_t size,
2360 enum dma_data_direction direction,
2361 u64 dma_mask)
2362 {
2363 dma_addr_t offset = paddr & ~PAGE_MASK;
2364 dma_addr_t address, start, ret;
2365 unsigned int pages;
2366 int prot = 0;
2367 int i;
2368
2369 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2370 paddr &= PAGE_MASK;
2371
2372 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2373 if (!address)
2374 goto out;
2375
2376 prot = dir2prot(direction);
2377
2378 start = address;
2379 for (i = 0; i < pages; ++i) {
2380 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2381 PAGE_SIZE, prot, GFP_ATOMIC);
2382 if (ret)
2383 goto out_unmap;
2384
2385 paddr += PAGE_SIZE;
2386 start += PAGE_SIZE;
2387 }
2388 address += offset;
2389
2390 domain_flush_np_cache(&dma_dom->domain, address, size);
2391
2392 out:
2393 return address;
2394
2395 out_unmap:
2396
2397 for (--i; i >= 0; --i) {
2398 start -= PAGE_SIZE;
2399 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2400 }
2401
2402 domain_flush_tlb(&dma_dom->domain);
2403 domain_flush_complete(&dma_dom->domain);
2404
2405 dma_ops_free_iova(dma_dom, address, pages);
2406
2407 return DMA_MAPPING_ERROR;
2408 }
2409
2410 /*
2411 * Does the reverse of the __map_single function. Must be called with
2412 * the domain lock held too
2413 */
2414 static void __unmap_single(struct dma_ops_domain *dma_dom,
2415 dma_addr_t dma_addr,
2416 size_t size,
2417 int dir)
2418 {
2419 dma_addr_t i, start;
2420 unsigned int pages;
2421
2422 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2423 dma_addr &= PAGE_MASK;
2424 start = dma_addr;
2425
2426 for (i = 0; i < pages; ++i) {
2427 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2428 start += PAGE_SIZE;
2429 }
2430
2431 if (amd_iommu_unmap_flush) {
2432 domain_flush_tlb(&dma_dom->domain);
2433 domain_flush_complete(&dma_dom->domain);
2434 dma_ops_free_iova(dma_dom, dma_addr, pages);
2435 } else {
2436 pages = __roundup_pow_of_two(pages);
2437 queue_iova(&dma_dom->iovad, dma_addr >> PAGE_SHIFT, pages, 0);
2438 }
2439 }
2440
2441 /*
2442 * The exported map_single function for dma_ops.
2443 */
2444 static dma_addr_t map_page(struct device *dev, struct page *page,
2445 unsigned long offset, size_t size,
2446 enum dma_data_direction dir,
2447 unsigned long attrs)
2448 {
2449 phys_addr_t paddr = page_to_phys(page) + offset;
2450 struct protection_domain *domain;
2451 struct dma_ops_domain *dma_dom;
2452 u64 dma_mask;
2453
2454 domain = get_domain(dev);
2455 if (PTR_ERR(domain) == -EINVAL)
2456 return (dma_addr_t)paddr;
2457 else if (IS_ERR(domain))
2458 return DMA_MAPPING_ERROR;
2459
2460 dma_mask = *dev->dma_mask;
2461 dma_dom = to_dma_ops_domain(domain);
2462
2463 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2464 }
2465
2466 /*
2467 * The exported unmap_single function for dma_ops.
2468 */
2469 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2470 enum dma_data_direction dir, unsigned long attrs)
2471 {
2472 struct protection_domain *domain;
2473 struct dma_ops_domain *dma_dom;
2474
2475 domain = get_domain(dev);
2476 if (IS_ERR(domain))
2477 return;
2478
2479 dma_dom = to_dma_ops_domain(domain);
2480
2481 __unmap_single(dma_dom, dma_addr, size, dir);
2482 }
2483
2484 static int sg_num_pages(struct device *dev,
2485 struct scatterlist *sglist,
2486 int nelems)
2487 {
2488 unsigned long mask, boundary_size;
2489 struct scatterlist *s;
2490 int i, npages = 0;
2491
2492 mask = dma_get_seg_boundary(dev);
2493 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2494 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2495
2496 for_each_sg(sglist, s, nelems, i) {
2497 int p, n;
2498
2499 s->dma_address = npages << PAGE_SHIFT;
2500 p = npages % boundary_size;
2501 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2502 if (p + n > boundary_size)
2503 npages += boundary_size - p;
2504 npages += n;
2505 }
2506
2507 return npages;
2508 }
2509
2510 /*
2511 * The exported map_sg function for dma_ops (handles scatter-gather
2512 * lists).
2513 */
2514 static int map_sg(struct device *dev, struct scatterlist *sglist,
2515 int nelems, enum dma_data_direction direction,
2516 unsigned long attrs)
2517 {
2518 int mapped_pages = 0, npages = 0, prot = 0, i;
2519 struct protection_domain *domain;
2520 struct dma_ops_domain *dma_dom;
2521 struct scatterlist *s;
2522 unsigned long address;
2523 u64 dma_mask;
2524 int ret;
2525
2526 domain = get_domain(dev);
2527 if (IS_ERR(domain))
2528 return 0;
2529
2530 dma_dom = to_dma_ops_domain(domain);
2531 dma_mask = *dev->dma_mask;
2532
2533 npages = sg_num_pages(dev, sglist, nelems);
2534
2535 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2536 if (!address)
2537 goto out_err;
2538
2539 prot = dir2prot(direction);
2540
2541 /* Map all sg entries */
2542 for_each_sg(sglist, s, nelems, i) {
2543 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2544
2545 for (j = 0; j < pages; ++j) {
2546 unsigned long bus_addr, phys_addr;
2547
2548 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2549 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2550 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2551 if (ret)
2552 goto out_unmap;
2553
2554 mapped_pages += 1;
2555 }
2556 }
2557
2558 /* Everything is mapped - write the right values into s->dma_address */
2559 for_each_sg(sglist, s, nelems, i) {
2560 /*
2561 * Add in the remaining piece of the scatter-gather offset that
2562 * was masked out when we were determining the physical address
2563 * via (sg_phys(s) & PAGE_MASK) earlier.
2564 */
2565 s->dma_address += address + (s->offset & ~PAGE_MASK);
2566 s->dma_length = s->length;
2567 }
2568
2569 if (s)
2570 domain_flush_np_cache(domain, s->dma_address, s->dma_length);
2571
2572 return nelems;
2573
2574 out_unmap:
2575 dev_err(dev, "IOMMU mapping error in map_sg (io-pages: %d reason: %d)\n",
2576 npages, ret);
2577
2578 for_each_sg(sglist, s, nelems, i) {
2579 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2580
2581 for (j = 0; j < pages; ++j) {
2582 unsigned long bus_addr;
2583
2584 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2585 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2586
2587 if (--mapped_pages == 0)
2588 goto out_free_iova;
2589 }
2590 }
2591
2592 out_free_iova:
2593 free_iova_fast(&dma_dom->iovad, address >> PAGE_SHIFT, npages);
2594
2595 out_err:
2596 return 0;
2597 }
2598
2599 /*
2600 * The exported map_sg function for dma_ops (handles scatter-gather
2601 * lists).
2602 */
2603 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2604 int nelems, enum dma_data_direction dir,
2605 unsigned long attrs)
2606 {
2607 struct protection_domain *domain;
2608 struct dma_ops_domain *dma_dom;
2609 unsigned long startaddr;
2610 int npages;
2611
2612 domain = get_domain(dev);
2613 if (IS_ERR(domain))
2614 return;
2615
2616 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2617 dma_dom = to_dma_ops_domain(domain);
2618 npages = sg_num_pages(dev, sglist, nelems);
2619
2620 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2621 }
2622
2623 /*
2624 * The exported alloc_coherent function for dma_ops.
2625 */
2626 static void *alloc_coherent(struct device *dev, size_t size,
2627 dma_addr_t *dma_addr, gfp_t flag,
2628 unsigned long attrs)
2629 {
2630 u64 dma_mask = dev->coherent_dma_mask;
2631 struct protection_domain *domain;
2632 struct dma_ops_domain *dma_dom;
2633 struct page *page;
2634
2635 domain = get_domain(dev);
2636 if (PTR_ERR(domain) == -EINVAL) {
2637 page = alloc_pages(flag, get_order(size));
2638 *dma_addr = page_to_phys(page);
2639 return page_address(page);
2640 } else if (IS_ERR(domain))
2641 return NULL;
2642
2643 dma_dom = to_dma_ops_domain(domain);
2644 size = PAGE_ALIGN(size);
2645 dma_mask = dev->coherent_dma_mask;
2646 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2647 flag |= __GFP_ZERO;
2648
2649 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2650 if (!page) {
2651 if (!gfpflags_allow_blocking(flag))
2652 return NULL;
2653
2654 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2655 get_order(size), flag & __GFP_NOWARN);
2656 if (!page)
2657 return NULL;
2658 }
2659
2660 if (!dma_mask)
2661 dma_mask = *dev->dma_mask;
2662
2663 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2664 size, DMA_BIDIRECTIONAL, dma_mask);
2665
2666 if (*dma_addr == DMA_MAPPING_ERROR)
2667 goto out_free;
2668
2669 return page_address(page);
2670
2671 out_free:
2672
2673 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2674 __free_pages(page, get_order(size));
2675
2676 return NULL;
2677 }
2678
2679 /*
2680 * The exported free_coherent function for dma_ops.
2681 */
2682 static void free_coherent(struct device *dev, size_t size,
2683 void *virt_addr, dma_addr_t dma_addr,
2684 unsigned long attrs)
2685 {
2686 struct protection_domain *domain;
2687 struct dma_ops_domain *dma_dom;
2688 struct page *page;
2689
2690 page = virt_to_page(virt_addr);
2691 size = PAGE_ALIGN(size);
2692
2693 domain = get_domain(dev);
2694 if (IS_ERR(domain))
2695 goto free_mem;
2696
2697 dma_dom = to_dma_ops_domain(domain);
2698
2699 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2700
2701 free_mem:
2702 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2703 __free_pages(page, get_order(size));
2704 }
2705
2706 /*
2707 * This function is called by the DMA layer to find out if we can handle a
2708 * particular device. It is part of the dma_ops.
2709 */
2710 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2711 {
2712 if (!dma_direct_supported(dev, mask))
2713 return 0;
2714 return check_device(dev);
2715 }
2716
2717 static const struct dma_map_ops amd_iommu_dma_ops = {
2718 .alloc = alloc_coherent,
2719 .free = free_coherent,
2720 .map_page = map_page,
2721 .unmap_page = unmap_page,
2722 .map_sg = map_sg,
2723 .unmap_sg = unmap_sg,
2724 .dma_supported = amd_iommu_dma_supported,
2725 };
2726
2727 static int init_reserved_iova_ranges(void)
2728 {
2729 struct pci_dev *pdev = NULL;
2730 struct iova *val;
2731
2732 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE, IOVA_START_PFN);
2733
2734 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2735 &reserved_rbtree_key);
2736
2737 /* MSI memory range */
2738 val = reserve_iova(&reserved_iova_ranges,
2739 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2740 if (!val) {
2741 pr_err("Reserving MSI range failed\n");
2742 return -ENOMEM;
2743 }
2744
2745 /* HT memory range */
2746 val = reserve_iova(&reserved_iova_ranges,
2747 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2748 if (!val) {
2749 pr_err("Reserving HT range failed\n");
2750 return -ENOMEM;
2751 }
2752
2753 /*
2754 * Memory used for PCI resources
2755 * FIXME: Check whether we can reserve the PCI-hole completly
2756 */
2757 for_each_pci_dev(pdev) {
2758 int i;
2759
2760 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2761 struct resource *r = &pdev->resource[i];
2762
2763 if (!(r->flags & IORESOURCE_MEM))
2764 continue;
2765
2766 val = reserve_iova(&reserved_iova_ranges,
2767 IOVA_PFN(r->start),
2768 IOVA_PFN(r->end));
2769 if (!val) {
2770 pci_err(pdev, "Reserve pci-resource range %pR failed\n", r);
2771 return -ENOMEM;
2772 }
2773 }
2774 }
2775
2776 return 0;
2777 }
2778
2779 int __init amd_iommu_init_api(void)
2780 {
2781 int ret, err = 0;
2782
2783 ret = iova_cache_get();
2784 if (ret)
2785 return ret;
2786
2787 ret = init_reserved_iova_ranges();
2788 if (ret)
2789 return ret;
2790
2791 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2792 if (err)
2793 return err;
2794 #ifdef CONFIG_ARM_AMBA
2795 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2796 if (err)
2797 return err;
2798 #endif
2799 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2800 if (err)
2801 return err;
2802
2803 return 0;
2804 }
2805
2806 int __init amd_iommu_init_dma_ops(void)
2807 {
2808 swiotlb = (iommu_pass_through || sme_me_mask) ? 1 : 0;
2809 iommu_detected = 1;
2810
2811 if (amd_iommu_unmap_flush)
2812 pr_info("IO/TLB flush on unmap enabled\n");
2813 else
2814 pr_info("Lazy IO/TLB flushing enabled\n");
2815
2816 return 0;
2817
2818 }
2819
2820 /*****************************************************************************
2821 *
2822 * The following functions belong to the exported interface of AMD IOMMU
2823 *
2824 * This interface allows access to lower level functions of the IOMMU
2825 * like protection domain handling and assignement of devices to domains
2826 * which is not possible with the dma_ops interface.
2827 *
2828 *****************************************************************************/
2829
2830 static void cleanup_domain(struct protection_domain *domain)
2831 {
2832 struct iommu_dev_data *entry;
2833 unsigned long flags;
2834
2835 spin_lock_irqsave(&amd_iommu_devtable_lock, flags);
2836
2837 while (!list_empty(&domain->dev_list)) {
2838 entry = list_first_entry(&domain->dev_list,
2839 struct iommu_dev_data, list);
2840 BUG_ON(!entry->domain);
2841 __detach_device(entry);
2842 }
2843
2844 spin_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2845 }
2846
2847 static void protection_domain_free(struct protection_domain *domain)
2848 {
2849 if (!domain)
2850 return;
2851
2852 if (domain->id)
2853 domain_id_free(domain->id);
2854
2855 kfree(domain);
2856 }
2857
2858 static int protection_domain_init(struct protection_domain *domain)
2859 {
2860 spin_lock_init(&domain->lock);
2861 mutex_init(&domain->api_lock);
2862 domain->id = domain_id_alloc();
2863 if (!domain->id)
2864 return -ENOMEM;
2865 INIT_LIST_HEAD(&domain->dev_list);
2866
2867 return 0;
2868 }
2869
2870 static struct protection_domain *protection_domain_alloc(void)
2871 {
2872 struct protection_domain *domain;
2873
2874 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2875 if (!domain)
2876 return NULL;
2877
2878 if (protection_domain_init(domain))
2879 goto out_err;
2880
2881 return domain;
2882
2883 out_err:
2884 kfree(domain);
2885
2886 return NULL;
2887 }
2888
2889 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2890 {
2891 struct protection_domain *pdomain;
2892 struct dma_ops_domain *dma_domain;
2893
2894 switch (type) {
2895 case IOMMU_DOMAIN_UNMANAGED:
2896 pdomain = protection_domain_alloc();
2897 if (!pdomain)
2898 return NULL;
2899
2900 pdomain->mode = PAGE_MODE_3_LEVEL;
2901 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2902 if (!pdomain->pt_root) {
2903 protection_domain_free(pdomain);
2904 return NULL;
2905 }
2906
2907 pdomain->domain.geometry.aperture_start = 0;
2908 pdomain->domain.geometry.aperture_end = ~0ULL;
2909 pdomain->domain.geometry.force_aperture = true;
2910
2911 break;
2912 case IOMMU_DOMAIN_DMA:
2913 dma_domain = dma_ops_domain_alloc();
2914 if (!dma_domain) {
2915 pr_err("Failed to allocate\n");
2916 return NULL;
2917 }
2918 pdomain = &dma_domain->domain;
2919 break;
2920 case IOMMU_DOMAIN_IDENTITY:
2921 pdomain = protection_domain_alloc();
2922 if (!pdomain)
2923 return NULL;
2924
2925 pdomain->mode = PAGE_MODE_NONE;
2926 break;
2927 default:
2928 return NULL;
2929 }
2930
2931 return &pdomain->domain;
2932 }
2933
2934 static void amd_iommu_domain_free(struct iommu_domain *dom)
2935 {
2936 struct protection_domain *domain;
2937 struct dma_ops_domain *dma_dom;
2938
2939 domain = to_pdomain(dom);
2940
2941 if (domain->dev_cnt > 0)
2942 cleanup_domain(domain);
2943
2944 BUG_ON(domain->dev_cnt != 0);
2945
2946 if (!dom)
2947 return;
2948
2949 switch (dom->type) {
2950 case IOMMU_DOMAIN_DMA:
2951 /* Now release the domain */
2952 dma_dom = to_dma_ops_domain(domain);
2953 dma_ops_domain_free(dma_dom);
2954 break;
2955 default:
2956 if (domain->mode != PAGE_MODE_NONE)
2957 free_pagetable(domain);
2958
2959 if (domain->flags & PD_IOMMUV2_MASK)
2960 free_gcr3_table(domain);
2961
2962 protection_domain_free(domain);
2963 break;
2964 }
2965 }
2966
2967 static void amd_iommu_detach_device(struct iommu_domain *dom,
2968 struct device *dev)
2969 {
2970 struct iommu_dev_data *dev_data = dev->archdata.iommu;
2971 struct amd_iommu *iommu;
2972 int devid;
2973
2974 if (!check_device(dev))
2975 return;
2976
2977 devid = get_device_id(dev);
2978 if (devid < 0)
2979 return;
2980
2981 if (dev_data->domain != NULL)
2982 detach_device(dev);
2983
2984 iommu = amd_iommu_rlookup_table[devid];
2985 if (!iommu)
2986 return;
2987
2988 #ifdef CONFIG_IRQ_REMAP
2989 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
2990 (dom->type == IOMMU_DOMAIN_UNMANAGED))
2991 dev_data->use_vapic = 0;
2992 #endif
2993
2994 iommu_completion_wait(iommu);
2995 }
2996
2997 static int amd_iommu_attach_device(struct iommu_domain *dom,
2998 struct device *dev)
2999 {
3000 struct protection_domain *domain = to_pdomain(dom);
3001 struct iommu_dev_data *dev_data;
3002 struct amd_iommu *iommu;
3003 int ret;
3004
3005 if (!check_device(dev))
3006 return -EINVAL;
3007
3008 dev_data = dev->archdata.iommu;
3009
3010 iommu = amd_iommu_rlookup_table[dev_data->devid];
3011 if (!iommu)
3012 return -EINVAL;
3013
3014 if (dev_data->domain)
3015 detach_device(dev);
3016
3017 ret = attach_device(dev, domain);
3018
3019 #ifdef CONFIG_IRQ_REMAP
3020 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3021 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3022 dev_data->use_vapic = 1;
3023 else
3024 dev_data->use_vapic = 0;
3025 }
3026 #endif
3027
3028 iommu_completion_wait(iommu);
3029
3030 return ret;
3031 }
3032
3033 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3034 phys_addr_t paddr, size_t page_size, int iommu_prot)
3035 {
3036 struct protection_domain *domain = to_pdomain(dom);
3037 int prot = 0;
3038 int ret;
3039
3040 if (domain->mode == PAGE_MODE_NONE)
3041 return -EINVAL;
3042
3043 if (iommu_prot & IOMMU_READ)
3044 prot |= IOMMU_PROT_IR;
3045 if (iommu_prot & IOMMU_WRITE)
3046 prot |= IOMMU_PROT_IW;
3047
3048 mutex_lock(&domain->api_lock);
3049 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3050 mutex_unlock(&domain->api_lock);
3051
3052 domain_flush_np_cache(domain, iova, page_size);
3053
3054 return ret;
3055 }
3056
3057 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3058 size_t page_size)
3059 {
3060 struct protection_domain *domain = to_pdomain(dom);
3061 size_t unmap_size;
3062
3063 if (domain->mode == PAGE_MODE_NONE)
3064 return 0;
3065
3066 mutex_lock(&domain->api_lock);
3067 unmap_size = iommu_unmap_page(domain, iova, page_size);
3068 mutex_unlock(&domain->api_lock);
3069
3070 return unmap_size;
3071 }
3072
3073 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3074 dma_addr_t iova)
3075 {
3076 struct protection_domain *domain = to_pdomain(dom);
3077 unsigned long offset_mask, pte_pgsize;
3078 u64 *pte, __pte;
3079
3080 if (domain->mode == PAGE_MODE_NONE)
3081 return iova;
3082
3083 pte = fetch_pte(domain, iova, &pte_pgsize);
3084
3085 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3086 return 0;
3087
3088 offset_mask = pte_pgsize - 1;
3089 __pte = __sme_clr(*pte & PM_ADDR_MASK);
3090
3091 return (__pte & ~offset_mask) | (iova & offset_mask);
3092 }
3093
3094 static bool amd_iommu_capable(enum iommu_cap cap)
3095 {
3096 switch (cap) {
3097 case IOMMU_CAP_CACHE_COHERENCY:
3098 return true;
3099 case IOMMU_CAP_INTR_REMAP:
3100 return (irq_remapping_enabled == 1);
3101 case IOMMU_CAP_NOEXEC:
3102 return false;
3103 default:
3104 break;
3105 }
3106
3107 return false;
3108 }
3109
3110 static void amd_iommu_get_resv_regions(struct device *dev,
3111 struct list_head *head)
3112 {
3113 struct iommu_resv_region *region;
3114 struct unity_map_entry *entry;
3115 int devid;
3116
3117 devid = get_device_id(dev);
3118 if (devid < 0)
3119 return;
3120
3121 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3122 int type, prot = 0;
3123 size_t length;
3124
3125 if (devid < entry->devid_start || devid > entry->devid_end)
3126 continue;
3127
3128 type = IOMMU_RESV_DIRECT;
3129 length = entry->address_end - entry->address_start;
3130 if (entry->prot & IOMMU_PROT_IR)
3131 prot |= IOMMU_READ;
3132 if (entry->prot & IOMMU_PROT_IW)
3133 prot |= IOMMU_WRITE;
3134 if (entry->prot & IOMMU_UNITY_MAP_FLAG_EXCL_RANGE)
3135 /* Exclusion range */
3136 type = IOMMU_RESV_RESERVED;
3137
3138 region = iommu_alloc_resv_region(entry->address_start,
3139 length, prot, type);
3140 if (!region) {
3141 dev_err(dev, "Out of memory allocating dm-regions\n");
3142 return;
3143 }
3144 list_add_tail(&region->list, head);
3145 }
3146
3147 region = iommu_alloc_resv_region(MSI_RANGE_START,
3148 MSI_RANGE_END - MSI_RANGE_START + 1,
3149 0, IOMMU_RESV_MSI);
3150 if (!region)
3151 return;
3152 list_add_tail(&region->list, head);
3153
3154 region = iommu_alloc_resv_region(HT_RANGE_START,
3155 HT_RANGE_END - HT_RANGE_START + 1,
3156 0, IOMMU_RESV_RESERVED);
3157 if (!region)
3158 return;
3159 list_add_tail(&region->list, head);
3160 }
3161
3162 static void amd_iommu_put_resv_regions(struct device *dev,
3163 struct list_head *head)
3164 {
3165 struct iommu_resv_region *entry, *next;
3166
3167 list_for_each_entry_safe(entry, next, head, list)
3168 kfree(entry);
3169 }
3170
3171 static void amd_iommu_apply_resv_region(struct device *dev,
3172 struct iommu_domain *domain,
3173 struct iommu_resv_region *region)
3174 {
3175 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3176 unsigned long start, end;
3177
3178 start = IOVA_PFN(region->start);
3179 end = IOVA_PFN(region->start + region->length - 1);
3180
3181 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3182 }
3183
3184 static bool amd_iommu_is_attach_deferred(struct iommu_domain *domain,
3185 struct device *dev)
3186 {
3187 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3188 return dev_data->defer_attach;
3189 }
3190
3191 static void amd_iommu_flush_iotlb_all(struct iommu_domain *domain)
3192 {
3193 struct protection_domain *dom = to_pdomain(domain);
3194
3195 domain_flush_tlb_pde(dom);
3196 domain_flush_complete(dom);
3197 }
3198
3199 static void amd_iommu_iotlb_range_add(struct iommu_domain *domain,
3200 unsigned long iova, size_t size)
3201 {
3202 }
3203
3204 const struct iommu_ops amd_iommu_ops = {
3205 .capable = amd_iommu_capable,
3206 .domain_alloc = amd_iommu_domain_alloc,
3207 .domain_free = amd_iommu_domain_free,
3208 .attach_dev = amd_iommu_attach_device,
3209 .detach_dev = amd_iommu_detach_device,
3210 .map = amd_iommu_map,
3211 .unmap = amd_iommu_unmap,
3212 .iova_to_phys = amd_iommu_iova_to_phys,
3213 .add_device = amd_iommu_add_device,
3214 .remove_device = amd_iommu_remove_device,
3215 .device_group = amd_iommu_device_group,
3216 .get_resv_regions = amd_iommu_get_resv_regions,
3217 .put_resv_regions = amd_iommu_put_resv_regions,
3218 .apply_resv_region = amd_iommu_apply_resv_region,
3219 .is_attach_deferred = amd_iommu_is_attach_deferred,
3220 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3221 .flush_iotlb_all = amd_iommu_flush_iotlb_all,
3222 .iotlb_range_add = amd_iommu_iotlb_range_add,
3223 .iotlb_sync = amd_iommu_flush_iotlb_all,
3224 };
3225
3226 /*****************************************************************************
3227 *
3228 * The next functions do a basic initialization of IOMMU for pass through
3229 * mode
3230 *
3231 * In passthrough mode the IOMMU is initialized and enabled but not used for
3232 * DMA-API translation.
3233 *
3234 *****************************************************************************/
3235
3236 /* IOMMUv2 specific functions */
3237 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3238 {
3239 return atomic_notifier_chain_register(&ppr_notifier, nb);
3240 }
3241 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3242
3243 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3244 {
3245 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3246 }
3247 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3248
3249 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3250 {
3251 struct protection_domain *domain = to_pdomain(dom);
3252 unsigned long flags;
3253
3254 spin_lock_irqsave(&domain->lock, flags);
3255
3256 /* Update data structure */
3257 domain->mode = PAGE_MODE_NONE;
3258 domain->updated = true;
3259
3260 /* Make changes visible to IOMMUs */
3261 update_domain(domain);
3262
3263 /* Page-table is not visible to IOMMU anymore, so free it */
3264 free_pagetable(domain);
3265
3266 spin_unlock_irqrestore(&domain->lock, flags);
3267 }
3268 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3269
3270 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3271 {
3272 struct protection_domain *domain = to_pdomain(dom);
3273 unsigned long flags;
3274 int levels, ret;
3275
3276 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3277 return -EINVAL;
3278
3279 /* Number of GCR3 table levels required */
3280 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3281 levels += 1;
3282
3283 if (levels > amd_iommu_max_glx_val)
3284 return -EINVAL;
3285
3286 spin_lock_irqsave(&domain->lock, flags);
3287
3288 /*
3289 * Save us all sanity checks whether devices already in the
3290 * domain support IOMMUv2. Just force that the domain has no
3291 * devices attached when it is switched into IOMMUv2 mode.
3292 */
3293 ret = -EBUSY;
3294 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3295 goto out;
3296
3297 ret = -ENOMEM;
3298 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3299 if (domain->gcr3_tbl == NULL)
3300 goto out;
3301
3302 domain->glx = levels;
3303 domain->flags |= PD_IOMMUV2_MASK;
3304 domain->updated = true;
3305
3306 update_domain(domain);
3307
3308 ret = 0;
3309
3310 out:
3311 spin_unlock_irqrestore(&domain->lock, flags);
3312
3313 return ret;
3314 }
3315 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3316
3317 static int __flush_pasid(struct protection_domain *domain, int pasid,
3318 u64 address, bool size)
3319 {
3320 struct iommu_dev_data *dev_data;
3321 struct iommu_cmd cmd;
3322 int i, ret;
3323
3324 if (!(domain->flags & PD_IOMMUV2_MASK))
3325 return -EINVAL;
3326
3327 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3328
3329 /*
3330 * IOMMU TLB needs to be flushed before Device TLB to
3331 * prevent device TLB refill from IOMMU TLB
3332 */
3333 for (i = 0; i < amd_iommu_get_num_iommus(); ++i) {
3334 if (domain->dev_iommu[i] == 0)
3335 continue;
3336
3337 ret = iommu_queue_command(amd_iommus[i], &cmd);
3338 if (ret != 0)
3339 goto out;
3340 }
3341
3342 /* Wait until IOMMU TLB flushes are complete */
3343 domain_flush_complete(domain);
3344
3345 /* Now flush device TLBs */
3346 list_for_each_entry(dev_data, &domain->dev_list, list) {
3347 struct amd_iommu *iommu;
3348 int qdep;
3349
3350 /*
3351 There might be non-IOMMUv2 capable devices in an IOMMUv2
3352 * domain.
3353 */
3354 if (!dev_data->ats.enabled)
3355 continue;
3356
3357 qdep = dev_data->ats.qdep;
3358 iommu = amd_iommu_rlookup_table[dev_data->devid];
3359
3360 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3361 qdep, address, size);
3362
3363 ret = iommu_queue_command(iommu, &cmd);
3364 if (ret != 0)
3365 goto out;
3366 }
3367
3368 /* Wait until all device TLBs are flushed */
3369 domain_flush_complete(domain);
3370
3371 ret = 0;
3372
3373 out:
3374
3375 return ret;
3376 }
3377
3378 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3379 u64 address)
3380 {
3381 return __flush_pasid(domain, pasid, address, false);
3382 }
3383
3384 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3385 u64 address)
3386 {
3387 struct protection_domain *domain = to_pdomain(dom);
3388 unsigned long flags;
3389 int ret;
3390
3391 spin_lock_irqsave(&domain->lock, flags);
3392 ret = __amd_iommu_flush_page(domain, pasid, address);
3393 spin_unlock_irqrestore(&domain->lock, flags);
3394
3395 return ret;
3396 }
3397 EXPORT_SYMBOL(amd_iommu_flush_page);
3398
3399 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3400 {
3401 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3402 true);
3403 }
3404
3405 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3406 {
3407 struct protection_domain *domain = to_pdomain(dom);
3408 unsigned long flags;
3409 int ret;
3410
3411 spin_lock_irqsave(&domain->lock, flags);
3412 ret = __amd_iommu_flush_tlb(domain, pasid);
3413 spin_unlock_irqrestore(&domain->lock, flags);
3414
3415 return ret;
3416 }
3417 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3418
3419 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3420 {
3421 int index;
3422 u64 *pte;
3423
3424 while (true) {
3425
3426 index = (pasid >> (9 * level)) & 0x1ff;
3427 pte = &root[index];
3428
3429 if (level == 0)
3430 break;
3431
3432 if (!(*pte & GCR3_VALID)) {
3433 if (!alloc)
3434 return NULL;
3435
3436 root = (void *)get_zeroed_page(GFP_ATOMIC);
3437 if (root == NULL)
3438 return NULL;
3439
3440 *pte = iommu_virt_to_phys(root) | GCR3_VALID;
3441 }
3442
3443 root = iommu_phys_to_virt(*pte & PAGE_MASK);
3444
3445 level -= 1;
3446 }
3447
3448 return pte;
3449 }
3450
3451 static int __set_gcr3(struct protection_domain *domain, int pasid,
3452 unsigned long cr3)
3453 {
3454 u64 *pte;
3455
3456 if (domain->mode != PAGE_MODE_NONE)
3457 return -EINVAL;
3458
3459 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3460 if (pte == NULL)
3461 return -ENOMEM;
3462
3463 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3464
3465 return __amd_iommu_flush_tlb(domain, pasid);
3466 }
3467
3468 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3469 {
3470 u64 *pte;
3471
3472 if (domain->mode != PAGE_MODE_NONE)
3473 return -EINVAL;
3474
3475 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3476 if (pte == NULL)
3477 return 0;
3478
3479 *pte = 0;
3480
3481 return __amd_iommu_flush_tlb(domain, pasid);
3482 }
3483
3484 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3485 unsigned long cr3)
3486 {
3487 struct protection_domain *domain = to_pdomain(dom);
3488 unsigned long flags;
3489 int ret;
3490
3491 spin_lock_irqsave(&domain->lock, flags);
3492 ret = __set_gcr3(domain, pasid, cr3);
3493 spin_unlock_irqrestore(&domain->lock, flags);
3494
3495 return ret;
3496 }
3497 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3498
3499 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3500 {
3501 struct protection_domain *domain = to_pdomain(dom);
3502 unsigned long flags;
3503 int ret;
3504
3505 spin_lock_irqsave(&domain->lock, flags);
3506 ret = __clear_gcr3(domain, pasid);
3507 spin_unlock_irqrestore(&domain->lock, flags);
3508
3509 return ret;
3510 }
3511 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3512
3513 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3514 int status, int tag)
3515 {
3516 struct iommu_dev_data *dev_data;
3517 struct amd_iommu *iommu;
3518 struct iommu_cmd cmd;
3519
3520 dev_data = get_dev_data(&pdev->dev);
3521 iommu = amd_iommu_rlookup_table[dev_data->devid];
3522
3523 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3524 tag, dev_data->pri_tlp);
3525
3526 return iommu_queue_command(iommu, &cmd);
3527 }
3528 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3529
3530 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3531 {
3532 struct protection_domain *pdomain;
3533
3534 pdomain = get_domain(&pdev->dev);
3535 if (IS_ERR(pdomain))
3536 return NULL;
3537
3538 /* Only return IOMMUv2 domains */
3539 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3540 return NULL;
3541
3542 return &pdomain->domain;
3543 }
3544 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3545
3546 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3547 {
3548 struct iommu_dev_data *dev_data;
3549
3550 if (!amd_iommu_v2_supported())
3551 return;
3552
3553 dev_data = get_dev_data(&pdev->dev);
3554 dev_data->errata |= (1 << erratum);
3555 }
3556 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3557
3558 int amd_iommu_device_info(struct pci_dev *pdev,
3559 struct amd_iommu_device_info *info)
3560 {
3561 int max_pasids;
3562 int pos;
3563
3564 if (pdev == NULL || info == NULL)
3565 return -EINVAL;
3566
3567 if (!amd_iommu_v2_supported())
3568 return -EINVAL;
3569
3570 memset(info, 0, sizeof(*info));
3571
3572 if (!pci_ats_disabled()) {
3573 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3574 if (pos)
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3576 }
3577
3578 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3579 if (pos)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3581
3582 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3583 if (pos) {
3584 int features;
3585
3586 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3587 max_pasids = min(max_pasids, (1 << 20));
3588
3589 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3590 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3591
3592 features = pci_pasid_features(pdev);
3593 if (features & PCI_PASID_CAP_EXEC)
3594 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3595 if (features & PCI_PASID_CAP_PRIV)
3596 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3597 }
3598
3599 return 0;
3600 }
3601 EXPORT_SYMBOL(amd_iommu_device_info);
3602
3603 #ifdef CONFIG_IRQ_REMAP
3604
3605 /*****************************************************************************
3606 *
3607 * Interrupt Remapping Implementation
3608 *
3609 *****************************************************************************/
3610
3611 static struct irq_chip amd_ir_chip;
3612 static DEFINE_SPINLOCK(iommu_table_lock);
3613
3614 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3615 {
3616 u64 dte;
3617
3618 dte = amd_iommu_dev_table[devid].data[2];
3619 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3620 dte |= iommu_virt_to_phys(table->table);
3621 dte |= DTE_IRQ_REMAP_INTCTL;
3622 dte |= DTE_IRQ_TABLE_LEN;
3623 dte |= DTE_IRQ_REMAP_ENABLE;
3624
3625 amd_iommu_dev_table[devid].data[2] = dte;
3626 }
3627
3628 static struct irq_remap_table *get_irq_table(u16 devid)
3629 {
3630 struct irq_remap_table *table;
3631
3632 if (WARN_ONCE(!amd_iommu_rlookup_table[devid],
3633 "%s: no iommu for devid %x\n", __func__, devid))
3634 return NULL;
3635
3636 table = irq_lookup_table[devid];
3637 if (WARN_ONCE(!table, "%s: no table for devid %x\n", __func__, devid))
3638 return NULL;
3639
3640 return table;
3641 }
3642
3643 static struct irq_remap_table *__alloc_irq_table(void)
3644 {
3645 struct irq_remap_table *table;
3646
3647 table = kzalloc(sizeof(*table), GFP_KERNEL);
3648 if (!table)
3649 return NULL;
3650
3651 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_KERNEL);
3652 if (!table->table) {
3653 kfree(table);
3654 return NULL;
3655 }
3656 raw_spin_lock_init(&table->lock);
3657
3658 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3659 memset(table->table, 0,
3660 MAX_IRQS_PER_TABLE * sizeof(u32));
3661 else
3662 memset(table->table, 0,
3663 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3664 return table;
3665 }
3666
3667 static void set_remap_table_entry(struct amd_iommu *iommu, u16 devid,
3668 struct irq_remap_table *table)
3669 {
3670 irq_lookup_table[devid] = table;
3671 set_dte_irq_entry(devid, table);
3672 iommu_flush_dte(iommu, devid);
3673 }
3674
3675 static struct irq_remap_table *alloc_irq_table(u16 devid)
3676 {
3677 struct irq_remap_table *table = NULL;
3678 struct irq_remap_table *new_table = NULL;
3679 struct amd_iommu *iommu;
3680 unsigned long flags;
3681 u16 alias;
3682
3683 spin_lock_irqsave(&iommu_table_lock, flags);
3684
3685 iommu = amd_iommu_rlookup_table[devid];
3686 if (!iommu)
3687 goto out_unlock;
3688
3689 table = irq_lookup_table[devid];
3690 if (table)
3691 goto out_unlock;
3692
3693 alias = amd_iommu_alias_table[devid];
3694 table = irq_lookup_table[alias];
3695 if (table) {
3696 set_remap_table_entry(iommu, devid, table);
3697 goto out_wait;
3698 }
3699 spin_unlock_irqrestore(&iommu_table_lock, flags);
3700
3701 /* Nothing there yet, allocate new irq remapping table */
3702 new_table = __alloc_irq_table();
3703 if (!new_table)
3704 return NULL;
3705
3706 spin_lock_irqsave(&iommu_table_lock, flags);
3707
3708 table = irq_lookup_table[devid];
3709 if (table)
3710 goto out_unlock;
3711
3712 table = irq_lookup_table[alias];
3713 if (table) {
3714 set_remap_table_entry(iommu, devid, table);
3715 goto out_wait;
3716 }
3717
3718 table = new_table;
3719 new_table = NULL;
3720
3721 set_remap_table_entry(iommu, devid, table);
3722 if (devid != alias)
3723 set_remap_table_entry(iommu, alias, table);
3724
3725 out_wait:
3726 iommu_completion_wait(iommu);
3727
3728 out_unlock:
3729 spin_unlock_irqrestore(&iommu_table_lock, flags);
3730
3731 if (new_table) {
3732 kmem_cache_free(amd_iommu_irq_cache, new_table->table);
3733 kfree(new_table);
3734 }
3735 return table;
3736 }
3737
3738 static int alloc_irq_index(u16 devid, int count, bool align)
3739 {
3740 struct irq_remap_table *table;
3741 int index, c, alignment = 1;
3742 unsigned long flags;
3743 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3744
3745 if (!iommu)
3746 return -ENODEV;
3747
3748 table = alloc_irq_table(devid);
3749 if (!table)
3750 return -ENODEV;
3751
3752 if (align)
3753 alignment = roundup_pow_of_two(count);
3754
3755 raw_spin_lock_irqsave(&table->lock, flags);
3756
3757 /* Scan table for free entries */
3758 for (index = ALIGN(table->min_index, alignment), c = 0;
3759 index < MAX_IRQS_PER_TABLE;) {
3760 if (!iommu->irte_ops->is_allocated(table, index)) {
3761 c += 1;
3762 } else {
3763 c = 0;
3764 index = ALIGN(index + 1, alignment);
3765 continue;
3766 }
3767
3768 if (c == count) {
3769 for (; c != 0; --c)
3770 iommu->irte_ops->set_allocated(table, index - c + 1);
3771
3772 index -= count - 1;
3773 goto out;
3774 }
3775
3776 index++;
3777 }
3778
3779 index = -ENOSPC;
3780
3781 out:
3782 raw_spin_unlock_irqrestore(&table->lock, flags);
3783
3784 return index;
3785 }
3786
3787 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3788 struct amd_ir_data *data)
3789 {
3790 struct irq_remap_table *table;
3791 struct amd_iommu *iommu;
3792 unsigned long flags;
3793 struct irte_ga *entry;
3794
3795 iommu = amd_iommu_rlookup_table[devid];
3796 if (iommu == NULL)
3797 return -EINVAL;
3798
3799 table = get_irq_table(devid);
3800 if (!table)
3801 return -ENOMEM;
3802
3803 raw_spin_lock_irqsave(&table->lock, flags);
3804
3805 entry = (struct irte_ga *)table->table;
3806 entry = &entry[index];
3807 entry->lo.fields_remap.valid = 0;
3808 entry->hi.val = irte->hi.val;
3809 entry->lo.val = irte->lo.val;
3810 entry->lo.fields_remap.valid = 1;
3811 if (data)
3812 data->ref = entry;
3813
3814 raw_spin_unlock_irqrestore(&table->lock, flags);
3815
3816 iommu_flush_irt(iommu, devid);
3817 iommu_completion_wait(iommu);
3818
3819 return 0;
3820 }
3821
3822 static int modify_irte(u16 devid, int index, union irte *irte)
3823 {
3824 struct irq_remap_table *table;
3825 struct amd_iommu *iommu;
3826 unsigned long flags;
3827
3828 iommu = amd_iommu_rlookup_table[devid];
3829 if (iommu == NULL)
3830 return -EINVAL;
3831
3832 table = get_irq_table(devid);
3833 if (!table)
3834 return -ENOMEM;
3835
3836 raw_spin_lock_irqsave(&table->lock, flags);
3837 table->table[index] = irte->val;
3838 raw_spin_unlock_irqrestore(&table->lock, flags);
3839
3840 iommu_flush_irt(iommu, devid);
3841 iommu_completion_wait(iommu);
3842
3843 return 0;
3844 }
3845
3846 static void free_irte(u16 devid, int index)
3847 {
3848 struct irq_remap_table *table;
3849 struct amd_iommu *iommu;
3850 unsigned long flags;
3851
3852 iommu = amd_iommu_rlookup_table[devid];
3853 if (iommu == NULL)
3854 return;
3855
3856 table = get_irq_table(devid);
3857 if (!table)
3858 return;
3859
3860 raw_spin_lock_irqsave(&table->lock, flags);
3861 iommu->irte_ops->clear_allocated(table, index);
3862 raw_spin_unlock_irqrestore(&table->lock, flags);
3863
3864 iommu_flush_irt(iommu, devid);
3865 iommu_completion_wait(iommu);
3866 }
3867
3868 static void irte_prepare(void *entry,
3869 u32 delivery_mode, u32 dest_mode,
3870 u8 vector, u32 dest_apicid, int devid)
3871 {
3872 union irte *irte = (union irte *) entry;
3873
3874 irte->val = 0;
3875 irte->fields.vector = vector;
3876 irte->fields.int_type = delivery_mode;
3877 irte->fields.destination = dest_apicid;
3878 irte->fields.dm = dest_mode;
3879 irte->fields.valid = 1;
3880 }
3881
3882 static void irte_ga_prepare(void *entry,
3883 u32 delivery_mode, u32 dest_mode,
3884 u8 vector, u32 dest_apicid, int devid)
3885 {
3886 struct irte_ga *irte = (struct irte_ga *) entry;
3887
3888 irte->lo.val = 0;
3889 irte->hi.val = 0;
3890 irte->lo.fields_remap.int_type = delivery_mode;
3891 irte->lo.fields_remap.dm = dest_mode;
3892 irte->hi.fields.vector = vector;
3893 irte->lo.fields_remap.destination = APICID_TO_IRTE_DEST_LO(dest_apicid);
3894 irte->hi.fields.destination = APICID_TO_IRTE_DEST_HI(dest_apicid);
3895 irte->lo.fields_remap.valid = 1;
3896 }
3897
3898 static void irte_activate(void *entry, u16 devid, u16 index)
3899 {
3900 union irte *irte = (union irte *) entry;
3901
3902 irte->fields.valid = 1;
3903 modify_irte(devid, index, irte);
3904 }
3905
3906 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3907 {
3908 struct irte_ga *irte = (struct irte_ga *) entry;
3909
3910 irte->lo.fields_remap.valid = 1;
3911 modify_irte_ga(devid, index, irte, NULL);
3912 }
3913
3914 static void irte_deactivate(void *entry, u16 devid, u16 index)
3915 {
3916 union irte *irte = (union irte *) entry;
3917
3918 irte->fields.valid = 0;
3919 modify_irte(devid, index, irte);
3920 }
3921
3922 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3923 {
3924 struct irte_ga *irte = (struct irte_ga *) entry;
3925
3926 irte->lo.fields_remap.valid = 0;
3927 modify_irte_ga(devid, index, irte, NULL);
3928 }
3929
3930 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3931 u8 vector, u32 dest_apicid)
3932 {
3933 union irte *irte = (union irte *) entry;
3934
3935 irte->fields.vector = vector;
3936 irte->fields.destination = dest_apicid;
3937 modify_irte(devid, index, irte);
3938 }
3939
3940 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3941 u8 vector, u32 dest_apicid)
3942 {
3943 struct irte_ga *irte = (struct irte_ga *) entry;
3944
3945 if (!irte->lo.fields_remap.guest_mode) {
3946 irte->hi.fields.vector = vector;
3947 irte->lo.fields_remap.destination =
3948 APICID_TO_IRTE_DEST_LO(dest_apicid);
3949 irte->hi.fields.destination =
3950 APICID_TO_IRTE_DEST_HI(dest_apicid);
3951 modify_irte_ga(devid, index, irte, NULL);
3952 }
3953 }
3954
3955 #define IRTE_ALLOCATED (~1U)
3956 static void irte_set_allocated(struct irq_remap_table *table, int index)
3957 {
3958 table->table[index] = IRTE_ALLOCATED;
3959 }
3960
3961 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3962 {
3963 struct irte_ga *ptr = (struct irte_ga *)table->table;
3964 struct irte_ga *irte = &ptr[index];
3965
3966 memset(&irte->lo.val, 0, sizeof(u64));
3967 memset(&irte->hi.val, 0, sizeof(u64));
3968 irte->hi.fields.vector = 0xff;
3969 }
3970
3971 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3972 {
3973 union irte *ptr = (union irte *)table->table;
3974 union irte *irte = &ptr[index];
3975
3976 return irte->val != 0;
3977 }
3978
3979 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3980 {
3981 struct irte_ga *ptr = (struct irte_ga *)table->table;
3982 struct irte_ga *irte = &ptr[index];
3983
3984 return irte->hi.fields.vector != 0;
3985 }
3986
3987 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3988 {
3989 table->table[index] = 0;
3990 }
3991
3992 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3993 {
3994 struct irte_ga *ptr = (struct irte_ga *)table->table;
3995 struct irte_ga *irte = &ptr[index];
3996
3997 memset(&irte->lo.val, 0, sizeof(u64));
3998 memset(&irte->hi.val, 0, sizeof(u64));
3999 }
4000
4001 static int get_devid(struct irq_alloc_info *info)
4002 {
4003 int devid = -1;
4004
4005 switch (info->type) {
4006 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4007 devid = get_ioapic_devid(info->ioapic_id);
4008 break;
4009 case X86_IRQ_ALLOC_TYPE_HPET:
4010 devid = get_hpet_devid(info->hpet_id);
4011 break;
4012 case X86_IRQ_ALLOC_TYPE_MSI:
4013 case X86_IRQ_ALLOC_TYPE_MSIX:
4014 devid = get_device_id(&info->msi_dev->dev);
4015 break;
4016 default:
4017 BUG_ON(1);
4018 break;
4019 }
4020
4021 return devid;
4022 }
4023
4024 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
4025 {
4026 struct amd_iommu *iommu;
4027 int devid;
4028
4029 if (!info)
4030 return NULL;
4031
4032 devid = get_devid(info);
4033 if (devid >= 0) {
4034 iommu = amd_iommu_rlookup_table[devid];
4035 if (iommu)
4036 return iommu->ir_domain;
4037 }
4038
4039 return NULL;
4040 }
4041
4042 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
4043 {
4044 struct amd_iommu *iommu;
4045 int devid;
4046
4047 if (!info)
4048 return NULL;
4049
4050 switch (info->type) {
4051 case X86_IRQ_ALLOC_TYPE_MSI:
4052 case X86_IRQ_ALLOC_TYPE_MSIX:
4053 devid = get_device_id(&info->msi_dev->dev);
4054 if (devid < 0)
4055 return NULL;
4056
4057 iommu = amd_iommu_rlookup_table[devid];
4058 if (iommu)
4059 return iommu->msi_domain;
4060 break;
4061 default:
4062 break;
4063 }
4064
4065 return NULL;
4066 }
4067
4068 struct irq_remap_ops amd_iommu_irq_ops = {
4069 .prepare = amd_iommu_prepare,
4070 .enable = amd_iommu_enable,
4071 .disable = amd_iommu_disable,
4072 .reenable = amd_iommu_reenable,
4073 .enable_faulting = amd_iommu_enable_faulting,
4074 .get_ir_irq_domain = get_ir_irq_domain,
4075 .get_irq_domain = get_irq_domain,
4076 };
4077
4078 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4079 struct irq_cfg *irq_cfg,
4080 struct irq_alloc_info *info,
4081 int devid, int index, int sub_handle)
4082 {
4083 struct irq_2_irte *irte_info = &data->irq_2_irte;
4084 struct msi_msg *msg = &data->msi_entry;
4085 struct IO_APIC_route_entry *entry;
4086 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4087
4088 if (!iommu)
4089 return;
4090
4091 data->irq_2_irte.devid = devid;
4092 data->irq_2_irte.index = index + sub_handle;
4093 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4094 apic->irq_dest_mode, irq_cfg->vector,
4095 irq_cfg->dest_apicid, devid);
4096
4097 switch (info->type) {
4098 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4099 /* Setup IOAPIC entry */
4100 entry = info->ioapic_entry;
4101 info->ioapic_entry = NULL;
4102 memset(entry, 0, sizeof(*entry));
4103 entry->vector = index;
4104 entry->mask = 0;
4105 entry->trigger = info->ioapic_trigger;
4106 entry->polarity = info->ioapic_polarity;
4107 /* Mask level triggered irqs. */
4108 if (info->ioapic_trigger)
4109 entry->mask = 1;
4110 break;
4111
4112 case X86_IRQ_ALLOC_TYPE_HPET:
4113 case X86_IRQ_ALLOC_TYPE_MSI:
4114 case X86_IRQ_ALLOC_TYPE_MSIX:
4115 msg->address_hi = MSI_ADDR_BASE_HI;
4116 msg->address_lo = MSI_ADDR_BASE_LO;
4117 msg->data = irte_info->index;
4118 break;
4119
4120 default:
4121 BUG_ON(1);
4122 break;
4123 }
4124 }
4125
4126 struct amd_irte_ops irte_32_ops = {
4127 .prepare = irte_prepare,
4128 .activate = irte_activate,
4129 .deactivate = irte_deactivate,
4130 .set_affinity = irte_set_affinity,
4131 .set_allocated = irte_set_allocated,
4132 .is_allocated = irte_is_allocated,
4133 .clear_allocated = irte_clear_allocated,
4134 };
4135
4136 struct amd_irte_ops irte_128_ops = {
4137 .prepare = irte_ga_prepare,
4138 .activate = irte_ga_activate,
4139 .deactivate = irte_ga_deactivate,
4140 .set_affinity = irte_ga_set_affinity,
4141 .set_allocated = irte_ga_set_allocated,
4142 .is_allocated = irte_ga_is_allocated,
4143 .clear_allocated = irte_ga_clear_allocated,
4144 };
4145
4146 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4147 unsigned int nr_irqs, void *arg)
4148 {
4149 struct irq_alloc_info *info = arg;
4150 struct irq_data *irq_data;
4151 struct amd_ir_data *data = NULL;
4152 struct irq_cfg *cfg;
4153 int i, ret, devid;
4154 int index;
4155
4156 if (!info)
4157 return -EINVAL;
4158 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4159 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4160 return -EINVAL;
4161
4162 /*
4163 * With IRQ remapping enabled, don't need contiguous CPU vectors
4164 * to support multiple MSI interrupts.
4165 */
4166 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4167 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4168
4169 devid = get_devid(info);
4170 if (devid < 0)
4171 return -EINVAL;
4172
4173 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4174 if (ret < 0)
4175 return ret;
4176
4177 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4178 struct irq_remap_table *table;
4179 struct amd_iommu *iommu;
4180
4181 table = alloc_irq_table(devid);
4182 if (table) {
4183 if (!table->min_index) {
4184 /*
4185 * Keep the first 32 indexes free for IOAPIC
4186 * interrupts.
4187 */
4188 table->min_index = 32;
4189 iommu = amd_iommu_rlookup_table[devid];
4190 for (i = 0; i < 32; ++i)
4191 iommu->irte_ops->set_allocated(table, i);
4192 }
4193 WARN_ON(table->min_index != 32);
4194 index = info->ioapic_pin;
4195 } else {
4196 index = -ENOMEM;
4197 }
4198 } else {
4199 bool align = (info->type == X86_IRQ_ALLOC_TYPE_MSI);
4200
4201 index = alloc_irq_index(devid, nr_irqs, align);
4202 }
4203 if (index < 0) {
4204 pr_warn("Failed to allocate IRTE\n");
4205 ret = index;
4206 goto out_free_parent;
4207 }
4208
4209 for (i = 0; i < nr_irqs; i++) {
4210 irq_data = irq_domain_get_irq_data(domain, virq + i);
4211 cfg = irqd_cfg(irq_data);
4212 if (!irq_data || !cfg) {
4213 ret = -EINVAL;
4214 goto out_free_data;
4215 }
4216
4217 ret = -ENOMEM;
4218 data = kzalloc(sizeof(*data), GFP_KERNEL);
4219 if (!data)
4220 goto out_free_data;
4221
4222 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4223 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4224 else
4225 data->entry = kzalloc(sizeof(struct irte_ga),
4226 GFP_KERNEL);
4227 if (!data->entry) {
4228 kfree(data);
4229 goto out_free_data;
4230 }
4231
4232 irq_data->hwirq = (devid << 16) + i;
4233 irq_data->chip_data = data;
4234 irq_data->chip = &amd_ir_chip;
4235 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4236 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4237 }
4238
4239 return 0;
4240
4241 out_free_data:
4242 for (i--; i >= 0; i--) {
4243 irq_data = irq_domain_get_irq_data(domain, virq + i);
4244 if (irq_data)
4245 kfree(irq_data->chip_data);
4246 }
4247 for (i = 0; i < nr_irqs; i++)
4248 free_irte(devid, index + i);
4249 out_free_parent:
4250 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4251 return ret;
4252 }
4253
4254 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4255 unsigned int nr_irqs)
4256 {
4257 struct irq_2_irte *irte_info;
4258 struct irq_data *irq_data;
4259 struct amd_ir_data *data;
4260 int i;
4261
4262 for (i = 0; i < nr_irqs; i++) {
4263 irq_data = irq_domain_get_irq_data(domain, virq + i);
4264 if (irq_data && irq_data->chip_data) {
4265 data = irq_data->chip_data;
4266 irte_info = &data->irq_2_irte;
4267 free_irte(irte_info->devid, irte_info->index);
4268 kfree(data->entry);
4269 kfree(data);
4270 }
4271 }
4272 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4273 }
4274
4275 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4276 struct amd_ir_data *ir_data,
4277 struct irq_2_irte *irte_info,
4278 struct irq_cfg *cfg);
4279
4280 static int irq_remapping_activate(struct irq_domain *domain,
4281 struct irq_data *irq_data, bool reserve)
4282 {
4283 struct amd_ir_data *data = irq_data->chip_data;
4284 struct irq_2_irte *irte_info = &data->irq_2_irte;
4285 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4286 struct irq_cfg *cfg = irqd_cfg(irq_data);
4287
4288 if (!iommu)
4289 return 0;
4290
4291 iommu->irte_ops->activate(data->entry, irte_info->devid,
4292 irte_info->index);
4293 amd_ir_update_irte(irq_data, iommu, data, irte_info, cfg);
4294 return 0;
4295 }
4296
4297 static void irq_remapping_deactivate(struct irq_domain *domain,
4298 struct irq_data *irq_data)
4299 {
4300 struct amd_ir_data *data = irq_data->chip_data;
4301 struct irq_2_irte *irte_info = &data->irq_2_irte;
4302 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4303
4304 if (iommu)
4305 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4306 irte_info->index);
4307 }
4308
4309 static const struct irq_domain_ops amd_ir_domain_ops = {
4310 .alloc = irq_remapping_alloc,
4311 .free = irq_remapping_free,
4312 .activate = irq_remapping_activate,
4313 .deactivate = irq_remapping_deactivate,
4314 };
4315
4316 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4317 {
4318 struct amd_iommu *iommu;
4319 struct amd_iommu_pi_data *pi_data = vcpu_info;
4320 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4321 struct amd_ir_data *ir_data = data->chip_data;
4322 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4323 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4324 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4325
4326 /* Note:
4327 * This device has never been set up for guest mode.
4328 * we should not modify the IRTE
4329 */
4330 if (!dev_data || !dev_data->use_vapic)
4331 return 0;
4332
4333 pi_data->ir_data = ir_data;
4334
4335 /* Note:
4336 * SVM tries to set up for VAPIC mode, but we are in
4337 * legacy mode. So, we force legacy mode instead.
4338 */
4339 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4340 pr_debug("%s: Fall back to using intr legacy remap\n",
4341 __func__);
4342 pi_data->is_guest_mode = false;
4343 }
4344
4345 iommu = amd_iommu_rlookup_table[irte_info->devid];
4346 if (iommu == NULL)
4347 return -EINVAL;
4348
4349 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4350 if (pi_data->is_guest_mode) {
4351 /* Setting */
4352 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4353 irte->hi.fields.vector = vcpu_pi_info->vector;
4354 irte->lo.fields_vapic.ga_log_intr = 1;
4355 irte->lo.fields_vapic.guest_mode = 1;
4356 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4357
4358 ir_data->cached_ga_tag = pi_data->ga_tag;
4359 } else {
4360 /* Un-Setting */
4361 struct irq_cfg *cfg = irqd_cfg(data);
4362
4363 irte->hi.val = 0;
4364 irte->lo.val = 0;
4365 irte->hi.fields.vector = cfg->vector;
4366 irte->lo.fields_remap.guest_mode = 0;
4367 irte->lo.fields_remap.destination =
4368 APICID_TO_IRTE_DEST_LO(cfg->dest_apicid);
4369 irte->hi.fields.destination =
4370 APICID_TO_IRTE_DEST_HI(cfg->dest_apicid);
4371 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4372 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4373
4374 /*
4375 * This communicates the ga_tag back to the caller
4376 * so that it can do all the necessary clean up.
4377 */
4378 ir_data->cached_ga_tag = 0;
4379 }
4380
4381 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4382 }
4383
4384
4385 static void amd_ir_update_irte(struct irq_data *irqd, struct amd_iommu *iommu,
4386 struct amd_ir_data *ir_data,
4387 struct irq_2_irte *irte_info,
4388 struct irq_cfg *cfg)
4389 {
4390
4391 /*
4392 * Atomically updates the IRTE with the new destination, vector
4393 * and flushes the interrupt entry cache.
4394 */
4395 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4396 irte_info->index, cfg->vector,
4397 cfg->dest_apicid);
4398 }
4399
4400 static int amd_ir_set_affinity(struct irq_data *data,
4401 const struct cpumask *mask, bool force)
4402 {
4403 struct amd_ir_data *ir_data = data->chip_data;
4404 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4405 struct irq_cfg *cfg = irqd_cfg(data);
4406 struct irq_data *parent = data->parent_data;
4407 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4408 int ret;
4409
4410 if (!iommu)
4411 return -ENODEV;
4412
4413 ret = parent->chip->irq_set_affinity(parent, mask, force);
4414 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4415 return ret;
4416
4417 amd_ir_update_irte(data, iommu, ir_data, irte_info, cfg);
4418 /*
4419 * After this point, all the interrupts will start arriving
4420 * at the new destination. So, time to cleanup the previous
4421 * vector allocation.
4422 */
4423 send_cleanup_vector(cfg);
4424
4425 return IRQ_SET_MASK_OK_DONE;
4426 }
4427
4428 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4429 {
4430 struct amd_ir_data *ir_data = irq_data->chip_data;
4431
4432 *msg = ir_data->msi_entry;
4433 }
4434
4435 static struct irq_chip amd_ir_chip = {
4436 .name = "AMD-IR",
4437 .irq_ack = apic_ack_irq,
4438 .irq_set_affinity = amd_ir_set_affinity,
4439 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4440 .irq_compose_msi_msg = ir_compose_msi_msg,
4441 };
4442
4443 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4444 {
4445 struct fwnode_handle *fn;
4446
4447 fn = irq_domain_alloc_named_id_fwnode("AMD-IR", iommu->index);
4448 if (!fn)
4449 return -ENOMEM;
4450 iommu->ir_domain = irq_domain_create_tree(fn, &amd_ir_domain_ops, iommu);
4451 irq_domain_free_fwnode(fn);
4452 if (!iommu->ir_domain)
4453 return -ENOMEM;
4454
4455 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4456 iommu->msi_domain = arch_create_remap_msi_irq_domain(iommu->ir_domain,
4457 "AMD-IR-MSI",
4458 iommu->index);
4459 return 0;
4460 }
4461
4462 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4463 {
4464 unsigned long flags;
4465 struct amd_iommu *iommu;
4466 struct irq_remap_table *table;
4467 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4468 int devid = ir_data->irq_2_irte.devid;
4469 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4470 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4471
4472 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4473 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4474 return 0;
4475
4476 iommu = amd_iommu_rlookup_table[devid];
4477 if (!iommu)
4478 return -ENODEV;
4479
4480 table = get_irq_table(devid);
4481 if (!table)
4482 return -ENODEV;
4483
4484 raw_spin_lock_irqsave(&table->lock, flags);
4485
4486 if (ref->lo.fields_vapic.guest_mode) {
4487 if (cpu >= 0) {
4488 ref->lo.fields_vapic.destination =
4489 APICID_TO_IRTE_DEST_LO(cpu);
4490 ref->hi.fields.destination =
4491 APICID_TO_IRTE_DEST_HI(cpu);
4492 }
4493 ref->lo.fields_vapic.is_run = is_run;
4494 barrier();
4495 }
4496
4497 raw_spin_unlock_irqrestore(&table->lock, flags);
4498
4499 iommu_flush_irt(iommu, devid);
4500 iommu_completion_wait(iommu);
4501 return 0;
4502 }
4503 EXPORT_SYMBOL(amd_iommu_update_ga);
4504 #endif
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