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iommu/amd: Enable vAPIC interrupt remapping mode by default
[mirror_ubuntu-artful-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/acpi.h>
23 #include <linux/amba/bus.h>
24 #include <linux/platform_device.h>
25 #include <linux/pci-ats.h>
26 #include <linux/bitmap.h>
27 #include <linux/slab.h>
28 #include <linux/debugfs.h>
29 #include <linux/scatterlist.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/iommu-helper.h>
32 #include <linux/iommu.h>
33 #include <linux/delay.h>
34 #include <linux/amd-iommu.h>
35 #include <linux/notifier.h>
36 #include <linux/export.h>
37 #include <linux/irq.h>
38 #include <linux/msi.h>
39 #include <linux/dma-contiguous.h>
40 #include <linux/irqdomain.h>
41 #include <linux/percpu.h>
42 #include <linux/iova.h>
43 #include <asm/irq_remapping.h>
44 #include <asm/io_apic.h>
45 #include <asm/apic.h>
46 #include <asm/hw_irq.h>
47 #include <asm/msidef.h>
48 #include <asm/proto.h>
49 #include <asm/iommu.h>
50 #include <asm/gart.h>
51 #include <asm/dma.h>
52
53 #include "amd_iommu_proto.h"
54 #include "amd_iommu_types.h"
55 #include "irq_remapping.h"
56
57 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
58
59 #define LOOP_TIMEOUT 100000
60
61 /* IO virtual address start page frame number */
62 #define IOVA_START_PFN (1)
63 #define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
64 #define DMA_32BIT_PFN IOVA_PFN(DMA_BIT_MASK(32))
65
66 /* Reserved IOVA ranges */
67 #define MSI_RANGE_START (0xfee00000)
68 #define MSI_RANGE_END (0xfeefffff)
69 #define HT_RANGE_START (0xfd00000000ULL)
70 #define HT_RANGE_END (0xffffffffffULL)
71
72 /*
73 * This bitmap is used to advertise the page sizes our hardware support
74 * to the IOMMU core, which will then use this information to split
75 * physically contiguous memory regions it is mapping into page sizes
76 * that we support.
77 *
78 * 512GB Pages are not supported due to a hardware bug
79 */
80 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
81
82 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
83
84 /* List of all available dev_data structures */
85 static LIST_HEAD(dev_data_list);
86 static DEFINE_SPINLOCK(dev_data_list_lock);
87
88 LIST_HEAD(ioapic_map);
89 LIST_HEAD(hpet_map);
90 LIST_HEAD(acpihid_map);
91
92 #define FLUSH_QUEUE_SIZE 256
93
94 struct flush_queue_entry {
95 unsigned long iova_pfn;
96 unsigned long pages;
97 struct dma_ops_domain *dma_dom;
98 };
99
100 struct flush_queue {
101 spinlock_t lock;
102 unsigned next;
103 struct flush_queue_entry *entries;
104 };
105
106 DEFINE_PER_CPU(struct flush_queue, flush_queue);
107
108 static atomic_t queue_timer_on;
109 static struct timer_list queue_timer;
110
111 /*
112 * Domain for untranslated devices - only allocated
113 * if iommu=pt passed on kernel cmd line.
114 */
115 static const struct iommu_ops amd_iommu_ops;
116
117 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
118 int amd_iommu_max_glx_val = -1;
119
120 static struct dma_map_ops amd_iommu_dma_ops;
121
122 /*
123 * This struct contains device specific data for the IOMMU
124 */
125 struct iommu_dev_data {
126 struct list_head list; /* For domain->dev_list */
127 struct list_head dev_data_list; /* For global dev_data_list */
128 struct protection_domain *domain; /* Domain the device is bound to */
129 u16 devid; /* PCI Device ID */
130 u16 alias; /* Alias Device ID */
131 bool iommu_v2; /* Device can make use of IOMMUv2 */
132 bool passthrough; /* Device is identity mapped */
133 struct {
134 bool enabled;
135 int qdep;
136 } ats; /* ATS state */
137 bool pri_tlp; /* PASID TLB required for
138 PPR completions */
139 u32 errata; /* Bitmap for errata to apply */
140 bool use_vapic; /* Enable device to use vapic mode */
141 };
142
143 /*
144 * general struct to manage commands send to an IOMMU
145 */
146 struct iommu_cmd {
147 u32 data[4];
148 };
149
150 struct kmem_cache *amd_iommu_irq_cache;
151
152 static void update_domain(struct protection_domain *domain);
153 static int protection_domain_init(struct protection_domain *domain);
154 static void detach_device(struct device *dev);
155
156 /*
157 * Data container for a dma_ops specific protection domain
158 */
159 struct dma_ops_domain {
160 /* generic protection domain information */
161 struct protection_domain domain;
162
163 /* IOVA RB-Tree */
164 struct iova_domain iovad;
165 };
166
167 static struct iova_domain reserved_iova_ranges;
168 static struct lock_class_key reserved_rbtree_key;
169
170 /****************************************************************************
171 *
172 * Helper functions
173 *
174 ****************************************************************************/
175
176 static inline int match_hid_uid(struct device *dev,
177 struct acpihid_map_entry *entry)
178 {
179 const char *hid, *uid;
180
181 hid = acpi_device_hid(ACPI_COMPANION(dev));
182 uid = acpi_device_uid(ACPI_COMPANION(dev));
183
184 if (!hid || !(*hid))
185 return -ENODEV;
186
187 if (!uid || !(*uid))
188 return strcmp(hid, entry->hid);
189
190 if (!(*entry->uid))
191 return strcmp(hid, entry->hid);
192
193 return (strcmp(hid, entry->hid) || strcmp(uid, entry->uid));
194 }
195
196 static inline u16 get_pci_device_id(struct device *dev)
197 {
198 struct pci_dev *pdev = to_pci_dev(dev);
199
200 return PCI_DEVID(pdev->bus->number, pdev->devfn);
201 }
202
203 static inline int get_acpihid_device_id(struct device *dev,
204 struct acpihid_map_entry **entry)
205 {
206 struct acpihid_map_entry *p;
207
208 list_for_each_entry(p, &acpihid_map, list) {
209 if (!match_hid_uid(dev, p)) {
210 if (entry)
211 *entry = p;
212 return p->devid;
213 }
214 }
215 return -EINVAL;
216 }
217
218 static inline int get_device_id(struct device *dev)
219 {
220 int devid;
221
222 if (dev_is_pci(dev))
223 devid = get_pci_device_id(dev);
224 else
225 devid = get_acpihid_device_id(dev, NULL);
226
227 return devid;
228 }
229
230 static struct protection_domain *to_pdomain(struct iommu_domain *dom)
231 {
232 return container_of(dom, struct protection_domain, domain);
233 }
234
235 static struct dma_ops_domain* to_dma_ops_domain(struct protection_domain *domain)
236 {
237 BUG_ON(domain->flags != PD_DMA_OPS_MASK);
238 return container_of(domain, struct dma_ops_domain, domain);
239 }
240
241 static struct iommu_dev_data *alloc_dev_data(u16 devid)
242 {
243 struct iommu_dev_data *dev_data;
244 unsigned long flags;
245
246 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
247 if (!dev_data)
248 return NULL;
249
250 dev_data->devid = devid;
251
252 spin_lock_irqsave(&dev_data_list_lock, flags);
253 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
254 spin_unlock_irqrestore(&dev_data_list_lock, flags);
255
256 return dev_data;
257 }
258
259 static struct iommu_dev_data *search_dev_data(u16 devid)
260 {
261 struct iommu_dev_data *dev_data;
262 unsigned long flags;
263
264 spin_lock_irqsave(&dev_data_list_lock, flags);
265 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
266 if (dev_data->devid == devid)
267 goto out_unlock;
268 }
269
270 dev_data = NULL;
271
272 out_unlock:
273 spin_unlock_irqrestore(&dev_data_list_lock, flags);
274
275 return dev_data;
276 }
277
278 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
279 {
280 *(u16 *)data = alias;
281 return 0;
282 }
283
284 static u16 get_alias(struct device *dev)
285 {
286 struct pci_dev *pdev = to_pci_dev(dev);
287 u16 devid, ivrs_alias, pci_alias;
288
289 /* The callers make sure that get_device_id() does not fail here */
290 devid = get_device_id(dev);
291 ivrs_alias = amd_iommu_alias_table[devid];
292 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
293
294 if (ivrs_alias == pci_alias)
295 return ivrs_alias;
296
297 /*
298 * DMA alias showdown
299 *
300 * The IVRS is fairly reliable in telling us about aliases, but it
301 * can't know about every screwy device. If we don't have an IVRS
302 * reported alias, use the PCI reported alias. In that case we may
303 * still need to initialize the rlookup and dev_table entries if the
304 * alias is to a non-existent device.
305 */
306 if (ivrs_alias == devid) {
307 if (!amd_iommu_rlookup_table[pci_alias]) {
308 amd_iommu_rlookup_table[pci_alias] =
309 amd_iommu_rlookup_table[devid];
310 memcpy(amd_iommu_dev_table[pci_alias].data,
311 amd_iommu_dev_table[devid].data,
312 sizeof(amd_iommu_dev_table[pci_alias].data));
313 }
314
315 return pci_alias;
316 }
317
318 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
319 "for device %s[%04x:%04x], kernel reported alias "
320 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
321 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
322 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
323 PCI_FUNC(pci_alias));
324
325 /*
326 * If we don't have a PCI DMA alias and the IVRS alias is on the same
327 * bus, then the IVRS table may know about a quirk that we don't.
328 */
329 if (pci_alias == devid &&
330 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
331 pci_add_dma_alias(pdev, ivrs_alias & 0xff);
332 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
333 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
334 dev_name(dev));
335 }
336
337 return ivrs_alias;
338 }
339
340 static struct iommu_dev_data *find_dev_data(u16 devid)
341 {
342 struct iommu_dev_data *dev_data;
343
344 dev_data = search_dev_data(devid);
345
346 if (dev_data == NULL)
347 dev_data = alloc_dev_data(devid);
348
349 return dev_data;
350 }
351
352 static struct iommu_dev_data *get_dev_data(struct device *dev)
353 {
354 return dev->archdata.iommu;
355 }
356
357 /*
358 * Find or create an IOMMU group for a acpihid device.
359 */
360 static struct iommu_group *acpihid_device_group(struct device *dev)
361 {
362 struct acpihid_map_entry *p, *entry = NULL;
363 int devid;
364
365 devid = get_acpihid_device_id(dev, &entry);
366 if (devid < 0)
367 return ERR_PTR(devid);
368
369 list_for_each_entry(p, &acpihid_map, list) {
370 if ((devid == p->devid) && p->group)
371 entry->group = p->group;
372 }
373
374 if (!entry->group)
375 entry->group = generic_device_group(dev);
376
377 return entry->group;
378 }
379
380 static bool pci_iommuv2_capable(struct pci_dev *pdev)
381 {
382 static const int caps[] = {
383 PCI_EXT_CAP_ID_ATS,
384 PCI_EXT_CAP_ID_PRI,
385 PCI_EXT_CAP_ID_PASID,
386 };
387 int i, pos;
388
389 for (i = 0; i < 3; ++i) {
390 pos = pci_find_ext_capability(pdev, caps[i]);
391 if (pos == 0)
392 return false;
393 }
394
395 return true;
396 }
397
398 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
399 {
400 struct iommu_dev_data *dev_data;
401
402 dev_data = get_dev_data(&pdev->dev);
403
404 return dev_data->errata & (1 << erratum) ? true : false;
405 }
406
407 /*
408 * This function checks if the driver got a valid device from the caller to
409 * avoid dereferencing invalid pointers.
410 */
411 static bool check_device(struct device *dev)
412 {
413 int devid;
414
415 if (!dev || !dev->dma_mask)
416 return false;
417
418 devid = get_device_id(dev);
419 if (devid < 0)
420 return false;
421
422 /* Out of our scope? */
423 if (devid > amd_iommu_last_bdf)
424 return false;
425
426 if (amd_iommu_rlookup_table[devid] == NULL)
427 return false;
428
429 return true;
430 }
431
432 static void init_iommu_group(struct device *dev)
433 {
434 struct iommu_group *group;
435
436 group = iommu_group_get_for_dev(dev);
437 if (IS_ERR(group))
438 return;
439
440 iommu_group_put(group);
441 }
442
443 static int iommu_init_device(struct device *dev)
444 {
445 struct iommu_dev_data *dev_data;
446 int devid;
447
448 if (dev->archdata.iommu)
449 return 0;
450
451 devid = get_device_id(dev);
452 if (devid < 0)
453 return devid;
454
455 dev_data = find_dev_data(devid);
456 if (!dev_data)
457 return -ENOMEM;
458
459 dev_data->alias = get_alias(dev);
460
461 if (dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
462 struct amd_iommu *iommu;
463
464 iommu = amd_iommu_rlookup_table[dev_data->devid];
465 dev_data->iommu_v2 = iommu->is_iommu_v2;
466 }
467
468 dev->archdata.iommu = dev_data;
469
470 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
471 dev);
472
473 return 0;
474 }
475
476 static void iommu_ignore_device(struct device *dev)
477 {
478 u16 alias;
479 int devid;
480
481 devid = get_device_id(dev);
482 if (devid < 0)
483 return;
484
485 alias = get_alias(dev);
486
487 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
488 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
489
490 amd_iommu_rlookup_table[devid] = NULL;
491 amd_iommu_rlookup_table[alias] = NULL;
492 }
493
494 static void iommu_uninit_device(struct device *dev)
495 {
496 int devid;
497 struct iommu_dev_data *dev_data;
498
499 devid = get_device_id(dev);
500 if (devid < 0)
501 return;
502
503 dev_data = search_dev_data(devid);
504 if (!dev_data)
505 return;
506
507 if (dev_data->domain)
508 detach_device(dev);
509
510 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
511 dev);
512
513 iommu_group_remove_device(dev);
514
515 /* Remove dma-ops */
516 dev->archdata.dma_ops = NULL;
517
518 /*
519 * We keep dev_data around for unplugged devices and reuse it when the
520 * device is re-plugged - not doing so would introduce a ton of races.
521 */
522 }
523
524 /****************************************************************************
525 *
526 * Interrupt handling functions
527 *
528 ****************************************************************************/
529
530 static void dump_dte_entry(u16 devid)
531 {
532 int i;
533
534 for (i = 0; i < 4; ++i)
535 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
536 amd_iommu_dev_table[devid].data[i]);
537 }
538
539 static void dump_command(unsigned long phys_addr)
540 {
541 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
542 int i;
543
544 for (i = 0; i < 4; ++i)
545 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
546 }
547
548 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
549 {
550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555 retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
571
572 printk(KERN_ERR "AMD-Vi: Event logged [");
573
574 switch (type) {
575 case EVENT_TYPE_ILL_DEV:
576 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
577 "address=0x%016llx flags=0x%04x]\n",
578 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
579 address, flags);
580 dump_dte_entry(devid);
581 break;
582 case EVENT_TYPE_IO_FAULT:
583 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
584 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
586 domid, address, flags);
587 break;
588 case EVENT_TYPE_DEV_TAB_ERR:
589 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
590 "address=0x%016llx flags=0x%04x]\n",
591 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
592 address, flags);
593 break;
594 case EVENT_TYPE_PAGE_TAB_ERR:
595 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
598 domid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
602 dump_command(address);
603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
606 "flags=0x%04x]\n", address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
610 "address=0x%016llx]\n",
611 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
612 address);
613 break;
614 case EVENT_TYPE_INV_DEV_REQ:
615 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
616 "address=0x%016llx flags=0x%04x]\n",
617 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
618 address, flags);
619 break;
620 default:
621 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
622 }
623
624 memset(__evt, 0, 4 * sizeof(u32));
625 }
626
627 static void iommu_poll_events(struct amd_iommu *iommu)
628 {
629 u32 head, tail;
630
631 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
633
634 while (head != tail) {
635 iommu_print_event(iommu, iommu->evt_buf + head);
636 head = (head + EVENT_ENTRY_SIZE) % EVT_BUFFER_SIZE;
637 }
638
639 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
640 }
641
642 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
643 {
644 struct amd_iommu_fault fault;
645
646 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
647 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
648 return;
649 }
650
651 fault.address = raw[1];
652 fault.pasid = PPR_PASID(raw[0]);
653 fault.device_id = PPR_DEVID(raw[0]);
654 fault.tag = PPR_TAG(raw[0]);
655 fault.flags = PPR_FLAGS(raw[0]);
656
657 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
658 }
659
660 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
661 {
662 u32 head, tail;
663
664 if (iommu->ppr_log == NULL)
665 return;
666
667 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
668 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669
670 while (head != tail) {
671 volatile u64 *raw;
672 u64 entry[2];
673 int i;
674
675 raw = (u64 *)(iommu->ppr_log + head);
676
677 /*
678 * Hardware bug: Interrupt may arrive before the entry is
679 * written to memory. If this happens we need to wait for the
680 * entry to arrive.
681 */
682 for (i = 0; i < LOOP_TIMEOUT; ++i) {
683 if (PPR_REQ_TYPE(raw[0]) != 0)
684 break;
685 udelay(1);
686 }
687
688 /* Avoid memcpy function-call overhead */
689 entry[0] = raw[0];
690 entry[1] = raw[1];
691
692 /*
693 * To detect the hardware bug we need to clear the entry
694 * back to zero.
695 */
696 raw[0] = raw[1] = 0UL;
697
698 /* Update head pointer of hardware ring-buffer */
699 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
700 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
701
702 /* Handle PPR entry */
703 iommu_handle_ppr_entry(iommu, entry);
704
705 /* Refresh ring-buffer information */
706 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
707 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
708 }
709 }
710
711 #ifdef CONFIG_IRQ_REMAP
712 static int (*iommu_ga_log_notifier)(u32);
713
714 int amd_iommu_register_ga_log_notifier(int (*notifier)(u32))
715 {
716 iommu_ga_log_notifier = notifier;
717
718 return 0;
719 }
720 EXPORT_SYMBOL(amd_iommu_register_ga_log_notifier);
721
722 static void iommu_poll_ga_log(struct amd_iommu *iommu)
723 {
724 u32 head, tail, cnt = 0;
725
726 if (iommu->ga_log == NULL)
727 return;
728
729 head = readl(iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
730 tail = readl(iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
731
732 while (head != tail) {
733 volatile u64 *raw;
734 u64 log_entry;
735
736 raw = (u64 *)(iommu->ga_log + head);
737 cnt++;
738
739 /* Avoid memcpy function-call overhead */
740 log_entry = *raw;
741
742 /* Update head pointer of hardware ring-buffer */
743 head = (head + GA_ENTRY_SIZE) % GA_LOG_SIZE;
744 writel(head, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
745
746 /* Handle GA entry */
747 switch (GA_REQ_TYPE(log_entry)) {
748 case GA_GUEST_NR:
749 if (!iommu_ga_log_notifier)
750 break;
751
752 pr_debug("AMD-Vi: %s: devid=%#x, ga_tag=%#x\n",
753 __func__, GA_DEVID(log_entry),
754 GA_TAG(log_entry));
755
756 if (iommu_ga_log_notifier(GA_TAG(log_entry)) != 0)
757 pr_err("AMD-Vi: GA log notifier failed.\n");
758 break;
759 default:
760 break;
761 }
762 }
763 }
764 #endif /* CONFIG_IRQ_REMAP */
765
766 #define AMD_IOMMU_INT_MASK \
767 (MMIO_STATUS_EVT_INT_MASK | \
768 MMIO_STATUS_PPR_INT_MASK | \
769 MMIO_STATUS_GALOG_INT_MASK)
770
771 irqreturn_t amd_iommu_int_thread(int irq, void *data)
772 {
773 struct amd_iommu *iommu = (struct amd_iommu *) data;
774 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
775
776 while (status & AMD_IOMMU_INT_MASK) {
777 /* Enable EVT and PPR and GA interrupts again */
778 writel(AMD_IOMMU_INT_MASK,
779 iommu->mmio_base + MMIO_STATUS_OFFSET);
780
781 if (status & MMIO_STATUS_EVT_INT_MASK) {
782 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
783 iommu_poll_events(iommu);
784 }
785
786 if (status & MMIO_STATUS_PPR_INT_MASK) {
787 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
788 iommu_poll_ppr_log(iommu);
789 }
790
791 #ifdef CONFIG_IRQ_REMAP
792 if (status & MMIO_STATUS_GALOG_INT_MASK) {
793 pr_devel("AMD-Vi: Processing IOMMU GA Log\n");
794 iommu_poll_ga_log(iommu);
795 }
796 #endif
797
798 /*
799 * Hardware bug: ERBT1312
800 * When re-enabling interrupt (by writing 1
801 * to clear the bit), the hardware might also try to set
802 * the interrupt bit in the event status register.
803 * In this scenario, the bit will be set, and disable
804 * subsequent interrupts.
805 *
806 * Workaround: The IOMMU driver should read back the
807 * status register and check if the interrupt bits are cleared.
808 * If not, driver will need to go through the interrupt handler
809 * again and re-clear the bits
810 */
811 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
812 }
813 return IRQ_HANDLED;
814 }
815
816 irqreturn_t amd_iommu_int_handler(int irq, void *data)
817 {
818 return IRQ_WAKE_THREAD;
819 }
820
821 /****************************************************************************
822 *
823 * IOMMU command queuing functions
824 *
825 ****************************************************************************/
826
827 static int wait_on_sem(volatile u64 *sem)
828 {
829 int i = 0;
830
831 while (*sem == 0 && i < LOOP_TIMEOUT) {
832 udelay(1);
833 i += 1;
834 }
835
836 if (i == LOOP_TIMEOUT) {
837 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
838 return -EIO;
839 }
840
841 return 0;
842 }
843
844 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
845 struct iommu_cmd *cmd,
846 u32 tail)
847 {
848 u8 *target;
849
850 target = iommu->cmd_buf + tail;
851 tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
852
853 /* Copy command to buffer */
854 memcpy(target, cmd, sizeof(*cmd));
855
856 /* Tell the IOMMU about it */
857 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
858 }
859
860 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
861 {
862 WARN_ON(address & 0x7ULL);
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
866 cmd->data[1] = upper_32_bits(__pa(address));
867 cmd->data[2] = 1;
868 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
869 }
870
871 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
872 {
873 memset(cmd, 0, sizeof(*cmd));
874 cmd->data[0] = devid;
875 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
876 }
877
878 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
879 size_t size, u16 domid, int pde)
880 {
881 u64 pages;
882 bool s;
883
884 pages = iommu_num_pages(address, size, PAGE_SIZE);
885 s = false;
886
887 if (pages > 1) {
888 /*
889 * If we have to flush more than one page, flush all
890 * TLB entries for this domain
891 */
892 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
893 s = true;
894 }
895
896 address &= PAGE_MASK;
897
898 memset(cmd, 0, sizeof(*cmd));
899 cmd->data[1] |= domid;
900 cmd->data[2] = lower_32_bits(address);
901 cmd->data[3] = upper_32_bits(address);
902 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
903 if (s) /* size bit - we flush more than one 4kb page */
904 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
905 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
907 }
908
909 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
910 u64 address, size_t size)
911 {
912 u64 pages;
913 bool s;
914
915 pages = iommu_num_pages(address, size, PAGE_SIZE);
916 s = false;
917
918 if (pages > 1) {
919 /*
920 * If we have to flush more than one page, flush all
921 * TLB entries for this domain
922 */
923 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
924 s = true;
925 }
926
927 address &= PAGE_MASK;
928
929 memset(cmd, 0, sizeof(*cmd));
930 cmd->data[0] = devid;
931 cmd->data[0] |= (qdep & 0xff) << 24;
932 cmd->data[1] = devid;
933 cmd->data[2] = lower_32_bits(address);
934 cmd->data[3] = upper_32_bits(address);
935 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
936 if (s)
937 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
938 }
939
940 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
941 u64 address, bool size)
942 {
943 memset(cmd, 0, sizeof(*cmd));
944
945 address &= ~(0xfffULL);
946
947 cmd->data[0] = pasid;
948 cmd->data[1] = domid;
949 cmd->data[2] = lower_32_bits(address);
950 cmd->data[3] = upper_32_bits(address);
951 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
952 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
953 if (size)
954 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
955 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
956 }
957
958 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
959 int qdep, u64 address, bool size)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962
963 address &= ~(0xfffULL);
964
965 cmd->data[0] = devid;
966 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
967 cmd->data[0] |= (qdep & 0xff) << 24;
968 cmd->data[1] = devid;
969 cmd->data[1] |= (pasid & 0xff) << 16;
970 cmd->data[2] = lower_32_bits(address);
971 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
972 cmd->data[3] = upper_32_bits(address);
973 if (size)
974 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
975 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
976 }
977
978 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
979 int status, int tag, bool gn)
980 {
981 memset(cmd, 0, sizeof(*cmd));
982
983 cmd->data[0] = devid;
984 if (gn) {
985 cmd->data[1] = pasid;
986 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
987 }
988 cmd->data[3] = tag & 0x1ff;
989 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
990
991 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
992 }
993
994 static void build_inv_all(struct iommu_cmd *cmd)
995 {
996 memset(cmd, 0, sizeof(*cmd));
997 CMD_SET_TYPE(cmd, CMD_INV_ALL);
998 }
999
1000 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
1001 {
1002 memset(cmd, 0, sizeof(*cmd));
1003 cmd->data[0] = devid;
1004 CMD_SET_TYPE(cmd, CMD_INV_IRT);
1005 }
1006
1007 /*
1008 * Writes the command to the IOMMUs command buffer and informs the
1009 * hardware about the new command.
1010 */
1011 static int iommu_queue_command_sync(struct amd_iommu *iommu,
1012 struct iommu_cmd *cmd,
1013 bool sync)
1014 {
1015 u32 left, tail, head, next_tail;
1016 unsigned long flags;
1017
1018 again:
1019 spin_lock_irqsave(&iommu->lock, flags);
1020
1021 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
1022 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
1023 next_tail = (tail + sizeof(*cmd)) % CMD_BUFFER_SIZE;
1024 left = (head - next_tail) % CMD_BUFFER_SIZE;
1025
1026 if (left <= 2) {
1027 struct iommu_cmd sync_cmd;
1028 volatile u64 sem = 0;
1029 int ret;
1030
1031 build_completion_wait(&sync_cmd, (u64)&sem);
1032 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1033
1034 spin_unlock_irqrestore(&iommu->lock, flags);
1035
1036 if ((ret = wait_on_sem(&sem)) != 0)
1037 return ret;
1038
1039 goto again;
1040 }
1041
1042 copy_cmd_to_buffer(iommu, cmd, tail);
1043
1044 /* We need to sync now to make sure all commands are processed */
1045 iommu->need_sync = sync;
1046
1047 spin_unlock_irqrestore(&iommu->lock, flags);
1048
1049 return 0;
1050 }
1051
1052 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1053 {
1054 return iommu_queue_command_sync(iommu, cmd, true);
1055 }
1056
1057 /*
1058 * This function queues a completion wait command into the command
1059 * buffer of an IOMMU
1060 */
1061 static int iommu_completion_wait(struct amd_iommu *iommu)
1062 {
1063 struct iommu_cmd cmd;
1064 volatile u64 sem = 0;
1065 int ret;
1066
1067 if (!iommu->need_sync)
1068 return 0;
1069
1070 build_completion_wait(&cmd, (u64)&sem);
1071
1072 ret = iommu_queue_command_sync(iommu, &cmd, false);
1073 if (ret)
1074 return ret;
1075
1076 return wait_on_sem(&sem);
1077 }
1078
1079 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1080 {
1081 struct iommu_cmd cmd;
1082
1083 build_inv_dte(&cmd, devid);
1084
1085 return iommu_queue_command(iommu, &cmd);
1086 }
1087
1088 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1089 {
1090 u32 devid;
1091
1092 for (devid = 0; devid <= 0xffff; ++devid)
1093 iommu_flush_dte(iommu, devid);
1094
1095 iommu_completion_wait(iommu);
1096 }
1097
1098 /*
1099 * This function uses heavy locking and may disable irqs for some time. But
1100 * this is no issue because it is only called during resume.
1101 */
1102 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1103 {
1104 u32 dom_id;
1105
1106 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1107 struct iommu_cmd cmd;
1108 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1109 dom_id, 1);
1110 iommu_queue_command(iommu, &cmd);
1111 }
1112
1113 iommu_completion_wait(iommu);
1114 }
1115
1116 static void iommu_flush_all(struct amd_iommu *iommu)
1117 {
1118 struct iommu_cmd cmd;
1119
1120 build_inv_all(&cmd);
1121
1122 iommu_queue_command(iommu, &cmd);
1123 iommu_completion_wait(iommu);
1124 }
1125
1126 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1127 {
1128 struct iommu_cmd cmd;
1129
1130 build_inv_irt(&cmd, devid);
1131
1132 iommu_queue_command(iommu, &cmd);
1133 }
1134
1135 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1136 {
1137 u32 devid;
1138
1139 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1140 iommu_flush_irt(iommu, devid);
1141
1142 iommu_completion_wait(iommu);
1143 }
1144
1145 void iommu_flush_all_caches(struct amd_iommu *iommu)
1146 {
1147 if (iommu_feature(iommu, FEATURE_IA)) {
1148 iommu_flush_all(iommu);
1149 } else {
1150 iommu_flush_dte_all(iommu);
1151 iommu_flush_irt_all(iommu);
1152 iommu_flush_tlb_all(iommu);
1153 }
1154 }
1155
1156 /*
1157 * Command send function for flushing on-device TLB
1158 */
1159 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1160 u64 address, size_t size)
1161 {
1162 struct amd_iommu *iommu;
1163 struct iommu_cmd cmd;
1164 int qdep;
1165
1166 qdep = dev_data->ats.qdep;
1167 iommu = amd_iommu_rlookup_table[dev_data->devid];
1168
1169 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1170
1171 return iommu_queue_command(iommu, &cmd);
1172 }
1173
1174 /*
1175 * Command send function for invalidating a device table entry
1176 */
1177 static int device_flush_dte(struct iommu_dev_data *dev_data)
1178 {
1179 struct amd_iommu *iommu;
1180 u16 alias;
1181 int ret;
1182
1183 iommu = amd_iommu_rlookup_table[dev_data->devid];
1184 alias = dev_data->alias;
1185
1186 ret = iommu_flush_dte(iommu, dev_data->devid);
1187 if (!ret && alias != dev_data->devid)
1188 ret = iommu_flush_dte(iommu, alias);
1189 if (ret)
1190 return ret;
1191
1192 if (dev_data->ats.enabled)
1193 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1194
1195 return ret;
1196 }
1197
1198 /*
1199 * TLB invalidation function which is called from the mapping functions.
1200 * It invalidates a single PTE if the range to flush is within a single
1201 * page. Otherwise it flushes the whole TLB of the IOMMU.
1202 */
1203 static void __domain_flush_pages(struct protection_domain *domain,
1204 u64 address, size_t size, int pde)
1205 {
1206 struct iommu_dev_data *dev_data;
1207 struct iommu_cmd cmd;
1208 int ret = 0, i;
1209
1210 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1211
1212 for (i = 0; i < amd_iommus_present; ++i) {
1213 if (!domain->dev_iommu[i])
1214 continue;
1215
1216 /*
1217 * Devices of this domain are behind this IOMMU
1218 * We need a TLB flush
1219 */
1220 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1221 }
1222
1223 list_for_each_entry(dev_data, &domain->dev_list, list) {
1224
1225 if (!dev_data->ats.enabled)
1226 continue;
1227
1228 ret |= device_flush_iotlb(dev_data, address, size);
1229 }
1230
1231 WARN_ON(ret);
1232 }
1233
1234 static void domain_flush_pages(struct protection_domain *domain,
1235 u64 address, size_t size)
1236 {
1237 __domain_flush_pages(domain, address, size, 0);
1238 }
1239
1240 /* Flush the whole IO/TLB for a given protection domain */
1241 static void domain_flush_tlb(struct protection_domain *domain)
1242 {
1243 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1244 }
1245
1246 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1247 static void domain_flush_tlb_pde(struct protection_domain *domain)
1248 {
1249 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1250 }
1251
1252 static void domain_flush_complete(struct protection_domain *domain)
1253 {
1254 int i;
1255
1256 for (i = 0; i < amd_iommus_present; ++i) {
1257 if (domain && !domain->dev_iommu[i])
1258 continue;
1259
1260 /*
1261 * Devices of this domain are behind this IOMMU
1262 * We need to wait for completion of all commands.
1263 */
1264 iommu_completion_wait(amd_iommus[i]);
1265 }
1266 }
1267
1268
1269 /*
1270 * This function flushes the DTEs for all devices in domain
1271 */
1272 static void domain_flush_devices(struct protection_domain *domain)
1273 {
1274 struct iommu_dev_data *dev_data;
1275
1276 list_for_each_entry(dev_data, &domain->dev_list, list)
1277 device_flush_dte(dev_data);
1278 }
1279
1280 /****************************************************************************
1281 *
1282 * The functions below are used the create the page table mappings for
1283 * unity mapped regions.
1284 *
1285 ****************************************************************************/
1286
1287 /*
1288 * This function is used to add another level to an IO page table. Adding
1289 * another level increases the size of the address space by 9 bits to a size up
1290 * to 64 bits.
1291 */
1292 static bool increase_address_space(struct protection_domain *domain,
1293 gfp_t gfp)
1294 {
1295 u64 *pte;
1296
1297 if (domain->mode == PAGE_MODE_6_LEVEL)
1298 /* address space already 64 bit large */
1299 return false;
1300
1301 pte = (void *)get_zeroed_page(gfp);
1302 if (!pte)
1303 return false;
1304
1305 *pte = PM_LEVEL_PDE(domain->mode,
1306 virt_to_phys(domain->pt_root));
1307 domain->pt_root = pte;
1308 domain->mode += 1;
1309 domain->updated = true;
1310
1311 return true;
1312 }
1313
1314 static u64 *alloc_pte(struct protection_domain *domain,
1315 unsigned long address,
1316 unsigned long page_size,
1317 u64 **pte_page,
1318 gfp_t gfp)
1319 {
1320 int level, end_lvl;
1321 u64 *pte, *page;
1322
1323 BUG_ON(!is_power_of_2(page_size));
1324
1325 while (address > PM_LEVEL_SIZE(domain->mode))
1326 increase_address_space(domain, gfp);
1327
1328 level = domain->mode - 1;
1329 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1330 address = PAGE_SIZE_ALIGN(address, page_size);
1331 end_lvl = PAGE_SIZE_LEVEL(page_size);
1332
1333 while (level > end_lvl) {
1334 u64 __pte, __npte;
1335
1336 __pte = *pte;
1337
1338 if (!IOMMU_PTE_PRESENT(__pte)) {
1339 page = (u64 *)get_zeroed_page(gfp);
1340 if (!page)
1341 return NULL;
1342
1343 __npte = PM_LEVEL_PDE(level, virt_to_phys(page));
1344
1345 if (cmpxchg64(pte, __pte, __npte)) {
1346 free_page((unsigned long)page);
1347 continue;
1348 }
1349 }
1350
1351 /* No level skipping support yet */
1352 if (PM_PTE_LEVEL(*pte) != level)
1353 return NULL;
1354
1355 level -= 1;
1356
1357 pte = IOMMU_PTE_PAGE(*pte);
1358
1359 if (pte_page && level == end_lvl)
1360 *pte_page = pte;
1361
1362 pte = &pte[PM_LEVEL_INDEX(level, address)];
1363 }
1364
1365 return pte;
1366 }
1367
1368 /*
1369 * This function checks if there is a PTE for a given dma address. If
1370 * there is one, it returns the pointer to it.
1371 */
1372 static u64 *fetch_pte(struct protection_domain *domain,
1373 unsigned long address,
1374 unsigned long *page_size)
1375 {
1376 int level;
1377 u64 *pte;
1378
1379 if (address > PM_LEVEL_SIZE(domain->mode))
1380 return NULL;
1381
1382 level = domain->mode - 1;
1383 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1384 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1385
1386 while (level > 0) {
1387
1388 /* Not Present */
1389 if (!IOMMU_PTE_PRESENT(*pte))
1390 return NULL;
1391
1392 /* Large PTE */
1393 if (PM_PTE_LEVEL(*pte) == 7 ||
1394 PM_PTE_LEVEL(*pte) == 0)
1395 break;
1396
1397 /* No level skipping support yet */
1398 if (PM_PTE_LEVEL(*pte) != level)
1399 return NULL;
1400
1401 level -= 1;
1402
1403 /* Walk to the next level */
1404 pte = IOMMU_PTE_PAGE(*pte);
1405 pte = &pte[PM_LEVEL_INDEX(level, address)];
1406 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1407 }
1408
1409 if (PM_PTE_LEVEL(*pte) == 0x07) {
1410 unsigned long pte_mask;
1411
1412 /*
1413 * If we have a series of large PTEs, make
1414 * sure to return a pointer to the first one.
1415 */
1416 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1417 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1418 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1419 }
1420
1421 return pte;
1422 }
1423
1424 /*
1425 * Generic mapping functions. It maps a physical address into a DMA
1426 * address space. It allocates the page table pages if necessary.
1427 * In the future it can be extended to a generic mapping function
1428 * supporting all features of AMD IOMMU page tables like level skipping
1429 * and full 64 bit address spaces.
1430 */
1431 static int iommu_map_page(struct protection_domain *dom,
1432 unsigned long bus_addr,
1433 unsigned long phys_addr,
1434 unsigned long page_size,
1435 int prot,
1436 gfp_t gfp)
1437 {
1438 u64 __pte, *pte;
1439 int i, count;
1440
1441 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1442 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1443
1444 if (!(prot & IOMMU_PROT_MASK))
1445 return -EINVAL;
1446
1447 count = PAGE_SIZE_PTE_COUNT(page_size);
1448 pte = alloc_pte(dom, bus_addr, page_size, NULL, gfp);
1449
1450 if (!pte)
1451 return -ENOMEM;
1452
1453 for (i = 0; i < count; ++i)
1454 if (IOMMU_PTE_PRESENT(pte[i]))
1455 return -EBUSY;
1456
1457 if (count > 1) {
1458 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1459 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1460 } else
1461 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1462
1463 if (prot & IOMMU_PROT_IR)
1464 __pte |= IOMMU_PTE_IR;
1465 if (prot & IOMMU_PROT_IW)
1466 __pte |= IOMMU_PTE_IW;
1467
1468 for (i = 0; i < count; ++i)
1469 pte[i] = __pte;
1470
1471 update_domain(dom);
1472
1473 return 0;
1474 }
1475
1476 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1477 unsigned long bus_addr,
1478 unsigned long page_size)
1479 {
1480 unsigned long long unmapped;
1481 unsigned long unmap_size;
1482 u64 *pte;
1483
1484 BUG_ON(!is_power_of_2(page_size));
1485
1486 unmapped = 0;
1487
1488 while (unmapped < page_size) {
1489
1490 pte = fetch_pte(dom, bus_addr, &unmap_size);
1491
1492 if (pte) {
1493 int i, count;
1494
1495 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1496 for (i = 0; i < count; i++)
1497 pte[i] = 0ULL;
1498 }
1499
1500 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1501 unmapped += unmap_size;
1502 }
1503
1504 BUG_ON(unmapped && !is_power_of_2(unmapped));
1505
1506 return unmapped;
1507 }
1508
1509 /****************************************************************************
1510 *
1511 * The next functions belong to the address allocator for the dma_ops
1512 * interface functions.
1513 *
1514 ****************************************************************************/
1515
1516
1517 static unsigned long dma_ops_alloc_iova(struct device *dev,
1518 struct dma_ops_domain *dma_dom,
1519 unsigned int pages, u64 dma_mask)
1520 {
1521 unsigned long pfn = 0;
1522
1523 pages = __roundup_pow_of_two(pages);
1524
1525 if (dma_mask > DMA_BIT_MASK(32))
1526 pfn = alloc_iova_fast(&dma_dom->iovad, pages,
1527 IOVA_PFN(DMA_BIT_MASK(32)));
1528
1529 if (!pfn)
1530 pfn = alloc_iova_fast(&dma_dom->iovad, pages, IOVA_PFN(dma_mask));
1531
1532 return (pfn << PAGE_SHIFT);
1533 }
1534
1535 static void dma_ops_free_iova(struct dma_ops_domain *dma_dom,
1536 unsigned long address,
1537 unsigned int pages)
1538 {
1539 pages = __roundup_pow_of_two(pages);
1540 address >>= PAGE_SHIFT;
1541
1542 free_iova_fast(&dma_dom->iovad, address, pages);
1543 }
1544
1545 /****************************************************************************
1546 *
1547 * The next functions belong to the domain allocation. A domain is
1548 * allocated for every IOMMU as the default domain. If device isolation
1549 * is enabled, every device get its own domain. The most important thing
1550 * about domains is the page table mapping the DMA address space they
1551 * contain.
1552 *
1553 ****************************************************************************/
1554
1555 /*
1556 * This function adds a protection domain to the global protection domain list
1557 */
1558 static void add_domain_to_list(struct protection_domain *domain)
1559 {
1560 unsigned long flags;
1561
1562 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1563 list_add(&domain->list, &amd_iommu_pd_list);
1564 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1565 }
1566
1567 /*
1568 * This function removes a protection domain to the global
1569 * protection domain list
1570 */
1571 static void del_domain_from_list(struct protection_domain *domain)
1572 {
1573 unsigned long flags;
1574
1575 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1576 list_del(&domain->list);
1577 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1578 }
1579
1580 static u16 domain_id_alloc(void)
1581 {
1582 unsigned long flags;
1583 int id;
1584
1585 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1586 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1587 BUG_ON(id == 0);
1588 if (id > 0 && id < MAX_DOMAIN_ID)
1589 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1590 else
1591 id = 0;
1592 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1593
1594 return id;
1595 }
1596
1597 static void domain_id_free(int id)
1598 {
1599 unsigned long flags;
1600
1601 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1602 if (id > 0 && id < MAX_DOMAIN_ID)
1603 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1604 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1605 }
1606
1607 #define DEFINE_FREE_PT_FN(LVL, FN) \
1608 static void free_pt_##LVL (unsigned long __pt) \
1609 { \
1610 unsigned long p; \
1611 u64 *pt; \
1612 int i; \
1613 \
1614 pt = (u64 *)__pt; \
1615 \
1616 for (i = 0; i < 512; ++i) { \
1617 /* PTE present? */ \
1618 if (!IOMMU_PTE_PRESENT(pt[i])) \
1619 continue; \
1620 \
1621 /* Large PTE? */ \
1622 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1623 PM_PTE_LEVEL(pt[i]) == 7) \
1624 continue; \
1625 \
1626 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1627 FN(p); \
1628 } \
1629 free_page((unsigned long)pt); \
1630 }
1631
1632 DEFINE_FREE_PT_FN(l2, free_page)
1633 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1634 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1635 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1636 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1637
1638 static void free_pagetable(struct protection_domain *domain)
1639 {
1640 unsigned long root = (unsigned long)domain->pt_root;
1641
1642 switch (domain->mode) {
1643 case PAGE_MODE_NONE:
1644 break;
1645 case PAGE_MODE_1_LEVEL:
1646 free_page(root);
1647 break;
1648 case PAGE_MODE_2_LEVEL:
1649 free_pt_l2(root);
1650 break;
1651 case PAGE_MODE_3_LEVEL:
1652 free_pt_l3(root);
1653 break;
1654 case PAGE_MODE_4_LEVEL:
1655 free_pt_l4(root);
1656 break;
1657 case PAGE_MODE_5_LEVEL:
1658 free_pt_l5(root);
1659 break;
1660 case PAGE_MODE_6_LEVEL:
1661 free_pt_l6(root);
1662 break;
1663 default:
1664 BUG();
1665 }
1666 }
1667
1668 static void free_gcr3_tbl_level1(u64 *tbl)
1669 {
1670 u64 *ptr;
1671 int i;
1672
1673 for (i = 0; i < 512; ++i) {
1674 if (!(tbl[i] & GCR3_VALID))
1675 continue;
1676
1677 ptr = __va(tbl[i] & PAGE_MASK);
1678
1679 free_page((unsigned long)ptr);
1680 }
1681 }
1682
1683 static void free_gcr3_tbl_level2(u64 *tbl)
1684 {
1685 u64 *ptr;
1686 int i;
1687
1688 for (i = 0; i < 512; ++i) {
1689 if (!(tbl[i] & GCR3_VALID))
1690 continue;
1691
1692 ptr = __va(tbl[i] & PAGE_MASK);
1693
1694 free_gcr3_tbl_level1(ptr);
1695 }
1696 }
1697
1698 static void free_gcr3_table(struct protection_domain *domain)
1699 {
1700 if (domain->glx == 2)
1701 free_gcr3_tbl_level2(domain->gcr3_tbl);
1702 else if (domain->glx == 1)
1703 free_gcr3_tbl_level1(domain->gcr3_tbl);
1704 else
1705 BUG_ON(domain->glx != 0);
1706
1707 free_page((unsigned long)domain->gcr3_tbl);
1708 }
1709
1710 /*
1711 * Free a domain, only used if something went wrong in the
1712 * allocation path and we need to free an already allocated page table
1713 */
1714 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1715 {
1716 if (!dom)
1717 return;
1718
1719 del_domain_from_list(&dom->domain);
1720
1721 put_iova_domain(&dom->iovad);
1722
1723 free_pagetable(&dom->domain);
1724
1725 kfree(dom);
1726 }
1727
1728 /*
1729 * Allocates a new protection domain usable for the dma_ops functions.
1730 * It also initializes the page table and the address allocator data
1731 * structures required for the dma_ops interface
1732 */
1733 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1734 {
1735 struct dma_ops_domain *dma_dom;
1736
1737 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1738 if (!dma_dom)
1739 return NULL;
1740
1741 if (protection_domain_init(&dma_dom->domain))
1742 goto free_dma_dom;
1743
1744 dma_dom->domain.mode = PAGE_MODE_3_LEVEL;
1745 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
1746 dma_dom->domain.flags = PD_DMA_OPS_MASK;
1747 if (!dma_dom->domain.pt_root)
1748 goto free_dma_dom;
1749
1750 init_iova_domain(&dma_dom->iovad, PAGE_SIZE,
1751 IOVA_START_PFN, DMA_32BIT_PFN);
1752
1753 /* Initialize reserved ranges */
1754 copy_reserved_iova(&reserved_iova_ranges, &dma_dom->iovad);
1755
1756 add_domain_to_list(&dma_dom->domain);
1757
1758 return dma_dom;
1759
1760 free_dma_dom:
1761 dma_ops_domain_free(dma_dom);
1762
1763 return NULL;
1764 }
1765
1766 /*
1767 * little helper function to check whether a given protection domain is a
1768 * dma_ops domain
1769 */
1770 static bool dma_ops_domain(struct protection_domain *domain)
1771 {
1772 return domain->flags & PD_DMA_OPS_MASK;
1773 }
1774
1775 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
1776 {
1777 u64 pte_root = 0;
1778 u64 flags = 0;
1779
1780 if (domain->mode != PAGE_MODE_NONE)
1781 pte_root = virt_to_phys(domain->pt_root);
1782
1783 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1784 << DEV_ENTRY_MODE_SHIFT;
1785 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
1786
1787 flags = amd_iommu_dev_table[devid].data[1];
1788
1789 if (ats)
1790 flags |= DTE_FLAG_IOTLB;
1791
1792 if (domain->flags & PD_IOMMUV2_MASK) {
1793 u64 gcr3 = __pa(domain->gcr3_tbl);
1794 u64 glx = domain->glx;
1795 u64 tmp;
1796
1797 pte_root |= DTE_FLAG_GV;
1798 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1799
1800 /* First mask out possible old values for GCR3 table */
1801 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1802 flags &= ~tmp;
1803
1804 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1805 flags &= ~tmp;
1806
1807 /* Encode GCR3 table into DTE */
1808 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1809 pte_root |= tmp;
1810
1811 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1812 flags |= tmp;
1813
1814 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1815 flags |= tmp;
1816 }
1817
1818 flags &= ~(0xffffUL);
1819 flags |= domain->id;
1820
1821 amd_iommu_dev_table[devid].data[1] = flags;
1822 amd_iommu_dev_table[devid].data[0] = pte_root;
1823 }
1824
1825 static void clear_dte_entry(u16 devid)
1826 {
1827 /* remove entry from the device table seen by the hardware */
1828 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1829 amd_iommu_dev_table[devid].data[1] &= DTE_FLAG_MASK;
1830
1831 amd_iommu_apply_erratum_63(devid);
1832 }
1833
1834 static void do_attach(struct iommu_dev_data *dev_data,
1835 struct protection_domain *domain)
1836 {
1837 struct amd_iommu *iommu;
1838 u16 alias;
1839 bool ats;
1840
1841 iommu = amd_iommu_rlookup_table[dev_data->devid];
1842 alias = dev_data->alias;
1843 ats = dev_data->ats.enabled;
1844
1845 /* Update data structures */
1846 dev_data->domain = domain;
1847 list_add(&dev_data->list, &domain->dev_list);
1848
1849 /* Do reference counting */
1850 domain->dev_iommu[iommu->index] += 1;
1851 domain->dev_cnt += 1;
1852
1853 /* Update device table */
1854 set_dte_entry(dev_data->devid, domain, ats);
1855 if (alias != dev_data->devid)
1856 set_dte_entry(alias, domain, ats);
1857
1858 device_flush_dte(dev_data);
1859 }
1860
1861 static void do_detach(struct iommu_dev_data *dev_data)
1862 {
1863 struct amd_iommu *iommu;
1864 u16 alias;
1865
1866 /*
1867 * First check if the device is still attached. It might already
1868 * be detached from its domain because the generic
1869 * iommu_detach_group code detached it and we try again here in
1870 * our alias handling.
1871 */
1872 if (!dev_data->domain)
1873 return;
1874
1875 iommu = amd_iommu_rlookup_table[dev_data->devid];
1876 alias = dev_data->alias;
1877
1878 /* decrease reference counters */
1879 dev_data->domain->dev_iommu[iommu->index] -= 1;
1880 dev_data->domain->dev_cnt -= 1;
1881
1882 /* Update data structures */
1883 dev_data->domain = NULL;
1884 list_del(&dev_data->list);
1885 clear_dte_entry(dev_data->devid);
1886 if (alias != dev_data->devid)
1887 clear_dte_entry(alias);
1888
1889 /* Flush the DTE entry */
1890 device_flush_dte(dev_data);
1891 }
1892
1893 /*
1894 * If a device is not yet associated with a domain, this function does
1895 * assigns it visible for the hardware
1896 */
1897 static int __attach_device(struct iommu_dev_data *dev_data,
1898 struct protection_domain *domain)
1899 {
1900 int ret;
1901
1902 /*
1903 * Must be called with IRQs disabled. Warn here to detect early
1904 * when its not.
1905 */
1906 WARN_ON(!irqs_disabled());
1907
1908 /* lock domain */
1909 spin_lock(&domain->lock);
1910
1911 ret = -EBUSY;
1912 if (dev_data->domain != NULL)
1913 goto out_unlock;
1914
1915 /* Attach alias group root */
1916 do_attach(dev_data, domain);
1917
1918 ret = 0;
1919
1920 out_unlock:
1921
1922 /* ready */
1923 spin_unlock(&domain->lock);
1924
1925 return ret;
1926 }
1927
1928
1929 static void pdev_iommuv2_disable(struct pci_dev *pdev)
1930 {
1931 pci_disable_ats(pdev);
1932 pci_disable_pri(pdev);
1933 pci_disable_pasid(pdev);
1934 }
1935
1936 /* FIXME: Change generic reset-function to do the same */
1937 static int pri_reset_while_enabled(struct pci_dev *pdev)
1938 {
1939 u16 control;
1940 int pos;
1941
1942 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
1943 if (!pos)
1944 return -EINVAL;
1945
1946 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
1947 control |= PCI_PRI_CTRL_RESET;
1948 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
1949
1950 return 0;
1951 }
1952
1953 static int pdev_iommuv2_enable(struct pci_dev *pdev)
1954 {
1955 bool reset_enable;
1956 int reqs, ret;
1957
1958 /* FIXME: Hardcode number of outstanding requests for now */
1959 reqs = 32;
1960 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
1961 reqs = 1;
1962 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
1963
1964 /* Only allow access to user-accessible pages */
1965 ret = pci_enable_pasid(pdev, 0);
1966 if (ret)
1967 goto out_err;
1968
1969 /* First reset the PRI state of the device */
1970 ret = pci_reset_pri(pdev);
1971 if (ret)
1972 goto out_err;
1973
1974 /* Enable PRI */
1975 ret = pci_enable_pri(pdev, reqs);
1976 if (ret)
1977 goto out_err;
1978
1979 if (reset_enable) {
1980 ret = pri_reset_while_enabled(pdev);
1981 if (ret)
1982 goto out_err;
1983 }
1984
1985 ret = pci_enable_ats(pdev, PAGE_SHIFT);
1986 if (ret)
1987 goto out_err;
1988
1989 return 0;
1990
1991 out_err:
1992 pci_disable_pri(pdev);
1993 pci_disable_pasid(pdev);
1994
1995 return ret;
1996 }
1997
1998 /* FIXME: Move this to PCI code */
1999 #define PCI_PRI_TLP_OFF (1 << 15)
2000
2001 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2002 {
2003 u16 status;
2004 int pos;
2005
2006 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2007 if (!pos)
2008 return false;
2009
2010 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2011
2012 return (status & PCI_PRI_TLP_OFF) ? true : false;
2013 }
2014
2015 /*
2016 * If a device is not yet associated with a domain, this function
2017 * assigns it visible for the hardware
2018 */
2019 static int attach_device(struct device *dev,
2020 struct protection_domain *domain)
2021 {
2022 struct pci_dev *pdev;
2023 struct iommu_dev_data *dev_data;
2024 unsigned long flags;
2025 int ret;
2026
2027 dev_data = get_dev_data(dev);
2028
2029 if (!dev_is_pci(dev))
2030 goto skip_ats_check;
2031
2032 pdev = to_pci_dev(dev);
2033 if (domain->flags & PD_IOMMUV2_MASK) {
2034 if (!dev_data->passthrough)
2035 return -EINVAL;
2036
2037 if (dev_data->iommu_v2) {
2038 if (pdev_iommuv2_enable(pdev) != 0)
2039 return -EINVAL;
2040
2041 dev_data->ats.enabled = true;
2042 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2043 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2044 }
2045 } else if (amd_iommu_iotlb_sup &&
2046 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2047 dev_data->ats.enabled = true;
2048 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2049 }
2050
2051 skip_ats_check:
2052 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2053 ret = __attach_device(dev_data, domain);
2054 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2055
2056 /*
2057 * We might boot into a crash-kernel here. The crashed kernel
2058 * left the caches in the IOMMU dirty. So we have to flush
2059 * here to evict all dirty stuff.
2060 */
2061 domain_flush_tlb_pde(domain);
2062
2063 return ret;
2064 }
2065
2066 /*
2067 * Removes a device from a protection domain (unlocked)
2068 */
2069 static void __detach_device(struct iommu_dev_data *dev_data)
2070 {
2071 struct protection_domain *domain;
2072
2073 /*
2074 * Must be called with IRQs disabled. Warn here to detect early
2075 * when its not.
2076 */
2077 WARN_ON(!irqs_disabled());
2078
2079 if (WARN_ON(!dev_data->domain))
2080 return;
2081
2082 domain = dev_data->domain;
2083
2084 spin_lock(&domain->lock);
2085
2086 do_detach(dev_data);
2087
2088 spin_unlock(&domain->lock);
2089 }
2090
2091 /*
2092 * Removes a device from a protection domain (with devtable_lock held)
2093 */
2094 static void detach_device(struct device *dev)
2095 {
2096 struct protection_domain *domain;
2097 struct iommu_dev_data *dev_data;
2098 unsigned long flags;
2099
2100 dev_data = get_dev_data(dev);
2101 domain = dev_data->domain;
2102
2103 /* lock device table */
2104 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2105 __detach_device(dev_data);
2106 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2107
2108 if (!dev_is_pci(dev))
2109 return;
2110
2111 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
2112 pdev_iommuv2_disable(to_pci_dev(dev));
2113 else if (dev_data->ats.enabled)
2114 pci_disable_ats(to_pci_dev(dev));
2115
2116 dev_data->ats.enabled = false;
2117 }
2118
2119 static int amd_iommu_add_device(struct device *dev)
2120 {
2121 struct iommu_dev_data *dev_data;
2122 struct iommu_domain *domain;
2123 struct amd_iommu *iommu;
2124 int ret, devid;
2125
2126 if (!check_device(dev) || get_dev_data(dev))
2127 return 0;
2128
2129 devid = get_device_id(dev);
2130 if (devid < 0)
2131 return devid;
2132
2133 iommu = amd_iommu_rlookup_table[devid];
2134
2135 ret = iommu_init_device(dev);
2136 if (ret) {
2137 if (ret != -ENOTSUPP)
2138 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2139 dev_name(dev));
2140
2141 iommu_ignore_device(dev);
2142 dev->archdata.dma_ops = &nommu_dma_ops;
2143 goto out;
2144 }
2145 init_iommu_group(dev);
2146
2147 dev_data = get_dev_data(dev);
2148
2149 BUG_ON(!dev_data);
2150
2151 if (iommu_pass_through || dev_data->iommu_v2)
2152 iommu_request_dm_for_dev(dev);
2153
2154 /* Domains are initialized for this device - have a look what we ended up with */
2155 domain = iommu_get_domain_for_dev(dev);
2156 if (domain->type == IOMMU_DOMAIN_IDENTITY)
2157 dev_data->passthrough = true;
2158 else
2159 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2160
2161 out:
2162 iommu_completion_wait(iommu);
2163
2164 return 0;
2165 }
2166
2167 static void amd_iommu_remove_device(struct device *dev)
2168 {
2169 struct amd_iommu *iommu;
2170 int devid;
2171
2172 if (!check_device(dev))
2173 return;
2174
2175 devid = get_device_id(dev);
2176 if (devid < 0)
2177 return;
2178
2179 iommu = amd_iommu_rlookup_table[devid];
2180
2181 iommu_uninit_device(dev);
2182 iommu_completion_wait(iommu);
2183 }
2184
2185 static struct iommu_group *amd_iommu_device_group(struct device *dev)
2186 {
2187 if (dev_is_pci(dev))
2188 return pci_device_group(dev);
2189
2190 return acpihid_device_group(dev);
2191 }
2192
2193 /*****************************************************************************
2194 *
2195 * The next functions belong to the dma_ops mapping/unmapping code.
2196 *
2197 *****************************************************************************/
2198
2199 static void __queue_flush(struct flush_queue *queue)
2200 {
2201 struct protection_domain *domain;
2202 unsigned long flags;
2203 int idx;
2204
2205 /* First flush TLB of all known domains */
2206 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
2207 list_for_each_entry(domain, &amd_iommu_pd_list, list)
2208 domain_flush_tlb(domain);
2209 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
2210
2211 /* Wait until flushes have completed */
2212 domain_flush_complete(NULL);
2213
2214 for (idx = 0; idx < queue->next; ++idx) {
2215 struct flush_queue_entry *entry;
2216
2217 entry = queue->entries + idx;
2218
2219 free_iova_fast(&entry->dma_dom->iovad,
2220 entry->iova_pfn,
2221 entry->pages);
2222
2223 /* Not really necessary, just to make sure we catch any bugs */
2224 entry->dma_dom = NULL;
2225 }
2226
2227 queue->next = 0;
2228 }
2229
2230 static void queue_flush_all(void)
2231 {
2232 int cpu;
2233
2234 for_each_possible_cpu(cpu) {
2235 struct flush_queue *queue;
2236 unsigned long flags;
2237
2238 queue = per_cpu_ptr(&flush_queue, cpu);
2239 spin_lock_irqsave(&queue->lock, flags);
2240 if (queue->next > 0)
2241 __queue_flush(queue);
2242 spin_unlock_irqrestore(&queue->lock, flags);
2243 }
2244 }
2245
2246 static void queue_flush_timeout(unsigned long unsused)
2247 {
2248 atomic_set(&queue_timer_on, 0);
2249 queue_flush_all();
2250 }
2251
2252 static void queue_add(struct dma_ops_domain *dma_dom,
2253 unsigned long address, unsigned long pages)
2254 {
2255 struct flush_queue_entry *entry;
2256 struct flush_queue *queue;
2257 unsigned long flags;
2258 int idx;
2259
2260 pages = __roundup_pow_of_two(pages);
2261 address >>= PAGE_SHIFT;
2262
2263 queue = get_cpu_ptr(&flush_queue);
2264 spin_lock_irqsave(&queue->lock, flags);
2265
2266 if (queue->next == FLUSH_QUEUE_SIZE)
2267 __queue_flush(queue);
2268
2269 idx = queue->next++;
2270 entry = queue->entries + idx;
2271
2272 entry->iova_pfn = address;
2273 entry->pages = pages;
2274 entry->dma_dom = dma_dom;
2275
2276 spin_unlock_irqrestore(&queue->lock, flags);
2277
2278 if (atomic_cmpxchg(&queue_timer_on, 0, 1) == 0)
2279 mod_timer(&queue_timer, jiffies + msecs_to_jiffies(10));
2280
2281 put_cpu_ptr(&flush_queue);
2282 }
2283
2284
2285 /*
2286 * In the dma_ops path we only have the struct device. This function
2287 * finds the corresponding IOMMU, the protection domain and the
2288 * requestor id for a given device.
2289 * If the device is not yet associated with a domain this is also done
2290 * in this function.
2291 */
2292 static struct protection_domain *get_domain(struct device *dev)
2293 {
2294 struct protection_domain *domain;
2295
2296 if (!check_device(dev))
2297 return ERR_PTR(-EINVAL);
2298
2299 domain = get_dev_data(dev)->domain;
2300 if (!dma_ops_domain(domain))
2301 return ERR_PTR(-EBUSY);
2302
2303 return domain;
2304 }
2305
2306 static void update_device_table(struct protection_domain *domain)
2307 {
2308 struct iommu_dev_data *dev_data;
2309
2310 list_for_each_entry(dev_data, &domain->dev_list, list) {
2311 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2312
2313 if (dev_data->devid == dev_data->alias)
2314 continue;
2315
2316 /* There is an alias, update device table entry for it */
2317 set_dte_entry(dev_data->alias, domain, dev_data->ats.enabled);
2318 }
2319 }
2320
2321 static void update_domain(struct protection_domain *domain)
2322 {
2323 if (!domain->updated)
2324 return;
2325
2326 update_device_table(domain);
2327
2328 domain_flush_devices(domain);
2329 domain_flush_tlb_pde(domain);
2330
2331 domain->updated = false;
2332 }
2333
2334 static int dir2prot(enum dma_data_direction direction)
2335 {
2336 if (direction == DMA_TO_DEVICE)
2337 return IOMMU_PROT_IR;
2338 else if (direction == DMA_FROM_DEVICE)
2339 return IOMMU_PROT_IW;
2340 else if (direction == DMA_BIDIRECTIONAL)
2341 return IOMMU_PROT_IW | IOMMU_PROT_IR;
2342 else
2343 return 0;
2344 }
2345 /*
2346 * This function contains common code for mapping of a physically
2347 * contiguous memory region into DMA address space. It is used by all
2348 * mapping functions provided with this IOMMU driver.
2349 * Must be called with the domain lock held.
2350 */
2351 static dma_addr_t __map_single(struct device *dev,
2352 struct dma_ops_domain *dma_dom,
2353 phys_addr_t paddr,
2354 size_t size,
2355 enum dma_data_direction direction,
2356 u64 dma_mask)
2357 {
2358 dma_addr_t offset = paddr & ~PAGE_MASK;
2359 dma_addr_t address, start, ret;
2360 unsigned int pages;
2361 int prot = 0;
2362 int i;
2363
2364 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2365 paddr &= PAGE_MASK;
2366
2367 address = dma_ops_alloc_iova(dev, dma_dom, pages, dma_mask);
2368 if (address == DMA_ERROR_CODE)
2369 goto out;
2370
2371 prot = dir2prot(direction);
2372
2373 start = address;
2374 for (i = 0; i < pages; ++i) {
2375 ret = iommu_map_page(&dma_dom->domain, start, paddr,
2376 PAGE_SIZE, prot, GFP_ATOMIC);
2377 if (ret)
2378 goto out_unmap;
2379
2380 paddr += PAGE_SIZE;
2381 start += PAGE_SIZE;
2382 }
2383 address += offset;
2384
2385 if (unlikely(amd_iommu_np_cache)) {
2386 domain_flush_pages(&dma_dom->domain, address, size);
2387 domain_flush_complete(&dma_dom->domain);
2388 }
2389
2390 out:
2391 return address;
2392
2393 out_unmap:
2394
2395 for (--i; i >= 0; --i) {
2396 start -= PAGE_SIZE;
2397 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2398 }
2399
2400 domain_flush_tlb(&dma_dom->domain);
2401 domain_flush_complete(&dma_dom->domain);
2402
2403 dma_ops_free_iova(dma_dom, address, pages);
2404
2405 return DMA_ERROR_CODE;
2406 }
2407
2408 /*
2409 * Does the reverse of the __map_single function. Must be called with
2410 * the domain lock held too
2411 */
2412 static void __unmap_single(struct dma_ops_domain *dma_dom,
2413 dma_addr_t dma_addr,
2414 size_t size,
2415 int dir)
2416 {
2417 dma_addr_t flush_addr;
2418 dma_addr_t i, start;
2419 unsigned int pages;
2420
2421 flush_addr = dma_addr;
2422 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2423 dma_addr &= PAGE_MASK;
2424 start = dma_addr;
2425
2426 for (i = 0; i < pages; ++i) {
2427 iommu_unmap_page(&dma_dom->domain, start, PAGE_SIZE);
2428 start += PAGE_SIZE;
2429 }
2430
2431 if (amd_iommu_unmap_flush) {
2432 dma_ops_free_iova(dma_dom, dma_addr, pages);
2433 domain_flush_tlb(&dma_dom->domain);
2434 domain_flush_complete(&dma_dom->domain);
2435 } else {
2436 queue_add(dma_dom, dma_addr, pages);
2437 }
2438 }
2439
2440 /*
2441 * The exported map_single function for dma_ops.
2442 */
2443 static dma_addr_t map_page(struct device *dev, struct page *page,
2444 unsigned long offset, size_t size,
2445 enum dma_data_direction dir,
2446 unsigned long attrs)
2447 {
2448 phys_addr_t paddr = page_to_phys(page) + offset;
2449 struct protection_domain *domain;
2450 struct dma_ops_domain *dma_dom;
2451 u64 dma_mask;
2452
2453 domain = get_domain(dev);
2454 if (PTR_ERR(domain) == -EINVAL)
2455 return (dma_addr_t)paddr;
2456 else if (IS_ERR(domain))
2457 return DMA_ERROR_CODE;
2458
2459 dma_mask = *dev->dma_mask;
2460 dma_dom = to_dma_ops_domain(domain);
2461
2462 return __map_single(dev, dma_dom, paddr, size, dir, dma_mask);
2463 }
2464
2465 /*
2466 * The exported unmap_single function for dma_ops.
2467 */
2468 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2469 enum dma_data_direction dir, unsigned long attrs)
2470 {
2471 struct protection_domain *domain;
2472 struct dma_ops_domain *dma_dom;
2473
2474 domain = get_domain(dev);
2475 if (IS_ERR(domain))
2476 return;
2477
2478 dma_dom = to_dma_ops_domain(domain);
2479
2480 __unmap_single(dma_dom, dma_addr, size, dir);
2481 }
2482
2483 static int sg_num_pages(struct device *dev,
2484 struct scatterlist *sglist,
2485 int nelems)
2486 {
2487 unsigned long mask, boundary_size;
2488 struct scatterlist *s;
2489 int i, npages = 0;
2490
2491 mask = dma_get_seg_boundary(dev);
2492 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
2493 1UL << (BITS_PER_LONG - PAGE_SHIFT);
2494
2495 for_each_sg(sglist, s, nelems, i) {
2496 int p, n;
2497
2498 s->dma_address = npages << PAGE_SHIFT;
2499 p = npages % boundary_size;
2500 n = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2501 if (p + n > boundary_size)
2502 npages += boundary_size - p;
2503 npages += n;
2504 }
2505
2506 return npages;
2507 }
2508
2509 /*
2510 * The exported map_sg function for dma_ops (handles scatter-gather
2511 * lists).
2512 */
2513 static int map_sg(struct device *dev, struct scatterlist *sglist,
2514 int nelems, enum dma_data_direction direction,
2515 unsigned long attrs)
2516 {
2517 int mapped_pages = 0, npages = 0, prot = 0, i;
2518 struct protection_domain *domain;
2519 struct dma_ops_domain *dma_dom;
2520 struct scatterlist *s;
2521 unsigned long address;
2522 u64 dma_mask;
2523
2524 domain = get_domain(dev);
2525 if (IS_ERR(domain))
2526 return 0;
2527
2528 dma_dom = to_dma_ops_domain(domain);
2529 dma_mask = *dev->dma_mask;
2530
2531 npages = sg_num_pages(dev, sglist, nelems);
2532
2533 address = dma_ops_alloc_iova(dev, dma_dom, npages, dma_mask);
2534 if (address == DMA_ERROR_CODE)
2535 goto out_err;
2536
2537 prot = dir2prot(direction);
2538
2539 /* Map all sg entries */
2540 for_each_sg(sglist, s, nelems, i) {
2541 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2542
2543 for (j = 0; j < pages; ++j) {
2544 unsigned long bus_addr, phys_addr;
2545 int ret;
2546
2547 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2548 phys_addr = (sg_phys(s) & PAGE_MASK) + (j << PAGE_SHIFT);
2549 ret = iommu_map_page(domain, bus_addr, phys_addr, PAGE_SIZE, prot, GFP_ATOMIC);
2550 if (ret)
2551 goto out_unmap;
2552
2553 mapped_pages += 1;
2554 }
2555 }
2556
2557 /* Everything is mapped - write the right values into s->dma_address */
2558 for_each_sg(sglist, s, nelems, i) {
2559 s->dma_address += address + s->offset;
2560 s->dma_length = s->length;
2561 }
2562
2563 return nelems;
2564
2565 out_unmap:
2566 pr_err("%s: IOMMU mapping error in map_sg (io-pages: %d)\n",
2567 dev_name(dev), npages);
2568
2569 for_each_sg(sglist, s, nelems, i) {
2570 int j, pages = iommu_num_pages(sg_phys(s), s->length, PAGE_SIZE);
2571
2572 for (j = 0; j < pages; ++j) {
2573 unsigned long bus_addr;
2574
2575 bus_addr = address + s->dma_address + (j << PAGE_SHIFT);
2576 iommu_unmap_page(domain, bus_addr, PAGE_SIZE);
2577
2578 if (--mapped_pages)
2579 goto out_free_iova;
2580 }
2581 }
2582
2583 out_free_iova:
2584 free_iova_fast(&dma_dom->iovad, address, npages);
2585
2586 out_err:
2587 return 0;
2588 }
2589
2590 /*
2591 * The exported map_sg function for dma_ops (handles scatter-gather
2592 * lists).
2593 */
2594 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2595 int nelems, enum dma_data_direction dir,
2596 unsigned long attrs)
2597 {
2598 struct protection_domain *domain;
2599 struct dma_ops_domain *dma_dom;
2600 unsigned long startaddr;
2601 int npages = 2;
2602
2603 domain = get_domain(dev);
2604 if (IS_ERR(domain))
2605 return;
2606
2607 startaddr = sg_dma_address(sglist) & PAGE_MASK;
2608 dma_dom = to_dma_ops_domain(domain);
2609 npages = sg_num_pages(dev, sglist, nelems);
2610
2611 __unmap_single(dma_dom, startaddr, npages << PAGE_SHIFT, dir);
2612 }
2613
2614 /*
2615 * The exported alloc_coherent function for dma_ops.
2616 */
2617 static void *alloc_coherent(struct device *dev, size_t size,
2618 dma_addr_t *dma_addr, gfp_t flag,
2619 unsigned long attrs)
2620 {
2621 u64 dma_mask = dev->coherent_dma_mask;
2622 struct protection_domain *domain;
2623 struct dma_ops_domain *dma_dom;
2624 struct page *page;
2625
2626 domain = get_domain(dev);
2627 if (PTR_ERR(domain) == -EINVAL) {
2628 page = alloc_pages(flag, get_order(size));
2629 *dma_addr = page_to_phys(page);
2630 return page_address(page);
2631 } else if (IS_ERR(domain))
2632 return NULL;
2633
2634 dma_dom = to_dma_ops_domain(domain);
2635 size = PAGE_ALIGN(size);
2636 dma_mask = dev->coherent_dma_mask;
2637 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2638 flag |= __GFP_ZERO;
2639
2640 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2641 if (!page) {
2642 if (!gfpflags_allow_blocking(flag))
2643 return NULL;
2644
2645 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2646 get_order(size));
2647 if (!page)
2648 return NULL;
2649 }
2650
2651 if (!dma_mask)
2652 dma_mask = *dev->dma_mask;
2653
2654 *dma_addr = __map_single(dev, dma_dom, page_to_phys(page),
2655 size, DMA_BIDIRECTIONAL, dma_mask);
2656
2657 if (*dma_addr == DMA_ERROR_CODE)
2658 goto out_free;
2659
2660 return page_address(page);
2661
2662 out_free:
2663
2664 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2665 __free_pages(page, get_order(size));
2666
2667 return NULL;
2668 }
2669
2670 /*
2671 * The exported free_coherent function for dma_ops.
2672 */
2673 static void free_coherent(struct device *dev, size_t size,
2674 void *virt_addr, dma_addr_t dma_addr,
2675 unsigned long attrs)
2676 {
2677 struct protection_domain *domain;
2678 struct dma_ops_domain *dma_dom;
2679 struct page *page;
2680
2681 page = virt_to_page(virt_addr);
2682 size = PAGE_ALIGN(size);
2683
2684 domain = get_domain(dev);
2685 if (IS_ERR(domain))
2686 goto free_mem;
2687
2688 dma_dom = to_dma_ops_domain(domain);
2689
2690 __unmap_single(dma_dom, dma_addr, size, DMA_BIDIRECTIONAL);
2691
2692 free_mem:
2693 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2694 __free_pages(page, get_order(size));
2695 }
2696
2697 /*
2698 * This function is called by the DMA layer to find out if we can handle a
2699 * particular device. It is part of the dma_ops.
2700 */
2701 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2702 {
2703 return check_device(dev);
2704 }
2705
2706 static struct dma_map_ops amd_iommu_dma_ops = {
2707 .alloc = alloc_coherent,
2708 .free = free_coherent,
2709 .map_page = map_page,
2710 .unmap_page = unmap_page,
2711 .map_sg = map_sg,
2712 .unmap_sg = unmap_sg,
2713 .dma_supported = amd_iommu_dma_supported,
2714 };
2715
2716 static int init_reserved_iova_ranges(void)
2717 {
2718 struct pci_dev *pdev = NULL;
2719 struct iova *val;
2720
2721 init_iova_domain(&reserved_iova_ranges, PAGE_SIZE,
2722 IOVA_START_PFN, DMA_32BIT_PFN);
2723
2724 lockdep_set_class(&reserved_iova_ranges.iova_rbtree_lock,
2725 &reserved_rbtree_key);
2726
2727 /* MSI memory range */
2728 val = reserve_iova(&reserved_iova_ranges,
2729 IOVA_PFN(MSI_RANGE_START), IOVA_PFN(MSI_RANGE_END));
2730 if (!val) {
2731 pr_err("Reserving MSI range failed\n");
2732 return -ENOMEM;
2733 }
2734
2735 /* HT memory range */
2736 val = reserve_iova(&reserved_iova_ranges,
2737 IOVA_PFN(HT_RANGE_START), IOVA_PFN(HT_RANGE_END));
2738 if (!val) {
2739 pr_err("Reserving HT range failed\n");
2740 return -ENOMEM;
2741 }
2742
2743 /*
2744 * Memory used for PCI resources
2745 * FIXME: Check whether we can reserve the PCI-hole completly
2746 */
2747 for_each_pci_dev(pdev) {
2748 int i;
2749
2750 for (i = 0; i < PCI_NUM_RESOURCES; ++i) {
2751 struct resource *r = &pdev->resource[i];
2752
2753 if (!(r->flags & IORESOURCE_MEM))
2754 continue;
2755
2756 val = reserve_iova(&reserved_iova_ranges,
2757 IOVA_PFN(r->start),
2758 IOVA_PFN(r->end));
2759 if (!val) {
2760 pr_err("Reserve pci-resource range failed\n");
2761 return -ENOMEM;
2762 }
2763 }
2764 }
2765
2766 return 0;
2767 }
2768
2769 int __init amd_iommu_init_api(void)
2770 {
2771 int ret, cpu, err = 0;
2772
2773 ret = iova_cache_get();
2774 if (ret)
2775 return ret;
2776
2777 ret = init_reserved_iova_ranges();
2778 if (ret)
2779 return ret;
2780
2781 for_each_possible_cpu(cpu) {
2782 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2783
2784 queue->entries = kzalloc(FLUSH_QUEUE_SIZE *
2785 sizeof(*queue->entries),
2786 GFP_KERNEL);
2787 if (!queue->entries)
2788 goto out_put_iova;
2789
2790 spin_lock_init(&queue->lock);
2791 }
2792
2793 err = bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
2794 if (err)
2795 return err;
2796 #ifdef CONFIG_ARM_AMBA
2797 err = bus_set_iommu(&amba_bustype, &amd_iommu_ops);
2798 if (err)
2799 return err;
2800 #endif
2801 err = bus_set_iommu(&platform_bus_type, &amd_iommu_ops);
2802 if (err)
2803 return err;
2804 return 0;
2805
2806 out_put_iova:
2807 for_each_possible_cpu(cpu) {
2808 struct flush_queue *queue = per_cpu_ptr(&flush_queue, cpu);
2809
2810 kfree(queue->entries);
2811 }
2812
2813 return -ENOMEM;
2814 }
2815
2816 int __init amd_iommu_init_dma_ops(void)
2817 {
2818 setup_timer(&queue_timer, queue_flush_timeout, 0);
2819 atomic_set(&queue_timer_on, 0);
2820
2821 swiotlb = iommu_pass_through ? 1 : 0;
2822 iommu_detected = 1;
2823
2824 /*
2825 * In case we don't initialize SWIOTLB (actually the common case
2826 * when AMD IOMMU is enabled), make sure there are global
2827 * dma_ops set as a fall-back for devices not handled by this
2828 * driver (for example non-PCI devices).
2829 */
2830 if (!swiotlb)
2831 dma_ops = &nommu_dma_ops;
2832
2833 if (amd_iommu_unmap_flush)
2834 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2835 else
2836 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2837
2838 return 0;
2839
2840 }
2841
2842 /*****************************************************************************
2843 *
2844 * The following functions belong to the exported interface of AMD IOMMU
2845 *
2846 * This interface allows access to lower level functions of the IOMMU
2847 * like protection domain handling and assignement of devices to domains
2848 * which is not possible with the dma_ops interface.
2849 *
2850 *****************************************************************************/
2851
2852 static void cleanup_domain(struct protection_domain *domain)
2853 {
2854 struct iommu_dev_data *entry;
2855 unsigned long flags;
2856
2857 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2858
2859 while (!list_empty(&domain->dev_list)) {
2860 entry = list_first_entry(&domain->dev_list,
2861 struct iommu_dev_data, list);
2862 __detach_device(entry);
2863 }
2864
2865 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2866 }
2867
2868 static void protection_domain_free(struct protection_domain *domain)
2869 {
2870 if (!domain)
2871 return;
2872
2873 del_domain_from_list(domain);
2874
2875 if (domain->id)
2876 domain_id_free(domain->id);
2877
2878 kfree(domain);
2879 }
2880
2881 static int protection_domain_init(struct protection_domain *domain)
2882 {
2883 spin_lock_init(&domain->lock);
2884 mutex_init(&domain->api_lock);
2885 domain->id = domain_id_alloc();
2886 if (!domain->id)
2887 return -ENOMEM;
2888 INIT_LIST_HEAD(&domain->dev_list);
2889
2890 return 0;
2891 }
2892
2893 static struct protection_domain *protection_domain_alloc(void)
2894 {
2895 struct protection_domain *domain;
2896
2897 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2898 if (!domain)
2899 return NULL;
2900
2901 if (protection_domain_init(domain))
2902 goto out_err;
2903
2904 add_domain_to_list(domain);
2905
2906 return domain;
2907
2908 out_err:
2909 kfree(domain);
2910
2911 return NULL;
2912 }
2913
2914 static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2915 {
2916 struct protection_domain *pdomain;
2917 struct dma_ops_domain *dma_domain;
2918
2919 switch (type) {
2920 case IOMMU_DOMAIN_UNMANAGED:
2921 pdomain = protection_domain_alloc();
2922 if (!pdomain)
2923 return NULL;
2924
2925 pdomain->mode = PAGE_MODE_3_LEVEL;
2926 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2927 if (!pdomain->pt_root) {
2928 protection_domain_free(pdomain);
2929 return NULL;
2930 }
2931
2932 pdomain->domain.geometry.aperture_start = 0;
2933 pdomain->domain.geometry.aperture_end = ~0ULL;
2934 pdomain->domain.geometry.force_aperture = true;
2935
2936 break;
2937 case IOMMU_DOMAIN_DMA:
2938 dma_domain = dma_ops_domain_alloc();
2939 if (!dma_domain) {
2940 pr_err("AMD-Vi: Failed to allocate\n");
2941 return NULL;
2942 }
2943 pdomain = &dma_domain->domain;
2944 break;
2945 case IOMMU_DOMAIN_IDENTITY:
2946 pdomain = protection_domain_alloc();
2947 if (!pdomain)
2948 return NULL;
2949
2950 pdomain->mode = PAGE_MODE_NONE;
2951 break;
2952 default:
2953 return NULL;
2954 }
2955
2956 return &pdomain->domain;
2957 }
2958
2959 static void amd_iommu_domain_free(struct iommu_domain *dom)
2960 {
2961 struct protection_domain *domain;
2962 struct dma_ops_domain *dma_dom;
2963
2964 domain = to_pdomain(dom);
2965
2966 if (domain->dev_cnt > 0)
2967 cleanup_domain(domain);
2968
2969 BUG_ON(domain->dev_cnt != 0);
2970
2971 if (!dom)
2972 return;
2973
2974 switch (dom->type) {
2975 case IOMMU_DOMAIN_DMA:
2976 /*
2977 * First make sure the domain is no longer referenced from the
2978 * flush queue
2979 */
2980 queue_flush_all();
2981
2982 /* Now release the domain */
2983 dma_dom = to_dma_ops_domain(domain);
2984 dma_ops_domain_free(dma_dom);
2985 break;
2986 default:
2987 if (domain->mode != PAGE_MODE_NONE)
2988 free_pagetable(domain);
2989
2990 if (domain->flags & PD_IOMMUV2_MASK)
2991 free_gcr3_table(domain);
2992
2993 protection_domain_free(domain);
2994 break;
2995 }
2996 }
2997
2998 static void amd_iommu_detach_device(struct iommu_domain *dom,
2999 struct device *dev)
3000 {
3001 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3002 struct amd_iommu *iommu;
3003 int devid;
3004
3005 if (!check_device(dev))
3006 return;
3007
3008 devid = get_device_id(dev);
3009 if (devid < 0)
3010 return;
3011
3012 if (dev_data->domain != NULL)
3013 detach_device(dev);
3014
3015 iommu = amd_iommu_rlookup_table[devid];
3016 if (!iommu)
3017 return;
3018
3019 #ifdef CONFIG_IRQ_REMAP
3020 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
3021 (dom->type == IOMMU_DOMAIN_UNMANAGED))
3022 dev_data->use_vapic = 0;
3023 #endif
3024
3025 iommu_completion_wait(iommu);
3026 }
3027
3028 static int amd_iommu_attach_device(struct iommu_domain *dom,
3029 struct device *dev)
3030 {
3031 struct protection_domain *domain = to_pdomain(dom);
3032 struct iommu_dev_data *dev_data;
3033 struct amd_iommu *iommu;
3034 int ret;
3035
3036 if (!check_device(dev))
3037 return -EINVAL;
3038
3039 dev_data = dev->archdata.iommu;
3040
3041 iommu = amd_iommu_rlookup_table[dev_data->devid];
3042 if (!iommu)
3043 return -EINVAL;
3044
3045 if (dev_data->domain)
3046 detach_device(dev);
3047
3048 ret = attach_device(dev, domain);
3049
3050 #ifdef CONFIG_IRQ_REMAP
3051 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
3052 if (dom->type == IOMMU_DOMAIN_UNMANAGED)
3053 dev_data->use_vapic = 1;
3054 else
3055 dev_data->use_vapic = 0;
3056 }
3057 #endif
3058
3059 iommu_completion_wait(iommu);
3060
3061 return ret;
3062 }
3063
3064 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3065 phys_addr_t paddr, size_t page_size, int iommu_prot)
3066 {
3067 struct protection_domain *domain = to_pdomain(dom);
3068 int prot = 0;
3069 int ret;
3070
3071 if (domain->mode == PAGE_MODE_NONE)
3072 return -EINVAL;
3073
3074 if (iommu_prot & IOMMU_READ)
3075 prot |= IOMMU_PROT_IR;
3076 if (iommu_prot & IOMMU_WRITE)
3077 prot |= IOMMU_PROT_IW;
3078
3079 mutex_lock(&domain->api_lock);
3080 ret = iommu_map_page(domain, iova, paddr, page_size, prot, GFP_KERNEL);
3081 mutex_unlock(&domain->api_lock);
3082
3083 return ret;
3084 }
3085
3086 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3087 size_t page_size)
3088 {
3089 struct protection_domain *domain = to_pdomain(dom);
3090 size_t unmap_size;
3091
3092 if (domain->mode == PAGE_MODE_NONE)
3093 return -EINVAL;
3094
3095 mutex_lock(&domain->api_lock);
3096 unmap_size = iommu_unmap_page(domain, iova, page_size);
3097 mutex_unlock(&domain->api_lock);
3098
3099 domain_flush_tlb_pde(domain);
3100
3101 return unmap_size;
3102 }
3103
3104 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3105 dma_addr_t iova)
3106 {
3107 struct protection_domain *domain = to_pdomain(dom);
3108 unsigned long offset_mask, pte_pgsize;
3109 u64 *pte, __pte;
3110
3111 if (domain->mode == PAGE_MODE_NONE)
3112 return iova;
3113
3114 pte = fetch_pte(domain, iova, &pte_pgsize);
3115
3116 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3117 return 0;
3118
3119 offset_mask = pte_pgsize - 1;
3120 __pte = *pte & PM_ADDR_MASK;
3121
3122 return (__pte & ~offset_mask) | (iova & offset_mask);
3123 }
3124
3125 static bool amd_iommu_capable(enum iommu_cap cap)
3126 {
3127 switch (cap) {
3128 case IOMMU_CAP_CACHE_COHERENCY:
3129 return true;
3130 case IOMMU_CAP_INTR_REMAP:
3131 return (irq_remapping_enabled == 1);
3132 case IOMMU_CAP_NOEXEC:
3133 return false;
3134 }
3135
3136 return false;
3137 }
3138
3139 static void amd_iommu_get_dm_regions(struct device *dev,
3140 struct list_head *head)
3141 {
3142 struct unity_map_entry *entry;
3143 int devid;
3144
3145 devid = get_device_id(dev);
3146 if (devid < 0)
3147 return;
3148
3149 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3150 struct iommu_dm_region *region;
3151
3152 if (devid < entry->devid_start || devid > entry->devid_end)
3153 continue;
3154
3155 region = kzalloc(sizeof(*region), GFP_KERNEL);
3156 if (!region) {
3157 pr_err("Out of memory allocating dm-regions for %s\n",
3158 dev_name(dev));
3159 return;
3160 }
3161
3162 region->start = entry->address_start;
3163 region->length = entry->address_end - entry->address_start;
3164 if (entry->prot & IOMMU_PROT_IR)
3165 region->prot |= IOMMU_READ;
3166 if (entry->prot & IOMMU_PROT_IW)
3167 region->prot |= IOMMU_WRITE;
3168
3169 list_add_tail(&region->list, head);
3170 }
3171 }
3172
3173 static void amd_iommu_put_dm_regions(struct device *dev,
3174 struct list_head *head)
3175 {
3176 struct iommu_dm_region *entry, *next;
3177
3178 list_for_each_entry_safe(entry, next, head, list)
3179 kfree(entry);
3180 }
3181
3182 static void amd_iommu_apply_dm_region(struct device *dev,
3183 struct iommu_domain *domain,
3184 struct iommu_dm_region *region)
3185 {
3186 struct dma_ops_domain *dma_dom = to_dma_ops_domain(to_pdomain(domain));
3187 unsigned long start, end;
3188
3189 start = IOVA_PFN(region->start);
3190 end = IOVA_PFN(region->start + region->length);
3191
3192 WARN_ON_ONCE(reserve_iova(&dma_dom->iovad, start, end) == NULL);
3193 }
3194
3195 static const struct iommu_ops amd_iommu_ops = {
3196 .capable = amd_iommu_capable,
3197 .domain_alloc = amd_iommu_domain_alloc,
3198 .domain_free = amd_iommu_domain_free,
3199 .attach_dev = amd_iommu_attach_device,
3200 .detach_dev = amd_iommu_detach_device,
3201 .map = amd_iommu_map,
3202 .unmap = amd_iommu_unmap,
3203 .map_sg = default_iommu_map_sg,
3204 .iova_to_phys = amd_iommu_iova_to_phys,
3205 .add_device = amd_iommu_add_device,
3206 .remove_device = amd_iommu_remove_device,
3207 .device_group = amd_iommu_device_group,
3208 .get_dm_regions = amd_iommu_get_dm_regions,
3209 .put_dm_regions = amd_iommu_put_dm_regions,
3210 .apply_dm_region = amd_iommu_apply_dm_region,
3211 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3212 };
3213
3214 /*****************************************************************************
3215 *
3216 * The next functions do a basic initialization of IOMMU for pass through
3217 * mode
3218 *
3219 * In passthrough mode the IOMMU is initialized and enabled but not used for
3220 * DMA-API translation.
3221 *
3222 *****************************************************************************/
3223
3224 /* IOMMUv2 specific functions */
3225 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3226 {
3227 return atomic_notifier_chain_register(&ppr_notifier, nb);
3228 }
3229 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3230
3231 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3232 {
3233 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3234 }
3235 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3236
3237 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3238 {
3239 struct protection_domain *domain = to_pdomain(dom);
3240 unsigned long flags;
3241
3242 spin_lock_irqsave(&domain->lock, flags);
3243
3244 /* Update data structure */
3245 domain->mode = PAGE_MODE_NONE;
3246 domain->updated = true;
3247
3248 /* Make changes visible to IOMMUs */
3249 update_domain(domain);
3250
3251 /* Page-table is not visible to IOMMU anymore, so free it */
3252 free_pagetable(domain);
3253
3254 spin_unlock_irqrestore(&domain->lock, flags);
3255 }
3256 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3257
3258 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3259 {
3260 struct protection_domain *domain = to_pdomain(dom);
3261 unsigned long flags;
3262 int levels, ret;
3263
3264 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3265 return -EINVAL;
3266
3267 /* Number of GCR3 table levels required */
3268 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3269 levels += 1;
3270
3271 if (levels > amd_iommu_max_glx_val)
3272 return -EINVAL;
3273
3274 spin_lock_irqsave(&domain->lock, flags);
3275
3276 /*
3277 * Save us all sanity checks whether devices already in the
3278 * domain support IOMMUv2. Just force that the domain has no
3279 * devices attached when it is switched into IOMMUv2 mode.
3280 */
3281 ret = -EBUSY;
3282 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3283 goto out;
3284
3285 ret = -ENOMEM;
3286 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3287 if (domain->gcr3_tbl == NULL)
3288 goto out;
3289
3290 domain->glx = levels;
3291 domain->flags |= PD_IOMMUV2_MASK;
3292 domain->updated = true;
3293
3294 update_domain(domain);
3295
3296 ret = 0;
3297
3298 out:
3299 spin_unlock_irqrestore(&domain->lock, flags);
3300
3301 return ret;
3302 }
3303 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3304
3305 static int __flush_pasid(struct protection_domain *domain, int pasid,
3306 u64 address, bool size)
3307 {
3308 struct iommu_dev_data *dev_data;
3309 struct iommu_cmd cmd;
3310 int i, ret;
3311
3312 if (!(domain->flags & PD_IOMMUV2_MASK))
3313 return -EINVAL;
3314
3315 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3316
3317 /*
3318 * IOMMU TLB needs to be flushed before Device TLB to
3319 * prevent device TLB refill from IOMMU TLB
3320 */
3321 for (i = 0; i < amd_iommus_present; ++i) {
3322 if (domain->dev_iommu[i] == 0)
3323 continue;
3324
3325 ret = iommu_queue_command(amd_iommus[i], &cmd);
3326 if (ret != 0)
3327 goto out;
3328 }
3329
3330 /* Wait until IOMMU TLB flushes are complete */
3331 domain_flush_complete(domain);
3332
3333 /* Now flush device TLBs */
3334 list_for_each_entry(dev_data, &domain->dev_list, list) {
3335 struct amd_iommu *iommu;
3336 int qdep;
3337
3338 /*
3339 There might be non-IOMMUv2 capable devices in an IOMMUv2
3340 * domain.
3341 */
3342 if (!dev_data->ats.enabled)
3343 continue;
3344
3345 qdep = dev_data->ats.qdep;
3346 iommu = amd_iommu_rlookup_table[dev_data->devid];
3347
3348 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3349 qdep, address, size);
3350
3351 ret = iommu_queue_command(iommu, &cmd);
3352 if (ret != 0)
3353 goto out;
3354 }
3355
3356 /* Wait until all device TLBs are flushed */
3357 domain_flush_complete(domain);
3358
3359 ret = 0;
3360
3361 out:
3362
3363 return ret;
3364 }
3365
3366 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3367 u64 address)
3368 {
3369 return __flush_pasid(domain, pasid, address, false);
3370 }
3371
3372 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3373 u64 address)
3374 {
3375 struct protection_domain *domain = to_pdomain(dom);
3376 unsigned long flags;
3377 int ret;
3378
3379 spin_lock_irqsave(&domain->lock, flags);
3380 ret = __amd_iommu_flush_page(domain, pasid, address);
3381 spin_unlock_irqrestore(&domain->lock, flags);
3382
3383 return ret;
3384 }
3385 EXPORT_SYMBOL(amd_iommu_flush_page);
3386
3387 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3388 {
3389 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3390 true);
3391 }
3392
3393 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3394 {
3395 struct protection_domain *domain = to_pdomain(dom);
3396 unsigned long flags;
3397 int ret;
3398
3399 spin_lock_irqsave(&domain->lock, flags);
3400 ret = __amd_iommu_flush_tlb(domain, pasid);
3401 spin_unlock_irqrestore(&domain->lock, flags);
3402
3403 return ret;
3404 }
3405 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3406
3407 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3408 {
3409 int index;
3410 u64 *pte;
3411
3412 while (true) {
3413
3414 index = (pasid >> (9 * level)) & 0x1ff;
3415 pte = &root[index];
3416
3417 if (level == 0)
3418 break;
3419
3420 if (!(*pte & GCR3_VALID)) {
3421 if (!alloc)
3422 return NULL;
3423
3424 root = (void *)get_zeroed_page(GFP_ATOMIC);
3425 if (root == NULL)
3426 return NULL;
3427
3428 *pte = __pa(root) | GCR3_VALID;
3429 }
3430
3431 root = __va(*pte & PAGE_MASK);
3432
3433 level -= 1;
3434 }
3435
3436 return pte;
3437 }
3438
3439 static int __set_gcr3(struct protection_domain *domain, int pasid,
3440 unsigned long cr3)
3441 {
3442 u64 *pte;
3443
3444 if (domain->mode != PAGE_MODE_NONE)
3445 return -EINVAL;
3446
3447 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3448 if (pte == NULL)
3449 return -ENOMEM;
3450
3451 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3452
3453 return __amd_iommu_flush_tlb(domain, pasid);
3454 }
3455
3456 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3457 {
3458 u64 *pte;
3459
3460 if (domain->mode != PAGE_MODE_NONE)
3461 return -EINVAL;
3462
3463 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3464 if (pte == NULL)
3465 return 0;
3466
3467 *pte = 0;
3468
3469 return __amd_iommu_flush_tlb(domain, pasid);
3470 }
3471
3472 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3473 unsigned long cr3)
3474 {
3475 struct protection_domain *domain = to_pdomain(dom);
3476 unsigned long flags;
3477 int ret;
3478
3479 spin_lock_irqsave(&domain->lock, flags);
3480 ret = __set_gcr3(domain, pasid, cr3);
3481 spin_unlock_irqrestore(&domain->lock, flags);
3482
3483 return ret;
3484 }
3485 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3486
3487 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3488 {
3489 struct protection_domain *domain = to_pdomain(dom);
3490 unsigned long flags;
3491 int ret;
3492
3493 spin_lock_irqsave(&domain->lock, flags);
3494 ret = __clear_gcr3(domain, pasid);
3495 spin_unlock_irqrestore(&domain->lock, flags);
3496
3497 return ret;
3498 }
3499 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3500
3501 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3502 int status, int tag)
3503 {
3504 struct iommu_dev_data *dev_data;
3505 struct amd_iommu *iommu;
3506 struct iommu_cmd cmd;
3507
3508 dev_data = get_dev_data(&pdev->dev);
3509 iommu = amd_iommu_rlookup_table[dev_data->devid];
3510
3511 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3512 tag, dev_data->pri_tlp);
3513
3514 return iommu_queue_command(iommu, &cmd);
3515 }
3516 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3517
3518 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3519 {
3520 struct protection_domain *pdomain;
3521
3522 pdomain = get_domain(&pdev->dev);
3523 if (IS_ERR(pdomain))
3524 return NULL;
3525
3526 /* Only return IOMMUv2 domains */
3527 if (!(pdomain->flags & PD_IOMMUV2_MASK))
3528 return NULL;
3529
3530 return &pdomain->domain;
3531 }
3532 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3533
3534 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3535 {
3536 struct iommu_dev_data *dev_data;
3537
3538 if (!amd_iommu_v2_supported())
3539 return;
3540
3541 dev_data = get_dev_data(&pdev->dev);
3542 dev_data->errata |= (1 << erratum);
3543 }
3544 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3545
3546 int amd_iommu_device_info(struct pci_dev *pdev,
3547 struct amd_iommu_device_info *info)
3548 {
3549 int max_pasids;
3550 int pos;
3551
3552 if (pdev == NULL || info == NULL)
3553 return -EINVAL;
3554
3555 if (!amd_iommu_v2_supported())
3556 return -EINVAL;
3557
3558 memset(info, 0, sizeof(*info));
3559
3560 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3561 if (pos)
3562 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3563
3564 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3565 if (pos)
3566 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3567
3568 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3569 if (pos) {
3570 int features;
3571
3572 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3573 max_pasids = min(max_pasids, (1 << 20));
3574
3575 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3576 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3577
3578 features = pci_pasid_features(pdev);
3579 if (features & PCI_PASID_CAP_EXEC)
3580 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3581 if (features & PCI_PASID_CAP_PRIV)
3582 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3583 }
3584
3585 return 0;
3586 }
3587 EXPORT_SYMBOL(amd_iommu_device_info);
3588
3589 #ifdef CONFIG_IRQ_REMAP
3590
3591 /*****************************************************************************
3592 *
3593 * Interrupt Remapping Implementation
3594 *
3595 *****************************************************************************/
3596
3597 static struct irq_chip amd_ir_chip;
3598
3599 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3600 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3601 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3602 #define DTE_IRQ_REMAP_ENABLE 1ULL
3603
3604 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3605 {
3606 u64 dte;
3607
3608 dte = amd_iommu_dev_table[devid].data[2];
3609 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3610 dte |= virt_to_phys(table->table);
3611 dte |= DTE_IRQ_REMAP_INTCTL;
3612 dte |= DTE_IRQ_TABLE_LEN;
3613 dte |= DTE_IRQ_REMAP_ENABLE;
3614
3615 amd_iommu_dev_table[devid].data[2] = dte;
3616 }
3617
3618 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3619 {
3620 struct irq_remap_table *table = NULL;
3621 struct amd_iommu *iommu;
3622 unsigned long flags;
3623 u16 alias;
3624
3625 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3626
3627 iommu = amd_iommu_rlookup_table[devid];
3628 if (!iommu)
3629 goto out_unlock;
3630
3631 table = irq_lookup_table[devid];
3632 if (table)
3633 goto out;
3634
3635 alias = amd_iommu_alias_table[devid];
3636 table = irq_lookup_table[alias];
3637 if (table) {
3638 irq_lookup_table[devid] = table;
3639 set_dte_irq_entry(devid, table);
3640 iommu_flush_dte(iommu, devid);
3641 goto out;
3642 }
3643
3644 /* Nothing there yet, allocate new irq remapping table */
3645 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3646 if (!table)
3647 goto out;
3648
3649 /* Initialize table spin-lock */
3650 spin_lock_init(&table->lock);
3651
3652 if (ioapic)
3653 /* Keep the first 32 indexes free for IOAPIC interrupts */
3654 table->min_index = 32;
3655
3656 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3657 if (!table->table) {
3658 kfree(table);
3659 table = NULL;
3660 goto out;
3661 }
3662
3663 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
3664 memset(table->table, 0,
3665 MAX_IRQS_PER_TABLE * sizeof(u32));
3666 else
3667 memset(table->table, 0,
3668 (MAX_IRQS_PER_TABLE * (sizeof(u64) * 2)));
3669
3670 if (ioapic) {
3671 int i;
3672
3673 for (i = 0; i < 32; ++i)
3674 iommu->irte_ops->set_allocated(table, i);
3675 }
3676
3677 irq_lookup_table[devid] = table;
3678 set_dte_irq_entry(devid, table);
3679 iommu_flush_dte(iommu, devid);
3680 if (devid != alias) {
3681 irq_lookup_table[alias] = table;
3682 set_dte_irq_entry(alias, table);
3683 iommu_flush_dte(iommu, alias);
3684 }
3685
3686 out:
3687 iommu_completion_wait(iommu);
3688
3689 out_unlock:
3690 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3691
3692 return table;
3693 }
3694
3695 static int alloc_irq_index(u16 devid, int count)
3696 {
3697 struct irq_remap_table *table;
3698 unsigned long flags;
3699 int index, c;
3700 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
3701
3702 if (!iommu)
3703 return -ENODEV;
3704
3705 table = get_irq_table(devid, false);
3706 if (!table)
3707 return -ENODEV;
3708
3709 spin_lock_irqsave(&table->lock, flags);
3710
3711 /* Scan table for free entries */
3712 for (c = 0, index = table->min_index;
3713 index < MAX_IRQS_PER_TABLE;
3714 ++index) {
3715 if (!iommu->irte_ops->is_allocated(table, index))
3716 c += 1;
3717 else
3718 c = 0;
3719
3720 if (c == count) {
3721 for (; c != 0; --c)
3722 iommu->irte_ops->set_allocated(table, index - c + 1);
3723
3724 index -= count - 1;
3725 goto out;
3726 }
3727 }
3728
3729 index = -ENOSPC;
3730
3731 out:
3732 spin_unlock_irqrestore(&table->lock, flags);
3733
3734 return index;
3735 }
3736
3737 static int modify_irte_ga(u16 devid, int index, struct irte_ga *irte,
3738 struct amd_ir_data *data)
3739 {
3740 struct irq_remap_table *table;
3741 struct amd_iommu *iommu;
3742 unsigned long flags;
3743 struct irte_ga *entry;
3744
3745 iommu = amd_iommu_rlookup_table[devid];
3746 if (iommu == NULL)
3747 return -EINVAL;
3748
3749 table = get_irq_table(devid, false);
3750 if (!table)
3751 return -ENOMEM;
3752
3753 spin_lock_irqsave(&table->lock, flags);
3754
3755 entry = (struct irte_ga *)table->table;
3756 entry = &entry[index];
3757 entry->lo.fields_remap.valid = 0;
3758 entry->hi.val = irte->hi.val;
3759 entry->lo.val = irte->lo.val;
3760 entry->lo.fields_remap.valid = 1;
3761 if (data)
3762 data->ref = entry;
3763
3764 spin_unlock_irqrestore(&table->lock, flags);
3765
3766 iommu_flush_irt(iommu, devid);
3767 iommu_completion_wait(iommu);
3768
3769 return 0;
3770 }
3771
3772 static int modify_irte(u16 devid, int index, union irte *irte)
3773 {
3774 struct irq_remap_table *table;
3775 struct amd_iommu *iommu;
3776 unsigned long flags;
3777
3778 iommu = amd_iommu_rlookup_table[devid];
3779 if (iommu == NULL)
3780 return -EINVAL;
3781
3782 table = get_irq_table(devid, false);
3783 if (!table)
3784 return -ENOMEM;
3785
3786 spin_lock_irqsave(&table->lock, flags);
3787 table->table[index] = irte->val;
3788 spin_unlock_irqrestore(&table->lock, flags);
3789
3790 iommu_flush_irt(iommu, devid);
3791 iommu_completion_wait(iommu);
3792
3793 return 0;
3794 }
3795
3796 static void free_irte(u16 devid, int index)
3797 {
3798 struct irq_remap_table *table;
3799 struct amd_iommu *iommu;
3800 unsigned long flags;
3801
3802 iommu = amd_iommu_rlookup_table[devid];
3803 if (iommu == NULL)
3804 return;
3805
3806 table = get_irq_table(devid, false);
3807 if (!table)
3808 return;
3809
3810 spin_lock_irqsave(&table->lock, flags);
3811 iommu->irte_ops->clear_allocated(table, index);
3812 spin_unlock_irqrestore(&table->lock, flags);
3813
3814 iommu_flush_irt(iommu, devid);
3815 iommu_completion_wait(iommu);
3816 }
3817
3818 static void irte_prepare(void *entry,
3819 u32 delivery_mode, u32 dest_mode,
3820 u8 vector, u32 dest_apicid, int devid)
3821 {
3822 union irte *irte = (union irte *) entry;
3823
3824 irte->val = 0;
3825 irte->fields.vector = vector;
3826 irte->fields.int_type = delivery_mode;
3827 irte->fields.destination = dest_apicid;
3828 irte->fields.dm = dest_mode;
3829 irte->fields.valid = 1;
3830 }
3831
3832 static void irte_ga_prepare(void *entry,
3833 u32 delivery_mode, u32 dest_mode,
3834 u8 vector, u32 dest_apicid, int devid)
3835 {
3836 struct irte_ga *irte = (struct irte_ga *) entry;
3837 struct iommu_dev_data *dev_data = search_dev_data(devid);
3838
3839 irte->lo.val = 0;
3840 irte->hi.val = 0;
3841 irte->lo.fields_remap.guest_mode = dev_data ? dev_data->use_vapic : 0;
3842 irte->lo.fields_remap.int_type = delivery_mode;
3843 irte->lo.fields_remap.dm = dest_mode;
3844 irte->hi.fields.vector = vector;
3845 irte->lo.fields_remap.destination = dest_apicid;
3846 irte->lo.fields_remap.valid = 1;
3847 }
3848
3849 static void irte_activate(void *entry, u16 devid, u16 index)
3850 {
3851 union irte *irte = (union irte *) entry;
3852
3853 irte->fields.valid = 1;
3854 modify_irte(devid, index, irte);
3855 }
3856
3857 static void irte_ga_activate(void *entry, u16 devid, u16 index)
3858 {
3859 struct irte_ga *irte = (struct irte_ga *) entry;
3860
3861 irte->lo.fields_remap.valid = 1;
3862 modify_irte_ga(devid, index, irte, NULL);
3863 }
3864
3865 static void irte_deactivate(void *entry, u16 devid, u16 index)
3866 {
3867 union irte *irte = (union irte *) entry;
3868
3869 irte->fields.valid = 0;
3870 modify_irte(devid, index, irte);
3871 }
3872
3873 static void irte_ga_deactivate(void *entry, u16 devid, u16 index)
3874 {
3875 struct irte_ga *irte = (struct irte_ga *) entry;
3876
3877 irte->lo.fields_remap.valid = 0;
3878 modify_irte_ga(devid, index, irte, NULL);
3879 }
3880
3881 static void irte_set_affinity(void *entry, u16 devid, u16 index,
3882 u8 vector, u32 dest_apicid)
3883 {
3884 union irte *irte = (union irte *) entry;
3885
3886 irte->fields.vector = vector;
3887 irte->fields.destination = dest_apicid;
3888 modify_irte(devid, index, irte);
3889 }
3890
3891 static void irte_ga_set_affinity(void *entry, u16 devid, u16 index,
3892 u8 vector, u32 dest_apicid)
3893 {
3894 struct irte_ga *irte = (struct irte_ga *) entry;
3895 struct iommu_dev_data *dev_data = search_dev_data(devid);
3896
3897 if (!dev_data || !dev_data->use_vapic) {
3898 irte->hi.fields.vector = vector;
3899 irte->lo.fields_remap.destination = dest_apicid;
3900 irte->lo.fields_remap.guest_mode = 0;
3901 modify_irte_ga(devid, index, irte, NULL);
3902 }
3903 }
3904
3905 #define IRTE_ALLOCATED (~1U)
3906 static void irte_set_allocated(struct irq_remap_table *table, int index)
3907 {
3908 table->table[index] = IRTE_ALLOCATED;
3909 }
3910
3911 static void irte_ga_set_allocated(struct irq_remap_table *table, int index)
3912 {
3913 struct irte_ga *ptr = (struct irte_ga *)table->table;
3914 struct irte_ga *irte = &ptr[index];
3915
3916 memset(&irte->lo.val, 0, sizeof(u64));
3917 memset(&irte->hi.val, 0, sizeof(u64));
3918 irte->hi.fields.vector = 0xff;
3919 }
3920
3921 static bool irte_is_allocated(struct irq_remap_table *table, int index)
3922 {
3923 union irte *ptr = (union irte *)table->table;
3924 union irte *irte = &ptr[index];
3925
3926 return irte->val != 0;
3927 }
3928
3929 static bool irte_ga_is_allocated(struct irq_remap_table *table, int index)
3930 {
3931 struct irte_ga *ptr = (struct irte_ga *)table->table;
3932 struct irte_ga *irte = &ptr[index];
3933
3934 return irte->hi.fields.vector != 0;
3935 }
3936
3937 static void irte_clear_allocated(struct irq_remap_table *table, int index)
3938 {
3939 table->table[index] = 0;
3940 }
3941
3942 static void irte_ga_clear_allocated(struct irq_remap_table *table, int index)
3943 {
3944 struct irte_ga *ptr = (struct irte_ga *)table->table;
3945 struct irte_ga *irte = &ptr[index];
3946
3947 memset(&irte->lo.val, 0, sizeof(u64));
3948 memset(&irte->hi.val, 0, sizeof(u64));
3949 }
3950
3951 static int get_devid(struct irq_alloc_info *info)
3952 {
3953 int devid = -1;
3954
3955 switch (info->type) {
3956 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3957 devid = get_ioapic_devid(info->ioapic_id);
3958 break;
3959 case X86_IRQ_ALLOC_TYPE_HPET:
3960 devid = get_hpet_devid(info->hpet_id);
3961 break;
3962 case X86_IRQ_ALLOC_TYPE_MSI:
3963 case X86_IRQ_ALLOC_TYPE_MSIX:
3964 devid = get_device_id(&info->msi_dev->dev);
3965 break;
3966 default:
3967 BUG_ON(1);
3968 break;
3969 }
3970
3971 return devid;
3972 }
3973
3974 static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
3975 {
3976 struct amd_iommu *iommu;
3977 int devid;
3978
3979 if (!info)
3980 return NULL;
3981
3982 devid = get_devid(info);
3983 if (devid >= 0) {
3984 iommu = amd_iommu_rlookup_table[devid];
3985 if (iommu)
3986 return iommu->ir_domain;
3987 }
3988
3989 return NULL;
3990 }
3991
3992 static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
3993 {
3994 struct amd_iommu *iommu;
3995 int devid;
3996
3997 if (!info)
3998 return NULL;
3999
4000 switch (info->type) {
4001 case X86_IRQ_ALLOC_TYPE_MSI:
4002 case X86_IRQ_ALLOC_TYPE_MSIX:
4003 devid = get_device_id(&info->msi_dev->dev);
4004 if (devid < 0)
4005 return NULL;
4006
4007 iommu = amd_iommu_rlookup_table[devid];
4008 if (iommu)
4009 return iommu->msi_domain;
4010 break;
4011 default:
4012 break;
4013 }
4014
4015 return NULL;
4016 }
4017
4018 struct irq_remap_ops amd_iommu_irq_ops = {
4019 .prepare = amd_iommu_prepare,
4020 .enable = amd_iommu_enable,
4021 .disable = amd_iommu_disable,
4022 .reenable = amd_iommu_reenable,
4023 .enable_faulting = amd_iommu_enable_faulting,
4024 .get_ir_irq_domain = get_ir_irq_domain,
4025 .get_irq_domain = get_irq_domain,
4026 };
4027
4028 static void irq_remapping_prepare_irte(struct amd_ir_data *data,
4029 struct irq_cfg *irq_cfg,
4030 struct irq_alloc_info *info,
4031 int devid, int index, int sub_handle)
4032 {
4033 struct irq_2_irte *irte_info = &data->irq_2_irte;
4034 struct msi_msg *msg = &data->msi_entry;
4035 struct IO_APIC_route_entry *entry;
4036 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
4037
4038 if (!iommu)
4039 return;
4040
4041 data->irq_2_irte.devid = devid;
4042 data->irq_2_irte.index = index + sub_handle;
4043 iommu->irte_ops->prepare(data->entry, apic->irq_delivery_mode,
4044 apic->irq_dest_mode, irq_cfg->vector,
4045 irq_cfg->dest_apicid, devid);
4046
4047 switch (info->type) {
4048 case X86_IRQ_ALLOC_TYPE_IOAPIC:
4049 /* Setup IOAPIC entry */
4050 entry = info->ioapic_entry;
4051 info->ioapic_entry = NULL;
4052 memset(entry, 0, sizeof(*entry));
4053 entry->vector = index;
4054 entry->mask = 0;
4055 entry->trigger = info->ioapic_trigger;
4056 entry->polarity = info->ioapic_polarity;
4057 /* Mask level triggered irqs. */
4058 if (info->ioapic_trigger)
4059 entry->mask = 1;
4060 break;
4061
4062 case X86_IRQ_ALLOC_TYPE_HPET:
4063 case X86_IRQ_ALLOC_TYPE_MSI:
4064 case X86_IRQ_ALLOC_TYPE_MSIX:
4065 msg->address_hi = MSI_ADDR_BASE_HI;
4066 msg->address_lo = MSI_ADDR_BASE_LO;
4067 msg->data = irte_info->index;
4068 break;
4069
4070 default:
4071 BUG_ON(1);
4072 break;
4073 }
4074 }
4075
4076 struct amd_irte_ops irte_32_ops = {
4077 .prepare = irte_prepare,
4078 .activate = irte_activate,
4079 .deactivate = irte_deactivate,
4080 .set_affinity = irte_set_affinity,
4081 .set_allocated = irte_set_allocated,
4082 .is_allocated = irte_is_allocated,
4083 .clear_allocated = irte_clear_allocated,
4084 };
4085
4086 struct amd_irte_ops irte_128_ops = {
4087 .prepare = irte_ga_prepare,
4088 .activate = irte_ga_activate,
4089 .deactivate = irte_ga_deactivate,
4090 .set_affinity = irte_ga_set_affinity,
4091 .set_allocated = irte_ga_set_allocated,
4092 .is_allocated = irte_ga_is_allocated,
4093 .clear_allocated = irte_ga_clear_allocated,
4094 };
4095
4096 static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
4097 unsigned int nr_irqs, void *arg)
4098 {
4099 struct irq_alloc_info *info = arg;
4100 struct irq_data *irq_data;
4101 struct amd_ir_data *data = NULL;
4102 struct irq_cfg *cfg;
4103 int i, ret, devid;
4104 int index = -1;
4105
4106 if (!info)
4107 return -EINVAL;
4108 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
4109 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
4110 return -EINVAL;
4111
4112 /*
4113 * With IRQ remapping enabled, don't need contiguous CPU vectors
4114 * to support multiple MSI interrupts.
4115 */
4116 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
4117 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
4118
4119 devid = get_devid(info);
4120 if (devid < 0)
4121 return -EINVAL;
4122
4123 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
4124 if (ret < 0)
4125 return ret;
4126
4127 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
4128 if (get_irq_table(devid, true))
4129 index = info->ioapic_pin;
4130 else
4131 ret = -ENOMEM;
4132 } else {
4133 index = alloc_irq_index(devid, nr_irqs);
4134 }
4135 if (index < 0) {
4136 pr_warn("Failed to allocate IRTE\n");
4137 goto out_free_parent;
4138 }
4139
4140 for (i = 0; i < nr_irqs; i++) {
4141 irq_data = irq_domain_get_irq_data(domain, virq + i);
4142 cfg = irqd_cfg(irq_data);
4143 if (!irq_data || !cfg) {
4144 ret = -EINVAL;
4145 goto out_free_data;
4146 }
4147
4148 ret = -ENOMEM;
4149 data = kzalloc(sizeof(*data), GFP_KERNEL);
4150 if (!data)
4151 goto out_free_data;
4152
4153 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
4154 data->entry = kzalloc(sizeof(union irte), GFP_KERNEL);
4155 else
4156 data->entry = kzalloc(sizeof(struct irte_ga),
4157 GFP_KERNEL);
4158 if (!data->entry) {
4159 kfree(data);
4160 goto out_free_data;
4161 }
4162
4163 irq_data->hwirq = (devid << 16) + i;
4164 irq_data->chip_data = data;
4165 irq_data->chip = &amd_ir_chip;
4166 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
4167 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
4168 }
4169
4170 return 0;
4171
4172 out_free_data:
4173 for (i--; i >= 0; i--) {
4174 irq_data = irq_domain_get_irq_data(domain, virq + i);
4175 if (irq_data)
4176 kfree(irq_data->chip_data);
4177 }
4178 for (i = 0; i < nr_irqs; i++)
4179 free_irte(devid, index + i);
4180 out_free_parent:
4181 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4182 return ret;
4183 }
4184
4185 static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
4186 unsigned int nr_irqs)
4187 {
4188 struct irq_2_irte *irte_info;
4189 struct irq_data *irq_data;
4190 struct amd_ir_data *data;
4191 int i;
4192
4193 for (i = 0; i < nr_irqs; i++) {
4194 irq_data = irq_domain_get_irq_data(domain, virq + i);
4195 if (irq_data && irq_data->chip_data) {
4196 data = irq_data->chip_data;
4197 irte_info = &data->irq_2_irte;
4198 free_irte(irte_info->devid, irte_info->index);
4199 kfree(data->entry);
4200 kfree(data);
4201 }
4202 }
4203 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4204 }
4205
4206 static void irq_remapping_activate(struct irq_domain *domain,
4207 struct irq_data *irq_data)
4208 {
4209 struct amd_ir_data *data = irq_data->chip_data;
4210 struct irq_2_irte *irte_info = &data->irq_2_irte;
4211 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4212
4213 if (iommu)
4214 iommu->irte_ops->activate(data->entry, irte_info->devid,
4215 irte_info->index);
4216 }
4217
4218 static void irq_remapping_deactivate(struct irq_domain *domain,
4219 struct irq_data *irq_data)
4220 {
4221 struct amd_ir_data *data = irq_data->chip_data;
4222 struct irq_2_irte *irte_info = &data->irq_2_irte;
4223 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4224
4225 if (iommu)
4226 iommu->irte_ops->deactivate(data->entry, irte_info->devid,
4227 irte_info->index);
4228 }
4229
4230 static struct irq_domain_ops amd_ir_domain_ops = {
4231 .alloc = irq_remapping_alloc,
4232 .free = irq_remapping_free,
4233 .activate = irq_remapping_activate,
4234 .deactivate = irq_remapping_deactivate,
4235 };
4236
4237 static int amd_ir_set_vcpu_affinity(struct irq_data *data, void *vcpu_info)
4238 {
4239 struct amd_iommu *iommu;
4240 struct amd_iommu_pi_data *pi_data = vcpu_info;
4241 struct vcpu_data *vcpu_pi_info = pi_data->vcpu_data;
4242 struct amd_ir_data *ir_data = data->chip_data;
4243 struct irte_ga *irte = (struct irte_ga *) ir_data->entry;
4244 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4245 struct iommu_dev_data *dev_data = search_dev_data(irte_info->devid);
4246
4247 /* Note:
4248 * This device has never been set up for guest mode.
4249 * we should not modify the IRTE
4250 */
4251 if (!dev_data || !dev_data->use_vapic)
4252 return 0;
4253
4254 pi_data->ir_data = ir_data;
4255
4256 /* Note:
4257 * SVM tries to set up for VAPIC mode, but we are in
4258 * legacy mode. So, we force legacy mode instead.
4259 */
4260 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir)) {
4261 pr_debug("AMD-Vi: %s: Fall back to using intr legacy remap\n",
4262 __func__);
4263 pi_data->is_guest_mode = false;
4264 }
4265
4266 iommu = amd_iommu_rlookup_table[irte_info->devid];
4267 if (iommu == NULL)
4268 return -EINVAL;
4269
4270 pi_data->prev_ga_tag = ir_data->cached_ga_tag;
4271 if (pi_data->is_guest_mode) {
4272 /* Setting */
4273 irte->hi.fields.ga_root_ptr = (pi_data->base >> 12);
4274 irte->hi.fields.vector = vcpu_pi_info->vector;
4275 irte->lo.fields_vapic.guest_mode = 1;
4276 irte->lo.fields_vapic.ga_tag = pi_data->ga_tag;
4277
4278 ir_data->cached_ga_tag = pi_data->ga_tag;
4279 } else {
4280 /* Un-Setting */
4281 struct irq_cfg *cfg = irqd_cfg(data);
4282
4283 irte->hi.val = 0;
4284 irte->lo.val = 0;
4285 irte->hi.fields.vector = cfg->vector;
4286 irte->lo.fields_remap.guest_mode = 0;
4287 irte->lo.fields_remap.destination = cfg->dest_apicid;
4288 irte->lo.fields_remap.int_type = apic->irq_delivery_mode;
4289 irte->lo.fields_remap.dm = apic->irq_dest_mode;
4290
4291 /*
4292 * This communicates the ga_tag back to the caller
4293 * so that it can do all the necessary clean up.
4294 */
4295 ir_data->cached_ga_tag = 0;
4296 }
4297
4298 return modify_irte_ga(irte_info->devid, irte_info->index, irte, ir_data);
4299 }
4300
4301 static int amd_ir_set_affinity(struct irq_data *data,
4302 const struct cpumask *mask, bool force)
4303 {
4304 struct amd_ir_data *ir_data = data->chip_data;
4305 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4306 struct irq_cfg *cfg = irqd_cfg(data);
4307 struct irq_data *parent = data->parent_data;
4308 struct amd_iommu *iommu = amd_iommu_rlookup_table[irte_info->devid];
4309 int ret;
4310
4311 if (!iommu)
4312 return -ENODEV;
4313
4314 ret = parent->chip->irq_set_affinity(parent, mask, force);
4315 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4316 return ret;
4317
4318 /*
4319 * Atomically updates the IRTE with the new destination, vector
4320 * and flushes the interrupt entry cache.
4321 */
4322 iommu->irte_ops->set_affinity(ir_data->entry, irte_info->devid,
4323 irte_info->index, cfg->vector, cfg->dest_apicid);
4324
4325 /*
4326 * After this point, all the interrupts will start arriving
4327 * at the new destination. So, time to cleanup the previous
4328 * vector allocation.
4329 */
4330 send_cleanup_vector(cfg);
4331
4332 return IRQ_SET_MASK_OK_DONE;
4333 }
4334
4335 static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4336 {
4337 struct amd_ir_data *ir_data = irq_data->chip_data;
4338
4339 *msg = ir_data->msi_entry;
4340 }
4341
4342 static struct irq_chip amd_ir_chip = {
4343 .irq_ack = ir_ack_apic_edge,
4344 .irq_set_affinity = amd_ir_set_affinity,
4345 .irq_set_vcpu_affinity = amd_ir_set_vcpu_affinity,
4346 .irq_compose_msi_msg = ir_compose_msi_msg,
4347 };
4348
4349 int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4350 {
4351 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4352 if (!iommu->ir_domain)
4353 return -ENOMEM;
4354
4355 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4356 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4357
4358 return 0;
4359 }
4360
4361 int amd_iommu_update_ga(int cpu, bool is_run, void *data)
4362 {
4363 unsigned long flags;
4364 struct amd_iommu *iommu;
4365 struct irq_remap_table *irt;
4366 struct amd_ir_data *ir_data = (struct amd_ir_data *)data;
4367 int devid = ir_data->irq_2_irte.devid;
4368 struct irte_ga *entry = (struct irte_ga *) ir_data->entry;
4369 struct irte_ga *ref = (struct irte_ga *) ir_data->ref;
4370
4371 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) ||
4372 !ref || !entry || !entry->lo.fields_vapic.guest_mode)
4373 return 0;
4374
4375 iommu = amd_iommu_rlookup_table[devid];
4376 if (!iommu)
4377 return -ENODEV;
4378
4379 irt = get_irq_table(devid, false);
4380 if (!irt)
4381 return -ENODEV;
4382
4383 spin_lock_irqsave(&irt->lock, flags);
4384
4385 if (ref->lo.fields_vapic.guest_mode) {
4386 if (cpu >= 0)
4387 ref->lo.fields_vapic.destination = cpu;
4388 ref->lo.fields_vapic.is_run = is_run;
4389 barrier();
4390 }
4391
4392 spin_unlock_irqrestore(&irt->lock, flags);
4393
4394 iommu_flush_irt(iommu, devid);
4395 iommu_completion_wait(iommu);
4396 return 0;
4397 }
4398 EXPORT_SYMBOL(amd_iommu_update_ga);
4399 #endif
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