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iommu/amd: Handle integer overflow in dma_ops_area_alloc
[mirror_ubuntu-bionic-kernel.git] / drivers / iommu / amd_iommu.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/ratelimit.h>
21 #include <linux/pci.h>
22 #include <linux/pci-ats.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/debugfs.h>
26 #include <linux/scatterlist.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/iommu-helper.h>
29 #include <linux/iommu.h>
30 #include <linux/delay.h>
31 #include <linux/amd-iommu.h>
32 #include <linux/notifier.h>
33 #include <linux/export.h>
34 #include <linux/irq.h>
35 #include <linux/msi.h>
36 #include <linux/dma-contiguous.h>
37 #include <asm/irq_remapping.h>
38 #include <asm/io_apic.h>
39 #include <asm/apic.h>
40 #include <asm/hw_irq.h>
41 #include <asm/msidef.h>
42 #include <asm/proto.h>
43 #include <asm/iommu.h>
44 #include <asm/gart.h>
45 #include <asm/dma.h>
46
47 #include "amd_iommu_proto.h"
48 #include "amd_iommu_types.h"
49 #include "irq_remapping.h"
50
51 #define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
52
53 #define LOOP_TIMEOUT 100000
54
55 /*
56 * This bitmap is used to advertise the page sizes our hardware support
57 * to the IOMMU core, which will then use this information to split
58 * physically contiguous memory regions it is mapping into page sizes
59 * that we support.
60 *
61 * 512GB Pages are not supported due to a hardware bug
62 */
63 #define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
64
65 static DEFINE_RWLOCK(amd_iommu_devtable_lock);
66
67 /* A list of preallocated protection domains */
68 static LIST_HEAD(iommu_pd_list);
69 static DEFINE_SPINLOCK(iommu_pd_list_lock);
70
71 /* List of all available dev_data structures */
72 static LIST_HEAD(dev_data_list);
73 static DEFINE_SPINLOCK(dev_data_list_lock);
74
75 LIST_HEAD(ioapic_map);
76 LIST_HEAD(hpet_map);
77
78 /*
79 * Domain for untranslated devices - only allocated
80 * if iommu=pt passed on kernel cmd line.
81 */
82 static struct protection_domain *pt_domain;
83
84 static const struct iommu_ops amd_iommu_ops;
85
86 static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
87 int amd_iommu_max_glx_val = -1;
88
89 static struct dma_map_ops amd_iommu_dma_ops;
90
91 /*
92 * This struct contains device specific data for the IOMMU
93 */
94 struct iommu_dev_data {
95 struct list_head list; /* For domain->dev_list */
96 struct list_head dev_data_list; /* For global dev_data_list */
97 struct list_head alias_list; /* Link alias-groups together */
98 struct iommu_dev_data *alias_data;/* The alias dev_data */
99 struct protection_domain *domain; /* Domain the device is bound to */
100 u16 devid; /* PCI Device ID */
101 bool iommu_v2; /* Device can make use of IOMMUv2 */
102 bool passthrough; /* Default for device is pt_domain */
103 struct {
104 bool enabled;
105 int qdep;
106 } ats; /* ATS state */
107 bool pri_tlp; /* PASID TLB required for
108 PPR completions */
109 u32 errata; /* Bitmap for errata to apply */
110 };
111
112 /*
113 * general struct to manage commands send to an IOMMU
114 */
115 struct iommu_cmd {
116 u32 data[4];
117 };
118
119 struct kmem_cache *amd_iommu_irq_cache;
120
121 static void update_domain(struct protection_domain *domain);
122 static int __init alloc_passthrough_domain(void);
123
124 /****************************************************************************
125 *
126 * Helper functions
127 *
128 ****************************************************************************/
129
130 static struct iommu_dev_data *alloc_dev_data(u16 devid)
131 {
132 struct iommu_dev_data *dev_data;
133 unsigned long flags;
134
135 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
136 if (!dev_data)
137 return NULL;
138
139 INIT_LIST_HEAD(&dev_data->alias_list);
140
141 dev_data->devid = devid;
142
143 spin_lock_irqsave(&dev_data_list_lock, flags);
144 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
145 spin_unlock_irqrestore(&dev_data_list_lock, flags);
146
147 return dev_data;
148 }
149
150 static void free_dev_data(struct iommu_dev_data *dev_data)
151 {
152 unsigned long flags;
153
154 spin_lock_irqsave(&dev_data_list_lock, flags);
155 list_del(&dev_data->dev_data_list);
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 kfree(dev_data);
159 }
160
161 static struct iommu_dev_data *search_dev_data(u16 devid)
162 {
163 struct iommu_dev_data *dev_data;
164 unsigned long flags;
165
166 spin_lock_irqsave(&dev_data_list_lock, flags);
167 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
168 if (dev_data->devid == devid)
169 goto out_unlock;
170 }
171
172 dev_data = NULL;
173
174 out_unlock:
175 spin_unlock_irqrestore(&dev_data_list_lock, flags);
176
177 return dev_data;
178 }
179
180 static struct iommu_dev_data *find_dev_data(u16 devid)
181 {
182 struct iommu_dev_data *dev_data;
183
184 dev_data = search_dev_data(devid);
185
186 if (dev_data == NULL)
187 dev_data = alloc_dev_data(devid);
188
189 return dev_data;
190 }
191
192 static inline u16 get_device_id(struct device *dev)
193 {
194 struct pci_dev *pdev = to_pci_dev(dev);
195
196 return PCI_DEVID(pdev->bus->number, pdev->devfn);
197 }
198
199 static struct iommu_dev_data *get_dev_data(struct device *dev)
200 {
201 return dev->archdata.iommu;
202 }
203
204 static bool pci_iommuv2_capable(struct pci_dev *pdev)
205 {
206 static const int caps[] = {
207 PCI_EXT_CAP_ID_ATS,
208 PCI_EXT_CAP_ID_PRI,
209 PCI_EXT_CAP_ID_PASID,
210 };
211 int i, pos;
212
213 for (i = 0; i < 3; ++i) {
214 pos = pci_find_ext_capability(pdev, caps[i]);
215 if (pos == 0)
216 return false;
217 }
218
219 return true;
220 }
221
222 static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
223 {
224 struct iommu_dev_data *dev_data;
225
226 dev_data = get_dev_data(&pdev->dev);
227
228 return dev_data->errata & (1 << erratum) ? true : false;
229 }
230
231 /*
232 * In this function the list of preallocated protection domains is traversed to
233 * find the domain for a specific device
234 */
235 static struct dma_ops_domain *find_protection_domain(u16 devid)
236 {
237 struct dma_ops_domain *entry, *ret = NULL;
238 unsigned long flags;
239 u16 alias = amd_iommu_alias_table[devid];
240
241 if (list_empty(&iommu_pd_list))
242 return NULL;
243
244 spin_lock_irqsave(&iommu_pd_list_lock, flags);
245
246 list_for_each_entry(entry, &iommu_pd_list, list) {
247 if (entry->target_dev == devid ||
248 entry->target_dev == alias) {
249 ret = entry;
250 break;
251 }
252 }
253
254 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
255
256 return ret;
257 }
258
259 /*
260 * This function checks if the driver got a valid device from the caller to
261 * avoid dereferencing invalid pointers.
262 */
263 static bool check_device(struct device *dev)
264 {
265 u16 devid;
266
267 if (!dev || !dev->dma_mask)
268 return false;
269
270 /* No PCI device */
271 if (!dev_is_pci(dev))
272 return false;
273
274 devid = get_device_id(dev);
275
276 /* Out of our scope? */
277 if (devid > amd_iommu_last_bdf)
278 return false;
279
280 if (amd_iommu_rlookup_table[devid] == NULL)
281 return false;
282
283 return true;
284 }
285
286 static void init_iommu_group(struct device *dev)
287 {
288 struct iommu_group *group;
289
290 group = iommu_group_get_for_dev(dev);
291 if (!IS_ERR(group))
292 iommu_group_put(group);
293 }
294
295 static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
296 {
297 *(u16 *)data = alias;
298 return 0;
299 }
300
301 static u16 get_alias(struct device *dev)
302 {
303 struct pci_dev *pdev = to_pci_dev(dev);
304 u16 devid, ivrs_alias, pci_alias;
305
306 devid = get_device_id(dev);
307 ivrs_alias = amd_iommu_alias_table[devid];
308 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
309
310 if (ivrs_alias == pci_alias)
311 return ivrs_alias;
312
313 /*
314 * DMA alias showdown
315 *
316 * The IVRS is fairly reliable in telling us about aliases, but it
317 * can't know about every screwy device. If we don't have an IVRS
318 * reported alias, use the PCI reported alias. In that case we may
319 * still need to initialize the rlookup and dev_table entries if the
320 * alias is to a non-existent device.
321 */
322 if (ivrs_alias == devid) {
323 if (!amd_iommu_rlookup_table[pci_alias]) {
324 amd_iommu_rlookup_table[pci_alias] =
325 amd_iommu_rlookup_table[devid];
326 memcpy(amd_iommu_dev_table[pci_alias].data,
327 amd_iommu_dev_table[devid].data,
328 sizeof(amd_iommu_dev_table[pci_alias].data));
329 }
330
331 return pci_alias;
332 }
333
334 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
335 "for device %s[%04x:%04x], kernel reported alias "
336 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
337 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
338 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
339 PCI_FUNC(pci_alias));
340
341 /*
342 * If we don't have a PCI DMA alias and the IVRS alias is on the same
343 * bus, then the IVRS table may know about a quirk that we don't.
344 */
345 if (pci_alias == devid &&
346 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
347 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
348 pdev->dma_alias_devfn = ivrs_alias & 0xff;
349 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
350 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
351 dev_name(dev));
352 }
353
354 return ivrs_alias;
355 }
356
357 static int iommu_init_device(struct device *dev)
358 {
359 struct pci_dev *pdev = to_pci_dev(dev);
360 struct iommu_dev_data *dev_data;
361 u16 alias;
362
363 if (dev->archdata.iommu)
364 return 0;
365
366 dev_data = find_dev_data(get_device_id(dev));
367 if (!dev_data)
368 return -ENOMEM;
369
370 alias = get_alias(dev);
371
372 if (alias != dev_data->devid) {
373 struct iommu_dev_data *alias_data;
374
375 alias_data = find_dev_data(alias);
376 if (alias_data == NULL) {
377 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
378 dev_name(dev));
379 free_dev_data(dev_data);
380 return -ENOTSUPP;
381 }
382 dev_data->alias_data = alias_data;
383
384 /* Add device to the alias_list */
385 list_add(&dev_data->alias_list, &alias_data->alias_list);
386 }
387
388 if (pci_iommuv2_capable(pdev)) {
389 struct amd_iommu *iommu;
390
391 iommu = amd_iommu_rlookup_table[dev_data->devid];
392 dev_data->iommu_v2 = iommu->is_iommu_v2;
393 }
394
395 dev->archdata.iommu = dev_data;
396
397 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
398 dev);
399
400 return 0;
401 }
402
403 static void iommu_ignore_device(struct device *dev)
404 {
405 u16 devid, alias;
406
407 devid = get_device_id(dev);
408 alias = amd_iommu_alias_table[devid];
409
410 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
411 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
412
413 amd_iommu_rlookup_table[devid] = NULL;
414 amd_iommu_rlookup_table[alias] = NULL;
415 }
416
417 static void iommu_uninit_device(struct device *dev)
418 {
419 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
420
421 if (!dev_data)
422 return;
423
424 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
425 dev);
426
427 iommu_group_remove_device(dev);
428
429 /* Unlink from alias, it may change if another device is re-plugged */
430 dev_data->alias_data = NULL;
431
432 /*
433 * We keep dev_data around for unplugged devices and reuse it when the
434 * device is re-plugged - not doing so would introduce a ton of races.
435 */
436 }
437
438 void __init amd_iommu_uninit_devices(void)
439 {
440 struct iommu_dev_data *dev_data, *n;
441 struct pci_dev *pdev = NULL;
442
443 for_each_pci_dev(pdev) {
444
445 if (!check_device(&pdev->dev))
446 continue;
447
448 iommu_uninit_device(&pdev->dev);
449 }
450
451 /* Free all of our dev_data structures */
452 list_for_each_entry_safe(dev_data, n, &dev_data_list, dev_data_list)
453 free_dev_data(dev_data);
454 }
455
456 int __init amd_iommu_init_devices(void)
457 {
458 struct pci_dev *pdev = NULL;
459 int ret = 0;
460
461 for_each_pci_dev(pdev) {
462
463 if (!check_device(&pdev->dev))
464 continue;
465
466 ret = iommu_init_device(&pdev->dev);
467 if (ret == -ENOTSUPP)
468 iommu_ignore_device(&pdev->dev);
469 else if (ret)
470 goto out_free;
471 }
472
473 /*
474 * Initialize IOMMU groups only after iommu_init_device() has
475 * had a chance to populate any IVRS defined aliases.
476 */
477 for_each_pci_dev(pdev) {
478 if (check_device(&pdev->dev))
479 init_iommu_group(&pdev->dev);
480 }
481
482 return 0;
483
484 out_free:
485
486 amd_iommu_uninit_devices();
487
488 return ret;
489 }
490 #ifdef CONFIG_AMD_IOMMU_STATS
491
492 /*
493 * Initialization code for statistics collection
494 */
495
496 DECLARE_STATS_COUNTER(compl_wait);
497 DECLARE_STATS_COUNTER(cnt_map_single);
498 DECLARE_STATS_COUNTER(cnt_unmap_single);
499 DECLARE_STATS_COUNTER(cnt_map_sg);
500 DECLARE_STATS_COUNTER(cnt_unmap_sg);
501 DECLARE_STATS_COUNTER(cnt_alloc_coherent);
502 DECLARE_STATS_COUNTER(cnt_free_coherent);
503 DECLARE_STATS_COUNTER(cross_page);
504 DECLARE_STATS_COUNTER(domain_flush_single);
505 DECLARE_STATS_COUNTER(domain_flush_all);
506 DECLARE_STATS_COUNTER(alloced_io_mem);
507 DECLARE_STATS_COUNTER(total_map_requests);
508 DECLARE_STATS_COUNTER(complete_ppr);
509 DECLARE_STATS_COUNTER(invalidate_iotlb);
510 DECLARE_STATS_COUNTER(invalidate_iotlb_all);
511 DECLARE_STATS_COUNTER(pri_requests);
512
513 static struct dentry *stats_dir;
514 static struct dentry *de_fflush;
515
516 static void amd_iommu_stats_add(struct __iommu_counter *cnt)
517 {
518 if (stats_dir == NULL)
519 return;
520
521 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
522 &cnt->value);
523 }
524
525 static void amd_iommu_stats_init(void)
526 {
527 stats_dir = debugfs_create_dir("amd-iommu", NULL);
528 if (stats_dir == NULL)
529 return;
530
531 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
532 &amd_iommu_unmap_flush);
533
534 amd_iommu_stats_add(&compl_wait);
535 amd_iommu_stats_add(&cnt_map_single);
536 amd_iommu_stats_add(&cnt_unmap_single);
537 amd_iommu_stats_add(&cnt_map_sg);
538 amd_iommu_stats_add(&cnt_unmap_sg);
539 amd_iommu_stats_add(&cnt_alloc_coherent);
540 amd_iommu_stats_add(&cnt_free_coherent);
541 amd_iommu_stats_add(&cross_page);
542 amd_iommu_stats_add(&domain_flush_single);
543 amd_iommu_stats_add(&domain_flush_all);
544 amd_iommu_stats_add(&alloced_io_mem);
545 amd_iommu_stats_add(&total_map_requests);
546 amd_iommu_stats_add(&complete_ppr);
547 amd_iommu_stats_add(&invalidate_iotlb);
548 amd_iommu_stats_add(&invalidate_iotlb_all);
549 amd_iommu_stats_add(&pri_requests);
550 }
551
552 #endif
553
554 /****************************************************************************
555 *
556 * Interrupt handling functions
557 *
558 ****************************************************************************/
559
560 static void dump_dte_entry(u16 devid)
561 {
562 int i;
563
564 for (i = 0; i < 4; ++i)
565 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
566 amd_iommu_dev_table[devid].data[i]);
567 }
568
569 static void dump_command(unsigned long phys_addr)
570 {
571 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
572 int i;
573
574 for (i = 0; i < 4; ++i)
575 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
576 }
577
578 static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
579 {
580 int type, devid, domid, flags;
581 volatile u32 *event = __evt;
582 int count = 0;
583 u64 address;
584
585 retry:
586 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
587 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
588 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
589 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
590 address = (u64)(((u64)event[3]) << 32) | event[2];
591
592 if (type == 0) {
593 /* Did we hit the erratum? */
594 if (++count == LOOP_TIMEOUT) {
595 pr_err("AMD-Vi: No event written to event log\n");
596 return;
597 }
598 udelay(1);
599 goto retry;
600 }
601
602 printk(KERN_ERR "AMD-Vi: Event logged [");
603
604 switch (type) {
605 case EVENT_TYPE_ILL_DEV:
606 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
607 "address=0x%016llx flags=0x%04x]\n",
608 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
609 address, flags);
610 dump_dte_entry(devid);
611 break;
612 case EVENT_TYPE_IO_FAULT:
613 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
614 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
615 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
616 domid, address, flags);
617 break;
618 case EVENT_TYPE_DEV_TAB_ERR:
619 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
620 "address=0x%016llx flags=0x%04x]\n",
621 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
622 address, flags);
623 break;
624 case EVENT_TYPE_PAGE_TAB_ERR:
625 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
626 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
627 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
628 domid, address, flags);
629 break;
630 case EVENT_TYPE_ILL_CMD:
631 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
632 dump_command(address);
633 break;
634 case EVENT_TYPE_CMD_HARD_ERR:
635 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
636 "flags=0x%04x]\n", address, flags);
637 break;
638 case EVENT_TYPE_IOTLB_INV_TO:
639 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
640 "address=0x%016llx]\n",
641 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
642 address);
643 break;
644 case EVENT_TYPE_INV_DEV_REQ:
645 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
646 "address=0x%016llx flags=0x%04x]\n",
647 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
648 address, flags);
649 break;
650 default:
651 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
652 }
653
654 memset(__evt, 0, 4 * sizeof(u32));
655 }
656
657 static void iommu_poll_events(struct amd_iommu *iommu)
658 {
659 u32 head, tail;
660
661 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
662 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
663
664 while (head != tail) {
665 iommu_print_event(iommu, iommu->evt_buf + head);
666 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
667 }
668
669 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
670 }
671
672 static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
673 {
674 struct amd_iommu_fault fault;
675
676 INC_STATS_COUNTER(pri_requests);
677
678 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
679 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
680 return;
681 }
682
683 fault.address = raw[1];
684 fault.pasid = PPR_PASID(raw[0]);
685 fault.device_id = PPR_DEVID(raw[0]);
686 fault.tag = PPR_TAG(raw[0]);
687 fault.flags = PPR_FLAGS(raw[0]);
688
689 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
690 }
691
692 static void iommu_poll_ppr_log(struct amd_iommu *iommu)
693 {
694 u32 head, tail;
695
696 if (iommu->ppr_log == NULL)
697 return;
698
699 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
700 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
701
702 while (head != tail) {
703 volatile u64 *raw;
704 u64 entry[2];
705 int i;
706
707 raw = (u64 *)(iommu->ppr_log + head);
708
709 /*
710 * Hardware bug: Interrupt may arrive before the entry is
711 * written to memory. If this happens we need to wait for the
712 * entry to arrive.
713 */
714 for (i = 0; i < LOOP_TIMEOUT; ++i) {
715 if (PPR_REQ_TYPE(raw[0]) != 0)
716 break;
717 udelay(1);
718 }
719
720 /* Avoid memcpy function-call overhead */
721 entry[0] = raw[0];
722 entry[1] = raw[1];
723
724 /*
725 * To detect the hardware bug we need to clear the entry
726 * back to zero.
727 */
728 raw[0] = raw[1] = 0UL;
729
730 /* Update head pointer of hardware ring-buffer */
731 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
732 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
733
734 /* Handle PPR entry */
735 iommu_handle_ppr_entry(iommu, entry);
736
737 /* Refresh ring-buffer information */
738 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
739 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
740 }
741 }
742
743 irqreturn_t amd_iommu_int_thread(int irq, void *data)
744 {
745 struct amd_iommu *iommu = (struct amd_iommu *) data;
746 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
747
748 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
749 /* Enable EVT and PPR interrupts again */
750 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
751 iommu->mmio_base + MMIO_STATUS_OFFSET);
752
753 if (status & MMIO_STATUS_EVT_INT_MASK) {
754 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
755 iommu_poll_events(iommu);
756 }
757
758 if (status & MMIO_STATUS_PPR_INT_MASK) {
759 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
760 iommu_poll_ppr_log(iommu);
761 }
762
763 /*
764 * Hardware bug: ERBT1312
765 * When re-enabling interrupt (by writing 1
766 * to clear the bit), the hardware might also try to set
767 * the interrupt bit in the event status register.
768 * In this scenario, the bit will be set, and disable
769 * subsequent interrupts.
770 *
771 * Workaround: The IOMMU driver should read back the
772 * status register and check if the interrupt bits are cleared.
773 * If not, driver will need to go through the interrupt handler
774 * again and re-clear the bits
775 */
776 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
777 }
778 return IRQ_HANDLED;
779 }
780
781 irqreturn_t amd_iommu_int_handler(int irq, void *data)
782 {
783 return IRQ_WAKE_THREAD;
784 }
785
786 /****************************************************************************
787 *
788 * IOMMU command queuing functions
789 *
790 ****************************************************************************/
791
792 static int wait_on_sem(volatile u64 *sem)
793 {
794 int i = 0;
795
796 while (*sem == 0 && i < LOOP_TIMEOUT) {
797 udelay(1);
798 i += 1;
799 }
800
801 if (i == LOOP_TIMEOUT) {
802 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
803 return -EIO;
804 }
805
806 return 0;
807 }
808
809 static void copy_cmd_to_buffer(struct amd_iommu *iommu,
810 struct iommu_cmd *cmd,
811 u32 tail)
812 {
813 u8 *target;
814
815 target = iommu->cmd_buf + tail;
816 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
817
818 /* Copy command to buffer */
819 memcpy(target, cmd, sizeof(*cmd));
820
821 /* Tell the IOMMU about it */
822 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
823 }
824
825 static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
826 {
827 WARN_ON(address & 0x7ULL);
828
829 memset(cmd, 0, sizeof(*cmd));
830 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
831 cmd->data[1] = upper_32_bits(__pa(address));
832 cmd->data[2] = 1;
833 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
834 }
835
836 static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
837 {
838 memset(cmd, 0, sizeof(*cmd));
839 cmd->data[0] = devid;
840 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
841 }
842
843 static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
844 size_t size, u16 domid, int pde)
845 {
846 u64 pages;
847 bool s;
848
849 pages = iommu_num_pages(address, size, PAGE_SIZE);
850 s = false;
851
852 if (pages > 1) {
853 /*
854 * If we have to flush more than one page, flush all
855 * TLB entries for this domain
856 */
857 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
858 s = true;
859 }
860
861 address &= PAGE_MASK;
862
863 memset(cmd, 0, sizeof(*cmd));
864 cmd->data[1] |= domid;
865 cmd->data[2] = lower_32_bits(address);
866 cmd->data[3] = upper_32_bits(address);
867 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
868 if (s) /* size bit - we flush more than one 4kb page */
869 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
870 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
871 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
872 }
873
874 static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
875 u64 address, size_t size)
876 {
877 u64 pages;
878 bool s;
879
880 pages = iommu_num_pages(address, size, PAGE_SIZE);
881 s = false;
882
883 if (pages > 1) {
884 /*
885 * If we have to flush more than one page, flush all
886 * TLB entries for this domain
887 */
888 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
889 s = true;
890 }
891
892 address &= PAGE_MASK;
893
894 memset(cmd, 0, sizeof(*cmd));
895 cmd->data[0] = devid;
896 cmd->data[0] |= (qdep & 0xff) << 24;
897 cmd->data[1] = devid;
898 cmd->data[2] = lower_32_bits(address);
899 cmd->data[3] = upper_32_bits(address);
900 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
901 if (s)
902 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
903 }
904
905 static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
906 u64 address, bool size)
907 {
908 memset(cmd, 0, sizeof(*cmd));
909
910 address &= ~(0xfffULL);
911
912 cmd->data[0] = pasid;
913 cmd->data[1] = domid;
914 cmd->data[2] = lower_32_bits(address);
915 cmd->data[3] = upper_32_bits(address);
916 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
917 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
918 if (size)
919 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
920 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
921 }
922
923 static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
924 int qdep, u64 address, bool size)
925 {
926 memset(cmd, 0, sizeof(*cmd));
927
928 address &= ~(0xfffULL);
929
930 cmd->data[0] = devid;
931 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
932 cmd->data[0] |= (qdep & 0xff) << 24;
933 cmd->data[1] = devid;
934 cmd->data[1] |= (pasid & 0xff) << 16;
935 cmd->data[2] = lower_32_bits(address);
936 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
937 cmd->data[3] = upper_32_bits(address);
938 if (size)
939 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
940 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
941 }
942
943 static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
944 int status, int tag, bool gn)
945 {
946 memset(cmd, 0, sizeof(*cmd));
947
948 cmd->data[0] = devid;
949 if (gn) {
950 cmd->data[1] = pasid;
951 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
952 }
953 cmd->data[3] = tag & 0x1ff;
954 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
955
956 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
957 }
958
959 static void build_inv_all(struct iommu_cmd *cmd)
960 {
961 memset(cmd, 0, sizeof(*cmd));
962 CMD_SET_TYPE(cmd, CMD_INV_ALL);
963 }
964
965 static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
966 {
967 memset(cmd, 0, sizeof(*cmd));
968 cmd->data[0] = devid;
969 CMD_SET_TYPE(cmd, CMD_INV_IRT);
970 }
971
972 /*
973 * Writes the command to the IOMMUs command buffer and informs the
974 * hardware about the new command.
975 */
976 static int iommu_queue_command_sync(struct amd_iommu *iommu,
977 struct iommu_cmd *cmd,
978 bool sync)
979 {
980 u32 left, tail, head, next_tail;
981 unsigned long flags;
982
983 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
984
985 again:
986 spin_lock_irqsave(&iommu->lock, flags);
987
988 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
989 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
990 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
991 left = (head - next_tail) % iommu->cmd_buf_size;
992
993 if (left <= 2) {
994 struct iommu_cmd sync_cmd;
995 volatile u64 sem = 0;
996 int ret;
997
998 build_completion_wait(&sync_cmd, (u64)&sem);
999 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
1000
1001 spin_unlock_irqrestore(&iommu->lock, flags);
1002
1003 if ((ret = wait_on_sem(&sem)) != 0)
1004 return ret;
1005
1006 goto again;
1007 }
1008
1009 copy_cmd_to_buffer(iommu, cmd, tail);
1010
1011 /* We need to sync now to make sure all commands are processed */
1012 iommu->need_sync = sync;
1013
1014 spin_unlock_irqrestore(&iommu->lock, flags);
1015
1016 return 0;
1017 }
1018
1019 static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
1020 {
1021 return iommu_queue_command_sync(iommu, cmd, true);
1022 }
1023
1024 /*
1025 * This function queues a completion wait command into the command
1026 * buffer of an IOMMU
1027 */
1028 static int iommu_completion_wait(struct amd_iommu *iommu)
1029 {
1030 struct iommu_cmd cmd;
1031 volatile u64 sem = 0;
1032 int ret;
1033
1034 if (!iommu->need_sync)
1035 return 0;
1036
1037 build_completion_wait(&cmd, (u64)&sem);
1038
1039 ret = iommu_queue_command_sync(iommu, &cmd, false);
1040 if (ret)
1041 return ret;
1042
1043 return wait_on_sem(&sem);
1044 }
1045
1046 static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
1047 {
1048 struct iommu_cmd cmd;
1049
1050 build_inv_dte(&cmd, devid);
1051
1052 return iommu_queue_command(iommu, &cmd);
1053 }
1054
1055 static void iommu_flush_dte_all(struct amd_iommu *iommu)
1056 {
1057 u32 devid;
1058
1059 for (devid = 0; devid <= 0xffff; ++devid)
1060 iommu_flush_dte(iommu, devid);
1061
1062 iommu_completion_wait(iommu);
1063 }
1064
1065 /*
1066 * This function uses heavy locking and may disable irqs for some time. But
1067 * this is no issue because it is only called during resume.
1068 */
1069 static void iommu_flush_tlb_all(struct amd_iommu *iommu)
1070 {
1071 u32 dom_id;
1072
1073 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1074 struct iommu_cmd cmd;
1075 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1076 dom_id, 1);
1077 iommu_queue_command(iommu, &cmd);
1078 }
1079
1080 iommu_completion_wait(iommu);
1081 }
1082
1083 static void iommu_flush_all(struct amd_iommu *iommu)
1084 {
1085 struct iommu_cmd cmd;
1086
1087 build_inv_all(&cmd);
1088
1089 iommu_queue_command(iommu, &cmd);
1090 iommu_completion_wait(iommu);
1091 }
1092
1093 static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1094 {
1095 struct iommu_cmd cmd;
1096
1097 build_inv_irt(&cmd, devid);
1098
1099 iommu_queue_command(iommu, &cmd);
1100 }
1101
1102 static void iommu_flush_irt_all(struct amd_iommu *iommu)
1103 {
1104 u32 devid;
1105
1106 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1107 iommu_flush_irt(iommu, devid);
1108
1109 iommu_completion_wait(iommu);
1110 }
1111
1112 void iommu_flush_all_caches(struct amd_iommu *iommu)
1113 {
1114 if (iommu_feature(iommu, FEATURE_IA)) {
1115 iommu_flush_all(iommu);
1116 } else {
1117 iommu_flush_dte_all(iommu);
1118 iommu_flush_irt_all(iommu);
1119 iommu_flush_tlb_all(iommu);
1120 }
1121 }
1122
1123 /*
1124 * Command send function for flushing on-device TLB
1125 */
1126 static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1127 u64 address, size_t size)
1128 {
1129 struct amd_iommu *iommu;
1130 struct iommu_cmd cmd;
1131 int qdep;
1132
1133 qdep = dev_data->ats.qdep;
1134 iommu = amd_iommu_rlookup_table[dev_data->devid];
1135
1136 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
1137
1138 return iommu_queue_command(iommu, &cmd);
1139 }
1140
1141 /*
1142 * Command send function for invalidating a device table entry
1143 */
1144 static int device_flush_dte(struct iommu_dev_data *dev_data)
1145 {
1146 struct amd_iommu *iommu;
1147 int ret;
1148
1149 iommu = amd_iommu_rlookup_table[dev_data->devid];
1150
1151 ret = iommu_flush_dte(iommu, dev_data->devid);
1152 if (ret)
1153 return ret;
1154
1155 if (dev_data->ats.enabled)
1156 ret = device_flush_iotlb(dev_data, 0, ~0UL);
1157
1158 return ret;
1159 }
1160
1161 /*
1162 * TLB invalidation function which is called from the mapping functions.
1163 * It invalidates a single PTE if the range to flush is within a single
1164 * page. Otherwise it flushes the whole TLB of the IOMMU.
1165 */
1166 static void __domain_flush_pages(struct protection_domain *domain,
1167 u64 address, size_t size, int pde)
1168 {
1169 struct iommu_dev_data *dev_data;
1170 struct iommu_cmd cmd;
1171 int ret = 0, i;
1172
1173 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
1174
1175 for (i = 0; i < amd_iommus_present; ++i) {
1176 if (!domain->dev_iommu[i])
1177 continue;
1178
1179 /*
1180 * Devices of this domain are behind this IOMMU
1181 * We need a TLB flush
1182 */
1183 ret |= iommu_queue_command(amd_iommus[i], &cmd);
1184 }
1185
1186 list_for_each_entry(dev_data, &domain->dev_list, list) {
1187
1188 if (!dev_data->ats.enabled)
1189 continue;
1190
1191 ret |= device_flush_iotlb(dev_data, address, size);
1192 }
1193
1194 WARN_ON(ret);
1195 }
1196
1197 static void domain_flush_pages(struct protection_domain *domain,
1198 u64 address, size_t size)
1199 {
1200 __domain_flush_pages(domain, address, size, 0);
1201 }
1202
1203 /* Flush the whole IO/TLB for a given protection domain */
1204 static void domain_flush_tlb(struct protection_domain *domain)
1205 {
1206 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
1207 }
1208
1209 /* Flush the whole IO/TLB for a given protection domain - including PDE */
1210 static void domain_flush_tlb_pde(struct protection_domain *domain)
1211 {
1212 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1213 }
1214
1215 static void domain_flush_complete(struct protection_domain *domain)
1216 {
1217 int i;
1218
1219 for (i = 0; i < amd_iommus_present; ++i) {
1220 if (!domain->dev_iommu[i])
1221 continue;
1222
1223 /*
1224 * Devices of this domain are behind this IOMMU
1225 * We need to wait for completion of all commands.
1226 */
1227 iommu_completion_wait(amd_iommus[i]);
1228 }
1229 }
1230
1231
1232 /*
1233 * This function flushes the DTEs for all devices in domain
1234 */
1235 static void domain_flush_devices(struct protection_domain *domain)
1236 {
1237 struct iommu_dev_data *dev_data;
1238
1239 list_for_each_entry(dev_data, &domain->dev_list, list)
1240 device_flush_dte(dev_data);
1241 }
1242
1243 /****************************************************************************
1244 *
1245 * The functions below are used the create the page table mappings for
1246 * unity mapped regions.
1247 *
1248 ****************************************************************************/
1249
1250 /*
1251 * This function is used to add another level to an IO page table. Adding
1252 * another level increases the size of the address space by 9 bits to a size up
1253 * to 64 bits.
1254 */
1255 static bool increase_address_space(struct protection_domain *domain,
1256 gfp_t gfp)
1257 {
1258 u64 *pte;
1259
1260 if (domain->mode == PAGE_MODE_6_LEVEL)
1261 /* address space already 64 bit large */
1262 return false;
1263
1264 pte = (void *)get_zeroed_page(gfp);
1265 if (!pte)
1266 return false;
1267
1268 *pte = PM_LEVEL_PDE(domain->mode,
1269 virt_to_phys(domain->pt_root));
1270 domain->pt_root = pte;
1271 domain->mode += 1;
1272 domain->updated = true;
1273
1274 return true;
1275 }
1276
1277 static u64 *alloc_pte(struct protection_domain *domain,
1278 unsigned long address,
1279 unsigned long page_size,
1280 u64 **pte_page,
1281 gfp_t gfp)
1282 {
1283 int level, end_lvl;
1284 u64 *pte, *page;
1285
1286 BUG_ON(!is_power_of_2(page_size));
1287
1288 while (address > PM_LEVEL_SIZE(domain->mode))
1289 increase_address_space(domain, gfp);
1290
1291 level = domain->mode - 1;
1292 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1293 address = PAGE_SIZE_ALIGN(address, page_size);
1294 end_lvl = PAGE_SIZE_LEVEL(page_size);
1295
1296 while (level > end_lvl) {
1297 if (!IOMMU_PTE_PRESENT(*pte)) {
1298 page = (u64 *)get_zeroed_page(gfp);
1299 if (!page)
1300 return NULL;
1301 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1302 }
1303
1304 /* No level skipping support yet */
1305 if (PM_PTE_LEVEL(*pte) != level)
1306 return NULL;
1307
1308 level -= 1;
1309
1310 pte = IOMMU_PTE_PAGE(*pte);
1311
1312 if (pte_page && level == end_lvl)
1313 *pte_page = pte;
1314
1315 pte = &pte[PM_LEVEL_INDEX(level, address)];
1316 }
1317
1318 return pte;
1319 }
1320
1321 /*
1322 * This function checks if there is a PTE for a given dma address. If
1323 * there is one, it returns the pointer to it.
1324 */
1325 static u64 *fetch_pte(struct protection_domain *domain,
1326 unsigned long address,
1327 unsigned long *page_size)
1328 {
1329 int level;
1330 u64 *pte;
1331
1332 if (address > PM_LEVEL_SIZE(domain->mode))
1333 return NULL;
1334
1335 level = domain->mode - 1;
1336 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1337 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1338
1339 while (level > 0) {
1340
1341 /* Not Present */
1342 if (!IOMMU_PTE_PRESENT(*pte))
1343 return NULL;
1344
1345 /* Large PTE */
1346 if (PM_PTE_LEVEL(*pte) == 7 ||
1347 PM_PTE_LEVEL(*pte) == 0)
1348 break;
1349
1350 /* No level skipping support yet */
1351 if (PM_PTE_LEVEL(*pte) != level)
1352 return NULL;
1353
1354 level -= 1;
1355
1356 /* Walk to the next level */
1357 pte = IOMMU_PTE_PAGE(*pte);
1358 pte = &pte[PM_LEVEL_INDEX(level, address)];
1359 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1360 }
1361
1362 if (PM_PTE_LEVEL(*pte) == 0x07) {
1363 unsigned long pte_mask;
1364
1365 /*
1366 * If we have a series of large PTEs, make
1367 * sure to return a pointer to the first one.
1368 */
1369 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1370 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1371 pte = (u64 *)(((unsigned long)pte) & pte_mask);
1372 }
1373
1374 return pte;
1375 }
1376
1377 /*
1378 * Generic mapping functions. It maps a physical address into a DMA
1379 * address space. It allocates the page table pages if necessary.
1380 * In the future it can be extended to a generic mapping function
1381 * supporting all features of AMD IOMMU page tables like level skipping
1382 * and full 64 bit address spaces.
1383 */
1384 static int iommu_map_page(struct protection_domain *dom,
1385 unsigned long bus_addr,
1386 unsigned long phys_addr,
1387 int prot,
1388 unsigned long page_size)
1389 {
1390 u64 __pte, *pte;
1391 int i, count;
1392
1393 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1394 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1395
1396 if (!(prot & IOMMU_PROT_MASK))
1397 return -EINVAL;
1398
1399 count = PAGE_SIZE_PTE_COUNT(page_size);
1400 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
1401
1402 if (!pte)
1403 return -ENOMEM;
1404
1405 for (i = 0; i < count; ++i)
1406 if (IOMMU_PTE_PRESENT(pte[i]))
1407 return -EBUSY;
1408
1409 if (count > 1) {
1410 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1411 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1412 } else
1413 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1414
1415 if (prot & IOMMU_PROT_IR)
1416 __pte |= IOMMU_PTE_IR;
1417 if (prot & IOMMU_PROT_IW)
1418 __pte |= IOMMU_PTE_IW;
1419
1420 for (i = 0; i < count; ++i)
1421 pte[i] = __pte;
1422
1423 update_domain(dom);
1424
1425 return 0;
1426 }
1427
1428 static unsigned long iommu_unmap_page(struct protection_domain *dom,
1429 unsigned long bus_addr,
1430 unsigned long page_size)
1431 {
1432 unsigned long long unmapped;
1433 unsigned long unmap_size;
1434 u64 *pte;
1435
1436 BUG_ON(!is_power_of_2(page_size));
1437
1438 unmapped = 0;
1439
1440 while (unmapped < page_size) {
1441
1442 pte = fetch_pte(dom, bus_addr, &unmap_size);
1443
1444 if (pte) {
1445 int i, count;
1446
1447 count = PAGE_SIZE_PTE_COUNT(unmap_size);
1448 for (i = 0; i < count; i++)
1449 pte[i] = 0ULL;
1450 }
1451
1452 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1453 unmapped += unmap_size;
1454 }
1455
1456 BUG_ON(unmapped && !is_power_of_2(unmapped));
1457
1458 return unmapped;
1459 }
1460
1461 /*
1462 * This function checks if a specific unity mapping entry is needed for
1463 * this specific IOMMU.
1464 */
1465 static int iommu_for_unity_map(struct amd_iommu *iommu,
1466 struct unity_map_entry *entry)
1467 {
1468 u16 bdf, i;
1469
1470 for (i = entry->devid_start; i <= entry->devid_end; ++i) {
1471 bdf = amd_iommu_alias_table[i];
1472 if (amd_iommu_rlookup_table[bdf] == iommu)
1473 return 1;
1474 }
1475
1476 return 0;
1477 }
1478
1479 /*
1480 * This function actually applies the mapping to the page table of the
1481 * dma_ops domain.
1482 */
1483 static int dma_ops_unity_map(struct dma_ops_domain *dma_dom,
1484 struct unity_map_entry *e)
1485 {
1486 u64 addr;
1487 int ret;
1488
1489 for (addr = e->address_start; addr < e->address_end;
1490 addr += PAGE_SIZE) {
1491 ret = iommu_map_page(&dma_dom->domain, addr, addr, e->prot,
1492 PAGE_SIZE);
1493 if (ret)
1494 return ret;
1495 /*
1496 * if unity mapping is in aperture range mark the page
1497 * as allocated in the aperture
1498 */
1499 if (addr < dma_dom->aperture_size)
1500 __set_bit(addr >> PAGE_SHIFT,
1501 dma_dom->aperture[0]->bitmap);
1502 }
1503
1504 return 0;
1505 }
1506
1507 /*
1508 * Init the unity mappings for a specific IOMMU in the system
1509 *
1510 * Basically iterates over all unity mapping entries and applies them to
1511 * the default domain DMA of that IOMMU if necessary.
1512 */
1513 static int iommu_init_unity_mappings(struct amd_iommu *iommu)
1514 {
1515 struct unity_map_entry *entry;
1516 int ret;
1517
1518 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
1519 if (!iommu_for_unity_map(iommu, entry))
1520 continue;
1521 ret = dma_ops_unity_map(iommu->default_dom, entry);
1522 if (ret)
1523 return ret;
1524 }
1525
1526 return 0;
1527 }
1528
1529 /*
1530 * Inits the unity mappings required for a specific device
1531 */
1532 static int init_unity_mappings_for_device(struct dma_ops_domain *dma_dom,
1533 u16 devid)
1534 {
1535 struct unity_map_entry *e;
1536 int ret;
1537
1538 list_for_each_entry(e, &amd_iommu_unity_map, list) {
1539 if (!(devid >= e->devid_start && devid <= e->devid_end))
1540 continue;
1541 ret = dma_ops_unity_map(dma_dom, e);
1542 if (ret)
1543 return ret;
1544 }
1545
1546 return 0;
1547 }
1548
1549 /****************************************************************************
1550 *
1551 * The next functions belong to the address allocator for the dma_ops
1552 * interface functions. They work like the allocators in the other IOMMU
1553 * drivers. Its basically a bitmap which marks the allocated pages in
1554 * the aperture. Maybe it could be enhanced in the future to a more
1555 * efficient allocator.
1556 *
1557 ****************************************************************************/
1558
1559 /*
1560 * The address allocator core functions.
1561 *
1562 * called with domain->lock held
1563 */
1564
1565 /*
1566 * Used to reserve address ranges in the aperture (e.g. for exclusion
1567 * ranges.
1568 */
1569 static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1570 unsigned long start_page,
1571 unsigned int pages)
1572 {
1573 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1574
1575 if (start_page + pages > last_page)
1576 pages = last_page - start_page;
1577
1578 for (i = start_page; i < start_page + pages; ++i) {
1579 int index = i / APERTURE_RANGE_PAGES;
1580 int page = i % APERTURE_RANGE_PAGES;
1581 __set_bit(page, dom->aperture[index]->bitmap);
1582 }
1583 }
1584
1585 /*
1586 * This function is used to add a new aperture range to an existing
1587 * aperture in case of dma_ops domain allocation or address allocation
1588 * failure.
1589 */
1590 static int alloc_new_range(struct dma_ops_domain *dma_dom,
1591 bool populate, gfp_t gfp)
1592 {
1593 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
1594 struct amd_iommu *iommu;
1595 unsigned long i, old_size, pte_pgsize;
1596
1597 #ifdef CONFIG_IOMMU_STRESS
1598 populate = false;
1599 #endif
1600
1601 if (index >= APERTURE_MAX_RANGES)
1602 return -ENOMEM;
1603
1604 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1605 if (!dma_dom->aperture[index])
1606 return -ENOMEM;
1607
1608 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1609 if (!dma_dom->aperture[index]->bitmap)
1610 goto out_free;
1611
1612 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1613
1614 if (populate) {
1615 unsigned long address = dma_dom->aperture_size;
1616 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1617 u64 *pte, *pte_page;
1618
1619 for (i = 0; i < num_ptes; ++i) {
1620 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
1621 &pte_page, gfp);
1622 if (!pte)
1623 goto out_free;
1624
1625 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1626
1627 address += APERTURE_RANGE_SIZE / 64;
1628 }
1629 }
1630
1631 old_size = dma_dom->aperture_size;
1632 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1633
1634 /* Reserve address range used for MSI messages */
1635 if (old_size < MSI_ADDR_BASE_LO &&
1636 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1637 unsigned long spage;
1638 int pages;
1639
1640 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1641 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1642
1643 dma_ops_reserve_addresses(dma_dom, spage, pages);
1644 }
1645
1646 /* Initialize the exclusion range if necessary */
1647 for_each_iommu(iommu) {
1648 if (iommu->exclusion_start &&
1649 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1650 && iommu->exclusion_start < dma_dom->aperture_size) {
1651 unsigned long startpage;
1652 int pages = iommu_num_pages(iommu->exclusion_start,
1653 iommu->exclusion_length,
1654 PAGE_SIZE);
1655 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1656 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1657 }
1658 }
1659
1660 /*
1661 * Check for areas already mapped as present in the new aperture
1662 * range and mark those pages as reserved in the allocator. Such
1663 * mappings may already exist as a result of requested unity
1664 * mappings for devices.
1665 */
1666 for (i = dma_dom->aperture[index]->offset;
1667 i < dma_dom->aperture_size;
1668 i += pte_pgsize) {
1669 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
1670 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1671 continue;
1672
1673 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1674 pte_pgsize >> 12);
1675 }
1676
1677 update_domain(&dma_dom->domain);
1678
1679 return 0;
1680
1681 out_free:
1682 update_domain(&dma_dom->domain);
1683
1684 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1685
1686 kfree(dma_dom->aperture[index]);
1687 dma_dom->aperture[index] = NULL;
1688
1689 return -ENOMEM;
1690 }
1691
1692 static unsigned long dma_ops_area_alloc(struct device *dev,
1693 struct dma_ops_domain *dom,
1694 unsigned int pages,
1695 unsigned long align_mask,
1696 u64 dma_mask,
1697 unsigned long start)
1698 {
1699 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
1700 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1701 int i = start >> APERTURE_RANGE_SHIFT;
1702 unsigned long boundary_size, mask;
1703 unsigned long address = -1;
1704 unsigned long limit;
1705
1706 next_bit >>= PAGE_SHIFT;
1707
1708 mask = dma_get_seg_boundary(dev);
1709
1710 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1711 1UL << (BITS_PER_LONG - PAGE_SHIFT);
1712
1713 for (;i < max_index; ++i) {
1714 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1715
1716 if (dom->aperture[i]->offset >= dma_mask)
1717 break;
1718
1719 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1720 dma_mask >> PAGE_SHIFT);
1721
1722 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1723 limit, next_bit, pages, 0,
1724 boundary_size, align_mask);
1725 if (address != -1) {
1726 address = dom->aperture[i]->offset +
1727 (address << PAGE_SHIFT);
1728 dom->next_address = address + (pages << PAGE_SHIFT);
1729 break;
1730 }
1731
1732 next_bit = 0;
1733 }
1734
1735 return address;
1736 }
1737
1738 static unsigned long dma_ops_alloc_addresses(struct device *dev,
1739 struct dma_ops_domain *dom,
1740 unsigned int pages,
1741 unsigned long align_mask,
1742 u64 dma_mask)
1743 {
1744 unsigned long address;
1745
1746 #ifdef CONFIG_IOMMU_STRESS
1747 dom->next_address = 0;
1748 dom->need_flush = true;
1749 #endif
1750
1751 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1752 dma_mask, dom->next_address);
1753
1754 if (address == -1) {
1755 dom->next_address = 0;
1756 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1757 dma_mask, 0);
1758 dom->need_flush = true;
1759 }
1760
1761 if (unlikely(address == -1))
1762 address = DMA_ERROR_CODE;
1763
1764 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1765
1766 return address;
1767 }
1768
1769 /*
1770 * The address free function.
1771 *
1772 * called with domain->lock held
1773 */
1774 static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1775 unsigned long address,
1776 unsigned int pages)
1777 {
1778 unsigned i = address >> APERTURE_RANGE_SHIFT;
1779 struct aperture_range *range = dom->aperture[i];
1780
1781 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1782
1783 #ifdef CONFIG_IOMMU_STRESS
1784 if (i < 4)
1785 return;
1786 #endif
1787
1788 if (address >= dom->next_address)
1789 dom->need_flush = true;
1790
1791 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
1792
1793 bitmap_clear(range->bitmap, address, pages);
1794
1795 }
1796
1797 /****************************************************************************
1798 *
1799 * The next functions belong to the domain allocation. A domain is
1800 * allocated for every IOMMU as the default domain. If device isolation
1801 * is enabled, every device get its own domain. The most important thing
1802 * about domains is the page table mapping the DMA address space they
1803 * contain.
1804 *
1805 ****************************************************************************/
1806
1807 /*
1808 * This function adds a protection domain to the global protection domain list
1809 */
1810 static void add_domain_to_list(struct protection_domain *domain)
1811 {
1812 unsigned long flags;
1813
1814 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1815 list_add(&domain->list, &amd_iommu_pd_list);
1816 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1817 }
1818
1819 /*
1820 * This function removes a protection domain to the global
1821 * protection domain list
1822 */
1823 static void del_domain_from_list(struct protection_domain *domain)
1824 {
1825 unsigned long flags;
1826
1827 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1828 list_del(&domain->list);
1829 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1830 }
1831
1832 static u16 domain_id_alloc(void)
1833 {
1834 unsigned long flags;
1835 int id;
1836
1837 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1838 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1839 BUG_ON(id == 0);
1840 if (id > 0 && id < MAX_DOMAIN_ID)
1841 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1842 else
1843 id = 0;
1844 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1845
1846 return id;
1847 }
1848
1849 static void domain_id_free(int id)
1850 {
1851 unsigned long flags;
1852
1853 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1854 if (id > 0 && id < MAX_DOMAIN_ID)
1855 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1856 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1857 }
1858
1859 #define DEFINE_FREE_PT_FN(LVL, FN) \
1860 static void free_pt_##LVL (unsigned long __pt) \
1861 { \
1862 unsigned long p; \
1863 u64 *pt; \
1864 int i; \
1865 \
1866 pt = (u64 *)__pt; \
1867 \
1868 for (i = 0; i < 512; ++i) { \
1869 if (!IOMMU_PTE_PRESENT(pt[i])) \
1870 continue; \
1871 \
1872 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1873 FN(p); \
1874 } \
1875 free_page((unsigned long)pt); \
1876 }
1877
1878 DEFINE_FREE_PT_FN(l2, free_page)
1879 DEFINE_FREE_PT_FN(l3, free_pt_l2)
1880 DEFINE_FREE_PT_FN(l4, free_pt_l3)
1881 DEFINE_FREE_PT_FN(l5, free_pt_l4)
1882 DEFINE_FREE_PT_FN(l6, free_pt_l5)
1883
1884 static void free_pagetable(struct protection_domain *domain)
1885 {
1886 unsigned long root = (unsigned long)domain->pt_root;
1887
1888 switch (domain->mode) {
1889 case PAGE_MODE_NONE:
1890 break;
1891 case PAGE_MODE_1_LEVEL:
1892 free_page(root);
1893 break;
1894 case PAGE_MODE_2_LEVEL:
1895 free_pt_l2(root);
1896 break;
1897 case PAGE_MODE_3_LEVEL:
1898 free_pt_l3(root);
1899 break;
1900 case PAGE_MODE_4_LEVEL:
1901 free_pt_l4(root);
1902 break;
1903 case PAGE_MODE_5_LEVEL:
1904 free_pt_l5(root);
1905 break;
1906 case PAGE_MODE_6_LEVEL:
1907 free_pt_l6(root);
1908 break;
1909 default:
1910 BUG();
1911 }
1912 }
1913
1914 static void free_gcr3_tbl_level1(u64 *tbl)
1915 {
1916 u64 *ptr;
1917 int i;
1918
1919 for (i = 0; i < 512; ++i) {
1920 if (!(tbl[i] & GCR3_VALID))
1921 continue;
1922
1923 ptr = __va(tbl[i] & PAGE_MASK);
1924
1925 free_page((unsigned long)ptr);
1926 }
1927 }
1928
1929 static void free_gcr3_tbl_level2(u64 *tbl)
1930 {
1931 u64 *ptr;
1932 int i;
1933
1934 for (i = 0; i < 512; ++i) {
1935 if (!(tbl[i] & GCR3_VALID))
1936 continue;
1937
1938 ptr = __va(tbl[i] & PAGE_MASK);
1939
1940 free_gcr3_tbl_level1(ptr);
1941 }
1942 }
1943
1944 static void free_gcr3_table(struct protection_domain *domain)
1945 {
1946 if (domain->glx == 2)
1947 free_gcr3_tbl_level2(domain->gcr3_tbl);
1948 else if (domain->glx == 1)
1949 free_gcr3_tbl_level1(domain->gcr3_tbl);
1950 else if (domain->glx != 0)
1951 BUG();
1952
1953 free_page((unsigned long)domain->gcr3_tbl);
1954 }
1955
1956 /*
1957 * Free a domain, only used if something went wrong in the
1958 * allocation path and we need to free an already allocated page table
1959 */
1960 static void dma_ops_domain_free(struct dma_ops_domain *dom)
1961 {
1962 int i;
1963
1964 if (!dom)
1965 return;
1966
1967 del_domain_from_list(&dom->domain);
1968
1969 free_pagetable(&dom->domain);
1970
1971 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1972 if (!dom->aperture[i])
1973 continue;
1974 free_page((unsigned long)dom->aperture[i]->bitmap);
1975 kfree(dom->aperture[i]);
1976 }
1977
1978 kfree(dom);
1979 }
1980
1981 /*
1982 * Allocates a new protection domain usable for the dma_ops functions.
1983 * It also initializes the page table and the address allocator data
1984 * structures required for the dma_ops interface
1985 */
1986 static struct dma_ops_domain *dma_ops_domain_alloc(void)
1987 {
1988 struct dma_ops_domain *dma_dom;
1989
1990 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1991 if (!dma_dom)
1992 return NULL;
1993
1994 spin_lock_init(&dma_dom->domain.lock);
1995
1996 dma_dom->domain.id = domain_id_alloc();
1997 if (dma_dom->domain.id == 0)
1998 goto free_dma_dom;
1999 INIT_LIST_HEAD(&dma_dom->domain.dev_list);
2000 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
2001 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2002 dma_dom->domain.flags = PD_DMA_OPS_MASK;
2003 dma_dom->domain.priv = dma_dom;
2004 if (!dma_dom->domain.pt_root)
2005 goto free_dma_dom;
2006
2007 dma_dom->need_flush = false;
2008 dma_dom->target_dev = 0xffff;
2009
2010 add_domain_to_list(&dma_dom->domain);
2011
2012 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
2013 goto free_dma_dom;
2014
2015 /*
2016 * mark the first page as allocated so we never return 0 as
2017 * a valid dma-address. So we can use 0 as error value
2018 */
2019 dma_dom->aperture[0]->bitmap[0] = 1;
2020 dma_dom->next_address = 0;
2021
2022
2023 return dma_dom;
2024
2025 free_dma_dom:
2026 dma_ops_domain_free(dma_dom);
2027
2028 return NULL;
2029 }
2030
2031 /*
2032 * little helper function to check whether a given protection domain is a
2033 * dma_ops domain
2034 */
2035 static bool dma_ops_domain(struct protection_domain *domain)
2036 {
2037 return domain->flags & PD_DMA_OPS_MASK;
2038 }
2039
2040 static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
2041 {
2042 u64 pte_root = 0;
2043 u64 flags = 0;
2044
2045 if (domain->mode != PAGE_MODE_NONE)
2046 pte_root = virt_to_phys(domain->pt_root);
2047
2048 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
2049 << DEV_ENTRY_MODE_SHIFT;
2050 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
2051
2052 flags = amd_iommu_dev_table[devid].data[1];
2053
2054 if (ats)
2055 flags |= DTE_FLAG_IOTLB;
2056
2057 if (domain->flags & PD_IOMMUV2_MASK) {
2058 u64 gcr3 = __pa(domain->gcr3_tbl);
2059 u64 glx = domain->glx;
2060 u64 tmp;
2061
2062 pte_root |= DTE_FLAG_GV;
2063 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
2064
2065 /* First mask out possible old values for GCR3 table */
2066 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
2067 flags &= ~tmp;
2068
2069 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
2070 flags &= ~tmp;
2071
2072 /* Encode GCR3 table into DTE */
2073 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
2074 pte_root |= tmp;
2075
2076 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
2077 flags |= tmp;
2078
2079 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
2080 flags |= tmp;
2081 }
2082
2083 flags &= ~(0xffffUL);
2084 flags |= domain->id;
2085
2086 amd_iommu_dev_table[devid].data[1] = flags;
2087 amd_iommu_dev_table[devid].data[0] = pte_root;
2088 }
2089
2090 static void clear_dte_entry(u16 devid)
2091 {
2092 /* remove entry from the device table seen by the hardware */
2093 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
2094 amd_iommu_dev_table[devid].data[1] = 0;
2095
2096 amd_iommu_apply_erratum_63(devid);
2097 }
2098
2099 static void do_attach(struct iommu_dev_data *dev_data,
2100 struct protection_domain *domain)
2101 {
2102 struct amd_iommu *iommu;
2103 bool ats;
2104
2105 iommu = amd_iommu_rlookup_table[dev_data->devid];
2106 ats = dev_data->ats.enabled;
2107
2108 /* Update data structures */
2109 dev_data->domain = domain;
2110 list_add(&dev_data->list, &domain->dev_list);
2111 set_dte_entry(dev_data->devid, domain, ats);
2112
2113 /* Do reference counting */
2114 domain->dev_iommu[iommu->index] += 1;
2115 domain->dev_cnt += 1;
2116
2117 /* Flush the DTE entry */
2118 device_flush_dte(dev_data);
2119 }
2120
2121 static void do_detach(struct iommu_dev_data *dev_data)
2122 {
2123 struct amd_iommu *iommu;
2124
2125 iommu = amd_iommu_rlookup_table[dev_data->devid];
2126
2127 /* decrease reference counters */
2128 dev_data->domain->dev_iommu[iommu->index] -= 1;
2129 dev_data->domain->dev_cnt -= 1;
2130
2131 /* Update data structures */
2132 dev_data->domain = NULL;
2133 list_del(&dev_data->list);
2134 clear_dte_entry(dev_data->devid);
2135
2136 /* Flush the DTE entry */
2137 device_flush_dte(dev_data);
2138 }
2139
2140 /*
2141 * If a device is not yet associated with a domain, this function does
2142 * assigns it visible for the hardware
2143 */
2144 static int __attach_device(struct iommu_dev_data *dev_data,
2145 struct protection_domain *domain)
2146 {
2147 struct iommu_dev_data *head, *entry;
2148 int ret;
2149
2150 /* lock domain */
2151 spin_lock(&domain->lock);
2152
2153 head = dev_data;
2154
2155 if (head->alias_data != NULL)
2156 head = head->alias_data;
2157
2158 /* Now we have the root of the alias group, if any */
2159
2160 ret = -EBUSY;
2161 if (head->domain != NULL)
2162 goto out_unlock;
2163
2164 /* Attach alias group root */
2165 do_attach(head, domain);
2166
2167 /* Attach other devices in the alias group */
2168 list_for_each_entry(entry, &head->alias_list, alias_list)
2169 do_attach(entry, domain);
2170
2171 ret = 0;
2172
2173 out_unlock:
2174
2175 /* ready */
2176 spin_unlock(&domain->lock);
2177
2178 return ret;
2179 }
2180
2181
2182 static void pdev_iommuv2_disable(struct pci_dev *pdev)
2183 {
2184 pci_disable_ats(pdev);
2185 pci_disable_pri(pdev);
2186 pci_disable_pasid(pdev);
2187 }
2188
2189 /* FIXME: Change generic reset-function to do the same */
2190 static int pri_reset_while_enabled(struct pci_dev *pdev)
2191 {
2192 u16 control;
2193 int pos;
2194
2195 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2196 if (!pos)
2197 return -EINVAL;
2198
2199 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2200 control |= PCI_PRI_CTRL_RESET;
2201 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
2202
2203 return 0;
2204 }
2205
2206 static int pdev_iommuv2_enable(struct pci_dev *pdev)
2207 {
2208 bool reset_enable;
2209 int reqs, ret;
2210
2211 /* FIXME: Hardcode number of outstanding requests for now */
2212 reqs = 32;
2213 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2214 reqs = 1;
2215 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
2216
2217 /* Only allow access to user-accessible pages */
2218 ret = pci_enable_pasid(pdev, 0);
2219 if (ret)
2220 goto out_err;
2221
2222 /* First reset the PRI state of the device */
2223 ret = pci_reset_pri(pdev);
2224 if (ret)
2225 goto out_err;
2226
2227 /* Enable PRI */
2228 ret = pci_enable_pri(pdev, reqs);
2229 if (ret)
2230 goto out_err;
2231
2232 if (reset_enable) {
2233 ret = pri_reset_while_enabled(pdev);
2234 if (ret)
2235 goto out_err;
2236 }
2237
2238 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2239 if (ret)
2240 goto out_err;
2241
2242 return 0;
2243
2244 out_err:
2245 pci_disable_pri(pdev);
2246 pci_disable_pasid(pdev);
2247
2248 return ret;
2249 }
2250
2251 /* FIXME: Move this to PCI code */
2252 #define PCI_PRI_TLP_OFF (1 << 15)
2253
2254 static bool pci_pri_tlp_required(struct pci_dev *pdev)
2255 {
2256 u16 status;
2257 int pos;
2258
2259 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
2260 if (!pos)
2261 return false;
2262
2263 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
2264
2265 return (status & PCI_PRI_TLP_OFF) ? true : false;
2266 }
2267
2268 /*
2269 * If a device is not yet associated with a domain, this function
2270 * assigns it visible for the hardware
2271 */
2272 static int attach_device(struct device *dev,
2273 struct protection_domain *domain)
2274 {
2275 struct pci_dev *pdev = to_pci_dev(dev);
2276 struct iommu_dev_data *dev_data;
2277 unsigned long flags;
2278 int ret;
2279
2280 dev_data = get_dev_data(dev);
2281
2282 if (domain->flags & PD_IOMMUV2_MASK) {
2283 if (!dev_data->iommu_v2 || !dev_data->passthrough)
2284 return -EINVAL;
2285
2286 if (pdev_iommuv2_enable(pdev) != 0)
2287 return -EINVAL;
2288
2289 dev_data->ats.enabled = true;
2290 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2291 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2292 } else if (amd_iommu_iotlb_sup &&
2293 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
2294 dev_data->ats.enabled = true;
2295 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2296 }
2297
2298 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2299 ret = __attach_device(dev_data, domain);
2300 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2301
2302 /*
2303 * We might boot into a crash-kernel here. The crashed kernel
2304 * left the caches in the IOMMU dirty. So we have to flush
2305 * here to evict all dirty stuff.
2306 */
2307 domain_flush_tlb_pde(domain);
2308
2309 return ret;
2310 }
2311
2312 /*
2313 * Removes a device from a protection domain (unlocked)
2314 */
2315 static void __detach_device(struct iommu_dev_data *dev_data)
2316 {
2317 struct iommu_dev_data *head, *entry;
2318 struct protection_domain *domain;
2319 unsigned long flags;
2320
2321 BUG_ON(!dev_data->domain);
2322
2323 domain = dev_data->domain;
2324
2325 spin_lock_irqsave(&domain->lock, flags);
2326
2327 head = dev_data;
2328 if (head->alias_data != NULL)
2329 head = head->alias_data;
2330
2331 list_for_each_entry(entry, &head->alias_list, alias_list)
2332 do_detach(entry);
2333
2334 do_detach(head);
2335
2336 spin_unlock_irqrestore(&domain->lock, flags);
2337
2338 /*
2339 * If we run in passthrough mode the device must be assigned to the
2340 * passthrough domain if it is detached from any other domain.
2341 * Make sure we can deassign from the pt_domain itself.
2342 */
2343 if (dev_data->passthrough &&
2344 (dev_data->domain == NULL && domain != pt_domain))
2345 __attach_device(dev_data, pt_domain);
2346 }
2347
2348 /*
2349 * Removes a device from a protection domain (with devtable_lock held)
2350 */
2351 static void detach_device(struct device *dev)
2352 {
2353 struct protection_domain *domain;
2354 struct iommu_dev_data *dev_data;
2355 unsigned long flags;
2356
2357 dev_data = get_dev_data(dev);
2358 domain = dev_data->domain;
2359
2360 /* lock device table */
2361 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2362 __detach_device(dev_data);
2363 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2364
2365 if (domain->flags & PD_IOMMUV2_MASK)
2366 pdev_iommuv2_disable(to_pci_dev(dev));
2367 else if (dev_data->ats.enabled)
2368 pci_disable_ats(to_pci_dev(dev));
2369
2370 dev_data->ats.enabled = false;
2371 }
2372
2373 /*
2374 * Find out the protection domain structure for a given PCI device. This
2375 * will give us the pointer to the page table root for example.
2376 */
2377 static struct protection_domain *domain_for_device(struct device *dev)
2378 {
2379 struct iommu_dev_data *dev_data;
2380 struct protection_domain *dom = NULL;
2381 unsigned long flags;
2382
2383 dev_data = get_dev_data(dev);
2384
2385 if (dev_data->domain)
2386 return dev_data->domain;
2387
2388 if (dev_data->alias_data != NULL) {
2389 struct iommu_dev_data *alias_data = dev_data->alias_data;
2390
2391 read_lock_irqsave(&amd_iommu_devtable_lock, flags);
2392 if (alias_data->domain != NULL) {
2393 __attach_device(dev_data, alias_data->domain);
2394 dom = alias_data->domain;
2395 }
2396 read_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2397 }
2398
2399 return dom;
2400 }
2401
2402 static int device_change_notifier(struct notifier_block *nb,
2403 unsigned long action, void *data)
2404 {
2405 struct dma_ops_domain *dma_domain;
2406 struct protection_domain *domain;
2407 struct iommu_dev_data *dev_data;
2408 struct device *dev = data;
2409 struct amd_iommu *iommu;
2410 unsigned long flags;
2411 u16 devid;
2412
2413 if (!check_device(dev))
2414 return 0;
2415
2416 devid = get_device_id(dev);
2417 iommu = amd_iommu_rlookup_table[devid];
2418 dev_data = get_dev_data(dev);
2419
2420 switch (action) {
2421 case BUS_NOTIFY_ADD_DEVICE:
2422
2423 iommu_init_device(dev);
2424 init_iommu_group(dev);
2425
2426 /*
2427 * dev_data is still NULL and
2428 * got initialized in iommu_init_device
2429 */
2430 dev_data = get_dev_data(dev);
2431
2432 if (iommu_pass_through || dev_data->iommu_v2) {
2433 dev_data->passthrough = true;
2434 attach_device(dev, pt_domain);
2435 break;
2436 }
2437
2438 domain = domain_for_device(dev);
2439
2440 /* allocate a protection domain if a device is added */
2441 dma_domain = find_protection_domain(devid);
2442 if (!dma_domain) {
2443 dma_domain = dma_ops_domain_alloc();
2444 if (!dma_domain)
2445 goto out;
2446 dma_domain->target_dev = devid;
2447
2448 spin_lock_irqsave(&iommu_pd_list_lock, flags);
2449 list_add_tail(&dma_domain->list, &iommu_pd_list);
2450 spin_unlock_irqrestore(&iommu_pd_list_lock, flags);
2451 }
2452
2453 dev->archdata.dma_ops = &amd_iommu_dma_ops;
2454
2455 break;
2456 case BUS_NOTIFY_REMOVED_DEVICE:
2457
2458 iommu_uninit_device(dev);
2459
2460 default:
2461 goto out;
2462 }
2463
2464 iommu_completion_wait(iommu);
2465
2466 out:
2467 return 0;
2468 }
2469
2470 static struct notifier_block device_nb = {
2471 .notifier_call = device_change_notifier,
2472 };
2473
2474 void amd_iommu_init_notifier(void)
2475 {
2476 bus_register_notifier(&pci_bus_type, &device_nb);
2477 }
2478
2479 /*****************************************************************************
2480 *
2481 * The next functions belong to the dma_ops mapping/unmapping code.
2482 *
2483 *****************************************************************************/
2484
2485 /*
2486 * In the dma_ops path we only have the struct device. This function
2487 * finds the corresponding IOMMU, the protection domain and the
2488 * requestor id for a given device.
2489 * If the device is not yet associated with a domain this is also done
2490 * in this function.
2491 */
2492 static struct protection_domain *get_domain(struct device *dev)
2493 {
2494 struct protection_domain *domain;
2495 struct dma_ops_domain *dma_dom;
2496 u16 devid = get_device_id(dev);
2497
2498 if (!check_device(dev))
2499 return ERR_PTR(-EINVAL);
2500
2501 domain = domain_for_device(dev);
2502 if (domain != NULL && !dma_ops_domain(domain))
2503 return ERR_PTR(-EBUSY);
2504
2505 if (domain != NULL)
2506 return domain;
2507
2508 /* Device not bound yet - bind it */
2509 dma_dom = find_protection_domain(devid);
2510 if (!dma_dom)
2511 dma_dom = amd_iommu_rlookup_table[devid]->default_dom;
2512 attach_device(dev, &dma_dom->domain);
2513 DUMP_printk("Using protection domain %d for device %s\n",
2514 dma_dom->domain.id, dev_name(dev));
2515
2516 return &dma_dom->domain;
2517 }
2518
2519 static void update_device_table(struct protection_domain *domain)
2520 {
2521 struct iommu_dev_data *dev_data;
2522
2523 list_for_each_entry(dev_data, &domain->dev_list, list)
2524 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
2525 }
2526
2527 static void update_domain(struct protection_domain *domain)
2528 {
2529 if (!domain->updated)
2530 return;
2531
2532 update_device_table(domain);
2533
2534 domain_flush_devices(domain);
2535 domain_flush_tlb_pde(domain);
2536
2537 domain->updated = false;
2538 }
2539
2540 /*
2541 * This function fetches the PTE for a given address in the aperture
2542 */
2543 static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2544 unsigned long address)
2545 {
2546 struct aperture_range *aperture;
2547 u64 *pte, *pte_page;
2548
2549 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2550 if (!aperture)
2551 return NULL;
2552
2553 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2554 if (!pte) {
2555 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
2556 GFP_ATOMIC);
2557 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2558 } else
2559 pte += PM_LEVEL_INDEX(0, address);
2560
2561 update_domain(&dom->domain);
2562
2563 return pte;
2564 }
2565
2566 /*
2567 * This is the generic map function. It maps one 4kb page at paddr to
2568 * the given address in the DMA address space for the domain.
2569 */
2570 static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
2571 unsigned long address,
2572 phys_addr_t paddr,
2573 int direction)
2574 {
2575 u64 *pte, __pte;
2576
2577 WARN_ON(address > dom->aperture_size);
2578
2579 paddr &= PAGE_MASK;
2580
2581 pte = dma_ops_get_pte(dom, address);
2582 if (!pte)
2583 return DMA_ERROR_CODE;
2584
2585 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2586
2587 if (direction == DMA_TO_DEVICE)
2588 __pte |= IOMMU_PTE_IR;
2589 else if (direction == DMA_FROM_DEVICE)
2590 __pte |= IOMMU_PTE_IW;
2591 else if (direction == DMA_BIDIRECTIONAL)
2592 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2593
2594 WARN_ON(*pte);
2595
2596 *pte = __pte;
2597
2598 return (dma_addr_t)address;
2599 }
2600
2601 /*
2602 * The generic unmapping function for on page in the DMA address space.
2603 */
2604 static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
2605 unsigned long address)
2606 {
2607 struct aperture_range *aperture;
2608 u64 *pte;
2609
2610 if (address >= dom->aperture_size)
2611 return;
2612
2613 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2614 if (!aperture)
2615 return;
2616
2617 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2618 if (!pte)
2619 return;
2620
2621 pte += PM_LEVEL_INDEX(0, address);
2622
2623 WARN_ON(!*pte);
2624
2625 *pte = 0ULL;
2626 }
2627
2628 /*
2629 * This function contains common code for mapping of a physically
2630 * contiguous memory region into DMA address space. It is used by all
2631 * mapping functions provided with this IOMMU driver.
2632 * Must be called with the domain lock held.
2633 */
2634 static dma_addr_t __map_single(struct device *dev,
2635 struct dma_ops_domain *dma_dom,
2636 phys_addr_t paddr,
2637 size_t size,
2638 int dir,
2639 bool align,
2640 u64 dma_mask)
2641 {
2642 dma_addr_t offset = paddr & ~PAGE_MASK;
2643 dma_addr_t address, start, ret;
2644 unsigned int pages;
2645 unsigned long align_mask = 0;
2646 int i;
2647
2648 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
2649 paddr &= PAGE_MASK;
2650
2651 INC_STATS_COUNTER(total_map_requests);
2652
2653 if (pages > 1)
2654 INC_STATS_COUNTER(cross_page);
2655
2656 if (align)
2657 align_mask = (1UL << get_order(size)) - 1;
2658
2659 retry:
2660 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2661 dma_mask);
2662 if (unlikely(address == DMA_ERROR_CODE)) {
2663 /*
2664 * setting next_address here will let the address
2665 * allocator only scan the new allocated range in the
2666 * first run. This is a small optimization.
2667 */
2668 dma_dom->next_address = dma_dom->aperture_size;
2669
2670 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
2671 goto out;
2672
2673 /*
2674 * aperture was successfully enlarged by 128 MB, try
2675 * allocation again
2676 */
2677 goto retry;
2678 }
2679
2680 start = address;
2681 for (i = 0; i < pages; ++i) {
2682 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
2683 if (ret == DMA_ERROR_CODE)
2684 goto out_unmap;
2685
2686 paddr += PAGE_SIZE;
2687 start += PAGE_SIZE;
2688 }
2689 address += offset;
2690
2691 ADD_STATS_COUNTER(alloced_io_mem, size);
2692
2693 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
2694 domain_flush_tlb(&dma_dom->domain);
2695 dma_dom->need_flush = false;
2696 } else if (unlikely(amd_iommu_np_cache))
2697 domain_flush_pages(&dma_dom->domain, address, size);
2698
2699 out:
2700 return address;
2701
2702 out_unmap:
2703
2704 for (--i; i >= 0; --i) {
2705 start -= PAGE_SIZE;
2706 dma_ops_domain_unmap(dma_dom, start);
2707 }
2708
2709 dma_ops_free_addresses(dma_dom, address, pages);
2710
2711 return DMA_ERROR_CODE;
2712 }
2713
2714 /*
2715 * Does the reverse of the __map_single function. Must be called with
2716 * the domain lock held too
2717 */
2718 static void __unmap_single(struct dma_ops_domain *dma_dom,
2719 dma_addr_t dma_addr,
2720 size_t size,
2721 int dir)
2722 {
2723 dma_addr_t flush_addr;
2724 dma_addr_t i, start;
2725 unsigned int pages;
2726
2727 if ((dma_addr == DMA_ERROR_CODE) ||
2728 (dma_addr + size > dma_dom->aperture_size))
2729 return;
2730
2731 flush_addr = dma_addr;
2732 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
2733 dma_addr &= PAGE_MASK;
2734 start = dma_addr;
2735
2736 for (i = 0; i < pages; ++i) {
2737 dma_ops_domain_unmap(dma_dom, start);
2738 start += PAGE_SIZE;
2739 }
2740
2741 SUB_STATS_COUNTER(alloced_io_mem, size);
2742
2743 dma_ops_free_addresses(dma_dom, dma_addr, pages);
2744
2745 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
2746 domain_flush_pages(&dma_dom->domain, flush_addr, size);
2747 dma_dom->need_flush = false;
2748 }
2749 }
2750
2751 /*
2752 * The exported map_single function for dma_ops.
2753 */
2754 static dma_addr_t map_page(struct device *dev, struct page *page,
2755 unsigned long offset, size_t size,
2756 enum dma_data_direction dir,
2757 struct dma_attrs *attrs)
2758 {
2759 unsigned long flags;
2760 struct protection_domain *domain;
2761 dma_addr_t addr;
2762 u64 dma_mask;
2763 phys_addr_t paddr = page_to_phys(page) + offset;
2764
2765 INC_STATS_COUNTER(cnt_map_single);
2766
2767 domain = get_domain(dev);
2768 if (PTR_ERR(domain) == -EINVAL)
2769 return (dma_addr_t)paddr;
2770 else if (IS_ERR(domain))
2771 return DMA_ERROR_CODE;
2772
2773 dma_mask = *dev->dma_mask;
2774
2775 spin_lock_irqsave(&domain->lock, flags);
2776
2777 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
2778 dma_mask);
2779 if (addr == DMA_ERROR_CODE)
2780 goto out;
2781
2782 domain_flush_complete(domain);
2783
2784 out:
2785 spin_unlock_irqrestore(&domain->lock, flags);
2786
2787 return addr;
2788 }
2789
2790 /*
2791 * The exported unmap_single function for dma_ops.
2792 */
2793 static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2794 enum dma_data_direction dir, struct dma_attrs *attrs)
2795 {
2796 unsigned long flags;
2797 struct protection_domain *domain;
2798
2799 INC_STATS_COUNTER(cnt_unmap_single);
2800
2801 domain = get_domain(dev);
2802 if (IS_ERR(domain))
2803 return;
2804
2805 spin_lock_irqsave(&domain->lock, flags);
2806
2807 __unmap_single(domain->priv, dma_addr, size, dir);
2808
2809 domain_flush_complete(domain);
2810
2811 spin_unlock_irqrestore(&domain->lock, flags);
2812 }
2813
2814 /*
2815 * The exported map_sg function for dma_ops (handles scatter-gather
2816 * lists).
2817 */
2818 static int map_sg(struct device *dev, struct scatterlist *sglist,
2819 int nelems, enum dma_data_direction dir,
2820 struct dma_attrs *attrs)
2821 {
2822 unsigned long flags;
2823 struct protection_domain *domain;
2824 int i;
2825 struct scatterlist *s;
2826 phys_addr_t paddr;
2827 int mapped_elems = 0;
2828 u64 dma_mask;
2829
2830 INC_STATS_COUNTER(cnt_map_sg);
2831
2832 domain = get_domain(dev);
2833 if (IS_ERR(domain))
2834 return 0;
2835
2836 dma_mask = *dev->dma_mask;
2837
2838 spin_lock_irqsave(&domain->lock, flags);
2839
2840 for_each_sg(sglist, s, nelems, i) {
2841 paddr = sg_phys(s);
2842
2843 s->dma_address = __map_single(dev, domain->priv,
2844 paddr, s->length, dir, false,
2845 dma_mask);
2846
2847 if (s->dma_address) {
2848 s->dma_length = s->length;
2849 mapped_elems++;
2850 } else
2851 goto unmap;
2852 }
2853
2854 domain_flush_complete(domain);
2855
2856 out:
2857 spin_unlock_irqrestore(&domain->lock, flags);
2858
2859 return mapped_elems;
2860 unmap:
2861 for_each_sg(sglist, s, mapped_elems, i) {
2862 if (s->dma_address)
2863 __unmap_single(domain->priv, s->dma_address,
2864 s->dma_length, dir);
2865 s->dma_address = s->dma_length = 0;
2866 }
2867
2868 mapped_elems = 0;
2869
2870 goto out;
2871 }
2872
2873 /*
2874 * The exported map_sg function for dma_ops (handles scatter-gather
2875 * lists).
2876 */
2877 static void unmap_sg(struct device *dev, struct scatterlist *sglist,
2878 int nelems, enum dma_data_direction dir,
2879 struct dma_attrs *attrs)
2880 {
2881 unsigned long flags;
2882 struct protection_domain *domain;
2883 struct scatterlist *s;
2884 int i;
2885
2886 INC_STATS_COUNTER(cnt_unmap_sg);
2887
2888 domain = get_domain(dev);
2889 if (IS_ERR(domain))
2890 return;
2891
2892 spin_lock_irqsave(&domain->lock, flags);
2893
2894 for_each_sg(sglist, s, nelems, i) {
2895 __unmap_single(domain->priv, s->dma_address,
2896 s->dma_length, dir);
2897 s->dma_address = s->dma_length = 0;
2898 }
2899
2900 domain_flush_complete(domain);
2901
2902 spin_unlock_irqrestore(&domain->lock, flags);
2903 }
2904
2905 /*
2906 * The exported alloc_coherent function for dma_ops.
2907 */
2908 static void *alloc_coherent(struct device *dev, size_t size,
2909 dma_addr_t *dma_addr, gfp_t flag,
2910 struct dma_attrs *attrs)
2911 {
2912 u64 dma_mask = dev->coherent_dma_mask;
2913 struct protection_domain *domain;
2914 unsigned long flags;
2915 struct page *page;
2916
2917 INC_STATS_COUNTER(cnt_alloc_coherent);
2918
2919 domain = get_domain(dev);
2920 if (PTR_ERR(domain) == -EINVAL) {
2921 page = alloc_pages(flag, get_order(size));
2922 *dma_addr = page_to_phys(page);
2923 return page_address(page);
2924 } else if (IS_ERR(domain))
2925 return NULL;
2926
2927 size = PAGE_ALIGN(size);
2928 dma_mask = dev->coherent_dma_mask;
2929 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
2930
2931 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2932 if (!page) {
2933 if (!(flag & __GFP_WAIT))
2934 return NULL;
2935
2936 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2937 get_order(size));
2938 if (!page)
2939 return NULL;
2940 }
2941
2942 if (!dma_mask)
2943 dma_mask = *dev->dma_mask;
2944
2945 spin_lock_irqsave(&domain->lock, flags);
2946
2947 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
2948 size, DMA_BIDIRECTIONAL, true, dma_mask);
2949
2950 if (*dma_addr == DMA_ERROR_CODE) {
2951 spin_unlock_irqrestore(&domain->lock, flags);
2952 goto out_free;
2953 }
2954
2955 domain_flush_complete(domain);
2956
2957 spin_unlock_irqrestore(&domain->lock, flags);
2958
2959 return page_address(page);
2960
2961 out_free:
2962
2963 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2964 __free_pages(page, get_order(size));
2965
2966 return NULL;
2967 }
2968
2969 /*
2970 * The exported free_coherent function for dma_ops.
2971 */
2972 static void free_coherent(struct device *dev, size_t size,
2973 void *virt_addr, dma_addr_t dma_addr,
2974 struct dma_attrs *attrs)
2975 {
2976 struct protection_domain *domain;
2977 unsigned long flags;
2978 struct page *page;
2979
2980 INC_STATS_COUNTER(cnt_free_coherent);
2981
2982 page = virt_to_page(virt_addr);
2983 size = PAGE_ALIGN(size);
2984
2985 domain = get_domain(dev);
2986 if (IS_ERR(domain))
2987 goto free_mem;
2988
2989 spin_lock_irqsave(&domain->lock, flags);
2990
2991 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
2992
2993 domain_flush_complete(domain);
2994
2995 spin_unlock_irqrestore(&domain->lock, flags);
2996
2997 free_mem:
2998 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2999 __free_pages(page, get_order(size));
3000 }
3001
3002 /*
3003 * This function is called by the DMA layer to find out if we can handle a
3004 * particular device. It is part of the dma_ops.
3005 */
3006 static int amd_iommu_dma_supported(struct device *dev, u64 mask)
3007 {
3008 return check_device(dev);
3009 }
3010
3011 /*
3012 * The function for pre-allocating protection domains.
3013 *
3014 * If the driver core informs the DMA layer if a driver grabs a device
3015 * we don't need to preallocate the protection domains anymore.
3016 * For now we have to.
3017 */
3018 static void __init prealloc_protection_domains(void)
3019 {
3020 struct iommu_dev_data *dev_data;
3021 struct dma_ops_domain *dma_dom;
3022 struct pci_dev *dev = NULL;
3023 u16 devid;
3024
3025 for_each_pci_dev(dev) {
3026
3027 /* Do we handle this device? */
3028 if (!check_device(&dev->dev))
3029 continue;
3030
3031 dev_data = get_dev_data(&dev->dev);
3032 if (!amd_iommu_force_isolation && dev_data->iommu_v2) {
3033 /* Make sure passthrough domain is allocated */
3034 alloc_passthrough_domain();
3035 dev_data->passthrough = true;
3036 attach_device(&dev->dev, pt_domain);
3037 pr_info("AMD-Vi: Using passthrough domain for device %s\n",
3038 dev_name(&dev->dev));
3039 }
3040
3041 /* Is there already any domain for it? */
3042 if (domain_for_device(&dev->dev))
3043 continue;
3044
3045 devid = get_device_id(&dev->dev);
3046
3047 dma_dom = dma_ops_domain_alloc();
3048 if (!dma_dom)
3049 continue;
3050 init_unity_mappings_for_device(dma_dom, devid);
3051 dma_dom->target_dev = devid;
3052
3053 attach_device(&dev->dev, &dma_dom->domain);
3054
3055 list_add_tail(&dma_dom->list, &iommu_pd_list);
3056 }
3057 }
3058
3059 static struct dma_map_ops amd_iommu_dma_ops = {
3060 .alloc = alloc_coherent,
3061 .free = free_coherent,
3062 .map_page = map_page,
3063 .unmap_page = unmap_page,
3064 .map_sg = map_sg,
3065 .unmap_sg = unmap_sg,
3066 .dma_supported = amd_iommu_dma_supported,
3067 };
3068
3069 static unsigned device_dma_ops_init(void)
3070 {
3071 struct iommu_dev_data *dev_data;
3072 struct pci_dev *pdev = NULL;
3073 unsigned unhandled = 0;
3074
3075 for_each_pci_dev(pdev) {
3076 if (!check_device(&pdev->dev)) {
3077
3078 iommu_ignore_device(&pdev->dev);
3079
3080 unhandled += 1;
3081 continue;
3082 }
3083
3084 dev_data = get_dev_data(&pdev->dev);
3085
3086 if (!dev_data->passthrough)
3087 pdev->dev.archdata.dma_ops = &amd_iommu_dma_ops;
3088 else
3089 pdev->dev.archdata.dma_ops = &nommu_dma_ops;
3090 }
3091
3092 return unhandled;
3093 }
3094
3095 /*
3096 * The function which clues the AMD IOMMU driver into dma_ops.
3097 */
3098
3099 void __init amd_iommu_init_api(void)
3100 {
3101 bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
3102 }
3103
3104 int __init amd_iommu_init_dma_ops(void)
3105 {
3106 struct amd_iommu *iommu;
3107 int ret, unhandled;
3108
3109 /*
3110 * first allocate a default protection domain for every IOMMU we
3111 * found in the system. Devices not assigned to any other
3112 * protection domain will be assigned to the default one.
3113 */
3114 for_each_iommu(iommu) {
3115 iommu->default_dom = dma_ops_domain_alloc();
3116 if (iommu->default_dom == NULL)
3117 return -ENOMEM;
3118 iommu->default_dom->domain.flags |= PD_DEFAULT_MASK;
3119 ret = iommu_init_unity_mappings(iommu);
3120 if (ret)
3121 goto free_domains;
3122 }
3123
3124 /*
3125 * Pre-allocate the protection domains for each device.
3126 */
3127 prealloc_protection_domains();
3128
3129 iommu_detected = 1;
3130 swiotlb = 0;
3131
3132 /* Make the driver finally visible to the drivers */
3133 unhandled = device_dma_ops_init();
3134 if (unhandled && max_pfn > MAX_DMA32_PFN) {
3135 /* There are unhandled devices - initialize swiotlb for them */
3136 swiotlb = 1;
3137 }
3138
3139 amd_iommu_stats_init();
3140
3141 if (amd_iommu_unmap_flush)
3142 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
3143 else
3144 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
3145
3146 return 0;
3147
3148 free_domains:
3149
3150 for_each_iommu(iommu) {
3151 dma_ops_domain_free(iommu->default_dom);
3152 }
3153
3154 return ret;
3155 }
3156
3157 /*****************************************************************************
3158 *
3159 * The following functions belong to the exported interface of AMD IOMMU
3160 *
3161 * This interface allows access to lower level functions of the IOMMU
3162 * like protection domain handling and assignement of devices to domains
3163 * which is not possible with the dma_ops interface.
3164 *
3165 *****************************************************************************/
3166
3167 static void cleanup_domain(struct protection_domain *domain)
3168 {
3169 struct iommu_dev_data *entry;
3170 unsigned long flags;
3171
3172 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3173
3174 while (!list_empty(&domain->dev_list)) {
3175 entry = list_first_entry(&domain->dev_list,
3176 struct iommu_dev_data, list);
3177 __detach_device(entry);
3178 }
3179
3180 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3181 }
3182
3183 static void protection_domain_free(struct protection_domain *domain)
3184 {
3185 if (!domain)
3186 return;
3187
3188 del_domain_from_list(domain);
3189
3190 if (domain->id)
3191 domain_id_free(domain->id);
3192
3193 kfree(domain);
3194 }
3195
3196 static struct protection_domain *protection_domain_alloc(void)
3197 {
3198 struct protection_domain *domain;
3199
3200 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
3201 if (!domain)
3202 return NULL;
3203
3204 spin_lock_init(&domain->lock);
3205 mutex_init(&domain->api_lock);
3206 domain->id = domain_id_alloc();
3207 if (!domain->id)
3208 goto out_err;
3209 INIT_LIST_HEAD(&domain->dev_list);
3210
3211 add_domain_to_list(domain);
3212
3213 return domain;
3214
3215 out_err:
3216 kfree(domain);
3217
3218 return NULL;
3219 }
3220
3221 static int __init alloc_passthrough_domain(void)
3222 {
3223 if (pt_domain != NULL)
3224 return 0;
3225
3226 /* allocate passthrough domain */
3227 pt_domain = protection_domain_alloc();
3228 if (!pt_domain)
3229 return -ENOMEM;
3230
3231 pt_domain->mode = PAGE_MODE_NONE;
3232
3233 return 0;
3234 }
3235 static int amd_iommu_domain_init(struct iommu_domain *dom)
3236 {
3237 struct protection_domain *domain;
3238
3239 domain = protection_domain_alloc();
3240 if (!domain)
3241 goto out_free;
3242
3243 domain->mode = PAGE_MODE_3_LEVEL;
3244 domain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
3245 if (!domain->pt_root)
3246 goto out_free;
3247
3248 domain->iommu_domain = dom;
3249
3250 dom->priv = domain;
3251
3252 dom->geometry.aperture_start = 0;
3253 dom->geometry.aperture_end = ~0ULL;
3254 dom->geometry.force_aperture = true;
3255
3256 return 0;
3257
3258 out_free:
3259 protection_domain_free(domain);
3260
3261 return -ENOMEM;
3262 }
3263
3264 static void amd_iommu_domain_destroy(struct iommu_domain *dom)
3265 {
3266 struct protection_domain *domain = dom->priv;
3267
3268 if (!domain)
3269 return;
3270
3271 if (domain->dev_cnt > 0)
3272 cleanup_domain(domain);
3273
3274 BUG_ON(domain->dev_cnt != 0);
3275
3276 if (domain->mode != PAGE_MODE_NONE)
3277 free_pagetable(domain);
3278
3279 if (domain->flags & PD_IOMMUV2_MASK)
3280 free_gcr3_table(domain);
3281
3282 protection_domain_free(domain);
3283
3284 dom->priv = NULL;
3285 }
3286
3287 static void amd_iommu_detach_device(struct iommu_domain *dom,
3288 struct device *dev)
3289 {
3290 struct iommu_dev_data *dev_data = dev->archdata.iommu;
3291 struct amd_iommu *iommu;
3292 u16 devid;
3293
3294 if (!check_device(dev))
3295 return;
3296
3297 devid = get_device_id(dev);
3298
3299 if (dev_data->domain != NULL)
3300 detach_device(dev);
3301
3302 iommu = amd_iommu_rlookup_table[devid];
3303 if (!iommu)
3304 return;
3305
3306 iommu_completion_wait(iommu);
3307 }
3308
3309 static int amd_iommu_attach_device(struct iommu_domain *dom,
3310 struct device *dev)
3311 {
3312 struct protection_domain *domain = dom->priv;
3313 struct iommu_dev_data *dev_data;
3314 struct amd_iommu *iommu;
3315 int ret;
3316
3317 if (!check_device(dev))
3318 return -EINVAL;
3319
3320 dev_data = dev->archdata.iommu;
3321
3322 iommu = amd_iommu_rlookup_table[dev_data->devid];
3323 if (!iommu)
3324 return -EINVAL;
3325
3326 if (dev_data->domain)
3327 detach_device(dev);
3328
3329 ret = attach_device(dev, domain);
3330
3331 iommu_completion_wait(iommu);
3332
3333 return ret;
3334 }
3335
3336 static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
3337 phys_addr_t paddr, size_t page_size, int iommu_prot)
3338 {
3339 struct protection_domain *domain = dom->priv;
3340 int prot = 0;
3341 int ret;
3342
3343 if (domain->mode == PAGE_MODE_NONE)
3344 return -EINVAL;
3345
3346 if (iommu_prot & IOMMU_READ)
3347 prot |= IOMMU_PROT_IR;
3348 if (iommu_prot & IOMMU_WRITE)
3349 prot |= IOMMU_PROT_IW;
3350
3351 mutex_lock(&domain->api_lock);
3352 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
3353 mutex_unlock(&domain->api_lock);
3354
3355 return ret;
3356 }
3357
3358 static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3359 size_t page_size)
3360 {
3361 struct protection_domain *domain = dom->priv;
3362 size_t unmap_size;
3363
3364 if (domain->mode == PAGE_MODE_NONE)
3365 return -EINVAL;
3366
3367 mutex_lock(&domain->api_lock);
3368 unmap_size = iommu_unmap_page(domain, iova, page_size);
3369 mutex_unlock(&domain->api_lock);
3370
3371 domain_flush_tlb_pde(domain);
3372
3373 return unmap_size;
3374 }
3375
3376 static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
3377 dma_addr_t iova)
3378 {
3379 struct protection_domain *domain = dom->priv;
3380 unsigned long offset_mask, pte_pgsize;
3381 u64 *pte, __pte;
3382
3383 if (domain->mode == PAGE_MODE_NONE)
3384 return iova;
3385
3386 pte = fetch_pte(domain, iova, &pte_pgsize);
3387
3388 if (!pte || !IOMMU_PTE_PRESENT(*pte))
3389 return 0;
3390
3391 offset_mask = pte_pgsize - 1;
3392 __pte = *pte & PM_ADDR_MASK;
3393
3394 return (__pte & ~offset_mask) | (iova & offset_mask);
3395 }
3396
3397 static bool amd_iommu_capable(enum iommu_cap cap)
3398 {
3399 switch (cap) {
3400 case IOMMU_CAP_CACHE_COHERENCY:
3401 return true;
3402 case IOMMU_CAP_INTR_REMAP:
3403 return (irq_remapping_enabled == 1);
3404 case IOMMU_CAP_NOEXEC:
3405 return false;
3406 }
3407
3408 return false;
3409 }
3410
3411 static const struct iommu_ops amd_iommu_ops = {
3412 .capable = amd_iommu_capable,
3413 .domain_init = amd_iommu_domain_init,
3414 .domain_destroy = amd_iommu_domain_destroy,
3415 .attach_dev = amd_iommu_attach_device,
3416 .detach_dev = amd_iommu_detach_device,
3417 .map = amd_iommu_map,
3418 .unmap = amd_iommu_unmap,
3419 .map_sg = default_iommu_map_sg,
3420 .iova_to_phys = amd_iommu_iova_to_phys,
3421 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
3422 };
3423
3424 /*****************************************************************************
3425 *
3426 * The next functions do a basic initialization of IOMMU for pass through
3427 * mode
3428 *
3429 * In passthrough mode the IOMMU is initialized and enabled but not used for
3430 * DMA-API translation.
3431 *
3432 *****************************************************************************/
3433
3434 int __init amd_iommu_init_passthrough(void)
3435 {
3436 struct iommu_dev_data *dev_data;
3437 struct pci_dev *dev = NULL;
3438 int ret;
3439
3440 ret = alloc_passthrough_domain();
3441 if (ret)
3442 return ret;
3443
3444 for_each_pci_dev(dev) {
3445 if (!check_device(&dev->dev))
3446 continue;
3447
3448 dev_data = get_dev_data(&dev->dev);
3449 dev_data->passthrough = true;
3450
3451 attach_device(&dev->dev, pt_domain);
3452 }
3453
3454 amd_iommu_stats_init();
3455
3456 pr_info("AMD-Vi: Initialized for Passthrough Mode\n");
3457
3458 return 0;
3459 }
3460
3461 /* IOMMUv2 specific functions */
3462 int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3463 {
3464 return atomic_notifier_chain_register(&ppr_notifier, nb);
3465 }
3466 EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3467
3468 int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3469 {
3470 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3471 }
3472 EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
3473
3474 void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3475 {
3476 struct protection_domain *domain = dom->priv;
3477 unsigned long flags;
3478
3479 spin_lock_irqsave(&domain->lock, flags);
3480
3481 /* Update data structure */
3482 domain->mode = PAGE_MODE_NONE;
3483 domain->updated = true;
3484
3485 /* Make changes visible to IOMMUs */
3486 update_domain(domain);
3487
3488 /* Page-table is not visible to IOMMU anymore, so free it */
3489 free_pagetable(domain);
3490
3491 spin_unlock_irqrestore(&domain->lock, flags);
3492 }
3493 EXPORT_SYMBOL(amd_iommu_domain_direct_map);
3494
3495 int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3496 {
3497 struct protection_domain *domain = dom->priv;
3498 unsigned long flags;
3499 int levels, ret;
3500
3501 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3502 return -EINVAL;
3503
3504 /* Number of GCR3 table levels required */
3505 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3506 levels += 1;
3507
3508 if (levels > amd_iommu_max_glx_val)
3509 return -EINVAL;
3510
3511 spin_lock_irqsave(&domain->lock, flags);
3512
3513 /*
3514 * Save us all sanity checks whether devices already in the
3515 * domain support IOMMUv2. Just force that the domain has no
3516 * devices attached when it is switched into IOMMUv2 mode.
3517 */
3518 ret = -EBUSY;
3519 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3520 goto out;
3521
3522 ret = -ENOMEM;
3523 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3524 if (domain->gcr3_tbl == NULL)
3525 goto out;
3526
3527 domain->glx = levels;
3528 domain->flags |= PD_IOMMUV2_MASK;
3529 domain->updated = true;
3530
3531 update_domain(domain);
3532
3533 ret = 0;
3534
3535 out:
3536 spin_unlock_irqrestore(&domain->lock, flags);
3537
3538 return ret;
3539 }
3540 EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
3541
3542 static int __flush_pasid(struct protection_domain *domain, int pasid,
3543 u64 address, bool size)
3544 {
3545 struct iommu_dev_data *dev_data;
3546 struct iommu_cmd cmd;
3547 int i, ret;
3548
3549 if (!(domain->flags & PD_IOMMUV2_MASK))
3550 return -EINVAL;
3551
3552 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3553
3554 /*
3555 * IOMMU TLB needs to be flushed before Device TLB to
3556 * prevent device TLB refill from IOMMU TLB
3557 */
3558 for (i = 0; i < amd_iommus_present; ++i) {
3559 if (domain->dev_iommu[i] == 0)
3560 continue;
3561
3562 ret = iommu_queue_command(amd_iommus[i], &cmd);
3563 if (ret != 0)
3564 goto out;
3565 }
3566
3567 /* Wait until IOMMU TLB flushes are complete */
3568 domain_flush_complete(domain);
3569
3570 /* Now flush device TLBs */
3571 list_for_each_entry(dev_data, &domain->dev_list, list) {
3572 struct amd_iommu *iommu;
3573 int qdep;
3574
3575 BUG_ON(!dev_data->ats.enabled);
3576
3577 qdep = dev_data->ats.qdep;
3578 iommu = amd_iommu_rlookup_table[dev_data->devid];
3579
3580 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3581 qdep, address, size);
3582
3583 ret = iommu_queue_command(iommu, &cmd);
3584 if (ret != 0)
3585 goto out;
3586 }
3587
3588 /* Wait until all device TLBs are flushed */
3589 domain_flush_complete(domain);
3590
3591 ret = 0;
3592
3593 out:
3594
3595 return ret;
3596 }
3597
3598 static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3599 u64 address)
3600 {
3601 INC_STATS_COUNTER(invalidate_iotlb);
3602
3603 return __flush_pasid(domain, pasid, address, false);
3604 }
3605
3606 int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3607 u64 address)
3608 {
3609 struct protection_domain *domain = dom->priv;
3610 unsigned long flags;
3611 int ret;
3612
3613 spin_lock_irqsave(&domain->lock, flags);
3614 ret = __amd_iommu_flush_page(domain, pasid, address);
3615 spin_unlock_irqrestore(&domain->lock, flags);
3616
3617 return ret;
3618 }
3619 EXPORT_SYMBOL(amd_iommu_flush_page);
3620
3621 static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3622 {
3623 INC_STATS_COUNTER(invalidate_iotlb_all);
3624
3625 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3626 true);
3627 }
3628
3629 int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3630 {
3631 struct protection_domain *domain = dom->priv;
3632 unsigned long flags;
3633 int ret;
3634
3635 spin_lock_irqsave(&domain->lock, flags);
3636 ret = __amd_iommu_flush_tlb(domain, pasid);
3637 spin_unlock_irqrestore(&domain->lock, flags);
3638
3639 return ret;
3640 }
3641 EXPORT_SYMBOL(amd_iommu_flush_tlb);
3642
3643 static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3644 {
3645 int index;
3646 u64 *pte;
3647
3648 while (true) {
3649
3650 index = (pasid >> (9 * level)) & 0x1ff;
3651 pte = &root[index];
3652
3653 if (level == 0)
3654 break;
3655
3656 if (!(*pte & GCR3_VALID)) {
3657 if (!alloc)
3658 return NULL;
3659
3660 root = (void *)get_zeroed_page(GFP_ATOMIC);
3661 if (root == NULL)
3662 return NULL;
3663
3664 *pte = __pa(root) | GCR3_VALID;
3665 }
3666
3667 root = __va(*pte & PAGE_MASK);
3668
3669 level -= 1;
3670 }
3671
3672 return pte;
3673 }
3674
3675 static int __set_gcr3(struct protection_domain *domain, int pasid,
3676 unsigned long cr3)
3677 {
3678 u64 *pte;
3679
3680 if (domain->mode != PAGE_MODE_NONE)
3681 return -EINVAL;
3682
3683 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3684 if (pte == NULL)
3685 return -ENOMEM;
3686
3687 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3688
3689 return __amd_iommu_flush_tlb(domain, pasid);
3690 }
3691
3692 static int __clear_gcr3(struct protection_domain *domain, int pasid)
3693 {
3694 u64 *pte;
3695
3696 if (domain->mode != PAGE_MODE_NONE)
3697 return -EINVAL;
3698
3699 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3700 if (pte == NULL)
3701 return 0;
3702
3703 *pte = 0;
3704
3705 return __amd_iommu_flush_tlb(domain, pasid);
3706 }
3707
3708 int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3709 unsigned long cr3)
3710 {
3711 struct protection_domain *domain = dom->priv;
3712 unsigned long flags;
3713 int ret;
3714
3715 spin_lock_irqsave(&domain->lock, flags);
3716 ret = __set_gcr3(domain, pasid, cr3);
3717 spin_unlock_irqrestore(&domain->lock, flags);
3718
3719 return ret;
3720 }
3721 EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3722
3723 int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3724 {
3725 struct protection_domain *domain = dom->priv;
3726 unsigned long flags;
3727 int ret;
3728
3729 spin_lock_irqsave(&domain->lock, flags);
3730 ret = __clear_gcr3(domain, pasid);
3731 spin_unlock_irqrestore(&domain->lock, flags);
3732
3733 return ret;
3734 }
3735 EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
3736
3737 int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3738 int status, int tag)
3739 {
3740 struct iommu_dev_data *dev_data;
3741 struct amd_iommu *iommu;
3742 struct iommu_cmd cmd;
3743
3744 INC_STATS_COUNTER(complete_ppr);
3745
3746 dev_data = get_dev_data(&pdev->dev);
3747 iommu = amd_iommu_rlookup_table[dev_data->devid];
3748
3749 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3750 tag, dev_data->pri_tlp);
3751
3752 return iommu_queue_command(iommu, &cmd);
3753 }
3754 EXPORT_SYMBOL(amd_iommu_complete_ppr);
3755
3756 struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3757 {
3758 struct protection_domain *domain;
3759
3760 domain = get_domain(&pdev->dev);
3761 if (IS_ERR(domain))
3762 return NULL;
3763
3764 /* Only return IOMMUv2 domains */
3765 if (!(domain->flags & PD_IOMMUV2_MASK))
3766 return NULL;
3767
3768 return domain->iommu_domain;
3769 }
3770 EXPORT_SYMBOL(amd_iommu_get_v2_domain);
3771
3772 void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3773 {
3774 struct iommu_dev_data *dev_data;
3775
3776 if (!amd_iommu_v2_supported())
3777 return;
3778
3779 dev_data = get_dev_data(&pdev->dev);
3780 dev_data->errata |= (1 << erratum);
3781 }
3782 EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
3783
3784 int amd_iommu_device_info(struct pci_dev *pdev,
3785 struct amd_iommu_device_info *info)
3786 {
3787 int max_pasids;
3788 int pos;
3789
3790 if (pdev == NULL || info == NULL)
3791 return -EINVAL;
3792
3793 if (!amd_iommu_v2_supported())
3794 return -EINVAL;
3795
3796 memset(info, 0, sizeof(*info));
3797
3798 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3799 if (pos)
3800 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3801
3802 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3803 if (pos)
3804 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3805
3806 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3807 if (pos) {
3808 int features;
3809
3810 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3811 max_pasids = min(max_pasids, (1 << 20));
3812
3813 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3814 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3815
3816 features = pci_pasid_features(pdev);
3817 if (features & PCI_PASID_CAP_EXEC)
3818 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3819 if (features & PCI_PASID_CAP_PRIV)
3820 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3821 }
3822
3823 return 0;
3824 }
3825 EXPORT_SYMBOL(amd_iommu_device_info);
3826
3827 #ifdef CONFIG_IRQ_REMAP
3828
3829 /*****************************************************************************
3830 *
3831 * Interrupt Remapping Implementation
3832 *
3833 *****************************************************************************/
3834
3835 union irte {
3836 u32 val;
3837 struct {
3838 u32 valid : 1,
3839 no_fault : 1,
3840 int_type : 3,
3841 rq_eoi : 1,
3842 dm : 1,
3843 rsvd_1 : 1,
3844 destination : 8,
3845 vector : 8,
3846 rsvd_2 : 8;
3847 } fields;
3848 };
3849
3850 #define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3851 #define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3852 #define DTE_IRQ_TABLE_LEN (8ULL << 1)
3853 #define DTE_IRQ_REMAP_ENABLE 1ULL
3854
3855 static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3856 {
3857 u64 dte;
3858
3859 dte = amd_iommu_dev_table[devid].data[2];
3860 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3861 dte |= virt_to_phys(table->table);
3862 dte |= DTE_IRQ_REMAP_INTCTL;
3863 dte |= DTE_IRQ_TABLE_LEN;
3864 dte |= DTE_IRQ_REMAP_ENABLE;
3865
3866 amd_iommu_dev_table[devid].data[2] = dte;
3867 }
3868
3869 #define IRTE_ALLOCATED (~1U)
3870
3871 static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3872 {
3873 struct irq_remap_table *table = NULL;
3874 struct amd_iommu *iommu;
3875 unsigned long flags;
3876 u16 alias;
3877
3878 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3879
3880 iommu = amd_iommu_rlookup_table[devid];
3881 if (!iommu)
3882 goto out_unlock;
3883
3884 table = irq_lookup_table[devid];
3885 if (table)
3886 goto out;
3887
3888 alias = amd_iommu_alias_table[devid];
3889 table = irq_lookup_table[alias];
3890 if (table) {
3891 irq_lookup_table[devid] = table;
3892 set_dte_irq_entry(devid, table);
3893 iommu_flush_dte(iommu, devid);
3894 goto out;
3895 }
3896
3897 /* Nothing there yet, allocate new irq remapping table */
3898 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3899 if (!table)
3900 goto out;
3901
3902 /* Initialize table spin-lock */
3903 spin_lock_init(&table->lock);
3904
3905 if (ioapic)
3906 /* Keep the first 32 indexes free for IOAPIC interrupts */
3907 table->min_index = 32;
3908
3909 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3910 if (!table->table) {
3911 kfree(table);
3912 table = NULL;
3913 goto out;
3914 }
3915
3916 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3917
3918 if (ioapic) {
3919 int i;
3920
3921 for (i = 0; i < 32; ++i)
3922 table->table[i] = IRTE_ALLOCATED;
3923 }
3924
3925 irq_lookup_table[devid] = table;
3926 set_dte_irq_entry(devid, table);
3927 iommu_flush_dte(iommu, devid);
3928 if (devid != alias) {
3929 irq_lookup_table[alias] = table;
3930 set_dte_irq_entry(alias, table);
3931 iommu_flush_dte(iommu, alias);
3932 }
3933
3934 out:
3935 iommu_completion_wait(iommu);
3936
3937 out_unlock:
3938 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3939
3940 return table;
3941 }
3942
3943 static int alloc_irq_index(struct irq_cfg *cfg, u16 devid, int count)
3944 {
3945 struct irq_remap_table *table;
3946 unsigned long flags;
3947 int index, c;
3948
3949 table = get_irq_table(devid, false);
3950 if (!table)
3951 return -ENODEV;
3952
3953 spin_lock_irqsave(&table->lock, flags);
3954
3955 /* Scan table for free entries */
3956 for (c = 0, index = table->min_index;
3957 index < MAX_IRQS_PER_TABLE;
3958 ++index) {
3959 if (table->table[index] == 0)
3960 c += 1;
3961 else
3962 c = 0;
3963
3964 if (c == count) {
3965 struct irq_2_irte *irte_info;
3966
3967 for (; c != 0; --c)
3968 table->table[index - c + 1] = IRTE_ALLOCATED;
3969
3970 index -= count - 1;
3971
3972 cfg->remapped = 1;
3973 irte_info = &cfg->irq_2_irte;
3974 irte_info->devid = devid;
3975 irte_info->index = index;
3976
3977 goto out;
3978 }
3979 }
3980
3981 index = -ENOSPC;
3982
3983 out:
3984 spin_unlock_irqrestore(&table->lock, flags);
3985
3986 return index;
3987 }
3988
3989 static int get_irte(u16 devid, int index, union irte *irte)
3990 {
3991 struct irq_remap_table *table;
3992 unsigned long flags;
3993
3994 table = get_irq_table(devid, false);
3995 if (!table)
3996 return -ENOMEM;
3997
3998 spin_lock_irqsave(&table->lock, flags);
3999 irte->val = table->table[index];
4000 spin_unlock_irqrestore(&table->lock, flags);
4001
4002 return 0;
4003 }
4004
4005 static int modify_irte(u16 devid, int index, union irte irte)
4006 {
4007 struct irq_remap_table *table;
4008 struct amd_iommu *iommu;
4009 unsigned long flags;
4010
4011 iommu = amd_iommu_rlookup_table[devid];
4012 if (iommu == NULL)
4013 return -EINVAL;
4014
4015 table = get_irq_table(devid, false);
4016 if (!table)
4017 return -ENOMEM;
4018
4019 spin_lock_irqsave(&table->lock, flags);
4020 table->table[index] = irte.val;
4021 spin_unlock_irqrestore(&table->lock, flags);
4022
4023 iommu_flush_irt(iommu, devid);
4024 iommu_completion_wait(iommu);
4025
4026 return 0;
4027 }
4028
4029 static void free_irte(u16 devid, int index)
4030 {
4031 struct irq_remap_table *table;
4032 struct amd_iommu *iommu;
4033 unsigned long flags;
4034
4035 iommu = amd_iommu_rlookup_table[devid];
4036 if (iommu == NULL)
4037 return;
4038
4039 table = get_irq_table(devid, false);
4040 if (!table)
4041 return;
4042
4043 spin_lock_irqsave(&table->lock, flags);
4044 table->table[index] = 0;
4045 spin_unlock_irqrestore(&table->lock, flags);
4046
4047 iommu_flush_irt(iommu, devid);
4048 iommu_completion_wait(iommu);
4049 }
4050
4051 static int setup_ioapic_entry(int irq, struct IO_APIC_route_entry *entry,
4052 unsigned int destination, int vector,
4053 struct io_apic_irq_attr *attr)
4054 {
4055 struct irq_remap_table *table;
4056 struct irq_2_irte *irte_info;
4057 struct irq_cfg *cfg;
4058 union irte irte;
4059 int ioapic_id;
4060 int index;
4061 int devid;
4062 int ret;
4063
4064 cfg = irq_cfg(irq);
4065 if (!cfg)
4066 return -EINVAL;
4067
4068 irte_info = &cfg->irq_2_irte;
4069 ioapic_id = mpc_ioapic_id(attr->ioapic);
4070 devid = get_ioapic_devid(ioapic_id);
4071
4072 if (devid < 0)
4073 return devid;
4074
4075 table = get_irq_table(devid, true);
4076 if (table == NULL)
4077 return -ENOMEM;
4078
4079 index = attr->ioapic_pin;
4080
4081 /* Setup IRQ remapping info */
4082 cfg->remapped = 1;
4083 irte_info->devid = devid;
4084 irte_info->index = index;
4085
4086 /* Setup IRTE for IOMMU */
4087 irte.val = 0;
4088 irte.fields.vector = vector;
4089 irte.fields.int_type = apic->irq_delivery_mode;
4090 irte.fields.destination = destination;
4091 irte.fields.dm = apic->irq_dest_mode;
4092 irte.fields.valid = 1;
4093
4094 ret = modify_irte(devid, index, irte);
4095 if (ret)
4096 return ret;
4097
4098 /* Setup IOAPIC entry */
4099 memset(entry, 0, sizeof(*entry));
4100
4101 entry->vector = index;
4102 entry->mask = 0;
4103 entry->trigger = attr->trigger;
4104 entry->polarity = attr->polarity;
4105
4106 /*
4107 * Mask level triggered irqs.
4108 */
4109 if (attr->trigger)
4110 entry->mask = 1;
4111
4112 return 0;
4113 }
4114
4115 static int set_affinity(struct irq_data *data, const struct cpumask *mask,
4116 bool force)
4117 {
4118 struct irq_2_irte *irte_info;
4119 unsigned int dest, irq;
4120 struct irq_cfg *cfg;
4121 union irte irte;
4122 int err;
4123
4124 if (!config_enabled(CONFIG_SMP))
4125 return -1;
4126
4127 cfg = irqd_cfg(data);
4128 irq = data->irq;
4129 irte_info = &cfg->irq_2_irte;
4130
4131 if (!cpumask_intersects(mask, cpu_online_mask))
4132 return -EINVAL;
4133
4134 if (get_irte(irte_info->devid, irte_info->index, &irte))
4135 return -EBUSY;
4136
4137 if (assign_irq_vector(irq, cfg, mask))
4138 return -EBUSY;
4139
4140 err = apic->cpu_mask_to_apicid_and(cfg->domain, mask, &dest);
4141 if (err) {
4142 if (assign_irq_vector(irq, cfg, data->affinity))
4143 pr_err("AMD-Vi: Failed to recover vector for irq %d\n", irq);
4144 return err;
4145 }
4146
4147 irte.fields.vector = cfg->vector;
4148 irte.fields.destination = dest;
4149
4150 modify_irte(irte_info->devid, irte_info->index, irte);
4151
4152 if (cfg->move_in_progress)
4153 send_cleanup_vector(cfg);
4154
4155 cpumask_copy(data->affinity, mask);
4156
4157 return 0;
4158 }
4159
4160 static int free_irq(int irq)
4161 {
4162 struct irq_2_irte *irte_info;
4163 struct irq_cfg *cfg;
4164
4165 cfg = irq_cfg(irq);
4166 if (!cfg)
4167 return -EINVAL;
4168
4169 irte_info = &cfg->irq_2_irte;
4170
4171 free_irte(irte_info->devid, irte_info->index);
4172
4173 return 0;
4174 }
4175
4176 static void compose_msi_msg(struct pci_dev *pdev,
4177 unsigned int irq, unsigned int dest,
4178 struct msi_msg *msg, u8 hpet_id)
4179 {
4180 struct irq_2_irte *irte_info;
4181 struct irq_cfg *cfg;
4182 union irte irte;
4183
4184 cfg = irq_cfg(irq);
4185 if (!cfg)
4186 return;
4187
4188 irte_info = &cfg->irq_2_irte;
4189
4190 irte.val = 0;
4191 irte.fields.vector = cfg->vector;
4192 irte.fields.int_type = apic->irq_delivery_mode;
4193 irte.fields.destination = dest;
4194 irte.fields.dm = apic->irq_dest_mode;
4195 irte.fields.valid = 1;
4196
4197 modify_irte(irte_info->devid, irte_info->index, irte);
4198
4199 msg->address_hi = MSI_ADDR_BASE_HI;
4200 msg->address_lo = MSI_ADDR_BASE_LO;
4201 msg->data = irte_info->index;
4202 }
4203
4204 static int msi_alloc_irq(struct pci_dev *pdev, int irq, int nvec)
4205 {
4206 struct irq_cfg *cfg;
4207 int index;
4208 u16 devid;
4209
4210 if (!pdev)
4211 return -EINVAL;
4212
4213 cfg = irq_cfg(irq);
4214 if (!cfg)
4215 return -EINVAL;
4216
4217 devid = get_device_id(&pdev->dev);
4218 index = alloc_irq_index(cfg, devid, nvec);
4219
4220 return index < 0 ? MAX_IRQS_PER_TABLE : index;
4221 }
4222
4223 static int msi_setup_irq(struct pci_dev *pdev, unsigned int irq,
4224 int index, int offset)
4225 {
4226 struct irq_2_irte *irte_info;
4227 struct irq_cfg *cfg;
4228 u16 devid;
4229
4230 if (!pdev)
4231 return -EINVAL;
4232
4233 cfg = irq_cfg(irq);
4234 if (!cfg)
4235 return -EINVAL;
4236
4237 if (index >= MAX_IRQS_PER_TABLE)
4238 return 0;
4239
4240 devid = get_device_id(&pdev->dev);
4241 irte_info = &cfg->irq_2_irte;
4242
4243 cfg->remapped = 1;
4244 irte_info->devid = devid;
4245 irte_info->index = index + offset;
4246
4247 return 0;
4248 }
4249
4250 static int alloc_hpet_msi(unsigned int irq, unsigned int id)
4251 {
4252 struct irq_2_irte *irte_info;
4253 struct irq_cfg *cfg;
4254 int index, devid;
4255
4256 cfg = irq_cfg(irq);
4257 if (!cfg)
4258 return -EINVAL;
4259
4260 irte_info = &cfg->irq_2_irte;
4261 devid = get_hpet_devid(id);
4262 if (devid < 0)
4263 return devid;
4264
4265 index = alloc_irq_index(cfg, devid, 1);
4266 if (index < 0)
4267 return index;
4268
4269 cfg->remapped = 1;
4270 irte_info->devid = devid;
4271 irte_info->index = index;
4272
4273 return 0;
4274 }
4275
4276 struct irq_remap_ops amd_iommu_irq_ops = {
4277 .prepare = amd_iommu_prepare,
4278 .enable = amd_iommu_enable,
4279 .disable = amd_iommu_disable,
4280 .reenable = amd_iommu_reenable,
4281 .enable_faulting = amd_iommu_enable_faulting,
4282 .setup_ioapic_entry = setup_ioapic_entry,
4283 .set_affinity = set_affinity,
4284 .free_irq = free_irq,
4285 .compose_msi_msg = compose_msi_msg,
4286 .msi_alloc_irq = msi_alloc_irq,
4287 .msi_setup_irq = msi_setup_irq,
4288 .alloc_hpet_msi = alloc_hpet_msi,
4289 };
4290 #endif
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