2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/mem_encrypt.h>
33 #include <asm/pci-direct.h>
34 #include <asm/iommu.h>
36 #include <asm/x86_init.h>
37 #include <asm/iommu_table.h>
38 #include <asm/io_apic.h>
39 #include <asm/irq_remapping.h>
41 #include <linux/crash_dump.h>
42 #include "amd_iommu_proto.h"
43 #include "amd_iommu_types.h"
44 #include "irq_remapping.h"
47 * definitions for the ACPI scanning code
49 #define IVRS_HEADER_LENGTH 48
51 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
52 #define ACPI_IVMD_TYPE_ALL 0x20
53 #define ACPI_IVMD_TYPE 0x21
54 #define ACPI_IVMD_TYPE_RANGE 0x22
56 #define IVHD_DEV_ALL 0x01
57 #define IVHD_DEV_SELECT 0x02
58 #define IVHD_DEV_SELECT_RANGE_START 0x03
59 #define IVHD_DEV_RANGE_END 0x04
60 #define IVHD_DEV_ALIAS 0x42
61 #define IVHD_DEV_ALIAS_RANGE 0x43
62 #define IVHD_DEV_EXT_SELECT 0x46
63 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
64 #define IVHD_DEV_SPECIAL 0x48
65 #define IVHD_DEV_ACPI_HID 0xf0
67 #define UID_NOT_PRESENT 0
68 #define UID_IS_INTEGER 1
69 #define UID_IS_CHARACTER 2
71 #define IVHD_SPECIAL_IOAPIC 1
72 #define IVHD_SPECIAL_HPET 2
74 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
75 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
76 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
77 #define IVHD_FLAG_ISOC_EN_MASK 0x08
79 #define IVMD_FLAG_EXCL_RANGE 0x08
80 #define IVMD_FLAG_UNITY_MAP 0x01
82 #define ACPI_DEVFLAG_INITPASS 0x01
83 #define ACPI_DEVFLAG_EXTINT 0x02
84 #define ACPI_DEVFLAG_NMI 0x04
85 #define ACPI_DEVFLAG_SYSMGT1 0x10
86 #define ACPI_DEVFLAG_SYSMGT2 0x20
87 #define ACPI_DEVFLAG_LINT0 0x40
88 #define ACPI_DEVFLAG_LINT1 0x80
89 #define ACPI_DEVFLAG_ATSDIS 0x10000000
91 #define LOOP_TIMEOUT 100000
93 * ACPI table definitions
95 * These data structures are laid over the table to parse the important values
99 extern const struct iommu_ops amd_iommu_ops
;
102 * structure describing one IOMMU in the ACPI table. Typically followed by one
103 * or more ivhd_entrys.
116 /* Following only valid on IVHD type 11h and 40h */
117 u64 efr_reg
; /* Exact copy of MMIO_EXT_FEATURES */
119 } __attribute__((packed
));
122 * A device entry describing which devices a specific IOMMU translates and
123 * which requestor ids they use.
135 } __attribute__((packed
));
138 * An AMD IOMMU memory definition structure. It defines things like exclusion
139 * ranges for devices and regions that should be unity mapped.
150 } __attribute__((packed
));
153 bool amd_iommu_irq_remap __read_mostly
;
155 int amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_VAPIC
;
156 static int amd_iommu_xt_mode
= IRQ_REMAP_X2APIC_MODE
;
158 static bool amd_iommu_detected
;
159 static bool __initdata amd_iommu_disabled
;
160 static int amd_iommu_target_ivhd_type
;
162 u16 amd_iommu_last_bdf
; /* largest PCI device id we have
164 LIST_HEAD(amd_iommu_unity_map
); /* a list of required unity mappings
166 bool amd_iommu_unmap_flush
; /* if true, flush on every unmap */
168 LIST_HEAD(amd_iommu_list
); /* list of all AMD IOMMUs in the
171 /* Array to assign indices to IOMMUs*/
172 struct amd_iommu
*amd_iommus
[MAX_IOMMUS
];
174 /* Number of IOMMUs present in the system */
175 static int amd_iommus_present
;
177 /* IOMMUs have a non-present cache? */
178 bool amd_iommu_np_cache __read_mostly
;
179 bool amd_iommu_iotlb_sup __read_mostly
= true;
181 u32 amd_iommu_max_pasid __read_mostly
= ~0;
183 bool amd_iommu_v2_present __read_mostly
;
184 static bool amd_iommu_pc_present __read_mostly
;
186 bool amd_iommu_force_isolation __read_mostly
;
189 * List of protection domains - used during resume
191 LIST_HEAD(amd_iommu_pd_list
);
192 spinlock_t amd_iommu_pd_lock
;
195 * Pointer to the device table which is shared by all AMD IOMMUs
196 * it is indexed by the PCI device id or the HT unit id and contains
197 * information about the domain the device belongs to as well as the
198 * page table root pointer.
200 struct dev_table_entry
*amd_iommu_dev_table
;
202 * Pointer to a device table which the content of old device table
203 * will be copied to. It's only be used in kdump kernel.
205 static struct dev_table_entry
*old_dev_tbl_cpy
;
208 * The alias table is a driver specific data structure which contains the
209 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
210 * More than one device can share the same requestor id.
212 u16
*amd_iommu_alias_table
;
215 * The rlookup table is used to find the IOMMU which is responsible
216 * for a specific device. It is also indexed by the PCI device id.
218 struct amd_iommu
**amd_iommu_rlookup_table
;
219 EXPORT_SYMBOL(amd_iommu_rlookup_table
);
222 * This table is used to find the irq remapping table for a given device id
225 struct irq_remap_table
**irq_lookup_table
;
228 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
229 * to know which ones are already in use.
231 unsigned long *amd_iommu_pd_alloc_bitmap
;
233 static u32 dev_table_size
; /* size of the device table */
234 static u32 alias_table_size
; /* size of the alias table */
235 static u32 rlookup_table_size
; /* size if the rlookup table */
237 enum iommu_init_state
{
248 IOMMU_CMDLINE_DISABLED
,
251 /* Early ioapic and hpet maps from kernel command line */
252 #define EARLY_MAP_SIZE 4
253 static struct devid_map __initdata early_ioapic_map
[EARLY_MAP_SIZE
];
254 static struct devid_map __initdata early_hpet_map
[EARLY_MAP_SIZE
];
255 static struct acpihid_map_entry __initdata early_acpihid_map
[EARLY_MAP_SIZE
];
257 static int __initdata early_ioapic_map_size
;
258 static int __initdata early_hpet_map_size
;
259 static int __initdata early_acpihid_map_size
;
261 static bool __initdata cmdline_maps
;
263 static enum iommu_init_state init_state
= IOMMU_START_STATE
;
265 static int amd_iommu_enable_interrupts(void);
266 static int __init
iommu_go_to_state(enum iommu_init_state state
);
267 static void init_device_table_dma(void);
269 static bool amd_iommu_pre_enabled
= true;
271 bool translation_pre_enabled(struct amd_iommu
*iommu
)
273 return (iommu
->flags
& AMD_IOMMU_FLAG_TRANS_PRE_ENABLED
);
275 EXPORT_SYMBOL(translation_pre_enabled
);
277 static void clear_translation_pre_enabled(struct amd_iommu
*iommu
)
279 iommu
->flags
&= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED
;
282 static void init_translation_status(struct amd_iommu
*iommu
)
286 ctrl
= readq(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
287 if (ctrl
& (1<<CONTROL_IOMMU_EN
))
288 iommu
->flags
|= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED
;
291 static inline void update_last_devid(u16 devid
)
293 if (devid
> amd_iommu_last_bdf
)
294 amd_iommu_last_bdf
= devid
;
297 static inline unsigned long tbl_size(int entry_size
)
299 unsigned shift
= PAGE_SHIFT
+
300 get_order(((int)amd_iommu_last_bdf
+ 1) * entry_size
);
305 int amd_iommu_get_num_iommus(void)
307 return amd_iommus_present
;
310 /* Access to l1 and l2 indexed register spaces */
312 static u32
iommu_read_l1(struct amd_iommu
*iommu
, u16 l1
, u8 address
)
316 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16));
317 pci_read_config_dword(iommu
->dev
, 0xfc, &val
);
321 static void iommu_write_l1(struct amd_iommu
*iommu
, u16 l1
, u8 address
, u32 val
)
323 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16 | 1 << 31));
324 pci_write_config_dword(iommu
->dev
, 0xfc, val
);
325 pci_write_config_dword(iommu
->dev
, 0xf8, (address
| l1
<< 16));
328 static u32
iommu_read_l2(struct amd_iommu
*iommu
, u8 address
)
332 pci_write_config_dword(iommu
->dev
, 0xf0, address
);
333 pci_read_config_dword(iommu
->dev
, 0xf4, &val
);
337 static void iommu_write_l2(struct amd_iommu
*iommu
, u8 address
, u32 val
)
339 pci_write_config_dword(iommu
->dev
, 0xf0, (address
| 1 << 8));
340 pci_write_config_dword(iommu
->dev
, 0xf4, val
);
343 /****************************************************************************
345 * AMD IOMMU MMIO register space handling functions
347 * These functions are used to program the IOMMU device registers in
348 * MMIO space required for that driver.
350 ****************************************************************************/
353 * This function set the exclusion range in the IOMMU. DMA accesses to the
354 * exclusion range are passed through untranslated
356 static void iommu_set_exclusion_range(struct amd_iommu
*iommu
)
358 u64 start
= iommu
->exclusion_start
& PAGE_MASK
;
359 u64 limit
= (start
+ iommu
->exclusion_length
- 1) & PAGE_MASK
;
362 if (!iommu
->exclusion_start
)
365 entry
= start
| MMIO_EXCL_ENABLE_MASK
;
366 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_BASE_OFFSET
,
367 &entry
, sizeof(entry
));
370 memcpy_toio(iommu
->mmio_base
+ MMIO_EXCL_LIMIT_OFFSET
,
371 &entry
, sizeof(entry
));
374 /* Programs the physical address of the device table into the IOMMU hardware */
375 static void iommu_set_device_table(struct amd_iommu
*iommu
)
379 BUG_ON(iommu
->mmio_base
== NULL
);
381 entry
= iommu_virt_to_phys(amd_iommu_dev_table
);
382 entry
|= (dev_table_size
>> 12) - 1;
383 memcpy_toio(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
,
384 &entry
, sizeof(entry
));
387 /* Generic functions to enable/disable certain features of the IOMMU. */
388 static void iommu_feature_enable(struct amd_iommu
*iommu
, u8 bit
)
392 ctrl
= readq(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
393 ctrl
|= (1ULL << bit
);
394 writeq(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
397 static void iommu_feature_disable(struct amd_iommu
*iommu
, u8 bit
)
401 ctrl
= readq(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
402 ctrl
&= ~(1ULL << bit
);
403 writeq(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
406 static void iommu_set_inv_tlb_timeout(struct amd_iommu
*iommu
, int timeout
)
410 ctrl
= readq(iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
411 ctrl
&= ~CTRL_INV_TO_MASK
;
412 ctrl
|= (timeout
<< CONTROL_INV_TIMEOUT
) & CTRL_INV_TO_MASK
;
413 writeq(ctrl
, iommu
->mmio_base
+ MMIO_CONTROL_OFFSET
);
416 /* Function to enable the hardware */
417 static void iommu_enable(struct amd_iommu
*iommu
)
419 iommu_feature_enable(iommu
, CONTROL_IOMMU_EN
);
422 static void iommu_disable(struct amd_iommu
*iommu
)
424 if (!iommu
->mmio_base
)
427 /* Disable command buffer */
428 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
430 /* Disable event logging and event interrupts */
431 iommu_feature_disable(iommu
, CONTROL_EVT_INT_EN
);
432 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
434 /* Disable IOMMU GA_LOG */
435 iommu_feature_disable(iommu
, CONTROL_GALOG_EN
);
436 iommu_feature_disable(iommu
, CONTROL_GAINT_EN
);
438 /* Disable IOMMU hardware itself */
439 iommu_feature_disable(iommu
, CONTROL_IOMMU_EN
);
443 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
444 * the system has one.
446 static u8 __iomem
* __init
iommu_map_mmio_space(u64 address
, u64 end
)
448 if (!request_mem_region(address
, end
, "amd_iommu")) {
449 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
451 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
455 return (u8 __iomem
*)ioremap_nocache(address
, end
);
458 static void __init
iommu_unmap_mmio_space(struct amd_iommu
*iommu
)
460 if (iommu
->mmio_base
)
461 iounmap(iommu
->mmio_base
);
462 release_mem_region(iommu
->mmio_phys
, iommu
->mmio_phys_end
);
465 static inline u32
get_ivhd_header_size(struct ivhd_header
*h
)
481 /****************************************************************************
483 * The functions below belong to the first pass of AMD IOMMU ACPI table
484 * parsing. In this pass we try to find out the highest device id this
485 * code has to handle. Upon this information the size of the shared data
486 * structures is determined later.
488 ****************************************************************************/
491 * This function calculates the length of a given IVHD entry
493 static inline int ivhd_entry_length(u8
*ivhd
)
495 u32 type
= ((struct ivhd_entry
*)ivhd
)->type
;
498 return 0x04 << (*ivhd
>> 6);
499 } else if (type
== IVHD_DEV_ACPI_HID
) {
500 /* For ACPI_HID, offset 21 is uid len */
501 return *((u8
*)ivhd
+ 21) + 22;
507 * After reading the highest device id from the IOMMU PCI capability header
508 * this function looks if there is a higher device id defined in the ACPI table
510 static int __init
find_last_devid_from_ivhd(struct ivhd_header
*h
)
512 u8
*p
= (void *)h
, *end
= (void *)h
;
513 struct ivhd_entry
*dev
;
515 u32 ivhd_size
= get_ivhd_header_size(h
);
518 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h
->type
);
526 dev
= (struct ivhd_entry
*)p
;
529 /* Use maximum BDF value for DEV_ALL */
530 update_last_devid(0xffff);
532 case IVHD_DEV_SELECT
:
533 case IVHD_DEV_RANGE_END
:
535 case IVHD_DEV_EXT_SELECT
:
536 /* all the above subfield types refer to device ids */
537 update_last_devid(dev
->devid
);
542 p
+= ivhd_entry_length(p
);
550 static int __init
check_ivrs_checksum(struct acpi_table_header
*table
)
553 u8 checksum
= 0, *p
= (u8
*)table
;
555 for (i
= 0; i
< table
->length
; ++i
)
558 /* ACPI table corrupt */
559 pr_err(FW_BUG
"AMD-Vi: IVRS invalid checksum\n");
567 * Iterate over all IVHD entries in the ACPI table and find the highest device
568 * id which we need to handle. This is the first of three functions which parse
569 * the ACPI table. So we check the checksum here.
571 static int __init
find_last_devid_acpi(struct acpi_table_header
*table
)
573 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
574 struct ivhd_header
*h
;
576 p
+= IVRS_HEADER_LENGTH
;
578 end
+= table
->length
;
580 h
= (struct ivhd_header
*)p
;
581 if (h
->type
== amd_iommu_target_ivhd_type
) {
582 int ret
= find_last_devid_from_ivhd(h
);
594 /****************************************************************************
596 * The following functions belong to the code path which parses the ACPI table
597 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
598 * data structures, initialize the device/alias/rlookup table and also
599 * basically initialize the hardware.
601 ****************************************************************************/
604 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
605 * write commands to that buffer later and the IOMMU will execute them
608 static int __init
alloc_command_buffer(struct amd_iommu
*iommu
)
610 iommu
->cmd_buf
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
611 get_order(CMD_BUFFER_SIZE
));
613 return iommu
->cmd_buf
? 0 : -ENOMEM
;
617 * This function resets the command buffer if the IOMMU stopped fetching
620 void amd_iommu_reset_cmd_buffer(struct amd_iommu
*iommu
)
622 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
624 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_HEAD_OFFSET
);
625 writel(0x00, iommu
->mmio_base
+ MMIO_CMD_TAIL_OFFSET
);
626 iommu
->cmd_buf_head
= 0;
627 iommu
->cmd_buf_tail
= 0;
629 iommu_feature_enable(iommu
, CONTROL_CMDBUF_EN
);
633 * This function writes the command buffer address to the hardware and
636 static void iommu_enable_command_buffer(struct amd_iommu
*iommu
)
640 BUG_ON(iommu
->cmd_buf
== NULL
);
642 entry
= iommu_virt_to_phys(iommu
->cmd_buf
);
643 entry
|= MMIO_CMD_SIZE_512
;
645 memcpy_toio(iommu
->mmio_base
+ MMIO_CMD_BUF_OFFSET
,
646 &entry
, sizeof(entry
));
648 amd_iommu_reset_cmd_buffer(iommu
);
652 * This function disables the command buffer
654 static void iommu_disable_command_buffer(struct amd_iommu
*iommu
)
656 iommu_feature_disable(iommu
, CONTROL_CMDBUF_EN
);
659 static void __init
free_command_buffer(struct amd_iommu
*iommu
)
661 free_pages((unsigned long)iommu
->cmd_buf
, get_order(CMD_BUFFER_SIZE
));
664 /* allocates the memory where the IOMMU will log its events to */
665 static int __init
alloc_event_buffer(struct amd_iommu
*iommu
)
667 iommu
->evt_buf
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
668 get_order(EVT_BUFFER_SIZE
));
670 return iommu
->evt_buf
? 0 : -ENOMEM
;
673 static void iommu_enable_event_buffer(struct amd_iommu
*iommu
)
677 BUG_ON(iommu
->evt_buf
== NULL
);
679 entry
= iommu_virt_to_phys(iommu
->evt_buf
) | EVT_LEN_MASK
;
681 memcpy_toio(iommu
->mmio_base
+ MMIO_EVT_BUF_OFFSET
,
682 &entry
, sizeof(entry
));
684 /* set head and tail to zero manually */
685 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_HEAD_OFFSET
);
686 writel(0x00, iommu
->mmio_base
+ MMIO_EVT_TAIL_OFFSET
);
688 iommu_feature_enable(iommu
, CONTROL_EVT_LOG_EN
);
692 * This function disables the event log buffer
694 static void iommu_disable_event_buffer(struct amd_iommu
*iommu
)
696 iommu_feature_disable(iommu
, CONTROL_EVT_LOG_EN
);
699 static void __init
free_event_buffer(struct amd_iommu
*iommu
)
701 free_pages((unsigned long)iommu
->evt_buf
, get_order(EVT_BUFFER_SIZE
));
704 /* allocates the memory where the IOMMU will log its events to */
705 static int __init
alloc_ppr_log(struct amd_iommu
*iommu
)
707 iommu
->ppr_log
= (void *)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
708 get_order(PPR_LOG_SIZE
));
710 return iommu
->ppr_log
? 0 : -ENOMEM
;
713 static void iommu_enable_ppr_log(struct amd_iommu
*iommu
)
717 if (iommu
->ppr_log
== NULL
)
720 entry
= iommu_virt_to_phys(iommu
->ppr_log
) | PPR_LOG_SIZE_512
;
722 memcpy_toio(iommu
->mmio_base
+ MMIO_PPR_LOG_OFFSET
,
723 &entry
, sizeof(entry
));
725 /* set head and tail to zero manually */
726 writel(0x00, iommu
->mmio_base
+ MMIO_PPR_HEAD_OFFSET
);
727 writel(0x00, iommu
->mmio_base
+ MMIO_PPR_TAIL_OFFSET
);
729 iommu_feature_enable(iommu
, CONTROL_PPFLOG_EN
);
730 iommu_feature_enable(iommu
, CONTROL_PPR_EN
);
733 static void __init
free_ppr_log(struct amd_iommu
*iommu
)
735 if (iommu
->ppr_log
== NULL
)
738 free_pages((unsigned long)iommu
->ppr_log
, get_order(PPR_LOG_SIZE
));
741 static void free_ga_log(struct amd_iommu
*iommu
)
743 #ifdef CONFIG_IRQ_REMAP
745 free_pages((unsigned long)iommu
->ga_log
,
746 get_order(GA_LOG_SIZE
));
747 if (iommu
->ga_log_tail
)
748 free_pages((unsigned long)iommu
->ga_log_tail
,
753 static int iommu_ga_log_enable(struct amd_iommu
*iommu
)
755 #ifdef CONFIG_IRQ_REMAP
761 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
763 /* Check if already running */
764 if (status
& (MMIO_STATUS_GALOG_RUN_MASK
))
767 iommu_feature_enable(iommu
, CONTROL_GAINT_EN
);
768 iommu_feature_enable(iommu
, CONTROL_GALOG_EN
);
770 for (i
= 0; i
< LOOP_TIMEOUT
; ++i
) {
771 status
= readl(iommu
->mmio_base
+ MMIO_STATUS_OFFSET
);
772 if (status
& (MMIO_STATUS_GALOG_RUN_MASK
))
776 if (i
>= LOOP_TIMEOUT
)
778 #endif /* CONFIG_IRQ_REMAP */
782 #ifdef CONFIG_IRQ_REMAP
783 static int iommu_init_ga_log(struct amd_iommu
*iommu
)
787 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
))
790 iommu
->ga_log
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
791 get_order(GA_LOG_SIZE
));
795 iommu
->ga_log_tail
= (u8
*)__get_free_pages(GFP_KERNEL
| __GFP_ZERO
,
797 if (!iommu
->ga_log_tail
)
800 entry
= iommu_virt_to_phys(iommu
->ga_log
) | GA_LOG_SIZE_512
;
801 memcpy_toio(iommu
->mmio_base
+ MMIO_GA_LOG_BASE_OFFSET
,
802 &entry
, sizeof(entry
));
803 entry
= (iommu_virt_to_phys(iommu
->ga_log_tail
) &
804 (BIT_ULL(52)-1)) & ~7ULL;
805 memcpy_toio(iommu
->mmio_base
+ MMIO_GA_LOG_TAIL_OFFSET
,
806 &entry
, sizeof(entry
));
807 writel(0x00, iommu
->mmio_base
+ MMIO_GA_HEAD_OFFSET
);
808 writel(0x00, iommu
->mmio_base
+ MMIO_GA_TAIL_OFFSET
);
815 #endif /* CONFIG_IRQ_REMAP */
817 static int iommu_init_ga(struct amd_iommu
*iommu
)
821 #ifdef CONFIG_IRQ_REMAP
822 /* Note: We have already checked GASup from IVRS table.
823 * Now, we need to make sure that GAMSup is set.
825 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
) &&
826 !iommu_feature(iommu
, FEATURE_GAM_VAPIC
))
827 amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_LEGACY_GA
;
829 ret
= iommu_init_ga_log(iommu
);
830 #endif /* CONFIG_IRQ_REMAP */
835 static void iommu_enable_xt(struct amd_iommu
*iommu
)
837 #ifdef CONFIG_IRQ_REMAP
839 * XT mode (32-bit APIC destination ID) requires
840 * GA mode (128-bit IRTE support) as a prerequisite.
842 if (AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
) &&
843 amd_iommu_xt_mode
== IRQ_REMAP_X2APIC_MODE
)
844 iommu_feature_enable(iommu
, CONTROL_XT_EN
);
845 #endif /* CONFIG_IRQ_REMAP */
848 static void iommu_enable_gt(struct amd_iommu
*iommu
)
850 if (!iommu_feature(iommu
, FEATURE_GT
))
853 iommu_feature_enable(iommu
, CONTROL_GT_EN
);
856 /* sets a specific bit in the device table entry. */
857 static void set_dev_entry_bit(u16 devid
, u8 bit
)
859 int i
= (bit
>> 6) & 0x03;
860 int _bit
= bit
& 0x3f;
862 amd_iommu_dev_table
[devid
].data
[i
] |= (1UL << _bit
);
865 static int get_dev_entry_bit(u16 devid
, u8 bit
)
867 int i
= (bit
>> 6) & 0x03;
868 int _bit
= bit
& 0x3f;
870 return (amd_iommu_dev_table
[devid
].data
[i
] & (1UL << _bit
)) >> _bit
;
874 static bool copy_device_table(void)
876 u64 int_ctl
, int_tab_len
, entry
= 0, last_entry
= 0;
877 struct dev_table_entry
*old_devtb
= NULL
;
878 u32 lo
, hi
, devid
, old_devtb_size
;
879 phys_addr_t old_devtb_phys
;
880 struct amd_iommu
*iommu
;
881 u16 dom_id
, dte_v
, irq_v
;
885 if (!amd_iommu_pre_enabled
)
888 pr_warn("Translation is already enabled - trying to copy translation structures\n");
889 for_each_iommu(iommu
) {
890 /* All IOMMUs should use the same device table with the same size */
891 lo
= readl(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
);
892 hi
= readl(iommu
->mmio_base
+ MMIO_DEV_TABLE_OFFSET
+ 4);
893 entry
= (((u64
) hi
) << 32) + lo
;
894 if (last_entry
&& last_entry
!= entry
) {
895 pr_err("IOMMU:%d should use the same dev table as others!\n",
901 old_devtb_size
= ((entry
& ~PAGE_MASK
) + 1) << 12;
902 if (old_devtb_size
!= dev_table_size
) {
903 pr_err("The device table size of IOMMU:%d is not expected!\n",
909 old_devtb_phys
= entry
& PAGE_MASK
;
910 if (old_devtb_phys
>= 0x100000000ULL
) {
911 pr_err("The address of old device table is above 4G, not trustworthy!\n");
914 old_devtb
= memremap(old_devtb_phys
, dev_table_size
, MEMREMAP_WB
);
918 gfp_flag
= GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
;
919 old_dev_tbl_cpy
= (void *)__get_free_pages(gfp_flag
,
920 get_order(dev_table_size
));
921 if (old_dev_tbl_cpy
== NULL
) {
922 pr_err("Failed to allocate memory for copying old device table!\n");
926 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
927 old_dev_tbl_cpy
[devid
] = old_devtb
[devid
];
928 dom_id
= old_devtb
[devid
].data
[1] & DEV_DOMID_MASK
;
929 dte_v
= old_devtb
[devid
].data
[0] & DTE_FLAG_V
;
931 if (dte_v
&& dom_id
) {
932 old_dev_tbl_cpy
[devid
].data
[0] = old_devtb
[devid
].data
[0];
933 old_dev_tbl_cpy
[devid
].data
[1] = old_devtb
[devid
].data
[1];
934 __set_bit(dom_id
, amd_iommu_pd_alloc_bitmap
);
935 /* If gcr3 table existed, mask it out */
936 if (old_devtb
[devid
].data
[0] & DTE_FLAG_GV
) {
937 tmp
= DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B
;
938 tmp
|= DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C
;
939 old_dev_tbl_cpy
[devid
].data
[1] &= ~tmp
;
940 tmp
= DTE_GCR3_VAL_A(~0ULL) << DTE_GCR3_SHIFT_A
;
942 old_dev_tbl_cpy
[devid
].data
[0] &= ~tmp
;
946 irq_v
= old_devtb
[devid
].data
[2] & DTE_IRQ_REMAP_ENABLE
;
947 int_ctl
= old_devtb
[devid
].data
[2] & DTE_IRQ_REMAP_INTCTL_MASK
;
948 int_tab_len
= old_devtb
[devid
].data
[2] & DTE_IRQ_TABLE_LEN_MASK
;
949 if (irq_v
&& (int_ctl
|| int_tab_len
)) {
950 if ((int_ctl
!= DTE_IRQ_REMAP_INTCTL
) ||
951 (int_tab_len
!= DTE_IRQ_TABLE_LEN
)) {
952 pr_err("Wrong old irq remapping flag: %#x\n", devid
);
956 old_dev_tbl_cpy
[devid
].data
[2] = old_devtb
[devid
].data
[2];
964 void amd_iommu_apply_erratum_63(u16 devid
)
968 sysmgt
= get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
) |
969 (get_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
) << 1);
972 set_dev_entry_bit(devid
, DEV_ENTRY_IW
);
975 /* Writes the specific IOMMU for a device into the rlookup table */
976 static void __init
set_iommu_for_device(struct amd_iommu
*iommu
, u16 devid
)
978 amd_iommu_rlookup_table
[devid
] = iommu
;
982 * This function takes the device specific flags read from the ACPI
983 * table and sets up the device table entry with that information
985 static void __init
set_dev_entry_from_acpi(struct amd_iommu
*iommu
,
986 u16 devid
, u32 flags
, u32 ext_flags
)
988 if (flags
& ACPI_DEVFLAG_INITPASS
)
989 set_dev_entry_bit(devid
, DEV_ENTRY_INIT_PASS
);
990 if (flags
& ACPI_DEVFLAG_EXTINT
)
991 set_dev_entry_bit(devid
, DEV_ENTRY_EINT_PASS
);
992 if (flags
& ACPI_DEVFLAG_NMI
)
993 set_dev_entry_bit(devid
, DEV_ENTRY_NMI_PASS
);
994 if (flags
& ACPI_DEVFLAG_SYSMGT1
)
995 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT1
);
996 if (flags
& ACPI_DEVFLAG_SYSMGT2
)
997 set_dev_entry_bit(devid
, DEV_ENTRY_SYSMGT2
);
998 if (flags
& ACPI_DEVFLAG_LINT0
)
999 set_dev_entry_bit(devid
, DEV_ENTRY_LINT0_PASS
);
1000 if (flags
& ACPI_DEVFLAG_LINT1
)
1001 set_dev_entry_bit(devid
, DEV_ENTRY_LINT1_PASS
);
1003 amd_iommu_apply_erratum_63(devid
);
1005 set_iommu_for_device(iommu
, devid
);
1008 static int __init
add_special_device(u8 type
, u8 id
, u16
*devid
, bool cmd_line
)
1010 struct devid_map
*entry
;
1011 struct list_head
*list
;
1013 if (type
== IVHD_SPECIAL_IOAPIC
)
1015 else if (type
== IVHD_SPECIAL_HPET
)
1020 list_for_each_entry(entry
, list
, list
) {
1021 if (!(entry
->id
== id
&& entry
->cmd_line
))
1024 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
1025 type
== IVHD_SPECIAL_IOAPIC
? "IOAPIC" : "HPET", id
);
1027 *devid
= entry
->devid
;
1032 entry
= kzalloc(sizeof(*entry
), GFP_KERNEL
);
1037 entry
->devid
= *devid
;
1038 entry
->cmd_line
= cmd_line
;
1040 list_add_tail(&entry
->list
, list
);
1045 static int __init
add_acpi_hid_device(u8
*hid
, u8
*uid
, u16
*devid
,
1048 struct acpihid_map_entry
*entry
;
1049 struct list_head
*list
= &acpihid_map
;
1051 list_for_each_entry(entry
, list
, list
) {
1052 if (strcmp(entry
->hid
, hid
) ||
1053 (*uid
&& *entry
->uid
&& strcmp(entry
->uid
, uid
)) ||
1057 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
1059 *devid
= entry
->devid
;
1063 entry
= kzalloc(sizeof(*entry
), GFP_KERNEL
);
1067 memcpy(entry
->uid
, uid
, strlen(uid
));
1068 memcpy(entry
->hid
, hid
, strlen(hid
));
1069 entry
->devid
= *devid
;
1070 entry
->cmd_line
= cmd_line
;
1071 entry
->root_devid
= (entry
->devid
& (~0x7));
1073 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
1074 entry
->cmd_line
? "cmd" : "ivrs",
1075 entry
->hid
, entry
->uid
, entry
->root_devid
);
1077 list_add_tail(&entry
->list
, list
);
1081 static int __init
add_early_maps(void)
1085 for (i
= 0; i
< early_ioapic_map_size
; ++i
) {
1086 ret
= add_special_device(IVHD_SPECIAL_IOAPIC
,
1087 early_ioapic_map
[i
].id
,
1088 &early_ioapic_map
[i
].devid
,
1089 early_ioapic_map
[i
].cmd_line
);
1094 for (i
= 0; i
< early_hpet_map_size
; ++i
) {
1095 ret
= add_special_device(IVHD_SPECIAL_HPET
,
1096 early_hpet_map
[i
].id
,
1097 &early_hpet_map
[i
].devid
,
1098 early_hpet_map
[i
].cmd_line
);
1103 for (i
= 0; i
< early_acpihid_map_size
; ++i
) {
1104 ret
= add_acpi_hid_device(early_acpihid_map
[i
].hid
,
1105 early_acpihid_map
[i
].uid
,
1106 &early_acpihid_map
[i
].devid
,
1107 early_acpihid_map
[i
].cmd_line
);
1116 * Reads the device exclusion range from ACPI and initializes the IOMMU with
1119 static void __init
set_device_exclusion_range(u16 devid
, struct ivmd_header
*m
)
1121 struct amd_iommu
*iommu
= amd_iommu_rlookup_table
[devid
];
1123 if (!(m
->flags
& IVMD_FLAG_EXCL_RANGE
))
1128 * We only can configure exclusion ranges per IOMMU, not
1129 * per device. But we can enable the exclusion range per
1130 * device. This is done here
1132 set_dev_entry_bit(devid
, DEV_ENTRY_EX
);
1133 iommu
->exclusion_start
= m
->range_start
;
1134 iommu
->exclusion_length
= m
->range_length
;
1139 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1140 * initializes the hardware and our data structures with it.
1142 static int __init
init_iommu_from_acpi(struct amd_iommu
*iommu
,
1143 struct ivhd_header
*h
)
1146 u8
*end
= p
, flags
= 0;
1147 u16 devid
= 0, devid_start
= 0, devid_to
= 0;
1148 u32 dev_i
, ext_flags
= 0;
1150 struct ivhd_entry
*e
;
1155 ret
= add_early_maps();
1160 * First save the recommended feature enable bits from ACPI
1162 iommu
->acpi_flags
= h
->flags
;
1165 * Done. Now parse the device entries
1167 ivhd_size
= get_ivhd_header_size(h
);
1169 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h
->type
);
1179 e
= (struct ivhd_entry
*)p
;
1183 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e
->flags
);
1185 for (dev_i
= 0; dev_i
<= amd_iommu_last_bdf
; ++dev_i
)
1186 set_dev_entry_from_acpi(iommu
, dev_i
, e
->flags
, 0);
1188 case IVHD_DEV_SELECT
:
1190 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1192 PCI_BUS_NUM(e
->devid
),
1198 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
1200 case IVHD_DEV_SELECT_RANGE_START
:
1202 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1203 "devid: %02x:%02x.%x flags: %02x\n",
1204 PCI_BUS_NUM(e
->devid
),
1209 devid_start
= e
->devid
;
1214 case IVHD_DEV_ALIAS
:
1216 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1217 "flags: %02x devid_to: %02x:%02x.%x\n",
1218 PCI_BUS_NUM(e
->devid
),
1222 PCI_BUS_NUM(e
->ext
>> 8),
1223 PCI_SLOT(e
->ext
>> 8),
1224 PCI_FUNC(e
->ext
>> 8));
1227 devid_to
= e
->ext
>> 8;
1228 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
1229 set_dev_entry_from_acpi(iommu
, devid_to
, e
->flags
, 0);
1230 amd_iommu_alias_table
[devid
] = devid_to
;
1232 case IVHD_DEV_ALIAS_RANGE
:
1234 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1235 "devid: %02x:%02x.%x flags: %02x "
1236 "devid_to: %02x:%02x.%x\n",
1237 PCI_BUS_NUM(e
->devid
),
1241 PCI_BUS_NUM(e
->ext
>> 8),
1242 PCI_SLOT(e
->ext
>> 8),
1243 PCI_FUNC(e
->ext
>> 8));
1245 devid_start
= e
->devid
;
1247 devid_to
= e
->ext
>> 8;
1251 case IVHD_DEV_EXT_SELECT
:
1253 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1254 "flags: %02x ext: %08x\n",
1255 PCI_BUS_NUM(e
->devid
),
1261 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
,
1264 case IVHD_DEV_EXT_SELECT_RANGE
:
1266 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1267 "%02x:%02x.%x flags: %02x ext: %08x\n",
1268 PCI_BUS_NUM(e
->devid
),
1273 devid_start
= e
->devid
;
1278 case IVHD_DEV_RANGE_END
:
1280 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1281 PCI_BUS_NUM(e
->devid
),
1283 PCI_FUNC(e
->devid
));
1286 for (dev_i
= devid_start
; dev_i
<= devid
; ++dev_i
) {
1288 amd_iommu_alias_table
[dev_i
] = devid_to
;
1289 set_dev_entry_from_acpi(iommu
,
1290 devid_to
, flags
, ext_flags
);
1292 set_dev_entry_from_acpi(iommu
, dev_i
,
1296 case IVHD_DEV_SPECIAL
: {
1302 handle
= e
->ext
& 0xff;
1303 devid
= (e
->ext
>> 8) & 0xffff;
1304 type
= (e
->ext
>> 24) & 0xff;
1306 if (type
== IVHD_SPECIAL_IOAPIC
)
1308 else if (type
== IVHD_SPECIAL_HPET
)
1313 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1319 ret
= add_special_device(type
, handle
, &devid
, false);
1324 * add_special_device might update the devid in case a
1325 * command-line override is present. So call
1326 * set_dev_entry_from_acpi after add_special_device.
1328 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
1332 case IVHD_DEV_ACPI_HID
: {
1334 u8 hid
[ACPIHID_HID_LEN
] = {0};
1335 u8 uid
[ACPIHID_UID_LEN
] = {0};
1338 if (h
->type
!= 0x40) {
1339 pr_err(FW_BUG
"Invalid IVHD device type %#x\n",
1344 memcpy(hid
, (u8
*)(&e
->ext
), ACPIHID_HID_LEN
- 1);
1345 hid
[ACPIHID_HID_LEN
- 1] = '\0';
1348 pr_err(FW_BUG
"Invalid HID.\n");
1353 case UID_NOT_PRESENT
:
1356 pr_warn(FW_BUG
"Invalid UID length.\n");
1359 case UID_IS_INTEGER
:
1361 sprintf(uid
, "%d", e
->uid
);
1364 case UID_IS_CHARACTER
:
1366 memcpy(uid
, (u8
*)(&e
->uid
), ACPIHID_UID_LEN
- 1);
1367 uid
[ACPIHID_UID_LEN
- 1] = '\0';
1375 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1383 ret
= add_acpi_hid_device(hid
, uid
, &devid
, false);
1388 * add_special_device might update the devid in case a
1389 * command-line override is present. So call
1390 * set_dev_entry_from_acpi after add_special_device.
1392 set_dev_entry_from_acpi(iommu
, devid
, e
->flags
, 0);
1400 p
+= ivhd_entry_length(p
);
1406 static void __init
free_iommu_one(struct amd_iommu
*iommu
)
1408 free_command_buffer(iommu
);
1409 free_event_buffer(iommu
);
1410 free_ppr_log(iommu
);
1412 iommu_unmap_mmio_space(iommu
);
1415 static void __init
free_iommu_all(void)
1417 struct amd_iommu
*iommu
, *next
;
1419 for_each_iommu_safe(iommu
, next
) {
1420 list_del(&iommu
->list
);
1421 free_iommu_one(iommu
);
1427 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1429 * BIOS should disable L2B micellaneous clock gating by setting
1430 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1432 static void amd_iommu_erratum_746_workaround(struct amd_iommu
*iommu
)
1436 if ((boot_cpu_data
.x86
!= 0x15) ||
1437 (boot_cpu_data
.x86_model
< 0x10) ||
1438 (boot_cpu_data
.x86_model
> 0x1f))
1441 pci_write_config_dword(iommu
->dev
, 0xf0, 0x90);
1442 pci_read_config_dword(iommu
->dev
, 0xf4, &value
);
1447 /* Select NB indirect register 0x90 and enable writing */
1448 pci_write_config_dword(iommu
->dev
, 0xf0, 0x90 | (1 << 8));
1450 pci_write_config_dword(iommu
->dev
, 0xf4, value
| 0x4);
1451 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1452 dev_name(&iommu
->dev
->dev
));
1454 /* Clear the enable writing bit */
1455 pci_write_config_dword(iommu
->dev
, 0xf0, 0x90);
1459 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1461 * BIOS should enable ATS write permission check by setting
1462 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1464 static void amd_iommu_ats_write_check_workaround(struct amd_iommu
*iommu
)
1468 if ((boot_cpu_data
.x86
!= 0x15) ||
1469 (boot_cpu_data
.x86_model
< 0x30) ||
1470 (boot_cpu_data
.x86_model
> 0x3f))
1473 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1474 value
= iommu_read_l2(iommu
, 0x47);
1479 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1480 iommu_write_l2(iommu
, 0x47, value
| BIT(0));
1482 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1483 dev_name(&iommu
->dev
->dev
));
1487 * This function clues the initialization function for one IOMMU
1488 * together and also allocates the command buffer and programs the
1489 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1491 static int __init
init_iommu_one(struct amd_iommu
*iommu
, struct ivhd_header
*h
)
1495 spin_lock_init(&iommu
->lock
);
1497 /* Add IOMMU to internal data structures */
1498 list_add_tail(&iommu
->list
, &amd_iommu_list
);
1499 iommu
->index
= amd_iommus_present
++;
1501 if (unlikely(iommu
->index
>= MAX_IOMMUS
)) {
1502 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1506 /* Index is fine - add IOMMU to the array */
1507 amd_iommus
[iommu
->index
] = iommu
;
1510 * Copy data from ACPI table entry to the iommu struct
1512 iommu
->devid
= h
->devid
;
1513 iommu
->cap_ptr
= h
->cap_ptr
;
1514 iommu
->pci_seg
= h
->pci_seg
;
1515 iommu
->mmio_phys
= h
->mmio_phys
;
1519 /* Check if IVHD EFR contains proper max banks/counters */
1520 if ((h
->efr_attr
!= 0) &&
1521 ((h
->efr_attr
& (0xF << 13)) != 0) &&
1522 ((h
->efr_attr
& (0x3F << 17)) != 0))
1523 iommu
->mmio_phys_end
= MMIO_REG_END_OFFSET
;
1525 iommu
->mmio_phys_end
= MMIO_CNTR_CONF_OFFSET
;
1526 if (((h
->efr_attr
& (0x1 << IOMMU_FEAT_GASUP_SHIFT
)) == 0))
1527 amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_LEGACY
;
1528 if (((h
->efr_attr
& (0x1 << IOMMU_FEAT_XTSUP_SHIFT
)) == 0))
1529 amd_iommu_xt_mode
= IRQ_REMAP_XAPIC_MODE
;
1533 if (h
->efr_reg
& (1 << 9))
1534 iommu
->mmio_phys_end
= MMIO_REG_END_OFFSET
;
1536 iommu
->mmio_phys_end
= MMIO_CNTR_CONF_OFFSET
;
1537 if (((h
->efr_reg
& (0x1 << IOMMU_EFR_GASUP_SHIFT
)) == 0))
1538 amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_LEGACY
;
1539 if (((h
->efr_reg
& (0x1 << IOMMU_EFR_XTSUP_SHIFT
)) == 0))
1540 amd_iommu_xt_mode
= IRQ_REMAP_XAPIC_MODE
;
1546 iommu
->mmio_base
= iommu_map_mmio_space(iommu
->mmio_phys
,
1547 iommu
->mmio_phys_end
);
1548 if (!iommu
->mmio_base
)
1551 if (alloc_command_buffer(iommu
))
1554 if (alloc_event_buffer(iommu
))
1557 iommu
->int_enabled
= false;
1559 init_translation_status(iommu
);
1560 if (translation_pre_enabled(iommu
) && !is_kdump_kernel()) {
1561 iommu_disable(iommu
);
1562 clear_translation_pre_enabled(iommu
);
1563 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n",
1566 if (amd_iommu_pre_enabled
)
1567 amd_iommu_pre_enabled
= translation_pre_enabled(iommu
);
1569 ret
= init_iommu_from_acpi(iommu
, h
);
1573 ret
= amd_iommu_create_irq_domain(iommu
);
1578 * Make sure IOMMU is not considered to translate itself. The IVRS
1579 * table tells us so, but this is a lie!
1581 amd_iommu_rlookup_table
[iommu
->devid
] = NULL
;
1587 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1588 * @ivrs Pointer to the IVRS header
1590 * This function search through all IVDB of the maximum supported IVHD
1592 static u8
get_highest_supported_ivhd_type(struct acpi_table_header
*ivrs
)
1594 u8
*base
= (u8
*)ivrs
;
1595 struct ivhd_header
*ivhd
= (struct ivhd_header
*)
1596 (base
+ IVRS_HEADER_LENGTH
);
1597 u8 last_type
= ivhd
->type
;
1598 u16 devid
= ivhd
->devid
;
1600 while (((u8
*)ivhd
- base
< ivrs
->length
) &&
1601 (ivhd
->type
<= ACPI_IVHD_TYPE_MAX_SUPPORTED
)) {
1602 u8
*p
= (u8
*) ivhd
;
1604 if (ivhd
->devid
== devid
)
1605 last_type
= ivhd
->type
;
1606 ivhd
= (struct ivhd_header
*)(p
+ ivhd
->length
);
1613 * Iterates over all IOMMU entries in the ACPI table, allocates the
1614 * IOMMU structure and initializes it with init_iommu_one()
1616 static int __init
init_iommu_all(struct acpi_table_header
*table
)
1618 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
1619 struct ivhd_header
*h
;
1620 struct amd_iommu
*iommu
;
1623 end
+= table
->length
;
1624 p
+= IVRS_HEADER_LENGTH
;
1627 h
= (struct ivhd_header
*)p
;
1628 if (*p
== amd_iommu_target_ivhd_type
) {
1630 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1631 "seg: %d flags: %01x info %04x\n",
1632 PCI_BUS_NUM(h
->devid
), PCI_SLOT(h
->devid
),
1633 PCI_FUNC(h
->devid
), h
->cap_ptr
,
1634 h
->pci_seg
, h
->flags
, h
->info
);
1635 DUMP_printk(" mmio-addr: %016llx\n",
1638 iommu
= kzalloc(sizeof(struct amd_iommu
), GFP_KERNEL
);
1642 ret
= init_iommu_one(iommu
, h
);
1654 static int iommu_pc_get_set_reg(struct amd_iommu
*iommu
, u8 bank
, u8 cntr
,
1655 u8 fxn
, u64
*value
, bool is_write
);
1657 static void init_iommu_perf_ctr(struct amd_iommu
*iommu
)
1659 u64 val
= 0xabcd, val2
= 0;
1661 if (!iommu_feature(iommu
, FEATURE_PC
))
1664 amd_iommu_pc_present
= true;
1666 /* Check if the performance counters can be written to */
1667 if ((iommu_pc_get_set_reg(iommu
, 0, 0, 0, &val
, true)) ||
1668 (iommu_pc_get_set_reg(iommu
, 0, 0, 0, &val2
, false)) ||
1670 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1671 amd_iommu_pc_present
= false;
1675 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1677 val
= readl(iommu
->mmio_base
+ MMIO_CNTR_CONF_OFFSET
);
1678 iommu
->max_banks
= (u8
) ((val
>> 12) & 0x3f);
1679 iommu
->max_counters
= (u8
) ((val
>> 7) & 0xf);
1682 static ssize_t
amd_iommu_show_cap(struct device
*dev
,
1683 struct device_attribute
*attr
,
1686 struct amd_iommu
*iommu
= dev_to_amd_iommu(dev
);
1687 return sprintf(buf
, "%x\n", iommu
->cap
);
1689 static DEVICE_ATTR(cap
, S_IRUGO
, amd_iommu_show_cap
, NULL
);
1691 static ssize_t
amd_iommu_show_features(struct device
*dev
,
1692 struct device_attribute
*attr
,
1695 struct amd_iommu
*iommu
= dev_to_amd_iommu(dev
);
1696 return sprintf(buf
, "%llx\n", iommu
->features
);
1698 static DEVICE_ATTR(features
, S_IRUGO
, amd_iommu_show_features
, NULL
);
1700 static struct attribute
*amd_iommu_attrs
[] = {
1702 &dev_attr_features
.attr
,
1706 static struct attribute_group amd_iommu_group
= {
1707 .name
= "amd-iommu",
1708 .attrs
= amd_iommu_attrs
,
1711 static const struct attribute_group
*amd_iommu_groups
[] = {
1716 static int __init
iommu_init_pci(struct amd_iommu
*iommu
)
1718 int cap_ptr
= iommu
->cap_ptr
;
1719 u32 range
, misc
, low
, high
;
1722 iommu
->dev
= pci_get_bus_and_slot(PCI_BUS_NUM(iommu
->devid
),
1723 iommu
->devid
& 0xff);
1727 /* Prevent binding other PCI device drivers to IOMMU devices */
1728 iommu
->dev
->match_driver
= false;
1730 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_CAP_HDR_OFFSET
,
1732 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_RANGE_OFFSET
,
1734 pci_read_config_dword(iommu
->dev
, cap_ptr
+ MMIO_MISC_OFFSET
,
1737 if (!(iommu
->cap
& (1 << IOMMU_CAP_IOTLB
)))
1738 amd_iommu_iotlb_sup
= false;
1740 /* read extended feature bits */
1741 low
= readl(iommu
->mmio_base
+ MMIO_EXT_FEATURES
);
1742 high
= readl(iommu
->mmio_base
+ MMIO_EXT_FEATURES
+ 4);
1744 iommu
->features
= ((u64
)high
<< 32) | low
;
1746 if (iommu_feature(iommu
, FEATURE_GT
)) {
1751 pasmax
= iommu
->features
& FEATURE_PASID_MASK
;
1752 pasmax
>>= FEATURE_PASID_SHIFT
;
1753 max_pasid
= (1 << (pasmax
+ 1)) - 1;
1755 amd_iommu_max_pasid
= min(amd_iommu_max_pasid
, max_pasid
);
1757 BUG_ON(amd_iommu_max_pasid
& ~PASID_MASK
);
1759 glxval
= iommu
->features
& FEATURE_GLXVAL_MASK
;
1760 glxval
>>= FEATURE_GLXVAL_SHIFT
;
1762 if (amd_iommu_max_glx_val
== -1)
1763 amd_iommu_max_glx_val
= glxval
;
1765 amd_iommu_max_glx_val
= min(amd_iommu_max_glx_val
, glxval
);
1768 if (iommu_feature(iommu
, FEATURE_GT
) &&
1769 iommu_feature(iommu
, FEATURE_PPR
)) {
1770 iommu
->is_iommu_v2
= true;
1771 amd_iommu_v2_present
= true;
1774 if (iommu_feature(iommu
, FEATURE_PPR
) && alloc_ppr_log(iommu
))
1777 ret
= iommu_init_ga(iommu
);
1781 if (iommu
->cap
& (1UL << IOMMU_CAP_NPCACHE
))
1782 amd_iommu_np_cache
= true;
1784 init_iommu_perf_ctr(iommu
);
1786 if (is_rd890_iommu(iommu
->dev
)) {
1789 iommu
->root_pdev
= pci_get_bus_and_slot(iommu
->dev
->bus
->number
,
1793 * Some rd890 systems may not be fully reconfigured by the
1794 * BIOS, so it's necessary for us to store this information so
1795 * it can be reprogrammed on resume
1797 pci_read_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
1798 &iommu
->stored_addr_lo
);
1799 pci_read_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 8,
1800 &iommu
->stored_addr_hi
);
1802 /* Low bit locks writes to configuration space */
1803 iommu
->stored_addr_lo
&= ~1;
1805 for (i
= 0; i
< 6; i
++)
1806 for (j
= 0; j
< 0x12; j
++)
1807 iommu
->stored_l1
[i
][j
] = iommu_read_l1(iommu
, i
, j
);
1809 for (i
= 0; i
< 0x83; i
++)
1810 iommu
->stored_l2
[i
] = iommu_read_l2(iommu
, i
);
1813 amd_iommu_erratum_746_workaround(iommu
);
1814 amd_iommu_ats_write_check_workaround(iommu
);
1816 iommu_device_sysfs_add(&iommu
->iommu
, &iommu
->dev
->dev
,
1817 amd_iommu_groups
, "ivhd%d", iommu
->index
);
1818 iommu_device_set_ops(&iommu
->iommu
, &amd_iommu_ops
);
1819 iommu_device_register(&iommu
->iommu
);
1821 return pci_enable_device(iommu
->dev
);
1824 static void print_iommu_info(void)
1826 static const char * const feat_str
[] = {
1827 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1828 "IA", "GA", "HE", "PC"
1830 struct amd_iommu
*iommu
;
1832 for_each_iommu(iommu
) {
1835 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1836 dev_name(&iommu
->dev
->dev
), iommu
->cap_ptr
);
1838 if (iommu
->cap
& (1 << IOMMU_CAP_EFR
)) {
1839 pr_info("AMD-Vi: Extended features (%#llx):\n",
1841 for (i
= 0; i
< ARRAY_SIZE(feat_str
); ++i
) {
1842 if (iommu_feature(iommu
, (1ULL << i
)))
1843 pr_cont(" %s", feat_str
[i
]);
1846 if (iommu
->features
& FEATURE_GAM_VAPIC
)
1847 pr_cont(" GA_vAPIC");
1852 if (irq_remapping_enabled
) {
1853 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1854 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
))
1855 pr_info("AMD-Vi: virtual APIC enabled\n");
1856 if (amd_iommu_xt_mode
== IRQ_REMAP_X2APIC_MODE
)
1857 pr_info("AMD-Vi: X2APIC enabled\n");
1861 static int __init
amd_iommu_init_pci(void)
1863 struct amd_iommu
*iommu
;
1866 for_each_iommu(iommu
) {
1867 ret
= iommu_init_pci(iommu
);
1873 * Order is important here to make sure any unity map requirements are
1874 * fulfilled. The unity mappings are created and written to the device
1875 * table during the amd_iommu_init_api() call.
1877 * After that we call init_device_table_dma() to make sure any
1878 * uninitialized DTE will block DMA, and in the end we flush the caches
1879 * of all IOMMUs to make sure the changes to the device table are
1882 ret
= amd_iommu_init_api();
1884 init_device_table_dma();
1886 for_each_iommu(iommu
)
1887 iommu_flush_all_caches(iommu
);
1895 /****************************************************************************
1897 * The following functions initialize the MSI interrupts for all IOMMUs
1898 * in the system. It's a bit challenging because there could be multiple
1899 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1902 ****************************************************************************/
1904 static int iommu_setup_msi(struct amd_iommu
*iommu
)
1908 r
= pci_enable_msi(iommu
->dev
);
1912 r
= request_threaded_irq(iommu
->dev
->irq
,
1913 amd_iommu_int_handler
,
1914 amd_iommu_int_thread
,
1919 pci_disable_msi(iommu
->dev
);
1923 iommu
->int_enabled
= true;
1928 static int iommu_init_msi(struct amd_iommu
*iommu
)
1932 if (iommu
->int_enabled
)
1935 if (iommu
->dev
->msi_cap
)
1936 ret
= iommu_setup_msi(iommu
);
1944 iommu_feature_enable(iommu
, CONTROL_EVT_INT_EN
);
1946 if (iommu
->ppr_log
!= NULL
)
1947 iommu_feature_enable(iommu
, CONTROL_PPFINT_EN
);
1949 iommu_ga_log_enable(iommu
);
1954 /****************************************************************************
1956 * The next functions belong to the third pass of parsing the ACPI
1957 * table. In this last pass the memory mapping requirements are
1958 * gathered (like exclusion and unity mapping ranges).
1960 ****************************************************************************/
1962 static void __init
free_unity_maps(void)
1964 struct unity_map_entry
*entry
, *next
;
1966 list_for_each_entry_safe(entry
, next
, &amd_iommu_unity_map
, list
) {
1967 list_del(&entry
->list
);
1972 /* called when we find an exclusion range definition in ACPI */
1973 static int __init
init_exclusion_range(struct ivmd_header
*m
)
1978 case ACPI_IVMD_TYPE
:
1979 set_device_exclusion_range(m
->devid
, m
);
1981 case ACPI_IVMD_TYPE_ALL
:
1982 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
1983 set_device_exclusion_range(i
, m
);
1985 case ACPI_IVMD_TYPE_RANGE
:
1986 for (i
= m
->devid
; i
<= m
->aux
; ++i
)
1987 set_device_exclusion_range(i
, m
);
1996 /* called for unity map ACPI definition */
1997 static int __init
init_unity_map_range(struct ivmd_header
*m
)
1999 struct unity_map_entry
*e
= NULL
;
2002 e
= kzalloc(sizeof(*e
), GFP_KERNEL
);
2006 if (m
->flags
& IVMD_FLAG_EXCL_RANGE
)
2007 init_exclusion_range(m
);
2013 case ACPI_IVMD_TYPE
:
2014 s
= "IVMD_TYPEi\t\t\t";
2015 e
->devid_start
= e
->devid_end
= m
->devid
;
2017 case ACPI_IVMD_TYPE_ALL
:
2018 s
= "IVMD_TYPE_ALL\t\t";
2020 e
->devid_end
= amd_iommu_last_bdf
;
2022 case ACPI_IVMD_TYPE_RANGE
:
2023 s
= "IVMD_TYPE_RANGE\t\t";
2024 e
->devid_start
= m
->devid
;
2025 e
->devid_end
= m
->aux
;
2028 e
->address_start
= PAGE_ALIGN(m
->range_start
);
2029 e
->address_end
= e
->address_start
+ PAGE_ALIGN(m
->range_length
);
2030 e
->prot
= m
->flags
>> 1;
2032 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
2033 " range_start: %016llx range_end: %016llx flags: %x\n", s
,
2034 PCI_BUS_NUM(e
->devid_start
), PCI_SLOT(e
->devid_start
),
2035 PCI_FUNC(e
->devid_start
), PCI_BUS_NUM(e
->devid_end
),
2036 PCI_SLOT(e
->devid_end
), PCI_FUNC(e
->devid_end
),
2037 e
->address_start
, e
->address_end
, m
->flags
);
2039 list_add_tail(&e
->list
, &amd_iommu_unity_map
);
2044 /* iterates over all memory definitions we find in the ACPI table */
2045 static int __init
init_memory_definitions(struct acpi_table_header
*table
)
2047 u8
*p
= (u8
*)table
, *end
= (u8
*)table
;
2048 struct ivmd_header
*m
;
2050 end
+= table
->length
;
2051 p
+= IVRS_HEADER_LENGTH
;
2054 m
= (struct ivmd_header
*)p
;
2055 if (m
->flags
& (IVMD_FLAG_UNITY_MAP
| IVMD_FLAG_EXCL_RANGE
))
2056 init_unity_map_range(m
);
2065 * Init the device table to not allow DMA access for devices
2067 static void init_device_table_dma(void)
2071 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
2072 set_dev_entry_bit(devid
, DEV_ENTRY_VALID
);
2073 set_dev_entry_bit(devid
, DEV_ENTRY_TRANSLATION
);
2077 static void __init
uninit_device_table_dma(void)
2081 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
) {
2082 amd_iommu_dev_table
[devid
].data
[0] = 0ULL;
2083 amd_iommu_dev_table
[devid
].data
[1] = 0ULL;
2087 static void init_device_table(void)
2091 if (!amd_iommu_irq_remap
)
2094 for (devid
= 0; devid
<= amd_iommu_last_bdf
; ++devid
)
2095 set_dev_entry_bit(devid
, DEV_ENTRY_IRQ_TBL_EN
);
2098 static void iommu_init_flags(struct amd_iommu
*iommu
)
2100 iommu
->acpi_flags
& IVHD_FLAG_HT_TUN_EN_MASK
?
2101 iommu_feature_enable(iommu
, CONTROL_HT_TUN_EN
) :
2102 iommu_feature_disable(iommu
, CONTROL_HT_TUN_EN
);
2104 iommu
->acpi_flags
& IVHD_FLAG_PASSPW_EN_MASK
?
2105 iommu_feature_enable(iommu
, CONTROL_PASSPW_EN
) :
2106 iommu_feature_disable(iommu
, CONTROL_PASSPW_EN
);
2108 iommu
->acpi_flags
& IVHD_FLAG_RESPASSPW_EN_MASK
?
2109 iommu_feature_enable(iommu
, CONTROL_RESPASSPW_EN
) :
2110 iommu_feature_disable(iommu
, CONTROL_RESPASSPW_EN
);
2112 iommu
->acpi_flags
& IVHD_FLAG_ISOC_EN_MASK
?
2113 iommu_feature_enable(iommu
, CONTROL_ISOC_EN
) :
2114 iommu_feature_disable(iommu
, CONTROL_ISOC_EN
);
2117 * make IOMMU memory accesses cache coherent
2119 iommu_feature_enable(iommu
, CONTROL_COHERENT_EN
);
2121 /* Set IOTLB invalidation timeout to 1s */
2122 iommu_set_inv_tlb_timeout(iommu
, CTRL_INV_TO_1S
);
2125 static void iommu_apply_resume_quirks(struct amd_iommu
*iommu
)
2128 u32 ioc_feature_control
;
2129 struct pci_dev
*pdev
= iommu
->root_pdev
;
2131 /* RD890 BIOSes may not have completely reconfigured the iommu */
2132 if (!is_rd890_iommu(iommu
->dev
) || !pdev
)
2136 * First, we need to ensure that the iommu is enabled. This is
2137 * controlled by a register in the northbridge
2140 /* Select Northbridge indirect register 0x75 and enable writing */
2141 pci_write_config_dword(pdev
, 0x60, 0x75 | (1 << 7));
2142 pci_read_config_dword(pdev
, 0x64, &ioc_feature_control
);
2144 /* Enable the iommu */
2145 if (!(ioc_feature_control
& 0x1))
2146 pci_write_config_dword(pdev
, 0x64, ioc_feature_control
| 1);
2148 /* Restore the iommu BAR */
2149 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
2150 iommu
->stored_addr_lo
);
2151 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 8,
2152 iommu
->stored_addr_hi
);
2154 /* Restore the l1 indirect regs for each of the 6 l1s */
2155 for (i
= 0; i
< 6; i
++)
2156 for (j
= 0; j
< 0x12; j
++)
2157 iommu_write_l1(iommu
, i
, j
, iommu
->stored_l1
[i
][j
]);
2159 /* Restore the l2 indirect regs */
2160 for (i
= 0; i
< 0x83; i
++)
2161 iommu_write_l2(iommu
, i
, iommu
->stored_l2
[i
]);
2163 /* Lock PCI setup registers */
2164 pci_write_config_dword(iommu
->dev
, iommu
->cap_ptr
+ 4,
2165 iommu
->stored_addr_lo
| 1);
2168 static void iommu_enable_ga(struct amd_iommu
*iommu
)
2170 #ifdef CONFIG_IRQ_REMAP
2171 switch (amd_iommu_guest_ir
) {
2172 case AMD_IOMMU_GUEST_IR_VAPIC
:
2173 iommu_feature_enable(iommu
, CONTROL_GAM_EN
);
2175 case AMD_IOMMU_GUEST_IR_LEGACY_GA
:
2176 iommu_feature_enable(iommu
, CONTROL_GA_EN
);
2177 iommu
->irte_ops
= &irte_128_ops
;
2180 iommu
->irte_ops
= &irte_32_ops
;
2186 static void early_enable_iommu(struct amd_iommu
*iommu
)
2188 iommu_disable(iommu
);
2189 iommu_init_flags(iommu
);
2190 iommu_set_device_table(iommu
);
2191 iommu_enable_command_buffer(iommu
);
2192 iommu_enable_event_buffer(iommu
);
2193 iommu_set_exclusion_range(iommu
);
2194 iommu_enable_ga(iommu
);
2195 iommu_enable_xt(iommu
);
2196 iommu_enable(iommu
);
2197 iommu_flush_all_caches(iommu
);
2201 * This function finally enables all IOMMUs found in the system after
2202 * they have been initialized.
2204 * Or if in kdump kernel and IOMMUs are all pre-enabled, try to copy
2205 * the old content of device table entries. Not this case or copy failed,
2206 * just continue as normal kernel does.
2208 static void early_enable_iommus(void)
2210 struct amd_iommu
*iommu
;
2213 if (!copy_device_table()) {
2215 * If come here because of failure in copying device table from old
2216 * kernel with all IOMMUs enabled, print error message and try to
2217 * free allocated old_dev_tbl_cpy.
2219 if (amd_iommu_pre_enabled
)
2220 pr_err("Failed to copy DEV table from previous kernel.\n");
2221 if (old_dev_tbl_cpy
!= NULL
)
2222 free_pages((unsigned long)old_dev_tbl_cpy
,
2223 get_order(dev_table_size
));
2225 for_each_iommu(iommu
) {
2226 clear_translation_pre_enabled(iommu
);
2227 early_enable_iommu(iommu
);
2230 pr_info("Copied DEV table from previous kernel.\n");
2231 free_pages((unsigned long)amd_iommu_dev_table
,
2232 get_order(dev_table_size
));
2233 amd_iommu_dev_table
= old_dev_tbl_cpy
;
2234 for_each_iommu(iommu
) {
2235 iommu_disable_command_buffer(iommu
);
2236 iommu_disable_event_buffer(iommu
);
2237 iommu_enable_command_buffer(iommu
);
2238 iommu_enable_event_buffer(iommu
);
2239 iommu_enable_ga(iommu
);
2240 iommu_enable_xt(iommu
);
2241 iommu_set_device_table(iommu
);
2242 iommu_flush_all_caches(iommu
);
2246 #ifdef CONFIG_IRQ_REMAP
2247 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
))
2248 amd_iommu_irq_ops
.capability
|= (1 << IRQ_POSTING_CAP
);
2252 static void enable_iommus_v2(void)
2254 struct amd_iommu
*iommu
;
2256 for_each_iommu(iommu
) {
2257 iommu_enable_ppr_log(iommu
);
2258 iommu_enable_gt(iommu
);
2262 static void enable_iommus(void)
2264 early_enable_iommus();
2269 static void disable_iommus(void)
2271 struct amd_iommu
*iommu
;
2273 for_each_iommu(iommu
)
2274 iommu_disable(iommu
);
2276 #ifdef CONFIG_IRQ_REMAP
2277 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir
))
2278 amd_iommu_irq_ops
.capability
&= ~(1 << IRQ_POSTING_CAP
);
2283 * Suspend/Resume support
2284 * disable suspend until real resume implemented
2287 static void amd_iommu_resume(void)
2289 struct amd_iommu
*iommu
;
2291 for_each_iommu(iommu
)
2292 iommu_apply_resume_quirks(iommu
);
2294 /* re-load the hardware */
2297 amd_iommu_enable_interrupts();
2300 static int amd_iommu_suspend(void)
2302 /* disable IOMMUs to go out of the way for BIOS */
2308 static struct syscore_ops amd_iommu_syscore_ops
= {
2309 .suspend
= amd_iommu_suspend
,
2310 .resume
= amd_iommu_resume
,
2313 static void __init
free_iommu_resources(void)
2315 kmemleak_free(irq_lookup_table
);
2316 free_pages((unsigned long)irq_lookup_table
,
2317 get_order(rlookup_table_size
));
2318 irq_lookup_table
= NULL
;
2320 kmem_cache_destroy(amd_iommu_irq_cache
);
2321 amd_iommu_irq_cache
= NULL
;
2323 free_pages((unsigned long)amd_iommu_rlookup_table
,
2324 get_order(rlookup_table_size
));
2325 amd_iommu_rlookup_table
= NULL
;
2327 free_pages((unsigned long)amd_iommu_alias_table
,
2328 get_order(alias_table_size
));
2329 amd_iommu_alias_table
= NULL
;
2331 free_pages((unsigned long)amd_iommu_dev_table
,
2332 get_order(dev_table_size
));
2333 amd_iommu_dev_table
= NULL
;
2337 #ifdef CONFIG_GART_IOMMU
2339 * We failed to initialize the AMD IOMMU - try fallback to GART
2347 /* SB IOAPIC is always on this device in AMD systems */
2348 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2350 static bool __init
check_ioapic_information(void)
2352 const char *fw_bug
= FW_BUG
;
2353 bool ret
, has_sb_ioapic
;
2356 has_sb_ioapic
= false;
2360 * If we have map overrides on the kernel command line the
2361 * messages in this function might not describe firmware bugs
2362 * anymore - so be careful
2367 for (idx
= 0; idx
< nr_ioapics
; idx
++) {
2368 int devid
, id
= mpc_ioapic_id(idx
);
2370 devid
= get_ioapic_devid(id
);
2372 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2375 } else if (devid
== IOAPIC_SB_DEVID
) {
2376 has_sb_ioapic
= true;
2381 if (!has_sb_ioapic
) {
2383 * We expect the SB IOAPIC to be listed in the IVRS
2384 * table. The system timer is connected to the SB IOAPIC
2385 * and if we don't have it in the list the system will
2386 * panic at boot time. This situation usually happens
2387 * when the BIOS is buggy and provides us the wrong
2388 * device id for the IOAPIC in the system.
2390 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug
);
2394 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2399 static void __init
free_dma_resources(void)
2401 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap
,
2402 get_order(MAX_DOMAIN_ID
/8));
2403 amd_iommu_pd_alloc_bitmap
= NULL
;
2409 * This is the hardware init function for AMD IOMMU in the system.
2410 * This function is called either from amd_iommu_init or from the interrupt
2411 * remapping setup code.
2413 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2416 * 1 pass) Discover the most comprehensive IVHD type to use.
2418 * 2 pass) Find the highest PCI device id the driver has to handle.
2419 * Upon this information the size of the data structures is
2420 * determined that needs to be allocated.
2422 * 3 pass) Initialize the data structures just allocated with the
2423 * information in the ACPI table about available AMD IOMMUs
2424 * in the system. It also maps the PCI devices in the
2425 * system to specific IOMMUs
2427 * 4 pass) After the basic data structures are allocated and
2428 * initialized we update them with information about memory
2429 * remapping requirements parsed out of the ACPI table in
2432 * After everything is set up the IOMMUs are enabled and the necessary
2433 * hotplug and suspend notifiers are registered.
2435 static int __init
early_amd_iommu_init(void)
2437 struct acpi_table_header
*ivrs_base
;
2439 int i
, remap_cache_sz
, ret
= 0;
2441 if (!amd_iommu_detected
)
2444 status
= acpi_get_table("IVRS", 0, &ivrs_base
);
2445 if (status
== AE_NOT_FOUND
)
2447 else if (ACPI_FAILURE(status
)) {
2448 const char *err
= acpi_format_exception(status
);
2449 pr_err("AMD-Vi: IVRS table error: %s\n", err
);
2454 * Validate checksum here so we don't need to do it when
2455 * we actually parse the table
2457 ret
= check_ivrs_checksum(ivrs_base
);
2461 amd_iommu_target_ivhd_type
= get_highest_supported_ivhd_type(ivrs_base
);
2462 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type
);
2465 * First parse ACPI tables to find the largest Bus/Dev/Func
2466 * we need to handle. Upon this information the shared data
2467 * structures for the IOMMUs in the system will be allocated
2469 ret
= find_last_devid_acpi(ivrs_base
);
2473 dev_table_size
= tbl_size(DEV_TABLE_ENTRY_SIZE
);
2474 alias_table_size
= tbl_size(ALIAS_TABLE_ENTRY_SIZE
);
2475 rlookup_table_size
= tbl_size(RLOOKUP_TABLE_ENTRY_SIZE
);
2477 /* Device table - directly used by all IOMMUs */
2479 amd_iommu_dev_table
= (void *)__get_free_pages(
2480 GFP_KERNEL
| __GFP_ZERO
| GFP_DMA32
,
2481 get_order(dev_table_size
));
2482 if (amd_iommu_dev_table
== NULL
)
2486 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2487 * IOMMU see for that device
2489 amd_iommu_alias_table
= (void *)__get_free_pages(GFP_KERNEL
,
2490 get_order(alias_table_size
));
2491 if (amd_iommu_alias_table
== NULL
)
2494 /* IOMMU rlookup table - find the IOMMU for a specific device */
2495 amd_iommu_rlookup_table
= (void *)__get_free_pages(
2496 GFP_KERNEL
| __GFP_ZERO
,
2497 get_order(rlookup_table_size
));
2498 if (amd_iommu_rlookup_table
== NULL
)
2501 amd_iommu_pd_alloc_bitmap
= (void *)__get_free_pages(
2502 GFP_KERNEL
| __GFP_ZERO
,
2503 get_order(MAX_DOMAIN_ID
/8));
2504 if (amd_iommu_pd_alloc_bitmap
== NULL
)
2508 * let all alias entries point to itself
2510 for (i
= 0; i
<= amd_iommu_last_bdf
; ++i
)
2511 amd_iommu_alias_table
[i
] = i
;
2514 * never allocate domain 0 because its used as the non-allocated and
2515 * error value placeholder
2517 __set_bit(0, amd_iommu_pd_alloc_bitmap
);
2519 spin_lock_init(&amd_iommu_pd_lock
);
2522 * now the data structures are allocated and basically initialized
2523 * start the real acpi table scan
2525 ret
= init_iommu_all(ivrs_base
);
2529 /* Disable any previously enabled IOMMUs */
2530 if (!is_kdump_kernel() || amd_iommu_disabled
)
2533 if (amd_iommu_irq_remap
)
2534 amd_iommu_irq_remap
= check_ioapic_information();
2536 if (amd_iommu_irq_remap
) {
2538 * Interrupt remapping enabled, create kmem_cache for the
2542 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir
))
2543 remap_cache_sz
= MAX_IRQS_PER_TABLE
* sizeof(u32
);
2545 remap_cache_sz
= MAX_IRQS_PER_TABLE
* (sizeof(u64
) * 2);
2546 amd_iommu_irq_cache
= kmem_cache_create("irq_remap_cache",
2548 IRQ_TABLE_ALIGNMENT
,
2550 if (!amd_iommu_irq_cache
)
2553 irq_lookup_table
= (void *)__get_free_pages(
2554 GFP_KERNEL
| __GFP_ZERO
,
2555 get_order(rlookup_table_size
));
2556 kmemleak_alloc(irq_lookup_table
, rlookup_table_size
,
2558 if (!irq_lookup_table
)
2562 ret
= init_memory_definitions(ivrs_base
);
2566 /* init the device table */
2567 init_device_table();
2570 /* Don't leak any ACPI memory */
2571 acpi_put_table(ivrs_base
);
2577 static int amd_iommu_enable_interrupts(void)
2579 struct amd_iommu
*iommu
;
2582 for_each_iommu(iommu
) {
2583 ret
= iommu_init_msi(iommu
);
2592 static bool detect_ivrs(void)
2594 struct acpi_table_header
*ivrs_base
;
2597 status
= acpi_get_table("IVRS", 0, &ivrs_base
);
2598 if (status
== AE_NOT_FOUND
)
2600 else if (ACPI_FAILURE(status
)) {
2601 const char *err
= acpi_format_exception(status
);
2602 pr_err("AMD-Vi: IVRS table error: %s\n", err
);
2606 acpi_put_table(ivrs_base
);
2608 /* Make sure ACS will be enabled during PCI probe */
2614 /****************************************************************************
2616 * AMD IOMMU Initialization State Machine
2618 ****************************************************************************/
2620 static int __init
state_next(void)
2624 switch (init_state
) {
2625 case IOMMU_START_STATE
:
2626 if (!detect_ivrs()) {
2627 init_state
= IOMMU_NOT_FOUND
;
2630 init_state
= IOMMU_IVRS_DETECTED
;
2633 case IOMMU_IVRS_DETECTED
:
2634 ret
= early_amd_iommu_init();
2635 init_state
= ret
? IOMMU_INIT_ERROR
: IOMMU_ACPI_FINISHED
;
2636 if (init_state
== IOMMU_ACPI_FINISHED
&& amd_iommu_disabled
) {
2637 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2638 free_dma_resources();
2639 free_iommu_resources();
2640 init_state
= IOMMU_CMDLINE_DISABLED
;
2644 case IOMMU_ACPI_FINISHED
:
2645 early_enable_iommus();
2646 x86_platform
.iommu_shutdown
= disable_iommus
;
2647 init_state
= IOMMU_ENABLED
;
2650 register_syscore_ops(&amd_iommu_syscore_ops
);
2651 ret
= amd_iommu_init_pci();
2652 init_state
= ret
? IOMMU_INIT_ERROR
: IOMMU_PCI_INIT
;
2655 case IOMMU_PCI_INIT
:
2656 ret
= amd_iommu_enable_interrupts();
2657 init_state
= ret
? IOMMU_INIT_ERROR
: IOMMU_INTERRUPTS_EN
;
2659 case IOMMU_INTERRUPTS_EN
:
2660 ret
= amd_iommu_init_dma_ops();
2661 init_state
= ret
? IOMMU_INIT_ERROR
: IOMMU_DMA_OPS
;
2664 init_state
= IOMMU_INITIALIZED
;
2666 case IOMMU_INITIALIZED
:
2669 case IOMMU_NOT_FOUND
:
2670 case IOMMU_INIT_ERROR
:
2671 case IOMMU_CMDLINE_DISABLED
:
2672 /* Error states => do nothing */
2683 static int __init
iommu_go_to_state(enum iommu_init_state state
)
2687 while (init_state
!= state
) {
2688 if (init_state
== IOMMU_NOT_FOUND
||
2689 init_state
== IOMMU_INIT_ERROR
||
2690 init_state
== IOMMU_CMDLINE_DISABLED
)
2698 #ifdef CONFIG_IRQ_REMAP
2699 int __init
amd_iommu_prepare(void)
2703 amd_iommu_irq_remap
= true;
2705 ret
= iommu_go_to_state(IOMMU_ACPI_FINISHED
);
2708 return amd_iommu_irq_remap
? 0 : -ENODEV
;
2711 int __init
amd_iommu_enable(void)
2715 ret
= iommu_go_to_state(IOMMU_ENABLED
);
2719 irq_remapping_enabled
= 1;
2720 return amd_iommu_xt_mode
;
2723 void amd_iommu_disable(void)
2725 amd_iommu_suspend();
2728 int amd_iommu_reenable(int mode
)
2735 int __init
amd_iommu_enable_faulting(void)
2737 /* We enable MSI later when PCI is initialized */
2743 * This is the core init function for AMD IOMMU hardware in the system.
2744 * This function is called from the generic x86 DMA layer initialization
2747 static int __init
amd_iommu_init(void)
2751 ret
= iommu_go_to_state(IOMMU_INITIALIZED
);
2753 free_dma_resources();
2754 if (!irq_remapping_enabled
) {
2756 free_iommu_resources();
2758 struct amd_iommu
*iommu
;
2760 uninit_device_table_dma();
2761 for_each_iommu(iommu
)
2762 iommu_flush_all_caches(iommu
);
2769 static bool amd_iommu_sme_check(void)
2771 if (!sme_active() || (boot_cpu_data
.x86
!= 0x17))
2774 /* For Fam17h, a specific level of support is required */
2775 if (boot_cpu_data
.microcode
>= 0x08001205)
2778 if ((boot_cpu_data
.microcode
>= 0x08001126) &&
2779 (boot_cpu_data
.microcode
<= 0x080011ff))
2782 pr_notice("AMD-Vi: IOMMU not currently supported when SME is active\n");
2787 /****************************************************************************
2789 * Early detect code. This code runs at IOMMU detection time in the DMA
2790 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2793 ****************************************************************************/
2794 int __init
amd_iommu_detect(void)
2798 if (no_iommu
|| (iommu_detected
&& !gart_iommu_aperture
))
2801 if (!amd_iommu_sme_check())
2804 ret
= iommu_go_to_state(IOMMU_IVRS_DETECTED
);
2808 amd_iommu_detected
= true;
2810 x86_init
.iommu
.iommu_init
= amd_iommu_init
;
2815 /****************************************************************************
2817 * Parsing functions for the AMD IOMMU specific kernel command line
2820 ****************************************************************************/
2822 static int __init
parse_amd_iommu_dump(char *str
)
2824 amd_iommu_dump
= true;
2829 static int __init
parse_amd_iommu_intr(char *str
)
2831 for (; *str
; ++str
) {
2832 if (strncmp(str
, "legacy", 6) == 0) {
2833 amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_LEGACY
;
2836 if (strncmp(str
, "vapic", 5) == 0) {
2837 amd_iommu_guest_ir
= AMD_IOMMU_GUEST_IR_VAPIC
;
2844 static int __init
parse_amd_iommu_options(char *str
)
2846 for (; *str
; ++str
) {
2847 if (strncmp(str
, "fullflush", 9) == 0)
2848 amd_iommu_unmap_flush
= true;
2849 if (strncmp(str
, "off", 3) == 0)
2850 amd_iommu_disabled
= true;
2851 if (strncmp(str
, "force_isolation", 15) == 0)
2852 amd_iommu_force_isolation
= true;
2858 static int __init
parse_ivrs_ioapic(char *str
)
2860 unsigned int bus
, dev
, fn
;
2864 ret
= sscanf(str
, "[%d]=%x:%x.%x", &id
, &bus
, &dev
, &fn
);
2867 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str
);
2871 if (early_ioapic_map_size
== EARLY_MAP_SIZE
) {
2872 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2877 devid
= ((bus
& 0xff) << 8) | ((dev
& 0x1f) << 3) | (fn
& 0x7);
2879 cmdline_maps
= true;
2880 i
= early_ioapic_map_size
++;
2881 early_ioapic_map
[i
].id
= id
;
2882 early_ioapic_map
[i
].devid
= devid
;
2883 early_ioapic_map
[i
].cmd_line
= true;
2888 static int __init
parse_ivrs_hpet(char *str
)
2890 unsigned int bus
, dev
, fn
;
2894 ret
= sscanf(str
, "[%d]=%x:%x.%x", &id
, &bus
, &dev
, &fn
);
2897 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str
);
2901 if (early_hpet_map_size
== EARLY_MAP_SIZE
) {
2902 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2907 devid
= ((bus
& 0xff) << 8) | ((dev
& 0x1f) << 3) | (fn
& 0x7);
2909 cmdline_maps
= true;
2910 i
= early_hpet_map_size
++;
2911 early_hpet_map
[i
].id
= id
;
2912 early_hpet_map
[i
].devid
= devid
;
2913 early_hpet_map
[i
].cmd_line
= true;
2918 static int __init
parse_ivrs_acpihid(char *str
)
2921 char *hid
, *uid
, *p
;
2922 char acpiid
[ACPIHID_UID_LEN
+ ACPIHID_HID_LEN
] = {0};
2925 ret
= sscanf(str
, "[%x:%x.%x]=%s", &bus
, &dev
, &fn
, acpiid
);
2927 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str
);
2932 hid
= strsep(&p
, ":");
2935 if (!hid
|| !(*hid
) || !uid
) {
2936 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2940 i
= early_acpihid_map_size
++;
2941 memcpy(early_acpihid_map
[i
].hid
, hid
, strlen(hid
));
2942 memcpy(early_acpihid_map
[i
].uid
, uid
, strlen(uid
));
2943 early_acpihid_map
[i
].devid
=
2944 ((bus
& 0xff) << 8) | ((dev
& 0x1f) << 3) | (fn
& 0x7);
2945 early_acpihid_map
[i
].cmd_line
= true;
2950 __setup("amd_iommu_dump", parse_amd_iommu_dump
);
2951 __setup("amd_iommu=", parse_amd_iommu_options
);
2952 __setup("amd_iommu_intr=", parse_amd_iommu_intr
);
2953 __setup("ivrs_ioapic", parse_ivrs_ioapic
);
2954 __setup("ivrs_hpet", parse_ivrs_hpet
);
2955 __setup("ivrs_acpihid", parse_ivrs_acpihid
);
2957 IOMMU_INIT_FINISH(amd_iommu_detect
,
2958 gart_iommu_hole_init
,
2962 bool amd_iommu_v2_supported(void)
2964 return amd_iommu_v2_present
;
2966 EXPORT_SYMBOL(amd_iommu_v2_supported
);
2968 struct amd_iommu
*get_amd_iommu(unsigned int idx
)
2971 struct amd_iommu
*iommu
;
2973 for_each_iommu(iommu
)
2978 EXPORT_SYMBOL(get_amd_iommu
);
2980 /****************************************************************************
2982 * IOMMU EFR Performance Counter support functionality. This code allows
2983 * access to the IOMMU PC functionality.
2985 ****************************************************************************/
2987 u8
amd_iommu_pc_get_max_banks(unsigned int idx
)
2989 struct amd_iommu
*iommu
= get_amd_iommu(idx
);
2992 return iommu
->max_banks
;
2996 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks
);
2998 bool amd_iommu_pc_supported(void)
3000 return amd_iommu_pc_present
;
3002 EXPORT_SYMBOL(amd_iommu_pc_supported
);
3004 u8
amd_iommu_pc_get_max_counters(unsigned int idx
)
3006 struct amd_iommu
*iommu
= get_amd_iommu(idx
);
3009 return iommu
->max_counters
;
3013 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters
);
3015 static int iommu_pc_get_set_reg(struct amd_iommu
*iommu
, u8 bank
, u8 cntr
,
3016 u8 fxn
, u64
*value
, bool is_write
)
3021 /* Make sure the IOMMU PC resource is available */
3022 if (!amd_iommu_pc_present
)
3025 /* Check for valid iommu and pc register indexing */
3026 if (WARN_ON(!iommu
|| (fxn
> 0x28) || (fxn
& 7)))
3029 offset
= (u32
)(((0x40 | bank
) << 12) | (cntr
<< 8) | fxn
);
3031 /* Limit the offset to the hw defined mmio region aperture */
3032 max_offset_lim
= (u32
)(((0x40 | iommu
->max_banks
) << 12) |
3033 (iommu
->max_counters
<< 8) | 0x28);
3034 if ((offset
< MMIO_CNTR_REG_OFFSET
) ||
3035 (offset
> max_offset_lim
))
3039 u64 val
= *value
& GENMASK_ULL(47, 0);
3041 writel((u32
)val
, iommu
->mmio_base
+ offset
);
3042 writel((val
>> 32), iommu
->mmio_base
+ offset
+ 4);
3044 *value
= readl(iommu
->mmio_base
+ offset
+ 4);
3046 *value
|= readl(iommu
->mmio_base
+ offset
);
3047 *value
&= GENMASK_ULL(47, 0);
3053 int amd_iommu_pc_get_reg(struct amd_iommu
*iommu
, u8 bank
, u8 cntr
, u8 fxn
, u64
*value
)
3058 return iommu_pc_get_set_reg(iommu
, bank
, cntr
, fxn
, value
, false);
3060 EXPORT_SYMBOL(amd_iommu_pc_get_reg
);
3062 int amd_iommu_pc_set_reg(struct amd_iommu
*iommu
, u8 bank
, u8 cntr
, u8 fxn
, u64
*value
)
3067 return iommu_pc_get_set_reg(iommu
, bank
, cntr
, fxn
, value
, true);
3069 EXPORT_SYMBOL(amd_iommu_pc_set_reg
);