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1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <linux/kmemleak.h>
32 #include <linux/crash_dump.h>
33 #include <linux/mem_encrypt.h>
34 #include <asm/pci-direct.h>
35 #include <asm/iommu.h>
36 #include <asm/gart.h>
37 #include <asm/x86_init.h>
38 #include <asm/iommu_table.h>
39 #include <asm/io_apic.h>
40 #include <asm/irq_remapping.h>
41
42 #include "amd_iommu_proto.h"
43 #include "amd_iommu_types.h"
44 #include "irq_remapping.h"
45
46 /*
47 * definitions for the ACPI scanning code
48 */
49 #define IVRS_HEADER_LENGTH 48
50
51 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
52 #define ACPI_IVMD_TYPE_ALL 0x20
53 #define ACPI_IVMD_TYPE 0x21
54 #define ACPI_IVMD_TYPE_RANGE 0x22
55
56 #define IVHD_DEV_ALL 0x01
57 #define IVHD_DEV_SELECT 0x02
58 #define IVHD_DEV_SELECT_RANGE_START 0x03
59 #define IVHD_DEV_RANGE_END 0x04
60 #define IVHD_DEV_ALIAS 0x42
61 #define IVHD_DEV_ALIAS_RANGE 0x43
62 #define IVHD_DEV_EXT_SELECT 0x46
63 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
64 #define IVHD_DEV_SPECIAL 0x48
65 #define IVHD_DEV_ACPI_HID 0xf0
66
67 #define UID_NOT_PRESENT 0
68 #define UID_IS_INTEGER 1
69 #define UID_IS_CHARACTER 2
70
71 #define IVHD_SPECIAL_IOAPIC 1
72 #define IVHD_SPECIAL_HPET 2
73
74 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
75 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
76 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
77 #define IVHD_FLAG_ISOC_EN_MASK 0x08
78
79 #define IVMD_FLAG_EXCL_RANGE 0x08
80 #define IVMD_FLAG_UNITY_MAP 0x01
81
82 #define ACPI_DEVFLAG_INITPASS 0x01
83 #define ACPI_DEVFLAG_EXTINT 0x02
84 #define ACPI_DEVFLAG_NMI 0x04
85 #define ACPI_DEVFLAG_SYSMGT1 0x10
86 #define ACPI_DEVFLAG_SYSMGT2 0x20
87 #define ACPI_DEVFLAG_LINT0 0x40
88 #define ACPI_DEVFLAG_LINT1 0x80
89 #define ACPI_DEVFLAG_ATSDIS 0x10000000
90
91 #define LOOP_TIMEOUT 100000
92 /*
93 * ACPI table definitions
94 *
95 * These data structures are laid over the table to parse the important values
96 * out of it.
97 */
98
99 extern const struct iommu_ops amd_iommu_ops;
100
101 /*
102 * structure describing one IOMMU in the ACPI table. Typically followed by one
103 * or more ivhd_entrys.
104 */
105 struct ivhd_header {
106 u8 type;
107 u8 flags;
108 u16 length;
109 u16 devid;
110 u16 cap_ptr;
111 u64 mmio_phys;
112 u16 pci_seg;
113 u16 info;
114 u32 efr_attr;
115
116 /* Following only valid on IVHD type 11h and 40h */
117 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
118 u64 res;
119 } __attribute__((packed));
120
121 /*
122 * A device entry describing which devices a specific IOMMU translates and
123 * which requestor ids they use.
124 */
125 struct ivhd_entry {
126 u8 type;
127 u16 devid;
128 u8 flags;
129 u32 ext;
130 u32 hidh;
131 u64 cid;
132 u8 uidf;
133 u8 uidl;
134 u8 uid;
135 } __attribute__((packed));
136
137 /*
138 * An AMD IOMMU memory definition structure. It defines things like exclusion
139 * ranges for devices and regions that should be unity mapped.
140 */
141 struct ivmd_header {
142 u8 type;
143 u8 flags;
144 u16 length;
145 u16 devid;
146 u16 aux;
147 u64 resv;
148 u64 range_start;
149 u64 range_length;
150 } __attribute__((packed));
151
152 bool amd_iommu_dump;
153 bool amd_iommu_irq_remap __read_mostly;
154
155 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
156
157 static bool amd_iommu_detected;
158 static bool __initdata amd_iommu_disabled;
159 static int amd_iommu_target_ivhd_type;
160
161 u16 amd_iommu_last_bdf; /* largest PCI device id we have
162 to handle */
163 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
164 we find in ACPI */
165 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
166
167 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
168 system */
169
170 /* Array to assign indices to IOMMUs*/
171 struct amd_iommu *amd_iommus[MAX_IOMMUS];
172
173 /* Number of IOMMUs present in the system */
174 static int amd_iommus_present;
175
176 /* IOMMUs have a non-present cache? */
177 bool amd_iommu_np_cache __read_mostly;
178 bool amd_iommu_iotlb_sup __read_mostly = true;
179
180 u32 amd_iommu_max_pasid __read_mostly = ~0;
181
182 bool amd_iommu_v2_present __read_mostly;
183 static bool amd_iommu_pc_present __read_mostly;
184
185 bool amd_iommu_force_isolation __read_mostly;
186
187 /*
188 * List of protection domains - used during resume
189 */
190 LIST_HEAD(amd_iommu_pd_list);
191 spinlock_t amd_iommu_pd_lock;
192
193 /*
194 * Pointer to the device table which is shared by all AMD IOMMUs
195 * it is indexed by the PCI device id or the HT unit id and contains
196 * information about the domain the device belongs to as well as the
197 * page table root pointer.
198 */
199 struct dev_table_entry *amd_iommu_dev_table;
200
201 /*
202 * The alias table is a driver specific data structure which contains the
203 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
204 * More than one device can share the same requestor id.
205 */
206 u16 *amd_iommu_alias_table;
207
208 /*
209 * The rlookup table is used to find the IOMMU which is responsible
210 * for a specific device. It is also indexed by the PCI device id.
211 */
212 struct amd_iommu **amd_iommu_rlookup_table;
213
214 /*
215 * This table is used to find the irq remapping table for a given device id
216 * quickly.
217 */
218 struct irq_remap_table **irq_lookup_table;
219
220 /*
221 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
222 * to know which ones are already in use.
223 */
224 unsigned long *amd_iommu_pd_alloc_bitmap;
225
226 static u32 dev_table_size; /* size of the device table */
227 static u32 alias_table_size; /* size of the alias table */
228 static u32 rlookup_table_size; /* size if the rlookup table */
229
230 enum iommu_init_state {
231 IOMMU_START_STATE,
232 IOMMU_IVRS_DETECTED,
233 IOMMU_ACPI_FINISHED,
234 IOMMU_ENABLED,
235 IOMMU_PCI_INIT,
236 IOMMU_INTERRUPTS_EN,
237 IOMMU_DMA_OPS,
238 IOMMU_INITIALIZED,
239 IOMMU_NOT_FOUND,
240 IOMMU_INIT_ERROR,
241 IOMMU_CMDLINE_DISABLED,
242 };
243
244 /* Early ioapic and hpet maps from kernel command line */
245 #define EARLY_MAP_SIZE 4
246 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
247 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
248 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
249
250 static int __initdata early_ioapic_map_size;
251 static int __initdata early_hpet_map_size;
252 static int __initdata early_acpihid_map_size;
253
254 static bool __initdata cmdline_maps;
255
256 static enum iommu_init_state init_state = IOMMU_START_STATE;
257
258 static int amd_iommu_enable_interrupts(void);
259 static int __init iommu_go_to_state(enum iommu_init_state state);
260 static void init_device_table_dma(void);
261
262 static inline void update_last_devid(u16 devid)
263 {
264 if (devid > amd_iommu_last_bdf)
265 amd_iommu_last_bdf = devid;
266 }
267
268 static inline unsigned long tbl_size(int entry_size)
269 {
270 unsigned shift = PAGE_SHIFT +
271 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
272
273 return 1UL << shift;
274 }
275
276 int amd_iommu_get_num_iommus(void)
277 {
278 return amd_iommus_present;
279 }
280
281 /* Access to l1 and l2 indexed register spaces */
282
283 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
284 {
285 u32 val;
286
287 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
288 pci_read_config_dword(iommu->dev, 0xfc, &val);
289 return val;
290 }
291
292 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
293 {
294 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
295 pci_write_config_dword(iommu->dev, 0xfc, val);
296 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
297 }
298
299 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
300 {
301 u32 val;
302
303 pci_write_config_dword(iommu->dev, 0xf0, address);
304 pci_read_config_dword(iommu->dev, 0xf4, &val);
305 return val;
306 }
307
308 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
309 {
310 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
311 pci_write_config_dword(iommu->dev, 0xf4, val);
312 }
313
314 /****************************************************************************
315 *
316 * AMD IOMMU MMIO register space handling functions
317 *
318 * These functions are used to program the IOMMU device registers in
319 * MMIO space required for that driver.
320 *
321 ****************************************************************************/
322
323 /*
324 * This function set the exclusion range in the IOMMU. DMA accesses to the
325 * exclusion range are passed through untranslated
326 */
327 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
328 {
329 u64 start = iommu->exclusion_start & PAGE_MASK;
330 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
331 u64 entry;
332
333 if (!iommu->exclusion_start)
334 return;
335
336 entry = start | MMIO_EXCL_ENABLE_MASK;
337 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
338 &entry, sizeof(entry));
339
340 entry = limit;
341 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
342 &entry, sizeof(entry));
343 }
344
345 /* Programs the physical address of the device table into the IOMMU hardware */
346 static void iommu_set_device_table(struct amd_iommu *iommu)
347 {
348 u64 entry;
349
350 BUG_ON(iommu->mmio_base == NULL);
351
352 entry = iommu_virt_to_phys(amd_iommu_dev_table);
353 entry |= (dev_table_size >> 12) - 1;
354 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
355 &entry, sizeof(entry));
356 }
357
358 /* Generic functions to enable/disable certain features of the IOMMU. */
359 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
360 {
361 u32 ctrl;
362
363 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
364 ctrl |= (1 << bit);
365 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
366 }
367
368 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
369 {
370 u32 ctrl;
371
372 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
373 ctrl &= ~(1 << bit);
374 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
375 }
376
377 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
378 {
379 u32 ctrl;
380
381 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
382 ctrl &= ~CTRL_INV_TO_MASK;
383 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
384 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
385 }
386
387 /* Function to enable the hardware */
388 static void iommu_enable(struct amd_iommu *iommu)
389 {
390 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
391 }
392
393 static void iommu_disable(struct amd_iommu *iommu)
394 {
395 /* Disable command buffer */
396 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
397
398 /* Disable event logging and event interrupts */
399 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
400 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
401
402 /* Disable IOMMU GA_LOG */
403 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
404 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
405
406 /* Disable IOMMU hardware itself */
407 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
408 }
409
410 /*
411 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
412 * the system has one.
413 */
414 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
415 {
416 if (!request_mem_region(address, end, "amd_iommu")) {
417 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
418 address, end);
419 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
420 return NULL;
421 }
422
423 return (u8 __iomem *)ioremap_nocache(address, end);
424 }
425
426 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
427 {
428 if (iommu->mmio_base)
429 iounmap(iommu->mmio_base);
430 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
431 }
432
433 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
434 {
435 u32 size = 0;
436
437 switch (h->type) {
438 case 0x10:
439 size = 24;
440 break;
441 case 0x11:
442 case 0x40:
443 size = 40;
444 break;
445 }
446 return size;
447 }
448
449 /****************************************************************************
450 *
451 * The functions below belong to the first pass of AMD IOMMU ACPI table
452 * parsing. In this pass we try to find out the highest device id this
453 * code has to handle. Upon this information the size of the shared data
454 * structures is determined later.
455 *
456 ****************************************************************************/
457
458 /*
459 * This function calculates the length of a given IVHD entry
460 */
461 static inline int ivhd_entry_length(u8 *ivhd)
462 {
463 u32 type = ((struct ivhd_entry *)ivhd)->type;
464
465 if (type < 0x80) {
466 return 0x04 << (*ivhd >> 6);
467 } else if (type == IVHD_DEV_ACPI_HID) {
468 /* For ACPI_HID, offset 21 is uid len */
469 return *((u8 *)ivhd + 21) + 22;
470 }
471 return 0;
472 }
473
474 /*
475 * After reading the highest device id from the IOMMU PCI capability header
476 * this function looks if there is a higher device id defined in the ACPI table
477 */
478 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
479 {
480 u8 *p = (void *)h, *end = (void *)h;
481 struct ivhd_entry *dev;
482
483 u32 ivhd_size = get_ivhd_header_size(h);
484
485 if (!ivhd_size) {
486 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
487 return -EINVAL;
488 }
489
490 p += ivhd_size;
491 end += h->length;
492
493 while (p < end) {
494 dev = (struct ivhd_entry *)p;
495 switch (dev->type) {
496 case IVHD_DEV_ALL:
497 /* Use maximum BDF value for DEV_ALL */
498 update_last_devid(0xffff);
499 break;
500 case IVHD_DEV_SELECT:
501 case IVHD_DEV_RANGE_END:
502 case IVHD_DEV_ALIAS:
503 case IVHD_DEV_EXT_SELECT:
504 /* all the above subfield types refer to device ids */
505 update_last_devid(dev->devid);
506 break;
507 default:
508 break;
509 }
510 p += ivhd_entry_length(p);
511 }
512
513 WARN_ON(p != end);
514
515 return 0;
516 }
517
518 static int __init check_ivrs_checksum(struct acpi_table_header *table)
519 {
520 int i;
521 u8 checksum = 0, *p = (u8 *)table;
522
523 for (i = 0; i < table->length; ++i)
524 checksum += p[i];
525 if (checksum != 0) {
526 /* ACPI table corrupt */
527 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
528 return -ENODEV;
529 }
530
531 return 0;
532 }
533
534 /*
535 * Iterate over all IVHD entries in the ACPI table and find the highest device
536 * id which we need to handle. This is the first of three functions which parse
537 * the ACPI table. So we check the checksum here.
538 */
539 static int __init find_last_devid_acpi(struct acpi_table_header *table)
540 {
541 u8 *p = (u8 *)table, *end = (u8 *)table;
542 struct ivhd_header *h;
543
544 p += IVRS_HEADER_LENGTH;
545
546 end += table->length;
547 while (p < end) {
548 h = (struct ivhd_header *)p;
549 if (h->type == amd_iommu_target_ivhd_type) {
550 int ret = find_last_devid_from_ivhd(h);
551
552 if (ret)
553 return ret;
554 }
555 p += h->length;
556 }
557 WARN_ON(p != end);
558
559 return 0;
560 }
561
562 /****************************************************************************
563 *
564 * The following functions belong to the code path which parses the ACPI table
565 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
566 * data structures, initialize the device/alias/rlookup table and also
567 * basically initialize the hardware.
568 *
569 ****************************************************************************/
570
571 /*
572 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
573 * write commands to that buffer later and the IOMMU will execute them
574 * asynchronously
575 */
576 static int __init alloc_command_buffer(struct amd_iommu *iommu)
577 {
578 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
579 get_order(CMD_BUFFER_SIZE));
580
581 return iommu->cmd_buf ? 0 : -ENOMEM;
582 }
583
584 /*
585 * This function resets the command buffer if the IOMMU stopped fetching
586 * commands from it.
587 */
588 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
589 {
590 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
591
592 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
593 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
594 iommu->cmd_buf_head = 0;
595 iommu->cmd_buf_tail = 0;
596
597 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
598 }
599
600 /*
601 * This function writes the command buffer address to the hardware and
602 * enables it.
603 */
604 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
605 {
606 u64 entry;
607
608 BUG_ON(iommu->cmd_buf == NULL);
609
610 entry = iommu_virt_to_phys(iommu->cmd_buf);
611 entry |= MMIO_CMD_SIZE_512;
612
613 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
614 &entry, sizeof(entry));
615
616 amd_iommu_reset_cmd_buffer(iommu);
617 }
618
619 static void __init free_command_buffer(struct amd_iommu *iommu)
620 {
621 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
622 }
623
624 /* allocates the memory where the IOMMU will log its events to */
625 static int __init alloc_event_buffer(struct amd_iommu *iommu)
626 {
627 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
628 get_order(EVT_BUFFER_SIZE));
629
630 return iommu->evt_buf ? 0 : -ENOMEM;
631 }
632
633 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
634 {
635 u64 entry;
636
637 BUG_ON(iommu->evt_buf == NULL);
638
639 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
640
641 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
642 &entry, sizeof(entry));
643
644 /* set head and tail to zero manually */
645 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
646 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
647
648 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
649 }
650
651 static void __init free_event_buffer(struct amd_iommu *iommu)
652 {
653 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
654 }
655
656 /* allocates the memory where the IOMMU will log its events to */
657 static int __init alloc_ppr_log(struct amd_iommu *iommu)
658 {
659 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
660 get_order(PPR_LOG_SIZE));
661
662 return iommu->ppr_log ? 0 : -ENOMEM;
663 }
664
665 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
666 {
667 u64 entry;
668
669 if (iommu->ppr_log == NULL)
670 return;
671
672 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
673
674 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
675 &entry, sizeof(entry));
676
677 /* set head and tail to zero manually */
678 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
679 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
680
681 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
682 iommu_feature_enable(iommu, CONTROL_PPR_EN);
683 }
684
685 static void __init free_ppr_log(struct amd_iommu *iommu)
686 {
687 if (iommu->ppr_log == NULL)
688 return;
689
690 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
691 }
692
693 static void free_ga_log(struct amd_iommu *iommu)
694 {
695 #ifdef CONFIG_IRQ_REMAP
696 if (iommu->ga_log)
697 free_pages((unsigned long)iommu->ga_log,
698 get_order(GA_LOG_SIZE));
699 if (iommu->ga_log_tail)
700 free_pages((unsigned long)iommu->ga_log_tail,
701 get_order(8));
702 #endif
703 }
704
705 static int iommu_ga_log_enable(struct amd_iommu *iommu)
706 {
707 #ifdef CONFIG_IRQ_REMAP
708 u32 status, i;
709
710 if (!iommu->ga_log)
711 return -EINVAL;
712
713 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
714
715 /* Check if already running */
716 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
717 return 0;
718
719 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
720 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
721
722 for (i = 0; i < LOOP_TIMEOUT; ++i) {
723 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
724 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
725 break;
726 }
727
728 if (i >= LOOP_TIMEOUT)
729 return -EINVAL;
730 #endif /* CONFIG_IRQ_REMAP */
731 return 0;
732 }
733
734 #ifdef CONFIG_IRQ_REMAP
735 static int iommu_init_ga_log(struct amd_iommu *iommu)
736 {
737 u64 entry;
738
739 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
740 return 0;
741
742 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
743 get_order(GA_LOG_SIZE));
744 if (!iommu->ga_log)
745 goto err_out;
746
747 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
748 get_order(8));
749 if (!iommu->ga_log_tail)
750 goto err_out;
751
752 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
753 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
754 &entry, sizeof(entry));
755 entry = (iommu_virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
756 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
757 &entry, sizeof(entry));
758 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
759 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
760
761 return 0;
762 err_out:
763 free_ga_log(iommu);
764 return -EINVAL;
765 }
766 #endif /* CONFIG_IRQ_REMAP */
767
768 static int iommu_init_ga(struct amd_iommu *iommu)
769 {
770 int ret = 0;
771
772 #ifdef CONFIG_IRQ_REMAP
773 /* Note: We have already checked GASup from IVRS table.
774 * Now, we need to make sure that GAMSup is set.
775 */
776 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
777 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
778 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
779
780 ret = iommu_init_ga_log(iommu);
781 #endif /* CONFIG_IRQ_REMAP */
782
783 return ret;
784 }
785
786 static void iommu_enable_gt(struct amd_iommu *iommu)
787 {
788 if (!iommu_feature(iommu, FEATURE_GT))
789 return;
790
791 iommu_feature_enable(iommu, CONTROL_GT_EN);
792 }
793
794 /* sets a specific bit in the device table entry. */
795 static void set_dev_entry_bit(u16 devid, u8 bit)
796 {
797 int i = (bit >> 6) & 0x03;
798 int _bit = bit & 0x3f;
799
800 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
801 }
802
803 static int get_dev_entry_bit(u16 devid, u8 bit)
804 {
805 int i = (bit >> 6) & 0x03;
806 int _bit = bit & 0x3f;
807
808 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
809 }
810
811
812 void amd_iommu_apply_erratum_63(u16 devid)
813 {
814 int sysmgt;
815
816 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
817 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
818
819 if (sysmgt == 0x01)
820 set_dev_entry_bit(devid, DEV_ENTRY_IW);
821 }
822
823 /* Writes the specific IOMMU for a device into the rlookup table */
824 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
825 {
826 amd_iommu_rlookup_table[devid] = iommu;
827 }
828
829 /*
830 * This function takes the device specific flags read from the ACPI
831 * table and sets up the device table entry with that information
832 */
833 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
834 u16 devid, u32 flags, u32 ext_flags)
835 {
836 if (flags & ACPI_DEVFLAG_INITPASS)
837 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
838 if (flags & ACPI_DEVFLAG_EXTINT)
839 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
840 if (flags & ACPI_DEVFLAG_NMI)
841 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
842 if (flags & ACPI_DEVFLAG_SYSMGT1)
843 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
844 if (flags & ACPI_DEVFLAG_SYSMGT2)
845 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
846 if (flags & ACPI_DEVFLAG_LINT0)
847 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
848 if (flags & ACPI_DEVFLAG_LINT1)
849 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
850
851 amd_iommu_apply_erratum_63(devid);
852
853 set_iommu_for_device(iommu, devid);
854 }
855
856 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
857 {
858 struct devid_map *entry;
859 struct list_head *list;
860
861 if (type == IVHD_SPECIAL_IOAPIC)
862 list = &ioapic_map;
863 else if (type == IVHD_SPECIAL_HPET)
864 list = &hpet_map;
865 else
866 return -EINVAL;
867
868 list_for_each_entry(entry, list, list) {
869 if (!(entry->id == id && entry->cmd_line))
870 continue;
871
872 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
873 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
874
875 *devid = entry->devid;
876
877 return 0;
878 }
879
880 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
881 if (!entry)
882 return -ENOMEM;
883
884 entry->id = id;
885 entry->devid = *devid;
886 entry->cmd_line = cmd_line;
887
888 list_add_tail(&entry->list, list);
889
890 return 0;
891 }
892
893 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
894 bool cmd_line)
895 {
896 struct acpihid_map_entry *entry;
897 struct list_head *list = &acpihid_map;
898
899 list_for_each_entry(entry, list, list) {
900 if (strcmp(entry->hid, hid) ||
901 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
902 !entry->cmd_line)
903 continue;
904
905 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
906 hid, uid);
907 *devid = entry->devid;
908 return 0;
909 }
910
911 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
912 if (!entry)
913 return -ENOMEM;
914
915 memcpy(entry->uid, uid, strlen(uid));
916 memcpy(entry->hid, hid, strlen(hid));
917 entry->devid = *devid;
918 entry->cmd_line = cmd_line;
919 entry->root_devid = (entry->devid & (~0x7));
920
921 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
922 entry->cmd_line ? "cmd" : "ivrs",
923 entry->hid, entry->uid, entry->root_devid);
924
925 list_add_tail(&entry->list, list);
926 return 0;
927 }
928
929 static int __init add_early_maps(void)
930 {
931 int i, ret;
932
933 for (i = 0; i < early_ioapic_map_size; ++i) {
934 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
935 early_ioapic_map[i].id,
936 &early_ioapic_map[i].devid,
937 early_ioapic_map[i].cmd_line);
938 if (ret)
939 return ret;
940 }
941
942 for (i = 0; i < early_hpet_map_size; ++i) {
943 ret = add_special_device(IVHD_SPECIAL_HPET,
944 early_hpet_map[i].id,
945 &early_hpet_map[i].devid,
946 early_hpet_map[i].cmd_line);
947 if (ret)
948 return ret;
949 }
950
951 for (i = 0; i < early_acpihid_map_size; ++i) {
952 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
953 early_acpihid_map[i].uid,
954 &early_acpihid_map[i].devid,
955 early_acpihid_map[i].cmd_line);
956 if (ret)
957 return ret;
958 }
959
960 return 0;
961 }
962
963 /*
964 * Reads the device exclusion range from ACPI and initializes the IOMMU with
965 * it
966 */
967 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
968 {
969 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
970
971 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
972 return;
973
974 if (iommu) {
975 /*
976 * We only can configure exclusion ranges per IOMMU, not
977 * per device. But we can enable the exclusion range per
978 * device. This is done here
979 */
980 set_dev_entry_bit(devid, DEV_ENTRY_EX);
981 iommu->exclusion_start = m->range_start;
982 iommu->exclusion_length = m->range_length;
983 }
984 }
985
986 /*
987 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
988 * initializes the hardware and our data structures with it.
989 */
990 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
991 struct ivhd_header *h)
992 {
993 u8 *p = (u8 *)h;
994 u8 *end = p, flags = 0;
995 u16 devid = 0, devid_start = 0, devid_to = 0;
996 u32 dev_i, ext_flags = 0;
997 bool alias = false;
998 struct ivhd_entry *e;
999 u32 ivhd_size;
1000 int ret;
1001
1002
1003 ret = add_early_maps();
1004 if (ret)
1005 return ret;
1006
1007 /*
1008 * First save the recommended feature enable bits from ACPI
1009 */
1010 iommu->acpi_flags = h->flags;
1011
1012 /*
1013 * Done. Now parse the device entries
1014 */
1015 ivhd_size = get_ivhd_header_size(h);
1016 if (!ivhd_size) {
1017 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1018 return -EINVAL;
1019 }
1020
1021 p += ivhd_size;
1022
1023 end += h->length;
1024
1025
1026 while (p < end) {
1027 e = (struct ivhd_entry *)p;
1028 switch (e->type) {
1029 case IVHD_DEV_ALL:
1030
1031 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1032
1033 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1034 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1035 break;
1036 case IVHD_DEV_SELECT:
1037
1038 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1039 "flags: %02x\n",
1040 PCI_BUS_NUM(e->devid),
1041 PCI_SLOT(e->devid),
1042 PCI_FUNC(e->devid),
1043 e->flags);
1044
1045 devid = e->devid;
1046 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1047 break;
1048 case IVHD_DEV_SELECT_RANGE_START:
1049
1050 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1051 "devid: %02x:%02x.%x flags: %02x\n",
1052 PCI_BUS_NUM(e->devid),
1053 PCI_SLOT(e->devid),
1054 PCI_FUNC(e->devid),
1055 e->flags);
1056
1057 devid_start = e->devid;
1058 flags = e->flags;
1059 ext_flags = 0;
1060 alias = false;
1061 break;
1062 case IVHD_DEV_ALIAS:
1063
1064 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1065 "flags: %02x devid_to: %02x:%02x.%x\n",
1066 PCI_BUS_NUM(e->devid),
1067 PCI_SLOT(e->devid),
1068 PCI_FUNC(e->devid),
1069 e->flags,
1070 PCI_BUS_NUM(e->ext >> 8),
1071 PCI_SLOT(e->ext >> 8),
1072 PCI_FUNC(e->ext >> 8));
1073
1074 devid = e->devid;
1075 devid_to = e->ext >> 8;
1076 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1077 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1078 amd_iommu_alias_table[devid] = devid_to;
1079 break;
1080 case IVHD_DEV_ALIAS_RANGE:
1081
1082 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1083 "devid: %02x:%02x.%x flags: %02x "
1084 "devid_to: %02x:%02x.%x\n",
1085 PCI_BUS_NUM(e->devid),
1086 PCI_SLOT(e->devid),
1087 PCI_FUNC(e->devid),
1088 e->flags,
1089 PCI_BUS_NUM(e->ext >> 8),
1090 PCI_SLOT(e->ext >> 8),
1091 PCI_FUNC(e->ext >> 8));
1092
1093 devid_start = e->devid;
1094 flags = e->flags;
1095 devid_to = e->ext >> 8;
1096 ext_flags = 0;
1097 alias = true;
1098 break;
1099 case IVHD_DEV_EXT_SELECT:
1100
1101 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1102 "flags: %02x ext: %08x\n",
1103 PCI_BUS_NUM(e->devid),
1104 PCI_SLOT(e->devid),
1105 PCI_FUNC(e->devid),
1106 e->flags, e->ext);
1107
1108 devid = e->devid;
1109 set_dev_entry_from_acpi(iommu, devid, e->flags,
1110 e->ext);
1111 break;
1112 case IVHD_DEV_EXT_SELECT_RANGE:
1113
1114 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1115 "%02x:%02x.%x flags: %02x ext: %08x\n",
1116 PCI_BUS_NUM(e->devid),
1117 PCI_SLOT(e->devid),
1118 PCI_FUNC(e->devid),
1119 e->flags, e->ext);
1120
1121 devid_start = e->devid;
1122 flags = e->flags;
1123 ext_flags = e->ext;
1124 alias = false;
1125 break;
1126 case IVHD_DEV_RANGE_END:
1127
1128 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1129 PCI_BUS_NUM(e->devid),
1130 PCI_SLOT(e->devid),
1131 PCI_FUNC(e->devid));
1132
1133 devid = e->devid;
1134 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1135 if (alias) {
1136 amd_iommu_alias_table[dev_i] = devid_to;
1137 set_dev_entry_from_acpi(iommu,
1138 devid_to, flags, ext_flags);
1139 }
1140 set_dev_entry_from_acpi(iommu, dev_i,
1141 flags, ext_flags);
1142 }
1143 break;
1144 case IVHD_DEV_SPECIAL: {
1145 u8 handle, type;
1146 const char *var;
1147 u16 devid;
1148 int ret;
1149
1150 handle = e->ext & 0xff;
1151 devid = (e->ext >> 8) & 0xffff;
1152 type = (e->ext >> 24) & 0xff;
1153
1154 if (type == IVHD_SPECIAL_IOAPIC)
1155 var = "IOAPIC";
1156 else if (type == IVHD_SPECIAL_HPET)
1157 var = "HPET";
1158 else
1159 var = "UNKNOWN";
1160
1161 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1162 var, (int)handle,
1163 PCI_BUS_NUM(devid),
1164 PCI_SLOT(devid),
1165 PCI_FUNC(devid));
1166
1167 ret = add_special_device(type, handle, &devid, false);
1168 if (ret)
1169 return ret;
1170
1171 /*
1172 * add_special_device might update the devid in case a
1173 * command-line override is present. So call
1174 * set_dev_entry_from_acpi after add_special_device.
1175 */
1176 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1177
1178 break;
1179 }
1180 case IVHD_DEV_ACPI_HID: {
1181 u16 devid;
1182 u8 hid[ACPIHID_HID_LEN] = {0};
1183 u8 uid[ACPIHID_UID_LEN] = {0};
1184 int ret;
1185
1186 if (h->type != 0x40) {
1187 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1188 e->type);
1189 break;
1190 }
1191
1192 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1193 hid[ACPIHID_HID_LEN - 1] = '\0';
1194
1195 if (!(*hid)) {
1196 pr_err(FW_BUG "Invalid HID.\n");
1197 break;
1198 }
1199
1200 switch (e->uidf) {
1201 case UID_NOT_PRESENT:
1202
1203 if (e->uidl != 0)
1204 pr_warn(FW_BUG "Invalid UID length.\n");
1205
1206 break;
1207 case UID_IS_INTEGER:
1208
1209 sprintf(uid, "%d", e->uid);
1210
1211 break;
1212 case UID_IS_CHARACTER:
1213
1214 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1215 uid[ACPIHID_UID_LEN - 1] = '\0';
1216
1217 break;
1218 default:
1219 break;
1220 }
1221
1222 devid = e->devid;
1223 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1224 hid, uid,
1225 PCI_BUS_NUM(devid),
1226 PCI_SLOT(devid),
1227 PCI_FUNC(devid));
1228
1229 flags = e->flags;
1230
1231 ret = add_acpi_hid_device(hid, uid, &devid, false);
1232 if (ret)
1233 return ret;
1234
1235 /*
1236 * add_special_device might update the devid in case a
1237 * command-line override is present. So call
1238 * set_dev_entry_from_acpi after add_special_device.
1239 */
1240 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1241
1242 break;
1243 }
1244 default:
1245 break;
1246 }
1247
1248 p += ivhd_entry_length(p);
1249 }
1250
1251 return 0;
1252 }
1253
1254 static void __init free_iommu_one(struct amd_iommu *iommu)
1255 {
1256 free_command_buffer(iommu);
1257 free_event_buffer(iommu);
1258 free_ppr_log(iommu);
1259 free_ga_log(iommu);
1260 iommu_unmap_mmio_space(iommu);
1261 }
1262
1263 static void __init free_iommu_all(void)
1264 {
1265 struct amd_iommu *iommu, *next;
1266
1267 for_each_iommu_safe(iommu, next) {
1268 list_del(&iommu->list);
1269 free_iommu_one(iommu);
1270 kfree(iommu);
1271 }
1272 }
1273
1274 /*
1275 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1276 * Workaround:
1277 * BIOS should disable L2B micellaneous clock gating by setting
1278 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1279 */
1280 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1281 {
1282 u32 value;
1283
1284 if ((boot_cpu_data.x86 != 0x15) ||
1285 (boot_cpu_data.x86_model < 0x10) ||
1286 (boot_cpu_data.x86_model > 0x1f))
1287 return;
1288
1289 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1290 pci_read_config_dword(iommu->dev, 0xf4, &value);
1291
1292 if (value & BIT(2))
1293 return;
1294
1295 /* Select NB indirect register 0x90 and enable writing */
1296 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1297
1298 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1299 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1300 dev_name(&iommu->dev->dev));
1301
1302 /* Clear the enable writing bit */
1303 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1304 }
1305
1306 /*
1307 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1308 * Workaround:
1309 * BIOS should enable ATS write permission check by setting
1310 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1311 */
1312 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1313 {
1314 u32 value;
1315
1316 if ((boot_cpu_data.x86 != 0x15) ||
1317 (boot_cpu_data.x86_model < 0x30) ||
1318 (boot_cpu_data.x86_model > 0x3f))
1319 return;
1320
1321 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1322 value = iommu_read_l2(iommu, 0x47);
1323
1324 if (value & BIT(0))
1325 return;
1326
1327 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1328 iommu_write_l2(iommu, 0x47, value | BIT(0));
1329
1330 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1331 dev_name(&iommu->dev->dev));
1332 }
1333
1334 /*
1335 * This function clues the initialization function for one IOMMU
1336 * together and also allocates the command buffer and programs the
1337 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1338 */
1339 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1340 {
1341 int ret;
1342
1343 spin_lock_init(&iommu->lock);
1344
1345 /* Add IOMMU to internal data structures */
1346 list_add_tail(&iommu->list, &amd_iommu_list);
1347 iommu->index = amd_iommus_present++;
1348
1349 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1350 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1351 return -ENOSYS;
1352 }
1353
1354 /* Index is fine - add IOMMU to the array */
1355 amd_iommus[iommu->index] = iommu;
1356
1357 /*
1358 * Copy data from ACPI table entry to the iommu struct
1359 */
1360 iommu->devid = h->devid;
1361 iommu->cap_ptr = h->cap_ptr;
1362 iommu->pci_seg = h->pci_seg;
1363 iommu->mmio_phys = h->mmio_phys;
1364
1365 switch (h->type) {
1366 case 0x10:
1367 /* Check if IVHD EFR contains proper max banks/counters */
1368 if ((h->efr_attr != 0) &&
1369 ((h->efr_attr & (0xF << 13)) != 0) &&
1370 ((h->efr_attr & (0x3F << 17)) != 0))
1371 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1372 else
1373 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1374 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1375 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1376 break;
1377 case 0x11:
1378 case 0x40:
1379 if (h->efr_reg & (1 << 9))
1380 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1381 else
1382 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1383 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1384 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1385 break;
1386 default:
1387 return -EINVAL;
1388 }
1389
1390 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1391 iommu->mmio_phys_end);
1392 if (!iommu->mmio_base)
1393 return -ENOMEM;
1394
1395 if (alloc_command_buffer(iommu))
1396 return -ENOMEM;
1397
1398 if (alloc_event_buffer(iommu))
1399 return -ENOMEM;
1400
1401 iommu->int_enabled = false;
1402
1403 ret = init_iommu_from_acpi(iommu, h);
1404 if (ret)
1405 return ret;
1406
1407 ret = amd_iommu_create_irq_domain(iommu);
1408 if (ret)
1409 return ret;
1410
1411 /*
1412 * Make sure IOMMU is not considered to translate itself. The IVRS
1413 * table tells us so, but this is a lie!
1414 */
1415 amd_iommu_rlookup_table[iommu->devid] = NULL;
1416
1417 return 0;
1418 }
1419
1420 /**
1421 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1422 * @ivrs Pointer to the IVRS header
1423 *
1424 * This function search through all IVDB of the maximum supported IVHD
1425 */
1426 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1427 {
1428 u8 *base = (u8 *)ivrs;
1429 struct ivhd_header *ivhd = (struct ivhd_header *)
1430 (base + IVRS_HEADER_LENGTH);
1431 u8 last_type = ivhd->type;
1432 u16 devid = ivhd->devid;
1433
1434 while (((u8 *)ivhd - base < ivrs->length) &&
1435 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1436 u8 *p = (u8 *) ivhd;
1437
1438 if (ivhd->devid == devid)
1439 last_type = ivhd->type;
1440 ivhd = (struct ivhd_header *)(p + ivhd->length);
1441 }
1442
1443 return last_type;
1444 }
1445
1446 /*
1447 * Iterates over all IOMMU entries in the ACPI table, allocates the
1448 * IOMMU structure and initializes it with init_iommu_one()
1449 */
1450 static int __init init_iommu_all(struct acpi_table_header *table)
1451 {
1452 u8 *p = (u8 *)table, *end = (u8 *)table;
1453 struct ivhd_header *h;
1454 struct amd_iommu *iommu;
1455 int ret;
1456
1457 end += table->length;
1458 p += IVRS_HEADER_LENGTH;
1459
1460 while (p < end) {
1461 h = (struct ivhd_header *)p;
1462 if (*p == amd_iommu_target_ivhd_type) {
1463
1464 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1465 "seg: %d flags: %01x info %04x\n",
1466 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1467 PCI_FUNC(h->devid), h->cap_ptr,
1468 h->pci_seg, h->flags, h->info);
1469 DUMP_printk(" mmio-addr: %016llx\n",
1470 h->mmio_phys);
1471
1472 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1473 if (iommu == NULL)
1474 return -ENOMEM;
1475
1476 ret = init_iommu_one(iommu, h);
1477 if (ret)
1478 return ret;
1479 }
1480 p += h->length;
1481
1482 }
1483 WARN_ON(p != end);
1484
1485 return 0;
1486 }
1487
1488 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
1489 u8 fxn, u64 *value, bool is_write);
1490
1491 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1492 {
1493 u64 val = 0xabcd, val2 = 0;
1494
1495 if (!iommu_feature(iommu, FEATURE_PC))
1496 return;
1497
1498 amd_iommu_pc_present = true;
1499
1500 /* Check if the performance counters can be written to */
1501 if ((iommu_pc_get_set_reg(iommu, 0, 0, 0, &val, true)) ||
1502 (iommu_pc_get_set_reg(iommu, 0, 0, 0, &val2, false)) ||
1503 (val != val2)) {
1504 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1505 amd_iommu_pc_present = false;
1506 return;
1507 }
1508
1509 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1510
1511 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1512 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1513 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1514 }
1515
1516 static ssize_t amd_iommu_show_cap(struct device *dev,
1517 struct device_attribute *attr,
1518 char *buf)
1519 {
1520 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1521 return sprintf(buf, "%x\n", iommu->cap);
1522 }
1523 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1524
1525 static ssize_t amd_iommu_show_features(struct device *dev,
1526 struct device_attribute *attr,
1527 char *buf)
1528 {
1529 struct amd_iommu *iommu = dev_to_amd_iommu(dev);
1530 return sprintf(buf, "%llx\n", iommu->features);
1531 }
1532 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1533
1534 static struct attribute *amd_iommu_attrs[] = {
1535 &dev_attr_cap.attr,
1536 &dev_attr_features.attr,
1537 NULL,
1538 };
1539
1540 static struct attribute_group amd_iommu_group = {
1541 .name = "amd-iommu",
1542 .attrs = amd_iommu_attrs,
1543 };
1544
1545 static const struct attribute_group *amd_iommu_groups[] = {
1546 &amd_iommu_group,
1547 NULL,
1548 };
1549
1550 static int iommu_init_pci(struct amd_iommu *iommu)
1551 {
1552 int cap_ptr = iommu->cap_ptr;
1553 u32 range, misc, low, high;
1554 int ret;
1555
1556 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1557 iommu->devid & 0xff);
1558 if (!iommu->dev)
1559 return -ENODEV;
1560
1561 /* Prevent binding other PCI device drivers to IOMMU devices */
1562 iommu->dev->match_driver = false;
1563
1564 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1565 &iommu->cap);
1566 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1567 &range);
1568 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1569 &misc);
1570
1571 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1572 amd_iommu_iotlb_sup = false;
1573
1574 /* read extended feature bits */
1575 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1576 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1577
1578 iommu->features = ((u64)high << 32) | low;
1579
1580 if (iommu_feature(iommu, FEATURE_GT)) {
1581 int glxval;
1582 u32 max_pasid;
1583 u64 pasmax;
1584
1585 pasmax = iommu->features & FEATURE_PASID_MASK;
1586 pasmax >>= FEATURE_PASID_SHIFT;
1587 max_pasid = (1 << (pasmax + 1)) - 1;
1588
1589 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1590
1591 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1592
1593 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1594 glxval >>= FEATURE_GLXVAL_SHIFT;
1595
1596 if (amd_iommu_max_glx_val == -1)
1597 amd_iommu_max_glx_val = glxval;
1598 else
1599 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1600 }
1601
1602 if (iommu_feature(iommu, FEATURE_GT) &&
1603 iommu_feature(iommu, FEATURE_PPR)) {
1604 iommu->is_iommu_v2 = true;
1605 amd_iommu_v2_present = true;
1606 }
1607
1608 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1609 return -ENOMEM;
1610
1611 ret = iommu_init_ga(iommu);
1612 if (ret)
1613 return ret;
1614
1615 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1616 amd_iommu_np_cache = true;
1617
1618 init_iommu_perf_ctr(iommu);
1619
1620 if (is_rd890_iommu(iommu->dev)) {
1621 int i, j;
1622
1623 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1624 PCI_DEVFN(0, 0));
1625
1626 /*
1627 * Some rd890 systems may not be fully reconfigured by the
1628 * BIOS, so it's necessary for us to store this information so
1629 * it can be reprogrammed on resume
1630 */
1631 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1632 &iommu->stored_addr_lo);
1633 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1634 &iommu->stored_addr_hi);
1635
1636 /* Low bit locks writes to configuration space */
1637 iommu->stored_addr_lo &= ~1;
1638
1639 for (i = 0; i < 6; i++)
1640 for (j = 0; j < 0x12; j++)
1641 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1642
1643 for (i = 0; i < 0x83; i++)
1644 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1645 }
1646
1647 amd_iommu_erratum_746_workaround(iommu);
1648 amd_iommu_ats_write_check_workaround(iommu);
1649
1650 iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev,
1651 amd_iommu_groups, "ivhd%d", iommu->index);
1652 iommu_device_set_ops(&iommu->iommu, &amd_iommu_ops);
1653 iommu_device_register(&iommu->iommu);
1654
1655 return pci_enable_device(iommu->dev);
1656 }
1657
1658 static void print_iommu_info(void)
1659 {
1660 static const char * const feat_str[] = {
1661 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1662 "IA", "GA", "HE", "PC"
1663 };
1664 struct amd_iommu *iommu;
1665
1666 for_each_iommu(iommu) {
1667 int i;
1668
1669 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1670 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1671
1672 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1673 pr_info("AMD-Vi: Extended features (%#llx):\n",
1674 iommu->features);
1675 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1676 if (iommu_feature(iommu, (1ULL << i)))
1677 pr_cont(" %s", feat_str[i]);
1678 }
1679
1680 if (iommu->features & FEATURE_GAM_VAPIC)
1681 pr_cont(" GA_vAPIC");
1682
1683 pr_cont("\n");
1684 }
1685 }
1686 if (irq_remapping_enabled) {
1687 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1688 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1689 pr_info("AMD-Vi: virtual APIC enabled\n");
1690 }
1691 }
1692
1693 static int __init amd_iommu_init_pci(void)
1694 {
1695 struct amd_iommu *iommu;
1696 int ret = 0;
1697
1698 for_each_iommu(iommu) {
1699 ret = iommu_init_pci(iommu);
1700 if (ret)
1701 break;
1702 }
1703
1704 /*
1705 * Order is important here to make sure any unity map requirements are
1706 * fulfilled. The unity mappings are created and written to the device
1707 * table during the amd_iommu_init_api() call.
1708 *
1709 * After that we call init_device_table_dma() to make sure any
1710 * uninitialized DTE will block DMA, and in the end we flush the caches
1711 * of all IOMMUs to make sure the changes to the device table are
1712 * active.
1713 */
1714 ret = amd_iommu_init_api();
1715
1716 init_device_table_dma();
1717
1718 for_each_iommu(iommu)
1719 iommu_flush_all_caches(iommu);
1720
1721 if (!ret)
1722 print_iommu_info();
1723
1724 return ret;
1725 }
1726
1727 /****************************************************************************
1728 *
1729 * The following functions initialize the MSI interrupts for all IOMMUs
1730 * in the system. It's a bit challenging because there could be multiple
1731 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1732 * pci_dev.
1733 *
1734 ****************************************************************************/
1735
1736 static int iommu_setup_msi(struct amd_iommu *iommu)
1737 {
1738 int r;
1739
1740 r = pci_enable_msi(iommu->dev);
1741 if (r)
1742 return r;
1743
1744 r = request_threaded_irq(iommu->dev->irq,
1745 amd_iommu_int_handler,
1746 amd_iommu_int_thread,
1747 0, "AMD-Vi",
1748 iommu);
1749
1750 if (r) {
1751 pci_disable_msi(iommu->dev);
1752 return r;
1753 }
1754
1755 iommu->int_enabled = true;
1756
1757 return 0;
1758 }
1759
1760 static int iommu_init_msi(struct amd_iommu *iommu)
1761 {
1762 int ret;
1763
1764 if (iommu->int_enabled)
1765 goto enable_faults;
1766
1767 if (iommu->dev->msi_cap)
1768 ret = iommu_setup_msi(iommu);
1769 else
1770 ret = -ENODEV;
1771
1772 if (ret)
1773 return ret;
1774
1775 enable_faults:
1776 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1777
1778 if (iommu->ppr_log != NULL)
1779 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1780
1781 iommu_ga_log_enable(iommu);
1782
1783 return 0;
1784 }
1785
1786 /****************************************************************************
1787 *
1788 * The next functions belong to the third pass of parsing the ACPI
1789 * table. In this last pass the memory mapping requirements are
1790 * gathered (like exclusion and unity mapping ranges).
1791 *
1792 ****************************************************************************/
1793
1794 static void __init free_unity_maps(void)
1795 {
1796 struct unity_map_entry *entry, *next;
1797
1798 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1799 list_del(&entry->list);
1800 kfree(entry);
1801 }
1802 }
1803
1804 /* called when we find an exclusion range definition in ACPI */
1805 static int __init init_exclusion_range(struct ivmd_header *m)
1806 {
1807 int i;
1808
1809 switch (m->type) {
1810 case ACPI_IVMD_TYPE:
1811 set_device_exclusion_range(m->devid, m);
1812 break;
1813 case ACPI_IVMD_TYPE_ALL:
1814 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1815 set_device_exclusion_range(i, m);
1816 break;
1817 case ACPI_IVMD_TYPE_RANGE:
1818 for (i = m->devid; i <= m->aux; ++i)
1819 set_device_exclusion_range(i, m);
1820 break;
1821 default:
1822 break;
1823 }
1824
1825 return 0;
1826 }
1827
1828 /* called for unity map ACPI definition */
1829 static int __init init_unity_map_range(struct ivmd_header *m)
1830 {
1831 struct unity_map_entry *e = NULL;
1832 char *s;
1833
1834 e = kzalloc(sizeof(*e), GFP_KERNEL);
1835 if (e == NULL)
1836 return -ENOMEM;
1837
1838 switch (m->type) {
1839 default:
1840 kfree(e);
1841 return 0;
1842 case ACPI_IVMD_TYPE:
1843 s = "IVMD_TYPEi\t\t\t";
1844 e->devid_start = e->devid_end = m->devid;
1845 break;
1846 case ACPI_IVMD_TYPE_ALL:
1847 s = "IVMD_TYPE_ALL\t\t";
1848 e->devid_start = 0;
1849 e->devid_end = amd_iommu_last_bdf;
1850 break;
1851 case ACPI_IVMD_TYPE_RANGE:
1852 s = "IVMD_TYPE_RANGE\t\t";
1853 e->devid_start = m->devid;
1854 e->devid_end = m->aux;
1855 break;
1856 }
1857 e->address_start = PAGE_ALIGN(m->range_start);
1858 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1859 e->prot = m->flags >> 1;
1860
1861 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1862 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1863 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1864 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1865 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1866 e->address_start, e->address_end, m->flags);
1867
1868 list_add_tail(&e->list, &amd_iommu_unity_map);
1869
1870 return 0;
1871 }
1872
1873 /* iterates over all memory definitions we find in the ACPI table */
1874 static int __init init_memory_definitions(struct acpi_table_header *table)
1875 {
1876 u8 *p = (u8 *)table, *end = (u8 *)table;
1877 struct ivmd_header *m;
1878
1879 end += table->length;
1880 p += IVRS_HEADER_LENGTH;
1881
1882 while (p < end) {
1883 m = (struct ivmd_header *)p;
1884 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1885 init_exclusion_range(m);
1886 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1887 init_unity_map_range(m);
1888
1889 p += m->length;
1890 }
1891
1892 return 0;
1893 }
1894
1895 /*
1896 * Init the device table to not allow DMA access for devices and
1897 * suppress all page faults
1898 */
1899 static void init_device_table_dma(void)
1900 {
1901 u32 devid;
1902
1903 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1904 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1905 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1906 /*
1907 * In kdump kernels in-flight DMA from the old kernel might
1908 * cause IO_PAGE_FAULTs. There are no reports that a kdump
1909 * actually failed because of that, so just disable fault
1910 * reporting in the hardware to get rid of the messages
1911 */
1912 if (is_kdump_kernel())
1913 set_dev_entry_bit(devid, DEV_ENTRY_NO_PAGE_FAULT);
1914 }
1915 }
1916
1917 static void __init uninit_device_table_dma(void)
1918 {
1919 u32 devid;
1920
1921 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1922 amd_iommu_dev_table[devid].data[0] = 0ULL;
1923 amd_iommu_dev_table[devid].data[1] = 0ULL;
1924 }
1925 }
1926
1927 static void init_device_table(void)
1928 {
1929 u32 devid;
1930
1931 if (!amd_iommu_irq_remap)
1932 return;
1933
1934 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1935 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1936 }
1937
1938 static void iommu_init_flags(struct amd_iommu *iommu)
1939 {
1940 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1941 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1942 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1943
1944 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1945 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1946 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1947
1948 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1949 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1950 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1951
1952 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1953 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1954 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1955
1956 /*
1957 * make IOMMU memory accesses cache coherent
1958 */
1959 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1960
1961 /* Set IOTLB invalidation timeout to 1s */
1962 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1963 }
1964
1965 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1966 {
1967 int i, j;
1968 u32 ioc_feature_control;
1969 struct pci_dev *pdev = iommu->root_pdev;
1970
1971 /* RD890 BIOSes may not have completely reconfigured the iommu */
1972 if (!is_rd890_iommu(iommu->dev) || !pdev)
1973 return;
1974
1975 /*
1976 * First, we need to ensure that the iommu is enabled. This is
1977 * controlled by a register in the northbridge
1978 */
1979
1980 /* Select Northbridge indirect register 0x75 and enable writing */
1981 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1982 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1983
1984 /* Enable the iommu */
1985 if (!(ioc_feature_control & 0x1))
1986 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1987
1988 /* Restore the iommu BAR */
1989 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1990 iommu->stored_addr_lo);
1991 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1992 iommu->stored_addr_hi);
1993
1994 /* Restore the l1 indirect regs for each of the 6 l1s */
1995 for (i = 0; i < 6; i++)
1996 for (j = 0; j < 0x12; j++)
1997 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1998
1999 /* Restore the l2 indirect regs */
2000 for (i = 0; i < 0x83; i++)
2001 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
2002
2003 /* Lock PCI setup registers */
2004 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
2005 iommu->stored_addr_lo | 1);
2006 }
2007
2008 static void iommu_enable_ga(struct amd_iommu *iommu)
2009 {
2010 #ifdef CONFIG_IRQ_REMAP
2011 switch (amd_iommu_guest_ir) {
2012 case AMD_IOMMU_GUEST_IR_VAPIC:
2013 iommu_feature_enable(iommu, CONTROL_GAM_EN);
2014 /* Fall through */
2015 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
2016 iommu_feature_enable(iommu, CONTROL_GA_EN);
2017 iommu->irte_ops = &irte_128_ops;
2018 break;
2019 default:
2020 iommu->irte_ops = &irte_32_ops;
2021 break;
2022 }
2023 #endif
2024 }
2025
2026 /*
2027 * This function finally enables all IOMMUs found in the system after
2028 * they have been initialized
2029 */
2030 static void early_enable_iommus(void)
2031 {
2032 struct amd_iommu *iommu;
2033
2034 for_each_iommu(iommu) {
2035 iommu_disable(iommu);
2036 iommu_init_flags(iommu);
2037 iommu_set_device_table(iommu);
2038 iommu_enable_command_buffer(iommu);
2039 iommu_enable_event_buffer(iommu);
2040 iommu_set_exclusion_range(iommu);
2041 iommu_enable_ga(iommu);
2042 iommu_enable(iommu);
2043 iommu_flush_all_caches(iommu);
2044 }
2045
2046 #ifdef CONFIG_IRQ_REMAP
2047 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2048 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2049 #endif
2050 }
2051
2052 static void enable_iommus_v2(void)
2053 {
2054 struct amd_iommu *iommu;
2055
2056 for_each_iommu(iommu) {
2057 iommu_enable_ppr_log(iommu);
2058 iommu_enable_gt(iommu);
2059 }
2060 }
2061
2062 static void enable_iommus(void)
2063 {
2064 early_enable_iommus();
2065
2066 enable_iommus_v2();
2067 }
2068
2069 static void disable_iommus(void)
2070 {
2071 struct amd_iommu *iommu;
2072
2073 for_each_iommu(iommu)
2074 iommu_disable(iommu);
2075
2076 #ifdef CONFIG_IRQ_REMAP
2077 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2078 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2079 #endif
2080 }
2081
2082 /*
2083 * Suspend/Resume support
2084 * disable suspend until real resume implemented
2085 */
2086
2087 static void amd_iommu_resume(void)
2088 {
2089 struct amd_iommu *iommu;
2090
2091 for_each_iommu(iommu)
2092 iommu_apply_resume_quirks(iommu);
2093
2094 /* re-load the hardware */
2095 enable_iommus();
2096
2097 amd_iommu_enable_interrupts();
2098 }
2099
2100 static int amd_iommu_suspend(void)
2101 {
2102 /* disable IOMMUs to go out of the way for BIOS */
2103 disable_iommus();
2104
2105 return 0;
2106 }
2107
2108 static struct syscore_ops amd_iommu_syscore_ops = {
2109 .suspend = amd_iommu_suspend,
2110 .resume = amd_iommu_resume,
2111 };
2112
2113 static void __init free_iommu_resources(void)
2114 {
2115 kmemleak_free(irq_lookup_table);
2116 free_pages((unsigned long)irq_lookup_table,
2117 get_order(rlookup_table_size));
2118 irq_lookup_table = NULL;
2119
2120 kmem_cache_destroy(amd_iommu_irq_cache);
2121 amd_iommu_irq_cache = NULL;
2122
2123 free_pages((unsigned long)amd_iommu_rlookup_table,
2124 get_order(rlookup_table_size));
2125 amd_iommu_rlookup_table = NULL;
2126
2127 free_pages((unsigned long)amd_iommu_alias_table,
2128 get_order(alias_table_size));
2129 amd_iommu_alias_table = NULL;
2130
2131 free_pages((unsigned long)amd_iommu_dev_table,
2132 get_order(dev_table_size));
2133 amd_iommu_dev_table = NULL;
2134
2135 free_iommu_all();
2136
2137 #ifdef CONFIG_GART_IOMMU
2138 /*
2139 * We failed to initialize the AMD IOMMU - try fallback to GART
2140 * if possible.
2141 */
2142 gart_iommu_init();
2143
2144 #endif
2145 }
2146
2147 /* SB IOAPIC is always on this device in AMD systems */
2148 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2149
2150 static bool __init check_ioapic_information(void)
2151 {
2152 const char *fw_bug = FW_BUG;
2153 bool ret, has_sb_ioapic;
2154 int idx;
2155
2156 has_sb_ioapic = false;
2157 ret = false;
2158
2159 /*
2160 * If we have map overrides on the kernel command line the
2161 * messages in this function might not describe firmware bugs
2162 * anymore - so be careful
2163 */
2164 if (cmdline_maps)
2165 fw_bug = "";
2166
2167 for (idx = 0; idx < nr_ioapics; idx++) {
2168 int devid, id = mpc_ioapic_id(idx);
2169
2170 devid = get_ioapic_devid(id);
2171 if (devid < 0) {
2172 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2173 fw_bug, id);
2174 ret = false;
2175 } else if (devid == IOAPIC_SB_DEVID) {
2176 has_sb_ioapic = true;
2177 ret = true;
2178 }
2179 }
2180
2181 if (!has_sb_ioapic) {
2182 /*
2183 * We expect the SB IOAPIC to be listed in the IVRS
2184 * table. The system timer is connected to the SB IOAPIC
2185 * and if we don't have it in the list the system will
2186 * panic at boot time. This situation usually happens
2187 * when the BIOS is buggy and provides us the wrong
2188 * device id for the IOAPIC in the system.
2189 */
2190 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2191 }
2192
2193 if (!ret)
2194 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2195
2196 return ret;
2197 }
2198
2199 static void __init free_dma_resources(void)
2200 {
2201 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2202 get_order(MAX_DOMAIN_ID/8));
2203 amd_iommu_pd_alloc_bitmap = NULL;
2204
2205 free_unity_maps();
2206 }
2207
2208 /*
2209 * This is the hardware init function for AMD IOMMU in the system.
2210 * This function is called either from amd_iommu_init or from the interrupt
2211 * remapping setup code.
2212 *
2213 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2214 * four times:
2215 *
2216 * 1 pass) Discover the most comprehensive IVHD type to use.
2217 *
2218 * 2 pass) Find the highest PCI device id the driver has to handle.
2219 * Upon this information the size of the data structures is
2220 * determined that needs to be allocated.
2221 *
2222 * 3 pass) Initialize the data structures just allocated with the
2223 * information in the ACPI table about available AMD IOMMUs
2224 * in the system. It also maps the PCI devices in the
2225 * system to specific IOMMUs
2226 *
2227 * 4 pass) After the basic data structures are allocated and
2228 * initialized we update them with information about memory
2229 * remapping requirements parsed out of the ACPI table in
2230 * this last pass.
2231 *
2232 * After everything is set up the IOMMUs are enabled and the necessary
2233 * hotplug and suspend notifiers are registered.
2234 */
2235 static int __init early_amd_iommu_init(void)
2236 {
2237 struct acpi_table_header *ivrs_base;
2238 acpi_status status;
2239 int i, remap_cache_sz, ret = 0;
2240
2241 if (!amd_iommu_detected)
2242 return -ENODEV;
2243
2244 status = acpi_get_table("IVRS", 0, &ivrs_base);
2245 if (status == AE_NOT_FOUND)
2246 return -ENODEV;
2247 else if (ACPI_FAILURE(status)) {
2248 const char *err = acpi_format_exception(status);
2249 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2250 return -EINVAL;
2251 }
2252
2253 /*
2254 * Validate checksum here so we don't need to do it when
2255 * we actually parse the table
2256 */
2257 ret = check_ivrs_checksum(ivrs_base);
2258 if (ret)
2259 goto out;
2260
2261 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2262 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2263
2264 /*
2265 * First parse ACPI tables to find the largest Bus/Dev/Func
2266 * we need to handle. Upon this information the shared data
2267 * structures for the IOMMUs in the system will be allocated
2268 */
2269 ret = find_last_devid_acpi(ivrs_base);
2270 if (ret)
2271 goto out;
2272
2273 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2274 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2275 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2276
2277 /* Device table - directly used by all IOMMUs */
2278 ret = -ENOMEM;
2279 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2280 get_order(dev_table_size));
2281 if (amd_iommu_dev_table == NULL)
2282 goto out;
2283
2284 /*
2285 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2286 * IOMMU see for that device
2287 */
2288 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2289 get_order(alias_table_size));
2290 if (amd_iommu_alias_table == NULL)
2291 goto out;
2292
2293 /* IOMMU rlookup table - find the IOMMU for a specific device */
2294 amd_iommu_rlookup_table = (void *)__get_free_pages(
2295 GFP_KERNEL | __GFP_ZERO,
2296 get_order(rlookup_table_size));
2297 if (amd_iommu_rlookup_table == NULL)
2298 goto out;
2299
2300 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2301 GFP_KERNEL | __GFP_ZERO,
2302 get_order(MAX_DOMAIN_ID/8));
2303 if (amd_iommu_pd_alloc_bitmap == NULL)
2304 goto out;
2305
2306 /*
2307 * let all alias entries point to itself
2308 */
2309 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2310 amd_iommu_alias_table[i] = i;
2311
2312 /*
2313 * never allocate domain 0 because its used as the non-allocated and
2314 * error value placeholder
2315 */
2316 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2317
2318 spin_lock_init(&amd_iommu_pd_lock);
2319
2320 /*
2321 * now the data structures are allocated and basically initialized
2322 * start the real acpi table scan
2323 */
2324 ret = init_iommu_all(ivrs_base);
2325 if (ret)
2326 goto out;
2327
2328 /* Disable any previously enabled IOMMUs */
2329 disable_iommus();
2330
2331 if (amd_iommu_irq_remap)
2332 amd_iommu_irq_remap = check_ioapic_information();
2333
2334 if (amd_iommu_irq_remap) {
2335 /*
2336 * Interrupt remapping enabled, create kmem_cache for the
2337 * remapping tables.
2338 */
2339 ret = -ENOMEM;
2340 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2341 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2342 else
2343 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2344 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2345 remap_cache_sz,
2346 IRQ_TABLE_ALIGNMENT,
2347 0, NULL);
2348 if (!amd_iommu_irq_cache)
2349 goto out;
2350
2351 irq_lookup_table = (void *)__get_free_pages(
2352 GFP_KERNEL | __GFP_ZERO,
2353 get_order(rlookup_table_size));
2354 kmemleak_alloc(irq_lookup_table, rlookup_table_size,
2355 1, GFP_KERNEL);
2356 if (!irq_lookup_table)
2357 goto out;
2358 }
2359
2360 ret = init_memory_definitions(ivrs_base);
2361 if (ret)
2362 goto out;
2363
2364 /* init the device table */
2365 init_device_table();
2366
2367 out:
2368 /* Don't leak any ACPI memory */
2369 acpi_put_table(ivrs_base);
2370 ivrs_base = NULL;
2371
2372 return ret;
2373 }
2374
2375 static int amd_iommu_enable_interrupts(void)
2376 {
2377 struct amd_iommu *iommu;
2378 int ret = 0;
2379
2380 for_each_iommu(iommu) {
2381 ret = iommu_init_msi(iommu);
2382 if (ret)
2383 goto out;
2384 }
2385
2386 out:
2387 return ret;
2388 }
2389
2390 static bool detect_ivrs(void)
2391 {
2392 struct acpi_table_header *ivrs_base;
2393 acpi_status status;
2394
2395 status = acpi_get_table("IVRS", 0, &ivrs_base);
2396 if (status == AE_NOT_FOUND)
2397 return false;
2398 else if (ACPI_FAILURE(status)) {
2399 const char *err = acpi_format_exception(status);
2400 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2401 return false;
2402 }
2403
2404 acpi_put_table(ivrs_base);
2405
2406 /* Make sure ACS will be enabled during PCI probe */
2407 pci_request_acs();
2408
2409 return true;
2410 }
2411
2412 /****************************************************************************
2413 *
2414 * AMD IOMMU Initialization State Machine
2415 *
2416 ****************************************************************************/
2417
2418 static int __init state_next(void)
2419 {
2420 int ret = 0;
2421
2422 switch (init_state) {
2423 case IOMMU_START_STATE:
2424 if (!detect_ivrs()) {
2425 init_state = IOMMU_NOT_FOUND;
2426 ret = -ENODEV;
2427 } else {
2428 init_state = IOMMU_IVRS_DETECTED;
2429 }
2430 break;
2431 case IOMMU_IVRS_DETECTED:
2432 ret = early_amd_iommu_init();
2433 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2434 if (init_state == IOMMU_ACPI_FINISHED && amd_iommu_disabled) {
2435 pr_info("AMD-Vi: AMD IOMMU disabled on kernel command-line\n");
2436 free_dma_resources();
2437 free_iommu_resources();
2438 init_state = IOMMU_CMDLINE_DISABLED;
2439 ret = -EINVAL;
2440 }
2441 break;
2442 case IOMMU_ACPI_FINISHED:
2443 early_enable_iommus();
2444 register_syscore_ops(&amd_iommu_syscore_ops);
2445 x86_platform.iommu_shutdown = disable_iommus;
2446 init_state = IOMMU_ENABLED;
2447 break;
2448 case IOMMU_ENABLED:
2449 ret = amd_iommu_init_pci();
2450 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2451 enable_iommus_v2();
2452 break;
2453 case IOMMU_PCI_INIT:
2454 ret = amd_iommu_enable_interrupts();
2455 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2456 break;
2457 case IOMMU_INTERRUPTS_EN:
2458 ret = amd_iommu_init_dma_ops();
2459 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2460 break;
2461 case IOMMU_DMA_OPS:
2462 init_state = IOMMU_INITIALIZED;
2463 break;
2464 case IOMMU_INITIALIZED:
2465 /* Nothing to do */
2466 break;
2467 case IOMMU_NOT_FOUND:
2468 case IOMMU_INIT_ERROR:
2469 case IOMMU_CMDLINE_DISABLED:
2470 /* Error states => do nothing */
2471 ret = -EINVAL;
2472 break;
2473 default:
2474 /* Unknown state */
2475 BUG();
2476 }
2477
2478 return ret;
2479 }
2480
2481 static int __init iommu_go_to_state(enum iommu_init_state state)
2482 {
2483 int ret = -EINVAL;
2484
2485 while (init_state != state) {
2486 if (init_state == IOMMU_NOT_FOUND ||
2487 init_state == IOMMU_INIT_ERROR ||
2488 init_state == IOMMU_CMDLINE_DISABLED)
2489 break;
2490 ret = state_next();
2491 }
2492
2493 return ret;
2494 }
2495
2496 #ifdef CONFIG_IRQ_REMAP
2497 int __init amd_iommu_prepare(void)
2498 {
2499 int ret;
2500
2501 amd_iommu_irq_remap = true;
2502
2503 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2504 if (ret)
2505 return ret;
2506 return amd_iommu_irq_remap ? 0 : -ENODEV;
2507 }
2508
2509 int __init amd_iommu_enable(void)
2510 {
2511 int ret;
2512
2513 ret = iommu_go_to_state(IOMMU_ENABLED);
2514 if (ret)
2515 return ret;
2516
2517 irq_remapping_enabled = 1;
2518
2519 return 0;
2520 }
2521
2522 void amd_iommu_disable(void)
2523 {
2524 amd_iommu_suspend();
2525 }
2526
2527 int amd_iommu_reenable(int mode)
2528 {
2529 amd_iommu_resume();
2530
2531 return 0;
2532 }
2533
2534 int __init amd_iommu_enable_faulting(void)
2535 {
2536 /* We enable MSI later when PCI is initialized */
2537 return 0;
2538 }
2539 #endif
2540
2541 /*
2542 * This is the core init function for AMD IOMMU hardware in the system.
2543 * This function is called from the generic x86 DMA layer initialization
2544 * code.
2545 */
2546 static int __init amd_iommu_init(void)
2547 {
2548 int ret;
2549
2550 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2551 if (ret) {
2552 free_dma_resources();
2553 if (!irq_remapping_enabled) {
2554 disable_iommus();
2555 free_iommu_resources();
2556 } else {
2557 struct amd_iommu *iommu;
2558
2559 uninit_device_table_dma();
2560 for_each_iommu(iommu)
2561 iommu_flush_all_caches(iommu);
2562 }
2563 }
2564
2565 return ret;
2566 }
2567
2568 static bool amd_iommu_sme_check(void)
2569 {
2570 if (!sme_active() || (boot_cpu_data.x86 != 0x17))
2571 return true;
2572
2573 /* For Fam17h, a specific level of support is required */
2574 if (boot_cpu_data.microcode >= 0x08001205)
2575 return true;
2576
2577 if ((boot_cpu_data.microcode >= 0x08001126) &&
2578 (boot_cpu_data.microcode <= 0x080011ff))
2579 return true;
2580
2581 pr_notice("AMD-Vi: IOMMU not currently supported when SME is active\n");
2582
2583 return false;
2584 }
2585
2586 /****************************************************************************
2587 *
2588 * Early detect code. This code runs at IOMMU detection time in the DMA
2589 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2590 * IOMMUs
2591 *
2592 ****************************************************************************/
2593 int __init amd_iommu_detect(void)
2594 {
2595 int ret;
2596
2597 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2598 return -ENODEV;
2599
2600 if (!amd_iommu_sme_check())
2601 return -ENODEV;
2602
2603 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2604 if (ret)
2605 return ret;
2606
2607 amd_iommu_detected = true;
2608 iommu_detected = 1;
2609 x86_init.iommu.iommu_init = amd_iommu_init;
2610
2611 return 1;
2612 }
2613
2614 /****************************************************************************
2615 *
2616 * Parsing functions for the AMD IOMMU specific kernel command line
2617 * options.
2618 *
2619 ****************************************************************************/
2620
2621 static int __init parse_amd_iommu_dump(char *str)
2622 {
2623 amd_iommu_dump = true;
2624
2625 return 1;
2626 }
2627
2628 static int __init parse_amd_iommu_intr(char *str)
2629 {
2630 for (; *str; ++str) {
2631 if (strncmp(str, "legacy", 6) == 0) {
2632 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2633 break;
2634 }
2635 if (strncmp(str, "vapic", 5) == 0) {
2636 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2637 break;
2638 }
2639 }
2640 return 1;
2641 }
2642
2643 static int __init parse_amd_iommu_options(char *str)
2644 {
2645 for (; *str; ++str) {
2646 if (strncmp(str, "fullflush", 9) == 0)
2647 amd_iommu_unmap_flush = true;
2648 if (strncmp(str, "off", 3) == 0)
2649 amd_iommu_disabled = true;
2650 if (strncmp(str, "force_isolation", 15) == 0)
2651 amd_iommu_force_isolation = true;
2652 }
2653
2654 return 1;
2655 }
2656
2657 static int __init parse_ivrs_ioapic(char *str)
2658 {
2659 unsigned int bus, dev, fn;
2660 int ret, id, i;
2661 u16 devid;
2662
2663 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2664
2665 if (ret != 4) {
2666 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2667 return 1;
2668 }
2669
2670 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2671 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2672 str);
2673 return 1;
2674 }
2675
2676 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2677
2678 cmdline_maps = true;
2679 i = early_ioapic_map_size++;
2680 early_ioapic_map[i].id = id;
2681 early_ioapic_map[i].devid = devid;
2682 early_ioapic_map[i].cmd_line = true;
2683
2684 return 1;
2685 }
2686
2687 static int __init parse_ivrs_hpet(char *str)
2688 {
2689 unsigned int bus, dev, fn;
2690 int ret, id, i;
2691 u16 devid;
2692
2693 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2694
2695 if (ret != 4) {
2696 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2697 return 1;
2698 }
2699
2700 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2701 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2702 str);
2703 return 1;
2704 }
2705
2706 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2707
2708 cmdline_maps = true;
2709 i = early_hpet_map_size++;
2710 early_hpet_map[i].id = id;
2711 early_hpet_map[i].devid = devid;
2712 early_hpet_map[i].cmd_line = true;
2713
2714 return 1;
2715 }
2716
2717 static int __init parse_ivrs_acpihid(char *str)
2718 {
2719 u32 bus, dev, fn;
2720 char *hid, *uid, *p;
2721 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2722 int ret, i;
2723
2724 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2725 if (ret != 4) {
2726 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2727 return 1;
2728 }
2729
2730 p = acpiid;
2731 hid = strsep(&p, ":");
2732 uid = p;
2733
2734 if (!hid || !(*hid) || !uid) {
2735 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2736 return 1;
2737 }
2738
2739 i = early_acpihid_map_size++;
2740 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2741 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2742 early_acpihid_map[i].devid =
2743 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2744 early_acpihid_map[i].cmd_line = true;
2745
2746 return 1;
2747 }
2748
2749 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2750 __setup("amd_iommu=", parse_amd_iommu_options);
2751 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2752 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2753 __setup("ivrs_hpet", parse_ivrs_hpet);
2754 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2755
2756 IOMMU_INIT_FINISH(amd_iommu_detect,
2757 gart_iommu_hole_init,
2758 NULL,
2759 NULL);
2760
2761 bool amd_iommu_v2_supported(void)
2762 {
2763 return amd_iommu_v2_present;
2764 }
2765 EXPORT_SYMBOL(amd_iommu_v2_supported);
2766
2767 struct amd_iommu *get_amd_iommu(unsigned int idx)
2768 {
2769 unsigned int i = 0;
2770 struct amd_iommu *iommu;
2771
2772 for_each_iommu(iommu)
2773 if (i++ == idx)
2774 return iommu;
2775 return NULL;
2776 }
2777 EXPORT_SYMBOL(get_amd_iommu);
2778
2779 /****************************************************************************
2780 *
2781 * IOMMU EFR Performance Counter support functionality. This code allows
2782 * access to the IOMMU PC functionality.
2783 *
2784 ****************************************************************************/
2785
2786 u8 amd_iommu_pc_get_max_banks(unsigned int idx)
2787 {
2788 struct amd_iommu *iommu = get_amd_iommu(idx);
2789
2790 if (iommu)
2791 return iommu->max_banks;
2792
2793 return 0;
2794 }
2795 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2796
2797 bool amd_iommu_pc_supported(void)
2798 {
2799 return amd_iommu_pc_present;
2800 }
2801 EXPORT_SYMBOL(amd_iommu_pc_supported);
2802
2803 u8 amd_iommu_pc_get_max_counters(unsigned int idx)
2804 {
2805 struct amd_iommu *iommu = get_amd_iommu(idx);
2806
2807 if (iommu)
2808 return iommu->max_counters;
2809
2810 return 0;
2811 }
2812 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2813
2814 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
2815 u8 fxn, u64 *value, bool is_write)
2816 {
2817 u32 offset;
2818 u32 max_offset_lim;
2819
2820 /* Make sure the IOMMU PC resource is available */
2821 if (!amd_iommu_pc_present)
2822 return -ENODEV;
2823
2824 /* Check for valid iommu and pc register indexing */
2825 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7)))
2826 return -ENODEV;
2827
2828 offset = (u32)(((0x40 | bank) << 12) | (cntr << 8) | fxn);
2829
2830 /* Limit the offset to the hw defined mmio region aperture */
2831 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) |
2832 (iommu->max_counters << 8) | 0x28);
2833 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2834 (offset > max_offset_lim))
2835 return -EINVAL;
2836
2837 if (is_write) {
2838 u64 val = *value & GENMASK_ULL(47, 0);
2839
2840 writel((u32)val, iommu->mmio_base + offset);
2841 writel((val >> 32), iommu->mmio_base + offset + 4);
2842 } else {
2843 *value = readl(iommu->mmio_base + offset + 4);
2844 *value <<= 32;
2845 *value |= readl(iommu->mmio_base + offset);
2846 *value &= GENMASK_ULL(47, 0);
2847 }
2848
2849 return 0;
2850 }
2851
2852 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2853 {
2854 if (!iommu)
2855 return -EINVAL;
2856
2857 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false);
2858 }
2859 EXPORT_SYMBOL(amd_iommu_pc_get_reg);
2860
2861 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value)
2862 {
2863 if (!iommu)
2864 return -EINVAL;
2865
2866 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true);
2867 }
2868 EXPORT_SYMBOL(amd_iommu_pc_set_reg);
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