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[mirror_ubuntu-zesty-kernel.git] / drivers / iommu / amd_iommu_init.c
1 /*
2 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
3 * Author: Joerg Roedel <jroedel@suse.de>
4 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
20 #include <linux/pci.h>
21 #include <linux/acpi.h>
22 #include <linux/list.h>
23 #include <linux/bitmap.h>
24 #include <linux/slab.h>
25 #include <linux/syscore_ops.h>
26 #include <linux/interrupt.h>
27 #include <linux/msi.h>
28 #include <linux/amd-iommu.h>
29 #include <linux/export.h>
30 #include <linux/iommu.h>
31 #include <asm/pci-direct.h>
32 #include <asm/iommu.h>
33 #include <asm/gart.h>
34 #include <asm/x86_init.h>
35 #include <asm/iommu_table.h>
36 #include <asm/io_apic.h>
37 #include <asm/irq_remapping.h>
38
39 #include "amd_iommu_proto.h"
40 #include "amd_iommu_types.h"
41 #include "irq_remapping.h"
42
43 /*
44 * definitions for the ACPI scanning code
45 */
46 #define IVRS_HEADER_LENGTH 48
47
48 #define ACPI_IVHD_TYPE_MAX_SUPPORTED 0x40
49 #define ACPI_IVMD_TYPE_ALL 0x20
50 #define ACPI_IVMD_TYPE 0x21
51 #define ACPI_IVMD_TYPE_RANGE 0x22
52
53 #define IVHD_DEV_ALL 0x01
54 #define IVHD_DEV_SELECT 0x02
55 #define IVHD_DEV_SELECT_RANGE_START 0x03
56 #define IVHD_DEV_RANGE_END 0x04
57 #define IVHD_DEV_ALIAS 0x42
58 #define IVHD_DEV_ALIAS_RANGE 0x43
59 #define IVHD_DEV_EXT_SELECT 0x46
60 #define IVHD_DEV_EXT_SELECT_RANGE 0x47
61 #define IVHD_DEV_SPECIAL 0x48
62 #define IVHD_DEV_ACPI_HID 0xf0
63
64 #define UID_NOT_PRESENT 0
65 #define UID_IS_INTEGER 1
66 #define UID_IS_CHARACTER 2
67
68 #define IVHD_SPECIAL_IOAPIC 1
69 #define IVHD_SPECIAL_HPET 2
70
71 #define IVHD_FLAG_HT_TUN_EN_MASK 0x01
72 #define IVHD_FLAG_PASSPW_EN_MASK 0x02
73 #define IVHD_FLAG_RESPASSPW_EN_MASK 0x04
74 #define IVHD_FLAG_ISOC_EN_MASK 0x08
75
76 #define IVMD_FLAG_EXCL_RANGE 0x08
77 #define IVMD_FLAG_UNITY_MAP 0x01
78
79 #define ACPI_DEVFLAG_INITPASS 0x01
80 #define ACPI_DEVFLAG_EXTINT 0x02
81 #define ACPI_DEVFLAG_NMI 0x04
82 #define ACPI_DEVFLAG_SYSMGT1 0x10
83 #define ACPI_DEVFLAG_SYSMGT2 0x20
84 #define ACPI_DEVFLAG_LINT0 0x40
85 #define ACPI_DEVFLAG_LINT1 0x80
86 #define ACPI_DEVFLAG_ATSDIS 0x10000000
87
88 #define LOOP_TIMEOUT 100000
89 /*
90 * ACPI table definitions
91 *
92 * These data structures are laid over the table to parse the important values
93 * out of it.
94 */
95
96 /*
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
98 * or more ivhd_entrys.
99 */
100 struct ivhd_header {
101 u8 type;
102 u8 flags;
103 u16 length;
104 u16 devid;
105 u16 cap_ptr;
106 u64 mmio_phys;
107 u16 pci_seg;
108 u16 info;
109 u32 efr_attr;
110
111 /* Following only valid on IVHD type 11h and 40h */
112 u64 efr_reg; /* Exact copy of MMIO_EXT_FEATURES */
113 u64 res;
114 } __attribute__((packed));
115
116 /*
117 * A device entry describing which devices a specific IOMMU translates and
118 * which requestor ids they use.
119 */
120 struct ivhd_entry {
121 u8 type;
122 u16 devid;
123 u8 flags;
124 u32 ext;
125 u32 hidh;
126 u64 cid;
127 u8 uidf;
128 u8 uidl;
129 u8 uid;
130 } __attribute__((packed));
131
132 /*
133 * An AMD IOMMU memory definition structure. It defines things like exclusion
134 * ranges for devices and regions that should be unity mapped.
135 */
136 struct ivmd_header {
137 u8 type;
138 u8 flags;
139 u16 length;
140 u16 devid;
141 u16 aux;
142 u64 resv;
143 u64 range_start;
144 u64 range_length;
145 } __attribute__((packed));
146
147 bool amd_iommu_dump;
148 bool amd_iommu_irq_remap __read_mostly;
149
150 int amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
151
152 static bool amd_iommu_detected;
153 static bool __initdata amd_iommu_disabled;
154 static int amd_iommu_target_ivhd_type;
155
156 u16 amd_iommu_last_bdf; /* largest PCI device id we have
157 to handle */
158 LIST_HEAD(amd_iommu_unity_map); /* a list of required unity mappings
159 we find in ACPI */
160 bool amd_iommu_unmap_flush; /* if true, flush on every unmap */
161
162 LIST_HEAD(amd_iommu_list); /* list of all AMD IOMMUs in the
163 system */
164
165 /* Array to assign indices to IOMMUs*/
166 struct amd_iommu *amd_iommus[MAX_IOMMUS];
167 int amd_iommus_present;
168
169 /* IOMMUs have a non-present cache? */
170 bool amd_iommu_np_cache __read_mostly;
171 bool amd_iommu_iotlb_sup __read_mostly = true;
172
173 u32 amd_iommu_max_pasid __read_mostly = ~0;
174
175 bool amd_iommu_v2_present __read_mostly;
176 static bool amd_iommu_pc_present __read_mostly;
177
178 bool amd_iommu_force_isolation __read_mostly;
179
180 /*
181 * List of protection domains - used during resume
182 */
183 LIST_HEAD(amd_iommu_pd_list);
184 spinlock_t amd_iommu_pd_lock;
185
186 /*
187 * Pointer to the device table which is shared by all AMD IOMMUs
188 * it is indexed by the PCI device id or the HT unit id and contains
189 * information about the domain the device belongs to as well as the
190 * page table root pointer.
191 */
192 struct dev_table_entry *amd_iommu_dev_table;
193
194 /*
195 * The alias table is a driver specific data structure which contains the
196 * mappings of the PCI device ids to the actual requestor ids on the IOMMU.
197 * More than one device can share the same requestor id.
198 */
199 u16 *amd_iommu_alias_table;
200
201 /*
202 * The rlookup table is used to find the IOMMU which is responsible
203 * for a specific device. It is also indexed by the PCI device id.
204 */
205 struct amd_iommu **amd_iommu_rlookup_table;
206
207 /*
208 * This table is used to find the irq remapping table for a given device id
209 * quickly.
210 */
211 struct irq_remap_table **irq_lookup_table;
212
213 /*
214 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
215 * to know which ones are already in use.
216 */
217 unsigned long *amd_iommu_pd_alloc_bitmap;
218
219 static u32 dev_table_size; /* size of the device table */
220 static u32 alias_table_size; /* size of the alias table */
221 static u32 rlookup_table_size; /* size if the rlookup table */
222
223 enum iommu_init_state {
224 IOMMU_START_STATE,
225 IOMMU_IVRS_DETECTED,
226 IOMMU_ACPI_FINISHED,
227 IOMMU_ENABLED,
228 IOMMU_PCI_INIT,
229 IOMMU_INTERRUPTS_EN,
230 IOMMU_DMA_OPS,
231 IOMMU_INITIALIZED,
232 IOMMU_NOT_FOUND,
233 IOMMU_INIT_ERROR,
234 };
235
236 /* Early ioapic and hpet maps from kernel command line */
237 #define EARLY_MAP_SIZE 4
238 static struct devid_map __initdata early_ioapic_map[EARLY_MAP_SIZE];
239 static struct devid_map __initdata early_hpet_map[EARLY_MAP_SIZE];
240 static struct acpihid_map_entry __initdata early_acpihid_map[EARLY_MAP_SIZE];
241
242 static int __initdata early_ioapic_map_size;
243 static int __initdata early_hpet_map_size;
244 static int __initdata early_acpihid_map_size;
245
246 static bool __initdata cmdline_maps;
247
248 static enum iommu_init_state init_state = IOMMU_START_STATE;
249
250 static int amd_iommu_enable_interrupts(void);
251 static int __init iommu_go_to_state(enum iommu_init_state state);
252 static void init_device_table_dma(void);
253
254 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
255 u8 bank, u8 cntr, u8 fxn,
256 u64 *value, bool is_write);
257
258 static inline void update_last_devid(u16 devid)
259 {
260 if (devid > amd_iommu_last_bdf)
261 amd_iommu_last_bdf = devid;
262 }
263
264 static inline unsigned long tbl_size(int entry_size)
265 {
266 unsigned shift = PAGE_SHIFT +
267 get_order(((int)amd_iommu_last_bdf + 1) * entry_size);
268
269 return 1UL << shift;
270 }
271
272 /* Access to l1 and l2 indexed register spaces */
273
274 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address)
275 {
276 u32 val;
277
278 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
279 pci_read_config_dword(iommu->dev, 0xfc, &val);
280 return val;
281 }
282
283 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val)
284 {
285 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31));
286 pci_write_config_dword(iommu->dev, 0xfc, val);
287 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16));
288 }
289
290 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address)
291 {
292 u32 val;
293
294 pci_write_config_dword(iommu->dev, 0xf0, address);
295 pci_read_config_dword(iommu->dev, 0xf4, &val);
296 return val;
297 }
298
299 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val)
300 {
301 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8));
302 pci_write_config_dword(iommu->dev, 0xf4, val);
303 }
304
305 /****************************************************************************
306 *
307 * AMD IOMMU MMIO register space handling functions
308 *
309 * These functions are used to program the IOMMU device registers in
310 * MMIO space required for that driver.
311 *
312 ****************************************************************************/
313
314 /*
315 * This function set the exclusion range in the IOMMU. DMA accesses to the
316 * exclusion range are passed through untranslated
317 */
318 static void iommu_set_exclusion_range(struct amd_iommu *iommu)
319 {
320 u64 start = iommu->exclusion_start & PAGE_MASK;
321 u64 limit = (start + iommu->exclusion_length) & PAGE_MASK;
322 u64 entry;
323
324 if (!iommu->exclusion_start)
325 return;
326
327 entry = start | MMIO_EXCL_ENABLE_MASK;
328 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET,
329 &entry, sizeof(entry));
330
331 entry = limit;
332 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET,
333 &entry, sizeof(entry));
334 }
335
336 /* Programs the physical address of the device table into the IOMMU hardware */
337 static void iommu_set_device_table(struct amd_iommu *iommu)
338 {
339 u64 entry;
340
341 BUG_ON(iommu->mmio_base == NULL);
342
343 entry = virt_to_phys(amd_iommu_dev_table);
344 entry |= (dev_table_size >> 12) - 1;
345 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET,
346 &entry, sizeof(entry));
347 }
348
349 /* Generic functions to enable/disable certain features of the IOMMU. */
350 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit)
351 {
352 u32 ctrl;
353
354 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
355 ctrl |= (1 << bit);
356 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
357 }
358
359 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit)
360 {
361 u32 ctrl;
362
363 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
364 ctrl &= ~(1 << bit);
365 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
366 }
367
368 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout)
369 {
370 u32 ctrl;
371
372 ctrl = readl(iommu->mmio_base + MMIO_CONTROL_OFFSET);
373 ctrl &= ~CTRL_INV_TO_MASK;
374 ctrl |= (timeout << CONTROL_INV_TIMEOUT) & CTRL_INV_TO_MASK;
375 writel(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET);
376 }
377
378 /* Function to enable the hardware */
379 static void iommu_enable(struct amd_iommu *iommu)
380 {
381 iommu_feature_enable(iommu, CONTROL_IOMMU_EN);
382 }
383
384 static void iommu_disable(struct amd_iommu *iommu)
385 {
386 /* Disable command buffer */
387 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
388
389 /* Disable event logging and event interrupts */
390 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN);
391 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN);
392
393 /* Disable IOMMU GA_LOG */
394 iommu_feature_disable(iommu, CONTROL_GALOG_EN);
395 iommu_feature_disable(iommu, CONTROL_GAINT_EN);
396
397 /* Disable IOMMU hardware itself */
398 iommu_feature_disable(iommu, CONTROL_IOMMU_EN);
399 }
400
401 /*
402 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
403 * the system has one.
404 */
405 static u8 __iomem * __init iommu_map_mmio_space(u64 address, u64 end)
406 {
407 if (!request_mem_region(address, end, "amd_iommu")) {
408 pr_err("AMD-Vi: Can not reserve memory region %llx-%llx for mmio\n",
409 address, end);
410 pr_err("AMD-Vi: This is a BIOS bug. Please contact your hardware vendor\n");
411 return NULL;
412 }
413
414 return (u8 __iomem *)ioremap_nocache(address, end);
415 }
416
417 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu)
418 {
419 if (iommu->mmio_base)
420 iounmap(iommu->mmio_base);
421 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end);
422 }
423
424 static inline u32 get_ivhd_header_size(struct ivhd_header *h)
425 {
426 u32 size = 0;
427
428 switch (h->type) {
429 case 0x10:
430 size = 24;
431 break;
432 case 0x11:
433 case 0x40:
434 size = 40;
435 break;
436 }
437 return size;
438 }
439
440 /****************************************************************************
441 *
442 * The functions below belong to the first pass of AMD IOMMU ACPI table
443 * parsing. In this pass we try to find out the highest device id this
444 * code has to handle. Upon this information the size of the shared data
445 * structures is determined later.
446 *
447 ****************************************************************************/
448
449 /*
450 * This function calculates the length of a given IVHD entry
451 */
452 static inline int ivhd_entry_length(u8 *ivhd)
453 {
454 u32 type = ((struct ivhd_entry *)ivhd)->type;
455
456 if (type < 0x80) {
457 return 0x04 << (*ivhd >> 6);
458 } else if (type == IVHD_DEV_ACPI_HID) {
459 /* For ACPI_HID, offset 21 is uid len */
460 return *((u8 *)ivhd + 21) + 22;
461 }
462 return 0;
463 }
464
465 /*
466 * After reading the highest device id from the IOMMU PCI capability header
467 * this function looks if there is a higher device id defined in the ACPI table
468 */
469 static int __init find_last_devid_from_ivhd(struct ivhd_header *h)
470 {
471 u8 *p = (void *)h, *end = (void *)h;
472 struct ivhd_entry *dev;
473
474 u32 ivhd_size = get_ivhd_header_size(h);
475
476 if (!ivhd_size) {
477 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
478 return -EINVAL;
479 }
480
481 p += ivhd_size;
482 end += h->length;
483
484 while (p < end) {
485 dev = (struct ivhd_entry *)p;
486 switch (dev->type) {
487 case IVHD_DEV_ALL:
488 /* Use maximum BDF value for DEV_ALL */
489 update_last_devid(0xffff);
490 break;
491 case IVHD_DEV_SELECT:
492 case IVHD_DEV_RANGE_END:
493 case IVHD_DEV_ALIAS:
494 case IVHD_DEV_EXT_SELECT:
495 /* all the above subfield types refer to device ids */
496 update_last_devid(dev->devid);
497 break;
498 default:
499 break;
500 }
501 p += ivhd_entry_length(p);
502 }
503
504 WARN_ON(p != end);
505
506 return 0;
507 }
508
509 static int __init check_ivrs_checksum(struct acpi_table_header *table)
510 {
511 int i;
512 u8 checksum = 0, *p = (u8 *)table;
513
514 for (i = 0; i < table->length; ++i)
515 checksum += p[i];
516 if (checksum != 0) {
517 /* ACPI table corrupt */
518 pr_err(FW_BUG "AMD-Vi: IVRS invalid checksum\n");
519 return -ENODEV;
520 }
521
522 return 0;
523 }
524
525 /*
526 * Iterate over all IVHD entries in the ACPI table and find the highest device
527 * id which we need to handle. This is the first of three functions which parse
528 * the ACPI table. So we check the checksum here.
529 */
530 static int __init find_last_devid_acpi(struct acpi_table_header *table)
531 {
532 u8 *p = (u8 *)table, *end = (u8 *)table;
533 struct ivhd_header *h;
534
535 p += IVRS_HEADER_LENGTH;
536
537 end += table->length;
538 while (p < end) {
539 h = (struct ivhd_header *)p;
540 if (h->type == amd_iommu_target_ivhd_type) {
541 int ret = find_last_devid_from_ivhd(h);
542
543 if (ret)
544 return ret;
545 }
546 p += h->length;
547 }
548 WARN_ON(p != end);
549
550 return 0;
551 }
552
553 /****************************************************************************
554 *
555 * The following functions belong to the code path which parses the ACPI table
556 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
557 * data structures, initialize the device/alias/rlookup table and also
558 * basically initialize the hardware.
559 *
560 ****************************************************************************/
561
562 /*
563 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
564 * write commands to that buffer later and the IOMMU will execute them
565 * asynchronously
566 */
567 static int __init alloc_command_buffer(struct amd_iommu *iommu)
568 {
569 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
570 get_order(CMD_BUFFER_SIZE));
571
572 return iommu->cmd_buf ? 0 : -ENOMEM;
573 }
574
575 /*
576 * This function resets the command buffer if the IOMMU stopped fetching
577 * commands from it.
578 */
579 void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu)
580 {
581 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN);
582
583 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
584 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
585
586 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN);
587 }
588
589 /*
590 * This function writes the command buffer address to the hardware and
591 * enables it.
592 */
593 static void iommu_enable_command_buffer(struct amd_iommu *iommu)
594 {
595 u64 entry;
596
597 BUG_ON(iommu->cmd_buf == NULL);
598
599 entry = (u64)virt_to_phys(iommu->cmd_buf);
600 entry |= MMIO_CMD_SIZE_512;
601
602 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET,
603 &entry, sizeof(entry));
604
605 amd_iommu_reset_cmd_buffer(iommu);
606 }
607
608 static void __init free_command_buffer(struct amd_iommu *iommu)
609 {
610 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE));
611 }
612
613 /* allocates the memory where the IOMMU will log its events to */
614 static int __init alloc_event_buffer(struct amd_iommu *iommu)
615 {
616 iommu->evt_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
617 get_order(EVT_BUFFER_SIZE));
618
619 return iommu->evt_buf ? 0 : -ENOMEM;
620 }
621
622 static void iommu_enable_event_buffer(struct amd_iommu *iommu)
623 {
624 u64 entry;
625
626 BUG_ON(iommu->evt_buf == NULL);
627
628 entry = (u64)virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK;
629
630 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET,
631 &entry, sizeof(entry));
632
633 /* set head and tail to zero manually */
634 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
635 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
636
637 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN);
638 }
639
640 static void __init free_event_buffer(struct amd_iommu *iommu)
641 {
642 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE));
643 }
644
645 /* allocates the memory where the IOMMU will log its events to */
646 static int __init alloc_ppr_log(struct amd_iommu *iommu)
647 {
648 iommu->ppr_log = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
649 get_order(PPR_LOG_SIZE));
650
651 return iommu->ppr_log ? 0 : -ENOMEM;
652 }
653
654 static void iommu_enable_ppr_log(struct amd_iommu *iommu)
655 {
656 u64 entry;
657
658 if (iommu->ppr_log == NULL)
659 return;
660
661 entry = (u64)virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512;
662
663 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET,
664 &entry, sizeof(entry));
665
666 /* set head and tail to zero manually */
667 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
668 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
669
670 iommu_feature_enable(iommu, CONTROL_PPFLOG_EN);
671 iommu_feature_enable(iommu, CONTROL_PPR_EN);
672 }
673
674 static void __init free_ppr_log(struct amd_iommu *iommu)
675 {
676 if (iommu->ppr_log == NULL)
677 return;
678
679 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE));
680 }
681
682 static void free_ga_log(struct amd_iommu *iommu)
683 {
684 #ifdef CONFIG_IRQ_REMAP
685 if (iommu->ga_log)
686 free_pages((unsigned long)iommu->ga_log,
687 get_order(GA_LOG_SIZE));
688 if (iommu->ga_log_tail)
689 free_pages((unsigned long)iommu->ga_log_tail,
690 get_order(8));
691 #endif
692 }
693
694 static int iommu_ga_log_enable(struct amd_iommu *iommu)
695 {
696 #ifdef CONFIG_IRQ_REMAP
697 u32 status, i;
698
699 if (!iommu->ga_log)
700 return -EINVAL;
701
702 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
703
704 /* Check if already running */
705 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
706 return 0;
707
708 iommu_feature_enable(iommu, CONTROL_GAINT_EN);
709 iommu_feature_enable(iommu, CONTROL_GALOG_EN);
710
711 for (i = 0; i < LOOP_TIMEOUT; ++i) {
712 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
713 if (status & (MMIO_STATUS_GALOG_RUN_MASK))
714 break;
715 }
716
717 if (i >= LOOP_TIMEOUT)
718 return -EINVAL;
719 #endif /* CONFIG_IRQ_REMAP */
720 return 0;
721 }
722
723 #ifdef CONFIG_IRQ_REMAP
724 static int iommu_init_ga_log(struct amd_iommu *iommu)
725 {
726 u64 entry;
727
728 if (!AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
729 return 0;
730
731 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
732 get_order(GA_LOG_SIZE));
733 if (!iommu->ga_log)
734 goto err_out;
735
736 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
737 get_order(8));
738 if (!iommu->ga_log_tail)
739 goto err_out;
740
741 entry = (u64)virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512;
742 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET,
743 &entry, sizeof(entry));
744 entry = ((u64)virt_to_phys(iommu->ga_log) & 0xFFFFFFFFFFFFFULL) & ~7ULL;
745 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET,
746 &entry, sizeof(entry));
747 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET);
748 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET);
749
750 return 0;
751 err_out:
752 free_ga_log(iommu);
753 return -EINVAL;
754 }
755 #endif /* CONFIG_IRQ_REMAP */
756
757 static int iommu_init_ga(struct amd_iommu *iommu)
758 {
759 int ret = 0;
760
761 #ifdef CONFIG_IRQ_REMAP
762 /* Note: We have already checked GASup from IVRS table.
763 * Now, we need to make sure that GAMSup is set.
764 */
765 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
766 !iommu_feature(iommu, FEATURE_GAM_VAPIC))
767 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
768
769 ret = iommu_init_ga_log(iommu);
770 #endif /* CONFIG_IRQ_REMAP */
771
772 return ret;
773 }
774
775 static void iommu_enable_gt(struct amd_iommu *iommu)
776 {
777 if (!iommu_feature(iommu, FEATURE_GT))
778 return;
779
780 iommu_feature_enable(iommu, CONTROL_GT_EN);
781 }
782
783 /* sets a specific bit in the device table entry. */
784 static void set_dev_entry_bit(u16 devid, u8 bit)
785 {
786 int i = (bit >> 6) & 0x03;
787 int _bit = bit & 0x3f;
788
789 amd_iommu_dev_table[devid].data[i] |= (1UL << _bit);
790 }
791
792 static int get_dev_entry_bit(u16 devid, u8 bit)
793 {
794 int i = (bit >> 6) & 0x03;
795 int _bit = bit & 0x3f;
796
797 return (amd_iommu_dev_table[devid].data[i] & (1UL << _bit)) >> _bit;
798 }
799
800
801 void amd_iommu_apply_erratum_63(u16 devid)
802 {
803 int sysmgt;
804
805 sysmgt = get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1) |
806 (get_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2) << 1);
807
808 if (sysmgt == 0x01)
809 set_dev_entry_bit(devid, DEV_ENTRY_IW);
810 }
811
812 /* Writes the specific IOMMU for a device into the rlookup table */
813 static void __init set_iommu_for_device(struct amd_iommu *iommu, u16 devid)
814 {
815 amd_iommu_rlookup_table[devid] = iommu;
816 }
817
818 /*
819 * This function takes the device specific flags read from the ACPI
820 * table and sets up the device table entry with that information
821 */
822 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu,
823 u16 devid, u32 flags, u32 ext_flags)
824 {
825 if (flags & ACPI_DEVFLAG_INITPASS)
826 set_dev_entry_bit(devid, DEV_ENTRY_INIT_PASS);
827 if (flags & ACPI_DEVFLAG_EXTINT)
828 set_dev_entry_bit(devid, DEV_ENTRY_EINT_PASS);
829 if (flags & ACPI_DEVFLAG_NMI)
830 set_dev_entry_bit(devid, DEV_ENTRY_NMI_PASS);
831 if (flags & ACPI_DEVFLAG_SYSMGT1)
832 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT1);
833 if (flags & ACPI_DEVFLAG_SYSMGT2)
834 set_dev_entry_bit(devid, DEV_ENTRY_SYSMGT2);
835 if (flags & ACPI_DEVFLAG_LINT0)
836 set_dev_entry_bit(devid, DEV_ENTRY_LINT0_PASS);
837 if (flags & ACPI_DEVFLAG_LINT1)
838 set_dev_entry_bit(devid, DEV_ENTRY_LINT1_PASS);
839
840 amd_iommu_apply_erratum_63(devid);
841
842 set_iommu_for_device(iommu, devid);
843 }
844
845 static int __init add_special_device(u8 type, u8 id, u16 *devid, bool cmd_line)
846 {
847 struct devid_map *entry;
848 struct list_head *list;
849
850 if (type == IVHD_SPECIAL_IOAPIC)
851 list = &ioapic_map;
852 else if (type == IVHD_SPECIAL_HPET)
853 list = &hpet_map;
854 else
855 return -EINVAL;
856
857 list_for_each_entry(entry, list, list) {
858 if (!(entry->id == id && entry->cmd_line))
859 continue;
860
861 pr_info("AMD-Vi: Command-line override present for %s id %d - ignoring\n",
862 type == IVHD_SPECIAL_IOAPIC ? "IOAPIC" : "HPET", id);
863
864 *devid = entry->devid;
865
866 return 0;
867 }
868
869 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
870 if (!entry)
871 return -ENOMEM;
872
873 entry->id = id;
874 entry->devid = *devid;
875 entry->cmd_line = cmd_line;
876
877 list_add_tail(&entry->list, list);
878
879 return 0;
880 }
881
882 static int __init add_acpi_hid_device(u8 *hid, u8 *uid, u16 *devid,
883 bool cmd_line)
884 {
885 struct acpihid_map_entry *entry;
886 struct list_head *list = &acpihid_map;
887
888 list_for_each_entry(entry, list, list) {
889 if (strcmp(entry->hid, hid) ||
890 (*uid && *entry->uid && strcmp(entry->uid, uid)) ||
891 !entry->cmd_line)
892 continue;
893
894 pr_info("AMD-Vi: Command-line override for hid:%s uid:%s\n",
895 hid, uid);
896 *devid = entry->devid;
897 return 0;
898 }
899
900 entry = kzalloc(sizeof(*entry), GFP_KERNEL);
901 if (!entry)
902 return -ENOMEM;
903
904 memcpy(entry->uid, uid, strlen(uid));
905 memcpy(entry->hid, hid, strlen(hid));
906 entry->devid = *devid;
907 entry->cmd_line = cmd_line;
908 entry->root_devid = (entry->devid & (~0x7));
909
910 pr_info("AMD-Vi:%s, add hid:%s, uid:%s, rdevid:%d\n",
911 entry->cmd_line ? "cmd" : "ivrs",
912 entry->hid, entry->uid, entry->root_devid);
913
914 list_add_tail(&entry->list, list);
915 return 0;
916 }
917
918 static int __init add_early_maps(void)
919 {
920 int i, ret;
921
922 for (i = 0; i < early_ioapic_map_size; ++i) {
923 ret = add_special_device(IVHD_SPECIAL_IOAPIC,
924 early_ioapic_map[i].id,
925 &early_ioapic_map[i].devid,
926 early_ioapic_map[i].cmd_line);
927 if (ret)
928 return ret;
929 }
930
931 for (i = 0; i < early_hpet_map_size; ++i) {
932 ret = add_special_device(IVHD_SPECIAL_HPET,
933 early_hpet_map[i].id,
934 &early_hpet_map[i].devid,
935 early_hpet_map[i].cmd_line);
936 if (ret)
937 return ret;
938 }
939
940 for (i = 0; i < early_acpihid_map_size; ++i) {
941 ret = add_acpi_hid_device(early_acpihid_map[i].hid,
942 early_acpihid_map[i].uid,
943 &early_acpihid_map[i].devid,
944 early_acpihid_map[i].cmd_line);
945 if (ret)
946 return ret;
947 }
948
949 return 0;
950 }
951
952 /*
953 * Reads the device exclusion range from ACPI and initializes the IOMMU with
954 * it
955 */
956 static void __init set_device_exclusion_range(u16 devid, struct ivmd_header *m)
957 {
958 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
959
960 if (!(m->flags & IVMD_FLAG_EXCL_RANGE))
961 return;
962
963 if (iommu) {
964 /*
965 * We only can configure exclusion ranges per IOMMU, not
966 * per device. But we can enable the exclusion range per
967 * device. This is done here
968 */
969 set_dev_entry_bit(devid, DEV_ENTRY_EX);
970 iommu->exclusion_start = m->range_start;
971 iommu->exclusion_length = m->range_length;
972 }
973 }
974
975 /*
976 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
977 * initializes the hardware and our data structures with it.
978 */
979 static int __init init_iommu_from_acpi(struct amd_iommu *iommu,
980 struct ivhd_header *h)
981 {
982 u8 *p = (u8 *)h;
983 u8 *end = p, flags = 0;
984 u16 devid = 0, devid_start = 0, devid_to = 0;
985 u32 dev_i, ext_flags = 0;
986 bool alias = false;
987 struct ivhd_entry *e;
988 u32 ivhd_size;
989 int ret;
990
991
992 ret = add_early_maps();
993 if (ret)
994 return ret;
995
996 /*
997 * First save the recommended feature enable bits from ACPI
998 */
999 iommu->acpi_flags = h->flags;
1000
1001 /*
1002 * Done. Now parse the device entries
1003 */
1004 ivhd_size = get_ivhd_header_size(h);
1005 if (!ivhd_size) {
1006 pr_err("AMD-Vi: Unsupported IVHD type %#x\n", h->type);
1007 return -EINVAL;
1008 }
1009
1010 p += ivhd_size;
1011
1012 end += h->length;
1013
1014
1015 while (p < end) {
1016 e = (struct ivhd_entry *)p;
1017 switch (e->type) {
1018 case IVHD_DEV_ALL:
1019
1020 DUMP_printk(" DEV_ALL\t\t\tflags: %02x\n", e->flags);
1021
1022 for (dev_i = 0; dev_i <= amd_iommu_last_bdf; ++dev_i)
1023 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0);
1024 break;
1025 case IVHD_DEV_SELECT:
1026
1027 DUMP_printk(" DEV_SELECT\t\t\t devid: %02x:%02x.%x "
1028 "flags: %02x\n",
1029 PCI_BUS_NUM(e->devid),
1030 PCI_SLOT(e->devid),
1031 PCI_FUNC(e->devid),
1032 e->flags);
1033
1034 devid = e->devid;
1035 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1036 break;
1037 case IVHD_DEV_SELECT_RANGE_START:
1038
1039 DUMP_printk(" DEV_SELECT_RANGE_START\t "
1040 "devid: %02x:%02x.%x flags: %02x\n",
1041 PCI_BUS_NUM(e->devid),
1042 PCI_SLOT(e->devid),
1043 PCI_FUNC(e->devid),
1044 e->flags);
1045
1046 devid_start = e->devid;
1047 flags = e->flags;
1048 ext_flags = 0;
1049 alias = false;
1050 break;
1051 case IVHD_DEV_ALIAS:
1052
1053 DUMP_printk(" DEV_ALIAS\t\t\t devid: %02x:%02x.%x "
1054 "flags: %02x devid_to: %02x:%02x.%x\n",
1055 PCI_BUS_NUM(e->devid),
1056 PCI_SLOT(e->devid),
1057 PCI_FUNC(e->devid),
1058 e->flags,
1059 PCI_BUS_NUM(e->ext >> 8),
1060 PCI_SLOT(e->ext >> 8),
1061 PCI_FUNC(e->ext >> 8));
1062
1063 devid = e->devid;
1064 devid_to = e->ext >> 8;
1065 set_dev_entry_from_acpi(iommu, devid , e->flags, 0);
1066 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0);
1067 amd_iommu_alias_table[devid] = devid_to;
1068 break;
1069 case IVHD_DEV_ALIAS_RANGE:
1070
1071 DUMP_printk(" DEV_ALIAS_RANGE\t\t "
1072 "devid: %02x:%02x.%x flags: %02x "
1073 "devid_to: %02x:%02x.%x\n",
1074 PCI_BUS_NUM(e->devid),
1075 PCI_SLOT(e->devid),
1076 PCI_FUNC(e->devid),
1077 e->flags,
1078 PCI_BUS_NUM(e->ext >> 8),
1079 PCI_SLOT(e->ext >> 8),
1080 PCI_FUNC(e->ext >> 8));
1081
1082 devid_start = e->devid;
1083 flags = e->flags;
1084 devid_to = e->ext >> 8;
1085 ext_flags = 0;
1086 alias = true;
1087 break;
1088 case IVHD_DEV_EXT_SELECT:
1089
1090 DUMP_printk(" DEV_EXT_SELECT\t\t devid: %02x:%02x.%x "
1091 "flags: %02x ext: %08x\n",
1092 PCI_BUS_NUM(e->devid),
1093 PCI_SLOT(e->devid),
1094 PCI_FUNC(e->devid),
1095 e->flags, e->ext);
1096
1097 devid = e->devid;
1098 set_dev_entry_from_acpi(iommu, devid, e->flags,
1099 e->ext);
1100 break;
1101 case IVHD_DEV_EXT_SELECT_RANGE:
1102
1103 DUMP_printk(" DEV_EXT_SELECT_RANGE\t devid: "
1104 "%02x:%02x.%x flags: %02x ext: %08x\n",
1105 PCI_BUS_NUM(e->devid),
1106 PCI_SLOT(e->devid),
1107 PCI_FUNC(e->devid),
1108 e->flags, e->ext);
1109
1110 devid_start = e->devid;
1111 flags = e->flags;
1112 ext_flags = e->ext;
1113 alias = false;
1114 break;
1115 case IVHD_DEV_RANGE_END:
1116
1117 DUMP_printk(" DEV_RANGE_END\t\t devid: %02x:%02x.%x\n",
1118 PCI_BUS_NUM(e->devid),
1119 PCI_SLOT(e->devid),
1120 PCI_FUNC(e->devid));
1121
1122 devid = e->devid;
1123 for (dev_i = devid_start; dev_i <= devid; ++dev_i) {
1124 if (alias) {
1125 amd_iommu_alias_table[dev_i] = devid_to;
1126 set_dev_entry_from_acpi(iommu,
1127 devid_to, flags, ext_flags);
1128 }
1129 set_dev_entry_from_acpi(iommu, dev_i,
1130 flags, ext_flags);
1131 }
1132 break;
1133 case IVHD_DEV_SPECIAL: {
1134 u8 handle, type;
1135 const char *var;
1136 u16 devid;
1137 int ret;
1138
1139 handle = e->ext & 0xff;
1140 devid = (e->ext >> 8) & 0xffff;
1141 type = (e->ext >> 24) & 0xff;
1142
1143 if (type == IVHD_SPECIAL_IOAPIC)
1144 var = "IOAPIC";
1145 else if (type == IVHD_SPECIAL_HPET)
1146 var = "HPET";
1147 else
1148 var = "UNKNOWN";
1149
1150 DUMP_printk(" DEV_SPECIAL(%s[%d])\t\tdevid: %02x:%02x.%x\n",
1151 var, (int)handle,
1152 PCI_BUS_NUM(devid),
1153 PCI_SLOT(devid),
1154 PCI_FUNC(devid));
1155
1156 ret = add_special_device(type, handle, &devid, false);
1157 if (ret)
1158 return ret;
1159
1160 /*
1161 * add_special_device might update the devid in case a
1162 * command-line override is present. So call
1163 * set_dev_entry_from_acpi after add_special_device.
1164 */
1165 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1166
1167 break;
1168 }
1169 case IVHD_DEV_ACPI_HID: {
1170 u16 devid;
1171 u8 hid[ACPIHID_HID_LEN] = {0};
1172 u8 uid[ACPIHID_UID_LEN] = {0};
1173 int ret;
1174
1175 if (h->type != 0x40) {
1176 pr_err(FW_BUG "Invalid IVHD device type %#x\n",
1177 e->type);
1178 break;
1179 }
1180
1181 memcpy(hid, (u8 *)(&e->ext), ACPIHID_HID_LEN - 1);
1182 hid[ACPIHID_HID_LEN - 1] = '\0';
1183
1184 if (!(*hid)) {
1185 pr_err(FW_BUG "Invalid HID.\n");
1186 break;
1187 }
1188
1189 switch (e->uidf) {
1190 case UID_NOT_PRESENT:
1191
1192 if (e->uidl != 0)
1193 pr_warn(FW_BUG "Invalid UID length.\n");
1194
1195 break;
1196 case UID_IS_INTEGER:
1197
1198 sprintf(uid, "%d", e->uid);
1199
1200 break;
1201 case UID_IS_CHARACTER:
1202
1203 memcpy(uid, (u8 *)(&e->uid), ACPIHID_UID_LEN - 1);
1204 uid[ACPIHID_UID_LEN - 1] = '\0';
1205
1206 break;
1207 default:
1208 break;
1209 }
1210
1211 devid = e->devid;
1212 DUMP_printk(" DEV_ACPI_HID(%s[%s])\t\tdevid: %02x:%02x.%x\n",
1213 hid, uid,
1214 PCI_BUS_NUM(devid),
1215 PCI_SLOT(devid),
1216 PCI_FUNC(devid));
1217
1218 flags = e->flags;
1219
1220 ret = add_acpi_hid_device(hid, uid, &devid, false);
1221 if (ret)
1222 return ret;
1223
1224 /*
1225 * add_special_device might update the devid in case a
1226 * command-line override is present. So call
1227 * set_dev_entry_from_acpi after add_special_device.
1228 */
1229 set_dev_entry_from_acpi(iommu, devid, e->flags, 0);
1230
1231 break;
1232 }
1233 default:
1234 break;
1235 }
1236
1237 p += ivhd_entry_length(p);
1238 }
1239
1240 return 0;
1241 }
1242
1243 static void __init free_iommu_one(struct amd_iommu *iommu)
1244 {
1245 free_command_buffer(iommu);
1246 free_event_buffer(iommu);
1247 free_ppr_log(iommu);
1248 free_ga_log(iommu);
1249 iommu_unmap_mmio_space(iommu);
1250 }
1251
1252 static void __init free_iommu_all(void)
1253 {
1254 struct amd_iommu *iommu, *next;
1255
1256 for_each_iommu_safe(iommu, next) {
1257 list_del(&iommu->list);
1258 free_iommu_one(iommu);
1259 kfree(iommu);
1260 }
1261 }
1262
1263 /*
1264 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1265 * Workaround:
1266 * BIOS should disable L2B micellaneous clock gating by setting
1267 * L2_L2B_CK_GATE_CONTROL[CKGateL2BMiscDisable](D0F2xF4_x90[2]) = 1b
1268 */
1269 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu)
1270 {
1271 u32 value;
1272
1273 if ((boot_cpu_data.x86 != 0x15) ||
1274 (boot_cpu_data.x86_model < 0x10) ||
1275 (boot_cpu_data.x86_model > 0x1f))
1276 return;
1277
1278 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1279 pci_read_config_dword(iommu->dev, 0xf4, &value);
1280
1281 if (value & BIT(2))
1282 return;
1283
1284 /* Select NB indirect register 0x90 and enable writing */
1285 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8));
1286
1287 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4);
1288 pr_info("AMD-Vi: Applying erratum 746 workaround for IOMMU at %s\n",
1289 dev_name(&iommu->dev->dev));
1290
1291 /* Clear the enable writing bit */
1292 pci_write_config_dword(iommu->dev, 0xf0, 0x90);
1293 }
1294
1295 /*
1296 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1297 * Workaround:
1298 * BIOS should enable ATS write permission check by setting
1299 * L2_DEBUG_3[AtsIgnoreIWDis](D0F2xF4_x47[0]) = 1b
1300 */
1301 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu)
1302 {
1303 u32 value;
1304
1305 if ((boot_cpu_data.x86 != 0x15) ||
1306 (boot_cpu_data.x86_model < 0x30) ||
1307 (boot_cpu_data.x86_model > 0x3f))
1308 return;
1309
1310 /* Test L2_DEBUG_3[AtsIgnoreIWDis] == 1 */
1311 value = iommu_read_l2(iommu, 0x47);
1312
1313 if (value & BIT(0))
1314 return;
1315
1316 /* Set L2_DEBUG_3[AtsIgnoreIWDis] = 1 */
1317 iommu_write_l2(iommu, 0x47, value | BIT(0));
1318
1319 pr_info("AMD-Vi: Applying ATS write check workaround for IOMMU at %s\n",
1320 dev_name(&iommu->dev->dev));
1321 }
1322
1323 /*
1324 * This function clues the initialization function for one IOMMU
1325 * together and also allocates the command buffer and programs the
1326 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1327 */
1328 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h)
1329 {
1330 int ret;
1331
1332 spin_lock_init(&iommu->lock);
1333
1334 /* Add IOMMU to internal data structures */
1335 list_add_tail(&iommu->list, &amd_iommu_list);
1336 iommu->index = amd_iommus_present++;
1337
1338 if (unlikely(iommu->index >= MAX_IOMMUS)) {
1339 WARN(1, "AMD-Vi: System has more IOMMUs than supported by this driver\n");
1340 return -ENOSYS;
1341 }
1342
1343 /* Index is fine - add IOMMU to the array */
1344 amd_iommus[iommu->index] = iommu;
1345
1346 /*
1347 * Copy data from ACPI table entry to the iommu struct
1348 */
1349 iommu->devid = h->devid;
1350 iommu->cap_ptr = h->cap_ptr;
1351 iommu->pci_seg = h->pci_seg;
1352 iommu->mmio_phys = h->mmio_phys;
1353
1354 switch (h->type) {
1355 case 0x10:
1356 /* Check if IVHD EFR contains proper max banks/counters */
1357 if ((h->efr_attr != 0) &&
1358 ((h->efr_attr & (0xF << 13)) != 0) &&
1359 ((h->efr_attr & (0x3F << 17)) != 0))
1360 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1361 else
1362 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1363 if (((h->efr_attr & (0x1 << IOMMU_FEAT_GASUP_SHIFT)) == 0))
1364 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1365 break;
1366 case 0x11:
1367 case 0x40:
1368 if (h->efr_reg & (1 << 9))
1369 iommu->mmio_phys_end = MMIO_REG_END_OFFSET;
1370 else
1371 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET;
1372 if (((h->efr_reg & (0x1 << IOMMU_EFR_GASUP_SHIFT)) == 0))
1373 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378
1379 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys,
1380 iommu->mmio_phys_end);
1381 if (!iommu->mmio_base)
1382 return -ENOMEM;
1383
1384 if (alloc_command_buffer(iommu))
1385 return -ENOMEM;
1386
1387 if (alloc_event_buffer(iommu))
1388 return -ENOMEM;
1389
1390 iommu->int_enabled = false;
1391
1392 ret = init_iommu_from_acpi(iommu, h);
1393 if (ret)
1394 return ret;
1395
1396 ret = amd_iommu_create_irq_domain(iommu);
1397 if (ret)
1398 return ret;
1399
1400 /*
1401 * Make sure IOMMU is not considered to translate itself. The IVRS
1402 * table tells us so, but this is a lie!
1403 */
1404 amd_iommu_rlookup_table[iommu->devid] = NULL;
1405
1406 return 0;
1407 }
1408
1409 /**
1410 * get_highest_supported_ivhd_type - Look up the appropriate IVHD type
1411 * @ivrs Pointer to the IVRS header
1412 *
1413 * This function search through all IVDB of the maximum supported IVHD
1414 */
1415 static u8 get_highest_supported_ivhd_type(struct acpi_table_header *ivrs)
1416 {
1417 u8 *base = (u8 *)ivrs;
1418 struct ivhd_header *ivhd = (struct ivhd_header *)
1419 (base + IVRS_HEADER_LENGTH);
1420 u8 last_type = ivhd->type;
1421 u16 devid = ivhd->devid;
1422
1423 while (((u8 *)ivhd - base < ivrs->length) &&
1424 (ivhd->type <= ACPI_IVHD_TYPE_MAX_SUPPORTED)) {
1425 u8 *p = (u8 *) ivhd;
1426
1427 if (ivhd->devid == devid)
1428 last_type = ivhd->type;
1429 ivhd = (struct ivhd_header *)(p + ivhd->length);
1430 }
1431
1432 return last_type;
1433 }
1434
1435 /*
1436 * Iterates over all IOMMU entries in the ACPI table, allocates the
1437 * IOMMU structure and initializes it with init_iommu_one()
1438 */
1439 static int __init init_iommu_all(struct acpi_table_header *table)
1440 {
1441 u8 *p = (u8 *)table, *end = (u8 *)table;
1442 struct ivhd_header *h;
1443 struct amd_iommu *iommu;
1444 int ret;
1445
1446 end += table->length;
1447 p += IVRS_HEADER_LENGTH;
1448
1449 while (p < end) {
1450 h = (struct ivhd_header *)p;
1451 if (*p == amd_iommu_target_ivhd_type) {
1452
1453 DUMP_printk("device: %02x:%02x.%01x cap: %04x "
1454 "seg: %d flags: %01x info %04x\n",
1455 PCI_BUS_NUM(h->devid), PCI_SLOT(h->devid),
1456 PCI_FUNC(h->devid), h->cap_ptr,
1457 h->pci_seg, h->flags, h->info);
1458 DUMP_printk(" mmio-addr: %016llx\n",
1459 h->mmio_phys);
1460
1461 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL);
1462 if (iommu == NULL)
1463 return -ENOMEM;
1464
1465 ret = init_iommu_one(iommu, h);
1466 if (ret)
1467 return ret;
1468 }
1469 p += h->length;
1470
1471 }
1472 WARN_ON(p != end);
1473
1474 return 0;
1475 }
1476
1477
1478 static void init_iommu_perf_ctr(struct amd_iommu *iommu)
1479 {
1480 u64 val = 0xabcd, val2 = 0;
1481
1482 if (!iommu_feature(iommu, FEATURE_PC))
1483 return;
1484
1485 amd_iommu_pc_present = true;
1486
1487 /* Check if the performance counters can be written to */
1488 if ((0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val, true)) ||
1489 (0 != iommu_pc_get_set_reg_val(iommu, 0, 0, 0, &val2, false)) ||
1490 (val != val2)) {
1491 pr_err("AMD-Vi: Unable to write to IOMMU perf counter.\n");
1492 amd_iommu_pc_present = false;
1493 return;
1494 }
1495
1496 pr_info("AMD-Vi: IOMMU performance counters supported\n");
1497
1498 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET);
1499 iommu->max_banks = (u8) ((val >> 12) & 0x3f);
1500 iommu->max_counters = (u8) ((val >> 7) & 0xf);
1501 }
1502
1503 static ssize_t amd_iommu_show_cap(struct device *dev,
1504 struct device_attribute *attr,
1505 char *buf)
1506 {
1507 struct amd_iommu *iommu = dev_get_drvdata(dev);
1508 return sprintf(buf, "%x\n", iommu->cap);
1509 }
1510 static DEVICE_ATTR(cap, S_IRUGO, amd_iommu_show_cap, NULL);
1511
1512 static ssize_t amd_iommu_show_features(struct device *dev,
1513 struct device_attribute *attr,
1514 char *buf)
1515 {
1516 struct amd_iommu *iommu = dev_get_drvdata(dev);
1517 return sprintf(buf, "%llx\n", iommu->features);
1518 }
1519 static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
1520
1521 static struct attribute *amd_iommu_attrs[] = {
1522 &dev_attr_cap.attr,
1523 &dev_attr_features.attr,
1524 NULL,
1525 };
1526
1527 static struct attribute_group amd_iommu_group = {
1528 .name = "amd-iommu",
1529 .attrs = amd_iommu_attrs,
1530 };
1531
1532 static const struct attribute_group *amd_iommu_groups[] = {
1533 &amd_iommu_group,
1534 NULL,
1535 };
1536
1537 static int iommu_init_pci(struct amd_iommu *iommu)
1538 {
1539 int cap_ptr = iommu->cap_ptr;
1540 u32 range, misc, low, high;
1541 int ret;
1542
1543 iommu->dev = pci_get_bus_and_slot(PCI_BUS_NUM(iommu->devid),
1544 iommu->devid & 0xff);
1545 if (!iommu->dev)
1546 return -ENODEV;
1547
1548 /* Prevent binding other PCI device drivers to IOMMU devices */
1549 iommu->dev->match_driver = false;
1550
1551 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET,
1552 &iommu->cap);
1553 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_RANGE_OFFSET,
1554 &range);
1555 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_MISC_OFFSET,
1556 &misc);
1557
1558 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB)))
1559 amd_iommu_iotlb_sup = false;
1560
1561 /* read extended feature bits */
1562 low = readl(iommu->mmio_base + MMIO_EXT_FEATURES);
1563 high = readl(iommu->mmio_base + MMIO_EXT_FEATURES + 4);
1564
1565 iommu->features = ((u64)high << 32) | low;
1566
1567 if (iommu_feature(iommu, FEATURE_GT)) {
1568 int glxval;
1569 u32 max_pasid;
1570 u64 pasmax;
1571
1572 pasmax = iommu->features & FEATURE_PASID_MASK;
1573 pasmax >>= FEATURE_PASID_SHIFT;
1574 max_pasid = (1 << (pasmax + 1)) - 1;
1575
1576 amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
1577
1578 BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
1579
1580 glxval = iommu->features & FEATURE_GLXVAL_MASK;
1581 glxval >>= FEATURE_GLXVAL_SHIFT;
1582
1583 if (amd_iommu_max_glx_val == -1)
1584 amd_iommu_max_glx_val = glxval;
1585 else
1586 amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
1587 }
1588
1589 if (iommu_feature(iommu, FEATURE_GT) &&
1590 iommu_feature(iommu, FEATURE_PPR)) {
1591 iommu->is_iommu_v2 = true;
1592 amd_iommu_v2_present = true;
1593 }
1594
1595 if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
1596 return -ENOMEM;
1597
1598 ret = iommu_init_ga(iommu);
1599 if (ret)
1600 return ret;
1601
1602 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE))
1603 amd_iommu_np_cache = true;
1604
1605 init_iommu_perf_ctr(iommu);
1606
1607 if (is_rd890_iommu(iommu->dev)) {
1608 int i, j;
1609
1610 iommu->root_pdev = pci_get_bus_and_slot(iommu->dev->bus->number,
1611 PCI_DEVFN(0, 0));
1612
1613 /*
1614 * Some rd890 systems may not be fully reconfigured by the
1615 * BIOS, so it's necessary for us to store this information so
1616 * it can be reprogrammed on resume
1617 */
1618 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4,
1619 &iommu->stored_addr_lo);
1620 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8,
1621 &iommu->stored_addr_hi);
1622
1623 /* Low bit locks writes to configuration space */
1624 iommu->stored_addr_lo &= ~1;
1625
1626 for (i = 0; i < 6; i++)
1627 for (j = 0; j < 0x12; j++)
1628 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j);
1629
1630 for (i = 0; i < 0x83; i++)
1631 iommu->stored_l2[i] = iommu_read_l2(iommu, i);
1632 }
1633
1634 amd_iommu_erratum_746_workaround(iommu);
1635 amd_iommu_ats_write_check_workaround(iommu);
1636
1637 iommu->iommu_dev = iommu_device_create(&iommu->dev->dev, iommu,
1638 amd_iommu_groups, "ivhd%d",
1639 iommu->index);
1640
1641 return pci_enable_device(iommu->dev);
1642 }
1643
1644 static void print_iommu_info(void)
1645 {
1646 static const char * const feat_str[] = {
1647 "PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
1648 "IA", "GA", "HE", "PC"
1649 };
1650 struct amd_iommu *iommu;
1651
1652 for_each_iommu(iommu) {
1653 int i;
1654
1655 pr_info("AMD-Vi: Found IOMMU at %s cap 0x%hx\n",
1656 dev_name(&iommu->dev->dev), iommu->cap_ptr);
1657
1658 if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
1659 pr_info("AMD-Vi: Extended features (%#llx):\n",
1660 iommu->features);
1661 for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
1662 if (iommu_feature(iommu, (1ULL << i)))
1663 pr_cont(" %s", feat_str[i]);
1664 }
1665
1666 if (iommu->features & FEATURE_GAM_VAPIC)
1667 pr_cont(" GA_vAPIC");
1668
1669 pr_cont("\n");
1670 }
1671 }
1672 if (irq_remapping_enabled) {
1673 pr_info("AMD-Vi: Interrupt remapping enabled\n");
1674 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
1675 pr_info("AMD-Vi: virtual APIC enabled\n");
1676 }
1677 }
1678
1679 static int __init amd_iommu_init_pci(void)
1680 {
1681 struct amd_iommu *iommu;
1682 int ret = 0;
1683
1684 for_each_iommu(iommu) {
1685 ret = iommu_init_pci(iommu);
1686 if (ret)
1687 break;
1688 }
1689
1690 /*
1691 * Order is important here to make sure any unity map requirements are
1692 * fulfilled. The unity mappings are created and written to the device
1693 * table during the amd_iommu_init_api() call.
1694 *
1695 * After that we call init_device_table_dma() to make sure any
1696 * uninitialized DTE will block DMA, and in the end we flush the caches
1697 * of all IOMMUs to make sure the changes to the device table are
1698 * active.
1699 */
1700 ret = amd_iommu_init_api();
1701
1702 init_device_table_dma();
1703
1704 for_each_iommu(iommu)
1705 iommu_flush_all_caches(iommu);
1706
1707 if (!ret)
1708 print_iommu_info();
1709
1710 return ret;
1711 }
1712
1713 /****************************************************************************
1714 *
1715 * The following functions initialize the MSI interrupts for all IOMMUs
1716 * in the system. It's a bit challenging because there could be multiple
1717 * IOMMUs per PCI BDF but we can call pci_enable_msi(x) only once per
1718 * pci_dev.
1719 *
1720 ****************************************************************************/
1721
1722 static int iommu_setup_msi(struct amd_iommu *iommu)
1723 {
1724 int r;
1725
1726 r = pci_enable_msi(iommu->dev);
1727 if (r)
1728 return r;
1729
1730 r = request_threaded_irq(iommu->dev->irq,
1731 amd_iommu_int_handler,
1732 amd_iommu_int_thread,
1733 0, "AMD-Vi",
1734 iommu);
1735
1736 if (r) {
1737 pci_disable_msi(iommu->dev);
1738 return r;
1739 }
1740
1741 iommu->int_enabled = true;
1742
1743 return 0;
1744 }
1745
1746 static int iommu_init_msi(struct amd_iommu *iommu)
1747 {
1748 int ret;
1749
1750 if (iommu->int_enabled)
1751 goto enable_faults;
1752
1753 if (iommu->dev->msi_cap)
1754 ret = iommu_setup_msi(iommu);
1755 else
1756 ret = -ENODEV;
1757
1758 if (ret)
1759 return ret;
1760
1761 enable_faults:
1762 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN);
1763
1764 if (iommu->ppr_log != NULL)
1765 iommu_feature_enable(iommu, CONTROL_PPFINT_EN);
1766
1767 iommu_ga_log_enable(iommu);
1768
1769 return 0;
1770 }
1771
1772 /****************************************************************************
1773 *
1774 * The next functions belong to the third pass of parsing the ACPI
1775 * table. In this last pass the memory mapping requirements are
1776 * gathered (like exclusion and unity mapping ranges).
1777 *
1778 ****************************************************************************/
1779
1780 static void __init free_unity_maps(void)
1781 {
1782 struct unity_map_entry *entry, *next;
1783
1784 list_for_each_entry_safe(entry, next, &amd_iommu_unity_map, list) {
1785 list_del(&entry->list);
1786 kfree(entry);
1787 }
1788 }
1789
1790 /* called when we find an exclusion range definition in ACPI */
1791 static int __init init_exclusion_range(struct ivmd_header *m)
1792 {
1793 int i;
1794
1795 switch (m->type) {
1796 case ACPI_IVMD_TYPE:
1797 set_device_exclusion_range(m->devid, m);
1798 break;
1799 case ACPI_IVMD_TYPE_ALL:
1800 for (i = 0; i <= amd_iommu_last_bdf; ++i)
1801 set_device_exclusion_range(i, m);
1802 break;
1803 case ACPI_IVMD_TYPE_RANGE:
1804 for (i = m->devid; i <= m->aux; ++i)
1805 set_device_exclusion_range(i, m);
1806 break;
1807 default:
1808 break;
1809 }
1810
1811 return 0;
1812 }
1813
1814 /* called for unity map ACPI definition */
1815 static int __init init_unity_map_range(struct ivmd_header *m)
1816 {
1817 struct unity_map_entry *e = NULL;
1818 char *s;
1819
1820 e = kzalloc(sizeof(*e), GFP_KERNEL);
1821 if (e == NULL)
1822 return -ENOMEM;
1823
1824 switch (m->type) {
1825 default:
1826 kfree(e);
1827 return 0;
1828 case ACPI_IVMD_TYPE:
1829 s = "IVMD_TYPEi\t\t\t";
1830 e->devid_start = e->devid_end = m->devid;
1831 break;
1832 case ACPI_IVMD_TYPE_ALL:
1833 s = "IVMD_TYPE_ALL\t\t";
1834 e->devid_start = 0;
1835 e->devid_end = amd_iommu_last_bdf;
1836 break;
1837 case ACPI_IVMD_TYPE_RANGE:
1838 s = "IVMD_TYPE_RANGE\t\t";
1839 e->devid_start = m->devid;
1840 e->devid_end = m->aux;
1841 break;
1842 }
1843 e->address_start = PAGE_ALIGN(m->range_start);
1844 e->address_end = e->address_start + PAGE_ALIGN(m->range_length);
1845 e->prot = m->flags >> 1;
1846
1847 DUMP_printk("%s devid_start: %02x:%02x.%x devid_end: %02x:%02x.%x"
1848 " range_start: %016llx range_end: %016llx flags: %x\n", s,
1849 PCI_BUS_NUM(e->devid_start), PCI_SLOT(e->devid_start),
1850 PCI_FUNC(e->devid_start), PCI_BUS_NUM(e->devid_end),
1851 PCI_SLOT(e->devid_end), PCI_FUNC(e->devid_end),
1852 e->address_start, e->address_end, m->flags);
1853
1854 list_add_tail(&e->list, &amd_iommu_unity_map);
1855
1856 return 0;
1857 }
1858
1859 /* iterates over all memory definitions we find in the ACPI table */
1860 static int __init init_memory_definitions(struct acpi_table_header *table)
1861 {
1862 u8 *p = (u8 *)table, *end = (u8 *)table;
1863 struct ivmd_header *m;
1864
1865 end += table->length;
1866 p += IVRS_HEADER_LENGTH;
1867
1868 while (p < end) {
1869 m = (struct ivmd_header *)p;
1870 if (m->flags & IVMD_FLAG_EXCL_RANGE)
1871 init_exclusion_range(m);
1872 else if (m->flags & IVMD_FLAG_UNITY_MAP)
1873 init_unity_map_range(m);
1874
1875 p += m->length;
1876 }
1877
1878 return 0;
1879 }
1880
1881 /*
1882 * Init the device table to not allow DMA access for devices and
1883 * suppress all page faults
1884 */
1885 static void init_device_table_dma(void)
1886 {
1887 u32 devid;
1888
1889 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1890 set_dev_entry_bit(devid, DEV_ENTRY_VALID);
1891 set_dev_entry_bit(devid, DEV_ENTRY_TRANSLATION);
1892 }
1893 }
1894
1895 static void __init uninit_device_table_dma(void)
1896 {
1897 u32 devid;
1898
1899 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid) {
1900 amd_iommu_dev_table[devid].data[0] = 0ULL;
1901 amd_iommu_dev_table[devid].data[1] = 0ULL;
1902 }
1903 }
1904
1905 static void init_device_table(void)
1906 {
1907 u32 devid;
1908
1909 if (!amd_iommu_irq_remap)
1910 return;
1911
1912 for (devid = 0; devid <= amd_iommu_last_bdf; ++devid)
1913 set_dev_entry_bit(devid, DEV_ENTRY_IRQ_TBL_EN);
1914 }
1915
1916 static void iommu_init_flags(struct amd_iommu *iommu)
1917 {
1918 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ?
1919 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) :
1920 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN);
1921
1922 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ?
1923 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) :
1924 iommu_feature_disable(iommu, CONTROL_PASSPW_EN);
1925
1926 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ?
1927 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) :
1928 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN);
1929
1930 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ?
1931 iommu_feature_enable(iommu, CONTROL_ISOC_EN) :
1932 iommu_feature_disable(iommu, CONTROL_ISOC_EN);
1933
1934 /*
1935 * make IOMMU memory accesses cache coherent
1936 */
1937 iommu_feature_enable(iommu, CONTROL_COHERENT_EN);
1938
1939 /* Set IOTLB invalidation timeout to 1s */
1940 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S);
1941 }
1942
1943 static void iommu_apply_resume_quirks(struct amd_iommu *iommu)
1944 {
1945 int i, j;
1946 u32 ioc_feature_control;
1947 struct pci_dev *pdev = iommu->root_pdev;
1948
1949 /* RD890 BIOSes may not have completely reconfigured the iommu */
1950 if (!is_rd890_iommu(iommu->dev) || !pdev)
1951 return;
1952
1953 /*
1954 * First, we need to ensure that the iommu is enabled. This is
1955 * controlled by a register in the northbridge
1956 */
1957
1958 /* Select Northbridge indirect register 0x75 and enable writing */
1959 pci_write_config_dword(pdev, 0x60, 0x75 | (1 << 7));
1960 pci_read_config_dword(pdev, 0x64, &ioc_feature_control);
1961
1962 /* Enable the iommu */
1963 if (!(ioc_feature_control & 0x1))
1964 pci_write_config_dword(pdev, 0x64, ioc_feature_control | 1);
1965
1966 /* Restore the iommu BAR */
1967 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1968 iommu->stored_addr_lo);
1969 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8,
1970 iommu->stored_addr_hi);
1971
1972 /* Restore the l1 indirect regs for each of the 6 l1s */
1973 for (i = 0; i < 6; i++)
1974 for (j = 0; j < 0x12; j++)
1975 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]);
1976
1977 /* Restore the l2 indirect regs */
1978 for (i = 0; i < 0x83; i++)
1979 iommu_write_l2(iommu, i, iommu->stored_l2[i]);
1980
1981 /* Lock PCI setup registers */
1982 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4,
1983 iommu->stored_addr_lo | 1);
1984 }
1985
1986 static void iommu_enable_ga(struct amd_iommu *iommu)
1987 {
1988 #ifdef CONFIG_IRQ_REMAP
1989 switch (amd_iommu_guest_ir) {
1990 case AMD_IOMMU_GUEST_IR_VAPIC:
1991 iommu_feature_enable(iommu, CONTROL_GAM_EN);
1992 /* Fall through */
1993 case AMD_IOMMU_GUEST_IR_LEGACY_GA:
1994 iommu_feature_enable(iommu, CONTROL_GA_EN);
1995 iommu->irte_ops = &irte_128_ops;
1996 break;
1997 default:
1998 iommu->irte_ops = &irte_32_ops;
1999 break;
2000 }
2001 #endif
2002 }
2003
2004 /*
2005 * This function finally enables all IOMMUs found in the system after
2006 * they have been initialized
2007 */
2008 static void early_enable_iommus(void)
2009 {
2010 struct amd_iommu *iommu;
2011
2012 for_each_iommu(iommu) {
2013 iommu_disable(iommu);
2014 iommu_init_flags(iommu);
2015 iommu_set_device_table(iommu);
2016 iommu_enable_command_buffer(iommu);
2017 iommu_enable_event_buffer(iommu);
2018 iommu_set_exclusion_range(iommu);
2019 iommu_enable_ga(iommu);
2020 iommu_enable(iommu);
2021 iommu_flush_all_caches(iommu);
2022 }
2023
2024 #ifdef CONFIG_IRQ_REMAP
2025 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2026 amd_iommu_irq_ops.capability |= (1 << IRQ_POSTING_CAP);
2027 #endif
2028 }
2029
2030 static void enable_iommus_v2(void)
2031 {
2032 struct amd_iommu *iommu;
2033
2034 for_each_iommu(iommu) {
2035 iommu_enable_ppr_log(iommu);
2036 iommu_enable_gt(iommu);
2037 }
2038 }
2039
2040 static void enable_iommus(void)
2041 {
2042 early_enable_iommus();
2043
2044 enable_iommus_v2();
2045 }
2046
2047 static void disable_iommus(void)
2048 {
2049 struct amd_iommu *iommu;
2050
2051 for_each_iommu(iommu)
2052 iommu_disable(iommu);
2053
2054 #ifdef CONFIG_IRQ_REMAP
2055 if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir))
2056 amd_iommu_irq_ops.capability &= ~(1 << IRQ_POSTING_CAP);
2057 #endif
2058 }
2059
2060 /*
2061 * Suspend/Resume support
2062 * disable suspend until real resume implemented
2063 */
2064
2065 static void amd_iommu_resume(void)
2066 {
2067 struct amd_iommu *iommu;
2068
2069 for_each_iommu(iommu)
2070 iommu_apply_resume_quirks(iommu);
2071
2072 /* re-load the hardware */
2073 enable_iommus();
2074
2075 amd_iommu_enable_interrupts();
2076 }
2077
2078 static int amd_iommu_suspend(void)
2079 {
2080 /* disable IOMMUs to go out of the way for BIOS */
2081 disable_iommus();
2082
2083 return 0;
2084 }
2085
2086 static struct syscore_ops amd_iommu_syscore_ops = {
2087 .suspend = amd_iommu_suspend,
2088 .resume = amd_iommu_resume,
2089 };
2090
2091 static void __init free_on_init_error(void)
2092 {
2093 free_pages((unsigned long)irq_lookup_table,
2094 get_order(rlookup_table_size));
2095
2096 kmem_cache_destroy(amd_iommu_irq_cache);
2097 amd_iommu_irq_cache = NULL;
2098
2099 free_pages((unsigned long)amd_iommu_rlookup_table,
2100 get_order(rlookup_table_size));
2101
2102 free_pages((unsigned long)amd_iommu_alias_table,
2103 get_order(alias_table_size));
2104
2105 free_pages((unsigned long)amd_iommu_dev_table,
2106 get_order(dev_table_size));
2107
2108 free_iommu_all();
2109
2110 #ifdef CONFIG_GART_IOMMU
2111 /*
2112 * We failed to initialize the AMD IOMMU - try fallback to GART
2113 * if possible.
2114 */
2115 gart_iommu_init();
2116
2117 #endif
2118 }
2119
2120 /* SB IOAPIC is always on this device in AMD systems */
2121 #define IOAPIC_SB_DEVID ((0x00 << 8) | PCI_DEVFN(0x14, 0))
2122
2123 static bool __init check_ioapic_information(void)
2124 {
2125 const char *fw_bug = FW_BUG;
2126 bool ret, has_sb_ioapic;
2127 int idx;
2128
2129 has_sb_ioapic = false;
2130 ret = false;
2131
2132 /*
2133 * If we have map overrides on the kernel command line the
2134 * messages in this function might not describe firmware bugs
2135 * anymore - so be careful
2136 */
2137 if (cmdline_maps)
2138 fw_bug = "";
2139
2140 for (idx = 0; idx < nr_ioapics; idx++) {
2141 int devid, id = mpc_ioapic_id(idx);
2142
2143 devid = get_ioapic_devid(id);
2144 if (devid < 0) {
2145 pr_err("%sAMD-Vi: IOAPIC[%d] not in IVRS table\n",
2146 fw_bug, id);
2147 ret = false;
2148 } else if (devid == IOAPIC_SB_DEVID) {
2149 has_sb_ioapic = true;
2150 ret = true;
2151 }
2152 }
2153
2154 if (!has_sb_ioapic) {
2155 /*
2156 * We expect the SB IOAPIC to be listed in the IVRS
2157 * table. The system timer is connected to the SB IOAPIC
2158 * and if we don't have it in the list the system will
2159 * panic at boot time. This situation usually happens
2160 * when the BIOS is buggy and provides us the wrong
2161 * device id for the IOAPIC in the system.
2162 */
2163 pr_err("%sAMD-Vi: No southbridge IOAPIC found\n", fw_bug);
2164 }
2165
2166 if (!ret)
2167 pr_err("AMD-Vi: Disabling interrupt remapping\n");
2168
2169 return ret;
2170 }
2171
2172 static void __init free_dma_resources(void)
2173 {
2174 free_pages((unsigned long)amd_iommu_pd_alloc_bitmap,
2175 get_order(MAX_DOMAIN_ID/8));
2176
2177 free_unity_maps();
2178 }
2179
2180 /*
2181 * This is the hardware init function for AMD IOMMU in the system.
2182 * This function is called either from amd_iommu_init or from the interrupt
2183 * remapping setup code.
2184 *
2185 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
2186 * four times:
2187 *
2188 * 1 pass) Discover the most comprehensive IVHD type to use.
2189 *
2190 * 2 pass) Find the highest PCI device id the driver has to handle.
2191 * Upon this information the size of the data structures is
2192 * determined that needs to be allocated.
2193 *
2194 * 3 pass) Initialize the data structures just allocated with the
2195 * information in the ACPI table about available AMD IOMMUs
2196 * in the system. It also maps the PCI devices in the
2197 * system to specific IOMMUs
2198 *
2199 * 4 pass) After the basic data structures are allocated and
2200 * initialized we update them with information about memory
2201 * remapping requirements parsed out of the ACPI table in
2202 * this last pass.
2203 *
2204 * After everything is set up the IOMMUs are enabled and the necessary
2205 * hotplug and suspend notifiers are registered.
2206 */
2207 static int __init early_amd_iommu_init(void)
2208 {
2209 struct acpi_table_header *ivrs_base;
2210 acpi_size ivrs_size;
2211 acpi_status status;
2212 int i, remap_cache_sz, ret = 0;
2213
2214 if (!amd_iommu_detected)
2215 return -ENODEV;
2216
2217 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2218 if (status == AE_NOT_FOUND)
2219 return -ENODEV;
2220 else if (ACPI_FAILURE(status)) {
2221 const char *err = acpi_format_exception(status);
2222 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2223 return -EINVAL;
2224 }
2225
2226 /*
2227 * Validate checksum here so we don't need to do it when
2228 * we actually parse the table
2229 */
2230 ret = check_ivrs_checksum(ivrs_base);
2231 if (ret)
2232 return ret;
2233
2234 amd_iommu_target_ivhd_type = get_highest_supported_ivhd_type(ivrs_base);
2235 DUMP_printk("Using IVHD type %#x\n", amd_iommu_target_ivhd_type);
2236
2237 /*
2238 * First parse ACPI tables to find the largest Bus/Dev/Func
2239 * we need to handle. Upon this information the shared data
2240 * structures for the IOMMUs in the system will be allocated
2241 */
2242 ret = find_last_devid_acpi(ivrs_base);
2243 if (ret)
2244 goto out;
2245
2246 dev_table_size = tbl_size(DEV_TABLE_ENTRY_SIZE);
2247 alias_table_size = tbl_size(ALIAS_TABLE_ENTRY_SIZE);
2248 rlookup_table_size = tbl_size(RLOOKUP_TABLE_ENTRY_SIZE);
2249
2250 /* Device table - directly used by all IOMMUs */
2251 ret = -ENOMEM;
2252 amd_iommu_dev_table = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO,
2253 get_order(dev_table_size));
2254 if (amd_iommu_dev_table == NULL)
2255 goto out;
2256
2257 /*
2258 * Alias table - map PCI Bus/Dev/Func to Bus/Dev/Func the
2259 * IOMMU see for that device
2260 */
2261 amd_iommu_alias_table = (void *)__get_free_pages(GFP_KERNEL,
2262 get_order(alias_table_size));
2263 if (amd_iommu_alias_table == NULL)
2264 goto out;
2265
2266 /* IOMMU rlookup table - find the IOMMU for a specific device */
2267 amd_iommu_rlookup_table = (void *)__get_free_pages(
2268 GFP_KERNEL | __GFP_ZERO,
2269 get_order(rlookup_table_size));
2270 if (amd_iommu_rlookup_table == NULL)
2271 goto out;
2272
2273 amd_iommu_pd_alloc_bitmap = (void *)__get_free_pages(
2274 GFP_KERNEL | __GFP_ZERO,
2275 get_order(MAX_DOMAIN_ID/8));
2276 if (amd_iommu_pd_alloc_bitmap == NULL)
2277 goto out;
2278
2279 /*
2280 * let all alias entries point to itself
2281 */
2282 for (i = 0; i <= amd_iommu_last_bdf; ++i)
2283 amd_iommu_alias_table[i] = i;
2284
2285 /*
2286 * never allocate domain 0 because its used as the non-allocated and
2287 * error value placeholder
2288 */
2289 __set_bit(0, amd_iommu_pd_alloc_bitmap);
2290
2291 spin_lock_init(&amd_iommu_pd_lock);
2292
2293 /*
2294 * now the data structures are allocated and basically initialized
2295 * start the real acpi table scan
2296 */
2297 ret = init_iommu_all(ivrs_base);
2298 if (ret)
2299 goto out;
2300
2301 if (amd_iommu_irq_remap)
2302 amd_iommu_irq_remap = check_ioapic_information();
2303
2304 if (amd_iommu_irq_remap) {
2305 /*
2306 * Interrupt remapping enabled, create kmem_cache for the
2307 * remapping tables.
2308 */
2309 ret = -ENOMEM;
2310 if (!AMD_IOMMU_GUEST_IR_GA(amd_iommu_guest_ir))
2311 remap_cache_sz = MAX_IRQS_PER_TABLE * sizeof(u32);
2312 else
2313 remap_cache_sz = MAX_IRQS_PER_TABLE * (sizeof(u64) * 2);
2314 amd_iommu_irq_cache = kmem_cache_create("irq_remap_cache",
2315 remap_cache_sz,
2316 IRQ_TABLE_ALIGNMENT,
2317 0, NULL);
2318 if (!amd_iommu_irq_cache)
2319 goto out;
2320
2321 irq_lookup_table = (void *)__get_free_pages(
2322 GFP_KERNEL | __GFP_ZERO,
2323 get_order(rlookup_table_size));
2324 if (!irq_lookup_table)
2325 goto out;
2326 }
2327
2328 ret = init_memory_definitions(ivrs_base);
2329 if (ret)
2330 goto out;
2331
2332 /* init the device table */
2333 init_device_table();
2334
2335 out:
2336 /* Don't leak any ACPI memory */
2337 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2338 ivrs_base = NULL;
2339
2340 return ret;
2341 }
2342
2343 static int amd_iommu_enable_interrupts(void)
2344 {
2345 struct amd_iommu *iommu;
2346 int ret = 0;
2347
2348 for_each_iommu(iommu) {
2349 ret = iommu_init_msi(iommu);
2350 if (ret)
2351 goto out;
2352 }
2353
2354 out:
2355 return ret;
2356 }
2357
2358 static bool detect_ivrs(void)
2359 {
2360 struct acpi_table_header *ivrs_base;
2361 acpi_size ivrs_size;
2362 acpi_status status;
2363
2364 status = acpi_get_table_with_size("IVRS", 0, &ivrs_base, &ivrs_size);
2365 if (status == AE_NOT_FOUND)
2366 return false;
2367 else if (ACPI_FAILURE(status)) {
2368 const char *err = acpi_format_exception(status);
2369 pr_err("AMD-Vi: IVRS table error: %s\n", err);
2370 return false;
2371 }
2372
2373 early_acpi_os_unmap_memory((char __iomem *)ivrs_base, ivrs_size);
2374
2375 /* Make sure ACS will be enabled during PCI probe */
2376 pci_request_acs();
2377
2378 return true;
2379 }
2380
2381 /****************************************************************************
2382 *
2383 * AMD IOMMU Initialization State Machine
2384 *
2385 ****************************************************************************/
2386
2387 static int __init state_next(void)
2388 {
2389 int ret = 0;
2390
2391 switch (init_state) {
2392 case IOMMU_START_STATE:
2393 if (!detect_ivrs()) {
2394 init_state = IOMMU_NOT_FOUND;
2395 ret = -ENODEV;
2396 } else {
2397 init_state = IOMMU_IVRS_DETECTED;
2398 }
2399 break;
2400 case IOMMU_IVRS_DETECTED:
2401 ret = early_amd_iommu_init();
2402 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_ACPI_FINISHED;
2403 break;
2404 case IOMMU_ACPI_FINISHED:
2405 early_enable_iommus();
2406 register_syscore_ops(&amd_iommu_syscore_ops);
2407 x86_platform.iommu_shutdown = disable_iommus;
2408 init_state = IOMMU_ENABLED;
2409 break;
2410 case IOMMU_ENABLED:
2411 ret = amd_iommu_init_pci();
2412 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_PCI_INIT;
2413 enable_iommus_v2();
2414 break;
2415 case IOMMU_PCI_INIT:
2416 ret = amd_iommu_enable_interrupts();
2417 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_INTERRUPTS_EN;
2418 break;
2419 case IOMMU_INTERRUPTS_EN:
2420 ret = amd_iommu_init_dma_ops();
2421 init_state = ret ? IOMMU_INIT_ERROR : IOMMU_DMA_OPS;
2422 break;
2423 case IOMMU_DMA_OPS:
2424 init_state = IOMMU_INITIALIZED;
2425 break;
2426 case IOMMU_INITIALIZED:
2427 /* Nothing to do */
2428 break;
2429 case IOMMU_NOT_FOUND:
2430 case IOMMU_INIT_ERROR:
2431 /* Error states => do nothing */
2432 ret = -EINVAL;
2433 break;
2434 default:
2435 /* Unknown state */
2436 BUG();
2437 }
2438
2439 return ret;
2440 }
2441
2442 static int __init iommu_go_to_state(enum iommu_init_state state)
2443 {
2444 int ret = 0;
2445
2446 while (init_state != state) {
2447 ret = state_next();
2448 if (init_state == IOMMU_NOT_FOUND ||
2449 init_state == IOMMU_INIT_ERROR)
2450 break;
2451 }
2452
2453 return ret;
2454 }
2455
2456 #ifdef CONFIG_IRQ_REMAP
2457 int __init amd_iommu_prepare(void)
2458 {
2459 int ret;
2460
2461 amd_iommu_irq_remap = true;
2462
2463 ret = iommu_go_to_state(IOMMU_ACPI_FINISHED);
2464 if (ret)
2465 return ret;
2466 return amd_iommu_irq_remap ? 0 : -ENODEV;
2467 }
2468
2469 int __init amd_iommu_enable(void)
2470 {
2471 int ret;
2472
2473 ret = iommu_go_to_state(IOMMU_ENABLED);
2474 if (ret)
2475 return ret;
2476
2477 irq_remapping_enabled = 1;
2478
2479 return 0;
2480 }
2481
2482 void amd_iommu_disable(void)
2483 {
2484 amd_iommu_suspend();
2485 }
2486
2487 int amd_iommu_reenable(int mode)
2488 {
2489 amd_iommu_resume();
2490
2491 return 0;
2492 }
2493
2494 int __init amd_iommu_enable_faulting(void)
2495 {
2496 /* We enable MSI later when PCI is initialized */
2497 return 0;
2498 }
2499 #endif
2500
2501 /*
2502 * This is the core init function for AMD IOMMU hardware in the system.
2503 * This function is called from the generic x86 DMA layer initialization
2504 * code.
2505 */
2506 static int __init amd_iommu_init(void)
2507 {
2508 int ret;
2509
2510 ret = iommu_go_to_state(IOMMU_INITIALIZED);
2511 if (ret) {
2512 free_dma_resources();
2513 if (!irq_remapping_enabled) {
2514 disable_iommus();
2515 free_on_init_error();
2516 } else {
2517 struct amd_iommu *iommu;
2518
2519 uninit_device_table_dma();
2520 for_each_iommu(iommu)
2521 iommu_flush_all_caches(iommu);
2522 }
2523 }
2524
2525 return ret;
2526 }
2527
2528 /****************************************************************************
2529 *
2530 * Early detect code. This code runs at IOMMU detection time in the DMA
2531 * layer. It just looks if there is an IVRS ACPI table to detect AMD
2532 * IOMMUs
2533 *
2534 ****************************************************************************/
2535 int __init amd_iommu_detect(void)
2536 {
2537 int ret;
2538
2539 if (no_iommu || (iommu_detected && !gart_iommu_aperture))
2540 return -ENODEV;
2541
2542 if (amd_iommu_disabled)
2543 return -ENODEV;
2544
2545 ret = iommu_go_to_state(IOMMU_IVRS_DETECTED);
2546 if (ret)
2547 return ret;
2548
2549 amd_iommu_detected = true;
2550 iommu_detected = 1;
2551 x86_init.iommu.iommu_init = amd_iommu_init;
2552
2553 return 1;
2554 }
2555
2556 /****************************************************************************
2557 *
2558 * Parsing functions for the AMD IOMMU specific kernel command line
2559 * options.
2560 *
2561 ****************************************************************************/
2562
2563 static int __init parse_amd_iommu_dump(char *str)
2564 {
2565 amd_iommu_dump = true;
2566
2567 return 1;
2568 }
2569
2570 static int __init parse_amd_iommu_intr(char *str)
2571 {
2572 for (; *str; ++str) {
2573 if (strncmp(str, "legacy", 6) == 0) {
2574 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY;
2575 break;
2576 }
2577 if (strncmp(str, "vapic", 5) == 0) {
2578 amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_VAPIC;
2579 break;
2580 }
2581 }
2582 return 1;
2583 }
2584
2585 static int __init parse_amd_iommu_options(char *str)
2586 {
2587 for (; *str; ++str) {
2588 if (strncmp(str, "fullflush", 9) == 0)
2589 amd_iommu_unmap_flush = true;
2590 if (strncmp(str, "off", 3) == 0)
2591 amd_iommu_disabled = true;
2592 if (strncmp(str, "force_isolation", 15) == 0)
2593 amd_iommu_force_isolation = true;
2594 }
2595
2596 return 1;
2597 }
2598
2599 static int __init parse_ivrs_ioapic(char *str)
2600 {
2601 unsigned int bus, dev, fn;
2602 int ret, id, i;
2603 u16 devid;
2604
2605 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2606
2607 if (ret != 4) {
2608 pr_err("AMD-Vi: Invalid command line: ivrs_ioapic%s\n", str);
2609 return 1;
2610 }
2611
2612 if (early_ioapic_map_size == EARLY_MAP_SIZE) {
2613 pr_err("AMD-Vi: Early IOAPIC map overflow - ignoring ivrs_ioapic%s\n",
2614 str);
2615 return 1;
2616 }
2617
2618 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2619
2620 cmdline_maps = true;
2621 i = early_ioapic_map_size++;
2622 early_ioapic_map[i].id = id;
2623 early_ioapic_map[i].devid = devid;
2624 early_ioapic_map[i].cmd_line = true;
2625
2626 return 1;
2627 }
2628
2629 static int __init parse_ivrs_hpet(char *str)
2630 {
2631 unsigned int bus, dev, fn;
2632 int ret, id, i;
2633 u16 devid;
2634
2635 ret = sscanf(str, "[%d]=%x:%x.%x", &id, &bus, &dev, &fn);
2636
2637 if (ret != 4) {
2638 pr_err("AMD-Vi: Invalid command line: ivrs_hpet%s\n", str);
2639 return 1;
2640 }
2641
2642 if (early_hpet_map_size == EARLY_MAP_SIZE) {
2643 pr_err("AMD-Vi: Early HPET map overflow - ignoring ivrs_hpet%s\n",
2644 str);
2645 return 1;
2646 }
2647
2648 devid = ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2649
2650 cmdline_maps = true;
2651 i = early_hpet_map_size++;
2652 early_hpet_map[i].id = id;
2653 early_hpet_map[i].devid = devid;
2654 early_hpet_map[i].cmd_line = true;
2655
2656 return 1;
2657 }
2658
2659 static int __init parse_ivrs_acpihid(char *str)
2660 {
2661 u32 bus, dev, fn;
2662 char *hid, *uid, *p;
2663 char acpiid[ACPIHID_UID_LEN + ACPIHID_HID_LEN] = {0};
2664 int ret, i;
2665
2666 ret = sscanf(str, "[%x:%x.%x]=%s", &bus, &dev, &fn, acpiid);
2667 if (ret != 4) {
2668 pr_err("AMD-Vi: Invalid command line: ivrs_acpihid(%s)\n", str);
2669 return 1;
2670 }
2671
2672 p = acpiid;
2673 hid = strsep(&p, ":");
2674 uid = p;
2675
2676 if (!hid || !(*hid) || !uid) {
2677 pr_err("AMD-Vi: Invalid command line: hid or uid\n");
2678 return 1;
2679 }
2680
2681 i = early_acpihid_map_size++;
2682 memcpy(early_acpihid_map[i].hid, hid, strlen(hid));
2683 memcpy(early_acpihid_map[i].uid, uid, strlen(uid));
2684 early_acpihid_map[i].devid =
2685 ((bus & 0xff) << 8) | ((dev & 0x1f) << 3) | (fn & 0x7);
2686 early_acpihid_map[i].cmd_line = true;
2687
2688 return 1;
2689 }
2690
2691 __setup("amd_iommu_dump", parse_amd_iommu_dump);
2692 __setup("amd_iommu=", parse_amd_iommu_options);
2693 __setup("amd_iommu_intr=", parse_amd_iommu_intr);
2694 __setup("ivrs_ioapic", parse_ivrs_ioapic);
2695 __setup("ivrs_hpet", parse_ivrs_hpet);
2696 __setup("ivrs_acpihid", parse_ivrs_acpihid);
2697
2698 IOMMU_INIT_FINISH(amd_iommu_detect,
2699 gart_iommu_hole_init,
2700 NULL,
2701 NULL);
2702
2703 bool amd_iommu_v2_supported(void)
2704 {
2705 return amd_iommu_v2_present;
2706 }
2707 EXPORT_SYMBOL(amd_iommu_v2_supported);
2708
2709 /****************************************************************************
2710 *
2711 * IOMMU EFR Performance Counter support functionality. This code allows
2712 * access to the IOMMU PC functionality.
2713 *
2714 ****************************************************************************/
2715
2716 u8 amd_iommu_pc_get_max_banks(u16 devid)
2717 {
2718 struct amd_iommu *iommu;
2719 u8 ret = 0;
2720
2721 /* locate the iommu governing the devid */
2722 iommu = amd_iommu_rlookup_table[devid];
2723 if (iommu)
2724 ret = iommu->max_banks;
2725
2726 return ret;
2727 }
2728 EXPORT_SYMBOL(amd_iommu_pc_get_max_banks);
2729
2730 bool amd_iommu_pc_supported(void)
2731 {
2732 return amd_iommu_pc_present;
2733 }
2734 EXPORT_SYMBOL(amd_iommu_pc_supported);
2735
2736 u8 amd_iommu_pc_get_max_counters(u16 devid)
2737 {
2738 struct amd_iommu *iommu;
2739 u8 ret = 0;
2740
2741 /* locate the iommu governing the devid */
2742 iommu = amd_iommu_rlookup_table[devid];
2743 if (iommu)
2744 ret = iommu->max_counters;
2745
2746 return ret;
2747 }
2748 EXPORT_SYMBOL(amd_iommu_pc_get_max_counters);
2749
2750 static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
2751 u8 bank, u8 cntr, u8 fxn,
2752 u64 *value, bool is_write)
2753 {
2754 u32 offset;
2755 u32 max_offset_lim;
2756
2757 /* Check for valid iommu and pc register indexing */
2758 if (WARN_ON((fxn > 0x28) || (fxn & 7)))
2759 return -ENODEV;
2760
2761 offset = (u32)(((0x40|bank) << 12) | (cntr << 8) | fxn);
2762
2763 /* Limit the offset to the hw defined mmio region aperture */
2764 max_offset_lim = (u32)(((0x40|iommu->max_banks) << 12) |
2765 (iommu->max_counters << 8) | 0x28);
2766 if ((offset < MMIO_CNTR_REG_OFFSET) ||
2767 (offset > max_offset_lim))
2768 return -EINVAL;
2769
2770 if (is_write) {
2771 writel((u32)*value, iommu->mmio_base + offset);
2772 writel((*value >> 32), iommu->mmio_base + offset + 4);
2773 } else {
2774 *value = readl(iommu->mmio_base + offset + 4);
2775 *value <<= 32;
2776 *value = readl(iommu->mmio_base + offset);
2777 }
2778
2779 return 0;
2780 }
2781 EXPORT_SYMBOL(amd_iommu_pc_get_set_reg_val);
2782
2783 int amd_iommu_pc_get_set_reg_val(u16 devid, u8 bank, u8 cntr, u8 fxn,
2784 u64 *value, bool is_write)
2785 {
2786 struct amd_iommu *iommu = amd_iommu_rlookup_table[devid];
2787
2788 /* Make sure the IOMMU PC resource is available */
2789 if (!amd_iommu_pc_present || iommu == NULL)
2790 return -ENODEV;
2791
2792 return iommu_pc_get_set_reg_val(iommu, bank, cntr, fxn,
2793 value, is_write);
2794 }
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