drivers/iommu/amd_iommu_types.h

   1 /*
   2  * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
   3  * Author: Joerg Roedel <jroedel@suse.de>
   4  *         Leo Duran <leo.duran@amd.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 as published
   8  * by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  18  */
  19
  20 #ifndef _ASM_X86_AMD_IOMMU_TYPES_H
  21 #define _ASM_X86_AMD_IOMMU_TYPES_H
  22
  23 #include <linux/types.h>
  24 #include <linux/mutex.h>
  25 #include <linux/msi.h>
  26 #include <linux/list.h>
  27 #include <linux/spinlock.h>
  28 #include <linux/pci.h>
  29 #include <linux/irqreturn.h>
  30
  31 /*
  32  * Maximum number of IOMMUs supported
  33  */
  34 #define MAX_IOMMUS      32
  35
  36 /*
  37  * some size calculation constants
  38  */
  39 #define DEV_TABLE_ENTRY_SIZE            32
  40 #define ALIAS_TABLE_ENTRY_SIZE          2
  41 #define RLOOKUP_TABLE_ENTRY_SIZE        (sizeof(void *))
  42
  43 /* Capability offsets used by the driver */
  44 #define MMIO_CAP_HDR_OFFSET     0x00
  45 #define MMIO_RANGE_OFFSET       0x0c
  46 #define MMIO_MISC_OFFSET        0x10
  47
  48 /* Masks, shifts and macros to parse the device range capability */
  49 #define MMIO_RANGE_LD_MASK      0xff000000
  50 #define MMIO_RANGE_FD_MASK      0x00ff0000
  51 #define MMIO_RANGE_BUS_MASK     0x0000ff00
  52 #define MMIO_RANGE_LD_SHIFT     24
  53 #define MMIO_RANGE_FD_SHIFT     16
  54 #define MMIO_RANGE_BUS_SHIFT    8
  55 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
  56 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
  57 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
  58 #define MMIO_MSI_NUM(x) ((x) & 0x1f)
  59
  60 /* Flag masks for the AMD IOMMU exclusion range */
  61 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
  62 #define MMIO_EXCL_ALLOW_MASK  0x02ULL
  63
  64 /* Used offsets into the MMIO space */
  65 #define MMIO_DEV_TABLE_OFFSET   0x0000
  66 #define MMIO_CMD_BUF_OFFSET     0x0008
  67 #define MMIO_EVT_BUF_OFFSET     0x0010
  68 #define MMIO_CONTROL_OFFSET     0x0018
  69 #define MMIO_EXCL_BASE_OFFSET   0x0020
  70 #define MMIO_EXCL_LIMIT_OFFSET  0x0028
  71 #define MMIO_EXT_FEATURES       0x0030
  72 #define MMIO_PPR_LOG_OFFSET     0x0038
  73 #define MMIO_GA_LOG_BASE_OFFSET 0x00e0
  74 #define MMIO_GA_LOG_TAIL_OFFSET 0x00e8
  75 #define MMIO_CMD_HEAD_OFFSET    0x2000
  76 #define MMIO_CMD_TAIL_OFFSET    0x2008
  77 #define MMIO_EVT_HEAD_OFFSET    0x2010
  78 #define MMIO_EVT_TAIL_OFFSET    0x2018
  79 #define MMIO_STATUS_OFFSET      0x2020
  80 #define MMIO_PPR_HEAD_OFFSET    0x2030
  81 #define MMIO_PPR_TAIL_OFFSET    0x2038
  82 #define MMIO_GA_HEAD_OFFSET     0x2040
  83 #define MMIO_GA_TAIL_OFFSET     0x2048
  84 #define MMIO_CNTR_CONF_OFFSET   0x4000
  85 #define MMIO_CNTR_REG_OFFSET    0x40000
  86 #define MMIO_REG_END_OFFSET     0x80000
  87
  88
  89
  90 /* Extended Feature Bits */
  91 #define FEATURE_PREFETCH        (1ULL<<0)
  92 #define FEATURE_PPR             (1ULL<<1)
  93 #define FEATURE_X2APIC          (1ULL<<2)
  94 #define FEATURE_NX              (1ULL<<3)
  95 #define FEATURE_GT              (1ULL<<4)
  96 #define FEATURE_IA              (1ULL<<6)
  97 #define FEATURE_GA              (1ULL<<7)
  98 #define FEATURE_HE              (1ULL<<8)
  99 #define FEATURE_PC              (1ULL<<9)
 100 #define FEATURE_GAM_VAPIC       (1ULL<<21)
 101
 102 #define FEATURE_PASID_SHIFT     32
 103 #define FEATURE_PASID_MASK      (0x1fULL << FEATURE_PASID_SHIFT)
 104
 105 #define FEATURE_GLXVAL_SHIFT    14
 106 #define FEATURE_GLXVAL_MASK     (0x03ULL << FEATURE_GLXVAL_SHIFT)
 107
 108 /* Note:
 109  * The current driver only support 16-bit PASID.
 110  * Currently, hardware only implement upto 16-bit PASID
 111  * even though the spec says it could have upto 20 bits.
 112  */
 113 #define PASID_MASK              0x0000ffff
 114
 115 /* MMIO status bits */
 116 #define MMIO_STATUS_EVT_INT_MASK        (1 << 1)
 117 #define MMIO_STATUS_COM_WAIT_INT_MASK   (1 << 2)
 118 #define MMIO_STATUS_PPR_INT_MASK        (1 << 6)
 119 #define MMIO_STATUS_GALOG_RUN_MASK      (1 << 8)
 120 #define MMIO_STATUS_GALOG_OVERFLOW_MASK (1 << 9)
 121 #define MMIO_STATUS_GALOG_INT_MASK      (1 << 10)
 122
 123 /* event logging constants */
 124 #define EVENT_ENTRY_SIZE        0x10
 125 #define EVENT_TYPE_SHIFT        28
 126 #define EVENT_TYPE_MASK         0xf
 127 #define EVENT_TYPE_ILL_DEV      0x1
 128 #define EVENT_TYPE_IO_FAULT     0x2
 129 #define EVENT_TYPE_DEV_TAB_ERR  0x3
 130 #define EVENT_TYPE_PAGE_TAB_ERR 0x4
 131 #define EVENT_TYPE_ILL_CMD      0x5
 132 #define EVENT_TYPE_CMD_HARD_ERR 0x6
 133 #define EVENT_TYPE_IOTLB_INV_TO 0x7
 134 #define EVENT_TYPE_INV_DEV_REQ  0x8
 135 #define EVENT_DEVID_MASK        0xffff
 136 #define EVENT_DEVID_SHIFT       0
 137 #define EVENT_DOMID_MASK        0xffff
 138 #define EVENT_DOMID_SHIFT       0
 139 #define EVENT_FLAGS_MASK        0xfff
 140 #define EVENT_FLAGS_SHIFT       0x10
 141
 142 /* feature control bits */
 143 #define CONTROL_IOMMU_EN        0x00ULL
 144 #define CONTROL_HT_TUN_EN       0x01ULL
 145 #define CONTROL_EVT_LOG_EN      0x02ULL
 146 #define CONTROL_EVT_INT_EN      0x03ULL
 147 #define CONTROL_COMWAIT_EN      0x04ULL
 148 #define CONTROL_INV_TIMEOUT     0x05ULL
 149 #define CONTROL_PASSPW_EN       0x08ULL
 150 #define CONTROL_RESPASSPW_EN    0x09ULL
 151 #define CONTROL_COHERENT_EN     0x0aULL
 152 #define CONTROL_ISOC_EN         0x0bULL
 153 #define CONTROL_CMDBUF_EN       0x0cULL
 154 #define CONTROL_PPFLOG_EN       0x0dULL
 155 #define CONTROL_PPFINT_EN       0x0eULL
 156 #define CONTROL_PPR_EN          0x0fULL
 157 #define CONTROL_GT_EN           0x10ULL
 158 #define CONTROL_GA_EN           0x11ULL
 159 #define CONTROL_GAM_EN          0x19ULL
 160 #define CONTROL_GALOG_EN        0x1CULL
 161 #define CONTROL_GAINT_EN        0x1DULL
 162
 163 #define CTRL_INV_TO_MASK        (7 << CONTROL_INV_TIMEOUT)
 164 #define CTRL_INV_TO_NONE        0
 165 #define CTRL_INV_TO_1MS         1
 166 #define CTRL_INV_TO_10MS        2
 167 #define CTRL_INV_TO_100MS       3
 168 #define CTRL_INV_TO_1S          4
 169 #define CTRL_INV_TO_10S         5
 170 #define CTRL_INV_TO_100S        6
 171
 172 /* command specific defines */
 173 #define CMD_COMPL_WAIT          0x01
 174 #define CMD_INV_DEV_ENTRY       0x02
 175 #define CMD_INV_IOMMU_PAGES     0x03
 176 #define CMD_INV_IOTLB_PAGES     0x04
 177 #define CMD_INV_IRT             0x05
 178 #define CMD_COMPLETE_PPR        0x07
 179 #define CMD_INV_ALL             0x08
 180
 181 #define CMD_COMPL_WAIT_STORE_MASK       0x01
 182 #define CMD_COMPL_WAIT_INT_MASK         0x02
 183 #define CMD_INV_IOMMU_PAGES_SIZE_MASK   0x01
 184 #define CMD_INV_IOMMU_PAGES_PDE_MASK    0x02
 185 #define CMD_INV_IOMMU_PAGES_GN_MASK     0x04
 186
 187 #define PPR_STATUS_MASK                 0xf
 188 #define PPR_STATUS_SHIFT                12
 189
 190 #define CMD_INV_IOMMU_ALL_PAGES_ADDRESS 0x7fffffffffffffffULL
 191
 192 /* macros and definitions for device table entries */
 193 #define DEV_ENTRY_VALID         0x00
 194 #define DEV_ENTRY_TRANSLATION   0x01
 195 #define DEV_ENTRY_IR            0x3d
 196 #define DEV_ENTRY_IW            0x3e
 197 #define DEV_ENTRY_NO_PAGE_FAULT 0x62
 198 #define DEV_ENTRY_EX            0x67
 199 #define DEV_ENTRY_SYSMGT1       0x68
 200 #define DEV_ENTRY_SYSMGT2       0x69
 201 #define DEV_ENTRY_IRQ_TBL_EN    0x80
 202 #define DEV_ENTRY_INIT_PASS     0xb8
 203 #define DEV_ENTRY_EINT_PASS     0xb9
 204 #define DEV_ENTRY_NMI_PASS      0xba
 205 #define DEV_ENTRY_LINT0_PASS    0xbe
 206 #define DEV_ENTRY_LINT1_PASS    0xbf
 207 #define DEV_ENTRY_MODE_MASK     0x07
 208 #define DEV_ENTRY_MODE_SHIFT    0x09
 209
 210 #define MAX_DEV_TABLE_ENTRIES   0xffff
 211
 212 /* constants to configure the command buffer */
 213 #define CMD_BUFFER_SIZE    8192
 214 #define CMD_BUFFER_UNINITIALIZED 1
 215 #define CMD_BUFFER_ENTRIES 512
 216 #define MMIO_CMD_SIZE_SHIFT 56
 217 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 218
 219 /* constants for event buffer handling */
 220 #define EVT_BUFFER_SIZE         8192 /* 512 entries */
 221 #define EVT_LEN_MASK            (0x9ULL << 56)
 222
 223 /* Constants for PPR Log handling */
 224 #define PPR_LOG_ENTRIES         512
 225 #define PPR_LOG_SIZE_SHIFT      56
 226 #define PPR_LOG_SIZE_512        (0x9ULL << PPR_LOG_SIZE_SHIFT)
 227 #define PPR_ENTRY_SIZE          16
 228 #define PPR_LOG_SIZE            (PPR_ENTRY_SIZE * PPR_LOG_ENTRIES)
 229
 230 #define PPR_REQ_TYPE(x)         (((x) >> 60) & 0xfULL)
 231 #define PPR_FLAGS(x)            (((x) >> 48) & 0xfffULL)
 232 #define PPR_DEVID(x)            ((x) & 0xffffULL)
 233 #define PPR_TAG(x)              (((x) >> 32) & 0x3ffULL)
 234 #define PPR_PASID1(x)           (((x) >> 16) & 0xffffULL)
 235 #define PPR_PASID2(x)           (((x) >> 42) & 0xfULL)
 236 #define PPR_PASID(x)            ((PPR_PASID2(x) << 16) | PPR_PASID1(x))
 237
 238 #define PPR_REQ_FAULT           0x01
 239
 240 /* Constants for GA Log handling */
 241 #define GA_LOG_ENTRIES          512
 242 #define GA_LOG_SIZE_SHIFT       56
 243 #define GA_LOG_SIZE_512         (0x8ULL << GA_LOG_SIZE_SHIFT)
 244 #define GA_ENTRY_SIZE           8
 245 #define GA_LOG_SIZE             (GA_ENTRY_SIZE * GA_LOG_ENTRIES)
 246
 247 #define GA_TAG(x)               (u32)(x & 0xffffffffULL)
 248 #define GA_DEVID(x)             (u16)(((x) >> 32) & 0xffffULL)
 249 #define GA_REQ_TYPE(x)          (((x) >> 60) & 0xfULL)
 250
 251 #define GA_GUEST_NR             0x1
 252
 253 #define PAGE_MODE_NONE    0x00
 254 #define PAGE_MODE_1_LEVEL 0x01
 255 #define PAGE_MODE_2_LEVEL 0x02
 256 #define PAGE_MODE_3_LEVEL 0x03
 257 #define PAGE_MODE_4_LEVEL 0x04
 258 #define PAGE_MODE_5_LEVEL 0x05
 259 #define PAGE_MODE_6_LEVEL 0x06
 260
 261 #define PM_LEVEL_SHIFT(x)       (12 + ((x) * 9))
 262 #define PM_LEVEL_SIZE(x)        (((x) < 6) ? \
 263                                   ((1ULL << PM_LEVEL_SHIFT((x))) - 1): \
 264                                    (0xffffffffffffffffULL))
 265 #define PM_LEVEL_INDEX(x, a)    (((a) >> PM_LEVEL_SHIFT((x))) & 0x1ffULL)
 266 #define PM_LEVEL_ENC(x)         (((x) << 9) & 0xe00ULL)
 267 #define PM_LEVEL_PDE(x, a)      ((a) | PM_LEVEL_ENC((x)) | \
 268                                  IOMMU_PTE_P | IOMMU_PTE_IR | IOMMU_PTE_IW)
 269 #define PM_PTE_LEVEL(pte)       (((pte) >> 9) & 0x7ULL)
 270
 271 #define PM_MAP_4k               0
 272 #define PM_ADDR_MASK            0x000ffffffffff000ULL
 273 #define PM_MAP_MASK(lvl)        (PM_ADDR_MASK & \
 274                                 (~((1ULL << (12 + ((lvl) * 9))) - 1)))
 275 #define PM_ALIGNED(lvl, addr)   ((PM_MAP_MASK(lvl) & (addr)) == (addr))
 276
 277 /*
 278  * Returns the page table level to use for a given page size
 279  * Pagesize is expected to be a power-of-two
 280  */
 281 #define PAGE_SIZE_LEVEL(pagesize) \
 282                 ((__ffs(pagesize) - 12) / 9)
 283 /*
 284  * Returns the number of ptes to use for a given page size
 285  * Pagesize is expected to be a power-of-two
 286  */
 287 #define PAGE_SIZE_PTE_COUNT(pagesize) \
 288                 (1ULL << ((__ffs(pagesize) - 12) % 9))
 289
 290 /*
 291  * Aligns a given io-virtual address to a given page size
 292  * Pagesize is expected to be a power-of-two
 293  */
 294 #define PAGE_SIZE_ALIGN(address, pagesize) \
 295                 ((address) & ~((pagesize) - 1))
 296 /*
 297  * Creates an IOMMU PTE for an address and a given pagesize
 298  * The PTE has no permission bits set
 299  * Pagesize is expected to be a power-of-two larger than 4096
 300  */
 301 #define PAGE_SIZE_PTE(address, pagesize)                \
 302                 (((address) | ((pagesize) - 1)) &       \
 303                  (~(pagesize >> 1)) & PM_ADDR_MASK)
 304
 305 /*
 306  * Takes a PTE value with mode=0x07 and returns the page size it maps
 307  */
 308 #define PTE_PAGE_SIZE(pte) \
 309         (1ULL << (1 + ffz(((pte) | 0xfffULL))))
 310
 311 /*
 312  * Takes a page-table level and returns the default page-size for this level
 313  */
 314 #define PTE_LEVEL_PAGE_SIZE(level)                      \
 315         (1ULL << (12 + (9 * (level))))
 316
 317 #define IOMMU_PTE_P  (1ULL << 0)
 318 #define IOMMU_PTE_TV (1ULL << 1)
 319 #define IOMMU_PTE_U  (1ULL << 59)
 320 #define IOMMU_PTE_FC (1ULL << 60)
 321 #define IOMMU_PTE_IR (1ULL << 61)
 322 #define IOMMU_PTE_IW (1ULL << 62)
 323
 324 #define DTE_FLAG_IOTLB  (1ULL << 32)
 325 #define DTE_FLAG_SA     (1ULL << 34)
 326 #define DTE_FLAG_GV     (1ULL << 55)
 327 #define DTE_FLAG_MASK   (0x3ffULL << 32)
 328 #define DTE_GLX_SHIFT   (56)
 329 #define DTE_GLX_MASK    (3)
 330
 331 #define DTE_GCR3_VAL_A(x)       (((x) >> 12) & 0x00007ULL)
 332 #define DTE_GCR3_VAL_B(x)       (((x) >> 15) & 0x0ffffULL)
 333 #define DTE_GCR3_VAL_C(x)       (((x) >> 31) & 0xfffffULL)
 334
 335 #define DTE_GCR3_INDEX_A        0
 336 #define DTE_GCR3_INDEX_B        1
 337 #define DTE_GCR3_INDEX_C        1
 338
 339 #define DTE_GCR3_SHIFT_A        58
 340 #define DTE_GCR3_SHIFT_B        16
 341 #define DTE_GCR3_SHIFT_C        43
 342
 343 #define GCR3_VALID              0x01ULL
 344
 345 #define IOMMU_PAGE_MASK (((1ULL << 52) - 1) & ~0xfffULL)
 346 #define IOMMU_PTE_PRESENT(pte) ((pte) & IOMMU_PTE_P)
 347 #define IOMMU_PTE_PAGE(pte) (phys_to_virt((pte) & IOMMU_PAGE_MASK))
 348 #define IOMMU_PTE_MODE(pte) (((pte) >> 9) & 0x07)
 349
 350 #define IOMMU_PROT_MASK 0x03
 351 #define IOMMU_PROT_IR 0x01
 352 #define IOMMU_PROT_IW 0x02
 353
 354 /* IOMMU capabilities */
 355 #define IOMMU_CAP_IOTLB   24
 356 #define IOMMU_CAP_NPCACHE 26
 357 #define IOMMU_CAP_EFR     27
 358
 359 /* IOMMU Feature Reporting Field (for IVHD type 10h */
 360 #define IOMMU_FEAT_GASUP_SHIFT  6
 361
 362 /* IOMMU Extended Feature Register (EFR) */
 363 #define IOMMU_EFR_GASUP_SHIFT   7
 364
 365 #define MAX_DOMAIN_ID 65536
 366
 367 /* Protection domain flags */
 368 #define PD_DMA_OPS_MASK         (1UL << 0) /* domain used for dma_ops */
 369 #define PD_DEFAULT_MASK         (1UL << 1) /* domain is a default dma_ops
 370                                               domain for an IOMMU */
 371 #define PD_PASSTHROUGH_MASK     (1UL << 2) /* domain has no page
 372                                               translation */
 373 #define PD_IOMMUV2_MASK         (1UL << 3) /* domain has gcr3 table */
 374
 375 extern bool amd_iommu_dump;
 376 #define DUMP_printk(format, arg...)                                     \
 377         do {                                                            \
 378                 if (amd_iommu_dump)                                             \
 379                         printk(KERN_INFO "AMD-Vi: " format, ## arg);    \
 380         } while(0);
 381
 382 /* global flag if IOMMUs cache non-present entries */
 383 extern bool amd_iommu_np_cache;
 384 /* Only true if all IOMMUs support device IOTLBs */
 385 extern bool amd_iommu_iotlb_sup;
 386
 387 #define MAX_IRQS_PER_TABLE      256
 388 #define IRQ_TABLE_ALIGNMENT     128
 389
 390 struct irq_remap_table {
 391         spinlock_t lock;
 392         unsigned min_index;
 393         u32 *table;
 394 };
 395
 396 extern struct irq_remap_table **irq_lookup_table;
 397
 398 /* Interrupt remapping feature used? */
 399 extern bool amd_iommu_irq_remap;
 400
 401 /* kmem_cache to get tables with 128 byte alignement */
 402 extern struct kmem_cache *amd_iommu_irq_cache;
 403
 404 /*
 405  * Make iterating over all IOMMUs easier
 406  */
 407 #define for_each_iommu(iommu) \
 408         list_for_each_entry((iommu), &amd_iommu_list, list)
 409 #define for_each_iommu_safe(iommu, next) \
 410         list_for_each_entry_safe((iommu), (next), &amd_iommu_list, list)
 411
 412 #define APERTURE_RANGE_SHIFT    27      /* 128 MB */
 413 #define APERTURE_RANGE_SIZE     (1ULL << APERTURE_RANGE_SHIFT)
 414 #define APERTURE_RANGE_PAGES    (APERTURE_RANGE_SIZE >> PAGE_SHIFT)
 415 #define APERTURE_MAX_RANGES     32      /* allows 4GB of DMA address space */
 416 #define APERTURE_RANGE_INDEX(a) ((a) >> APERTURE_RANGE_SHIFT)
 417 #define APERTURE_PAGE_INDEX(a)  (((a) >> 21) & 0x3fULL)
 418
 419
 420 /*
 421  * This struct is used to pass information about
 422  * incoming PPR faults around.
 423  */
 424 struct amd_iommu_fault {
 425         u64 address;    /* IO virtual address of the fault*/
 426         u32 pasid;      /* Address space identifier */
 427         u16 device_id;  /* Originating PCI device id */
 428         u16 tag;        /* PPR tag */
 429         u16 flags;      /* Fault flags */
 430
 431 };
 432
 433
 434 struct iommu_domain;
 435 struct irq_domain;
 436 struct amd_irte_ops;
 437
 438 /*
 439  * This structure contains generic data for  IOMMU protection domains
 440  * independent of their use.
 441  */
 442 struct protection_domain {
 443         struct list_head list;  /* for list of all protection domains */
 444         struct list_head dev_list; /* List of all devices in this domain */
 445         struct iommu_domain domain; /* generic domain handle used by
 446                                        iommu core code */
 447         spinlock_t lock;        /* mostly used to lock the page table*/
 448         struct mutex api_lock;  /* protect page tables in the iommu-api path */
 449         u16 id;                 /* the domain id written to the device table */
 450         int mode;               /* paging mode (0-6 levels) */
 451         u64 *pt_root;           /* page table root pointer */
 452         int glx;                /* Number of levels for GCR3 table */
 453         u64 *gcr3_tbl;          /* Guest CR3 table */
 454         unsigned long flags;    /* flags to find out type of domain */
 455         bool updated;           /* complete domain flush required */
 456         unsigned dev_cnt;       /* devices assigned to this domain */
 457         unsigned dev_iommu[MAX_IOMMUS]; /* per-IOMMU reference count */
 458 };
 459
 460 /*
 461  * Structure where we save information about one hardware AMD IOMMU in the
 462  * system.
 463  */
 464 struct amd_iommu {
 465         struct list_head list;
 466
 467         /* Index within the IOMMU array */
 468         int index;
 469
 470         /* locks the accesses to the hardware */
 471         spinlock_t lock;
 472
 473         /* Pointer to PCI device of this IOMMU */
 474         struct pci_dev *dev;
 475
 476         /* Cache pdev to root device for resume quirks */
 477         struct pci_dev *root_pdev;
 478
 479         /* physical address of MMIO space */
 480         u64 mmio_phys;
 481
 482         /* physical end address of MMIO space */
 483         u64 mmio_phys_end;
 484
 485         /* virtual address of MMIO space */
 486         u8 __iomem *mmio_base;
 487
 488         /* capabilities of that IOMMU read from ACPI */
 489         u32 cap;
 490
 491         /* flags read from acpi table */
 492         u8 acpi_flags;
 493
 494         /* Extended features */
 495         u64 features;
 496
 497         /* IOMMUv2 */
 498         bool is_iommu_v2;
 499
 500         /* PCI device id of the IOMMU device */
 501         u16 devid;
 502
 503         /*
 504          * Capability pointer. There could be more than one IOMMU per PCI
 505          * device function if there are more than one AMD IOMMU capability
 506          * pointers.
 507          */
 508         u16 cap_ptr;
 509
 510         /* pci domain of this IOMMU */
 511         u16 pci_seg;
 512
 513         /* start of exclusion range of that IOMMU */
 514         u64 exclusion_start;
 515         /* length of exclusion range of that IOMMU */
 516         u64 exclusion_length;
 517
 518         /* command buffer virtual address */
 519         u8 *cmd_buf;
 520         u32 cmd_buf_head;
 521         u32 cmd_buf_tail;
 522
 523         /* event buffer virtual address */
 524         u8 *evt_buf;
 525
 526         /* Base of the PPR log, if present */
 527         u8 *ppr_log;
 528
 529         /* Base of the GA log, if present */
 530         u8 *ga_log;
 531
 532         /* Tail of the GA log, if present */
 533         u8 *ga_log_tail;
 534
 535         /* true if interrupts for this IOMMU are already enabled */
 536         bool int_enabled;
 537
 538         /* if one, we need to send a completion wait command */
 539         bool need_sync;
 540
 541         /* Handle for IOMMU core code */
 542         struct iommu_device iommu;
 543
 544         /*
 545          * We can't rely on the BIOS to restore all values on reinit, so we
 546          * need to stash them
 547          */
 548
 549         /* The iommu BAR */
 550         u32 stored_addr_lo;
 551         u32 stored_addr_hi;
 552
 553         /*
 554          * Each iommu has 6 l1s, each of which is documented as having 0x12
 555          * registers
 556          */
 557         u32 stored_l1[6][0x12];
 558
 559         /* The l2 indirect registers */
 560         u32 stored_l2[0x83];
 561
 562         /* The maximum PC banks and counters/bank (PCSup=1) */
 563         u8 max_banks;
 564         u8 max_counters;
 565 #ifdef CONFIG_IRQ_REMAP
 566         struct irq_domain *ir_domain;
 567         struct irq_domain *msi_domain;
 568
 569         struct amd_irte_ops *irte_ops;
 570 #endif
 571
 572         volatile u64 __aligned(8) cmd_sem;
 573 };
 574
 575 static inline struct amd_iommu *dev_to_amd_iommu(struct device *dev)
 576 {
 577         return container_of(dev, struct amd_iommu, iommu.dev);
 578 }
 579
 580 #define ACPIHID_UID_LEN 256
 581 #define ACPIHID_HID_LEN 9
 582
 583 struct acpihid_map_entry {
 584         struct list_head list;
 585         u8 uid[ACPIHID_UID_LEN];
 586         u8 hid[ACPIHID_HID_LEN];
 587         u16 devid;
 588         u16 root_devid;
 589         bool cmd_line;
 590         struct iommu_group *group;
 591 };
 592
 593 struct devid_map {
 594         struct list_head list;
 595         u8 id;
 596         u16 devid;
 597         bool cmd_line;
 598 };
 599
 600 /* Map HPET and IOAPIC ids to the devid used by the IOMMU */
 601 extern struct list_head ioapic_map;
 602 extern struct list_head hpet_map;
 603 extern struct list_head acpihid_map;
 604
 605 /*
 606  * List with all IOMMUs in the system. This list is not locked because it is
 607  * only written and read at driver initialization or suspend time
 608  */
 609 extern struct list_head amd_iommu_list;
 610
 611 /*
 612  * Array with pointers to each IOMMU struct
 613  * The indices are referenced in the protection domains
 614  */
 615 extern struct amd_iommu *amd_iommus[MAX_IOMMUS];
 616
 617 /*
 618  * Declarations for the global list of all protection domains
 619  */
 620 extern spinlock_t amd_iommu_pd_lock;
 621 extern struct list_head amd_iommu_pd_list;
 622
 623 /*
 624  * Structure defining one entry in the device table
 625  */
 626 struct dev_table_entry {
 627         u64 data[4];
 628 };
 629
 630 /*
 631  * One entry for unity mappings parsed out of the ACPI table.
 632  */
 633 struct unity_map_entry {
 634         struct list_head list;
 635
 636         /* starting device id this entry is used for (including) */
 637         u16 devid_start;
 638         /* end device id this entry is used for (including) */
 639         u16 devid_end;
 640
 641         /* start address to unity map (including) */
 642         u64 address_start;
 643         /* end address to unity map (including) */
 644         u64 address_end;
 645
 646         /* required protection */
 647         int prot;
 648 };
 649
 650 /*
 651  * List of all unity mappings. It is not locked because as runtime it is only
 652  * read. It is created at ACPI table parsing time.
 653  */
 654 extern struct list_head amd_iommu_unity_map;
 655
 656 /*
 657  * Data structures for device handling
 658  */
 659
 660 /*
 661  * Device table used by hardware. Read and write accesses by software are
 662  * locked with the amd_iommu_pd_table lock.
 663  */
 664 extern struct dev_table_entry *amd_iommu_dev_table;
 665
 666 /*
 667  * Alias table to find requestor ids to device ids. Not locked because only
 668  * read on runtime.
 669  */
 670 extern u16 *amd_iommu_alias_table;
 671
 672 /*
 673  * Reverse lookup table to find the IOMMU which translates a specific device.
 674  */
 675 extern struct amd_iommu **amd_iommu_rlookup_table;
 676
 677 /* size of the dma_ops aperture as power of 2 */
 678 extern unsigned amd_iommu_aperture_order;
 679
 680 /* largest PCI device id we expect translation requests for */
 681 extern u16 amd_iommu_last_bdf;
 682
 683 /* allocation bitmap for domain ids */
 684 extern unsigned long *amd_iommu_pd_alloc_bitmap;
 685
 686 /*
 687  * If true, the addresses will be flushed on unmap time, not when
 688  * they are reused
 689  */
 690 extern bool amd_iommu_unmap_flush;
 691
 692 /* Smallest max PASID supported by any IOMMU in the system */
 693 extern u32 amd_iommu_max_pasid;
 694
 695 extern bool amd_iommu_v2_present;
 696
 697 extern bool amd_iommu_force_isolation;
 698
 699 /* Max levels of glxval supported */
 700 extern int amd_iommu_max_glx_val;
 701
 702 /*
 703  * This function flushes all internal caches of
 704  * the IOMMU used by this driver.
 705  */
 706 extern void iommu_flush_all_caches(struct amd_iommu *iommu);
 707
 708 static inline int get_ioapic_devid(int id)
 709 {
 710         struct devid_map *entry;
 711
 712         list_for_each_entry(entry, &ioapic_map, list) {
 713                 if (entry->id == id)
 714                         return entry->devid;
 715         }
 716
 717         return -EINVAL;
 718 }
 719
 720 static inline int get_hpet_devid(int id)
 721 {
 722         struct devid_map *entry;
 723
 724         list_for_each_entry(entry, &hpet_map, list) {
 725                 if (entry->id == id)
 726                         return entry->devid;
 727         }
 728
 729         return -EINVAL;
 730 }
 731
 732 enum amd_iommu_intr_mode_type {
 733         AMD_IOMMU_GUEST_IR_LEGACY,
 734
 735         /* This mode is not visible to users. It is used when
 736          * we cannot fully enable vAPIC and fallback to only support
 737          * legacy interrupt remapping via 128-bit IRTE.
 738          */
 739         AMD_IOMMU_GUEST_IR_LEGACY_GA,
 740         AMD_IOMMU_GUEST_IR_VAPIC,
 741 };
 742
 743 #define AMD_IOMMU_GUEST_IR_GA(x)        (x == AMD_IOMMU_GUEST_IR_VAPIC || \
 744                                          x == AMD_IOMMU_GUEST_IR_LEGACY_GA)
 745
 746 #define AMD_IOMMU_GUEST_IR_VAPIC(x)     (x == AMD_IOMMU_GUEST_IR_VAPIC)
 747
 748 union irte {
 749         u32 val;
 750         struct {
 751                 u32 valid       : 1,
 752                     no_fault    : 1,
 753                     int_type    : 3,
 754                     rq_eoi      : 1,
 755                     dm          : 1,
 756                     rsvd_1      : 1,
 757                     destination : 8,
 758                     vector      : 8,
 759                     rsvd_2      : 8;
 760         } fields;
 761 };
 762
 763 union irte_ga_lo {
 764         u64 val;
 765
 766         /* For int remapping */
 767         struct {
 768                 u64 valid       : 1,
 769                     no_fault    : 1,
 770                     /* ------ */
 771                     int_type    : 3,
 772                     rq_eoi      : 1,
 773                     dm          : 1,
 774                     /* ------ */
 775                     guest_mode  : 1,
 776                     destination : 8,
 777                     rsvd        : 48;
 778         } fields_remap;
 779
 780         /* For guest vAPIC */
 781         struct {
 782                 u64 valid       : 1,
 783                     no_fault    : 1,
 784                     /* ------ */
 785                     ga_log_intr : 1,
 786                     rsvd1       : 3,
 787                     is_run      : 1,
 788                     /* ------ */
 789                     guest_mode  : 1,
 790                     destination : 8,
 791                     rsvd2       : 16,
 792                     ga_tag      : 32;
 793         } fields_vapic;
 794 };
 795
 796 union irte_ga_hi {
 797         u64 val;
 798         struct {
 799                 u64 vector      : 8,
 800                     rsvd_1      : 4,
 801                     ga_root_ptr : 40,
 802                     rsvd_2      : 12;
 803         } fields;
 804 };
 805
 806 struct irte_ga {
 807         union irte_ga_lo lo;
 808         union irte_ga_hi hi;
 809 };
 810
 811 struct irq_2_irte {
 812         u16 devid; /* Device ID for IRTE table */
 813         u16 index; /* Index into IRTE table*/
 814 };
 815
 816 struct amd_ir_data {
 817         u32 cached_ga_tag;
 818         struct irq_2_irte irq_2_irte;
 819         struct msi_msg msi_entry;
 820         void *entry;    /* Pointer to union irte or struct irte_ga */
 821         void *ref;      /* Pointer to the actual irte */
 822 };
 823
 824 struct amd_irte_ops {
 825         void (*prepare)(void *, u32, u32, u8, u32, int);
 826         void (*activate)(void *, u16, u16);
 827         void (*deactivate)(void *, u16, u16);
 828         void (*set_affinity)(void *, u16, u16, u8, u32);
 829         void *(*get)(struct irq_remap_table *, int);
 830         void (*set_allocated)(struct irq_remap_table *, int);
 831         bool (*is_allocated)(struct irq_remap_table *, int);
 832         void (*clear_allocated)(struct irq_remap_table *, int);
 833 };
 834
 835 #ifdef CONFIG_IRQ_REMAP
 836 extern struct amd_irte_ops irte_32_ops;
 837 extern struct amd_irte_ops irte_128_ops;
 838 #endif
 839
 840 #endif /* _ASM_X86_AMD_IOMMU_TYPES_H */