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[mirror_ubuntu-jammy-kernel.git] / drivers / iommu / arm-smmu.c
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 42-bit addressing (dependent on VA_BITS)
28 * - Context fault reporting
29 */
30
31 #define pr_fmt(fmt) "arm-smmu: " fmt
32
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iommu.h>
39 #include <linux/mm.h>
40 #include <linux/module.h>
41 #include <linux/of.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45
46 #include <linux/amba/bus.h>
47
48 #include <asm/pgalloc.h>
49
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS 8
52
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
55
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
58
59 /* SMMU global address space */
60 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
61 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
62
63 /* Page table bits */
64 #define ARM_SMMU_PTE_XN (((pteval_t)3) << 53)
65 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
66 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
67 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
68 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
69 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
70 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
71
72 #if PAGE_SIZE == SZ_4K
73 #define ARM_SMMU_PTE_CONT_ENTRIES 16
74 #elif PAGE_SIZE == SZ_64K
75 #define ARM_SMMU_PTE_CONT_ENTRIES 32
76 #else
77 #define ARM_SMMU_PTE_CONT_ENTRIES 1
78 #endif
79
80 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
81 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
82
83 /* Stage-1 PTE */
84 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
85 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
86 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
87 #define ARM_SMMU_PTE_nG (((pteval_t)1) << 11)
88
89 /* Stage-2 PTE */
90 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
91 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
92 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
93 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
94 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
95 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
96
97 /* Configuration registers */
98 #define ARM_SMMU_GR0_sCR0 0x0
99 #define sCR0_CLIENTPD (1 << 0)
100 #define sCR0_GFRE (1 << 1)
101 #define sCR0_GFIE (1 << 2)
102 #define sCR0_GCFGFRE (1 << 4)
103 #define sCR0_GCFGFIE (1 << 5)
104 #define sCR0_USFCFG (1 << 10)
105 #define sCR0_VMIDPNE (1 << 11)
106 #define sCR0_PTM (1 << 12)
107 #define sCR0_FB (1 << 13)
108 #define sCR0_BSU_SHIFT 14
109 #define sCR0_BSU_MASK 0x3
110
111 /* Identification registers */
112 #define ARM_SMMU_GR0_ID0 0x20
113 #define ARM_SMMU_GR0_ID1 0x24
114 #define ARM_SMMU_GR0_ID2 0x28
115 #define ARM_SMMU_GR0_ID3 0x2c
116 #define ARM_SMMU_GR0_ID4 0x30
117 #define ARM_SMMU_GR0_ID5 0x34
118 #define ARM_SMMU_GR0_ID6 0x38
119 #define ARM_SMMU_GR0_ID7 0x3c
120 #define ARM_SMMU_GR0_sGFSR 0x48
121 #define ARM_SMMU_GR0_sGFSYNR0 0x50
122 #define ARM_SMMU_GR0_sGFSYNR1 0x54
123 #define ARM_SMMU_GR0_sGFSYNR2 0x58
124 #define ARM_SMMU_GR0_PIDR0 0xfe0
125 #define ARM_SMMU_GR0_PIDR1 0xfe4
126 #define ARM_SMMU_GR0_PIDR2 0xfe8
127
128 #define ID0_S1TS (1 << 30)
129 #define ID0_S2TS (1 << 29)
130 #define ID0_NTS (1 << 28)
131 #define ID0_SMS (1 << 27)
132 #define ID0_PTFS_SHIFT 24
133 #define ID0_PTFS_MASK 0x2
134 #define ID0_PTFS_V8_ONLY 0x2
135 #define ID0_CTTW (1 << 14)
136 #define ID0_NUMIRPT_SHIFT 16
137 #define ID0_NUMIRPT_MASK 0xff
138 #define ID0_NUMSMRG_SHIFT 0
139 #define ID0_NUMSMRG_MASK 0xff
140
141 #define ID1_PAGESIZE (1 << 31)
142 #define ID1_NUMPAGENDXB_SHIFT 28
143 #define ID1_NUMPAGENDXB_MASK 7
144 #define ID1_NUMS2CB_SHIFT 16
145 #define ID1_NUMS2CB_MASK 0xff
146 #define ID1_NUMCB_SHIFT 0
147 #define ID1_NUMCB_MASK 0xff
148
149 #define ID2_OAS_SHIFT 4
150 #define ID2_OAS_MASK 0xf
151 #define ID2_IAS_SHIFT 0
152 #define ID2_IAS_MASK 0xf
153 #define ID2_UBS_SHIFT 8
154 #define ID2_UBS_MASK 0xf
155 #define ID2_PTFS_4K (1 << 12)
156 #define ID2_PTFS_16K (1 << 13)
157 #define ID2_PTFS_64K (1 << 14)
158
159 #define PIDR2_ARCH_SHIFT 4
160 #define PIDR2_ARCH_MASK 0xf
161
162 /* Global TLB invalidation */
163 #define ARM_SMMU_GR0_STLBIALL 0x60
164 #define ARM_SMMU_GR0_TLBIVMID 0x64
165 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
166 #define ARM_SMMU_GR0_TLBIALLH 0x6c
167 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
168 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
169 #define sTLBGSTATUS_GSACTIVE (1 << 0)
170 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
171
172 /* Stream mapping registers */
173 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
174 #define SMR_VALID (1 << 31)
175 #define SMR_MASK_SHIFT 16
176 #define SMR_MASK_MASK 0x7fff
177 #define SMR_ID_SHIFT 0
178 #define SMR_ID_MASK 0x7fff
179
180 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
181 #define S2CR_CBNDX_SHIFT 0
182 #define S2CR_CBNDX_MASK 0xff
183 #define S2CR_TYPE_SHIFT 16
184 #define S2CR_TYPE_MASK 0x3
185 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
186 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
187 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
188
189 /* Context bank attribute registers */
190 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
191 #define CBAR_VMID_SHIFT 0
192 #define CBAR_VMID_MASK 0xff
193 #define CBAR_S1_BPSHCFG_SHIFT 8
194 #define CBAR_S1_BPSHCFG_MASK 3
195 #define CBAR_S1_BPSHCFG_NSH 3
196 #define CBAR_S1_MEMATTR_SHIFT 12
197 #define CBAR_S1_MEMATTR_MASK 0xf
198 #define CBAR_S1_MEMATTR_WB 0xf
199 #define CBAR_TYPE_SHIFT 16
200 #define CBAR_TYPE_MASK 0x3
201 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
202 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
203 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
204 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
205 #define CBAR_IRPTNDX_SHIFT 24
206 #define CBAR_IRPTNDX_MASK 0xff
207
208 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
209 #define CBA2R_RW64_32BIT (0 << 0)
210 #define CBA2R_RW64_64BIT (1 << 0)
211
212 /* Translation context bank */
213 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
214 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
215
216 #define ARM_SMMU_CB_SCTLR 0x0
217 #define ARM_SMMU_CB_RESUME 0x8
218 #define ARM_SMMU_CB_TTBCR2 0x10
219 #define ARM_SMMU_CB_TTBR0_LO 0x20
220 #define ARM_SMMU_CB_TTBR0_HI 0x24
221 #define ARM_SMMU_CB_TTBCR 0x30
222 #define ARM_SMMU_CB_S1_MAIR0 0x38
223 #define ARM_SMMU_CB_FSR 0x58
224 #define ARM_SMMU_CB_FAR_LO 0x60
225 #define ARM_SMMU_CB_FAR_HI 0x64
226 #define ARM_SMMU_CB_FSYNR0 0x68
227 #define ARM_SMMU_CB_S1_TLBIASID 0x610
228
229 #define SCTLR_S1_ASIDPNE (1 << 12)
230 #define SCTLR_CFCFG (1 << 7)
231 #define SCTLR_CFIE (1 << 6)
232 #define SCTLR_CFRE (1 << 5)
233 #define SCTLR_E (1 << 4)
234 #define SCTLR_AFE (1 << 2)
235 #define SCTLR_TRE (1 << 1)
236 #define SCTLR_M (1 << 0)
237 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
238
239 #define RESUME_RETRY (0 << 0)
240 #define RESUME_TERMINATE (1 << 0)
241
242 #define TTBCR_EAE (1 << 31)
243
244 #define TTBCR_PASIZE_SHIFT 16
245 #define TTBCR_PASIZE_MASK 0x7
246
247 #define TTBCR_TG0_4K (0 << 14)
248 #define TTBCR_TG0_64K (1 << 14)
249
250 #define TTBCR_SH0_SHIFT 12
251 #define TTBCR_SH0_MASK 0x3
252 #define TTBCR_SH_NS 0
253 #define TTBCR_SH_OS 2
254 #define TTBCR_SH_IS 3
255
256 #define TTBCR_ORGN0_SHIFT 10
257 #define TTBCR_IRGN0_SHIFT 8
258 #define TTBCR_RGN_MASK 0x3
259 #define TTBCR_RGN_NC 0
260 #define TTBCR_RGN_WBWA 1
261 #define TTBCR_RGN_WT 2
262 #define TTBCR_RGN_WB 3
263
264 #define TTBCR_SL0_SHIFT 6
265 #define TTBCR_SL0_MASK 0x3
266 #define TTBCR_SL0_LVL_2 0
267 #define TTBCR_SL0_LVL_1 1
268
269 #define TTBCR_T1SZ_SHIFT 16
270 #define TTBCR_T0SZ_SHIFT 0
271 #define TTBCR_SZ_MASK 0xf
272
273 #define TTBCR2_SEP_SHIFT 15
274 #define TTBCR2_SEP_MASK 0x7
275
276 #define TTBCR2_PASIZE_SHIFT 0
277 #define TTBCR2_PASIZE_MASK 0x7
278
279 /* Common definitions for PASize and SEP fields */
280 #define TTBCR2_ADDR_32 0
281 #define TTBCR2_ADDR_36 1
282 #define TTBCR2_ADDR_40 2
283 #define TTBCR2_ADDR_42 3
284 #define TTBCR2_ADDR_44 4
285 #define TTBCR2_ADDR_48 5
286
287 #define TTBRn_HI_ASID_SHIFT 16
288
289 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
290 #define MAIR_ATTR_MASK 0xff
291 #define MAIR_ATTR_DEVICE 0x04
292 #define MAIR_ATTR_NC 0x44
293 #define MAIR_ATTR_WBRWA 0xff
294 #define MAIR_ATTR_IDX_NC 0
295 #define MAIR_ATTR_IDX_CACHE 1
296 #define MAIR_ATTR_IDX_DEV 2
297
298 #define FSR_MULTI (1 << 31)
299 #define FSR_SS (1 << 30)
300 #define FSR_UUT (1 << 8)
301 #define FSR_ASF (1 << 7)
302 #define FSR_TLBLKF (1 << 6)
303 #define FSR_TLBMCF (1 << 5)
304 #define FSR_EF (1 << 4)
305 #define FSR_PF (1 << 3)
306 #define FSR_AFF (1 << 2)
307 #define FSR_TF (1 << 1)
308
309 #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \
310 FSR_TLBLKF)
311 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
312 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
313
314 #define FSYNR0_WNR (1 << 4)
315
316 struct arm_smmu_smr {
317 u8 idx;
318 u16 mask;
319 u16 id;
320 };
321
322 struct arm_smmu_master {
323 struct device_node *of_node;
324
325 /*
326 * The following is specific to the master's position in the
327 * SMMU chain.
328 */
329 struct rb_node node;
330 int num_streamids;
331 u16 streamids[MAX_MASTER_STREAMIDS];
332
333 /*
334 * We only need to allocate these on the root SMMU, as we
335 * configure unmatched streams to bypass translation.
336 */
337 struct arm_smmu_smr *smrs;
338 };
339
340 struct arm_smmu_device {
341 struct device *dev;
342 struct device_node *parent_of_node;
343
344 void __iomem *base;
345 unsigned long size;
346 unsigned long pagesize;
347
348 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
349 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
350 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
351 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
352 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
353 u32 features;
354 int version;
355
356 u32 num_context_banks;
357 u32 num_s2_context_banks;
358 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
359 atomic_t irptndx;
360
361 u32 num_mapping_groups;
362 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
363
364 unsigned long input_size;
365 unsigned long s1_output_size;
366 unsigned long s2_output_size;
367
368 u32 num_global_irqs;
369 u32 num_context_irqs;
370 unsigned int *irqs;
371
372 struct list_head list;
373 struct rb_root masters;
374 };
375
376 struct arm_smmu_cfg {
377 struct arm_smmu_device *smmu;
378 u8 cbndx;
379 u8 irptndx;
380 u32 cbar;
381 pgd_t *pgd;
382 };
383 #define INVALID_IRPTNDX 0xff
384
385 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
386 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
387
388 struct arm_smmu_domain {
389 /*
390 * A domain can span across multiple, chained SMMUs and requires
391 * all devices within the domain to follow the same translation
392 * path.
393 */
394 struct arm_smmu_device *leaf_smmu;
395 struct arm_smmu_cfg root_cfg;
396 phys_addr_t output_mask;
397
398 spinlock_t lock;
399 };
400
401 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
402 static LIST_HEAD(arm_smmu_devices);
403
404 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
405 struct device_node *dev_node)
406 {
407 struct rb_node *node = smmu->masters.rb_node;
408
409 while (node) {
410 struct arm_smmu_master *master;
411 master = container_of(node, struct arm_smmu_master, node);
412
413 if (dev_node < master->of_node)
414 node = node->rb_left;
415 else if (dev_node > master->of_node)
416 node = node->rb_right;
417 else
418 return master;
419 }
420
421 return NULL;
422 }
423
424 static int insert_smmu_master(struct arm_smmu_device *smmu,
425 struct arm_smmu_master *master)
426 {
427 struct rb_node **new, *parent;
428
429 new = &smmu->masters.rb_node;
430 parent = NULL;
431 while (*new) {
432 struct arm_smmu_master *this;
433 this = container_of(*new, struct arm_smmu_master, node);
434
435 parent = *new;
436 if (master->of_node < this->of_node)
437 new = &((*new)->rb_left);
438 else if (master->of_node > this->of_node)
439 new = &((*new)->rb_right);
440 else
441 return -EEXIST;
442 }
443
444 rb_link_node(&master->node, parent, new);
445 rb_insert_color(&master->node, &smmu->masters);
446 return 0;
447 }
448
449 static int register_smmu_master(struct arm_smmu_device *smmu,
450 struct device *dev,
451 struct of_phandle_args *masterspec)
452 {
453 int i;
454 struct arm_smmu_master *master;
455
456 master = find_smmu_master(smmu, masterspec->np);
457 if (master) {
458 dev_err(dev,
459 "rejecting multiple registrations for master device %s\n",
460 masterspec->np->name);
461 return -EBUSY;
462 }
463
464 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
465 dev_err(dev,
466 "reached maximum number (%d) of stream IDs for master device %s\n",
467 MAX_MASTER_STREAMIDS, masterspec->np->name);
468 return -ENOSPC;
469 }
470
471 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
472 if (!master)
473 return -ENOMEM;
474
475 master->of_node = masterspec->np;
476 master->num_streamids = masterspec->args_count;
477
478 for (i = 0; i < master->num_streamids; ++i)
479 master->streamids[i] = masterspec->args[i];
480
481 return insert_smmu_master(smmu, master);
482 }
483
484 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
485 {
486 struct arm_smmu_device *parent;
487
488 if (!smmu->parent_of_node)
489 return NULL;
490
491 spin_lock(&arm_smmu_devices_lock);
492 list_for_each_entry(parent, &arm_smmu_devices, list)
493 if (parent->dev->of_node == smmu->parent_of_node)
494 goto out_unlock;
495
496 parent = NULL;
497 dev_warn(smmu->dev,
498 "Failed to find SMMU parent despite parent in DT\n");
499 out_unlock:
500 spin_unlock(&arm_smmu_devices_lock);
501 return parent;
502 }
503
504 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
505 {
506 int idx;
507
508 do {
509 idx = find_next_zero_bit(map, end, start);
510 if (idx == end)
511 return -ENOSPC;
512 } while (test_and_set_bit(idx, map));
513
514 return idx;
515 }
516
517 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
518 {
519 clear_bit(idx, map);
520 }
521
522 /* Wait for any pending TLB invalidations to complete */
523 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
524 {
525 int count = 0;
526 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
527
528 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
529 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
530 & sTLBGSTATUS_GSACTIVE) {
531 cpu_relax();
532 if (++count == TLB_LOOP_TIMEOUT) {
533 dev_err_ratelimited(smmu->dev,
534 "TLB sync timed out -- SMMU may be deadlocked\n");
535 return;
536 }
537 udelay(1);
538 }
539 }
540
541 static void arm_smmu_tlb_inv_context(struct arm_smmu_cfg *cfg)
542 {
543 struct arm_smmu_device *smmu = cfg->smmu;
544 void __iomem *base = ARM_SMMU_GR0(smmu);
545 bool stage1 = cfg->cbar != CBAR_TYPE_S2_TRANS;
546
547 if (stage1) {
548 base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, cfg->cbndx);
549 writel_relaxed(ARM_SMMU_CB_ASID(cfg),
550 base + ARM_SMMU_CB_S1_TLBIASID);
551 } else {
552 base = ARM_SMMU_GR0(smmu);
553 writel_relaxed(ARM_SMMU_CB_VMID(cfg),
554 base + ARM_SMMU_GR0_TLBIVMID);
555 }
556
557 arm_smmu_tlb_sync(smmu);
558 }
559
560 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
561 {
562 int flags, ret;
563 u32 fsr, far, fsynr, resume;
564 unsigned long iova;
565 struct iommu_domain *domain = dev;
566 struct arm_smmu_domain *smmu_domain = domain->priv;
567 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
568 struct arm_smmu_device *smmu = root_cfg->smmu;
569 void __iomem *cb_base;
570
571 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
572 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
573
574 if (!(fsr & FSR_FAULT))
575 return IRQ_NONE;
576
577 if (fsr & FSR_IGN)
578 dev_err_ratelimited(smmu->dev,
579 "Unexpected context fault (fsr 0x%u)\n",
580 fsr);
581
582 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
583 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
584
585 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
586 iova = far;
587 #ifdef CONFIG_64BIT
588 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
589 iova |= ((unsigned long)far << 32);
590 #endif
591
592 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
593 ret = IRQ_HANDLED;
594 resume = RESUME_RETRY;
595 } else {
596 dev_err_ratelimited(smmu->dev,
597 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
598 iova, fsynr, root_cfg->cbndx);
599 ret = IRQ_NONE;
600 resume = RESUME_TERMINATE;
601 }
602
603 /* Clear the faulting FSR */
604 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
605
606 /* Retry or terminate any stalled transactions */
607 if (fsr & FSR_SS)
608 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
609
610 return ret;
611 }
612
613 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
614 {
615 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
616 struct arm_smmu_device *smmu = dev;
617 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
618
619 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
620 if (!gfsr)
621 return IRQ_NONE;
622
623 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
624 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
625 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
626
627 dev_err_ratelimited(smmu->dev,
628 "Unexpected global fault, this could be serious\n");
629 dev_err_ratelimited(smmu->dev,
630 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
631 gfsr, gfsynr0, gfsynr1, gfsynr2);
632
633 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
634 return IRQ_HANDLED;
635 }
636
637 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
638 size_t size)
639 {
640 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
641
642
643 /* Ensure new page tables are visible to the hardware walker */
644 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) {
645 dsb();
646 } else {
647 /*
648 * If the SMMU can't walk tables in the CPU caches, treat them
649 * like non-coherent DMA since we need to flush the new entries
650 * all the way out to memory. There's no possibility of
651 * recursion here as the SMMU table walker will not be wired
652 * through another SMMU.
653 */
654 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
655 DMA_TO_DEVICE);
656 }
657 }
658
659 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
660 {
661 u32 reg;
662 bool stage1;
663 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
664 struct arm_smmu_device *smmu = root_cfg->smmu;
665 void __iomem *cb_base, *gr0_base, *gr1_base;
666
667 gr0_base = ARM_SMMU_GR0(smmu);
668 gr1_base = ARM_SMMU_GR1(smmu);
669 stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
670 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
671
672 /* CBAR */
673 reg = root_cfg->cbar;
674 if (smmu->version == 1)
675 reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
676
677 /*
678 * Use the weakest shareability/memory types, so they are
679 * overridden by the ttbcr/pte.
680 */
681 if (stage1) {
682 reg |= (CBAR_S1_BPSHCFG_NSH << CBAR_S1_BPSHCFG_SHIFT) |
683 (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
684 } else {
685 reg |= ARM_SMMU_CB_VMID(root_cfg) << CBAR_VMID_SHIFT;
686 }
687 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
688
689 if (smmu->version > 1) {
690 /* CBA2R */
691 #ifdef CONFIG_64BIT
692 reg = CBA2R_RW64_64BIT;
693 #else
694 reg = CBA2R_RW64_32BIT;
695 #endif
696 writel_relaxed(reg,
697 gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
698
699 /* TTBCR2 */
700 switch (smmu->input_size) {
701 case 32:
702 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
703 break;
704 case 36:
705 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
706 break;
707 case 39:
708 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
709 break;
710 case 42:
711 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
712 break;
713 case 44:
714 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
715 break;
716 case 48:
717 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
718 break;
719 }
720
721 switch (smmu->s1_output_size) {
722 case 32:
723 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
724 break;
725 case 36:
726 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
727 break;
728 case 39:
729 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
730 break;
731 case 42:
732 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
733 break;
734 case 44:
735 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
736 break;
737 case 48:
738 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
739 break;
740 }
741
742 if (stage1)
743 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
744 }
745
746 /* TTBR0 */
747 arm_smmu_flush_pgtable(smmu, root_cfg->pgd,
748 PTRS_PER_PGD * sizeof(pgd_t));
749 reg = __pa(root_cfg->pgd);
750 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
751 reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
752 if (stage1)
753 reg |= ARM_SMMU_CB_ASID(root_cfg) << TTBRn_HI_ASID_SHIFT;
754 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
755
756 /*
757 * TTBCR
758 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
759 */
760 if (smmu->version > 1) {
761 if (PAGE_SIZE == SZ_4K)
762 reg = TTBCR_TG0_4K;
763 else
764 reg = TTBCR_TG0_64K;
765
766 if (!stage1) {
767 switch (smmu->s2_output_size) {
768 case 32:
769 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
770 break;
771 case 36:
772 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
773 break;
774 case 40:
775 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
776 break;
777 case 42:
778 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
779 break;
780 case 44:
781 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
782 break;
783 case 48:
784 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
785 break;
786 }
787 } else {
788 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
789 }
790 } else {
791 reg = 0;
792 }
793
794 reg |= TTBCR_EAE |
795 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
796 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
797 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
798 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
799 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
800
801 /* MAIR0 (stage-1 only) */
802 if (stage1) {
803 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
804 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
805 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
806 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
807 }
808
809 /* SCTLR */
810 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
811 if (stage1)
812 reg |= SCTLR_S1_ASIDPNE;
813 #ifdef __BIG_ENDIAN
814 reg |= SCTLR_E;
815 #endif
816 writel_relaxed(reg, cb_base + ARM_SMMU_CB_SCTLR);
817 }
818
819 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
820 struct device *dev)
821 {
822 int irq, ret, start;
823 struct arm_smmu_domain *smmu_domain = domain->priv;
824 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
825 struct arm_smmu_device *smmu, *parent;
826
827 /*
828 * Walk the SMMU chain to find the root device for this chain.
829 * We assume that no masters have translations which terminate
830 * early, and therefore check that the root SMMU does indeed have
831 * a StreamID for the master in question.
832 */
833 parent = dev->archdata.iommu;
834 smmu_domain->output_mask = -1;
835 do {
836 smmu = parent;
837 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
838 } while ((parent = find_parent_smmu(smmu)));
839
840 if (!find_smmu_master(smmu, dev->of_node)) {
841 dev_err(dev, "unable to find root SMMU for device\n");
842 return -ENODEV;
843 }
844
845 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
846 /*
847 * We will likely want to change this if/when KVM gets
848 * involved.
849 */
850 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
851 start = smmu->num_s2_context_banks;
852 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
853 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
854 start = 0;
855 } else {
856 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
857 start = smmu->num_s2_context_banks;
858 }
859
860 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
861 smmu->num_context_banks);
862 if (IS_ERR_VALUE(ret))
863 return ret;
864
865 root_cfg->cbndx = ret;
866 if (smmu->version == 1) {
867 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
868 root_cfg->irptndx %= smmu->num_context_irqs;
869 } else {
870 root_cfg->irptndx = root_cfg->cbndx;
871 }
872
873 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
874 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
875 "arm-smmu-context-fault", domain);
876 if (IS_ERR_VALUE(ret)) {
877 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
878 root_cfg->irptndx, irq);
879 root_cfg->irptndx = INVALID_IRPTNDX;
880 goto out_free_context;
881 }
882
883 root_cfg->smmu = smmu;
884 arm_smmu_init_context_bank(smmu_domain);
885 return ret;
886
887 out_free_context:
888 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
889 return ret;
890 }
891
892 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
893 {
894 struct arm_smmu_domain *smmu_domain = domain->priv;
895 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
896 struct arm_smmu_device *smmu = root_cfg->smmu;
897 void __iomem *cb_base;
898 int irq;
899
900 if (!smmu)
901 return;
902
903 /* Disable the context bank and nuke the TLB before freeing it. */
904 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
905 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
906 arm_smmu_tlb_inv_context(root_cfg);
907
908 if (root_cfg->irptndx != INVALID_IRPTNDX) {
909 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
910 free_irq(irq, domain);
911 }
912
913 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
914 }
915
916 static int arm_smmu_domain_init(struct iommu_domain *domain)
917 {
918 struct arm_smmu_domain *smmu_domain;
919 pgd_t *pgd;
920
921 /*
922 * Allocate the domain and initialise some of its data structures.
923 * We can't really do anything meaningful until we've added a
924 * master.
925 */
926 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
927 if (!smmu_domain)
928 return -ENOMEM;
929
930 pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
931 if (!pgd)
932 goto out_free_domain;
933 smmu_domain->root_cfg.pgd = pgd;
934
935 spin_lock_init(&smmu_domain->lock);
936 domain->priv = smmu_domain;
937 return 0;
938
939 out_free_domain:
940 kfree(smmu_domain);
941 return -ENOMEM;
942 }
943
944 static void arm_smmu_free_ptes(pmd_t *pmd)
945 {
946 pgtable_t table = pmd_pgtable(*pmd);
947 pgtable_page_dtor(table);
948 __free_page(table);
949 }
950
951 static void arm_smmu_free_pmds(pud_t *pud)
952 {
953 int i;
954 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
955
956 pmd = pmd_base;
957 for (i = 0; i < PTRS_PER_PMD; ++i) {
958 if (pmd_none(*pmd))
959 continue;
960
961 arm_smmu_free_ptes(pmd);
962 pmd++;
963 }
964
965 pmd_free(NULL, pmd_base);
966 }
967
968 static void arm_smmu_free_puds(pgd_t *pgd)
969 {
970 int i;
971 pud_t *pud, *pud_base = pud_offset(pgd, 0);
972
973 pud = pud_base;
974 for (i = 0; i < PTRS_PER_PUD; ++i) {
975 if (pud_none(*pud))
976 continue;
977
978 arm_smmu_free_pmds(pud);
979 pud++;
980 }
981
982 pud_free(NULL, pud_base);
983 }
984
985 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
986 {
987 int i;
988 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
989 pgd_t *pgd, *pgd_base = root_cfg->pgd;
990
991 /*
992 * Recursively free the page tables for this domain. We don't
993 * care about speculative TLB filling, because the TLB will be
994 * nuked next time this context bank is re-allocated and no devices
995 * currently map to these tables.
996 */
997 pgd = pgd_base;
998 for (i = 0; i < PTRS_PER_PGD; ++i) {
999 if (pgd_none(*pgd))
1000 continue;
1001 arm_smmu_free_puds(pgd);
1002 pgd++;
1003 }
1004
1005 kfree(pgd_base);
1006 }
1007
1008 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
1009 {
1010 struct arm_smmu_domain *smmu_domain = domain->priv;
1011
1012 /*
1013 * Free the domain resources. We assume that all devices have
1014 * already been detached.
1015 */
1016 arm_smmu_destroy_domain_context(domain);
1017 arm_smmu_free_pgtables(smmu_domain);
1018 kfree(smmu_domain);
1019 }
1020
1021 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
1022 struct arm_smmu_master *master)
1023 {
1024 int i;
1025 struct arm_smmu_smr *smrs;
1026 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1027
1028 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
1029 return 0;
1030
1031 if (master->smrs)
1032 return -EEXIST;
1033
1034 smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
1035 if (!smrs) {
1036 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
1037 master->num_streamids, master->of_node->name);
1038 return -ENOMEM;
1039 }
1040
1041 /* Allocate the SMRs on the root SMMU */
1042 for (i = 0; i < master->num_streamids; ++i) {
1043 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
1044 smmu->num_mapping_groups);
1045 if (IS_ERR_VALUE(idx)) {
1046 dev_err(smmu->dev, "failed to allocate free SMR\n");
1047 goto err_free_smrs;
1048 }
1049
1050 smrs[i] = (struct arm_smmu_smr) {
1051 .idx = idx,
1052 .mask = 0, /* We don't currently share SMRs */
1053 .id = master->streamids[i],
1054 };
1055 }
1056
1057 /* It worked! Now, poke the actual hardware */
1058 for (i = 0; i < master->num_streamids; ++i) {
1059 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1060 smrs[i].mask << SMR_MASK_SHIFT;
1061 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1062 }
1063
1064 master->smrs = smrs;
1065 return 0;
1066
1067 err_free_smrs:
1068 while (--i >= 0)
1069 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1070 kfree(smrs);
1071 return -ENOSPC;
1072 }
1073
1074 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1075 struct arm_smmu_master *master)
1076 {
1077 int i;
1078 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1079 struct arm_smmu_smr *smrs = master->smrs;
1080
1081 /* Invalidate the SMRs before freeing back to the allocator */
1082 for (i = 0; i < master->num_streamids; ++i) {
1083 u8 idx = smrs[i].idx;
1084 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1085 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1086 }
1087
1088 master->smrs = NULL;
1089 kfree(smrs);
1090 }
1091
1092 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1093 struct arm_smmu_master *master)
1094 {
1095 int i;
1096 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1097
1098 for (i = 0; i < master->num_streamids; ++i) {
1099 u16 sid = master->streamids[i];
1100 writel_relaxed(S2CR_TYPE_BYPASS,
1101 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1102 }
1103 }
1104
1105 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1106 struct arm_smmu_master *master)
1107 {
1108 int i, ret;
1109 struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1110 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1111
1112 ret = arm_smmu_master_configure_smrs(smmu, master);
1113 if (ret)
1114 return ret;
1115
1116 /* Bypass the leaves */
1117 smmu = smmu_domain->leaf_smmu;
1118 while ((parent = find_parent_smmu(smmu))) {
1119 /*
1120 * We won't have a StreamID match for anything but the root
1121 * smmu, so we only need to worry about StreamID indexing,
1122 * where we must install bypass entries in the S2CRs.
1123 */
1124 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1125 continue;
1126
1127 arm_smmu_bypass_stream_mapping(smmu, master);
1128 smmu = parent;
1129 }
1130
1131 /* Now we're at the root, time to point at our context bank */
1132 for (i = 0; i < master->num_streamids; ++i) {
1133 u32 idx, s2cr;
1134 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1135 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1136 (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1137 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1138 }
1139
1140 return 0;
1141 }
1142
1143 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1144 struct arm_smmu_master *master)
1145 {
1146 struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1147
1148 /*
1149 * We *must* clear the S2CR first, because freeing the SMR means
1150 * that it can be re-allocated immediately.
1151 */
1152 arm_smmu_bypass_stream_mapping(smmu, master);
1153 arm_smmu_master_free_smrs(smmu, master);
1154 }
1155
1156 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1157 {
1158 int ret = -EINVAL;
1159 struct arm_smmu_domain *smmu_domain = domain->priv;
1160 struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1161 struct arm_smmu_master *master;
1162 unsigned long flags;
1163
1164 if (!device_smmu) {
1165 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1166 return -ENXIO;
1167 }
1168
1169 /*
1170 * Sanity check the domain. We don't currently support domains
1171 * that cross between different SMMU chains.
1172 */
1173 spin_lock_irqsave(&smmu_domain->lock, flags);
1174 if (!smmu_domain->leaf_smmu) {
1175 /* Now that we have a master, we can finalise the domain */
1176 ret = arm_smmu_init_domain_context(domain, dev);
1177 if (IS_ERR_VALUE(ret))
1178 goto err_unlock;
1179
1180 smmu_domain->leaf_smmu = device_smmu;
1181 } else if (smmu_domain->leaf_smmu != device_smmu) {
1182 dev_err(dev,
1183 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1184 dev_name(smmu_domain->leaf_smmu->dev),
1185 dev_name(device_smmu->dev));
1186 goto err_unlock;
1187 }
1188 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1189
1190 /* Looks ok, so add the device to the domain */
1191 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1192 if (!master)
1193 return -ENODEV;
1194
1195 return arm_smmu_domain_add_master(smmu_domain, master);
1196
1197 err_unlock:
1198 spin_unlock_irqrestore(&smmu_domain->lock, flags);
1199 return ret;
1200 }
1201
1202 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1203 {
1204 struct arm_smmu_domain *smmu_domain = domain->priv;
1205 struct arm_smmu_master *master;
1206
1207 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1208 if (master)
1209 arm_smmu_domain_remove_master(smmu_domain, master);
1210 }
1211
1212 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1213 unsigned long end)
1214 {
1215 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1216 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1217 }
1218
1219 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1220 unsigned long addr, unsigned long end,
1221 unsigned long pfn, int flags, int stage)
1222 {
1223 pte_t *pte, *start;
1224 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF | ARM_SMMU_PTE_XN;
1225
1226 if (pmd_none(*pmd)) {
1227 /* Allocate a new set of tables */
1228 pgtable_t table = alloc_page(GFP_ATOMIC|__GFP_ZERO);
1229 if (!table)
1230 return -ENOMEM;
1231
1232 arm_smmu_flush_pgtable(smmu, page_address(table), PAGE_SIZE);
1233 if (!pgtable_page_ctor(table)) {
1234 __free_page(table);
1235 return -ENOMEM;
1236 }
1237 pmd_populate(NULL, pmd, table);
1238 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1239 }
1240
1241 if (stage == 1) {
1242 pteval |= ARM_SMMU_PTE_AP_UNPRIV | ARM_SMMU_PTE_nG;
1243 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
1244 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1245
1246 if (flags & IOMMU_CACHE)
1247 pteval |= (MAIR_ATTR_IDX_CACHE <<
1248 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1249 } else {
1250 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1251 if (flags & IOMMU_READ)
1252 pteval |= ARM_SMMU_PTE_HAP_READ;
1253 if (flags & IOMMU_WRITE)
1254 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1255 if (flags & IOMMU_CACHE)
1256 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1257 else
1258 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1259 }
1260
1261 /* If no access, create a faulting entry to avoid TLB fills */
1262 if (flags & IOMMU_EXEC)
1263 pteval &= ~ARM_SMMU_PTE_XN;
1264 else if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1265 pteval &= ~ARM_SMMU_PTE_PAGE;
1266
1267 pteval |= ARM_SMMU_PTE_SH_IS;
1268 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1269 pte = start;
1270
1271 /*
1272 * Install the page table entries. This is fairly complicated
1273 * since we attempt to make use of the contiguous hint in the
1274 * ptes where possible. The contiguous hint indicates a series
1275 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1276 * contiguous region with the following constraints:
1277 *
1278 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1279 * - Each pte in the region has the contiguous hint bit set
1280 *
1281 * This complicates unmapping (also handled by this code, when
1282 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1283 * possible, yet highly unlikely, that a client may unmap only
1284 * part of a contiguous range. This requires clearing of the
1285 * contiguous hint bits in the range before installing the new
1286 * faulting entries.
1287 *
1288 * Note that re-mapping an address range without first unmapping
1289 * it is not supported, so TLB invalidation is not required here
1290 * and is instead performed at unmap and domain-init time.
1291 */
1292 do {
1293 int i = 1;
1294 pteval &= ~ARM_SMMU_PTE_CONT;
1295
1296 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1297 i = ARM_SMMU_PTE_CONT_ENTRIES;
1298 pteval |= ARM_SMMU_PTE_CONT;
1299 } else if (pte_val(*pte) &
1300 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1301 int j;
1302 pte_t *cont_start;
1303 unsigned long idx = pte_index(addr);
1304
1305 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1306 cont_start = pmd_page_vaddr(*pmd) + idx;
1307 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1308 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1309
1310 arm_smmu_flush_pgtable(smmu, cont_start,
1311 sizeof(*pte) *
1312 ARM_SMMU_PTE_CONT_ENTRIES);
1313 }
1314
1315 do {
1316 *pte = pfn_pte(pfn, __pgprot(pteval));
1317 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1318 } while (addr != end);
1319
1320 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1321 return 0;
1322 }
1323
1324 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1325 unsigned long addr, unsigned long end,
1326 phys_addr_t phys, int flags, int stage)
1327 {
1328 int ret;
1329 pmd_t *pmd;
1330 unsigned long next, pfn = __phys_to_pfn(phys);
1331
1332 #ifndef __PAGETABLE_PMD_FOLDED
1333 if (pud_none(*pud)) {
1334 pmd = (pmd_t *)get_zeroed_page(GFP_ATOMIC);
1335 if (!pmd)
1336 return -ENOMEM;
1337
1338 arm_smmu_flush_pgtable(smmu, pmd, PAGE_SIZE);
1339 pud_populate(NULL, pud, pmd);
1340 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1341
1342 pmd += pmd_index(addr);
1343 } else
1344 #endif
1345 pmd = pmd_offset(pud, addr);
1346
1347 do {
1348 next = pmd_addr_end(addr, end);
1349 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1350 flags, stage);
1351 phys += next - addr;
1352 } while (pmd++, addr = next, addr < end);
1353
1354 return ret;
1355 }
1356
1357 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1358 unsigned long addr, unsigned long end,
1359 phys_addr_t phys, int flags, int stage)
1360 {
1361 int ret = 0;
1362 pud_t *pud;
1363 unsigned long next;
1364
1365 #ifndef __PAGETABLE_PUD_FOLDED
1366 if (pgd_none(*pgd)) {
1367 pud = (pud_t *)get_zeroed_page(GFP_ATOMIC);
1368 if (!pud)
1369 return -ENOMEM;
1370
1371 arm_smmu_flush_pgtable(smmu, pud, PAGE_SIZE);
1372 pgd_populate(NULL, pgd, pud);
1373 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1374
1375 pud += pud_index(addr);
1376 } else
1377 #endif
1378 pud = pud_offset(pgd, addr);
1379
1380 do {
1381 next = pud_addr_end(addr, end);
1382 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1383 flags, stage);
1384 phys += next - addr;
1385 } while (pud++, addr = next, addr < end);
1386
1387 return ret;
1388 }
1389
1390 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1391 unsigned long iova, phys_addr_t paddr,
1392 size_t size, int flags)
1393 {
1394 int ret, stage;
1395 unsigned long end;
1396 phys_addr_t input_mask, output_mask;
1397 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1398 pgd_t *pgd = root_cfg->pgd;
1399 struct arm_smmu_device *smmu = root_cfg->smmu;
1400 unsigned long irqflags;
1401
1402 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1403 stage = 2;
1404 output_mask = (1ULL << smmu->s2_output_size) - 1;
1405 } else {
1406 stage = 1;
1407 output_mask = (1ULL << smmu->s1_output_size) - 1;
1408 }
1409
1410 if (!pgd)
1411 return -EINVAL;
1412
1413 if (size & ~PAGE_MASK)
1414 return -EINVAL;
1415
1416 input_mask = (1ULL << smmu->input_size) - 1;
1417 if ((phys_addr_t)iova & ~input_mask)
1418 return -ERANGE;
1419
1420 if (paddr & ~output_mask)
1421 return -ERANGE;
1422
1423 spin_lock_irqsave(&smmu_domain->lock, irqflags);
1424 pgd += pgd_index(iova);
1425 end = iova + size;
1426 do {
1427 unsigned long next = pgd_addr_end(iova, end);
1428
1429 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1430 flags, stage);
1431 if (ret)
1432 goto out_unlock;
1433
1434 paddr += next - iova;
1435 iova = next;
1436 } while (pgd++, iova != end);
1437
1438 out_unlock:
1439 spin_unlock_irqrestore(&smmu_domain->lock, irqflags);
1440
1441 return ret;
1442 }
1443
1444 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1445 phys_addr_t paddr, size_t size, int flags)
1446 {
1447 struct arm_smmu_domain *smmu_domain = domain->priv;
1448
1449 if (!smmu_domain)
1450 return -ENODEV;
1451
1452 /* Check for silent address truncation up the SMMU chain. */
1453 if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1454 return -ERANGE;
1455
1456 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
1457 }
1458
1459 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1460 size_t size)
1461 {
1462 int ret;
1463 struct arm_smmu_domain *smmu_domain = domain->priv;
1464
1465 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1466 arm_smmu_tlb_inv_context(&smmu_domain->root_cfg);
1467 return ret ? ret : size;
1468 }
1469
1470 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1471 dma_addr_t iova)
1472 {
1473 pgd_t *pgdp, pgd;
1474 pud_t pud;
1475 pmd_t pmd;
1476 pte_t pte;
1477 struct arm_smmu_domain *smmu_domain = domain->priv;
1478 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1479
1480 pgdp = root_cfg->pgd;
1481 if (!pgdp)
1482 return 0;
1483
1484 pgd = *(pgdp + pgd_index(iova));
1485 if (pgd_none(pgd))
1486 return 0;
1487
1488 pud = *pud_offset(&pgd, iova);
1489 if (pud_none(pud))
1490 return 0;
1491
1492 pmd = *pmd_offset(&pud, iova);
1493 if (pmd_none(pmd))
1494 return 0;
1495
1496 pte = *(pmd_page_vaddr(pmd) + pte_index(iova));
1497 if (pte_none(pte))
1498 return 0;
1499
1500 return __pfn_to_phys(pte_pfn(pte)) | (iova & ~PAGE_MASK);
1501 }
1502
1503 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1504 unsigned long cap)
1505 {
1506 unsigned long caps = 0;
1507 struct arm_smmu_domain *smmu_domain = domain->priv;
1508
1509 if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1510 caps |= IOMMU_CAP_CACHE_COHERENCY;
1511
1512 return !!(cap & caps);
1513 }
1514
1515 static int arm_smmu_add_device(struct device *dev)
1516 {
1517 struct arm_smmu_device *child, *parent, *smmu;
1518 struct arm_smmu_master *master = NULL;
1519 struct iommu_group *group;
1520 int ret;
1521
1522 if (dev->archdata.iommu) {
1523 dev_warn(dev, "IOMMU driver already assigned to device\n");
1524 return -EINVAL;
1525 }
1526
1527 spin_lock(&arm_smmu_devices_lock);
1528 list_for_each_entry(parent, &arm_smmu_devices, list) {
1529 smmu = parent;
1530
1531 /* Try to find a child of the current SMMU. */
1532 list_for_each_entry(child, &arm_smmu_devices, list) {
1533 if (child->parent_of_node == parent->dev->of_node) {
1534 /* Does the child sit above our master? */
1535 master = find_smmu_master(child, dev->of_node);
1536 if (master) {
1537 smmu = NULL;
1538 break;
1539 }
1540 }
1541 }
1542
1543 /* We found some children, so keep searching. */
1544 if (!smmu) {
1545 master = NULL;
1546 continue;
1547 }
1548
1549 master = find_smmu_master(smmu, dev->of_node);
1550 if (master)
1551 break;
1552 }
1553 spin_unlock(&arm_smmu_devices_lock);
1554
1555 if (!master)
1556 return -ENODEV;
1557
1558 group = iommu_group_alloc();
1559 if (IS_ERR(group)) {
1560 dev_err(dev, "Failed to allocate IOMMU group\n");
1561 return PTR_ERR(group);
1562 }
1563
1564 ret = iommu_group_add_device(group, dev);
1565 iommu_group_put(group);
1566 dev->archdata.iommu = smmu;
1567
1568 return ret;
1569 }
1570
1571 static void arm_smmu_remove_device(struct device *dev)
1572 {
1573 dev->archdata.iommu = NULL;
1574 iommu_group_remove_device(dev);
1575 }
1576
1577 static struct iommu_ops arm_smmu_ops = {
1578 .domain_init = arm_smmu_domain_init,
1579 .domain_destroy = arm_smmu_domain_destroy,
1580 .attach_dev = arm_smmu_attach_dev,
1581 .detach_dev = arm_smmu_detach_dev,
1582 .map = arm_smmu_map,
1583 .unmap = arm_smmu_unmap,
1584 .iova_to_phys = arm_smmu_iova_to_phys,
1585 .domain_has_cap = arm_smmu_domain_has_cap,
1586 .add_device = arm_smmu_add_device,
1587 .remove_device = arm_smmu_remove_device,
1588 .pgsize_bitmap = (SECTION_SIZE |
1589 ARM_SMMU_PTE_CONT_SIZE |
1590 PAGE_SIZE),
1591 };
1592
1593 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1594 {
1595 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1596 void __iomem *cb_base;
1597 int i = 0;
1598 u32 reg;
1599
1600 /* Clear Global FSR */
1601 reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
1602 writel(reg, gr0_base + ARM_SMMU_GR0_sGFSR);
1603
1604 /* Mark all SMRn as invalid and all S2CRn as bypass */
1605 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1606 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1607 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1608 }
1609
1610 /* Make sure all context banks are disabled and clear CB_FSR */
1611 for (i = 0; i < smmu->num_context_banks; ++i) {
1612 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, i);
1613 writel_relaxed(0, cb_base + ARM_SMMU_CB_SCTLR);
1614 writel_relaxed(FSR_FAULT, cb_base + ARM_SMMU_CB_FSR);
1615 }
1616
1617 /* Invalidate the TLB, just in case */
1618 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1619 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1620 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1621
1622 reg = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
1623
1624 /* Enable fault reporting */
1625 reg |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1626
1627 /* Disable TLB broadcasting. */
1628 reg |= (sCR0_VMIDPNE | sCR0_PTM);
1629
1630 /* Enable client access, but bypass when no mapping is found */
1631 reg &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1632
1633 /* Disable forced broadcasting */
1634 reg &= ~sCR0_FB;
1635
1636 /* Don't upgrade barriers */
1637 reg &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1638
1639 /* Push the button */
1640 arm_smmu_tlb_sync(smmu);
1641 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_sCR0);
1642 }
1643
1644 static int arm_smmu_id_size_to_bits(int size)
1645 {
1646 switch (size) {
1647 case 0:
1648 return 32;
1649 case 1:
1650 return 36;
1651 case 2:
1652 return 40;
1653 case 3:
1654 return 42;
1655 case 4:
1656 return 44;
1657 case 5:
1658 default:
1659 return 48;
1660 }
1661 }
1662
1663 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1664 {
1665 unsigned long size;
1666 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1667 u32 id;
1668
1669 dev_notice(smmu->dev, "probing hardware configuration...\n");
1670
1671 /* Primecell ID */
1672 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1673 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1674 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1675
1676 /* ID0 */
1677 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1678 #ifndef CONFIG_64BIT
1679 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1680 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1681 return -ENODEV;
1682 }
1683 #endif
1684 if (id & ID0_S1TS) {
1685 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1686 dev_notice(smmu->dev, "\tstage 1 translation\n");
1687 }
1688
1689 if (id & ID0_S2TS) {
1690 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1691 dev_notice(smmu->dev, "\tstage 2 translation\n");
1692 }
1693
1694 if (id & ID0_NTS) {
1695 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1696 dev_notice(smmu->dev, "\tnested translation\n");
1697 }
1698
1699 if (!(smmu->features &
1700 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1701 ARM_SMMU_FEAT_TRANS_NESTED))) {
1702 dev_err(smmu->dev, "\tno translation support!\n");
1703 return -ENODEV;
1704 }
1705
1706 if (id & ID0_CTTW) {
1707 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1708 dev_notice(smmu->dev, "\tcoherent table walk\n");
1709 }
1710
1711 if (id & ID0_SMS) {
1712 u32 smr, sid, mask;
1713
1714 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1715 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1716 ID0_NUMSMRG_MASK;
1717 if (smmu->num_mapping_groups == 0) {
1718 dev_err(smmu->dev,
1719 "stream-matching supported, but no SMRs present!\n");
1720 return -ENODEV;
1721 }
1722
1723 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1724 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1725 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1726 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1727
1728 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1729 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1730 if ((mask & sid) != sid) {
1731 dev_err(smmu->dev,
1732 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1733 mask, sid);
1734 return -ENODEV;
1735 }
1736
1737 dev_notice(smmu->dev,
1738 "\tstream matching with %u register groups, mask 0x%x",
1739 smmu->num_mapping_groups, mask);
1740 }
1741
1742 /* ID1 */
1743 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1744 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1745
1746 /* Check for size mismatch of SMMU address space from mapped region */
1747 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1748 size *= (smmu->pagesize << 1);
1749 if (smmu->size != size)
1750 dev_warn(smmu->dev, "SMMU address space size (0x%lx) differs "
1751 "from mapped region size (0x%lx)!\n", size, smmu->size);
1752
1753 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1754 ID1_NUMS2CB_MASK;
1755 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1756 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1757 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1758 return -ENODEV;
1759 }
1760 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1761 smmu->num_context_banks, smmu->num_s2_context_banks);
1762
1763 /* ID2 */
1764 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1765 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1766
1767 /*
1768 * Stage-1 output limited by stage-2 input size due to pgd
1769 * allocation (PTRS_PER_PGD).
1770 */
1771 #ifdef CONFIG_64BIT
1772 smmu->s1_output_size = min(39UL, size);
1773 #else
1774 smmu->s1_output_size = min(32UL, size);
1775 #endif
1776
1777 /* The stage-2 output mask is also applied for bypass */
1778 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1779 smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1780
1781 if (smmu->version == 1) {
1782 smmu->input_size = 32;
1783 } else {
1784 #ifdef CONFIG_64BIT
1785 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1786 size = min(VA_BITS, arm_smmu_id_size_to_bits(size));
1787 #else
1788 size = 32;
1789 #endif
1790 smmu->input_size = size;
1791
1792 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1793 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1794 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1795 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1796 PAGE_SIZE);
1797 return -ENODEV;
1798 }
1799 }
1800
1801 dev_notice(smmu->dev,
1802 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1803 smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1804 return 0;
1805 }
1806
1807 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1808 {
1809 struct resource *res;
1810 struct arm_smmu_device *smmu;
1811 struct device_node *dev_node;
1812 struct device *dev = &pdev->dev;
1813 struct rb_node *node;
1814 struct of_phandle_args masterspec;
1815 int num_irqs, i, err;
1816
1817 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1818 if (!smmu) {
1819 dev_err(dev, "failed to allocate arm_smmu_device\n");
1820 return -ENOMEM;
1821 }
1822 smmu->dev = dev;
1823
1824 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1825 smmu->base = devm_ioremap_resource(dev, res);
1826 if (IS_ERR(smmu->base))
1827 return PTR_ERR(smmu->base);
1828 smmu->size = resource_size(res);
1829
1830 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1831 &smmu->num_global_irqs)) {
1832 dev_err(dev, "missing #global-interrupts property\n");
1833 return -ENODEV;
1834 }
1835
1836 num_irqs = 0;
1837 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1838 num_irqs++;
1839 if (num_irqs > smmu->num_global_irqs)
1840 smmu->num_context_irqs++;
1841 }
1842
1843 if (!smmu->num_context_irqs) {
1844 dev_err(dev, "found %d interrupts but expected at least %d\n",
1845 num_irqs, smmu->num_global_irqs + 1);
1846 return -ENODEV;
1847 }
1848
1849 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1850 GFP_KERNEL);
1851 if (!smmu->irqs) {
1852 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1853 return -ENOMEM;
1854 }
1855
1856 for (i = 0; i < num_irqs; ++i) {
1857 int irq = platform_get_irq(pdev, i);
1858 if (irq < 0) {
1859 dev_err(dev, "failed to get irq index %d\n", i);
1860 return -ENODEV;
1861 }
1862 smmu->irqs[i] = irq;
1863 }
1864
1865 i = 0;
1866 smmu->masters = RB_ROOT;
1867 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1868 "#stream-id-cells", i,
1869 &masterspec)) {
1870 err = register_smmu_master(smmu, dev, &masterspec);
1871 if (err) {
1872 dev_err(dev, "failed to add master %s\n",
1873 masterspec.np->name);
1874 goto out_put_masters;
1875 }
1876
1877 i++;
1878 }
1879 dev_notice(dev, "registered %d master devices\n", i);
1880
1881 if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1882 smmu->parent_of_node = dev_node;
1883
1884 err = arm_smmu_device_cfg_probe(smmu);
1885 if (err)
1886 goto out_put_parent;
1887
1888 if (smmu->version > 1 &&
1889 smmu->num_context_banks != smmu->num_context_irqs) {
1890 dev_err(dev,
1891 "found only %d context interrupt(s) but %d required\n",
1892 smmu->num_context_irqs, smmu->num_context_banks);
1893 err = -ENODEV;
1894 goto out_put_parent;
1895 }
1896
1897 for (i = 0; i < smmu->num_global_irqs; ++i) {
1898 err = request_irq(smmu->irqs[i],
1899 arm_smmu_global_fault,
1900 IRQF_SHARED,
1901 "arm-smmu global fault",
1902 smmu);
1903 if (err) {
1904 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1905 i, smmu->irqs[i]);
1906 goto out_free_irqs;
1907 }
1908 }
1909
1910 INIT_LIST_HEAD(&smmu->list);
1911 spin_lock(&arm_smmu_devices_lock);
1912 list_add(&smmu->list, &arm_smmu_devices);
1913 spin_unlock(&arm_smmu_devices_lock);
1914
1915 arm_smmu_device_reset(smmu);
1916 return 0;
1917
1918 out_free_irqs:
1919 while (i--)
1920 free_irq(smmu->irqs[i], smmu);
1921
1922 out_put_parent:
1923 if (smmu->parent_of_node)
1924 of_node_put(smmu->parent_of_node);
1925
1926 out_put_masters:
1927 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1928 struct arm_smmu_master *master;
1929 master = container_of(node, struct arm_smmu_master, node);
1930 of_node_put(master->of_node);
1931 }
1932
1933 return err;
1934 }
1935
1936 static int arm_smmu_device_remove(struct platform_device *pdev)
1937 {
1938 int i;
1939 struct device *dev = &pdev->dev;
1940 struct arm_smmu_device *curr, *smmu = NULL;
1941 struct rb_node *node;
1942
1943 spin_lock(&arm_smmu_devices_lock);
1944 list_for_each_entry(curr, &arm_smmu_devices, list) {
1945 if (curr->dev == dev) {
1946 smmu = curr;
1947 list_del(&smmu->list);
1948 break;
1949 }
1950 }
1951 spin_unlock(&arm_smmu_devices_lock);
1952
1953 if (!smmu)
1954 return -ENODEV;
1955
1956 if (smmu->parent_of_node)
1957 of_node_put(smmu->parent_of_node);
1958
1959 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1960 struct arm_smmu_master *master;
1961 master = container_of(node, struct arm_smmu_master, node);
1962 of_node_put(master->of_node);
1963 }
1964
1965 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS))
1966 dev_err(dev, "removing device with active domains!\n");
1967
1968 for (i = 0; i < smmu->num_global_irqs; ++i)
1969 free_irq(smmu->irqs[i], smmu);
1970
1971 /* Turn the thing off */
1972 writel_relaxed(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
1973 return 0;
1974 }
1975
1976 #ifdef CONFIG_OF
1977 static struct of_device_id arm_smmu_of_match[] = {
1978 { .compatible = "arm,smmu-v1", },
1979 { .compatible = "arm,smmu-v2", },
1980 { .compatible = "arm,mmu-400", },
1981 { .compatible = "arm,mmu-500", },
1982 { },
1983 };
1984 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1985 #endif
1986
1987 static struct platform_driver arm_smmu_driver = {
1988 .driver = {
1989 .owner = THIS_MODULE,
1990 .name = "arm-smmu",
1991 .of_match_table = of_match_ptr(arm_smmu_of_match),
1992 },
1993 .probe = arm_smmu_device_dt_probe,
1994 .remove = arm_smmu_device_remove,
1995 };
1996
1997 static int __init arm_smmu_init(void)
1998 {
1999 int ret;
2000
2001 ret = platform_driver_register(&arm_smmu_driver);
2002 if (ret)
2003 return ret;
2004
2005 /* Oh, for a proper bus abstraction */
2006 if (!iommu_present(&platform_bus_type))
2007 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
2008
2009 #ifdef CONFIG_ARM_AMBA
2010 if (!iommu_present(&amba_bustype))
2011 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
2012 #endif
2013
2014 return 0;
2015 }
2016
2017 static void __exit arm_smmu_exit(void)
2018 {
2019 return platform_driver_unregister(&arm_smmu_driver);
2020 }
2021
2022 subsys_initcall(arm_smmu_init);
2023 module_exit(arm_smmu_exit);
2024
2025 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2026 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
2027 MODULE_LICENSE("GPL v2");
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