2 * IOMMU API for ARM architected SMMU implementations.
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * Copyright (C) 2013 ARM Limited
19 * Author: Will Deacon <will.deacon@arm.com>
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - Context fault reporting
29 #define pr_fmt(fmt) "arm-smmu: " fmt
31 #include <linux/delay.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/err.h>
34 #include <linux/interrupt.h>
36 #include <linux/iommu.h>
37 #include <linux/iopoll.h>
38 #include <linux/module.h>
40 #include <linux/of_address.h>
41 #include <linux/pci.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
46 #include <linux/amba/bus.h>
48 #include "io-pgtable.h"
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS MAX_PHANDLE_ARGS
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
59 /* SMMU global address space */
60 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
61 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (1 << (smmu)->pgshift))
64 * SMMU global address space with conditional offset to access secure
65 * aliases of non-secure registers (e.g. nsCR0: 0x400, nsGFSR: 0x448,
68 #define ARM_SMMU_GR0_NS(smmu) \
70 ((smmu->options & ARM_SMMU_OPT_SECURE_CFG_ACCESS) \
74 #define smmu_writeq writeq_relaxed
76 #define smmu_writeq(reg64, addr) \
78 u64 __val = (reg64); \
79 void __iomem *__addr = (addr); \
80 writel_relaxed(__val >> 32, __addr + 4); \
81 writel_relaxed(__val, __addr); \
85 /* Configuration registers */
86 #define ARM_SMMU_GR0_sCR0 0x0
87 #define sCR0_CLIENTPD (1 << 0)
88 #define sCR0_GFRE (1 << 1)
89 #define sCR0_GFIE (1 << 2)
90 #define sCR0_GCFGFRE (1 << 4)
91 #define sCR0_GCFGFIE (1 << 5)
92 #define sCR0_USFCFG (1 << 10)
93 #define sCR0_VMIDPNE (1 << 11)
94 #define sCR0_PTM (1 << 12)
95 #define sCR0_FB (1 << 13)
96 #define sCR0_BSU_SHIFT 14
97 #define sCR0_BSU_MASK 0x3
99 /* Identification registers */
100 #define ARM_SMMU_GR0_ID0 0x20
101 #define ARM_SMMU_GR0_ID1 0x24
102 #define ARM_SMMU_GR0_ID2 0x28
103 #define ARM_SMMU_GR0_ID3 0x2c
104 #define ARM_SMMU_GR0_ID4 0x30
105 #define ARM_SMMU_GR0_ID5 0x34
106 #define ARM_SMMU_GR0_ID6 0x38
107 #define ARM_SMMU_GR0_ID7 0x3c
108 #define ARM_SMMU_GR0_sGFSR 0x48
109 #define ARM_SMMU_GR0_sGFSYNR0 0x50
110 #define ARM_SMMU_GR0_sGFSYNR1 0x54
111 #define ARM_SMMU_GR0_sGFSYNR2 0x58
113 #define ID0_S1TS (1 << 30)
114 #define ID0_S2TS (1 << 29)
115 #define ID0_NTS (1 << 28)
116 #define ID0_SMS (1 << 27)
117 #define ID0_ATOSNS (1 << 26)
118 #define ID0_CTTW (1 << 14)
119 #define ID0_NUMIRPT_SHIFT 16
120 #define ID0_NUMIRPT_MASK 0xff
121 #define ID0_NUMSIDB_SHIFT 9
122 #define ID0_NUMSIDB_MASK 0xf
123 #define ID0_NUMSMRG_SHIFT 0
124 #define ID0_NUMSMRG_MASK 0xff
126 #define ID1_PAGESIZE (1 << 31)
127 #define ID1_NUMPAGENDXB_SHIFT 28
128 #define ID1_NUMPAGENDXB_MASK 7
129 #define ID1_NUMS2CB_SHIFT 16
130 #define ID1_NUMS2CB_MASK 0xff
131 #define ID1_NUMCB_SHIFT 0
132 #define ID1_NUMCB_MASK 0xff
134 #define ID2_OAS_SHIFT 4
135 #define ID2_OAS_MASK 0xf
136 #define ID2_IAS_SHIFT 0
137 #define ID2_IAS_MASK 0xf
138 #define ID2_UBS_SHIFT 8
139 #define ID2_UBS_MASK 0xf
140 #define ID2_PTFS_4K (1 << 12)
141 #define ID2_PTFS_16K (1 << 13)
142 #define ID2_PTFS_64K (1 << 14)
144 /* Global TLB invalidation */
145 #define ARM_SMMU_GR0_TLBIVMID 0x64
146 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
147 #define ARM_SMMU_GR0_TLBIALLH 0x6c
148 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
149 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
150 #define sTLBGSTATUS_GSACTIVE (1 << 0)
151 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
153 /* Stream mapping registers */
154 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
155 #define SMR_VALID (1 << 31)
156 #define SMR_MASK_SHIFT 16
157 #define SMR_MASK_MASK 0x7fff
158 #define SMR_ID_SHIFT 0
159 #define SMR_ID_MASK 0x7fff
161 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
162 #define S2CR_CBNDX_SHIFT 0
163 #define S2CR_CBNDX_MASK 0xff
164 #define S2CR_TYPE_SHIFT 16
165 #define S2CR_TYPE_MASK 0x3
166 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
167 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
168 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
170 /* Context bank attribute registers */
171 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
172 #define CBAR_VMID_SHIFT 0
173 #define CBAR_VMID_MASK 0xff
174 #define CBAR_S1_BPSHCFG_SHIFT 8
175 #define CBAR_S1_BPSHCFG_MASK 3
176 #define CBAR_S1_BPSHCFG_NSH 3
177 #define CBAR_S1_MEMATTR_SHIFT 12
178 #define CBAR_S1_MEMATTR_MASK 0xf
179 #define CBAR_S1_MEMATTR_WB 0xf
180 #define CBAR_TYPE_SHIFT 16
181 #define CBAR_TYPE_MASK 0x3
182 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
183 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
184 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
185 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
186 #define CBAR_IRPTNDX_SHIFT 24
187 #define CBAR_IRPTNDX_MASK 0xff
189 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
190 #define CBA2R_RW64_32BIT (0 << 0)
191 #define CBA2R_RW64_64BIT (1 << 0)
193 /* Translation context bank */
194 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
195 #define ARM_SMMU_CB(smmu, n) ((n) * (1 << (smmu)->pgshift))
197 #define ARM_SMMU_CB_SCTLR 0x0
198 #define ARM_SMMU_CB_RESUME 0x8
199 #define ARM_SMMU_CB_TTBCR2 0x10
200 #define ARM_SMMU_CB_TTBR0 0x20
201 #define ARM_SMMU_CB_TTBR1 0x28
202 #define ARM_SMMU_CB_TTBCR 0x30
203 #define ARM_SMMU_CB_S1_MAIR0 0x38
204 #define ARM_SMMU_CB_S1_MAIR1 0x3c
205 #define ARM_SMMU_CB_PAR_LO 0x50
206 #define ARM_SMMU_CB_PAR_HI 0x54
207 #define ARM_SMMU_CB_FSR 0x58
208 #define ARM_SMMU_CB_FAR_LO 0x60
209 #define ARM_SMMU_CB_FAR_HI 0x64
210 #define ARM_SMMU_CB_FSYNR0 0x68
211 #define ARM_SMMU_CB_S1_TLBIVA 0x600
212 #define ARM_SMMU_CB_S1_TLBIASID 0x610
213 #define ARM_SMMU_CB_S1_TLBIVAL 0x620
214 #define ARM_SMMU_CB_S2_TLBIIPAS2 0x630
215 #define ARM_SMMU_CB_S2_TLBIIPAS2L 0x638
216 #define ARM_SMMU_CB_ATS1PR 0x800
217 #define ARM_SMMU_CB_ATSR 0x8f0
219 #define SCTLR_S1_ASIDPNE (1 << 12)
220 #define SCTLR_CFCFG (1 << 7)
221 #define SCTLR_CFIE (1 << 6)
222 #define SCTLR_CFRE (1 << 5)
223 #define SCTLR_E (1 << 4)
224 #define SCTLR_AFE (1 << 2)
225 #define SCTLR_TRE (1 << 1)
226 #define SCTLR_M (1 << 0)
227 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
229 #define CB_PAR_F (1 << 0)
231 #define ATSR_ACTIVE (1 << 0)
233 #define RESUME_RETRY (0 << 0)
234 #define RESUME_TERMINATE (1 << 0)
236 #define TTBCR2_SEP_SHIFT 15
237 #define TTBCR2_SEP_UPSTREAM (0x7 << TTBCR2_SEP_SHIFT)
239 #define TTBRn_ASID_SHIFT 48
241 #define FSR_MULTI (1 << 31)
242 #define FSR_SS (1 << 30)
243 #define FSR_UUT (1 << 8)
244 #define FSR_ASF (1 << 7)
245 #define FSR_TLBLKF (1 << 6)
246 #define FSR_TLBMCF (1 << 5)
247 #define FSR_EF (1 << 4)
248 #define FSR_PF (1 << 3)
249 #define FSR_AFF (1 << 2)
250 #define FSR_TF (1 << 1)
252 #define FSR_IGN (FSR_AFF | FSR_ASF | \
253 FSR_TLBMCF | FSR_TLBLKF)
254 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
255 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
257 #define FSYNR0_WNR (1 << 4)
259 static int force_stage
;
260 module_param_named(force_stage
, force_stage
, int, S_IRUGO
);
261 MODULE_PARM_DESC(force_stage
,
262 "Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' forces the corresponding stage. All other values are ignored (i.e. no stage is forced). Note that selecting a specific stage will disable support for nested translation.");
264 enum arm_smmu_arch_version
{
269 struct arm_smmu_smr
{
275 struct arm_smmu_master_cfg
{
277 u16 streamids
[MAX_MASTER_STREAMIDS
];
278 struct arm_smmu_smr
*smrs
;
281 struct arm_smmu_master
{
282 struct device_node
*of_node
;
284 struct arm_smmu_master_cfg cfg
;
287 struct arm_smmu_device
{
292 unsigned long pgshift
;
294 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
295 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
296 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
297 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
298 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
299 #define ARM_SMMU_FEAT_TRANS_OPS (1 << 5)
302 #define ARM_SMMU_OPT_SECURE_CFG_ACCESS (1 << 0)
304 enum arm_smmu_arch_version version
;
306 u32 num_context_banks
;
307 u32 num_s2_context_banks
;
308 DECLARE_BITMAP(context_map
, ARM_SMMU_MAX_CBS
);
311 u32 num_mapping_groups
;
312 DECLARE_BITMAP(smr_map
, ARM_SMMU_MAX_SMRS
);
314 unsigned long va_size
;
315 unsigned long ipa_size
;
316 unsigned long pa_size
;
319 u32 num_context_irqs
;
322 struct list_head list
;
323 struct rb_root masters
;
326 struct arm_smmu_cfg
{
331 #define INVALID_IRPTNDX 0xff
333 #define ARM_SMMU_CB_ASID(cfg) ((cfg)->cbndx)
334 #define ARM_SMMU_CB_VMID(cfg) ((cfg)->cbndx + 1)
336 enum arm_smmu_domain_stage
{
337 ARM_SMMU_DOMAIN_S1
= 0,
339 ARM_SMMU_DOMAIN_NESTED
,
342 struct arm_smmu_domain
{
343 struct arm_smmu_device
*smmu
;
344 struct io_pgtable_ops
*pgtbl_ops
;
345 spinlock_t pgtbl_lock
;
346 struct arm_smmu_cfg cfg
;
347 enum arm_smmu_domain_stage stage
;
348 struct mutex init_mutex
; /* Protects smmu pointer */
349 struct iommu_domain domain
;
352 static struct iommu_ops arm_smmu_ops
;
354 static DEFINE_SPINLOCK(arm_smmu_devices_lock
);
355 static LIST_HEAD(arm_smmu_devices
);
357 struct arm_smmu_option_prop
{
362 static struct arm_smmu_option_prop arm_smmu_options
[] = {
363 { ARM_SMMU_OPT_SECURE_CFG_ACCESS
, "calxeda,smmu-secure-config-access" },
367 static struct arm_smmu_domain
*to_smmu_domain(struct iommu_domain
*dom
)
369 return container_of(dom
, struct arm_smmu_domain
, domain
);
372 static void parse_driver_options(struct arm_smmu_device
*smmu
)
377 if (of_property_read_bool(smmu
->dev
->of_node
,
378 arm_smmu_options
[i
].prop
)) {
379 smmu
->options
|= arm_smmu_options
[i
].opt
;
380 dev_notice(smmu
->dev
, "option %s\n",
381 arm_smmu_options
[i
].prop
);
383 } while (arm_smmu_options
[++i
].opt
);
386 static struct device_node
*dev_get_dev_node(struct device
*dev
)
388 if (dev_is_pci(dev
)) {
389 struct pci_bus
*bus
= to_pci_dev(dev
)->bus
;
391 while (!pci_is_root_bus(bus
))
393 return bus
->bridge
->parent
->of_node
;
399 static struct arm_smmu_master
*find_smmu_master(struct arm_smmu_device
*smmu
,
400 struct device_node
*dev_node
)
402 struct rb_node
*node
= smmu
->masters
.rb_node
;
405 struct arm_smmu_master
*master
;
407 master
= container_of(node
, struct arm_smmu_master
, node
);
409 if (dev_node
< master
->of_node
)
410 node
= node
->rb_left
;
411 else if (dev_node
> master
->of_node
)
412 node
= node
->rb_right
;
420 static struct arm_smmu_master_cfg
*
421 find_smmu_master_cfg(struct device
*dev
)
423 struct arm_smmu_master_cfg
*cfg
= NULL
;
424 struct iommu_group
*group
= iommu_group_get(dev
);
427 cfg
= iommu_group_get_iommudata(group
);
428 iommu_group_put(group
);
434 static int insert_smmu_master(struct arm_smmu_device
*smmu
,
435 struct arm_smmu_master
*master
)
437 struct rb_node
**new, *parent
;
439 new = &smmu
->masters
.rb_node
;
442 struct arm_smmu_master
*this
443 = container_of(*new, struct arm_smmu_master
, node
);
446 if (master
->of_node
< this->of_node
)
447 new = &((*new)->rb_left
);
448 else if (master
->of_node
> this->of_node
)
449 new = &((*new)->rb_right
);
454 rb_link_node(&master
->node
, parent
, new);
455 rb_insert_color(&master
->node
, &smmu
->masters
);
459 static int register_smmu_master(struct arm_smmu_device
*smmu
,
461 struct of_phandle_args
*masterspec
)
464 struct arm_smmu_master
*master
;
466 master
= find_smmu_master(smmu
, masterspec
->np
);
469 "rejecting multiple registrations for master device %s\n",
470 masterspec
->np
->name
);
474 if (masterspec
->args_count
> MAX_MASTER_STREAMIDS
) {
476 "reached maximum number (%d) of stream IDs for master device %s\n",
477 MAX_MASTER_STREAMIDS
, masterspec
->np
->name
);
481 master
= devm_kzalloc(dev
, sizeof(*master
), GFP_KERNEL
);
485 master
->of_node
= masterspec
->np
;
486 master
->cfg
.num_streamids
= masterspec
->args_count
;
488 for (i
= 0; i
< master
->cfg
.num_streamids
; ++i
) {
489 u16 streamid
= masterspec
->args
[i
];
491 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) &&
492 (streamid
>= smmu
->num_mapping_groups
)) {
494 "stream ID for master device %s greater than maximum allowed (%d)\n",
495 masterspec
->np
->name
, smmu
->num_mapping_groups
);
498 master
->cfg
.streamids
[i
] = streamid
;
500 return insert_smmu_master(smmu
, master
);
503 static struct arm_smmu_device
*find_smmu_for_device(struct device
*dev
)
505 struct arm_smmu_device
*smmu
;
506 struct arm_smmu_master
*master
= NULL
;
507 struct device_node
*dev_node
= dev_get_dev_node(dev
);
509 spin_lock(&arm_smmu_devices_lock
);
510 list_for_each_entry(smmu
, &arm_smmu_devices
, list
) {
511 master
= find_smmu_master(smmu
, dev_node
);
515 spin_unlock(&arm_smmu_devices_lock
);
517 return master
? smmu
: NULL
;
520 static int __arm_smmu_alloc_bitmap(unsigned long *map
, int start
, int end
)
525 idx
= find_next_zero_bit(map
, end
, start
);
528 } while (test_and_set_bit(idx
, map
));
533 static void __arm_smmu_free_bitmap(unsigned long *map
, int idx
)
538 /* Wait for any pending TLB invalidations to complete */
539 static void __arm_smmu_tlb_sync(struct arm_smmu_device
*smmu
)
542 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
544 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_sTLBGSYNC
);
545 while (readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sTLBGSTATUS
)
546 & sTLBGSTATUS_GSACTIVE
) {
548 if (++count
== TLB_LOOP_TIMEOUT
) {
549 dev_err_ratelimited(smmu
->dev
,
550 "TLB sync timed out -- SMMU may be deadlocked\n");
557 static void arm_smmu_tlb_sync(void *cookie
)
559 struct arm_smmu_domain
*smmu_domain
= cookie
;
560 __arm_smmu_tlb_sync(smmu_domain
->smmu
);
563 static void arm_smmu_tlb_inv_context(void *cookie
)
565 struct arm_smmu_domain
*smmu_domain
= cookie
;
566 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
567 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
568 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
572 base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
573 writel_relaxed(ARM_SMMU_CB_ASID(cfg
),
574 base
+ ARM_SMMU_CB_S1_TLBIASID
);
576 base
= ARM_SMMU_GR0(smmu
);
577 writel_relaxed(ARM_SMMU_CB_VMID(cfg
),
578 base
+ ARM_SMMU_GR0_TLBIVMID
);
581 __arm_smmu_tlb_sync(smmu
);
584 static void arm_smmu_tlb_inv_range_nosync(unsigned long iova
, size_t size
,
585 size_t granule
, bool leaf
, void *cookie
)
587 struct arm_smmu_domain
*smmu_domain
= cookie
;
588 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
589 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
590 bool stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
594 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
595 reg
+= leaf
? ARM_SMMU_CB_S1_TLBIVAL
: ARM_SMMU_CB_S1_TLBIVA
;
597 if (!IS_ENABLED(CONFIG_64BIT
) || smmu
->version
== ARM_SMMU_V1
) {
599 iova
|= ARM_SMMU_CB_ASID(cfg
);
601 writel_relaxed(iova
, reg
);
603 } while (size
-= granule
);
607 iova
|= (u64
)ARM_SMMU_CB_ASID(cfg
) << 48;
609 writeq_relaxed(iova
, reg
);
610 iova
+= granule
>> 12;
611 } while (size
-= granule
);
615 } else if (smmu
->version
== ARM_SMMU_V2
) {
616 reg
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
617 reg
+= leaf
? ARM_SMMU_CB_S2_TLBIIPAS2L
:
618 ARM_SMMU_CB_S2_TLBIIPAS2
;
621 writeq_relaxed(iova
, reg
);
622 iova
+= granule
>> 12;
623 } while (size
-= granule
);
626 reg
= ARM_SMMU_GR0(smmu
) + ARM_SMMU_GR0_TLBIVMID
;
627 writel_relaxed(ARM_SMMU_CB_VMID(cfg
), reg
);
631 static struct iommu_gather_ops arm_smmu_gather_ops
= {
632 .tlb_flush_all
= arm_smmu_tlb_inv_context
,
633 .tlb_add_flush
= arm_smmu_tlb_inv_range_nosync
,
634 .tlb_sync
= arm_smmu_tlb_sync
,
637 static irqreturn_t
arm_smmu_context_fault(int irq
, void *dev
)
640 u32 fsr
, far
, fsynr
, resume
;
642 struct iommu_domain
*domain
= dev
;
643 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
644 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
645 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
646 void __iomem
*cb_base
;
648 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
649 fsr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSR
);
651 if (!(fsr
& FSR_FAULT
))
655 dev_err_ratelimited(smmu
->dev
,
656 "Unexpected context fault (fsr 0x%x)\n",
659 fsynr
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FSYNR0
);
660 flags
= fsynr
& FSYNR0_WNR
? IOMMU_FAULT_WRITE
: IOMMU_FAULT_READ
;
662 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_LO
);
665 far
= readl_relaxed(cb_base
+ ARM_SMMU_CB_FAR_HI
);
666 iova
|= ((unsigned long)far
<< 32);
669 if (!report_iommu_fault(domain
, smmu
->dev
, iova
, flags
)) {
671 resume
= RESUME_RETRY
;
673 dev_err_ratelimited(smmu
->dev
,
674 "Unhandled context fault: iova=0x%08lx, fsynr=0x%x, cb=%d\n",
675 iova
, fsynr
, cfg
->cbndx
);
677 resume
= RESUME_TERMINATE
;
680 /* Clear the faulting FSR */
681 writel(fsr
, cb_base
+ ARM_SMMU_CB_FSR
);
683 /* Retry or terminate any stalled transactions */
685 writel_relaxed(resume
, cb_base
+ ARM_SMMU_CB_RESUME
);
690 static irqreturn_t
arm_smmu_global_fault(int irq
, void *dev
)
692 u32 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
;
693 struct arm_smmu_device
*smmu
= dev
;
694 void __iomem
*gr0_base
= ARM_SMMU_GR0_NS(smmu
);
696 gfsr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSR
);
697 gfsynr0
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR0
);
698 gfsynr1
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR1
);
699 gfsynr2
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_sGFSYNR2
);
704 dev_err_ratelimited(smmu
->dev
,
705 "Unexpected global fault, this could be serious\n");
706 dev_err_ratelimited(smmu
->dev
,
707 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
708 gfsr
, gfsynr0
, gfsynr1
, gfsynr2
);
710 writel(gfsr
, gr0_base
+ ARM_SMMU_GR0_sGFSR
);
714 static void arm_smmu_init_context_bank(struct arm_smmu_domain
*smmu_domain
,
715 struct io_pgtable_cfg
*pgtbl_cfg
)
720 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
721 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
722 void __iomem
*cb_base
, *gr1_base
;
724 gr1_base
= ARM_SMMU_GR1(smmu
);
725 stage1
= cfg
->cbar
!= CBAR_TYPE_S2_TRANS
;
726 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
728 if (smmu
->version
> ARM_SMMU_V1
) {
731 * *Must* be initialised before CBAR thanks to VMID16
732 * architectural oversight affected some implementations.
735 reg
= CBA2R_RW64_64BIT
;
737 reg
= CBA2R_RW64_32BIT
;
739 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBA2R(cfg
->cbndx
));
744 if (smmu
->version
== ARM_SMMU_V1
)
745 reg
|= cfg
->irptndx
<< CBAR_IRPTNDX_SHIFT
;
748 * Use the weakest shareability/memory types, so they are
749 * overridden by the ttbcr/pte.
752 reg
|= (CBAR_S1_BPSHCFG_NSH
<< CBAR_S1_BPSHCFG_SHIFT
) |
753 (CBAR_S1_MEMATTR_WB
<< CBAR_S1_MEMATTR_SHIFT
);
755 reg
|= ARM_SMMU_CB_VMID(cfg
) << CBAR_VMID_SHIFT
;
757 writel_relaxed(reg
, gr1_base
+ ARM_SMMU_GR1_CBAR(cfg
->cbndx
));
761 reg64
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[0];
763 reg64
|= ((u64
)ARM_SMMU_CB_ASID(cfg
)) << TTBRn_ASID_SHIFT
;
764 smmu_writeq(reg64
, cb_base
+ ARM_SMMU_CB_TTBR0
);
766 reg64
= pgtbl_cfg
->arm_lpae_s1_cfg
.ttbr
[1];
767 reg64
|= ((u64
)ARM_SMMU_CB_ASID(cfg
)) << TTBRn_ASID_SHIFT
;
768 smmu_writeq(reg64
, cb_base
+ ARM_SMMU_CB_TTBR1
);
770 reg64
= pgtbl_cfg
->arm_lpae_s2_cfg
.vttbr
;
771 smmu_writeq(reg64
, cb_base
+ ARM_SMMU_CB_TTBR0
);
776 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
;
777 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
778 if (smmu
->version
> ARM_SMMU_V1
) {
779 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.tcr
>> 32;
780 reg
|= TTBCR2_SEP_UPSTREAM
;
781 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR2
);
784 reg
= pgtbl_cfg
->arm_lpae_s2_cfg
.vtcr
;
785 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_TTBCR
);
788 /* MAIRs (stage-1 only) */
790 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[0];
791 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR0
);
792 reg
= pgtbl_cfg
->arm_lpae_s1_cfg
.mair
[1];
793 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_S1_MAIR1
);
797 reg
= SCTLR_CFCFG
| SCTLR_CFIE
| SCTLR_CFRE
| SCTLR_M
| SCTLR_EAE_SBOP
;
799 reg
|= SCTLR_S1_ASIDPNE
;
803 writel_relaxed(reg
, cb_base
+ ARM_SMMU_CB_SCTLR
);
806 static int arm_smmu_init_domain_context(struct iommu_domain
*domain
,
807 struct arm_smmu_device
*smmu
)
809 int irq
, start
, ret
= 0;
810 unsigned long ias
, oas
;
811 struct io_pgtable_ops
*pgtbl_ops
;
812 struct io_pgtable_cfg pgtbl_cfg
;
813 enum io_pgtable_fmt fmt
;
814 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
815 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
817 mutex_lock(&smmu_domain
->init_mutex
);
818 if (smmu_domain
->smmu
)
822 * Mapping the requested stage onto what we support is surprisingly
823 * complicated, mainly because the spec allows S1+S2 SMMUs without
824 * support for nested translation. That means we end up with the
827 * Requested Supported Actual
837 * Note that you can't actually request stage-2 mappings.
839 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
))
840 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S2
;
841 if (!(smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
))
842 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
844 switch (smmu_domain
->stage
) {
845 case ARM_SMMU_DOMAIN_S1
:
846 cfg
->cbar
= CBAR_TYPE_S1_TRANS_S2_BYPASS
;
847 start
= smmu
->num_s2_context_banks
;
849 oas
= smmu
->ipa_size
;
850 if (IS_ENABLED(CONFIG_64BIT
))
851 fmt
= ARM_64_LPAE_S1
;
853 fmt
= ARM_32_LPAE_S1
;
855 case ARM_SMMU_DOMAIN_NESTED
:
857 * We will likely want to change this if/when KVM gets
860 case ARM_SMMU_DOMAIN_S2
:
861 cfg
->cbar
= CBAR_TYPE_S2_TRANS
;
863 ias
= smmu
->ipa_size
;
865 if (IS_ENABLED(CONFIG_64BIT
))
866 fmt
= ARM_64_LPAE_S2
;
868 fmt
= ARM_32_LPAE_S2
;
875 ret
= __arm_smmu_alloc_bitmap(smmu
->context_map
, start
,
876 smmu
->num_context_banks
);
877 if (IS_ERR_VALUE(ret
))
881 if (smmu
->version
== ARM_SMMU_V1
) {
882 cfg
->irptndx
= atomic_inc_return(&smmu
->irptndx
);
883 cfg
->irptndx
%= smmu
->num_context_irqs
;
885 cfg
->irptndx
= cfg
->cbndx
;
888 pgtbl_cfg
= (struct io_pgtable_cfg
) {
889 .pgsize_bitmap
= arm_smmu_ops
.pgsize_bitmap
,
892 .tlb
= &arm_smmu_gather_ops
,
893 .iommu_dev
= smmu
->dev
,
896 smmu_domain
->smmu
= smmu
;
897 pgtbl_ops
= alloc_io_pgtable_ops(fmt
, &pgtbl_cfg
, smmu_domain
);
903 /* Update our support page sizes to reflect the page table format */
904 arm_smmu_ops
.pgsize_bitmap
= pgtbl_cfg
.pgsize_bitmap
;
906 /* Initialise the context bank with our page table cfg */
907 arm_smmu_init_context_bank(smmu_domain
, &pgtbl_cfg
);
910 * Request context fault interrupt. Do this last to avoid the
911 * handler seeing a half-initialised domain state.
913 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
914 ret
= request_irq(irq
, arm_smmu_context_fault
, IRQF_SHARED
,
915 "arm-smmu-context-fault", domain
);
916 if (IS_ERR_VALUE(ret
)) {
917 dev_err(smmu
->dev
, "failed to request context IRQ %d (%u)\n",
919 cfg
->irptndx
= INVALID_IRPTNDX
;
922 mutex_unlock(&smmu_domain
->init_mutex
);
924 /* Publish page table ops for map/unmap */
925 smmu_domain
->pgtbl_ops
= pgtbl_ops
;
929 smmu_domain
->smmu
= NULL
;
931 mutex_unlock(&smmu_domain
->init_mutex
);
935 static void arm_smmu_destroy_domain_context(struct iommu_domain
*domain
)
937 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
938 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
939 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
940 void __iomem
*cb_base
;
947 * Disable the context bank and free the page tables before freeing
950 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
951 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
953 if (cfg
->irptndx
!= INVALID_IRPTNDX
) {
954 irq
= smmu
->irqs
[smmu
->num_global_irqs
+ cfg
->irptndx
];
955 free_irq(irq
, domain
);
958 free_io_pgtable_ops(smmu_domain
->pgtbl_ops
);
959 __arm_smmu_free_bitmap(smmu
->context_map
, cfg
->cbndx
);
962 static struct iommu_domain
*arm_smmu_domain_alloc(unsigned type
)
964 struct arm_smmu_domain
*smmu_domain
;
966 if (type
!= IOMMU_DOMAIN_UNMANAGED
)
969 * Allocate the domain and initialise some of its data structures.
970 * We can't really do anything meaningful until we've added a
973 smmu_domain
= kzalloc(sizeof(*smmu_domain
), GFP_KERNEL
);
977 mutex_init(&smmu_domain
->init_mutex
);
978 spin_lock_init(&smmu_domain
->pgtbl_lock
);
980 return &smmu_domain
->domain
;
983 static void arm_smmu_domain_free(struct iommu_domain
*domain
)
985 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
988 * Free the domain resources. We assume that all devices have
989 * already been detached.
991 arm_smmu_destroy_domain_context(domain
);
995 static int arm_smmu_master_configure_smrs(struct arm_smmu_device
*smmu
,
996 struct arm_smmu_master_cfg
*cfg
)
999 struct arm_smmu_smr
*smrs
;
1000 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1002 if (!(smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
))
1008 smrs
= kmalloc_array(cfg
->num_streamids
, sizeof(*smrs
), GFP_KERNEL
);
1010 dev_err(smmu
->dev
, "failed to allocate %d SMRs\n",
1011 cfg
->num_streamids
);
1015 /* Allocate the SMRs on the SMMU */
1016 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1017 int idx
= __arm_smmu_alloc_bitmap(smmu
->smr_map
, 0,
1018 smmu
->num_mapping_groups
);
1019 if (IS_ERR_VALUE(idx
)) {
1020 dev_err(smmu
->dev
, "failed to allocate free SMR\n");
1024 smrs
[i
] = (struct arm_smmu_smr
) {
1026 .mask
= 0, /* We don't currently share SMRs */
1027 .id
= cfg
->streamids
[i
],
1031 /* It worked! Now, poke the actual hardware */
1032 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1033 u32 reg
= SMR_VALID
| smrs
[i
].id
<< SMR_ID_SHIFT
|
1034 smrs
[i
].mask
<< SMR_MASK_SHIFT
;
1035 writel_relaxed(reg
, gr0_base
+ ARM_SMMU_GR0_SMR(smrs
[i
].idx
));
1043 __arm_smmu_free_bitmap(smmu
->smr_map
, smrs
[i
].idx
);
1048 static void arm_smmu_master_free_smrs(struct arm_smmu_device
*smmu
,
1049 struct arm_smmu_master_cfg
*cfg
)
1052 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1053 struct arm_smmu_smr
*smrs
= cfg
->smrs
;
1058 /* Invalidate the SMRs before freeing back to the allocator */
1059 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1060 u8 idx
= smrs
[i
].idx
;
1062 writel_relaxed(~SMR_VALID
, gr0_base
+ ARM_SMMU_GR0_SMR(idx
));
1063 __arm_smmu_free_bitmap(smmu
->smr_map
, idx
);
1070 static int arm_smmu_domain_add_master(struct arm_smmu_domain
*smmu_domain
,
1071 struct arm_smmu_master_cfg
*cfg
)
1074 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1075 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1077 /* Devices in an IOMMU group may already be configured */
1078 ret
= arm_smmu_master_configure_smrs(smmu
, cfg
);
1080 return ret
== -EEXIST
? 0 : ret
;
1082 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1085 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1086 s2cr
= S2CR_TYPE_TRANS
|
1087 (smmu_domain
->cfg
.cbndx
<< S2CR_CBNDX_SHIFT
);
1088 writel_relaxed(s2cr
, gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1094 static void arm_smmu_domain_remove_master(struct arm_smmu_domain
*smmu_domain
,
1095 struct arm_smmu_master_cfg
*cfg
)
1098 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1099 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1101 /* An IOMMU group is torn down by the first device to be removed */
1102 if ((smmu
->features
& ARM_SMMU_FEAT_STREAM_MATCH
) && !cfg
->smrs
)
1106 * We *must* clear the S2CR first, because freeing the SMR means
1107 * that it can be re-allocated immediately.
1109 for (i
= 0; i
< cfg
->num_streamids
; ++i
) {
1110 u32 idx
= cfg
->smrs
? cfg
->smrs
[i
].idx
: cfg
->streamids
[i
];
1112 writel_relaxed(S2CR_TYPE_BYPASS
,
1113 gr0_base
+ ARM_SMMU_GR0_S2CR(idx
));
1116 arm_smmu_master_free_smrs(smmu
, cfg
);
1119 static int arm_smmu_attach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1122 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1123 struct arm_smmu_device
*smmu
;
1124 struct arm_smmu_master_cfg
*cfg
;
1126 smmu
= find_smmu_for_device(dev
);
1128 dev_err(dev
, "cannot attach to SMMU, is it on the same bus?\n");
1132 if (dev
->archdata
.iommu
) {
1133 dev_err(dev
, "already attached to IOMMU domain\n");
1137 /* Ensure that the domain is finalised */
1138 ret
= arm_smmu_init_domain_context(domain
, smmu
);
1139 if (IS_ERR_VALUE(ret
))
1143 * Sanity check the domain. We don't support domains across
1146 if (smmu_domain
->smmu
!= smmu
) {
1148 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1149 dev_name(smmu_domain
->smmu
->dev
), dev_name(smmu
->dev
));
1153 /* Looks ok, so add the device to the domain */
1154 cfg
= find_smmu_master_cfg(dev
);
1158 ret
= arm_smmu_domain_add_master(smmu_domain
, cfg
);
1160 dev
->archdata
.iommu
= domain
;
1164 static void arm_smmu_detach_dev(struct iommu_domain
*domain
, struct device
*dev
)
1166 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1167 struct arm_smmu_master_cfg
*cfg
;
1169 cfg
= find_smmu_master_cfg(dev
);
1173 dev
->archdata
.iommu
= NULL
;
1174 arm_smmu_domain_remove_master(smmu_domain
, cfg
);
1177 static int arm_smmu_map(struct iommu_domain
*domain
, unsigned long iova
,
1178 phys_addr_t paddr
, size_t size
, int prot
)
1181 unsigned long flags
;
1182 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1183 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1188 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1189 ret
= ops
->map(ops
, iova
, paddr
, size
, prot
);
1190 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1194 static size_t arm_smmu_unmap(struct iommu_domain
*domain
, unsigned long iova
,
1198 unsigned long flags
;
1199 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1200 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1205 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1206 ret
= ops
->unmap(ops
, iova
, size
);
1207 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1211 static phys_addr_t
arm_smmu_iova_to_phys_hard(struct iommu_domain
*domain
,
1214 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1215 struct arm_smmu_device
*smmu
= smmu_domain
->smmu
;
1216 struct arm_smmu_cfg
*cfg
= &smmu_domain
->cfg
;
1217 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1218 struct device
*dev
= smmu
->dev
;
1219 void __iomem
*cb_base
;
1224 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, cfg
->cbndx
);
1226 /* ATS1 registers can only be written atomically */
1227 va
= iova
& ~0xfffUL
;
1228 if (smmu
->version
== ARM_SMMU_V2
)
1229 smmu_writeq(va
, cb_base
+ ARM_SMMU_CB_ATS1PR
);
1231 writel_relaxed(va
, cb_base
+ ARM_SMMU_CB_ATS1PR
);
1233 if (readl_poll_timeout_atomic(cb_base
+ ARM_SMMU_CB_ATSR
, tmp
,
1234 !(tmp
& ATSR_ACTIVE
), 5, 50)) {
1236 "iova to phys timed out on %pad. Falling back to software table walk.\n",
1238 return ops
->iova_to_phys(ops
, iova
);
1241 phys
= readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_LO
);
1242 phys
|= ((u64
)readl_relaxed(cb_base
+ ARM_SMMU_CB_PAR_HI
)) << 32;
1244 if (phys
& CB_PAR_F
) {
1245 dev_err(dev
, "translation fault!\n");
1246 dev_err(dev
, "PAR = 0x%llx\n", phys
);
1250 return (phys
& GENMASK_ULL(39, 12)) | (iova
& 0xfff);
1253 static phys_addr_t
arm_smmu_iova_to_phys(struct iommu_domain
*domain
,
1257 unsigned long flags
;
1258 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1259 struct io_pgtable_ops
*ops
= smmu_domain
->pgtbl_ops
;
1264 spin_lock_irqsave(&smmu_domain
->pgtbl_lock
, flags
);
1265 if (smmu_domain
->smmu
->features
& ARM_SMMU_FEAT_TRANS_OPS
&&
1266 smmu_domain
->stage
== ARM_SMMU_DOMAIN_S1
) {
1267 ret
= arm_smmu_iova_to_phys_hard(domain
, iova
);
1269 ret
= ops
->iova_to_phys(ops
, iova
);
1272 spin_unlock_irqrestore(&smmu_domain
->pgtbl_lock
, flags
);
1277 static bool arm_smmu_capable(enum iommu_cap cap
)
1280 case IOMMU_CAP_CACHE_COHERENCY
:
1282 * Return true here as the SMMU can always send out coherent
1286 case IOMMU_CAP_INTR_REMAP
:
1287 return true; /* MSIs are just memory writes */
1288 case IOMMU_CAP_NOEXEC
:
1295 static int __arm_smmu_get_pci_sid(struct pci_dev
*pdev
, u16 alias
, void *data
)
1297 *((u16
*)data
) = alias
;
1298 return 0; /* Continue walking */
1301 static void __arm_smmu_release_pci_iommudata(void *data
)
1306 static int arm_smmu_init_pci_device(struct pci_dev
*pdev
,
1307 struct iommu_group
*group
)
1309 struct arm_smmu_master_cfg
*cfg
;
1313 cfg
= iommu_group_get_iommudata(group
);
1315 cfg
= kzalloc(sizeof(*cfg
), GFP_KERNEL
);
1319 iommu_group_set_iommudata(group
, cfg
,
1320 __arm_smmu_release_pci_iommudata
);
1323 if (cfg
->num_streamids
>= MAX_MASTER_STREAMIDS
)
1327 * Assume Stream ID == Requester ID for now.
1328 * We need a way to describe the ID mappings in FDT.
1330 pci_for_each_dma_alias(pdev
, __arm_smmu_get_pci_sid
, &sid
);
1331 for (i
= 0; i
< cfg
->num_streamids
; ++i
)
1332 if (cfg
->streamids
[i
] == sid
)
1335 /* Avoid duplicate SIDs, as this can lead to SMR conflicts */
1336 if (i
== cfg
->num_streamids
)
1337 cfg
->streamids
[cfg
->num_streamids
++] = sid
;
1342 static int arm_smmu_init_platform_device(struct device
*dev
,
1343 struct iommu_group
*group
)
1345 struct arm_smmu_device
*smmu
= find_smmu_for_device(dev
);
1346 struct arm_smmu_master
*master
;
1351 master
= find_smmu_master(smmu
, dev
->of_node
);
1355 iommu_group_set_iommudata(group
, &master
->cfg
, NULL
);
1360 static int arm_smmu_add_device(struct device
*dev
)
1362 struct iommu_group
*group
;
1364 group
= iommu_group_get_for_dev(dev
);
1366 return PTR_ERR(group
);
1368 iommu_group_put(group
);
1372 static void arm_smmu_remove_device(struct device
*dev
)
1374 iommu_group_remove_device(dev
);
1377 static struct iommu_group
*arm_smmu_device_group(struct device
*dev
)
1379 struct iommu_group
*group
;
1382 if (dev_is_pci(dev
))
1383 group
= pci_device_group(dev
);
1385 group
= generic_device_group(dev
);
1390 if (dev_is_pci(dev
))
1391 ret
= arm_smmu_init_pci_device(to_pci_dev(dev
), group
);
1393 ret
= arm_smmu_init_platform_device(dev
, group
);
1396 iommu_group_put(group
);
1397 group
= ERR_PTR(ret
);
1403 static int arm_smmu_domain_get_attr(struct iommu_domain
*domain
,
1404 enum iommu_attr attr
, void *data
)
1406 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1409 case DOMAIN_ATTR_NESTING
:
1410 *(int *)data
= (smmu_domain
->stage
== ARM_SMMU_DOMAIN_NESTED
);
1417 static int arm_smmu_domain_set_attr(struct iommu_domain
*domain
,
1418 enum iommu_attr attr
, void *data
)
1421 struct arm_smmu_domain
*smmu_domain
= to_smmu_domain(domain
);
1423 mutex_lock(&smmu_domain
->init_mutex
);
1426 case DOMAIN_ATTR_NESTING
:
1427 if (smmu_domain
->smmu
) {
1433 smmu_domain
->stage
= ARM_SMMU_DOMAIN_NESTED
;
1435 smmu_domain
->stage
= ARM_SMMU_DOMAIN_S1
;
1443 mutex_unlock(&smmu_domain
->init_mutex
);
1447 static struct iommu_ops arm_smmu_ops
= {
1448 .capable
= arm_smmu_capable
,
1449 .domain_alloc
= arm_smmu_domain_alloc
,
1450 .domain_free
= arm_smmu_domain_free
,
1451 .attach_dev
= arm_smmu_attach_dev
,
1452 .detach_dev
= arm_smmu_detach_dev
,
1453 .map
= arm_smmu_map
,
1454 .unmap
= arm_smmu_unmap
,
1455 .map_sg
= default_iommu_map_sg
,
1456 .iova_to_phys
= arm_smmu_iova_to_phys
,
1457 .add_device
= arm_smmu_add_device
,
1458 .remove_device
= arm_smmu_remove_device
,
1459 .device_group
= arm_smmu_device_group
,
1460 .domain_get_attr
= arm_smmu_domain_get_attr
,
1461 .domain_set_attr
= arm_smmu_domain_set_attr
,
1462 .pgsize_bitmap
= -1UL, /* Restricted during device attach */
1465 static void arm_smmu_device_reset(struct arm_smmu_device
*smmu
)
1467 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1468 void __iomem
*cb_base
;
1472 /* clear global FSR */
1473 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1474 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sGFSR
);
1476 /* Mark all SMRn as invalid and all S2CRn as bypass */
1477 for (i
= 0; i
< smmu
->num_mapping_groups
; ++i
) {
1478 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_SMR(i
));
1479 writel_relaxed(S2CR_TYPE_BYPASS
,
1480 gr0_base
+ ARM_SMMU_GR0_S2CR(i
));
1483 /* Make sure all context banks are disabled and clear CB_FSR */
1484 for (i
= 0; i
< smmu
->num_context_banks
; ++i
) {
1485 cb_base
= ARM_SMMU_CB_BASE(smmu
) + ARM_SMMU_CB(smmu
, i
);
1486 writel_relaxed(0, cb_base
+ ARM_SMMU_CB_SCTLR
);
1487 writel_relaxed(FSR_FAULT
, cb_base
+ ARM_SMMU_CB_FSR
);
1490 /* Invalidate the TLB, just in case */
1491 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLH
);
1492 writel_relaxed(0, gr0_base
+ ARM_SMMU_GR0_TLBIALLNSNH
);
1494 reg
= readl_relaxed(ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1496 /* Enable fault reporting */
1497 reg
|= (sCR0_GFRE
| sCR0_GFIE
| sCR0_GCFGFRE
| sCR0_GCFGFIE
);
1499 /* Disable TLB broadcasting. */
1500 reg
|= (sCR0_VMIDPNE
| sCR0_PTM
);
1502 /* Enable client access, but bypass when no mapping is found */
1503 reg
&= ~(sCR0_CLIENTPD
| sCR0_USFCFG
);
1505 /* Disable forced broadcasting */
1508 /* Don't upgrade barriers */
1509 reg
&= ~(sCR0_BSU_MASK
<< sCR0_BSU_SHIFT
);
1511 /* Push the button */
1512 __arm_smmu_tlb_sync(smmu
);
1513 writel(reg
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1516 static int arm_smmu_id_size_to_bits(int size
)
1535 static int arm_smmu_device_cfg_probe(struct arm_smmu_device
*smmu
)
1538 void __iomem
*gr0_base
= ARM_SMMU_GR0(smmu
);
1540 bool cttw_dt
, cttw_reg
;
1542 dev_notice(smmu
->dev
, "probing hardware configuration...\n");
1543 dev_notice(smmu
->dev
, "SMMUv%d with:\n", smmu
->version
);
1546 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID0
);
1548 /* Restrict available stages based on module parameter */
1549 if (force_stage
== 1)
1550 id
&= ~(ID0_S2TS
| ID0_NTS
);
1551 else if (force_stage
== 2)
1552 id
&= ~(ID0_S1TS
| ID0_NTS
);
1554 if (id
& ID0_S1TS
) {
1555 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S1
;
1556 dev_notice(smmu
->dev
, "\tstage 1 translation\n");
1559 if (id
& ID0_S2TS
) {
1560 smmu
->features
|= ARM_SMMU_FEAT_TRANS_S2
;
1561 dev_notice(smmu
->dev
, "\tstage 2 translation\n");
1565 smmu
->features
|= ARM_SMMU_FEAT_TRANS_NESTED
;
1566 dev_notice(smmu
->dev
, "\tnested translation\n");
1569 if (!(smmu
->features
&
1570 (ARM_SMMU_FEAT_TRANS_S1
| ARM_SMMU_FEAT_TRANS_S2
))) {
1571 dev_err(smmu
->dev
, "\tno translation support!\n");
1575 if ((id
& ID0_S1TS
) && ((smmu
->version
== 1) || !(id
& ID0_ATOSNS
))) {
1576 smmu
->features
|= ARM_SMMU_FEAT_TRANS_OPS
;
1577 dev_notice(smmu
->dev
, "\taddress translation ops\n");
1581 * In order for DMA API calls to work properly, we must defer to what
1582 * the DT says about coherency, regardless of what the hardware claims.
1583 * Fortunately, this also opens up a workaround for systems where the
1584 * ID register value has ended up configured incorrectly.
1586 cttw_dt
= of_dma_is_coherent(smmu
->dev
->of_node
);
1587 cttw_reg
= !!(id
& ID0_CTTW
);
1589 smmu
->features
|= ARM_SMMU_FEAT_COHERENT_WALK
;
1590 if (cttw_dt
|| cttw_reg
)
1591 dev_notice(smmu
->dev
, "\t%scoherent table walk\n",
1592 cttw_dt
? "" : "non-");
1593 if (cttw_dt
!= cttw_reg
)
1594 dev_notice(smmu
->dev
,
1595 "\t(IDR0.CTTW overridden by dma-coherent property)\n");
1600 smmu
->features
|= ARM_SMMU_FEAT_STREAM_MATCH
;
1601 smmu
->num_mapping_groups
= (id
>> ID0_NUMSMRG_SHIFT
) &
1603 if (smmu
->num_mapping_groups
== 0) {
1605 "stream-matching supported, but no SMRs present!\n");
1609 smr
= SMR_MASK_MASK
<< SMR_MASK_SHIFT
;
1610 smr
|= (SMR_ID_MASK
<< SMR_ID_SHIFT
);
1611 writel_relaxed(smr
, gr0_base
+ ARM_SMMU_GR0_SMR(0));
1612 smr
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_SMR(0));
1614 mask
= (smr
>> SMR_MASK_SHIFT
) & SMR_MASK_MASK
;
1615 sid
= (smr
>> SMR_ID_SHIFT
) & SMR_ID_MASK
;
1616 if ((mask
& sid
) != sid
) {
1618 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1623 dev_notice(smmu
->dev
,
1624 "\tstream matching with %u register groups, mask 0x%x",
1625 smmu
->num_mapping_groups
, mask
);
1627 smmu
->num_mapping_groups
= (id
>> ID0_NUMSIDB_SHIFT
) &
1632 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID1
);
1633 smmu
->pgshift
= (id
& ID1_PAGESIZE
) ? 16 : 12;
1635 /* Check for size mismatch of SMMU address space from mapped region */
1636 size
= 1 << (((id
>> ID1_NUMPAGENDXB_SHIFT
) & ID1_NUMPAGENDXB_MASK
) + 1);
1637 size
*= 2 << smmu
->pgshift
;
1638 if (smmu
->size
!= size
)
1640 "SMMU address space size (0x%lx) differs from mapped region size (0x%lx)!\n",
1643 smmu
->num_s2_context_banks
= (id
>> ID1_NUMS2CB_SHIFT
) & ID1_NUMS2CB_MASK
;
1644 smmu
->num_context_banks
= (id
>> ID1_NUMCB_SHIFT
) & ID1_NUMCB_MASK
;
1645 if (smmu
->num_s2_context_banks
> smmu
->num_context_banks
) {
1646 dev_err(smmu
->dev
, "impossible number of S2 context banks!\n");
1649 dev_notice(smmu
->dev
, "\t%u context banks (%u stage-2 only)\n",
1650 smmu
->num_context_banks
, smmu
->num_s2_context_banks
);
1653 id
= readl_relaxed(gr0_base
+ ARM_SMMU_GR0_ID2
);
1654 size
= arm_smmu_id_size_to_bits((id
>> ID2_IAS_SHIFT
) & ID2_IAS_MASK
);
1655 smmu
->ipa_size
= size
;
1657 /* The output mask is also applied for bypass */
1658 size
= arm_smmu_id_size_to_bits((id
>> ID2_OAS_SHIFT
) & ID2_OAS_MASK
);
1659 smmu
->pa_size
= size
;
1662 * What the page table walker can address actually depends on which
1663 * descriptor format is in use, but since a) we don't know that yet,
1664 * and b) it can vary per context bank, this will have to do...
1666 if (dma_set_mask_and_coherent(smmu
->dev
, DMA_BIT_MASK(size
)))
1668 "failed to set DMA mask for table walker\n");
1670 if (smmu
->version
== ARM_SMMU_V1
) {
1671 smmu
->va_size
= smmu
->ipa_size
;
1672 size
= SZ_4K
| SZ_2M
| SZ_1G
;
1674 size
= (id
>> ID2_UBS_SHIFT
) & ID2_UBS_MASK
;
1675 smmu
->va_size
= arm_smmu_id_size_to_bits(size
);
1676 #ifndef CONFIG_64BIT
1677 smmu
->va_size
= min(32UL, smmu
->va_size
);
1680 if (id
& ID2_PTFS_4K
)
1681 size
|= SZ_4K
| SZ_2M
| SZ_1G
;
1682 if (id
& ID2_PTFS_16K
)
1683 size
|= SZ_16K
| SZ_32M
;
1684 if (id
& ID2_PTFS_64K
)
1685 size
|= SZ_64K
| SZ_512M
;
1688 arm_smmu_ops
.pgsize_bitmap
&= size
;
1689 dev_notice(smmu
->dev
, "\tSupported page sizes: 0x%08lx\n", size
);
1691 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S1
)
1692 dev_notice(smmu
->dev
, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n",
1693 smmu
->va_size
, smmu
->ipa_size
);
1695 if (smmu
->features
& ARM_SMMU_FEAT_TRANS_S2
)
1696 dev_notice(smmu
->dev
, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n",
1697 smmu
->ipa_size
, smmu
->pa_size
);
1702 static const struct of_device_id arm_smmu_of_match
[] = {
1703 { .compatible
= "arm,smmu-v1", .data
= (void *)ARM_SMMU_V1
},
1704 { .compatible
= "arm,smmu-v2", .data
= (void *)ARM_SMMU_V2
},
1705 { .compatible
= "arm,mmu-400", .data
= (void *)ARM_SMMU_V1
},
1706 { .compatible
= "arm,mmu-401", .data
= (void *)ARM_SMMU_V1
},
1707 { .compatible
= "arm,mmu-500", .data
= (void *)ARM_SMMU_V2
},
1710 MODULE_DEVICE_TABLE(of
, arm_smmu_of_match
);
1712 static int arm_smmu_device_dt_probe(struct platform_device
*pdev
)
1714 const struct of_device_id
*of_id
;
1715 struct resource
*res
;
1716 struct arm_smmu_device
*smmu
;
1717 struct device
*dev
= &pdev
->dev
;
1718 struct rb_node
*node
;
1719 struct of_phandle_args masterspec
;
1720 int num_irqs
, i
, err
;
1722 smmu
= devm_kzalloc(dev
, sizeof(*smmu
), GFP_KERNEL
);
1724 dev_err(dev
, "failed to allocate arm_smmu_device\n");
1729 of_id
= of_match_node(arm_smmu_of_match
, dev
->of_node
);
1730 smmu
->version
= (enum arm_smmu_arch_version
)of_id
->data
;
1732 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
1733 smmu
->base
= devm_ioremap_resource(dev
, res
);
1734 if (IS_ERR(smmu
->base
))
1735 return PTR_ERR(smmu
->base
);
1736 smmu
->size
= resource_size(res
);
1738 if (of_property_read_u32(dev
->of_node
, "#global-interrupts",
1739 &smmu
->num_global_irqs
)) {
1740 dev_err(dev
, "missing #global-interrupts property\n");
1745 while ((res
= platform_get_resource(pdev
, IORESOURCE_IRQ
, num_irqs
))) {
1747 if (num_irqs
> smmu
->num_global_irqs
)
1748 smmu
->num_context_irqs
++;
1751 if (!smmu
->num_context_irqs
) {
1752 dev_err(dev
, "found %d interrupts but expected at least %d\n",
1753 num_irqs
, smmu
->num_global_irqs
+ 1);
1757 smmu
->irqs
= devm_kzalloc(dev
, sizeof(*smmu
->irqs
) * num_irqs
,
1760 dev_err(dev
, "failed to allocate %d irqs\n", num_irqs
);
1764 for (i
= 0; i
< num_irqs
; ++i
) {
1765 int irq
= platform_get_irq(pdev
, i
);
1768 dev_err(dev
, "failed to get irq index %d\n", i
);
1771 smmu
->irqs
[i
] = irq
;
1774 err
= arm_smmu_device_cfg_probe(smmu
);
1779 smmu
->masters
= RB_ROOT
;
1780 while (!of_parse_phandle_with_args(dev
->of_node
, "mmu-masters",
1781 "#stream-id-cells", i
,
1783 err
= register_smmu_master(smmu
, dev
, &masterspec
);
1785 dev_err(dev
, "failed to add master %s\n",
1786 masterspec
.np
->name
);
1787 goto out_put_masters
;
1792 dev_notice(dev
, "registered %d master devices\n", i
);
1794 parse_driver_options(smmu
);
1796 if (smmu
->version
> ARM_SMMU_V1
&&
1797 smmu
->num_context_banks
!= smmu
->num_context_irqs
) {
1799 "found only %d context interrupt(s) but %d required\n",
1800 smmu
->num_context_irqs
, smmu
->num_context_banks
);
1802 goto out_put_masters
;
1805 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
) {
1806 err
= request_irq(smmu
->irqs
[i
],
1807 arm_smmu_global_fault
,
1809 "arm-smmu global fault",
1812 dev_err(dev
, "failed to request global IRQ %d (%u)\n",
1818 INIT_LIST_HEAD(&smmu
->list
);
1819 spin_lock(&arm_smmu_devices_lock
);
1820 list_add(&smmu
->list
, &arm_smmu_devices
);
1821 spin_unlock(&arm_smmu_devices_lock
);
1823 arm_smmu_device_reset(smmu
);
1828 free_irq(smmu
->irqs
[i
], smmu
);
1831 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1832 struct arm_smmu_master
*master
1833 = container_of(node
, struct arm_smmu_master
, node
);
1834 of_node_put(master
->of_node
);
1840 static int arm_smmu_device_remove(struct platform_device
*pdev
)
1843 struct device
*dev
= &pdev
->dev
;
1844 struct arm_smmu_device
*curr
, *smmu
= NULL
;
1845 struct rb_node
*node
;
1847 spin_lock(&arm_smmu_devices_lock
);
1848 list_for_each_entry(curr
, &arm_smmu_devices
, list
) {
1849 if (curr
->dev
== dev
) {
1851 list_del(&smmu
->list
);
1855 spin_unlock(&arm_smmu_devices_lock
);
1860 for (node
= rb_first(&smmu
->masters
); node
; node
= rb_next(node
)) {
1861 struct arm_smmu_master
*master
1862 = container_of(node
, struct arm_smmu_master
, node
);
1863 of_node_put(master
->of_node
);
1866 if (!bitmap_empty(smmu
->context_map
, ARM_SMMU_MAX_CBS
))
1867 dev_err(dev
, "removing device with active domains!\n");
1869 for (i
= 0; i
< smmu
->num_global_irqs
; ++i
)
1870 free_irq(smmu
->irqs
[i
], smmu
);
1872 /* Turn the thing off */
1873 writel(sCR0_CLIENTPD
, ARM_SMMU_GR0_NS(smmu
) + ARM_SMMU_GR0_sCR0
);
1877 static struct platform_driver arm_smmu_driver
= {
1880 .of_match_table
= of_match_ptr(arm_smmu_of_match
),
1882 .probe
= arm_smmu_device_dt_probe
,
1883 .remove
= arm_smmu_device_remove
,
1886 static int __init
arm_smmu_init(void)
1888 struct device_node
*np
;
1892 * Play nice with systems that don't have an ARM SMMU by checking that
1893 * an ARM SMMU exists in the system before proceeding with the driver
1894 * and IOMMU bus operation registration.
1896 np
= of_find_matching_node(NULL
, arm_smmu_of_match
);
1902 ret
= platform_driver_register(&arm_smmu_driver
);
1906 /* Oh, for a proper bus abstraction */
1907 if (!iommu_present(&platform_bus_type
))
1908 bus_set_iommu(&platform_bus_type
, &arm_smmu_ops
);
1910 #ifdef CONFIG_ARM_AMBA
1911 if (!iommu_present(&amba_bustype
))
1912 bus_set_iommu(&amba_bustype
, &arm_smmu_ops
);
1916 if (!iommu_present(&pci_bus_type
))
1917 bus_set_iommu(&pci_bus_type
, &arm_smmu_ops
);
1923 static void __exit
arm_smmu_exit(void)
1925 return platform_driver_unregister(&arm_smmu_driver
);
1928 subsys_initcall(arm_smmu_init
);
1929 module_exit(arm_smmu_exit
);
1931 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1932 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1933 MODULE_LICENSE("GPL v2");