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iommu/arm-smmu: Tighten up global fault reporting
[mirror_ubuntu-artful-kernel.git] / drivers / iommu / arm-smmu.c
1 /*
2 * IOMMU API for ARM architected SMMU implementations.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
16 *
17 * Copyright (C) 2013 ARM Limited
18 *
19 * Author: Will Deacon <will.deacon@arm.com>
20 *
21 * This driver currently supports:
22 * - SMMUv1 and v2 implementations
23 * - Stream-matching and stream-indexing
24 * - v7/v8 long-descriptor format
25 * - Non-secure access to the SMMU
26 * - 4k and 64k pages, with contiguous pte hints.
27 * - Up to 39-bit addressing
28 * - Context fault reporting
29 */
30
31 #define pr_fmt(fmt) "arm-smmu: " fmt
32
33 #include <linux/delay.h>
34 #include <linux/dma-mapping.h>
35 #include <linux/err.h>
36 #include <linux/interrupt.h>
37 #include <linux/io.h>
38 #include <linux/iommu.h>
39 #include <linux/mm.h>
40 #include <linux/module.h>
41 #include <linux/of.h>
42 #include <linux/platform_device.h>
43 #include <linux/slab.h>
44 #include <linux/spinlock.h>
45
46 #include <linux/amba/bus.h>
47
48 #include <asm/pgalloc.h>
49
50 /* Maximum number of stream IDs assigned to a single device */
51 #define MAX_MASTER_STREAMIDS 8
52
53 /* Maximum number of context banks per SMMU */
54 #define ARM_SMMU_MAX_CBS 128
55
56 /* Maximum number of mapping groups per SMMU */
57 #define ARM_SMMU_MAX_SMRS 128
58
59 /* Number of VMIDs per SMMU */
60 #define ARM_SMMU_NUM_VMIDS 256
61
62 /* SMMU global address space */
63 #define ARM_SMMU_GR0(smmu) ((smmu)->base)
64 #define ARM_SMMU_GR1(smmu) ((smmu)->base + (smmu)->pagesize)
65
66 /* Page table bits */
67 #define ARM_SMMU_PTE_PAGE (((pteval_t)3) << 0)
68 #define ARM_SMMU_PTE_CONT (((pteval_t)1) << 52)
69 #define ARM_SMMU_PTE_AF (((pteval_t)1) << 10)
70 #define ARM_SMMU_PTE_SH_NS (((pteval_t)0) << 8)
71 #define ARM_SMMU_PTE_SH_OS (((pteval_t)2) << 8)
72 #define ARM_SMMU_PTE_SH_IS (((pteval_t)3) << 8)
73
74 #if PAGE_SIZE == SZ_4K
75 #define ARM_SMMU_PTE_CONT_ENTRIES 16
76 #elif PAGE_SIZE == SZ_64K
77 #define ARM_SMMU_PTE_CONT_ENTRIES 32
78 #else
79 #define ARM_SMMU_PTE_CONT_ENTRIES 1
80 #endif
81
82 #define ARM_SMMU_PTE_CONT_SIZE (PAGE_SIZE * ARM_SMMU_PTE_CONT_ENTRIES)
83 #define ARM_SMMU_PTE_CONT_MASK (~(ARM_SMMU_PTE_CONT_SIZE - 1))
84 #define ARM_SMMU_PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(pte_t))
85
86 /* Stage-1 PTE */
87 #define ARM_SMMU_PTE_AP_UNPRIV (((pteval_t)1) << 6)
88 #define ARM_SMMU_PTE_AP_RDONLY (((pteval_t)2) << 6)
89 #define ARM_SMMU_PTE_ATTRINDX_SHIFT 2
90
91 /* Stage-2 PTE */
92 #define ARM_SMMU_PTE_HAP_FAULT (((pteval_t)0) << 6)
93 #define ARM_SMMU_PTE_HAP_READ (((pteval_t)1) << 6)
94 #define ARM_SMMU_PTE_HAP_WRITE (((pteval_t)2) << 6)
95 #define ARM_SMMU_PTE_MEMATTR_OIWB (((pteval_t)0xf) << 2)
96 #define ARM_SMMU_PTE_MEMATTR_NC (((pteval_t)0x5) << 2)
97 #define ARM_SMMU_PTE_MEMATTR_DEV (((pteval_t)0x1) << 2)
98
99 /* Configuration registers */
100 #define ARM_SMMU_GR0_sCR0 0x0
101 #define sCR0_CLIENTPD (1 << 0)
102 #define sCR0_GFRE (1 << 1)
103 #define sCR0_GFIE (1 << 2)
104 #define sCR0_GCFGFRE (1 << 4)
105 #define sCR0_GCFGFIE (1 << 5)
106 #define sCR0_USFCFG (1 << 10)
107 #define sCR0_VMIDPNE (1 << 11)
108 #define sCR0_PTM (1 << 12)
109 #define sCR0_FB (1 << 13)
110 #define sCR0_BSU_SHIFT 14
111 #define sCR0_BSU_MASK 0x3
112
113 /* Identification registers */
114 #define ARM_SMMU_GR0_ID0 0x20
115 #define ARM_SMMU_GR0_ID1 0x24
116 #define ARM_SMMU_GR0_ID2 0x28
117 #define ARM_SMMU_GR0_ID3 0x2c
118 #define ARM_SMMU_GR0_ID4 0x30
119 #define ARM_SMMU_GR0_ID5 0x34
120 #define ARM_SMMU_GR0_ID6 0x38
121 #define ARM_SMMU_GR0_ID7 0x3c
122 #define ARM_SMMU_GR0_sGFSR 0x48
123 #define ARM_SMMU_GR0_sGFSYNR0 0x50
124 #define ARM_SMMU_GR0_sGFSYNR1 0x54
125 #define ARM_SMMU_GR0_sGFSYNR2 0x58
126 #define ARM_SMMU_GR0_PIDR0 0xfe0
127 #define ARM_SMMU_GR0_PIDR1 0xfe4
128 #define ARM_SMMU_GR0_PIDR2 0xfe8
129
130 #define ID0_S1TS (1 << 30)
131 #define ID0_S2TS (1 << 29)
132 #define ID0_NTS (1 << 28)
133 #define ID0_SMS (1 << 27)
134 #define ID0_PTFS_SHIFT 24
135 #define ID0_PTFS_MASK 0x2
136 #define ID0_PTFS_V8_ONLY 0x2
137 #define ID0_CTTW (1 << 14)
138 #define ID0_NUMIRPT_SHIFT 16
139 #define ID0_NUMIRPT_MASK 0xff
140 #define ID0_NUMSMRG_SHIFT 0
141 #define ID0_NUMSMRG_MASK 0xff
142
143 #define ID1_PAGESIZE (1 << 31)
144 #define ID1_NUMPAGENDXB_SHIFT 28
145 #define ID1_NUMPAGENDXB_MASK 7
146 #define ID1_NUMS2CB_SHIFT 16
147 #define ID1_NUMS2CB_MASK 0xff
148 #define ID1_NUMCB_SHIFT 0
149 #define ID1_NUMCB_MASK 0xff
150
151 #define ID2_OAS_SHIFT 4
152 #define ID2_OAS_MASK 0xf
153 #define ID2_IAS_SHIFT 0
154 #define ID2_IAS_MASK 0xf
155 #define ID2_UBS_SHIFT 8
156 #define ID2_UBS_MASK 0xf
157 #define ID2_PTFS_4K (1 << 12)
158 #define ID2_PTFS_16K (1 << 13)
159 #define ID2_PTFS_64K (1 << 14)
160
161 #define PIDR2_ARCH_SHIFT 4
162 #define PIDR2_ARCH_MASK 0xf
163
164 /* Global TLB invalidation */
165 #define ARM_SMMU_GR0_STLBIALL 0x60
166 #define ARM_SMMU_GR0_TLBIVMID 0x64
167 #define ARM_SMMU_GR0_TLBIALLNSNH 0x68
168 #define ARM_SMMU_GR0_TLBIALLH 0x6c
169 #define ARM_SMMU_GR0_sTLBGSYNC 0x70
170 #define ARM_SMMU_GR0_sTLBGSTATUS 0x74
171 #define sTLBGSTATUS_GSACTIVE (1 << 0)
172 #define TLB_LOOP_TIMEOUT 1000000 /* 1s! */
173
174 /* Stream mapping registers */
175 #define ARM_SMMU_GR0_SMR(n) (0x800 + ((n) << 2))
176 #define SMR_VALID (1 << 31)
177 #define SMR_MASK_SHIFT 16
178 #define SMR_MASK_MASK 0x7fff
179 #define SMR_ID_SHIFT 0
180 #define SMR_ID_MASK 0x7fff
181
182 #define ARM_SMMU_GR0_S2CR(n) (0xc00 + ((n) << 2))
183 #define S2CR_CBNDX_SHIFT 0
184 #define S2CR_CBNDX_MASK 0xff
185 #define S2CR_TYPE_SHIFT 16
186 #define S2CR_TYPE_MASK 0x3
187 #define S2CR_TYPE_TRANS (0 << S2CR_TYPE_SHIFT)
188 #define S2CR_TYPE_BYPASS (1 << S2CR_TYPE_SHIFT)
189 #define S2CR_TYPE_FAULT (2 << S2CR_TYPE_SHIFT)
190
191 /* Context bank attribute registers */
192 #define ARM_SMMU_GR1_CBAR(n) (0x0 + ((n) << 2))
193 #define CBAR_VMID_SHIFT 0
194 #define CBAR_VMID_MASK 0xff
195 #define CBAR_S1_MEMATTR_SHIFT 12
196 #define CBAR_S1_MEMATTR_MASK 0xf
197 #define CBAR_S1_MEMATTR_WB 0xf
198 #define CBAR_TYPE_SHIFT 16
199 #define CBAR_TYPE_MASK 0x3
200 #define CBAR_TYPE_S2_TRANS (0 << CBAR_TYPE_SHIFT)
201 #define CBAR_TYPE_S1_TRANS_S2_BYPASS (1 << CBAR_TYPE_SHIFT)
202 #define CBAR_TYPE_S1_TRANS_S2_FAULT (2 << CBAR_TYPE_SHIFT)
203 #define CBAR_TYPE_S1_TRANS_S2_TRANS (3 << CBAR_TYPE_SHIFT)
204 #define CBAR_IRPTNDX_SHIFT 24
205 #define CBAR_IRPTNDX_MASK 0xff
206
207 #define ARM_SMMU_GR1_CBA2R(n) (0x800 + ((n) << 2))
208 #define CBA2R_RW64_32BIT (0 << 0)
209 #define CBA2R_RW64_64BIT (1 << 0)
210
211 /* Translation context bank */
212 #define ARM_SMMU_CB_BASE(smmu) ((smmu)->base + ((smmu)->size >> 1))
213 #define ARM_SMMU_CB(smmu, n) ((n) * (smmu)->pagesize)
214
215 #define ARM_SMMU_CB_SCTLR 0x0
216 #define ARM_SMMU_CB_RESUME 0x8
217 #define ARM_SMMU_CB_TTBCR2 0x10
218 #define ARM_SMMU_CB_TTBR0_LO 0x20
219 #define ARM_SMMU_CB_TTBR0_HI 0x24
220 #define ARM_SMMU_CB_TTBCR 0x30
221 #define ARM_SMMU_CB_S1_MAIR0 0x38
222 #define ARM_SMMU_CB_FSR 0x58
223 #define ARM_SMMU_CB_FAR_LO 0x60
224 #define ARM_SMMU_CB_FAR_HI 0x64
225 #define ARM_SMMU_CB_FSYNR0 0x68
226
227 #define SCTLR_S1_ASIDPNE (1 << 12)
228 #define SCTLR_CFCFG (1 << 7)
229 #define SCTLR_CFIE (1 << 6)
230 #define SCTLR_CFRE (1 << 5)
231 #define SCTLR_E (1 << 4)
232 #define SCTLR_AFE (1 << 2)
233 #define SCTLR_TRE (1 << 1)
234 #define SCTLR_M (1 << 0)
235 #define SCTLR_EAE_SBOP (SCTLR_AFE | SCTLR_TRE)
236
237 #define RESUME_RETRY (0 << 0)
238 #define RESUME_TERMINATE (1 << 0)
239
240 #define TTBCR_EAE (1 << 31)
241
242 #define TTBCR_PASIZE_SHIFT 16
243 #define TTBCR_PASIZE_MASK 0x7
244
245 #define TTBCR_TG0_4K (0 << 14)
246 #define TTBCR_TG0_64K (1 << 14)
247
248 #define TTBCR_SH0_SHIFT 12
249 #define TTBCR_SH0_MASK 0x3
250 #define TTBCR_SH_NS 0
251 #define TTBCR_SH_OS 2
252 #define TTBCR_SH_IS 3
253
254 #define TTBCR_ORGN0_SHIFT 10
255 #define TTBCR_IRGN0_SHIFT 8
256 #define TTBCR_RGN_MASK 0x3
257 #define TTBCR_RGN_NC 0
258 #define TTBCR_RGN_WBWA 1
259 #define TTBCR_RGN_WT 2
260 #define TTBCR_RGN_WB 3
261
262 #define TTBCR_SL0_SHIFT 6
263 #define TTBCR_SL0_MASK 0x3
264 #define TTBCR_SL0_LVL_2 0
265 #define TTBCR_SL0_LVL_1 1
266
267 #define TTBCR_T1SZ_SHIFT 16
268 #define TTBCR_T0SZ_SHIFT 0
269 #define TTBCR_SZ_MASK 0xf
270
271 #define TTBCR2_SEP_SHIFT 15
272 #define TTBCR2_SEP_MASK 0x7
273
274 #define TTBCR2_PASIZE_SHIFT 0
275 #define TTBCR2_PASIZE_MASK 0x7
276
277 /* Common definitions for PASize and SEP fields */
278 #define TTBCR2_ADDR_32 0
279 #define TTBCR2_ADDR_36 1
280 #define TTBCR2_ADDR_40 2
281 #define TTBCR2_ADDR_42 3
282 #define TTBCR2_ADDR_44 4
283 #define TTBCR2_ADDR_48 5
284
285 #define MAIR_ATTR_SHIFT(n) ((n) << 3)
286 #define MAIR_ATTR_MASK 0xff
287 #define MAIR_ATTR_DEVICE 0x04
288 #define MAIR_ATTR_NC 0x44
289 #define MAIR_ATTR_WBRWA 0xff
290 #define MAIR_ATTR_IDX_NC 0
291 #define MAIR_ATTR_IDX_CACHE 1
292 #define MAIR_ATTR_IDX_DEV 2
293
294 #define FSR_MULTI (1 << 31)
295 #define FSR_SS (1 << 30)
296 #define FSR_UUT (1 << 8)
297 #define FSR_ASF (1 << 7)
298 #define FSR_TLBLKF (1 << 6)
299 #define FSR_TLBMCF (1 << 5)
300 #define FSR_EF (1 << 4)
301 #define FSR_PF (1 << 3)
302 #define FSR_AFF (1 << 2)
303 #define FSR_TF (1 << 1)
304
305 #define FSR_IGN (FSR_AFF | FSR_ASF | FSR_TLBMCF | \
306 FSR_TLBLKF)
307 #define FSR_FAULT (FSR_MULTI | FSR_SS | FSR_UUT | \
308 FSR_EF | FSR_PF | FSR_TF | FSR_IGN)
309
310 #define FSYNR0_WNR (1 << 4)
311
312 struct arm_smmu_smr {
313 u8 idx;
314 u16 mask;
315 u16 id;
316 };
317
318 struct arm_smmu_master {
319 struct device_node *of_node;
320
321 /*
322 * The following is specific to the master's position in the
323 * SMMU chain.
324 */
325 struct rb_node node;
326 int num_streamids;
327 u16 streamids[MAX_MASTER_STREAMIDS];
328
329 /*
330 * We only need to allocate these on the root SMMU, as we
331 * configure unmatched streams to bypass translation.
332 */
333 struct arm_smmu_smr *smrs;
334 };
335
336 struct arm_smmu_device {
337 struct device *dev;
338 struct device_node *parent_of_node;
339
340 void __iomem *base;
341 unsigned long size;
342 unsigned long pagesize;
343
344 #define ARM_SMMU_FEAT_COHERENT_WALK (1 << 0)
345 #define ARM_SMMU_FEAT_STREAM_MATCH (1 << 1)
346 #define ARM_SMMU_FEAT_TRANS_S1 (1 << 2)
347 #define ARM_SMMU_FEAT_TRANS_S2 (1 << 3)
348 #define ARM_SMMU_FEAT_TRANS_NESTED (1 << 4)
349 u32 features;
350 int version;
351
352 u32 num_context_banks;
353 u32 num_s2_context_banks;
354 DECLARE_BITMAP(context_map, ARM_SMMU_MAX_CBS);
355 atomic_t irptndx;
356
357 u32 num_mapping_groups;
358 DECLARE_BITMAP(smr_map, ARM_SMMU_MAX_SMRS);
359
360 unsigned long input_size;
361 unsigned long s1_output_size;
362 unsigned long s2_output_size;
363
364 u32 num_global_irqs;
365 u32 num_context_irqs;
366 unsigned int *irqs;
367
368 DECLARE_BITMAP(vmid_map, ARM_SMMU_NUM_VMIDS);
369
370 struct list_head list;
371 struct rb_root masters;
372 };
373
374 struct arm_smmu_cfg {
375 struct arm_smmu_device *smmu;
376 u8 vmid;
377 u8 cbndx;
378 u8 irptndx;
379 u32 cbar;
380 pgd_t *pgd;
381 };
382
383 struct arm_smmu_domain {
384 /*
385 * A domain can span across multiple, chained SMMUs and requires
386 * all devices within the domain to follow the same translation
387 * path.
388 */
389 struct arm_smmu_device *leaf_smmu;
390 struct arm_smmu_cfg root_cfg;
391 phys_addr_t output_mask;
392
393 spinlock_t lock;
394 };
395
396 static DEFINE_SPINLOCK(arm_smmu_devices_lock);
397 static LIST_HEAD(arm_smmu_devices);
398
399 static struct arm_smmu_master *find_smmu_master(struct arm_smmu_device *smmu,
400 struct device_node *dev_node)
401 {
402 struct rb_node *node = smmu->masters.rb_node;
403
404 while (node) {
405 struct arm_smmu_master *master;
406 master = container_of(node, struct arm_smmu_master, node);
407
408 if (dev_node < master->of_node)
409 node = node->rb_left;
410 else if (dev_node > master->of_node)
411 node = node->rb_right;
412 else
413 return master;
414 }
415
416 return NULL;
417 }
418
419 static int insert_smmu_master(struct arm_smmu_device *smmu,
420 struct arm_smmu_master *master)
421 {
422 struct rb_node **new, *parent;
423
424 new = &smmu->masters.rb_node;
425 parent = NULL;
426 while (*new) {
427 struct arm_smmu_master *this;
428 this = container_of(*new, struct arm_smmu_master, node);
429
430 parent = *new;
431 if (master->of_node < this->of_node)
432 new = &((*new)->rb_left);
433 else if (master->of_node > this->of_node)
434 new = &((*new)->rb_right);
435 else
436 return -EEXIST;
437 }
438
439 rb_link_node(&master->node, parent, new);
440 rb_insert_color(&master->node, &smmu->masters);
441 return 0;
442 }
443
444 static int register_smmu_master(struct arm_smmu_device *smmu,
445 struct device *dev,
446 struct of_phandle_args *masterspec)
447 {
448 int i;
449 struct arm_smmu_master *master;
450
451 master = find_smmu_master(smmu, masterspec->np);
452 if (master) {
453 dev_err(dev,
454 "rejecting multiple registrations for master device %s\n",
455 masterspec->np->name);
456 return -EBUSY;
457 }
458
459 if (masterspec->args_count > MAX_MASTER_STREAMIDS) {
460 dev_err(dev,
461 "reached maximum number (%d) of stream IDs for master device %s\n",
462 MAX_MASTER_STREAMIDS, masterspec->np->name);
463 return -ENOSPC;
464 }
465
466 master = devm_kzalloc(dev, sizeof(*master), GFP_KERNEL);
467 if (!master)
468 return -ENOMEM;
469
470 master->of_node = masterspec->np;
471 master->num_streamids = masterspec->args_count;
472
473 for (i = 0; i < master->num_streamids; ++i)
474 master->streamids[i] = masterspec->args[i];
475
476 return insert_smmu_master(smmu, master);
477 }
478
479 static struct arm_smmu_device *find_parent_smmu(struct arm_smmu_device *smmu)
480 {
481 struct arm_smmu_device *parent;
482
483 if (!smmu->parent_of_node)
484 return NULL;
485
486 spin_lock(&arm_smmu_devices_lock);
487 list_for_each_entry(parent, &arm_smmu_devices, list)
488 if (parent->dev->of_node == smmu->parent_of_node)
489 goto out_unlock;
490
491 parent = NULL;
492 dev_warn(smmu->dev,
493 "Failed to find SMMU parent despite parent in DT\n");
494 out_unlock:
495 spin_unlock(&arm_smmu_devices_lock);
496 return parent;
497 }
498
499 static int __arm_smmu_alloc_bitmap(unsigned long *map, int start, int end)
500 {
501 int idx;
502
503 do {
504 idx = find_next_zero_bit(map, end, start);
505 if (idx == end)
506 return -ENOSPC;
507 } while (test_and_set_bit(idx, map));
508
509 return idx;
510 }
511
512 static void __arm_smmu_free_bitmap(unsigned long *map, int idx)
513 {
514 clear_bit(idx, map);
515 }
516
517 /* Wait for any pending TLB invalidations to complete */
518 static void arm_smmu_tlb_sync(struct arm_smmu_device *smmu)
519 {
520 int count = 0;
521 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
522
523 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_sTLBGSYNC);
524 while (readl_relaxed(gr0_base + ARM_SMMU_GR0_sTLBGSTATUS)
525 & sTLBGSTATUS_GSACTIVE) {
526 cpu_relax();
527 if (++count == TLB_LOOP_TIMEOUT) {
528 dev_err_ratelimited(smmu->dev,
529 "TLB sync timed out -- SMMU may be deadlocked\n");
530 return;
531 }
532 udelay(1);
533 }
534 }
535
536 static irqreturn_t arm_smmu_context_fault(int irq, void *dev)
537 {
538 int flags, ret;
539 u32 fsr, far, fsynr, resume;
540 unsigned long iova;
541 struct iommu_domain *domain = dev;
542 struct arm_smmu_domain *smmu_domain = domain->priv;
543 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
544 struct arm_smmu_device *smmu = root_cfg->smmu;
545 void __iomem *cb_base;
546
547 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
548 fsr = readl_relaxed(cb_base + ARM_SMMU_CB_FSR);
549
550 if (!(fsr & FSR_FAULT))
551 return IRQ_NONE;
552
553 if (fsr & FSR_IGN)
554 dev_err_ratelimited(smmu->dev,
555 "Unexpected context fault (fsr 0x%u)\n",
556 fsr);
557
558 fsynr = readl_relaxed(cb_base + ARM_SMMU_CB_FSYNR0);
559 flags = fsynr & FSYNR0_WNR ? IOMMU_FAULT_WRITE : IOMMU_FAULT_READ;
560
561 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_LO);
562 iova = far;
563 #ifdef CONFIG_64BIT
564 far = readl_relaxed(cb_base + ARM_SMMU_CB_FAR_HI);
565 iova |= ((unsigned long)far << 32);
566 #endif
567
568 if (!report_iommu_fault(domain, smmu->dev, iova, flags)) {
569 ret = IRQ_HANDLED;
570 resume = RESUME_RETRY;
571 } else {
572 ret = IRQ_NONE;
573 resume = RESUME_TERMINATE;
574 }
575
576 /* Clear the faulting FSR */
577 writel(fsr, cb_base + ARM_SMMU_CB_FSR);
578
579 /* Retry or terminate any stalled transactions */
580 if (fsr & FSR_SS)
581 writel_relaxed(resume, cb_base + ARM_SMMU_CB_RESUME);
582
583 return ret;
584 }
585
586 static irqreturn_t arm_smmu_global_fault(int irq, void *dev)
587 {
588 u32 gfsr, gfsynr0, gfsynr1, gfsynr2;
589 struct arm_smmu_device *smmu = dev;
590 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
591
592 gfsr = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSR);
593 if (!gfsr)
594 return IRQ_NONE;
595
596 gfsynr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR0);
597 gfsynr1 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR1);
598 gfsynr2 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sGFSYNR2);
599
600 dev_err_ratelimited(smmu->dev,
601 "Unexpected global fault, this could be serious\n");
602 dev_err_ratelimited(smmu->dev,
603 "\tGFSR 0x%08x, GFSYNR0 0x%08x, GFSYNR1 0x%08x, GFSYNR2 0x%08x\n",
604 gfsr, gfsynr0, gfsynr1, gfsynr2);
605
606 writel(gfsr, gr0_base + ARM_SMMU_GR0_sGFSR);
607 return IRQ_HANDLED;
608 }
609
610 static void arm_smmu_init_context_bank(struct arm_smmu_domain *smmu_domain)
611 {
612 u32 reg;
613 bool stage1;
614 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
615 struct arm_smmu_device *smmu = root_cfg->smmu;
616 void __iomem *cb_base, *gr0_base, *gr1_base;
617
618 gr0_base = ARM_SMMU_GR0(smmu);
619 gr1_base = ARM_SMMU_GR1(smmu);
620 stage1 = root_cfg->cbar != CBAR_TYPE_S2_TRANS;
621 cb_base = ARM_SMMU_CB_BASE(smmu) + ARM_SMMU_CB(smmu, root_cfg->cbndx);
622
623 /* CBAR */
624 reg = root_cfg->cbar |
625 (root_cfg->vmid << CBAR_VMID_SHIFT);
626 if (smmu->version == 1)
627 reg |= root_cfg->irptndx << CBAR_IRPTNDX_SHIFT;
628
629 /* Use the weakest memory type, so it is overridden by the pte */
630 if (stage1)
631 reg |= (CBAR_S1_MEMATTR_WB << CBAR_S1_MEMATTR_SHIFT);
632 writel_relaxed(reg, gr1_base + ARM_SMMU_GR1_CBAR(root_cfg->cbndx));
633
634 if (smmu->version > 1) {
635 /* CBA2R */
636 #ifdef CONFIG_64BIT
637 reg = CBA2R_RW64_64BIT;
638 #else
639 reg = CBA2R_RW64_32BIT;
640 #endif
641 writel_relaxed(reg,
642 gr1_base + ARM_SMMU_GR1_CBA2R(root_cfg->cbndx));
643
644 /* TTBCR2 */
645 switch (smmu->input_size) {
646 case 32:
647 reg = (TTBCR2_ADDR_32 << TTBCR2_SEP_SHIFT);
648 break;
649 case 36:
650 reg = (TTBCR2_ADDR_36 << TTBCR2_SEP_SHIFT);
651 break;
652 case 39:
653 reg = (TTBCR2_ADDR_40 << TTBCR2_SEP_SHIFT);
654 break;
655 case 42:
656 reg = (TTBCR2_ADDR_42 << TTBCR2_SEP_SHIFT);
657 break;
658 case 44:
659 reg = (TTBCR2_ADDR_44 << TTBCR2_SEP_SHIFT);
660 break;
661 case 48:
662 reg = (TTBCR2_ADDR_48 << TTBCR2_SEP_SHIFT);
663 break;
664 }
665
666 switch (smmu->s1_output_size) {
667 case 32:
668 reg |= (TTBCR2_ADDR_32 << TTBCR2_PASIZE_SHIFT);
669 break;
670 case 36:
671 reg |= (TTBCR2_ADDR_36 << TTBCR2_PASIZE_SHIFT);
672 break;
673 case 39:
674 reg |= (TTBCR2_ADDR_40 << TTBCR2_PASIZE_SHIFT);
675 break;
676 case 42:
677 reg |= (TTBCR2_ADDR_42 << TTBCR2_PASIZE_SHIFT);
678 break;
679 case 44:
680 reg |= (TTBCR2_ADDR_44 << TTBCR2_PASIZE_SHIFT);
681 break;
682 case 48:
683 reg |= (TTBCR2_ADDR_48 << TTBCR2_PASIZE_SHIFT);
684 break;
685 }
686
687 if (stage1)
688 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR2);
689 }
690
691 /* TTBR0 */
692 reg = __pa(root_cfg->pgd);
693 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_LO);
694 reg = (phys_addr_t)__pa(root_cfg->pgd) >> 32;
695 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBR0_HI);
696
697 /*
698 * TTBCR
699 * We use long descriptor, with inner-shareable WBWA tables in TTBR0.
700 */
701 if (smmu->version > 1) {
702 if (PAGE_SIZE == SZ_4K)
703 reg = TTBCR_TG0_4K;
704 else
705 reg = TTBCR_TG0_64K;
706
707 if (!stage1) {
708 switch (smmu->s2_output_size) {
709 case 32:
710 reg |= (TTBCR2_ADDR_32 << TTBCR_PASIZE_SHIFT);
711 break;
712 case 36:
713 reg |= (TTBCR2_ADDR_36 << TTBCR_PASIZE_SHIFT);
714 break;
715 case 40:
716 reg |= (TTBCR2_ADDR_40 << TTBCR_PASIZE_SHIFT);
717 break;
718 case 42:
719 reg |= (TTBCR2_ADDR_42 << TTBCR_PASIZE_SHIFT);
720 break;
721 case 44:
722 reg |= (TTBCR2_ADDR_44 << TTBCR_PASIZE_SHIFT);
723 break;
724 case 48:
725 reg |= (TTBCR2_ADDR_48 << TTBCR_PASIZE_SHIFT);
726 break;
727 }
728 } else {
729 reg |= (64 - smmu->s1_output_size) << TTBCR_T0SZ_SHIFT;
730 }
731 } else {
732 reg = 0;
733 }
734
735 reg |= TTBCR_EAE |
736 (TTBCR_SH_IS << TTBCR_SH0_SHIFT) |
737 (TTBCR_RGN_WBWA << TTBCR_ORGN0_SHIFT) |
738 (TTBCR_RGN_WBWA << TTBCR_IRGN0_SHIFT) |
739 (TTBCR_SL0_LVL_1 << TTBCR_SL0_SHIFT);
740 writel_relaxed(reg, cb_base + ARM_SMMU_CB_TTBCR);
741
742 /* MAIR0 (stage-1 only) */
743 if (stage1) {
744 reg = (MAIR_ATTR_NC << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_NC)) |
745 (MAIR_ATTR_WBRWA << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_CACHE)) |
746 (MAIR_ATTR_DEVICE << MAIR_ATTR_SHIFT(MAIR_ATTR_IDX_DEV));
747 writel_relaxed(reg, cb_base + ARM_SMMU_CB_S1_MAIR0);
748 }
749
750 /* Nuke the TLB */
751 writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID);
752 arm_smmu_tlb_sync(smmu);
753
754 /* SCTLR */
755 reg = SCTLR_CFCFG | SCTLR_CFIE | SCTLR_CFRE | SCTLR_M | SCTLR_EAE_SBOP;
756 if (stage1)
757 reg |= SCTLR_S1_ASIDPNE;
758 #ifdef __BIG_ENDIAN
759 reg |= SCTLR_E;
760 #endif
761 writel(reg, cb_base + ARM_SMMU_CB_SCTLR);
762 }
763
764 static int arm_smmu_init_domain_context(struct iommu_domain *domain,
765 struct device *dev)
766 {
767 int irq, ret, start;
768 struct arm_smmu_domain *smmu_domain = domain->priv;
769 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
770 struct arm_smmu_device *smmu, *parent;
771
772 /*
773 * Walk the SMMU chain to find the root device for this chain.
774 * We assume that no masters have translations which terminate
775 * early, and therefore check that the root SMMU does indeed have
776 * a StreamID for the master in question.
777 */
778 parent = dev->archdata.iommu;
779 smmu_domain->output_mask = -1;
780 do {
781 smmu = parent;
782 smmu_domain->output_mask &= (1ULL << smmu->s2_output_size) - 1;
783 } while ((parent = find_parent_smmu(smmu)));
784
785 if (!find_smmu_master(smmu, dev->of_node)) {
786 dev_err(dev, "unable to find root SMMU for device\n");
787 return -ENODEV;
788 }
789
790 ret = __arm_smmu_alloc_bitmap(smmu->vmid_map, 0, ARM_SMMU_NUM_VMIDS);
791 if (IS_ERR_VALUE(ret))
792 return ret;
793
794 root_cfg->vmid = ret;
795 if (smmu->features & ARM_SMMU_FEAT_TRANS_NESTED) {
796 /*
797 * We will likely want to change this if/when KVM gets
798 * involved.
799 */
800 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
801 start = smmu->num_s2_context_banks;
802 } else if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) {
803 root_cfg->cbar = CBAR_TYPE_S2_TRANS;
804 start = 0;
805 } else {
806 root_cfg->cbar = CBAR_TYPE_S1_TRANS_S2_BYPASS;
807 start = smmu->num_s2_context_banks;
808 }
809
810 ret = __arm_smmu_alloc_bitmap(smmu->context_map, start,
811 smmu->num_context_banks);
812 if (IS_ERR_VALUE(ret))
813 goto out_free_vmid;
814
815 root_cfg->cbndx = ret;
816
817 if (smmu->version == 1) {
818 root_cfg->irptndx = atomic_inc_return(&smmu->irptndx);
819 root_cfg->irptndx %= smmu->num_context_irqs;
820 } else {
821 root_cfg->irptndx = root_cfg->cbndx;
822 }
823
824 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
825 ret = request_irq(irq, arm_smmu_context_fault, IRQF_SHARED,
826 "arm-smmu-context-fault", domain);
827 if (IS_ERR_VALUE(ret)) {
828 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n",
829 root_cfg->irptndx, irq);
830 root_cfg->irptndx = -1;
831 goto out_free_context;
832 }
833
834 root_cfg->smmu = smmu;
835 arm_smmu_init_context_bank(smmu_domain);
836 return ret;
837
838 out_free_context:
839 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
840 out_free_vmid:
841 __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid);
842 return ret;
843 }
844
845 static void arm_smmu_destroy_domain_context(struct iommu_domain *domain)
846 {
847 struct arm_smmu_domain *smmu_domain = domain->priv;
848 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
849 struct arm_smmu_device *smmu = root_cfg->smmu;
850 int irq;
851
852 if (!smmu)
853 return;
854
855 if (root_cfg->irptndx != -1) {
856 irq = smmu->irqs[smmu->num_global_irqs + root_cfg->irptndx];
857 free_irq(irq, domain);
858 }
859
860 __arm_smmu_free_bitmap(smmu->vmid_map, root_cfg->vmid);
861 __arm_smmu_free_bitmap(smmu->context_map, root_cfg->cbndx);
862 }
863
864 static int arm_smmu_domain_init(struct iommu_domain *domain)
865 {
866 struct arm_smmu_domain *smmu_domain;
867 pgd_t *pgd;
868
869 /*
870 * Allocate the domain and initialise some of its data structures.
871 * We can't really do anything meaningful until we've added a
872 * master.
873 */
874 smmu_domain = kzalloc(sizeof(*smmu_domain), GFP_KERNEL);
875 if (!smmu_domain)
876 return -ENOMEM;
877
878 pgd = kzalloc(PTRS_PER_PGD * sizeof(pgd_t), GFP_KERNEL);
879 if (!pgd)
880 goto out_free_domain;
881 smmu_domain->root_cfg.pgd = pgd;
882
883 spin_lock_init(&smmu_domain->lock);
884 domain->priv = smmu_domain;
885 return 0;
886
887 out_free_domain:
888 kfree(smmu_domain);
889 return -ENOMEM;
890 }
891
892 static void arm_smmu_free_ptes(pmd_t *pmd)
893 {
894 pgtable_t table = pmd_pgtable(*pmd);
895 pgtable_page_dtor(table);
896 __free_page(table);
897 }
898
899 static void arm_smmu_free_pmds(pud_t *pud)
900 {
901 int i;
902 pmd_t *pmd, *pmd_base = pmd_offset(pud, 0);
903
904 pmd = pmd_base;
905 for (i = 0; i < PTRS_PER_PMD; ++i) {
906 if (pmd_none(*pmd))
907 continue;
908
909 arm_smmu_free_ptes(pmd);
910 pmd++;
911 }
912
913 pmd_free(NULL, pmd_base);
914 }
915
916 static void arm_smmu_free_puds(pgd_t *pgd)
917 {
918 int i;
919 pud_t *pud, *pud_base = pud_offset(pgd, 0);
920
921 pud = pud_base;
922 for (i = 0; i < PTRS_PER_PUD; ++i) {
923 if (pud_none(*pud))
924 continue;
925
926 arm_smmu_free_pmds(pud);
927 pud++;
928 }
929
930 pud_free(NULL, pud_base);
931 }
932
933 static void arm_smmu_free_pgtables(struct arm_smmu_domain *smmu_domain)
934 {
935 int i;
936 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
937 pgd_t *pgd, *pgd_base = root_cfg->pgd;
938
939 /*
940 * Recursively free the page tables for this domain. We don't
941 * care about speculative TLB filling, because the TLB will be
942 * nuked next time this context bank is re-allocated and no devices
943 * currently map to these tables.
944 */
945 pgd = pgd_base;
946 for (i = 0; i < PTRS_PER_PGD; ++i) {
947 if (pgd_none(*pgd))
948 continue;
949 arm_smmu_free_puds(pgd);
950 pgd++;
951 }
952
953 kfree(pgd_base);
954 }
955
956 static void arm_smmu_domain_destroy(struct iommu_domain *domain)
957 {
958 struct arm_smmu_domain *smmu_domain = domain->priv;
959 arm_smmu_destroy_domain_context(domain);
960 arm_smmu_free_pgtables(smmu_domain);
961 kfree(smmu_domain);
962 }
963
964 static int arm_smmu_master_configure_smrs(struct arm_smmu_device *smmu,
965 struct arm_smmu_master *master)
966 {
967 int i;
968 struct arm_smmu_smr *smrs;
969 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
970
971 if (!(smmu->features & ARM_SMMU_FEAT_STREAM_MATCH))
972 return 0;
973
974 if (master->smrs)
975 return -EEXIST;
976
977 smrs = kmalloc(sizeof(*smrs) * master->num_streamids, GFP_KERNEL);
978 if (!smrs) {
979 dev_err(smmu->dev, "failed to allocate %d SMRs for master %s\n",
980 master->num_streamids, master->of_node->name);
981 return -ENOMEM;
982 }
983
984 /* Allocate the SMRs on the root SMMU */
985 for (i = 0; i < master->num_streamids; ++i) {
986 int idx = __arm_smmu_alloc_bitmap(smmu->smr_map, 0,
987 smmu->num_mapping_groups);
988 if (IS_ERR_VALUE(idx)) {
989 dev_err(smmu->dev, "failed to allocate free SMR\n");
990 goto err_free_smrs;
991 }
992
993 smrs[i] = (struct arm_smmu_smr) {
994 .idx = idx,
995 .mask = 0, /* We don't currently share SMRs */
996 .id = master->streamids[i],
997 };
998 }
999
1000 /* It worked! Now, poke the actual hardware */
1001 for (i = 0; i < master->num_streamids; ++i) {
1002 u32 reg = SMR_VALID | smrs[i].id << SMR_ID_SHIFT |
1003 smrs[i].mask << SMR_MASK_SHIFT;
1004 writel_relaxed(reg, gr0_base + ARM_SMMU_GR0_SMR(smrs[i].idx));
1005 }
1006
1007 master->smrs = smrs;
1008 return 0;
1009
1010 err_free_smrs:
1011 while (--i >= 0)
1012 __arm_smmu_free_bitmap(smmu->smr_map, smrs[i].idx);
1013 kfree(smrs);
1014 return -ENOSPC;
1015 }
1016
1017 static void arm_smmu_master_free_smrs(struct arm_smmu_device *smmu,
1018 struct arm_smmu_master *master)
1019 {
1020 int i;
1021 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1022 struct arm_smmu_smr *smrs = master->smrs;
1023
1024 /* Invalidate the SMRs before freeing back to the allocator */
1025 for (i = 0; i < master->num_streamids; ++i) {
1026 u8 idx = smrs[i].idx;
1027 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(idx));
1028 __arm_smmu_free_bitmap(smmu->smr_map, idx);
1029 }
1030
1031 master->smrs = NULL;
1032 kfree(smrs);
1033 }
1034
1035 static void arm_smmu_bypass_stream_mapping(struct arm_smmu_device *smmu,
1036 struct arm_smmu_master *master)
1037 {
1038 int i;
1039 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1040
1041 for (i = 0; i < master->num_streamids; ++i) {
1042 u16 sid = master->streamids[i];
1043 writel_relaxed(S2CR_TYPE_BYPASS,
1044 gr0_base + ARM_SMMU_GR0_S2CR(sid));
1045 }
1046 }
1047
1048 static int arm_smmu_domain_add_master(struct arm_smmu_domain *smmu_domain,
1049 struct arm_smmu_master *master)
1050 {
1051 int i, ret;
1052 struct arm_smmu_device *parent, *smmu = smmu_domain->root_cfg.smmu;
1053 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1054
1055 ret = arm_smmu_master_configure_smrs(smmu, master);
1056 if (ret)
1057 return ret;
1058
1059 /* Bypass the leaves */
1060 smmu = smmu_domain->leaf_smmu;
1061 while ((parent = find_parent_smmu(smmu))) {
1062 /*
1063 * We won't have a StreamID match for anything but the root
1064 * smmu, so we only need to worry about StreamID indexing,
1065 * where we must install bypass entries in the S2CRs.
1066 */
1067 if (smmu->features & ARM_SMMU_FEAT_STREAM_MATCH)
1068 continue;
1069
1070 arm_smmu_bypass_stream_mapping(smmu, master);
1071 smmu = parent;
1072 }
1073
1074 /* Now we're at the root, time to point at our context bank */
1075 for (i = 0; i < master->num_streamids; ++i) {
1076 u32 idx, s2cr;
1077 idx = master->smrs ? master->smrs[i].idx : master->streamids[i];
1078 s2cr = (S2CR_TYPE_TRANS << S2CR_TYPE_SHIFT) |
1079 (smmu_domain->root_cfg.cbndx << S2CR_CBNDX_SHIFT);
1080 writel_relaxed(s2cr, gr0_base + ARM_SMMU_GR0_S2CR(idx));
1081 }
1082
1083 return 0;
1084 }
1085
1086 static void arm_smmu_domain_remove_master(struct arm_smmu_domain *smmu_domain,
1087 struct arm_smmu_master *master)
1088 {
1089 struct arm_smmu_device *smmu = smmu_domain->root_cfg.smmu;
1090
1091 /*
1092 * We *must* clear the S2CR first, because freeing the SMR means
1093 * that it can be re-allocated immediately.
1094 */
1095 arm_smmu_bypass_stream_mapping(smmu, master);
1096 arm_smmu_master_free_smrs(smmu, master);
1097 }
1098
1099 static int arm_smmu_attach_dev(struct iommu_domain *domain, struct device *dev)
1100 {
1101 int ret = -EINVAL;
1102 struct arm_smmu_domain *smmu_domain = domain->priv;
1103 struct arm_smmu_device *device_smmu = dev->archdata.iommu;
1104 struct arm_smmu_master *master;
1105
1106 if (!device_smmu) {
1107 dev_err(dev, "cannot attach to SMMU, is it on the same bus?\n");
1108 return -ENXIO;
1109 }
1110
1111 /*
1112 * Sanity check the domain. We don't currently support domains
1113 * that cross between different SMMU chains.
1114 */
1115 spin_lock(&smmu_domain->lock);
1116 if (!smmu_domain->leaf_smmu) {
1117 /* Now that we have a master, we can finalise the domain */
1118 ret = arm_smmu_init_domain_context(domain, dev);
1119 if (IS_ERR_VALUE(ret))
1120 goto err_unlock;
1121
1122 smmu_domain->leaf_smmu = device_smmu;
1123 } else if (smmu_domain->leaf_smmu != device_smmu) {
1124 dev_err(dev,
1125 "cannot attach to SMMU %s whilst already attached to domain on SMMU %s\n",
1126 dev_name(smmu_domain->leaf_smmu->dev),
1127 dev_name(device_smmu->dev));
1128 goto err_unlock;
1129 }
1130 spin_unlock(&smmu_domain->lock);
1131
1132 /* Looks ok, so add the device to the domain */
1133 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1134 if (!master)
1135 return -ENODEV;
1136
1137 return arm_smmu_domain_add_master(smmu_domain, master);
1138
1139 err_unlock:
1140 spin_unlock(&smmu_domain->lock);
1141 return ret;
1142 }
1143
1144 static void arm_smmu_detach_dev(struct iommu_domain *domain, struct device *dev)
1145 {
1146 struct arm_smmu_domain *smmu_domain = domain->priv;
1147 struct arm_smmu_master *master;
1148
1149 master = find_smmu_master(smmu_domain->leaf_smmu, dev->of_node);
1150 if (master)
1151 arm_smmu_domain_remove_master(smmu_domain, master);
1152 }
1153
1154 static void arm_smmu_flush_pgtable(struct arm_smmu_device *smmu, void *addr,
1155 size_t size)
1156 {
1157 unsigned long offset = (unsigned long)addr & ~PAGE_MASK;
1158
1159 /*
1160 * If the SMMU can't walk tables in the CPU caches, treat them
1161 * like non-coherent DMA since we need to flush the new entries
1162 * all the way out to memory. There's no possibility of recursion
1163 * here as the SMMU table walker will not be wired through another
1164 * SMMU.
1165 */
1166 if (!(smmu->features & ARM_SMMU_FEAT_COHERENT_WALK))
1167 dma_map_page(smmu->dev, virt_to_page(addr), offset, size,
1168 DMA_TO_DEVICE);
1169 }
1170
1171 static bool arm_smmu_pte_is_contiguous_range(unsigned long addr,
1172 unsigned long end)
1173 {
1174 return !(addr & ~ARM_SMMU_PTE_CONT_MASK) &&
1175 (addr + ARM_SMMU_PTE_CONT_SIZE <= end);
1176 }
1177
1178 static int arm_smmu_alloc_init_pte(struct arm_smmu_device *smmu, pmd_t *pmd,
1179 unsigned long addr, unsigned long end,
1180 unsigned long pfn, int flags, int stage)
1181 {
1182 pte_t *pte, *start;
1183 pteval_t pteval = ARM_SMMU_PTE_PAGE | ARM_SMMU_PTE_AF;
1184
1185 if (pmd_none(*pmd)) {
1186 /* Allocate a new set of tables */
1187 pgtable_t table = alloc_page(PGALLOC_GFP);
1188 if (!table)
1189 return -ENOMEM;
1190
1191 arm_smmu_flush_pgtable(smmu, page_address(table),
1192 ARM_SMMU_PTE_HWTABLE_SIZE);
1193 pgtable_page_ctor(table);
1194 pmd_populate(NULL, pmd, table);
1195 arm_smmu_flush_pgtable(smmu, pmd, sizeof(*pmd));
1196 }
1197
1198 if (stage == 1) {
1199 pteval |= ARM_SMMU_PTE_AP_UNPRIV;
1200 if (!(flags & IOMMU_WRITE) && (flags & IOMMU_READ))
1201 pteval |= ARM_SMMU_PTE_AP_RDONLY;
1202
1203 if (flags & IOMMU_CACHE)
1204 pteval |= (MAIR_ATTR_IDX_CACHE <<
1205 ARM_SMMU_PTE_ATTRINDX_SHIFT);
1206 } else {
1207 pteval |= ARM_SMMU_PTE_HAP_FAULT;
1208 if (flags & IOMMU_READ)
1209 pteval |= ARM_SMMU_PTE_HAP_READ;
1210 if (flags & IOMMU_WRITE)
1211 pteval |= ARM_SMMU_PTE_HAP_WRITE;
1212 if (flags & IOMMU_CACHE)
1213 pteval |= ARM_SMMU_PTE_MEMATTR_OIWB;
1214 else
1215 pteval |= ARM_SMMU_PTE_MEMATTR_NC;
1216 }
1217
1218 /* If no access, create a faulting entry to avoid TLB fills */
1219 if (!(flags & (IOMMU_READ | IOMMU_WRITE)))
1220 pteval &= ~ARM_SMMU_PTE_PAGE;
1221
1222 pteval |= ARM_SMMU_PTE_SH_IS;
1223 start = pmd_page_vaddr(*pmd) + pte_index(addr);
1224 pte = start;
1225
1226 /*
1227 * Install the page table entries. This is fairly complicated
1228 * since we attempt to make use of the contiguous hint in the
1229 * ptes where possible. The contiguous hint indicates a series
1230 * of ARM_SMMU_PTE_CONT_ENTRIES ptes mapping a physically
1231 * contiguous region with the following constraints:
1232 *
1233 * - The region start is aligned to ARM_SMMU_PTE_CONT_SIZE
1234 * - Each pte in the region has the contiguous hint bit set
1235 *
1236 * This complicates unmapping (also handled by this code, when
1237 * neither IOMMU_READ or IOMMU_WRITE are set) because it is
1238 * possible, yet highly unlikely, that a client may unmap only
1239 * part of a contiguous range. This requires clearing of the
1240 * contiguous hint bits in the range before installing the new
1241 * faulting entries.
1242 *
1243 * Note that re-mapping an address range without first unmapping
1244 * it is not supported, so TLB invalidation is not required here
1245 * and is instead performed at unmap and domain-init time.
1246 */
1247 do {
1248 int i = 1;
1249 pteval &= ~ARM_SMMU_PTE_CONT;
1250
1251 if (arm_smmu_pte_is_contiguous_range(addr, end)) {
1252 i = ARM_SMMU_PTE_CONT_ENTRIES;
1253 pteval |= ARM_SMMU_PTE_CONT;
1254 } else if (pte_val(*pte) &
1255 (ARM_SMMU_PTE_CONT | ARM_SMMU_PTE_PAGE)) {
1256 int j;
1257 pte_t *cont_start;
1258 unsigned long idx = pte_index(addr);
1259
1260 idx &= ~(ARM_SMMU_PTE_CONT_ENTRIES - 1);
1261 cont_start = pmd_page_vaddr(*pmd) + idx;
1262 for (j = 0; j < ARM_SMMU_PTE_CONT_ENTRIES; ++j)
1263 pte_val(*(cont_start + j)) &= ~ARM_SMMU_PTE_CONT;
1264
1265 arm_smmu_flush_pgtable(smmu, cont_start,
1266 sizeof(*pte) *
1267 ARM_SMMU_PTE_CONT_ENTRIES);
1268 }
1269
1270 do {
1271 *pte = pfn_pte(pfn, __pgprot(pteval));
1272 } while (pte++, pfn++, addr += PAGE_SIZE, --i);
1273 } while (addr != end);
1274
1275 arm_smmu_flush_pgtable(smmu, start, sizeof(*pte) * (pte - start));
1276 return 0;
1277 }
1278
1279 static int arm_smmu_alloc_init_pmd(struct arm_smmu_device *smmu, pud_t *pud,
1280 unsigned long addr, unsigned long end,
1281 phys_addr_t phys, int flags, int stage)
1282 {
1283 int ret;
1284 pmd_t *pmd;
1285 unsigned long next, pfn = __phys_to_pfn(phys);
1286
1287 #ifndef __PAGETABLE_PMD_FOLDED
1288 if (pud_none(*pud)) {
1289 pmd = pmd_alloc_one(NULL, addr);
1290 if (!pmd)
1291 return -ENOMEM;
1292 } else
1293 #endif
1294 pmd = pmd_offset(pud, addr);
1295
1296 do {
1297 next = pmd_addr_end(addr, end);
1298 ret = arm_smmu_alloc_init_pte(smmu, pmd, addr, end, pfn,
1299 flags, stage);
1300 pud_populate(NULL, pud, pmd);
1301 arm_smmu_flush_pgtable(smmu, pud, sizeof(*pud));
1302 phys += next - addr;
1303 } while (pmd++, addr = next, addr < end);
1304
1305 return ret;
1306 }
1307
1308 static int arm_smmu_alloc_init_pud(struct arm_smmu_device *smmu, pgd_t *pgd,
1309 unsigned long addr, unsigned long end,
1310 phys_addr_t phys, int flags, int stage)
1311 {
1312 int ret = 0;
1313 pud_t *pud;
1314 unsigned long next;
1315
1316 #ifndef __PAGETABLE_PUD_FOLDED
1317 if (pgd_none(*pgd)) {
1318 pud = pud_alloc_one(NULL, addr);
1319 if (!pud)
1320 return -ENOMEM;
1321 } else
1322 #endif
1323 pud = pud_offset(pgd, addr);
1324
1325 do {
1326 next = pud_addr_end(addr, end);
1327 ret = arm_smmu_alloc_init_pmd(smmu, pud, addr, next, phys,
1328 flags, stage);
1329 pgd_populate(NULL, pud, pgd);
1330 arm_smmu_flush_pgtable(smmu, pgd, sizeof(*pgd));
1331 phys += next - addr;
1332 } while (pud++, addr = next, addr < end);
1333
1334 return ret;
1335 }
1336
1337 static int arm_smmu_handle_mapping(struct arm_smmu_domain *smmu_domain,
1338 unsigned long iova, phys_addr_t paddr,
1339 size_t size, int flags)
1340 {
1341 int ret, stage;
1342 unsigned long end;
1343 phys_addr_t input_mask, output_mask;
1344 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1345 pgd_t *pgd = root_cfg->pgd;
1346 struct arm_smmu_device *smmu = root_cfg->smmu;
1347
1348 if (root_cfg->cbar == CBAR_TYPE_S2_TRANS) {
1349 stage = 2;
1350 output_mask = (1ULL << smmu->s2_output_size) - 1;
1351 } else {
1352 stage = 1;
1353 output_mask = (1ULL << smmu->s1_output_size) - 1;
1354 }
1355
1356 if (!pgd)
1357 return -EINVAL;
1358
1359 if (size & ~PAGE_MASK)
1360 return -EINVAL;
1361
1362 input_mask = (1ULL << smmu->input_size) - 1;
1363 if ((phys_addr_t)iova & ~input_mask)
1364 return -ERANGE;
1365
1366 if (paddr & ~output_mask)
1367 return -ERANGE;
1368
1369 spin_lock(&smmu_domain->lock);
1370 pgd += pgd_index(iova);
1371 end = iova + size;
1372 do {
1373 unsigned long next = pgd_addr_end(iova, end);
1374
1375 ret = arm_smmu_alloc_init_pud(smmu, pgd, iova, next, paddr,
1376 flags, stage);
1377 if (ret)
1378 goto out_unlock;
1379
1380 paddr += next - iova;
1381 iova = next;
1382 } while (pgd++, iova != end);
1383
1384 out_unlock:
1385 spin_unlock(&smmu_domain->lock);
1386
1387 /* Ensure new page tables are visible to the hardware walker */
1388 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1389 dsb();
1390
1391 return ret;
1392 }
1393
1394 static int arm_smmu_map(struct iommu_domain *domain, unsigned long iova,
1395 phys_addr_t paddr, size_t size, int flags)
1396 {
1397 struct arm_smmu_domain *smmu_domain = domain->priv;
1398 struct arm_smmu_device *smmu = smmu_domain->leaf_smmu;
1399
1400 if (!smmu_domain || !smmu)
1401 return -ENODEV;
1402
1403 /* Check for silent address truncation up the SMMU chain. */
1404 if ((phys_addr_t)iova & ~smmu_domain->output_mask)
1405 return -ERANGE;
1406
1407 return arm_smmu_handle_mapping(smmu_domain, iova, paddr, size, flags);
1408 }
1409
1410 static size_t arm_smmu_unmap(struct iommu_domain *domain, unsigned long iova,
1411 size_t size)
1412 {
1413 int ret;
1414 struct arm_smmu_domain *smmu_domain = domain->priv;
1415 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1416 struct arm_smmu_device *smmu = root_cfg->smmu;
1417 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1418
1419 ret = arm_smmu_handle_mapping(smmu_domain, iova, 0, size, 0);
1420 writel_relaxed(root_cfg->vmid, gr0_base + ARM_SMMU_GR0_TLBIVMID);
1421 arm_smmu_tlb_sync(smmu);
1422 return ret ? ret : size;
1423 }
1424
1425 static phys_addr_t arm_smmu_iova_to_phys(struct iommu_domain *domain,
1426 dma_addr_t iova)
1427 {
1428 pgd_t *pgd;
1429 pud_t *pud;
1430 pmd_t *pmd;
1431 pte_t *pte;
1432 struct arm_smmu_domain *smmu_domain = domain->priv;
1433 struct arm_smmu_cfg *root_cfg = &smmu_domain->root_cfg;
1434 struct arm_smmu_device *smmu = root_cfg->smmu;
1435
1436 spin_lock(&smmu_domain->lock);
1437 pgd = root_cfg->pgd;
1438 if (!pgd)
1439 goto err_unlock;
1440
1441 pgd += pgd_index(iova);
1442 if (pgd_none_or_clear_bad(pgd))
1443 goto err_unlock;
1444
1445 pud = pud_offset(pgd, iova);
1446 if (pud_none_or_clear_bad(pud))
1447 goto err_unlock;
1448
1449 pmd = pmd_offset(pud, iova);
1450 if (pmd_none_or_clear_bad(pmd))
1451 goto err_unlock;
1452
1453 pte = pmd_page_vaddr(*pmd) + pte_index(iova);
1454 if (pte_none(pte))
1455 goto err_unlock;
1456
1457 spin_unlock(&smmu_domain->lock);
1458 return __pfn_to_phys(pte_pfn(*pte)) | (iova & ~PAGE_MASK);
1459
1460 err_unlock:
1461 spin_unlock(&smmu_domain->lock);
1462 dev_warn(smmu->dev,
1463 "invalid (corrupt?) page tables detected for iova 0x%llx\n",
1464 (unsigned long long)iova);
1465 return -EINVAL;
1466 }
1467
1468 static int arm_smmu_domain_has_cap(struct iommu_domain *domain,
1469 unsigned long cap)
1470 {
1471 unsigned long caps = 0;
1472 struct arm_smmu_domain *smmu_domain = domain->priv;
1473
1474 if (smmu_domain->root_cfg.smmu->features & ARM_SMMU_FEAT_COHERENT_WALK)
1475 caps |= IOMMU_CAP_CACHE_COHERENCY;
1476
1477 return !!(cap & caps);
1478 }
1479
1480 static int arm_smmu_add_device(struct device *dev)
1481 {
1482 struct arm_smmu_device *child, *parent, *smmu;
1483 struct arm_smmu_master *master = NULL;
1484
1485 spin_lock(&arm_smmu_devices_lock);
1486 list_for_each_entry(parent, &arm_smmu_devices, list) {
1487 smmu = parent;
1488
1489 /* Try to find a child of the current SMMU. */
1490 list_for_each_entry(child, &arm_smmu_devices, list) {
1491 if (child->parent_of_node == parent->dev->of_node) {
1492 /* Does the child sit above our master? */
1493 master = find_smmu_master(child, dev->of_node);
1494 if (master) {
1495 smmu = NULL;
1496 break;
1497 }
1498 }
1499 }
1500
1501 /* We found some children, so keep searching. */
1502 if (!smmu) {
1503 master = NULL;
1504 continue;
1505 }
1506
1507 master = find_smmu_master(smmu, dev->of_node);
1508 if (master)
1509 break;
1510 }
1511 spin_unlock(&arm_smmu_devices_lock);
1512
1513 if (!master)
1514 return -ENODEV;
1515
1516 dev->archdata.iommu = smmu;
1517 return 0;
1518 }
1519
1520 static void arm_smmu_remove_device(struct device *dev)
1521 {
1522 dev->archdata.iommu = NULL;
1523 }
1524
1525 static struct iommu_ops arm_smmu_ops = {
1526 .domain_init = arm_smmu_domain_init,
1527 .domain_destroy = arm_smmu_domain_destroy,
1528 .attach_dev = arm_smmu_attach_dev,
1529 .detach_dev = arm_smmu_detach_dev,
1530 .map = arm_smmu_map,
1531 .unmap = arm_smmu_unmap,
1532 .iova_to_phys = arm_smmu_iova_to_phys,
1533 .domain_has_cap = arm_smmu_domain_has_cap,
1534 .add_device = arm_smmu_add_device,
1535 .remove_device = arm_smmu_remove_device,
1536 .pgsize_bitmap = (SECTION_SIZE |
1537 ARM_SMMU_PTE_CONT_SIZE |
1538 PAGE_SIZE),
1539 };
1540
1541 static void arm_smmu_device_reset(struct arm_smmu_device *smmu)
1542 {
1543 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1544 int i = 0;
1545 u32 scr0 = readl_relaxed(gr0_base + ARM_SMMU_GR0_sCR0);
1546
1547 /* Mark all SMRn as invalid and all S2CRn as bypass */
1548 for (i = 0; i < smmu->num_mapping_groups; ++i) {
1549 writel_relaxed(~SMR_VALID, gr0_base + ARM_SMMU_GR0_SMR(i));
1550 writel_relaxed(S2CR_TYPE_BYPASS, gr0_base + ARM_SMMU_GR0_S2CR(i));
1551 }
1552
1553 /* Invalidate the TLB, just in case */
1554 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_STLBIALL);
1555 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLH);
1556 writel_relaxed(0, gr0_base + ARM_SMMU_GR0_TLBIALLNSNH);
1557
1558 /* Enable fault reporting */
1559 scr0 |= (sCR0_GFRE | sCR0_GFIE | sCR0_GCFGFRE | sCR0_GCFGFIE);
1560
1561 /* Disable TLB broadcasting. */
1562 scr0 |= (sCR0_VMIDPNE | sCR0_PTM);
1563
1564 /* Enable client access, but bypass when no mapping is found */
1565 scr0 &= ~(sCR0_CLIENTPD | sCR0_USFCFG);
1566
1567 /* Disable forced broadcasting */
1568 scr0 &= ~sCR0_FB;
1569
1570 /* Don't upgrade barriers */
1571 scr0 &= ~(sCR0_BSU_MASK << sCR0_BSU_SHIFT);
1572
1573 /* Push the button */
1574 arm_smmu_tlb_sync(smmu);
1575 writel(scr0, gr0_base + ARM_SMMU_GR0_sCR0);
1576 }
1577
1578 static int arm_smmu_id_size_to_bits(int size)
1579 {
1580 switch (size) {
1581 case 0:
1582 return 32;
1583 case 1:
1584 return 36;
1585 case 2:
1586 return 40;
1587 case 3:
1588 return 42;
1589 case 4:
1590 return 44;
1591 case 5:
1592 default:
1593 return 48;
1594 }
1595 }
1596
1597 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu)
1598 {
1599 unsigned long size;
1600 void __iomem *gr0_base = ARM_SMMU_GR0(smmu);
1601 u32 id;
1602
1603 dev_notice(smmu->dev, "probing hardware configuration...\n");
1604
1605 /* Primecell ID */
1606 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_PIDR2);
1607 smmu->version = ((id >> PIDR2_ARCH_SHIFT) & PIDR2_ARCH_MASK) + 1;
1608 dev_notice(smmu->dev, "SMMUv%d with:\n", smmu->version);
1609
1610 /* ID0 */
1611 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID0);
1612 #ifndef CONFIG_64BIT
1613 if (((id >> ID0_PTFS_SHIFT) & ID0_PTFS_MASK) == ID0_PTFS_V8_ONLY) {
1614 dev_err(smmu->dev, "\tno v7 descriptor support!\n");
1615 return -ENODEV;
1616 }
1617 #endif
1618 if (id & ID0_S1TS) {
1619 smmu->features |= ARM_SMMU_FEAT_TRANS_S1;
1620 dev_notice(smmu->dev, "\tstage 1 translation\n");
1621 }
1622
1623 if (id & ID0_S2TS) {
1624 smmu->features |= ARM_SMMU_FEAT_TRANS_S2;
1625 dev_notice(smmu->dev, "\tstage 2 translation\n");
1626 }
1627
1628 if (id & ID0_NTS) {
1629 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED;
1630 dev_notice(smmu->dev, "\tnested translation\n");
1631 }
1632
1633 if (!(smmu->features &
1634 (ARM_SMMU_FEAT_TRANS_S1 | ARM_SMMU_FEAT_TRANS_S2 |
1635 ARM_SMMU_FEAT_TRANS_NESTED))) {
1636 dev_err(smmu->dev, "\tno translation support!\n");
1637 return -ENODEV;
1638 }
1639
1640 if (id & ID0_CTTW) {
1641 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK;
1642 dev_notice(smmu->dev, "\tcoherent table walk\n");
1643 }
1644
1645 if (id & ID0_SMS) {
1646 u32 smr, sid, mask;
1647
1648 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH;
1649 smmu->num_mapping_groups = (id >> ID0_NUMSMRG_SHIFT) &
1650 ID0_NUMSMRG_MASK;
1651 if (smmu->num_mapping_groups == 0) {
1652 dev_err(smmu->dev,
1653 "stream-matching supported, but no SMRs present!\n");
1654 return -ENODEV;
1655 }
1656
1657 smr = SMR_MASK_MASK << SMR_MASK_SHIFT;
1658 smr |= (SMR_ID_MASK << SMR_ID_SHIFT);
1659 writel_relaxed(smr, gr0_base + ARM_SMMU_GR0_SMR(0));
1660 smr = readl_relaxed(gr0_base + ARM_SMMU_GR0_SMR(0));
1661
1662 mask = (smr >> SMR_MASK_SHIFT) & SMR_MASK_MASK;
1663 sid = (smr >> SMR_ID_SHIFT) & SMR_ID_MASK;
1664 if ((mask & sid) != sid) {
1665 dev_err(smmu->dev,
1666 "SMR mask bits (0x%x) insufficient for ID field (0x%x)\n",
1667 mask, sid);
1668 return -ENODEV;
1669 }
1670
1671 dev_notice(smmu->dev,
1672 "\tstream matching with %u register groups, mask 0x%x",
1673 smmu->num_mapping_groups, mask);
1674 }
1675
1676 /* ID1 */
1677 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID1);
1678 smmu->pagesize = (id & ID1_PAGESIZE) ? SZ_64K : SZ_4K;
1679
1680 /* Check that we ioremapped enough */
1681 size = 1 << (((id >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1);
1682 size *= (smmu->pagesize << 1);
1683 if (smmu->size < size)
1684 dev_warn(smmu->dev,
1685 "device is 0x%lx bytes but only mapped 0x%lx!\n",
1686 size, smmu->size);
1687
1688 smmu->num_s2_context_banks = (id >> ID1_NUMS2CB_SHIFT) &
1689 ID1_NUMS2CB_MASK;
1690 smmu->num_context_banks = (id >> ID1_NUMCB_SHIFT) & ID1_NUMCB_MASK;
1691 if (smmu->num_s2_context_banks > smmu->num_context_banks) {
1692 dev_err(smmu->dev, "impossible number of S2 context banks!\n");
1693 return -ENODEV;
1694 }
1695 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n",
1696 smmu->num_context_banks, smmu->num_s2_context_banks);
1697
1698 /* ID2 */
1699 id = readl_relaxed(gr0_base + ARM_SMMU_GR0_ID2);
1700 size = arm_smmu_id_size_to_bits((id >> ID2_IAS_SHIFT) & ID2_IAS_MASK);
1701
1702 /*
1703 * Stage-1 output limited by stage-2 input size due to pgd
1704 * allocation (PTRS_PER_PGD).
1705 */
1706 #ifdef CONFIG_64BIT
1707 /* Current maximum output size of 39 bits */
1708 smmu->s1_output_size = min(39UL, size);
1709 #else
1710 smmu->s1_output_size = min(32UL, size);
1711 #endif
1712
1713 /* The stage-2 output mask is also applied for bypass */
1714 size = arm_smmu_id_size_to_bits((id >> ID2_OAS_SHIFT) & ID2_OAS_MASK);
1715 smmu->s2_output_size = min((unsigned long)PHYS_MASK_SHIFT, size);
1716
1717 if (smmu->version == 1) {
1718 smmu->input_size = 32;
1719 } else {
1720 #ifdef CONFIG_64BIT
1721 size = (id >> ID2_UBS_SHIFT) & ID2_UBS_MASK;
1722 size = min(39, arm_smmu_id_size_to_bits(size));
1723 #else
1724 size = 32;
1725 #endif
1726 smmu->input_size = size;
1727
1728 if ((PAGE_SIZE == SZ_4K && !(id & ID2_PTFS_4K)) ||
1729 (PAGE_SIZE == SZ_64K && !(id & ID2_PTFS_64K)) ||
1730 (PAGE_SIZE != SZ_4K && PAGE_SIZE != SZ_64K)) {
1731 dev_err(smmu->dev, "CPU page size 0x%lx unsupported\n",
1732 PAGE_SIZE);
1733 return -ENODEV;
1734 }
1735 }
1736
1737 dev_notice(smmu->dev,
1738 "\t%lu-bit VA, %lu-bit IPA, %lu-bit PA\n",
1739 smmu->input_size, smmu->s1_output_size, smmu->s2_output_size);
1740 return 0;
1741 }
1742
1743 static int arm_smmu_device_dt_probe(struct platform_device *pdev)
1744 {
1745 struct resource *res;
1746 struct arm_smmu_device *smmu;
1747 struct device_node *dev_node;
1748 struct device *dev = &pdev->dev;
1749 struct rb_node *node;
1750 struct of_phandle_args masterspec;
1751 int num_irqs, i, err;
1752
1753 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL);
1754 if (!smmu) {
1755 dev_err(dev, "failed to allocate arm_smmu_device\n");
1756 return -ENOMEM;
1757 }
1758 smmu->dev = dev;
1759
1760 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1761 if (!res) {
1762 dev_err(dev, "missing base address/size\n");
1763 return -ENODEV;
1764 }
1765
1766 smmu->size = resource_size(res);
1767 smmu->base = devm_request_and_ioremap(dev, res);
1768 if (!smmu->base)
1769 return -EADDRNOTAVAIL;
1770
1771 if (of_property_read_u32(dev->of_node, "#global-interrupts",
1772 &smmu->num_global_irqs)) {
1773 dev_err(dev, "missing #global-interrupts property\n");
1774 return -ENODEV;
1775 }
1776
1777 num_irqs = 0;
1778 while ((res = platform_get_resource(pdev, IORESOURCE_IRQ, num_irqs))) {
1779 num_irqs++;
1780 if (num_irqs > smmu->num_global_irqs)
1781 smmu->num_context_irqs++;
1782 }
1783
1784 if (num_irqs < smmu->num_global_irqs) {
1785 dev_warn(dev, "found %d interrupts but expected at least %d\n",
1786 num_irqs, smmu->num_global_irqs);
1787 smmu->num_global_irqs = num_irqs;
1788 }
1789 smmu->num_context_irqs = num_irqs - smmu->num_global_irqs;
1790
1791 smmu->irqs = devm_kzalloc(dev, sizeof(*smmu->irqs) * num_irqs,
1792 GFP_KERNEL);
1793 if (!smmu->irqs) {
1794 dev_err(dev, "failed to allocate %d irqs\n", num_irqs);
1795 return -ENOMEM;
1796 }
1797
1798 for (i = 0; i < num_irqs; ++i) {
1799 int irq = platform_get_irq(pdev, i);
1800 if (irq < 0) {
1801 dev_err(dev, "failed to get irq index %d\n", i);
1802 return -ENODEV;
1803 }
1804 smmu->irqs[i] = irq;
1805 }
1806
1807 i = 0;
1808 smmu->masters = RB_ROOT;
1809 while (!of_parse_phandle_with_args(dev->of_node, "mmu-masters",
1810 "#stream-id-cells", i,
1811 &masterspec)) {
1812 err = register_smmu_master(smmu, dev, &masterspec);
1813 if (err) {
1814 dev_err(dev, "failed to add master %s\n",
1815 masterspec.np->name);
1816 goto out_put_masters;
1817 }
1818
1819 i++;
1820 }
1821 dev_notice(dev, "registered %d master devices\n", i);
1822
1823 if ((dev_node = of_parse_phandle(dev->of_node, "smmu-parent", 0)))
1824 smmu->parent_of_node = dev_node;
1825
1826 err = arm_smmu_device_cfg_probe(smmu);
1827 if (err)
1828 goto out_put_parent;
1829
1830 if (smmu->version > 1 &&
1831 smmu->num_context_banks != smmu->num_context_irqs) {
1832 dev_err(dev,
1833 "found only %d context interrupt(s) but %d required\n",
1834 smmu->num_context_irqs, smmu->num_context_banks);
1835 goto out_put_parent;
1836 }
1837
1838 arm_smmu_device_reset(smmu);
1839
1840 for (i = 0; i < smmu->num_global_irqs; ++i) {
1841 err = request_irq(smmu->irqs[i],
1842 arm_smmu_global_fault,
1843 IRQF_SHARED,
1844 "arm-smmu global fault",
1845 smmu);
1846 if (err) {
1847 dev_err(dev, "failed to request global IRQ %d (%u)\n",
1848 i, smmu->irqs[i]);
1849 goto out_free_irqs;
1850 }
1851 }
1852
1853 INIT_LIST_HEAD(&smmu->list);
1854 spin_lock(&arm_smmu_devices_lock);
1855 list_add(&smmu->list, &arm_smmu_devices);
1856 spin_unlock(&arm_smmu_devices_lock);
1857 return 0;
1858
1859 out_free_irqs:
1860 while (i--)
1861 free_irq(smmu->irqs[i], smmu);
1862
1863 out_put_parent:
1864 if (smmu->parent_of_node)
1865 of_node_put(smmu->parent_of_node);
1866
1867 out_put_masters:
1868 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1869 struct arm_smmu_master *master;
1870 master = container_of(node, struct arm_smmu_master, node);
1871 of_node_put(master->of_node);
1872 }
1873
1874 return err;
1875 }
1876
1877 static int arm_smmu_device_remove(struct platform_device *pdev)
1878 {
1879 int i;
1880 struct device *dev = &pdev->dev;
1881 struct arm_smmu_device *curr, *smmu = NULL;
1882 struct rb_node *node;
1883
1884 spin_lock(&arm_smmu_devices_lock);
1885 list_for_each_entry(curr, &arm_smmu_devices, list) {
1886 if (curr->dev == dev) {
1887 smmu = curr;
1888 list_del(&smmu->list);
1889 break;
1890 }
1891 }
1892 spin_unlock(&arm_smmu_devices_lock);
1893
1894 if (!smmu)
1895 return -ENODEV;
1896
1897 if (smmu->parent_of_node)
1898 of_node_put(smmu->parent_of_node);
1899
1900 for (node = rb_first(&smmu->masters); node; node = rb_next(node)) {
1901 struct arm_smmu_master *master;
1902 master = container_of(node, struct arm_smmu_master, node);
1903 of_node_put(master->of_node);
1904 }
1905
1906 if (!bitmap_empty(smmu->vmid_map, ARM_SMMU_NUM_VMIDS))
1907 dev_err(dev, "removing device with active domains!\n");
1908
1909 for (i = 0; i < smmu->num_global_irqs; ++i)
1910 free_irq(smmu->irqs[i], smmu);
1911
1912 /* Turn the thing off */
1913 writel(sCR0_CLIENTPD, ARM_SMMU_GR0(smmu) + ARM_SMMU_GR0_sCR0);
1914 return 0;
1915 }
1916
1917 #ifdef CONFIG_OF
1918 static struct of_device_id arm_smmu_of_match[] = {
1919 { .compatible = "arm,smmu-v1", },
1920 { .compatible = "arm,smmu-v2", },
1921 { .compatible = "arm,mmu-400", },
1922 { .compatible = "arm,mmu-500", },
1923 { },
1924 };
1925 MODULE_DEVICE_TABLE(of, arm_smmu_of_match);
1926 #endif
1927
1928 static struct platform_driver arm_smmu_driver = {
1929 .driver = {
1930 .owner = THIS_MODULE,
1931 .name = "arm-smmu",
1932 .of_match_table = of_match_ptr(arm_smmu_of_match),
1933 },
1934 .probe = arm_smmu_device_dt_probe,
1935 .remove = arm_smmu_device_remove,
1936 };
1937
1938 static int __init arm_smmu_init(void)
1939 {
1940 int ret;
1941
1942 ret = platform_driver_register(&arm_smmu_driver);
1943 if (ret)
1944 return ret;
1945
1946 /* Oh, for a proper bus abstraction */
1947 if (!iommu_present(&platform_bus_type));
1948 bus_set_iommu(&platform_bus_type, &arm_smmu_ops);
1949
1950 if (!iommu_present(&amba_bustype));
1951 bus_set_iommu(&amba_bustype, &arm_smmu_ops);
1952
1953 return 0;
1954 }
1955
1956 static void __exit arm_smmu_exit(void)
1957 {
1958 return platform_driver_unregister(&arm_smmu_driver);
1959 }
1960
1961 module_init(arm_smmu_init);
1962 module_exit(arm_smmu_exit);
1963
1964 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
1965 MODULE_AUTHOR("Will Deacon <will.deacon@arm.com>");
1966 MODULE_LICENSE("GPL v2");
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