2 * A fairly generic DMA-API to IOMMU-API glue layer.
4 * Copyright (C) 2014-2015 ARM Ltd.
6 * based in part on arch/arm/mm/dma-mapping.c:
7 * Copyright (C) 2000-2004 Russell King
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
22 #include <linux/acpi_iort.h>
23 #include <linux/device.h>
24 #include <linux/dma-iommu.h>
25 #include <linux/gfp.h>
26 #include <linux/huge_mm.h>
27 #include <linux/iommu.h>
28 #include <linux/iova.h>
29 #include <linux/irq.h>
31 #include <linux/pci.h>
32 #include <linux/scatterlist.h>
33 #include <linux/vmalloc.h>
35 struct iommu_dma_msi_page
{
36 struct list_head list
;
41 enum iommu_dma_cookie_type
{
42 IOMMU_DMA_IOVA_COOKIE
,
46 struct iommu_dma_cookie
{
47 enum iommu_dma_cookie_type type
;
49 /* Full allocator for IOMMU_DMA_IOVA_COOKIE */
50 struct iova_domain iovad
;
51 /* Trivial linear page allocator for IOMMU_DMA_MSI_COOKIE */
54 struct list_head msi_page_list
;
57 /* Domain for flush queue callback; NULL if flush queue not in use */
58 struct iommu_domain
*fq_domain
;
61 static inline size_t cookie_msi_granule(struct iommu_dma_cookie
*cookie
)
63 if (cookie
->type
== IOMMU_DMA_IOVA_COOKIE
)
64 return cookie
->iovad
.granule
;
68 static struct iommu_dma_cookie
*cookie_alloc(enum iommu_dma_cookie_type type
)
70 struct iommu_dma_cookie
*cookie
;
72 cookie
= kzalloc(sizeof(*cookie
), GFP_KERNEL
);
74 spin_lock_init(&cookie
->msi_lock
);
75 INIT_LIST_HEAD(&cookie
->msi_page_list
);
81 int iommu_dma_init(void)
83 return iova_cache_get();
87 * iommu_get_dma_cookie - Acquire DMA-API resources for a domain
88 * @domain: IOMMU domain to prepare for DMA-API usage
90 * IOMMU drivers should normally call this from their domain_alloc
91 * callback when domain->type == IOMMU_DOMAIN_DMA.
93 int iommu_get_dma_cookie(struct iommu_domain
*domain
)
95 if (domain
->iova_cookie
)
98 domain
->iova_cookie
= cookie_alloc(IOMMU_DMA_IOVA_COOKIE
);
99 if (!domain
->iova_cookie
)
104 EXPORT_SYMBOL(iommu_get_dma_cookie
);
107 * iommu_get_msi_cookie - Acquire just MSI remapping resources
108 * @domain: IOMMU domain to prepare
109 * @base: Start address of IOVA region for MSI mappings
111 * Users who manage their own IOVA allocation and do not want DMA API support,
112 * but would still like to take advantage of automatic MSI remapping, can use
113 * this to initialise their own domain appropriately. Users should reserve a
114 * contiguous IOVA region, starting at @base, large enough to accommodate the
115 * number of PAGE_SIZE mappings necessary to cover every MSI doorbell address
116 * used by the devices attached to @domain.
118 int iommu_get_msi_cookie(struct iommu_domain
*domain
, dma_addr_t base
)
120 struct iommu_dma_cookie
*cookie
;
122 if (domain
->type
!= IOMMU_DOMAIN_UNMANAGED
)
125 if (domain
->iova_cookie
)
128 cookie
= cookie_alloc(IOMMU_DMA_MSI_COOKIE
);
132 cookie
->msi_iova
= base
;
133 domain
->iova_cookie
= cookie
;
136 EXPORT_SYMBOL(iommu_get_msi_cookie
);
139 * iommu_put_dma_cookie - Release a domain's DMA mapping resources
140 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie() or
141 * iommu_get_msi_cookie()
143 * IOMMU drivers should normally call this from their domain_free callback.
145 void iommu_put_dma_cookie(struct iommu_domain
*domain
)
147 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
148 struct iommu_dma_msi_page
*msi
, *tmp
;
153 if (cookie
->type
== IOMMU_DMA_IOVA_COOKIE
&& cookie
->iovad
.granule
)
154 put_iova_domain(&cookie
->iovad
);
156 list_for_each_entry_safe(msi
, tmp
, &cookie
->msi_page_list
, list
) {
157 list_del(&msi
->list
);
161 domain
->iova_cookie
= NULL
;
163 EXPORT_SYMBOL(iommu_put_dma_cookie
);
166 * iommu_dma_get_resv_regions - Reserved region driver helper
167 * @dev: Device from iommu_get_resv_regions()
168 * @list: Reserved region list from iommu_get_resv_regions()
170 * IOMMU drivers can use this to implement their .get_resv_regions callback
171 * for general non-IOMMU-specific reservations. Currently, this covers GICv3
172 * ITS region reservation on ACPI based ARM platforms that may require HW MSI
175 void iommu_dma_get_resv_regions(struct device
*dev
, struct list_head
*list
)
178 if (!is_of_node(dev_iommu_fwspec_get(dev
)->iommu_fwnode
))
179 iort_iommu_msi_get_resv_regions(dev
, list
);
182 EXPORT_SYMBOL(iommu_dma_get_resv_regions
);
184 static int cookie_init_hw_msi_region(struct iommu_dma_cookie
*cookie
,
185 phys_addr_t start
, phys_addr_t end
)
187 struct iova_domain
*iovad
= &cookie
->iovad
;
188 struct iommu_dma_msi_page
*msi_page
;
191 start
-= iova_offset(iovad
, start
);
192 num_pages
= iova_align(iovad
, end
- start
) >> iova_shift(iovad
);
194 msi_page
= kcalloc(num_pages
, sizeof(*msi_page
), GFP_KERNEL
);
198 for (i
= 0; i
< num_pages
; i
++) {
199 msi_page
[i
].phys
= start
;
200 msi_page
[i
].iova
= start
;
201 INIT_LIST_HEAD(&msi_page
[i
].list
);
202 list_add(&msi_page
[i
].list
, &cookie
->msi_page_list
);
203 start
+= iovad
->granule
;
209 static int iova_reserve_pci_windows(struct pci_dev
*dev
,
210 struct iova_domain
*iovad
)
212 struct pci_host_bridge
*bridge
= pci_find_host_bridge(dev
->bus
);
213 struct resource_entry
*window
;
214 unsigned long lo
, hi
;
215 phys_addr_t start
= 0, end
;
217 resource_list_for_each_entry(window
, &bridge
->windows
) {
218 if (resource_type(window
->res
) != IORESOURCE_MEM
)
221 lo
= iova_pfn(iovad
, window
->res
->start
- window
->offset
);
222 hi
= iova_pfn(iovad
, window
->res
->end
- window
->offset
);
223 reserve_iova(iovad
, lo
, hi
);
226 /* Get reserved DMA windows from host bridge */
227 resource_list_for_each_entry(window
, &bridge
->dma_ranges
) {
228 end
= window
->res
->start
- window
->offset
;
231 lo
= iova_pfn(iovad
, start
);
232 hi
= iova_pfn(iovad
, end
);
233 reserve_iova(iovad
, lo
, hi
);
235 /* dma_ranges list should be sorted */
236 dev_err(&dev
->dev
, "Failed to reserve IOVA\n");
240 start
= window
->res
->end
- window
->offset
+ 1;
241 /* If window is last entry */
242 if (window
->node
.next
== &bridge
->dma_ranges
&&
243 end
!= ~(dma_addr_t
)0) {
244 end
= ~(dma_addr_t
)0;
252 static int iova_reserve_iommu_regions(struct device
*dev
,
253 struct iommu_domain
*domain
)
255 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
256 struct iova_domain
*iovad
= &cookie
->iovad
;
257 struct iommu_resv_region
*region
;
258 LIST_HEAD(resv_regions
);
261 if (dev_is_pci(dev
)) {
262 ret
= iova_reserve_pci_windows(to_pci_dev(dev
), iovad
);
267 iommu_get_resv_regions(dev
, &resv_regions
);
268 list_for_each_entry(region
, &resv_regions
, list
) {
269 unsigned long lo
, hi
;
271 /* We ARE the software that manages these! */
272 if (region
->type
== IOMMU_RESV_SW_MSI
)
275 lo
= iova_pfn(iovad
, region
->start
);
276 hi
= iova_pfn(iovad
, region
->start
+ region
->length
- 1);
277 reserve_iova(iovad
, lo
, hi
);
279 if (region
->type
== IOMMU_RESV_MSI
)
280 ret
= cookie_init_hw_msi_region(cookie
, region
->start
,
281 region
->start
+ region
->length
);
285 iommu_put_resv_regions(dev
, &resv_regions
);
290 static void iommu_dma_flush_iotlb_all(struct iova_domain
*iovad
)
292 struct iommu_dma_cookie
*cookie
;
293 struct iommu_domain
*domain
;
295 cookie
= container_of(iovad
, struct iommu_dma_cookie
, iovad
);
296 domain
= cookie
->fq_domain
;
298 * The IOMMU driver supporting DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
299 * implies that ops->flush_iotlb_all must be non-NULL.
301 domain
->ops
->flush_iotlb_all(domain
);
305 * iommu_dma_init_domain - Initialise a DMA mapping domain
306 * @domain: IOMMU domain previously prepared by iommu_get_dma_cookie()
307 * @base: IOVA at which the mappable address space starts
308 * @size: Size of IOVA space
309 * @dev: Device the domain is being initialised for
311 * @base and @size should be exact multiples of IOMMU page granularity to
312 * avoid rounding surprises. If necessary, we reserve the page at address 0
313 * to ensure it is an invalid IOVA. It is safe to reinitialise a domain, but
314 * any change which could make prior IOVAs invalid will fail.
316 int iommu_dma_init_domain(struct iommu_domain
*domain
, dma_addr_t base
,
317 u64 size
, struct device
*dev
)
319 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
320 struct iova_domain
*iovad
= &cookie
->iovad
;
321 unsigned long order
, base_pfn
;
324 if (!cookie
|| cookie
->type
!= IOMMU_DMA_IOVA_COOKIE
)
327 /* Use the smallest supported page size for IOVA granularity */
328 order
= __ffs(domain
->pgsize_bitmap
);
329 base_pfn
= max_t(unsigned long, 1, base
>> order
);
331 /* Check the domain allows at least some access to the device... */
332 if (domain
->geometry
.force_aperture
) {
333 if (base
> domain
->geometry
.aperture_end
||
334 base
+ size
<= domain
->geometry
.aperture_start
) {
335 pr_warn("specified DMA range outside IOMMU capability\n");
338 /* ...then finally give it a kicking to make sure it fits */
339 base_pfn
= max_t(unsigned long, base_pfn
,
340 domain
->geometry
.aperture_start
>> order
);
343 /* start_pfn is always nonzero for an already-initialised domain */
344 if (iovad
->start_pfn
) {
345 if (1UL << order
!= iovad
->granule
||
346 base_pfn
!= iovad
->start_pfn
) {
347 pr_warn("Incompatible range for DMA domain\n");
354 init_iova_domain(iovad
, 1UL << order
, base_pfn
);
356 if (!cookie
->fq_domain
&& !iommu_domain_get_attr(domain
,
357 DOMAIN_ATTR_DMA_USE_FLUSH_QUEUE
, &attr
) && attr
) {
358 cookie
->fq_domain
= domain
;
359 init_iova_flush_queue(iovad
, iommu_dma_flush_iotlb_all
, NULL
);
365 return iova_reserve_iommu_regions(dev
, domain
);
367 EXPORT_SYMBOL(iommu_dma_init_domain
);
370 * dma_info_to_prot - Translate DMA API directions and attributes to IOMMU API
372 * @dir: Direction of DMA transfer
373 * @coherent: Is the DMA master cache-coherent?
374 * @attrs: DMA attributes for the mapping
376 * Return: corresponding IOMMU API page protection flags
378 int dma_info_to_prot(enum dma_data_direction dir
, bool coherent
,
381 int prot
= coherent
? IOMMU_CACHE
: 0;
383 if (attrs
& DMA_ATTR_PRIVILEGED
)
387 case DMA_BIDIRECTIONAL
:
388 return prot
| IOMMU_READ
| IOMMU_WRITE
;
390 return prot
| IOMMU_READ
;
391 case DMA_FROM_DEVICE
:
392 return prot
| IOMMU_WRITE
;
398 static dma_addr_t
iommu_dma_alloc_iova(struct iommu_domain
*domain
,
399 size_t size
, dma_addr_t dma_limit
, struct device
*dev
)
401 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
402 struct iova_domain
*iovad
= &cookie
->iovad
;
403 unsigned long shift
, iova_len
, iova
= 0;
405 if (cookie
->type
== IOMMU_DMA_MSI_COOKIE
) {
406 cookie
->msi_iova
+= size
;
407 return cookie
->msi_iova
- size
;
410 shift
= iova_shift(iovad
);
411 iova_len
= size
>> shift
;
413 * Freeing non-power-of-two-sized allocations back into the IOVA caches
414 * will come back to bite us badly, so we have to waste a bit of space
415 * rounding up anything cacheable to make sure that can't happen. The
416 * order of the unadjusted size will still match upon freeing.
418 if (iova_len
< (1 << (IOVA_RANGE_CACHE_MAX_SIZE
- 1)))
419 iova_len
= roundup_pow_of_two(iova_len
);
421 if (dev
->bus_dma_mask
)
422 dma_limit
&= dev
->bus_dma_mask
;
424 if (domain
->geometry
.force_aperture
)
425 dma_limit
= min(dma_limit
, domain
->geometry
.aperture_end
);
427 /* Try to get PCI devices a SAC address */
428 if (dma_limit
> DMA_BIT_MASK(32) && dev_is_pci(dev
))
429 iova
= alloc_iova_fast(iovad
, iova_len
,
430 DMA_BIT_MASK(32) >> shift
, false);
433 iova
= alloc_iova_fast(iovad
, iova_len
, dma_limit
>> shift
,
436 return (dma_addr_t
)iova
<< shift
;
439 static void iommu_dma_free_iova(struct iommu_dma_cookie
*cookie
,
440 dma_addr_t iova
, size_t size
)
442 struct iova_domain
*iovad
= &cookie
->iovad
;
444 /* The MSI case is only ever cleaning up its most recent allocation */
445 if (cookie
->type
== IOMMU_DMA_MSI_COOKIE
)
446 cookie
->msi_iova
-= size
;
447 else if (cookie
->fq_domain
) /* non-strict mode */
448 queue_iova(iovad
, iova_pfn(iovad
, iova
),
449 size
>> iova_shift(iovad
), 0);
451 free_iova_fast(iovad
, iova_pfn(iovad
, iova
),
452 size
>> iova_shift(iovad
));
455 static void __iommu_dma_unmap(struct iommu_domain
*domain
, dma_addr_t dma_addr
,
458 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
459 struct iova_domain
*iovad
= &cookie
->iovad
;
460 size_t iova_off
= iova_offset(iovad
, dma_addr
);
462 dma_addr
-= iova_off
;
463 size
= iova_align(iovad
, size
+ iova_off
);
465 WARN_ON(iommu_unmap_fast(domain
, dma_addr
, size
) != size
);
466 if (!cookie
->fq_domain
)
467 iommu_tlb_sync(domain
);
468 iommu_dma_free_iova(cookie
, dma_addr
, size
);
471 static void __iommu_dma_free_pages(struct page
**pages
, int count
)
474 __free_page(pages
[count
]);
478 static struct page
**__iommu_dma_alloc_pages(struct device
*dev
,
479 unsigned int count
, unsigned long order_mask
, gfp_t gfp
)
482 unsigned int i
= 0, nid
= dev_to_node(dev
);
484 order_mask
&= (2U << MAX_ORDER
) - 1;
488 pages
= kvzalloc(count
* sizeof(*pages
), GFP_KERNEL
);
492 /* IOMMU can map any pages, so himem can also be used here */
493 gfp
|= __GFP_NOWARN
| __GFP_HIGHMEM
;
496 struct page
*page
= NULL
;
497 unsigned int order_size
;
500 * Higher-order allocations are a convenience rather
501 * than a necessity, hence using __GFP_NORETRY until
502 * falling back to minimum-order allocations.
504 for (order_mask
&= (2U << __fls(count
)) - 1;
505 order_mask
; order_mask
&= ~order_size
) {
506 unsigned int order
= __fls(order_mask
);
507 gfp_t alloc_flags
= gfp
;
509 order_size
= 1U << order
;
510 if (order_mask
> order_size
)
511 alloc_flags
|= __GFP_NORETRY
;
512 page
= alloc_pages_node(nid
, alloc_flags
, order
);
517 if (!PageCompound(page
)) {
518 split_page(page
, order
);
520 } else if (!split_huge_page(page
)) {
523 __free_pages(page
, order
);
526 __iommu_dma_free_pages(pages
, i
);
537 * iommu_dma_free - Free a buffer allocated by iommu_dma_alloc()
538 * @dev: Device which owns this buffer
539 * @pages: Array of buffer pages as returned by iommu_dma_alloc()
540 * @size: Size of buffer in bytes
541 * @handle: DMA address of buffer
543 * Frees both the pages associated with the buffer, and the array
546 void iommu_dma_free(struct device
*dev
, struct page
**pages
, size_t size
,
549 __iommu_dma_unmap(iommu_get_dma_domain(dev
), *handle
, size
);
550 __iommu_dma_free_pages(pages
, PAGE_ALIGN(size
) >> PAGE_SHIFT
);
551 *handle
= DMA_MAPPING_ERROR
;
555 * iommu_dma_alloc - Allocate and map a buffer contiguous in IOVA space
556 * @dev: Device to allocate memory for. Must be a real device
557 * attached to an iommu_dma_domain
558 * @size: Size of buffer in bytes
559 * @gfp: Allocation flags
560 * @attrs: DMA attributes for this allocation
561 * @prot: IOMMU mapping flags
562 * @handle: Out argument for allocated DMA handle
563 * @flush_page: Arch callback which must ensure PAGE_SIZE bytes from the
564 * given VA/PA are visible to the given non-coherent device.
566 * If @size is less than PAGE_SIZE, then a full CPU page will be allocated,
567 * but an IOMMU which supports smaller pages might not map the whole thing.
569 * Return: Array of struct page pointers describing the buffer,
570 * or NULL on failure.
572 struct page
**iommu_dma_alloc(struct device
*dev
, size_t size
, gfp_t gfp
,
573 unsigned long attrs
, int prot
, dma_addr_t
*handle
,
574 void (*flush_page
)(struct device
*, const void *, phys_addr_t
))
576 struct iommu_domain
*domain
= iommu_get_dma_domain(dev
);
577 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
578 struct iova_domain
*iovad
= &cookie
->iovad
;
582 unsigned int count
, min_size
, alloc_sizes
= domain
->pgsize_bitmap
;
584 *handle
= DMA_MAPPING_ERROR
;
586 min_size
= alloc_sizes
& -alloc_sizes
;
587 if (min_size
< PAGE_SIZE
) {
588 min_size
= PAGE_SIZE
;
589 alloc_sizes
|= PAGE_SIZE
;
591 size
= ALIGN(size
, min_size
);
593 if (attrs
& DMA_ATTR_ALLOC_SINGLE_PAGES
)
594 alloc_sizes
= min_size
;
596 count
= PAGE_ALIGN(size
) >> PAGE_SHIFT
;
597 pages
= __iommu_dma_alloc_pages(dev
, count
, alloc_sizes
>> PAGE_SHIFT
,
602 size
= iova_align(iovad
, size
);
603 iova
= iommu_dma_alloc_iova(domain
, size
, dev
->coherent_dma_mask
, dev
);
607 if (sg_alloc_table_from_pages(&sgt
, pages
, count
, 0, size
, GFP_KERNEL
))
610 if (!(prot
& IOMMU_CACHE
)) {
611 struct sg_mapping_iter miter
;
613 * The CPU-centric flushing implied by SG_MITER_TO_SG isn't
614 * sufficient here, so skip it by using the "wrong" direction.
616 sg_miter_start(&miter
, sgt
.sgl
, sgt
.orig_nents
, SG_MITER_FROM_SG
);
617 while (sg_miter_next(&miter
))
618 flush_page(dev
, miter
.addr
, page_to_phys(miter
.page
));
619 sg_miter_stop(&miter
);
622 if (iommu_map_sg(domain
, iova
, sgt
.sgl
, sgt
.orig_nents
, prot
)
633 iommu_dma_free_iova(cookie
, iova
, size
);
635 __iommu_dma_free_pages(pages
, count
);
640 * iommu_dma_mmap - Map a buffer into provided user VMA
641 * @pages: Array representing buffer from iommu_dma_alloc()
642 * @size: Size of buffer in bytes
643 * @vma: VMA describing requested userspace mapping
645 * Maps the pages of the buffer in @pages into @vma. The caller is responsible
646 * for verifying the correct size and protection of @vma beforehand.
649 int iommu_dma_mmap(struct page
**pages
, size_t size
, struct vm_area_struct
*vma
)
651 return vm_map_pages(vma
, pages
, PAGE_ALIGN(size
) >> PAGE_SHIFT
);
654 static dma_addr_t
__iommu_dma_map(struct device
*dev
, phys_addr_t phys
,
655 size_t size
, int prot
, struct iommu_domain
*domain
)
657 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
661 if (cookie
->type
== IOMMU_DMA_IOVA_COOKIE
) {
662 iova_off
= iova_offset(&cookie
->iovad
, phys
);
663 size
= iova_align(&cookie
->iovad
, size
+ iova_off
);
666 iova
= iommu_dma_alloc_iova(domain
, size
, dma_get_mask(dev
), dev
);
668 return DMA_MAPPING_ERROR
;
670 if (iommu_map(domain
, iova
, phys
- iova_off
, size
, prot
)) {
671 iommu_dma_free_iova(cookie
, iova
, size
);
672 return DMA_MAPPING_ERROR
;
674 return iova
+ iova_off
;
677 dma_addr_t
iommu_dma_map_page(struct device
*dev
, struct page
*page
,
678 unsigned long offset
, size_t size
, int prot
)
680 return __iommu_dma_map(dev
, page_to_phys(page
) + offset
, size
, prot
,
681 iommu_get_dma_domain(dev
));
684 void iommu_dma_unmap_page(struct device
*dev
, dma_addr_t handle
, size_t size
,
685 enum dma_data_direction dir
, unsigned long attrs
)
687 __iommu_dma_unmap(iommu_get_dma_domain(dev
), handle
, size
);
691 * Prepare a successfully-mapped scatterlist to give back to the caller.
693 * At this point the segments are already laid out by iommu_dma_map_sg() to
694 * avoid individually crossing any boundaries, so we merely need to check a
695 * segment's start address to avoid concatenating across one.
697 static int __finalise_sg(struct device
*dev
, struct scatterlist
*sg
, int nents
,
700 struct scatterlist
*s
, *cur
= sg
;
701 unsigned long seg_mask
= dma_get_seg_boundary(dev
);
702 unsigned int cur_len
= 0, max_len
= dma_get_max_seg_size(dev
);
705 for_each_sg(sg
, s
, nents
, i
) {
706 /* Restore this segment's original unaligned fields first */
707 unsigned int s_iova_off
= sg_dma_address(s
);
708 unsigned int s_length
= sg_dma_len(s
);
709 unsigned int s_iova_len
= s
->length
;
711 s
->offset
+= s_iova_off
;
712 s
->length
= s_length
;
713 sg_dma_address(s
) = DMA_MAPPING_ERROR
;
717 * Now fill in the real DMA data. If...
718 * - there is a valid output segment to append to
719 * - and this segment starts on an IOVA page boundary
720 * - but doesn't fall at a segment boundary
721 * - and wouldn't make the resulting output segment too long
723 if (cur_len
&& !s_iova_off
&& (dma_addr
& seg_mask
) &&
724 (cur_len
+ s_length
<= max_len
)) {
725 /* ...then concatenate it with the previous one */
728 /* Otherwise start the next output segment */
734 sg_dma_address(cur
) = dma_addr
+ s_iova_off
;
737 sg_dma_len(cur
) = cur_len
;
738 dma_addr
+= s_iova_len
;
740 if (s_length
+ s_iova_off
< s_iova_len
)
747 * If mapping failed, then just restore the original list,
748 * but making sure the DMA fields are invalidated.
750 static void __invalidate_sg(struct scatterlist
*sg
, int nents
)
752 struct scatterlist
*s
;
755 for_each_sg(sg
, s
, nents
, i
) {
756 if (sg_dma_address(s
) != DMA_MAPPING_ERROR
)
757 s
->offset
+= sg_dma_address(s
);
759 s
->length
= sg_dma_len(s
);
760 sg_dma_address(s
) = DMA_MAPPING_ERROR
;
766 * The DMA API client is passing in a scatterlist which could describe
767 * any old buffer layout, but the IOMMU API requires everything to be
768 * aligned to IOMMU pages. Hence the need for this complicated bit of
769 * impedance-matching, to be able to hand off a suitably-aligned list,
770 * but still preserve the original offsets and sizes for the caller.
772 int iommu_dma_map_sg(struct device
*dev
, struct scatterlist
*sg
,
775 struct iommu_domain
*domain
= iommu_get_dma_domain(dev
);
776 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
777 struct iova_domain
*iovad
= &cookie
->iovad
;
778 struct scatterlist
*s
, *prev
= NULL
;
781 unsigned long mask
= dma_get_seg_boundary(dev
);
785 * Work out how much IOVA space we need, and align the segments to
786 * IOVA granules for the IOMMU driver to handle. With some clever
787 * trickery we can modify the list in-place, but reversibly, by
788 * stashing the unaligned parts in the as-yet-unused DMA fields.
790 for_each_sg(sg
, s
, nents
, i
) {
791 size_t s_iova_off
= iova_offset(iovad
, s
->offset
);
792 size_t s_length
= s
->length
;
793 size_t pad_len
= (mask
- iova_len
+ 1) & mask
;
795 sg_dma_address(s
) = s_iova_off
;
796 sg_dma_len(s
) = s_length
;
797 s
->offset
-= s_iova_off
;
798 s_length
= iova_align(iovad
, s_length
+ s_iova_off
);
799 s
->length
= s_length
;
802 * Due to the alignment of our single IOVA allocation, we can
803 * depend on these assumptions about the segment boundary mask:
804 * - If mask size >= IOVA size, then the IOVA range cannot
805 * possibly fall across a boundary, so we don't care.
806 * - If mask size < IOVA size, then the IOVA range must start
807 * exactly on a boundary, therefore we can lay things out
808 * based purely on segment lengths without needing to know
809 * the actual addresses beforehand.
810 * - The mask must be a power of 2, so pad_len == 0 if
811 * iova_len == 0, thus we cannot dereference prev the first
812 * time through here (i.e. before it has a meaningful value).
814 if (pad_len
&& pad_len
< s_length
- 1) {
815 prev
->length
+= pad_len
;
819 iova_len
+= s_length
;
823 iova
= iommu_dma_alloc_iova(domain
, iova_len
, dma_get_mask(dev
), dev
);
828 * We'll leave any physical concatenation to the IOMMU driver's
829 * implementation - it knows better than we do.
831 if (iommu_map_sg(domain
, iova
, sg
, nents
, prot
) < iova_len
)
834 return __finalise_sg(dev
, sg
, nents
, iova
);
837 iommu_dma_free_iova(cookie
, iova
, iova_len
);
839 __invalidate_sg(sg
, nents
);
843 void iommu_dma_unmap_sg(struct device
*dev
, struct scatterlist
*sg
, int nents
,
844 enum dma_data_direction dir
, unsigned long attrs
)
846 dma_addr_t start
, end
;
847 struct scatterlist
*tmp
;
850 * The scatterlist segments are mapped into a single
851 * contiguous IOVA allocation, so this is incredibly easy.
853 start
= sg_dma_address(sg
);
854 for_each_sg(sg_next(sg
), tmp
, nents
- 1, i
) {
855 if (sg_dma_len(tmp
) == 0)
859 end
= sg_dma_address(sg
) + sg_dma_len(sg
);
860 __iommu_dma_unmap(iommu_get_dma_domain(dev
), start
, end
- start
);
863 dma_addr_t
iommu_dma_map_resource(struct device
*dev
, phys_addr_t phys
,
864 size_t size
, enum dma_data_direction dir
, unsigned long attrs
)
866 return __iommu_dma_map(dev
, phys
, size
,
867 dma_info_to_prot(dir
, false, attrs
) | IOMMU_MMIO
,
868 iommu_get_dma_domain(dev
));
871 void iommu_dma_unmap_resource(struct device
*dev
, dma_addr_t handle
,
872 size_t size
, enum dma_data_direction dir
, unsigned long attrs
)
874 __iommu_dma_unmap(iommu_get_dma_domain(dev
), handle
, size
);
877 static struct iommu_dma_msi_page
*iommu_dma_get_msi_page(struct device
*dev
,
878 phys_addr_t msi_addr
, struct iommu_domain
*domain
)
880 struct iommu_dma_cookie
*cookie
= domain
->iova_cookie
;
881 struct iommu_dma_msi_page
*msi_page
;
883 int prot
= IOMMU_WRITE
| IOMMU_NOEXEC
| IOMMU_MMIO
;
884 size_t size
= cookie_msi_granule(cookie
);
886 msi_addr
&= ~(phys_addr_t
)(size
- 1);
887 list_for_each_entry(msi_page
, &cookie
->msi_page_list
, list
)
888 if (msi_page
->phys
== msi_addr
)
891 msi_page
= kzalloc(sizeof(*msi_page
), GFP_ATOMIC
);
895 iova
= __iommu_dma_map(dev
, msi_addr
, size
, prot
, domain
);
896 if (iova
== DMA_MAPPING_ERROR
)
899 INIT_LIST_HEAD(&msi_page
->list
);
900 msi_page
->phys
= msi_addr
;
901 msi_page
->iova
= iova
;
902 list_add(&msi_page
->list
, &cookie
->msi_page_list
);
910 void iommu_dma_map_msi_msg(int irq
, struct msi_msg
*msg
)
912 struct device
*dev
= msi_desc_to_dev(irq_get_msi_desc(irq
));
913 struct iommu_domain
*domain
= iommu_get_domain_for_dev(dev
);
914 struct iommu_dma_cookie
*cookie
;
915 struct iommu_dma_msi_page
*msi_page
;
916 phys_addr_t msi_addr
= (u64
)msg
->address_hi
<< 32 | msg
->address_lo
;
919 if (!domain
|| !domain
->iova_cookie
)
922 cookie
= domain
->iova_cookie
;
925 * We disable IRQs to rule out a possible inversion against
926 * irq_desc_lock if, say, someone tries to retarget the affinity
927 * of an MSI from within an IPI handler.
929 spin_lock_irqsave(&cookie
->msi_lock
, flags
);
930 msi_page
= iommu_dma_get_msi_page(dev
, msi_addr
, domain
);
931 spin_unlock_irqrestore(&cookie
->msi_lock
, flags
);
933 if (WARN_ON(!msi_page
)) {
935 * We're called from a void callback, so the best we can do is
936 * 'fail' by filling the message with obviously bogus values.
937 * Since we got this far due to an IOMMU being present, it's
938 * not like the existing address would have worked anyway...
940 msg
->address_hi
= ~0U;
941 msg
->address_lo
= ~0U;
944 msg
->address_hi
= upper_32_bits(msi_page
->iova
);
945 msg
->address_lo
&= cookie_msi_granule(cookie
) - 1;
946 msg
->address_lo
+= lower_32_bits(msi_page
->iova
);