drivers/iommu/intel-svm.c

   1 /*
   2  * Copyright © 2015 Intel Corporation.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * Authors: David Woodhouse <dwmw2@infradead.org>
  14  */
  15
  16 #include <linux/intel-iommu.h>
  17 #include <linux/mmu_notifier.h>
  18 #include <linux/sched.h>
  19 #include <linux/sched/mm.h>
  20 #include <linux/slab.h>
  21 #include <linux/intel-svm.h>
  22 #include <linux/rculist.h>
  23 #include <linux/pci.h>
  24 #include <linux/pci-ats.h>
  25 #include <linux/dmar.h>
  26 #include <linux/interrupt.h>
  27
  28 static irqreturn_t prq_event_thread(int irq, void *d);
  29
  30 struct pasid_entry {
  31         u64 val;
  32 };
  33
  34 struct pasid_state_entry {
  35         u64 val;
  36 };
  37
  38 int intel_svm_alloc_pasid_tables(struct intel_iommu *iommu)
  39 {
  40         struct page *pages;
  41         int order;
  42
  43         /* Start at 2 because it's defined as 2^(1+PSS) */
  44         iommu->pasid_max = 2 << ecap_pss(iommu->ecap);
  45
  46         /* Eventually I'm promised we will get a multi-level PASID table
  47          * and it won't have to be physically contiguous. Until then,
  48          * limit the size because 8MiB contiguous allocations can be hard
  49          * to come by. The limit of 0x20000, which is 1MiB for each of
  50          * the PASID and PASID-state tables, is somewhat arbitrary. */
  51         if (iommu->pasid_max > 0x20000)
  52                 iommu->pasid_max = 0x20000;
  53
  54         order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  55         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  56         if (!pages) {
  57                 pr_warn("IOMMU: %s: Failed to allocate PASID table\n",
  58                         iommu->name);
  59                 return -ENOMEM;
  60         }
  61         iommu->pasid_table = page_address(pages);
  62         pr_info("%s: Allocated order %d PASID table.\n", iommu->name, order);
  63
  64         if (ecap_dis(iommu->ecap)) {
  65                 /* Just making it explicit... */
  66                 BUILD_BUG_ON(sizeof(struct pasid_entry) != sizeof(struct pasid_state_entry));
  67                 pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, order);
  68                 if (pages)
  69                         iommu->pasid_state_table = page_address(pages);
  70                 else
  71                         pr_warn("IOMMU: %s: Failed to allocate PASID state table\n",
  72                                 iommu->name);
  73         }
  74
  75         idr_init(&iommu->pasid_idr);
  76
  77         return 0;
  78 }
  79
  80 int intel_svm_free_pasid_tables(struct intel_iommu *iommu)
  81 {
  82         int order = get_order(sizeof(struct pasid_entry) * iommu->pasid_max);
  83
  84         if (iommu->pasid_table) {
  85                 free_pages((unsigned long)iommu->pasid_table, order);
  86                 iommu->pasid_table = NULL;
  87         }
  88         if (iommu->pasid_state_table) {
  89                 free_pages((unsigned long)iommu->pasid_state_table, order);
  90                 iommu->pasid_state_table = NULL;
  91         }
  92         idr_destroy(&iommu->pasid_idr);
  93         return 0;
  94 }
  95
  96 #define PRQ_ORDER 0
  97
  98 int intel_svm_enable_prq(struct intel_iommu *iommu)
  99 {
 100         struct page *pages;
 101         int irq, ret;
 102
 103         pages = alloc_pages(GFP_KERNEL | __GFP_ZERO, PRQ_ORDER);
 104         if (!pages) {
 105                 pr_warn("IOMMU: %s: Failed to allocate page request queue\n",
 106                         iommu->name);
 107                 return -ENOMEM;
 108         }
 109         iommu->prq = page_address(pages);
 110
 111         irq = dmar_alloc_hwirq(DMAR_UNITS_SUPPORTED + iommu->seq_id, iommu->node, iommu);
 112         if (irq <= 0) {
 113                 pr_err("IOMMU: %s: Failed to create IRQ vector for page request queue\n",
 114                        iommu->name);
 115                 ret = -EINVAL;
 116         err:
 117                 free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 118                 iommu->prq = NULL;
 119                 return ret;
 120         }
 121         iommu->pr_irq = irq;
 122
 123         snprintf(iommu->prq_name, sizeof(iommu->prq_name), "dmar%d-prq", iommu->seq_id);
 124
 125         ret = request_threaded_irq(irq, NULL, prq_event_thread, IRQF_ONESHOT,
 126                                    iommu->prq_name, iommu);
 127         if (ret) {
 128                 pr_err("IOMMU: %s: Failed to request IRQ for page request queue\n",
 129                        iommu->name);
 130                 dmar_free_hwirq(irq);
 131                 goto err;
 132         }
 133         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 134         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 135         dmar_writeq(iommu->reg + DMAR_PQA_REG, virt_to_phys(iommu->prq) | PRQ_ORDER);
 136
 137         return 0;
 138 }
 139
 140 int intel_svm_finish_prq(struct intel_iommu *iommu)
 141 {
 142         dmar_writeq(iommu->reg + DMAR_PQH_REG, 0ULL);
 143         dmar_writeq(iommu->reg + DMAR_PQT_REG, 0ULL);
 144         dmar_writeq(iommu->reg + DMAR_PQA_REG, 0ULL);
 145
 146         free_irq(iommu->pr_irq, iommu);
 147         dmar_free_hwirq(iommu->pr_irq);
 148         iommu->pr_irq = 0;
 149
 150         free_pages((unsigned long)iommu->prq, PRQ_ORDER);
 151         iommu->prq = NULL;
 152
 153         return 0;
 154 }
 155
 156 static void intel_flush_svm_range_dev (struct intel_svm *svm, struct intel_svm_dev *sdev,
 157                                        unsigned long address, unsigned long pages, int ih, int gl)
 158 {
 159         struct qi_desc desc;
 160
 161         if (pages == -1) {
 162                 /* For global kernel pages we have to flush them in *all* PASIDs
 163                  * because that's the only option the hardware gives us. Despite
 164                  * the fact that they are actually only accessible through one. */
 165                 if (gl)
 166                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 167                                 QI_EIOTLB_GRAN(QI_GRAN_ALL_ALL) | QI_EIOTLB_TYPE;
 168                 else
 169                         desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 170                                 QI_EIOTLB_GRAN(QI_GRAN_NONG_PASID) | QI_EIOTLB_TYPE;
 171                 desc.high = 0;
 172         } else {
 173                 int mask = ilog2(__roundup_pow_of_two(pages));
 174
 175                 desc.low = QI_EIOTLB_PASID(svm->pasid) | QI_EIOTLB_DID(sdev->did) |
 176                         QI_EIOTLB_GRAN(QI_GRAN_PSI_PASID) | QI_EIOTLB_TYPE;
 177                 desc.high = QI_EIOTLB_ADDR(address) | QI_EIOTLB_GL(gl) |
 178                         QI_EIOTLB_IH(ih) | QI_EIOTLB_AM(mask);
 179         }
 180         qi_submit_sync(&desc, svm->iommu);
 181
 182         if (sdev->dev_iotlb) {
 183                 desc.low = QI_DEV_EIOTLB_PASID(svm->pasid) | QI_DEV_EIOTLB_SID(sdev->sid) |
 184                         QI_DEV_EIOTLB_QDEP(sdev->qdep) | QI_DEIOTLB_TYPE;
 185                 if (pages == -1) {
 186                         desc.high = QI_DEV_EIOTLB_ADDR(-1ULL >> 1) | QI_DEV_EIOTLB_SIZE;
 187                 } else if (pages > 1) {
 188                         /* The least significant zero bit indicates the size. So,
 189                          * for example, an "address" value of 0x12345f000 will
 190                          * flush from 0x123440000 to 0x12347ffff (256KiB). */
 191                         unsigned long last = address + ((unsigned long)(pages - 1) << VTD_PAGE_SHIFT);
 192                         unsigned long mask = __rounddown_pow_of_two(address ^ last);;
 193
 194                         desc.high = QI_DEV_EIOTLB_ADDR((address & ~mask) | (mask - 1)) | QI_DEV_EIOTLB_SIZE;
 195                 } else {
 196                         desc.high = QI_DEV_EIOTLB_ADDR(address);
 197                 }
 198                 qi_submit_sync(&desc, svm->iommu);
 199         }
 200 }
 201
 202 static void intel_flush_svm_range(struct intel_svm *svm, unsigned long address,
 203                                   unsigned long pages, int ih, int gl)
 204 {
 205         struct intel_svm_dev *sdev;
 206
 207         /* Try deferred invalidate if available */
 208         if (svm->iommu->pasid_state_table &&
 209             !cmpxchg64(&svm->iommu->pasid_state_table[svm->pasid].val, 0, 1ULL << 63))
 210                 return;
 211
 212         rcu_read_lock();
 213         list_for_each_entry_rcu(sdev, &svm->devs, list)
 214                 intel_flush_svm_range_dev(svm, sdev, address, pages, ih, gl);
 215         rcu_read_unlock();
 216 }
 217
 218 static void intel_change_pte(struct mmu_notifier *mn, struct mm_struct *mm,
 219                              unsigned long address, pte_t pte)
 220 {
 221         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 222
 223         intel_flush_svm_range(svm, address, 1, 1, 0);
 224 }
 225
 226 static void intel_invalidate_page(struct mmu_notifier *mn, struct mm_struct *mm,
 227                                   unsigned long address)
 228 {
 229         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 230
 231         intel_flush_svm_range(svm, address, 1, 1, 0);
 232 }
 233
 234 /* Pages have been freed at this point */
 235 static void intel_invalidate_range(struct mmu_notifier *mn,
 236                                    struct mm_struct *mm,
 237                                    unsigned long start, unsigned long end)
 238 {
 239         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 240
 241         intel_flush_svm_range(svm, start,
 242                               (end - start + PAGE_SIZE - 1) >> VTD_PAGE_SHIFT, 0, 0);
 243 }
 244
 245
 246 static void intel_flush_pasid_dev(struct intel_svm *svm, struct intel_svm_dev *sdev, int pasid)
 247 {
 248         struct qi_desc desc;
 249
 250         desc.high = 0;
 251         desc.low = QI_PC_TYPE | QI_PC_DID(sdev->did) | QI_PC_PASID_SEL | QI_PC_PASID(pasid);
 252
 253         qi_submit_sync(&desc, svm->iommu);
 254 }
 255
 256 static void intel_mm_release(struct mmu_notifier *mn, struct mm_struct *mm)
 257 {
 258         struct intel_svm *svm = container_of(mn, struct intel_svm, notifier);
 259         struct intel_svm_dev *sdev;
 260
 261         /* This might end up being called from exit_mmap(), *before* the page
 262          * tables are cleared. And __mmu_notifier_release() will delete us from
 263          * the list of notifiers so that our invalidate_range() callback doesn't
 264          * get called when the page tables are cleared. So we need to protect
 265          * against hardware accessing those page tables.
 266          *
 267          * We do it by clearing the entry in the PASID table and then flushing
 268          * the IOTLB and the PASID table caches. This might upset hardware;
 269          * perhaps we'll want to point the PASID to a dummy PGD (like the zero
 270          * page) so that we end up taking a fault that the hardware really
 271          * *has* to handle gracefully without affecting other processes.
 272          */
 273         svm->iommu->pasid_table[svm->pasid].val = 0;
 274         wmb();
 275
 276         rcu_read_lock();
 277         list_for_each_entry_rcu(sdev, &svm->devs, list) {
 278                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 279                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 280         }
 281         rcu_read_unlock();
 282
 283 }
 284
 285 static const struct mmu_notifier_ops intel_mmuops = {
 286         .release = intel_mm_release,
 287         .change_pte = intel_change_pte,
 288         .invalidate_page = intel_invalidate_page,
 289         .invalidate_range = intel_invalidate_range,
 290 };
 291
 292 static DEFINE_MUTEX(pasid_mutex);
 293
 294 int intel_svm_bind_mm(struct device *dev, int *pasid, int flags, struct svm_dev_ops *ops)
 295 {
 296         struct intel_iommu *iommu = intel_svm_device_to_iommu(dev);
 297         struct intel_svm_dev *sdev;
 298         struct intel_svm *svm = NULL;
 299         struct mm_struct *mm = NULL;
 300         int pasid_max;
 301         int ret;
 302
 303         if (WARN_ON(!iommu))
 304                 return -EINVAL;
 305
 306         if (dev_is_pci(dev)) {
 307                 pasid_max = pci_max_pasids(to_pci_dev(dev));
 308                 if (pasid_max < 0)
 309                         return -EINVAL;
 310         } else
 311                 pasid_max = 1 << 20;
 312
 313         if ((flags & SVM_FLAG_SUPERVISOR_MODE)) {
 314                 if (!ecap_srs(iommu->ecap))
 315                         return -EINVAL;
 316         } else if (pasid) {
 317                 mm = get_task_mm(current);
 318                 BUG_ON(!mm);
 319         }
 320
 321         mutex_lock(&pasid_mutex);
 322         if (pasid && !(flags & SVM_FLAG_PRIVATE_PASID)) {
 323                 int i;
 324
 325                 idr_for_each_entry(&iommu->pasid_idr, svm, i) {
 326                         if (svm->mm != mm ||
 327                             (svm->flags & SVM_FLAG_PRIVATE_PASID))
 328                                 continue;
 329
 330                         if (svm->pasid >= pasid_max) {
 331                                 dev_warn(dev,
 332                                          "Limited PASID width. Cannot use existing PASID %d\n",
 333                                          svm->pasid);
 334                                 ret = -ENOSPC;
 335                                 goto out;
 336                         }
 337
 338                         list_for_each_entry(sdev, &svm->devs, list) {
 339                                 if (dev == sdev->dev) {
 340                                         if (sdev->ops != ops) {
 341                                                 ret = -EBUSY;
 342                                                 goto out;
 343                                         }
 344                                         sdev->users++;
 345                                         goto success;
 346                                 }
 347                         }
 348
 349                         break;
 350                 }
 351         }
 352
 353         sdev = kzalloc(sizeof(*sdev), GFP_KERNEL);
 354         if (!sdev) {
 355                 ret = -ENOMEM;
 356                 goto out;
 357         }
 358         sdev->dev = dev;
 359
 360         ret = intel_iommu_enable_pasid(iommu, sdev);
 361         if (ret || !pasid) {
 362                 /* If they don't actually want to assign a PASID, this is
 363                  * just an enabling check/preparation. */
 364                 kfree(sdev);
 365                 goto out;
 366         }
 367         /* Finish the setup now we know we're keeping it */
 368         sdev->users = 1;
 369         sdev->ops = ops;
 370         init_rcu_head(&sdev->rcu);
 371
 372         if (!svm) {
 373                 svm = kzalloc(sizeof(*svm), GFP_KERNEL);
 374                 if (!svm) {
 375                         ret = -ENOMEM;
 376                         kfree(sdev);
 377                         goto out;
 378                 }
 379                 svm->iommu = iommu;
 380
 381                 if (pasid_max > iommu->pasid_max)
 382                         pasid_max = iommu->pasid_max;
 383
 384                 /* Do not use PASID 0 in caching mode (virtualised IOMMU) */
 385                 ret = idr_alloc(&iommu->pasid_idr, svm,
 386                                 !!cap_caching_mode(iommu->cap),
 387                                 pasid_max - 1, GFP_KERNEL);
 388                 if (ret < 0) {
 389                         kfree(svm);
 390                         goto out;
 391                 }
 392                 svm->pasid = ret;
 393                 svm->notifier.ops = &intel_mmuops;
 394                 svm->mm = mm;
 395                 svm->flags = flags;
 396                 INIT_LIST_HEAD_RCU(&svm->devs);
 397                 ret = -ENOMEM;
 398                 if (mm) {
 399                         ret = mmu_notifier_register(&svm->notifier, mm);
 400                         if (ret) {
 401                                 idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 402                                 kfree(svm);
 403                                 kfree(sdev);
 404                                 goto out;
 405                         }
 406                         iommu->pasid_table[svm->pasid].val = (u64)__pa(mm->pgd) | 1;
 407                 } else
 408                         iommu->pasid_table[svm->pasid].val = (u64)__pa(init_mm.pgd) | 1 | (1ULL << 11);
 409                 wmb();
 410                 /* In caching mode, we still have to flush with PASID 0 when
 411                  * a PASID table entry becomes present. Not entirely clear
 412                  * *why* that would be the case — surely we could just issue
 413                  * a flush with the PASID value that we've changed? The PASID
 414                  * is the index into the table, after all. It's not like domain
 415                  * IDs in the case of the equivalent context-entry change in
 416                  * caching mode. And for that matter it's not entirely clear why
 417                  * a VMM would be in the business of caching the PASID table
 418                  * anyway. Surely that can be left entirely to the guest? */
 419                 if (cap_caching_mode(iommu->cap))
 420                         intel_flush_pasid_dev(svm, sdev, 0);
 421         }
 422         list_add_rcu(&sdev->list, &svm->devs);
 423
 424  success:
 425         *pasid = svm->pasid;
 426         ret = 0;
 427  out:
 428         mutex_unlock(&pasid_mutex);
 429         if (mm)
 430                 mmput(mm);
 431         return ret;
 432 }
 433 EXPORT_SYMBOL_GPL(intel_svm_bind_mm);
 434
 435 int intel_svm_unbind_mm(struct device *dev, int pasid)
 436 {
 437         struct intel_svm_dev *sdev;
 438         struct intel_iommu *iommu;
 439         struct intel_svm *svm;
 440         int ret = -EINVAL;
 441
 442         mutex_lock(&pasid_mutex);
 443         iommu = intel_svm_device_to_iommu(dev);
 444         if (!iommu || !iommu->pasid_table)
 445                 goto out;
 446
 447         svm = idr_find(&iommu->pasid_idr, pasid);
 448         if (!svm)
 449                 goto out;
 450
 451         list_for_each_entry(sdev, &svm->devs, list) {
 452                 if (dev == sdev->dev) {
 453                         ret = 0;
 454                         sdev->users--;
 455                         if (!sdev->users) {
 456                                 list_del_rcu(&sdev->list);
 457                                 /* Flush the PASID cache and IOTLB for this device.
 458                                  * Note that we do depend on the hardware *not* using
 459                                  * the PASID any more. Just as we depend on other
 460                                  * devices never using PASIDs that they have no right
 461                                  * to use. We have a *shared* PASID table, because it's
 462                                  * large and has to be physically contiguous. So it's
 463                                  * hard to be as defensive as we might like. */
 464                                 intel_flush_pasid_dev(svm, sdev, svm->pasid);
 465                                 intel_flush_svm_range_dev(svm, sdev, 0, -1, 0, !svm->mm);
 466                                 kfree_rcu(sdev, rcu);
 467
 468                                 if (list_empty(&svm->devs)) {
 469
 470                                         idr_remove(&svm->iommu->pasid_idr, svm->pasid);
 471                                         if (svm->mm)
 472                                                 mmu_notifier_unregister(&svm->notifier, svm->mm);
 473
 474                                         /* We mandate that no page faults may be outstanding
 475                                          * for the PASID when intel_svm_unbind_mm() is called.
 476                                          * If that is not obeyed, subtle errors will happen.
 477                                          * Let's make them less subtle... */
 478                                         memset(svm, 0x6b, sizeof(*svm));
 479                                         kfree(svm);
 480                                 }
 481                         }
 482                         break;
 483                 }
 484         }
 485  out:
 486         mutex_unlock(&pasid_mutex);
 487
 488         return ret;
 489 }
 490 EXPORT_SYMBOL_GPL(intel_svm_unbind_mm);
 491
 492 int intel_svm_is_pasid_valid(struct device *dev, int pasid)
 493 {
 494         struct intel_iommu *iommu;
 495         struct intel_svm *svm;
 496         int ret = -EINVAL;
 497
 498         mutex_lock(&pasid_mutex);
 499         iommu = intel_svm_device_to_iommu(dev);
 500         if (!iommu || !iommu->pasid_table)
 501                 goto out;
 502
 503         svm = idr_find(&iommu->pasid_idr, pasid);
 504         if (!svm)
 505                 goto out;
 506
 507         /* init_mm is used in this case */
 508         if (!svm->mm)
 509                 ret = 1;
 510         else if (atomic_read(&svm->mm->mm_users) > 0)
 511                 ret = 1;
 512         else
 513                 ret = 0;
 514
 515  out:
 516         mutex_unlock(&pasid_mutex);
 517
 518         return ret;
 519 }
 520 EXPORT_SYMBOL_GPL(intel_svm_is_pasid_valid);
 521
 522 /* Page request queue descriptor */
 523 struct page_req_dsc {
 524         u64 srr:1;
 525         u64 bof:1;
 526         u64 pasid_present:1;
 527         u64 lpig:1;
 528         u64 pasid:20;
 529         u64 bus:8;
 530         u64 private:23;
 531         u64 prg_index:9;
 532         u64 rd_req:1;
 533         u64 wr_req:1;
 534         u64 exe_req:1;
 535         u64 priv_req:1;
 536         u64 devfn:8;
 537         u64 addr:52;
 538 };
 539
 540 #define PRQ_RING_MASK ((0x1000 << PRQ_ORDER) - 0x10)
 541
 542 static bool access_error(struct vm_area_struct *vma, struct page_req_dsc *req)
 543 {
 544         unsigned long requested = 0;
 545
 546         if (req->exe_req)
 547                 requested |= VM_EXEC;
 548
 549         if (req->rd_req)
 550                 requested |= VM_READ;
 551
 552         if (req->wr_req)
 553                 requested |= VM_WRITE;
 554
 555         return (requested & ~vma->vm_flags) != 0;
 556 }
 557
 558 static irqreturn_t prq_event_thread(int irq, void *d)
 559 {
 560         struct intel_iommu *iommu = d;
 561         struct intel_svm *svm = NULL;
 562         int head, tail, handled = 0;
 563
 564         /* Clear PPR bit before reading head/tail registers, to
 565          * ensure that we get a new interrupt if needed. */
 566         writel(DMA_PRS_PPR, iommu->reg + DMAR_PRS_REG);
 567
 568         tail = dmar_readq(iommu->reg + DMAR_PQT_REG) & PRQ_RING_MASK;
 569         head = dmar_readq(iommu->reg + DMAR_PQH_REG) & PRQ_RING_MASK;
 570         while (head != tail) {
 571                 struct intel_svm_dev *sdev;
 572                 struct vm_area_struct *vma;
 573                 struct page_req_dsc *req;
 574                 struct qi_desc resp;
 575                 int ret, result;
 576                 u64 address;
 577
 578                 handled = 1;
 579
 580                 req = &iommu->prq[head / sizeof(*req)];
 581
 582                 result = QI_RESP_FAILURE;
 583                 address = (u64)req->addr << VTD_PAGE_SHIFT;
 584                 if (!req->pasid_present) {
 585                         pr_err("%s: Page request without PASID: %08llx %08llx\n",
 586                                iommu->name, ((unsigned long long *)req)[0],
 587                                ((unsigned long long *)req)[1]);
 588                         goto bad_req;
 589                 }
 590
 591                 if (!svm || svm->pasid != req->pasid) {
 592                         rcu_read_lock();
 593                         svm = idr_find(&iommu->pasid_idr, req->pasid);
 594                         /* It *can't* go away, because the driver is not permitted
 595                          * to unbind the mm while any page faults are outstanding.
 596                          * So we only need RCU to protect the internal idr code. */
 597                         rcu_read_unlock();
 598
 599                         if (!svm) {
 600                                 pr_err("%s: Page request for invalid PASID %d: %08llx %08llx\n",
 601                                        iommu->name, req->pasid, ((unsigned long long *)req)[0],
 602                                        ((unsigned long long *)req)[1]);
 603                                 goto no_pasid;
 604                         }
 605                 }
 606
 607                 result = QI_RESP_INVALID;
 608                 /* Since we're using init_mm.pgd directly, we should never take
 609                  * any faults on kernel addresses. */
 610                 if (!svm->mm)
 611                         goto bad_req;
 612                 /* If the mm is already defunct, don't handle faults. */
 613                 if (!mmget_not_zero(svm->mm))
 614                         goto bad_req;
 615                 down_read(&svm->mm->mmap_sem);
 616                 vma = find_extend_vma(svm->mm, address);
 617                 if (!vma || address < vma->vm_start)
 618                         goto invalid;
 619
 620                 if (access_error(vma, req))
 621                         goto invalid;
 622
 623                 ret = handle_mm_fault(vma, address,
 624                                       req->wr_req ? FAULT_FLAG_WRITE : 0);
 625                 if (ret & VM_FAULT_ERROR)
 626                         goto invalid;
 627
 628                 result = QI_RESP_SUCCESS;
 629         invalid:
 630                 up_read(&svm->mm->mmap_sem);
 631                 mmput(svm->mm);
 632         bad_req:
 633                 /* Accounting for major/minor faults? */
 634                 rcu_read_lock();
 635                 list_for_each_entry_rcu(sdev, &svm->devs, list) {
 636                         if (sdev->sid == PCI_DEVID(req->bus, req->devfn))
 637                                 break;
 638                 }
 639                 /* Other devices can go away, but the drivers are not permitted
 640                  * to unbind while any page faults might be in flight. So it's
 641                  * OK to drop the 'lock' here now we have it. */
 642                 rcu_read_unlock();
 643
 644                 if (WARN_ON(&sdev->list == &svm->devs))
 645                         sdev = NULL;
 646
 647                 if (sdev && sdev->ops && sdev->ops->fault_cb) {
 648                         int rwxp = (req->rd_req << 3) | (req->wr_req << 2) |
 649                                 (req->exe_req << 1) | (req->priv_req);
 650                         sdev->ops->fault_cb(sdev->dev, req->pasid, req->addr, req->private, rwxp, result);
 651                 }
 652                 /* We get here in the error case where the PASID lookup failed,
 653                    and these can be NULL. Do not use them below this point! */
 654                 sdev = NULL;
 655                 svm = NULL;
 656         no_pasid:
 657                 if (req->lpig) {
 658                         /* Page Group Response */
 659                         resp.low = QI_PGRP_PASID(req->pasid) |
 660                                 QI_PGRP_DID((req->bus << 8) | req->devfn) |
 661                                 QI_PGRP_PASID_P(req->pasid_present) |
 662                                 QI_PGRP_RESP_TYPE;
 663                         resp.high = QI_PGRP_IDX(req->prg_index) |
 664                                 QI_PGRP_PRIV(req->private) | QI_PGRP_RESP_CODE(result);
 665
 666                         qi_submit_sync(&resp, iommu);
 667                 } else if (req->srr) {
 668                         /* Page Stream Response */
 669                         resp.low = QI_PSTRM_IDX(req->prg_index) |
 670                                 QI_PSTRM_PRIV(req->private) | QI_PSTRM_BUS(req->bus) |
 671                                 QI_PSTRM_PASID(req->pasid) | QI_PSTRM_RESP_TYPE;
 672                         resp.high = QI_PSTRM_ADDR(address) | QI_PSTRM_DEVFN(req->devfn) |
 673                                 QI_PSTRM_RESP_CODE(result);
 674
 675                         qi_submit_sync(&resp, iommu);
 676                 }
 677
 678                 head = (head + sizeof(*req)) & PRQ_RING_MASK;
 679         }
 680
 681         dmar_writeq(iommu->reg + DMAR_PQH_REG, tail);
 682
 683         return IRQ_RETVAL(handled);
 684 }